system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} | code for sm_80
Function : _Z18transposeCoalescedPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R3, R8, 0x5, RZ ; /* 0x0000000508037819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R4, R14, 0x5 ; /* 0x0000000e04007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R6, R16, R5, 0x5 ; /* 0x0000000510067211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R7, R6, R3, R0 ; /* 0x0000000306077224 */
/* 0x000fe200078e0200 */
/*00c0*/ SHF.L.U32 R0, R8, 0x8, RZ ; /* 0x0000000808007819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0202 */
/*00e0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0110*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0130*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0150*/ IMAD R19, R5, 0x21, R14 ; /* 0x0000002105137824 */
/* 0x000fe400078e020e */
/*0160*/ IMAD R18, R14, 0x21, R5 ; /* 0x000000210e127824 */
/* 0x000fe200078e0205 */
/*0170*/ LEA R14, R16, R14, 0x5 ; /* 0x0000000e100e7211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R4, R4, R5, 0x5 ; /* 0x0000000504047211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R3, R3, R4, R14 ; /* 0x0000000403037224 */
/* 0x000fc800078e020e */
/*01a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*01b0*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*01c0*/ STS [R19.X4], R6 ; /* 0x0000000613007388 */
/* 0x0041e80000004800 */
/*01d0*/ STS [R19.X4+0x420], R8 ; /* 0x0004200813007388 */
/* 0x0083e80000004800 */
/*01e0*/ STS [R19.X4+0x840], R10 ; /* 0x0008400a13007388 */
/* 0x010fe80000004800 */
/*01f0*/ STS [R19.X4+0xc60], R12 ; /* 0x000c600c13007388 */
/* 0x020fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R15, [R18.X4] ; /* 0x00000000120f7984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R17, [R18.X4+0x20] ; /* 0x0000200012117984 */
/* 0x000ee80000004800 */
/*0230*/ LDS R11, [R18.X4+0x40] ; /* 0x00004000120b7984 */
/* 0x000f280000004800 */
/*0240*/ LDS R13, [R18.X4+0x60] ; /* 0x00006000120d7984 */
/* 0x000f620000004800 */
/*0250*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x001fcc00078e0204 */
/*0260*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x002fe200078e0206 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x004fe8000c101904 */
/*0280*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x008fe8000c101904 */
/*0290*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x010fe8000c101904 */
/*02a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x020fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14transposeNaivePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R4, R11, 0x5, RZ ; /* 0x000000050b047819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R5, R5, R2, 0x5 ; /* 0x0000000205057211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R2, R5, R4, R0 ; /* 0x0000000405027224 */
/* 0x000fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0207 */
/*00d0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ SHF.L.U32 R11, R11, 0x8, RZ ; /* 0x000000080b0b7819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R4, R0, R4, R5 ; /* 0x0000000400047224 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0110*/ IMAD.WIDE R6, R11.reuse, 0x4, R2 ; /* 0x000000040b067825 */
/* 0x040fe200078e0202 */
/*0120*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101904 */
/*0130*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE R8, R11, 0x4, R6 ; /* 0x000000040b087825 */
/* 0x000fc600078e0206 */
/*0150*/ STG.E [R4.64+0x20], R15 ; /* 0x0000200f04007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R10, R11, 0x4, R8 ; /* 0x000000040b0a7825 */
/* 0x000fc600078e0208 */
/*0180*/ STG.E [R4.64+0x40], R17 ; /* 0x0000401104007986 */
/* 0x004fe8000c101904 */
/*0190*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64+0x60], R11 ; /* 0x0000600b04007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4copyPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0060*/ LEA R0, R0, R7, 0x5 ; /* 0x0000000700007211 */
/* 0x001fe200078e28ff */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fca00078e0203 */
/*0090*/ LEA R0, R0, R5, 0x5 ; /* 0x0000000500007211 */
/* 0x004fca00078e28ff */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R15, c[0x0][0xc] ; /* 0x00000300000f7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0207 */
/*00e0*/ SHF.L.U32 R15, R15, 0x8, RZ ; /* 0x000000080f0f7819 */
/* 0x000fca00000006ff */
/*00f0*/ IMAD.WIDE R6, R15.reuse, 0x4, R2 ; /* 0x000000040f067825 */
/* 0x040fe200078e0202 */
/*0100*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x004fe8000c101904 */
/*0110*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R10, R15.reuse, 0x4, R6 ; /* 0x000000040f0a7825 */
/* 0x040fe200078e0206 */
/*0140*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x004fe8000c101904 */
/*0150*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*0180*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x004fea000c101904 */
/*0190*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.WIDE R14, R15, 0x4, R2 ; /* 0x000000040f0e7825 */
/* 0x000fca00078e0202 */
/*01b0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x004fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} | .file "tmpxft_001558ff_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4copyPfPKfPfPKf
.type _Z26__device_stub__Z4copyPfPKfPfPKf, @function
_Z26__device_stub__Z4copyPfPKfPfPKf:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z26__device_stub__Z4copyPfPKfPfPKf, .-_Z26__device_stub__Z4copyPfPKfPfPKf
.globl _Z4copyPfPKf
.type _Z4copyPfPKf, @function
_Z4copyPfPKf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4copyPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4copyPfPKf, .-_Z4copyPfPKf
.globl _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.type _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, @function
_Z37__device_stub__Z14transposeNaivePfPKfPfPKf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14transposeNaivePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, .-_Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.globl _Z14transposeNaivePfPKf
.type _Z14transposeNaivePfPKf, @function
_Z14transposeNaivePfPKf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14transposeNaivePfPKf, .-_Z14transposeNaivePfPKf
.globl _Z40__device_stub__Z18transposeCoalescedPfS_PfS_
.type _Z40__device_stub__Z18transposeCoalescedPfS_PfS_, @function
_Z40__device_stub__Z18transposeCoalescedPfS_PfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18transposeCoalescedPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z18transposeCoalescedPfS_PfS_, .-_Z40__device_stub__Z18transposeCoalescedPfS_PfS_
.globl _Z18transposeCoalescedPfS_
.type _Z18transposeCoalescedPfS_, @function
_Z18transposeCoalescedPfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18transposeCoalescedPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18transposeCoalescedPfS_, .-_Z18transposeCoalescedPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeCoalescedPfS_"
.LC1:
.string "_Z14transposeNaivePfPKf"
.LC2:
.string "_Z4copyPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeCoalescedPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14transposeNaivePfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKf
.globl _Z4copyPfPKf
.p2align 8
.type _Z4copyPfPKf,@function
_Z4copyPfPKf:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s15, 5, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v0, v1, s5
s_mov_b32 s5, -8
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPfPKf, .Lfunc_end0-_Z4copyPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 8
.type _Z14transposeNaivePfPKf,@function
_Z14transposeNaivePfPKf:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s14, 5
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v2
v_mul_lo_u32 v3, s4, v3
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 5, v2
v_lshlrev_b32_e32 v3, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, s6
v_add3_u32 v0, v1, v3, s5
s_mov_b32 s5, -8
.p2align 6
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_add_nc_u32_e32 v3, s5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14transposeNaivePfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14transposeNaivePfPKf, .Lfunc_end1-_Z14transposeNaivePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeCoalescedPfS_
.globl _Z18transposeCoalescedPfS_
.p2align 8
.type _Z18transposeCoalescedPfS_,@function
_Z18transposeCoalescedPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v4, v2, 0x84, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 0x420, v4
s_cbranch_scc0 .LBB2_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_mad_u32_u24 v2, v3, 0x84, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB2_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB2_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeCoalescedPfS_
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18transposeCoalescedPfS_, .Lfunc_end2-_Z18transposeCoalescedPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14transposeNaivePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14transposeNaivePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeCoalescedPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeCoalescedPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
__global__ void copy(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
// row is (tile y + offset into tile j)*width of matrix + col x
odata[(y+j)*width + x] = idata[(y+j)*width + x];
}
}
__global__ void transposeNaive(float *odata, const float *idata)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[x*width + (y+j)] = idata[(y+j)*width + x];
}
}
__global__ void transposeCoalesced(float *odata, float *idata)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
tile[threadIdx.y+j][threadIdx.x] = idata[(y+j)*width + x];
}
__syncthreads();
// Now these are the offsets into the transposed tile
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS)
{
odata[(y+j)*width + x] = tile[threadIdx.x][threadIdx.y + j];
}
} | .text
.file "transpose.hip"
.globl _Z19__device_stub__copyPfPKf # -- Begin function _Z19__device_stub__copyPfPKf
.p2align 4, 0x90
.type _Z19__device_stub__copyPfPKf,@function
_Z19__device_stub__copyPfPKf: # @_Z19__device_stub__copyPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4copyPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPfPKf, .Lfunc_end0-_Z19__device_stub__copyPfPKf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__transposeNaivePfPKf # -- Begin function _Z29__device_stub__transposeNaivePfPKf
.p2align 4, 0x90
.type _Z29__device_stub__transposeNaivePfPKf,@function
_Z29__device_stub__transposeNaivePfPKf: # @_Z29__device_stub__transposeNaivePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14transposeNaivePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z29__device_stub__transposeNaivePfPKf, .Lfunc_end1-_Z29__device_stub__transposeNaivePfPKf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__transposeCoalescedPfS_ # -- Begin function _Z33__device_stub__transposeCoalescedPfS_
.p2align 4, 0x90
.type _Z33__device_stub__transposeCoalescedPfS_,@function
_Z33__device_stub__transposeCoalescedPfS_: # @_Z33__device_stub__transposeCoalescedPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18transposeCoalescedPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__transposeCoalescedPfS_, .Lfunc_end2-_Z33__device_stub__transposeCoalescedPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14transposeNaivePfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeCoalescedPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPfPKf,@object # @_Z4copyPfPKf
.section .rodata,"a",@progbits
.globl _Z4copyPfPKf
.p2align 3, 0x0
_Z4copyPfPKf:
.quad _Z19__device_stub__copyPfPKf
.size _Z4copyPfPKf, 8
.type _Z14transposeNaivePfPKf,@object # @_Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 3, 0x0
_Z14transposeNaivePfPKf:
.quad _Z29__device_stub__transposeNaivePfPKf
.size _Z14transposeNaivePfPKf, 8
.type _Z18transposeCoalescedPfS_,@object # @_Z18transposeCoalescedPfS_
.globl _Z18transposeCoalescedPfS_
.p2align 3, 0x0
_Z18transposeCoalescedPfS_:
.quad _Z33__device_stub__transposeCoalescedPfS_
.size _Z18transposeCoalescedPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPfPKf"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14transposeNaivePfPKf"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18transposeCoalescedPfS_"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPfPKf
.addrsig_sym _Z29__device_stub__transposeNaivePfPKf
.addrsig_sym _Z33__device_stub__transposeCoalescedPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPfPKf
.addrsig_sym _Z14transposeNaivePfPKf
.addrsig_sym _Z18transposeCoalescedPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18transposeCoalescedPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0xc] ; /* 0x0000030000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R3, R8, 0x5, RZ ; /* 0x0000000508037819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R4, R14, 0x5 ; /* 0x0000000e04007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R6, R16, R5, 0x5 ; /* 0x0000000510067211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R7, R6, R3, R0 ; /* 0x0000000306077224 */
/* 0x000fe200078e0200 */
/*00c0*/ SHF.L.U32 R0, R8, 0x8, RZ ; /* 0x0000000808007819 */
/* 0x000fc600000006ff */
/*00d0*/ IMAD.WIDE R6, R7, R2, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0202 */
/*00e0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe400078e0206 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0100*/ IMAD.WIDE R10, R0.reuse, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x040fe400078e0208 */
/*0110*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0120*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc400078e020a */
/*0130*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f28000c1e1900 */
/*0140*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0150*/ IMAD R19, R5, 0x21, R14 ; /* 0x0000002105137824 */
/* 0x000fe400078e020e */
/*0160*/ IMAD R18, R14, 0x21, R5 ; /* 0x000000210e127824 */
/* 0x000fe200078e0205 */
/*0170*/ LEA R14, R16, R14, 0x5 ; /* 0x0000000e100e7211 */
/* 0x000fe400078e28ff */
/*0180*/ LEA R4, R4, R5, 0x5 ; /* 0x0000000504047211 */
/* 0x000fca00078e28ff */
/*0190*/ IMAD R3, R3, R4, R14 ; /* 0x0000000403037224 */
/* 0x000fc800078e020e */
/*01a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*01b0*/ IMAD.WIDE R4, R0.reuse, 0x4, R2 ; /* 0x0000000400047825 */
/* 0x040fe200078e0202 */
/*01c0*/ STS [R19.X4], R6 ; /* 0x0000000613007388 */
/* 0x0041e80000004800 */
/*01d0*/ STS [R19.X4+0x420], R8 ; /* 0x0004200813007388 */
/* 0x0083e80000004800 */
/*01e0*/ STS [R19.X4+0x840], R10 ; /* 0x0008400a13007388 */
/* 0x010fe80000004800 */
/*01f0*/ STS [R19.X4+0xc60], R12 ; /* 0x000c600c13007388 */
/* 0x020fe80000004800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ LDS R15, [R18.X4] ; /* 0x00000000120f7984 */
/* 0x000ea80000004800 */
/*0220*/ LDS R17, [R18.X4+0x20] ; /* 0x0000200012117984 */
/* 0x000ee80000004800 */
/*0230*/ LDS R11, [R18.X4+0x40] ; /* 0x00004000120b7984 */
/* 0x000f280000004800 */
/*0240*/ LDS R13, [R18.X4+0x60] ; /* 0x00006000120d7984 */
/* 0x000f620000004800 */
/*0250*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x001fcc00078e0204 */
/*0260*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x002fe200078e0206 */
/*0270*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x004fe8000c101904 */
/*0280*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x008fe8000c101904 */
/*0290*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x010fe8000c101904 */
/*02a0*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x020fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14transposeNaivePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ SHF.L.U32 R4, R11, 0x5, RZ ; /* 0x000000050b047819 */
/* 0x000fc600000006ff */
/*0070*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x001fe400078e28ff */
/*00a0*/ LEA R5, R5, R2, 0x5 ; /* 0x0000000205057211 */
/* 0x002fca00078e28ff */
/*00b0*/ IMAD R2, R5, R4, R0 ; /* 0x0000000405027224 */
/* 0x000fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0207 */
/*00d0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ SHF.L.U32 R11, R11, 0x8, RZ ; /* 0x000000080b0b7819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R4, R0, R4, R5 ; /* 0x0000000400047224 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0110*/ IMAD.WIDE R6, R11.reuse, 0x4, R2 ; /* 0x000000040b067825 */
/* 0x040fe200078e0202 */
/*0120*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe8000c101904 */
/*0130*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE R8, R11, 0x4, R6 ; /* 0x000000040b087825 */
/* 0x000fc600078e0206 */
/*0150*/ STG.E [R4.64+0x20], R15 ; /* 0x0000200f04007986 */
/* 0x004fe8000c101904 */
/*0160*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.WIDE R10, R11, 0x4, R8 ; /* 0x000000040b0a7825 */
/* 0x000fc600078e0208 */
/*0180*/ STG.E [R4.64+0x40], R17 ; /* 0x0000401104007986 */
/* 0x004fe8000c101904 */
/*0190*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64+0x60], R11 ; /* 0x0000600b04007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4copyPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0060*/ LEA R0, R0, R7, 0x5 ; /* 0x0000000700007211 */
/* 0x001fe200078e28ff */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc800000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fca00078e0203 */
/*0090*/ LEA R0, R0, R5, 0x5 ; /* 0x0000000500007211 */
/* 0x004fca00078e28ff */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*00b0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R15, c[0x0][0xc] ; /* 0x00000300000f7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0207 */
/*00e0*/ SHF.L.U32 R15, R15, 0x8, RZ ; /* 0x000000080f0f7819 */
/* 0x000fca00000006ff */
/*00f0*/ IMAD.WIDE R6, R15.reuse, 0x4, R2 ; /* 0x000000040f067825 */
/* 0x040fe200078e0202 */
/*0100*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x004fe8000c101904 */
/*0110*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x000fc800078e0204 */
/*0130*/ IMAD.WIDE R10, R15.reuse, 0x4, R6 ; /* 0x000000040f0a7825 */
/* 0x040fe200078e0206 */
/*0140*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x004fe8000c101904 */
/*0150*/ LDG.E R21, [R10.64] ; /* 0x000000040a157981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IMAD.WIDE R2, R15, 0x4, R8 ; /* 0x000000040f027825 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R12, R15.reuse, 0x4, R10 ; /* 0x000000040f0c7825 */
/* 0x040fe200078e020a */
/*0180*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x004fea000c101904 */
/*0190*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.WIDE R14, R15, 0x4, R2 ; /* 0x000000040f0e7825 */
/* 0x000fca00078e0202 */
/*01b0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x004fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKf
.globl _Z4copyPfPKf
.p2align 8
.type _Z4copyPfPKf,@function
_Z4copyPfPKf:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s5, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s15, 5, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 5, v1
v_add3_u32 v0, v0, v1, s5
s_mov_b32 s5, -8
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPfPKf, .Lfunc_end0-_Z4copyPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 8
.type _Z14transposeNaivePfPKf,@function
_Z14transposeNaivePfPKf:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s5, s14, 5
s_lshl_b32 s6, s15, 5
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s6, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v2
v_mul_lo_u32 v3, s4, v3
s_lshl_b32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 5, v2
v_lshlrev_b32_e32 v3, 5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, s6
v_add3_u32 v0, v1, v3, s5
s_mov_b32 s5, -8
.p2align 6
.LBB1_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, 8
s_cmp_gt_u32 s5, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_add_nc_u32_e32 v3, s5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_cbranch_scc0 .LBB1_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14transposeNaivePfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14transposeNaivePfPKf, .Lfunc_end1-_Z14transposeNaivePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18transposeCoalescedPfS_
.globl _Z18transposeCoalescedPfS_
.p2align 8
.type _Z18transposeCoalescedPfS_,@function
_Z18transposeCoalescedPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s5, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s6, s14, 5
s_mov_b32 s8, -8
v_add_nc_u32_e32 v1, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v3
v_mad_u32_u24 v4, v2, 0x84, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v1
s_lshl_b32 s7, s4, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s6
.LBB2_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, 8
s_cmp_gt_u32 s8, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 0x420, v4
s_cbranch_scc0 .LBB2_1
v_add_nc_u32_e32 v0, s6, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s2, s4, 8
s_mov_b32 s3, -8
v_mul_lo_u32 v0, s4, v0
s_waitcnt lgkmcnt(0)
v_mad_u32_u24 v2, v3, 0x84, v1
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s5
.LBB2_3:
ds_load_b32 v5, v2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, 32, v2
s_add_i32 s3, s3, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s3, 23
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_cbranch_scc0 .LBB2_3
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeCoalescedPfS_
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18transposeCoalescedPfS_, .Lfunc_end2-_Z18transposeCoalescedPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14transposeNaivePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14transposeNaivePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeCoalescedPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeCoalescedPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001558ff_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4copyPfPKfPfPKf
.type _Z26__device_stub__Z4copyPfPKfPfPKf, @function
_Z26__device_stub__Z4copyPfPKfPfPKf:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z26__device_stub__Z4copyPfPKfPfPKf, .-_Z26__device_stub__Z4copyPfPKfPfPKf
.globl _Z4copyPfPKf
.type _Z4copyPfPKf, @function
_Z4copyPfPKf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4copyPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4copyPfPKf, .-_Z4copyPfPKf
.globl _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.type _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, @function
_Z37__device_stub__Z14transposeNaivePfPKfPfPKf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14transposeNaivePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z14transposeNaivePfPKfPfPKf, .-_Z37__device_stub__Z14transposeNaivePfPKfPfPKf
.globl _Z14transposeNaivePfPKf
.type _Z14transposeNaivePfPKf, @function
_Z14transposeNaivePfPKf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14transposeNaivePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14transposeNaivePfPKf, .-_Z14transposeNaivePfPKf
.globl _Z40__device_stub__Z18transposeCoalescedPfS_PfS_
.type _Z40__device_stub__Z18transposeCoalescedPfS_PfS_, @function
_Z40__device_stub__Z18transposeCoalescedPfS_PfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18transposeCoalescedPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z18transposeCoalescedPfS_PfS_, .-_Z40__device_stub__Z18transposeCoalescedPfS_PfS_
.globl _Z18transposeCoalescedPfS_
.type _Z18transposeCoalescedPfS_, @function
_Z18transposeCoalescedPfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18transposeCoalescedPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18transposeCoalescedPfS_, .-_Z18transposeCoalescedPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeCoalescedPfS_"
.LC1:
.string "_Z14transposeNaivePfPKf"
.LC2:
.string "_Z4copyPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeCoalescedPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14transposeNaivePfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
.globl _Z19__device_stub__copyPfPKf # -- Begin function _Z19__device_stub__copyPfPKf
.p2align 4, 0x90
.type _Z19__device_stub__copyPfPKf,@function
_Z19__device_stub__copyPfPKf: # @_Z19__device_stub__copyPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4copyPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPfPKf, .Lfunc_end0-_Z19__device_stub__copyPfPKf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__transposeNaivePfPKf # -- Begin function _Z29__device_stub__transposeNaivePfPKf
.p2align 4, 0x90
.type _Z29__device_stub__transposeNaivePfPKf,@function
_Z29__device_stub__transposeNaivePfPKf: # @_Z29__device_stub__transposeNaivePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14transposeNaivePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z29__device_stub__transposeNaivePfPKf, .Lfunc_end1-_Z29__device_stub__transposeNaivePfPKf
.cfi_endproc
# -- End function
.globl _Z33__device_stub__transposeCoalescedPfS_ # -- Begin function _Z33__device_stub__transposeCoalescedPfS_
.p2align 4, 0x90
.type _Z33__device_stub__transposeCoalescedPfS_,@function
_Z33__device_stub__transposeCoalescedPfS_: # @_Z33__device_stub__transposeCoalescedPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18transposeCoalescedPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z33__device_stub__transposeCoalescedPfS_, .Lfunc_end2-_Z33__device_stub__transposeCoalescedPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14transposeNaivePfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeCoalescedPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPfPKf,@object # @_Z4copyPfPKf
.section .rodata,"a",@progbits
.globl _Z4copyPfPKf
.p2align 3, 0x0
_Z4copyPfPKf:
.quad _Z19__device_stub__copyPfPKf
.size _Z4copyPfPKf, 8
.type _Z14transposeNaivePfPKf,@object # @_Z14transposeNaivePfPKf
.globl _Z14transposeNaivePfPKf
.p2align 3, 0x0
_Z14transposeNaivePfPKf:
.quad _Z29__device_stub__transposeNaivePfPKf
.size _Z14transposeNaivePfPKf, 8
.type _Z18transposeCoalescedPfS_,@object # @_Z18transposeCoalescedPfS_
.globl _Z18transposeCoalescedPfS_
.p2align 3, 0x0
_Z18transposeCoalescedPfS_:
.quad _Z33__device_stub__transposeCoalescedPfS_
.size _Z18transposeCoalescedPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPfPKf"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14transposeNaivePfPKf"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18transposeCoalescedPfS_"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPfPKf
.addrsig_sym _Z29__device_stub__transposeNaivePfPKf
.addrsig_sym _Z33__device_stub__transposeCoalescedPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPfPKf
.addrsig_sym _Z14transposeNaivePfPKf
.addrsig_sym _Z18transposeCoalescedPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdio.h>
__global__ static void sayHello()
{
int i = blockIdx.x*blockDim.x+threadIdx.x;
printf("Hello from thread %d!\n", i);
}
int main()
{
int grid_size;
int tpb;
puts("Please enter the grid size: ");
scanf("%d", &grid_size);
puts("\nPlease enter the threads per block: ");
scanf("%d", &tpb);
puts("\n");
sayHello<<<grid_size,tpb>>>();
cudaError_t cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | code for sm_80
Function : _Z8sayHellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdio.h>
__global__ static void sayHello()
{
int i = blockIdx.x*blockDim.x+threadIdx.x;
printf("Hello from thread %d!\n", i);
}
int main()
{
int grid_size;
int tpb;
puts("Please enter the grid size: ");
scanf("%d", &grid_size);
puts("\nPlease enter the threads per block: ");
scanf("%d", &tpb);
puts("\n");
sayHello<<<grid_size,tpb>>>();
cudaError_t cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | .file "tmpxft_0012a783_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL8sayHellov, @function
_ZL8sayHellov:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _ZL8sayHellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _ZL8sayHellov, .-_ZL8sayHellov
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Please enter the grid size: "
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nPlease enter the threads per block: "
.section .rodata.str1.1
.LC3:
.string "\n"
.LC4:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rdi
call puts@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rdi
call puts@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC3(%rip), %rdi
call puts@PLT
movl 12(%rsp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl 8(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L10:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L16
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L17
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _ZL8sayHellov
jmp .L10
.L16:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L9
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8sayHellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8sayHellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdio.h>
__global__ static void sayHello()
{
int i = blockIdx.x*blockDim.x+threadIdx.x;
printf("Hello from thread %d!\n", i);
}
int main()
{
int grid_size;
int tpb;
puts("Please enter the grid size: ");
scanf("%d", &grid_size);
puts("\nPlease enter the threads per block: ");
scanf("%d", &tpb);
puts("\n");
sayHello<<<grid_size,tpb>>>();
cudaError_t cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ static void sayHello()
{
int i = blockIdx.x*blockDim.x+threadIdx.x;
printf("Hello from thread %d!\n", i);
}
int main()
{
int grid_size;
int tpb;
puts("Please enter the grid size: ");
scanf("%d", &grid_size);
puts("\nPlease enter the threads per block: ");
scanf("%d", &tpb);
puts("\n");
sayHello<<<grid_size,tpb>>>();
hipError_t cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ static void sayHello()
{
int i = blockIdx.x*blockDim.x+threadIdx.x;
printf("Hello from thread %d!\n", i);
}
int main()
{
int grid_size;
int tpb;
puts("Please enter the grid size: ");
scanf("%d", &grid_size);
puts("\nPlease enter the threads per block: ");
scanf("%d", &tpb);
puts("\n");
sayHello<<<grid_size,tpb>>>();
hipError_t cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
} | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $.L.str, %edi
callq puts
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
callq puts
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %edi
callq puts
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL8sayHellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceReset
testl %eax, %eax
jne .LBB0_3
.LBB0_4:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB0_4
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL23__device_stub__sayHellov
.type _ZL23__device_stub__sayHellov,@function
_ZL23__device_stub__sayHellov: # @_ZL23__device_stub__sayHellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_ZL8sayHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _ZL23__device_stub__sayHellov, .Lfunc_end1-_ZL23__device_stub__sayHellov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL8sayHellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Please enter the grid size: "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nPlease enter the threads per block: "
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type _ZL8sayHellov,@object # @_ZL8sayHellov
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL8sayHellov:
.quad _ZL23__device_stub__sayHellov
.size _ZL8sayHellov, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "hipDeviceReset failed!"
.size .L.str.4, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL8sayHellov"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL23__device_stub__sayHellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL8sayHellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a783_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL8sayHellov, @function
_ZL8sayHellov:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _ZL8sayHellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _ZL8sayHellov, .-_ZL8sayHellov
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Please enter the grid size: "
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nPlease enter the threads per block: "
.section .rodata.str1.1
.LC3:
.string "\n"
.LC4:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rdi
call puts@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rdi
call puts@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC3(%rip), %rdi
call puts@PLT
movl 12(%rsp), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl 8(%rsp), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L10:
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L16
.L9:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L17
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _ZL8sayHellov
jmp .L10
.L16:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L9
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z8sayHellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8sayHellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $.L.str, %edi
callq puts
xorl %ebx, %ebx
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.2, %edi
callq puts
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.3, %edi
callq puts
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL8sayHellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceReset
testl %eax, %eax
jne .LBB0_3
.LBB0_4:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %ebx
jmp .LBB0_4
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL23__device_stub__sayHellov
.type _ZL23__device_stub__sayHellov,@function
_ZL23__device_stub__sayHellov: # @_ZL23__device_stub__sayHellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_ZL8sayHellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _ZL23__device_stub__sayHellov, .Lfunc_end1-_ZL23__device_stub__sayHellov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL8sayHellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Please enter the grid size: "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nPlease enter the threads per block: "
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type _ZL8sayHellov,@object # @_ZL8sayHellov
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL8sayHellov:
.quad _ZL23__device_stub__sayHellov
.size _ZL8sayHellov, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "hipDeviceReset failed!"
.size .L.str.4, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL8sayHellov"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL23__device_stub__sayHellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL8sayHellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
cudaError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
cudaError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_0018321e_00000000-6_task1-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "addKernel launch failed: %s\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L23
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L23:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L19
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.section .rodata.str1.1
.LC4:
.string "addWithCuda failed!"
.LC5:
.string "%d + %d = %d\t"
.LC6:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32792
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3256, %rsp
.cfi_def_cfa_offset 36048
movq %fs:40, %rax
movq %rax, 36008(%rsp)
xorl %eax, %eax
leaq 24000(%rsp), %rdi
movl $12000, %edx
movl $0, %esi
call memset@PLT
movl $0, %ebx
.L33:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 12000(%rsp,%rbx)
addq $4, %rbx
cmpq $12000, %rbx
jne .L33
leaq 12000(%rsp), %rdx
movq %rsp, %rsi
leaq 24000(%rsp), %rdi
movl $3000, %ecx
call _Z11addWithCudaPiPKiS1_j
movl $0, %ebx
leaq .LC5(%rip), %rbp
testl %eax, %eax
jne .L43
.L34:
movl 12000(%rsp,%rbx), %ecx
movl (%rsp,%rbx), %edx
movl 24000(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $12000, %rbx
jne .L34
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L44
.L32:
movq 36008(%rsp), %rdx
subq %fs:40, %rdx
jne .L45
addq $36024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L44:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
}
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
cudaError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
hipError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
hipError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b){
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main(){
const int arraySize = 3000;
int i = 0;
int a[arraySize];
int b[arraySize];
int c[arraySize] = { 0 };
for(i = 0; i < arraySize; i++){
a[i] = (int)(rand()% 100);
b[i] = (int)(rand()% 100);
}
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
for(i = 0;i < arraySize; i++){
printf("%d + %d = %d\t",a[i],b[i],c[i]);
}
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
}
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size){
hipError_t cudaStatus;
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "task1-2.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $36000, %rsp # imm = 0x8CA0
.cfi_def_cfa_offset 36016
.cfi_offset %rbx, -16
movq %rsp, %rdi
xorl %ebx, %ebx
movl $12000, %edx # imm = 0x2EE0
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 24000(%rsp,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 12000(%rsp,%rbx,4)
incq %rbx
cmpq $3000, %rbx # imm = 0xBB8
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
leaq 24000(%rsp), %rsi
leaq 12000(%rsp), %rdx
movl $3000, %ecx # imm = 0xBB8
callq _Z11addWithCudaPiPKiS1_j
testl %eax, %eax
jne .LBB1_9
# %bb.3: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 24000(%rsp,%rbx,4), %esi
movl 12000(%rsp,%rbx,4), %edx
movl (%rsp,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3000, %rbx # imm = 0xBB8
jne .LBB1_4
# %bb.5:
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_6
.LBB1_8:
addq $36000, %rsp # imm = 0x8CA0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 36016
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
jmp .LBB1_7
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $22, %esi
.LBB1_7:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_8
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_j # -- Begin function _Z11addWithCudaPiPKiS1_j
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_j,@function
_Z11addWithCudaPiPKiS1_j: # @_Z11addWithCudaPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_17
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_18
# %bb.9:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_16
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_15
.LBB2_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB2_13
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB2_13:
movl $17, %esi
.LBB2_14:
movl $1, %edx
.LBB2_15:
callq fwrite@PLT
.LBB2_16:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $63, %esi
jmp .LBB2_14
.LBB2_18:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.Lfunc_end2:
.size _Z11addWithCudaPiPKiS1_j, .Lfunc_end2-_Z11addWithCudaPiPKiS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda failed!"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d + %d = %d\t"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset failed!"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.3, 64
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "addKernel launch failed: %s\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018321e_00000000-6_task1-2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "addKernel launch failed: %s\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L23
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L24
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L23:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L19
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.section .rodata.str1.1
.LC4:
.string "addWithCuda failed!"
.LC5:
.string "%d + %d = %d\t"
.LC6:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32792
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3256, %rsp
.cfi_def_cfa_offset 36048
movq %fs:40, %rax
movq %rax, 36008(%rsp)
xorl %eax, %eax
leaq 24000(%rsp), %rdi
movl $12000, %edx
movl $0, %esi
call memset@PLT
movl $0, %ebx
.L33:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 12000(%rsp,%rbx)
addq $4, %rbx
cmpq $12000, %rbx
jne .L33
leaq 12000(%rsp), %rdx
movq %rsp, %rsi
leaq 24000(%rsp), %rdi
movl $3000, %ecx
call _Z11addWithCudaPiPKiS1_j
movl $0, %ebx
leaq .LC5(%rip), %rbp
testl %eax, %eax
jne .L43
.L34:
movl 12000(%rsp,%rbx), %ecx
movl (%rsp,%rbx), %edx
movl 24000(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $12000, %rbx
jne .L34
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L44
.L32:
movq 36008(%rsp), %rdx
subq %fs:40, %rdx
jne .L45
addq $36024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L44:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task1-2.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $36000, %rsp # imm = 0x8CA0
.cfi_def_cfa_offset 36016
.cfi_offset %rbx, -16
movq %rsp, %rdi
xorl %ebx, %ebx
movl $12000, %edx # imm = 0x2EE0
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 24000(%rsp,%rbx,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, 12000(%rsp,%rbx,4)
incq %rbx
cmpq $3000, %rbx # imm = 0xBB8
jne .LBB1_1
# %bb.2:
movq %rsp, %rdi
leaq 24000(%rsp), %rsi
leaq 12000(%rsp), %rdx
movl $3000, %ecx # imm = 0xBB8
callq _Z11addWithCudaPiPKiS1_j
testl %eax, %eax
jne .LBB1_9
# %bb.3: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 24000(%rsp,%rbx,4), %esi
movl 12000(%rsp,%rbx,4), %edx
movl (%rsp,%rbx,4), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3000, %rbx # imm = 0xBB8
jne .LBB1_4
# %bb.5:
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB1_6
.LBB1_8:
addq $36000, %rsp # imm = 0x8CA0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 36016
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $20, %esi
jmp .LBB1_7
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $22, %esi
.LBB1_7:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_8
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_j # -- Begin function _Z11addWithCudaPiPKiS1_j
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_j,@function
_Z11addWithCudaPiPKiS1_j: # @_Z11addWithCudaPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_17
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_18
# %bb.9:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_16
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_15
.LBB2_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
jmp .LBB2_13
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
.LBB2_13:
movl $17, %esi
.LBB2_14:
movl $1, %edx
.LBB2_15:
callq fwrite@PLT
.LBB2_16:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $63, %esi
jmp .LBB2_14
.LBB2_18:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.Lfunc_end2:
.size _Z11addWithCudaPiPKiS1_j, .Lfunc_end2-_Z11addWithCudaPiPKiS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda failed!"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d + %d = %d\t"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset failed!"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.3, 64
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc failed!"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy failed!"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "addKernel launch failed: %s\n"
.size .L.str.6, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
cudaMalloc((void**) &gpu_input, SIZE);
cudaMalloc((void**) &gpu_output, SIZE);
cudaMemset(gpu_output, 0, SIZE);
cudaMemset(gpu_input, 0, SIZE);
/* End preprocessing */
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output,
(void*)gpu_output,
SIZE,
cudaMemcpyDeviceToHost);
/* End copy array */
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree((void**) &gpu_input);
cudaFree((void**) &gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | code for sm_80
Function : _Z11compute_gpuPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e640000002200 */
/*0040*/ LEA.HI R2, R0, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0000027a11 */
/* 0x000fc800078f08ff */
/*0050*/ SHF.R.S32.HI R4, RZ, 0x1, R2 ; /* 0x00000001ff047819 */
/* 0x000fc80000011402 */
/*0060*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe40007ffe0ff */
/*0070*/ IADD3 R2, R17, 0x1, RZ ; /* 0x0000000111027810 */
/* 0x001fc80007ffe0ff */
/*0080*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f05270 */
/*0090*/ IADD3 R3, R16, 0x1, RZ ; /* 0x0000000110037810 */
/* 0x002fd60007ffe0ff */
/*00a0*/ @P0 BRA 0xe0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f05270 */
/*00c0*/ ISETP.EQ.OR P0, PT, R3, R2, !P0 ; /* 0x000000020300720c */
/* 0x000fda0004702670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fe20003f05270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0100*/ @P0 BRA 0x140 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fc80003f05270 */
/*0120*/ ISETP.EQ.OR P0, PT, R3, R2, !P0 ; /* 0x000000020300720c */
/* 0x000fda0004702670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff177424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD R22, R17, c[0x0][0x170], R16 ; /* 0x00005c0011167a24 */
/* 0x000fc800078e0210 */
/*0160*/ IMAD.WIDE R22, R22, R23, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0217 */
/*0170*/ LDG.E.64 R20, [R22.64+0x8] ; /* 0x0000080416147981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ IMAD.WIDE R24, R0, 0x8, R22 ; /* 0x0000000800187825 */
/* 0x000fc600078e0216 */
/*01a0*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R14, [R24.64+0x8] ; /* 0x00000804180e7981 */
/* 0x000f62000c1e1b00 */
/*01d0*/ IMAD.WIDE R26, R0, 0x8, R24 ; /* 0x00000008001a7825 */
/* 0x000fc600078e0218 */
/*01e0*/ LDG.E.64 R10, [R24.64+0x10] ; /* 0x00001004180a7981 */
/* 0x000f68000c1e1b00 */
/*01f0*/ LDG.E.64 R6, [R26.64] ; /* 0x000000041a067981 */
/* 0x000f68000c1e1b00 */
/*0200*/ LDG.E.64 R4, [R26.64+0x8] ; /* 0x000008041a047981 */
/* 0x000f68000c1e1b00 */
/*0210*/ LDG.E.64 R2, [R26.64+0x10] ; /* 0x000010041a027981 */
/* 0x000f62000c1e1b00 */
/*0220*/ IMAD R17, R17, R0, c[0x0][0x170] ; /* 0x00005c0011117624 */
/* 0x000fe200078e0200 */
/*0230*/ BSSY B0, 0x420 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*0240*/ IMAD.IADD R16, R17, 0x1, R16 ; /* 0x0000000111107824 */
/* 0x000fe200078e0210 */
/*0250*/ DADD R20, R20, R18 ; /* 0x0000000014147229 */
/* 0x0040c40000000012 */
/*0260*/ MUFU.RCP64H R19, 9 ; /* 0x4022000000137908 */
/* 0x001e220000001800 */
/*0270*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc600078e00ff */
/*0280*/ DADD R20, R20, R12 ; /* 0x0000000014147229 */
/* 0x008324000000000c */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x002fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40220000 ; /* 0x40220000ff0d7424 */
/* 0x000fe400078e00ff */
/*02b0*/ DADD R8, R20, R8 ; /* 0x0000000014087229 */
/* 0x010f480000000008 */
/*02c0*/ DFMA R20, R18, -R12, 1 ; /* 0x3ff000001214742b */
/* 0x001e08000000080c */
/*02d0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e48000000000e */
/*02e0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*02f0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x002e48000000000a */
/*0300*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e080000000012 */
/*0310*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x002e480000000006 */
/*0320*/ DFMA R12, R20, -R12, 1 ; /* 0x3ff00000140c742b */
/* 0x001e08000000080c */
/*0330*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e480000000004 */
/*0340*/ DFMA R12, R20, R12, R20 ; /* 0x0000000c140c722b */
/* 0x001fc80000000014 */
/*0350*/ DADD R4, R4, R2 ; /* 0x0000000004047229 */
/* 0x002e0c0000000002 */
/*0360*/ DMUL R2, R4, R12 ; /* 0x0000000c04027228 */
/* 0x001e080000000000 */
/*0370*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe40003f2e200 */
/*0380*/ DFMA R6, R2, -9, R4 ; /* 0xc02200000206782b */
/* 0x001e0c0000000004 */
/*0390*/ DFMA R2, R12, R6, R2 ; /* 0x000000060c02722b */
/* 0x001e140000000002 */
/*03a0*/ FFMA R6, RZ, 2.53125, R3 ; /* 0x40220000ff067823 */
/* 0x001fca0000000003 */
/*03b0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*03c0*/ @P0 BRA P1, 0x410 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03d0*/ MOV R0, 0x3f0 ; /* 0x000003f000007802 */
/* 0x000fe40000000f00 */
/*03e0*/ CALL.REL.NOINC 0x460 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0400*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*0440*/ STG.E.64 [R16.64+0x8], R2 ; /* 0x0000080210007986 */
/* 0x000fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3ff20000 ; /* 0x3ff20000ff037424 */
/* 0x000fe200078e00ff */
/*0470*/ FSETP.GEU.AND P1, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f2e200 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0490*/ LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005067812 */
/* 0x000fe200078ec0ff */
/*04a0*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x000e220000001800 */
/*04b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*04c0*/ BSSY B1, 0x920 ; /* 0x0000045000017945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff077424 */
/* 0x000fe200078e00ff */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, 0x40200000, PT ; /* 0x402000000600780c */
/* 0x000fe20003f06070 */
/*04f0*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x000fc400078e0006 */
/*0500*/ IMAD.MOV.U32 R18, RZ, RZ, 0x40200000 ; /* 0x40200000ff127424 */
/* 0x000fe200078e00ff */
/*0510*/ SEL R7, R7, 0x63400000, !P0 ; /* 0x6340000007077807 */
/* 0x000fc80004000000 */
/*0520*/ @!P1 LOP3.LUT R14, R7, 0x80000000, R5, 0xf8, !PT ; /* 0x80000000070e9812 */
/* 0x000fe400078ef805 */
/*0530*/ IADD3 R20, R18, -0x1, RZ ; /* 0xffffffff12147810 */
/* 0x000fe20007ffe0ff */
/*0540*/ DFMA R10, R8, -R2, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000802 */
/*0550*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0560*/ DFMA R12, R8, R10, R8 ; /* 0x0000000a080c722b */
/* 0x0010640000000008 */
/*0570*/ LOP3.LUT R9, R7, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff07097812 */
/* 0x001fe200078ef805 */
/*0580*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0590*/ @!P1 LOP3.LUT R11, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0b9812 */
/* 0x000fe200078efcff */
/*05a0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e00ff */
/*05b0*/ DFMA R14, R12, -R2, 1 ; /* 0x3ff000000c0e742b */
/* 0x002e0a0000000802 */
/*05c0*/ @!P1 DFMA R8, R8, 2, -R10 ; /* 0x400000000808982b */
/* 0x000e48000000080a */
/*05d0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e0c000000000c */
/*05e0*/ @!P1 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009119812 */
/* 0x002fe200078ec0ff */
/*05f0*/ DMUL R10, R14, R8 ; /* 0x000000080e0a7228 */
/* 0x001e060000000000 */
/*0600*/ IADD3 R19, R17, -0x1, RZ ; /* 0xffffffff11137810 */
/* 0x000fc60007ffe0ff */
/*0610*/ DFMA R12, R10, -R2, R8 ; /* 0x800000020a0c722b */
/* 0x001e220000000008 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R19, 0x7feffffe, PT ; /* 0x7feffffe1300780c */
/* 0x000fc80003f04070 */
/*0630*/ ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; /* 0x7feffffe1400780c */
/* 0x000fe20000704470 */
/*0640*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x001058000000000a */
/*0650*/ @P0 BRA 0x800 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R6, R6, -0x40200000, RZ ; /* 0xbfe0000006067810 */
/* 0x003fe20007ffe0ff */
/*0670*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0680*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0690*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*06a0*/ IMAD.IADD R12, R6, 0x1, -R7 ; /* 0x00000001060c7824 */
/* 0x000fca00078e0a07 */
/*06b0*/ IADD3 R5, R12, 0x7fe00000, RZ ; /* 0x7fe000000c057810 */
/* 0x000fcc0007ffe0ff */
/*06c0*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x000e140000000000 */
/*06d0*/ FSETP.GTU.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x001fda0003f0c200 */
/*06e0*/ @P0 BRA 0x910 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*06f0*/ DFMA R2, R10, -R2, R8 ; /* 0x800000020a02722b */
/* 0x000e220000000008 */
/*0700*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0710*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0720*/ LOP3.LUT R2, R3, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000003027812 */
/* 0x000fc800078e3cff */
/*0730*/ LOP3.LUT R9, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002097812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R5, R9, R5, RZ, 0xfc, !PT ; /* 0x0000000509057212 */
/* 0x000fc600078efcff */
/*0750*/ @!P0 BRA 0x910 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV R3, RZ, RZ, -R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0c */
/*0770*/ DMUL.RP R4, R10, R4 ; /* 0x000000040a047228 */
/* 0x000e220000008000 */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0790*/ DFMA R2, R6, -R2, R10 ; /* 0x800000020602722b */
/* 0x000e46000000000a */
/*07a0*/ LOP3.LUT R9, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905097212 */
/* 0x001fc600078e3cff */
/*07b0*/ IADD3 R2, -R12, -0x43300000, RZ ; /* 0xbcd000000c027810 */
/* 0x002fc80007ffe1ff */
/*07c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*07d0*/ FSEL R6, R4, R6, !P0 ; /* 0x0000000604067208 */
/* 0x000fe40004000000 */
/*07e0*/ FSEL R7, R9, R7, !P0 ; /* 0x0000000709077208 */
/* 0x000fe20004000000 */
/*07f0*/ BRA 0x910 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0800*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x003e1c0003f08000 */
/*0810*/ @P0 BRA 0x8f0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R17, R18, PT ; /* 0x000000121100720c */
/* 0x000fe20003f05270 */
/*0830*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff077424 */
/* 0x000fd400078e00ff */
/*0850*/ @!P0 BRA 0x910 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0860*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0870*/ LOP3.LUT R4, R5, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000005047812 */
/* 0x000fe400078e3cff */
/*0880*/ ISETP.EQ.OR P0, PT, R18, RZ, !P0 ; /* 0x000000ff1200720c */
/* 0x000fe40004702670 */
/*0890*/ LOP3.LUT R7, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004077812 */
/* 0x000fd600078ec0ff */
/*08a0*/ @P0 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000007020812 */
/* 0x000fe200078efcff */
/*08b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe400078e00ff */
/*08c0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*08d0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0002 */
/*08e0*/ BRA 0x910 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe200078efcff */
/*0900*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0910*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0920*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0930*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0940*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff6b002007950 */
/* 0x000fea0003c3ffff */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8init_gpuPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fe20000000f00 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 2.279296875, 2 ; /* 0x408f4000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ LEA.HI R0, R0, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0000007a11 */
/* 0x000fe200078f08ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*0080*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x000fca0007ffe0ff */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c0003067a24 */
/* 0x100fe400078e0200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R0 ; /* 0x00005c0000007a24 */
/* 0x000fe400078e0200 */
/*00b0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x0c0fe200078e0207 */
/*00d0*/ STG.E.64 [R2.64+-0x8], R10 ; /* 0xfffff80a02007986 */
/* 0x000fe6000c101b04 */
/*00e0*/ IMAD.WIDE R8, R0, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x080fe200078e0207 */
/*00f0*/ STG.E.64 [R4.64+-0x8], R10 ; /* 0xfffff80a04007986 */
/* 0x000fe6000c101b04 */
/*0100*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0110*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe8000c101b04 */
/*0120*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe8000c101b04 */
/*0130*/ STG.E.64 [R6.64+-0x8], R10 ; /* 0xfffff80a06007986 */
/* 0x000fe8000c101b04 */
/*0140*/ STG.E.64 [R8.64+-0x8], R10 ; /* 0xfffff80a08007986 */
/* 0x000fe8000c101b04 */
/*0150*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x000fe8000c101b04 */
/*0160*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
cudaMalloc((void**) &gpu_input, SIZE);
cudaMalloc((void**) &gpu_output, SIZE);
cudaMemset(gpu_output, 0, SIZE);
cudaMemset(gpu_input, 0, SIZE);
/* End preprocessing */
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output,
(void*)gpu_output,
SIZE,
cudaMemcpyDeviceToHost);
/* End copy array */
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree((void**) &gpu_input);
cudaFree((void**) &gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .file "tmpxft_00008ec3_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z30__device_stub__Z8init_gpuPdS_iPdS_i
.type _Z30__device_stub__Z8init_gpuPdS_iPdS_i, @function
_Z30__device_stub__Z8init_gpuPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8init_gpuPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z30__device_stub__Z8init_gpuPdS_iPdS_i, .-_Z30__device_stub__Z8init_gpuPdS_iPdS_i
.globl _Z8init_gpuPdS_i
.type _Z8init_gpuPdS_i, @function
_Z8init_gpuPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8init_gpuPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z8init_gpuPdS_i, .-_Z8init_gpuPdS_i
.globl _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
.type _Z34__device_stub__Z11compute_gpuPdS_iPdS_i, @function
_Z34__device_stub__Z11compute_gpuPdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11compute_gpuPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z34__device_stub__Z11compute_gpuPdS_iPdS_i, .-_Z34__device_stub__Z11compute_gpuPdS_iPdS_i
.globl _Z11compute_gpuPdS_i
.type _Z11compute_gpuPdS_i, @function
_Z11compute_gpuPdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z11compute_gpuPdS_i, .-_Z11compute_gpuPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host to Device MemCpy takes "
.LC4:
.string "s"
.LC5:
.string "Computation takes "
.LC6:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %r14
movl %edx, %r13d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
salq $3, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq %r12, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L29:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leal -2(%r13), %eax
movl $1, 80(%rsp)
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
testl %ebp, %ebp
jle .L30
movl $0, %ebx
jmp .L32
.L48:
movl %r13d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z30__device_stub__Z8init_gpuPdS_iPdS_i
jmp .L29
.L31:
movq 64(%rsp), %rax
movq 72(%rsp), %rdx
movq %rdx, 64(%rsp)
movq %rax, 72(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L30
.L32:
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl %r13d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
jmp .L31
.L30:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r12, %rdx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %rdi
call cudaFree@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L49
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %esi
.L40:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L51
cmpb $0, 56(%rbp)
je .L43
movzbl 67(%rbp), %esi
.L44:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L51:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L43:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L44
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC7:
.string "_Z11compute_gpuPdS_i"
.LC8:
.string "_Z8init_gpuPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11compute_gpuPdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8init_gpuPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
cudaMalloc((void**) &gpu_input, SIZE);
cudaMalloc((void**) &gpu_output, SIZE);
cudaMemset(gpu_output, 0, SIZE);
cudaMemset(gpu_input, 0, SIZE);
/* End preprocessing */
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output,
(void*)gpu_output,
SIZE,
cudaMemcpyDeviceToHost);
/* End copy array */
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree((void**) &gpu_input);
cudaFree((void**) &gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
hipMalloc((void**) &gpu_input, SIZE);
hipMalloc((void**) &gpu_output, SIZE);
hipMemset(gpu_output, 0, SIZE);
hipMemset(gpu_input, 0, SIZE);
/* End preprocessing */
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output,
(void*)gpu_output,
SIZE,
hipMemcpyDeviceToHost);
/* End copy array */
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree((void**) &gpu_input);
hipFree((void**) &gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
hipMalloc((void**) &gpu_input, SIZE);
hipMalloc((void**) &gpu_output, SIZE);
hipMemset(gpu_output, 0, SIZE);
hipMemset(gpu_input, 0, SIZE);
/* End preprocessing */
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output,
(void*)gpu_output,
SIZE,
hipMemcpyDeviceToHost);
/* End copy array */
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree((void**) &gpu_input);
hipFree((void**) &gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8init_gpuPdS_i
.globl _Z8init_gpuPdS_i
.p2align 8
.type _Z8init_gpuPdS_i,@function
_Z8init_gpuPdS_i:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s11, 0x408f4000
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s6, s4
s_ashr_i32 s16, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s16, -1
s_mul_i32 s17, s16, s6
s_mul_i32 s10, s8, s6
s_add_i32 s4, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[4:5], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
s_add_i32 s8, s17, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s12, s0, s8
s_addc_u32 s13, s1, s9
s_add_i32 s14, s10, s16
s_mov_b32 s10, 0
s_ashr_i32 s15, s14, 31
v_mov_b32_e32 v0, s10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s11
s_lshl_b64 s[10:11], s[14:15], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s0, s10
s_addc_u32 s15, s1, s11
s_add_i32 s16, s17, s16
global_store_b64 v2, v[0:1], s[6:7]
s_ashr_i32 s17, s16, 31
global_store_b64 v2, v[0:1], s[12:13]
s_lshl_b64 s[6:7], s[16:17], 3
global_store_b64 v2, v[0:1], s[14:15]
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
global_store_b64 v2, v[0:1], s[0:1]
s_add_u32 s0, s2, s8
s_addc_u32 s1, s3, s9
global_store_b64 v2, v[0:1], s[4:5]
s_add_u32 s4, s2, s10
s_addc_u32 s5, s3, s11
global_store_b64 v2, v[0:1], s[0:1]
s_add_u32 s0, s2, s6
s_addc_u32 s1, s3, s7
s_clause 0x1
global_store_b64 v2, v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8init_gpuPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 18
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8init_gpuPdS_i, .Lfunc_end0-_Z8init_gpuPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11compute_gpuPdS_i
.globl _Z11compute_gpuPdS_i
.p2align 8
.type _Z11compute_gpuPdS_i,@function
_Z11compute_gpuPdS_i:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_i32 s5, s15, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, 1, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 31
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 1
s_add_i32 s6, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s5, s6
s_cselect_b32 s7, -1, 0
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_2
v_cmp_ne_u32_e32 vcc_lo, s6, v0
v_cmp_ne_u32_e64 s2, s3, v0
s_and_not1_b32 s7, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s2
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB1_7
s_cmp_lg_u32 s5, s3
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_5
v_cmp_ne_u32_e32 vcc_lo, s6, v0
v_cmp_ne_u32_e64 s2, s3, v0
s_and_not1_b32 s3, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s3, s2
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB1_7
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s6, s15, s4
v_add_nc_u32_e32 v18, 2, v1
v_add_nc_u32_e32 v2, s6, v1
v_add_nc_u32_e32 v4, s6, v0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, s6, v18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v8, s5, v1
v_add_nc_u32_e32 v10, s5, v0
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_nc_u32_e32 v14, s5, v18
s_add_i32 s5, s15, 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
global_load_b64 v[6:7], v[6:7], off
s_mul_i32 s5, s5, s4
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
global_load_b64 v[8:9], v[8:9], off
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_add_nc_u32_e32 v16, s5, v1
global_load_b64 v[12:13], v[12:13], off
v_add_nc_u32_e32 v0, s5, v0
v_add_nc_u32_e32 v18, s5, v18
v_add_co_u32 v14, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v19, 31, v18
global_load_b64 v[14:15], v[14:15], off
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[18:19], 3, v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v16, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v18, vcc_lo, s0, v18
global_load_b64 v[0:1], v[0:1], off
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(7)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(5)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[12:13]
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[2:3], v[14:15]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[16:17]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[18:19]
v_div_scale_f64 v[2:3], null, 0x40220000, 0x40220000, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_div_scale_f64 v[6:7], vcc_lo, v[0:1], 0x40220000, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[6:7], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
v_div_fixup_f64 v[0:1], v[2:3], 0x40220000, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11compute_gpuPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11compute_gpuPdS_i, .Lfunc_end1-_Z11compute_gpuPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8init_gpuPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8init_gpuPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11compute_gpuPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11compute_gpuPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
============================================================================
Filename : implementation.cu
Author : Lucien Michaël Iseli, Loris Pilotto
SCIPER : 274999, 262651
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void init_gpu(double* gpu_input, double* gpu_output, int length){
gpu_input[(length/2-1)*length+(length/2-1)] = 1000;
gpu_input[(length/2)*length+(length/2-1)] = 1000;
gpu_input[(length/2-1)*length+(length/2)] = 1000;
gpu_input[(length/2)*length+(length/2)] = 1000;
gpu_output[(length/2-1)*length+(length/2-1)] = 1000;
gpu_output[(length/2)*length+(length/2-1)] = 1000;
gpu_output[(length/2-1)*length+(length/2)] = 1000;
gpu_output[(length/2)*length+(length/2)] = 1000;
}
__global__
void compute_gpu(double* gpu_input, double* gpu_output, int length){
int x_glob = blockIdx.x + 1;
int y_glob = threadIdx.y + 1;
if(x_glob == length/2-1 && (y_glob == length/2-1 || y_glob == length/2) ||
x_glob == length/2 && (y_glob == length/2-1 || y_glob == length/2))
return;
gpu_output[(x_glob)*(length)+(y_glob)] = (gpu_input[(x_glob-1)*(length)+(y_glob-1)] +
gpu_input[(x_glob-1)*(length)+(y_glob)] +
gpu_input[(x_glob-1)*(length)+(y_glob+1)] +
gpu_input[(x_glob)*(length)+(y_glob-1)] +
gpu_input[(x_glob)*(length)+(y_glob)] +
gpu_input[(x_glob)*(length)+(y_glob+1)] +
gpu_input[(x_glob+1)*(length)+(y_glob-1)] +
gpu_input[(x_glob+1)*(length)+(y_glob)] +
gpu_input[(x_glob+1)*(length)+(y_glob+1)] ) /9;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t SIZE = length * length * sizeof(double);
double* gpu_input;
double* gpu_output;
double* temp;
hipMalloc((void**) &gpu_input, SIZE);
hipMalloc((void**) &gpu_output, SIZE);
hipMemset(gpu_output, 0, SIZE);
hipMemset(gpu_input, 0, SIZE);
/* End preprocessing */
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
init_gpu <<< 1, 1 >>> (gpu_input, gpu_output, length);
/* End copy array */
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
dim3 thrsPerBlock(1,length-2);
dim3 nBlks(length-2,1);
for(int n = 0; n <(int)iterations; n++){
compute_gpu <<< nBlks, thrsPerBlock >>> (gpu_input, gpu_output, length);
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
/* End GPU calculation */
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output,
(void*)gpu_output,
SIZE,
hipMemcpyDeviceToHost);
/* End copy array */
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree((void**) &gpu_input);
hipFree((void**) &gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__init_gpuPdS_i # -- Begin function _Z23__device_stub__init_gpuPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__init_gpuPdS_i,@function
_Z23__device_stub__init_gpuPdS_i: # @_Z23__device_stub__init_gpuPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8init_gpuPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__init_gpuPdS_i, .Lfunc_end1-_Z23__device_stub__init_gpuPdS_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__compute_gpuPdS_i # -- Begin function _Z26__device_stub__compute_gpuPdS_i
.p2align 4, 0x90
.type _Z26__device_stub__compute_gpuPdS_i,@function
_Z26__device_stub__compute_gpuPdS_i: # @_Z26__device_stub__compute_gpuPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11compute_gpuPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z26__device_stub__compute_gpuPdS_i, .Lfunc_end2-_Z26__device_stub__compute_gpuPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, 192(%rsp) # 8-byte Spill
movabsq $4294967297, %r12 # imm = 0x100000001
leaq 176(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
movq %rbx, 64(%rsp) # 8-byte Spill
# kill: def $ebx killed $ebx killed $rbx def $rbx
imull %ebx, %ebx
shlq $3, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq hipMemset
movq 176(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8init_gpuPdS_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %ebp, %ebp
jle .LBB3_7
# %bb.3:
movq 64(%rsp), %rax # 8-byte Reload
leal -2(%rax), %r13d
addq %r13, %r12
decq %r12
shlq $32, %r13
orq $1, %r13
leaq 104(%rsp), %r14
leaq 96(%rsp), %rbx
leaq 32(%rsp), %r15
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, 24(%rsp)
movq %rax, 8(%rsp)
decl %ebp
je .LBB3_7
.LBB3_4: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z11compute_gpuPdS_i, %edi
movq %r15, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_6
.LBB3_7: # %._crit_edge
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq 192(%rsp), %rdi # 8-byte Reload
movq 184(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
leaq 24(%rsp), %rdi
callq hipFree
leaq 8(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_10
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB3_11
.LBB3_10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 168(%rsp), %rsi
movq 80(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r14)
je .LBB3_14
# %bb.13:
movzbl 67(%r14), %eax
jmp .LBB3_15
.LBB3_14:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 160(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r14)
je .LBB3_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB3_19
.LBB3_18:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_20:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end3-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8init_gpuPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11compute_gpuPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8init_gpuPdS_i,@object # @_Z8init_gpuPdS_i
.section .rodata,"a",@progbits
.globl _Z8init_gpuPdS_i
.p2align 3, 0x0
_Z8init_gpuPdS_i:
.quad _Z23__device_stub__init_gpuPdS_i
.size _Z8init_gpuPdS_i, 8
.type _Z11compute_gpuPdS_i,@object # @_Z11compute_gpuPdS_i
.globl _Z11compute_gpuPdS_i
.p2align 3, 0x0
_Z11compute_gpuPdS_i:
.quad _Z26__device_stub__compute_gpuPdS_i
.size _Z11compute_gpuPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8init_gpuPdS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11compute_gpuPdS_i"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__init_gpuPdS_i
.addrsig_sym _Z26__device_stub__compute_gpuPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8init_gpuPdS_i
.addrsig_sym _Z11compute_gpuPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11compute_gpuPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e640000002200 */
/*0040*/ LEA.HI R2, R0, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0000027a11 */
/* 0x000fc800078f08ff */
/*0050*/ SHF.R.S32.HI R4, RZ, 0x1, R2 ; /* 0x00000001ff047819 */
/* 0x000fc80000011402 */
/*0060*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe40007ffe0ff */
/*0070*/ IADD3 R2, R17, 0x1, RZ ; /* 0x0000000111027810 */
/* 0x001fc80007ffe0ff */
/*0080*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f05270 */
/*0090*/ IADD3 R3, R16, 0x1, RZ ; /* 0x0000000110037810 */
/* 0x002fd60007ffe0ff */
/*00a0*/ @P0 BRA 0xe0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f05270 */
/*00c0*/ ISETP.EQ.OR P0, PT, R3, R2, !P0 ; /* 0x000000020300720c */
/* 0x000fda0004702670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fe20003f05270 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0100*/ @P0 BRA 0x140 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fc80003f05270 */
/*0120*/ ISETP.EQ.OR P0, PT, R3, R2, !P0 ; /* 0x000000020300720c */
/* 0x000fda0004702670 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff177424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD R22, R17, c[0x0][0x170], R16 ; /* 0x00005c0011167a24 */
/* 0x000fc800078e0210 */
/*0160*/ IMAD.WIDE R22, R22, R23, c[0x0][0x160] ; /* 0x0000580016167625 */
/* 0x000fca00078e0217 */
/*0170*/ LDG.E.64 R20, [R22.64+0x8] ; /* 0x0000080416147981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ IMAD.WIDE R24, R0, 0x8, R22 ; /* 0x0000000800187825 */
/* 0x000fc600078e0216 */
/*01a0*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R14, [R24.64+0x8] ; /* 0x00000804180e7981 */
/* 0x000f62000c1e1b00 */
/*01d0*/ IMAD.WIDE R26, R0, 0x8, R24 ; /* 0x00000008001a7825 */
/* 0x000fc600078e0218 */
/*01e0*/ LDG.E.64 R10, [R24.64+0x10] ; /* 0x00001004180a7981 */
/* 0x000f68000c1e1b00 */
/*01f0*/ LDG.E.64 R6, [R26.64] ; /* 0x000000041a067981 */
/* 0x000f68000c1e1b00 */
/*0200*/ LDG.E.64 R4, [R26.64+0x8] ; /* 0x000008041a047981 */
/* 0x000f68000c1e1b00 */
/*0210*/ LDG.E.64 R2, [R26.64+0x10] ; /* 0x000010041a027981 */
/* 0x000f62000c1e1b00 */
/*0220*/ IMAD R17, R17, R0, c[0x0][0x170] ; /* 0x00005c0011117624 */
/* 0x000fe200078e0200 */
/*0230*/ BSSY B0, 0x420 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*0240*/ IMAD.IADD R16, R17, 0x1, R16 ; /* 0x0000000111107824 */
/* 0x000fe200078e0210 */
/*0250*/ DADD R20, R20, R18 ; /* 0x0000000014147229 */
/* 0x0040c40000000012 */
/*0260*/ MUFU.RCP64H R19, 9 ; /* 0x4022000000137908 */
/* 0x001e220000001800 */
/*0270*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc600078e00ff */
/*0280*/ DADD R20, R20, R12 ; /* 0x0000000014147229 */
/* 0x008324000000000c */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x002fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40220000 ; /* 0x40220000ff0d7424 */
/* 0x000fe400078e00ff */
/*02b0*/ DADD R8, R20, R8 ; /* 0x0000000014087229 */
/* 0x010f480000000008 */
/*02c0*/ DFMA R20, R18, -R12, 1 ; /* 0x3ff000001214742b */
/* 0x001e08000000080c */
/*02d0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e48000000000e */
/*02e0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*02f0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x002e48000000000a */
/*0300*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e080000000012 */
/*0310*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x002e480000000006 */
/*0320*/ DFMA R12, R20, -R12, 1 ; /* 0x3ff00000140c742b */
/* 0x001e08000000080c */
/*0330*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e480000000004 */
/*0340*/ DFMA R12, R20, R12, R20 ; /* 0x0000000c140c722b */
/* 0x001fc80000000014 */
/*0350*/ DADD R4, R4, R2 ; /* 0x0000000004047229 */
/* 0x002e0c0000000002 */
/*0360*/ DMUL R2, R4, R12 ; /* 0x0000000c04027228 */
/* 0x001e080000000000 */
/*0370*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe40003f2e200 */
/*0380*/ DFMA R6, R2, -9, R4 ; /* 0xc02200000206782b */
/* 0x001e0c0000000004 */
/*0390*/ DFMA R2, R12, R6, R2 ; /* 0x000000060c02722b */
/* 0x001e140000000002 */
/*03a0*/ FFMA R6, RZ, 2.53125, R3 ; /* 0x40220000ff067823 */
/* 0x001fca0000000003 */
/*03b0*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*03c0*/ @P0 BRA P1, 0x410 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03d0*/ MOV R0, 0x3f0 ; /* 0x000003f000007802 */
/* 0x000fe40000000f00 */
/*03e0*/ CALL.REL.NOINC 0x460 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0400*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*0440*/ STG.E.64 [R16.64+0x8], R2 ; /* 0x0000080210007986 */
/* 0x000fe2000c101b04 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3ff20000 ; /* 0x3ff20000ff037424 */
/* 0x000fe200078e00ff */
/*0470*/ FSETP.GEU.AND P1, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f2e200 */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0490*/ LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005067812 */
/* 0x000fe200078ec0ff */
/*04a0*/ MUFU.RCP64H R9, R3 ; /* 0x0000000300097308 */
/* 0x000e220000001800 */
/*04b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*04c0*/ BSSY B1, 0x920 ; /* 0x0000045000017945 */
/* 0x000fe20003800000 */
/*04d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff077424 */
/* 0x000fe200078e00ff */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, 0x40200000, PT ; /* 0x402000000600780c */
/* 0x000fe20003f06070 */
/*04f0*/ IMAD.MOV.U32 R17, RZ, RZ, R6 ; /* 0x000000ffff117224 */
/* 0x000fc400078e0006 */
/*0500*/ IMAD.MOV.U32 R18, RZ, RZ, 0x40200000 ; /* 0x40200000ff127424 */
/* 0x000fe200078e00ff */
/*0510*/ SEL R7, R7, 0x63400000, !P0 ; /* 0x6340000007077807 */
/* 0x000fc80004000000 */
/*0520*/ @!P1 LOP3.LUT R14, R7, 0x80000000, R5, 0xf8, !PT ; /* 0x80000000070e9812 */
/* 0x000fe400078ef805 */
/*0530*/ IADD3 R20, R18, -0x1, RZ ; /* 0xffffffff12147810 */
/* 0x000fe20007ffe0ff */
/*0540*/ DFMA R10, R8, -R2, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000802 */
/*0550*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0560*/ DFMA R12, R8, R10, R8 ; /* 0x0000000a080c722b */
/* 0x0010640000000008 */
/*0570*/ LOP3.LUT R9, R7, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff07097812 */
/* 0x001fe200078ef805 */
/*0580*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0590*/ @!P1 LOP3.LUT R11, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0b9812 */
/* 0x000fe200078efcff */
/*05a0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e00ff */
/*05b0*/ DFMA R14, R12, -R2, 1 ; /* 0x3ff000000c0e742b */
/* 0x002e0a0000000802 */
/*05c0*/ @!P1 DFMA R8, R8, 2, -R10 ; /* 0x400000000808982b */
/* 0x000e48000000080a */
/*05d0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e0c000000000c */
/*05e0*/ @!P1 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009119812 */
/* 0x002fe200078ec0ff */
/*05f0*/ DMUL R10, R14, R8 ; /* 0x000000080e0a7228 */
/* 0x001e060000000000 */
/*0600*/ IADD3 R19, R17, -0x1, RZ ; /* 0xffffffff11137810 */
/* 0x000fc60007ffe0ff */
/*0610*/ DFMA R12, R10, -R2, R8 ; /* 0x800000020a0c722b */
/* 0x001e220000000008 */
/*0620*/ ISETP.GT.U32.AND P0, PT, R19, 0x7feffffe, PT ; /* 0x7feffffe1300780c */
/* 0x000fc80003f04070 */
/*0630*/ ISETP.GT.U32.OR P0, PT, R20, 0x7feffffe, P0 ; /* 0x7feffffe1400780c */
/* 0x000fe20000704470 */
/*0640*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x001058000000000a */
/*0650*/ @P0 BRA 0x800 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R6, R6, -0x40200000, RZ ; /* 0xbfe0000006067810 */
/* 0x003fe20007ffe0ff */
/*0670*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0680*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0690*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*06a0*/ IMAD.IADD R12, R6, 0x1, -R7 ; /* 0x00000001060c7824 */
/* 0x000fca00078e0a07 */
/*06b0*/ IADD3 R5, R12, 0x7fe00000, RZ ; /* 0x7fe000000c057810 */
/* 0x000fcc0007ffe0ff */
/*06c0*/ DMUL R6, R10, R4 ; /* 0x000000040a067228 */
/* 0x000e140000000000 */
/*06d0*/ FSETP.GTU.AND P0, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x001fda0003f0c200 */
/*06e0*/ @P0 BRA 0x910 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*06f0*/ DFMA R2, R10, -R2, R8 ; /* 0x800000020a02722b */
/* 0x000e220000000008 */
/*0700*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0710*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0720*/ LOP3.LUT R2, R3, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000003027812 */
/* 0x000fc800078e3cff */
/*0730*/ LOP3.LUT R9, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002097812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R5, R9, R5, RZ, 0xfc, !PT ; /* 0x0000000509057212 */
/* 0x000fc600078efcff */
/*0750*/ @!P0 BRA 0x910 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV R3, RZ, RZ, -R12 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0c */
/*0770*/ DMUL.RP R4, R10, R4 ; /* 0x000000040a047228 */
/* 0x000e220000008000 */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0790*/ DFMA R2, R6, -R2, R10 ; /* 0x800000020602722b */
/* 0x000e46000000000a */
/*07a0*/ LOP3.LUT R9, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905097212 */
/* 0x001fc600078e3cff */
/*07b0*/ IADD3 R2, -R12, -0x43300000, RZ ; /* 0xbcd000000c027810 */
/* 0x002fc80007ffe1ff */
/*07c0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*07d0*/ FSEL R6, R4, R6, !P0 ; /* 0x0000000604067208 */
/* 0x000fe40004000000 */
/*07e0*/ FSEL R7, R9, R7, !P0 ; /* 0x0000000709077208 */
/* 0x000fe20004000000 */
/*07f0*/ BRA 0x910 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0800*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x003e1c0003f08000 */
/*0810*/ @P0 BRA 0x8f0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R17, R18, PT ; /* 0x000000121100720c */
/* 0x000fe20003f05270 */
/*0830*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff077424 */
/* 0x000fd400078e00ff */
/*0850*/ @!P0 BRA 0x910 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0860*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0870*/ LOP3.LUT R4, R5, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000005047812 */
/* 0x000fe400078e3cff */
/*0880*/ ISETP.EQ.OR P0, PT, R18, RZ, !P0 ; /* 0x000000ff1200720c */
/* 0x000fe40004702670 */
/*0890*/ LOP3.LUT R7, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004077812 */
/* 0x000fd600078ec0ff */
/*08a0*/ @P0 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000007020812 */
/* 0x000fe200078efcff */
/*08b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe400078e00ff */
/*08c0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*08d0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0002 */
/*08e0*/ BRA 0x910 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe200078efcff */
/*0900*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0910*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0920*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0930*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0940*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff6b002007950 */
/* 0x000fea0003c3ffff */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8init_gpuPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fe20000000f00 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 2.279296875, 2 ; /* 0x408f4000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ LEA.HI R0, R0, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0000007a11 */
/* 0x000fe200078f08ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*0080*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x000fca0007ffe0ff */
/*0090*/ IMAD R6, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c0003067a24 */
/* 0x100fe400078e0200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x170], R0 ; /* 0x00005c0000007a24 */
/* 0x000fe400078e0200 */
/*00b0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x0c0fe200078e0207 */
/*00d0*/ STG.E.64 [R2.64+-0x8], R10 ; /* 0xfffff80a02007986 */
/* 0x000fe6000c101b04 */
/*00e0*/ IMAD.WIDE R8, R0, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x080fe200078e0207 */
/*00f0*/ STG.E.64 [R4.64+-0x8], R10 ; /* 0xfffff80a04007986 */
/* 0x000fe6000c101b04 */
/*0100*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0110*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe8000c101b04 */
/*0120*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe8000c101b04 */
/*0130*/ STG.E.64 [R6.64+-0x8], R10 ; /* 0xfffff80a06007986 */
/* 0x000fe8000c101b04 */
/*0140*/ STG.E.64 [R8.64+-0x8], R10 ; /* 0xfffff80a08007986 */
/* 0x000fe8000c101b04 */
/*0150*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x000fe8000c101b04 */
/*0160*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8init_gpuPdS_i
.globl _Z8init_gpuPdS_i
.p2align 8
.type _Z8init_gpuPdS_i,@function
_Z8init_gpuPdS_i:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s11, 0x408f4000
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s6, s4
s_ashr_i32 s16, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s16, -1
s_mul_i32 s17, s16, s6
s_mul_i32 s10, s8, s6
s_add_i32 s4, s10, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[4:5], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
s_add_i32 s8, s17, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 3
s_add_u32 s12, s0, s8
s_addc_u32 s13, s1, s9
s_add_i32 s14, s10, s16
s_mov_b32 s10, 0
s_ashr_i32 s15, s14, 31
v_mov_b32_e32 v0, s10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s11
s_lshl_b64 s[10:11], s[14:15], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s0, s10
s_addc_u32 s15, s1, s11
s_add_i32 s16, s17, s16
global_store_b64 v2, v[0:1], s[6:7]
s_ashr_i32 s17, s16, 31
global_store_b64 v2, v[0:1], s[12:13]
s_lshl_b64 s[6:7], s[16:17], 3
global_store_b64 v2, v[0:1], s[14:15]
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
global_store_b64 v2, v[0:1], s[0:1]
s_add_u32 s0, s2, s8
s_addc_u32 s1, s3, s9
global_store_b64 v2, v[0:1], s[4:5]
s_add_u32 s4, s2, s10
s_addc_u32 s5, s3, s11
global_store_b64 v2, v[0:1], s[0:1]
s_add_u32 s0, s2, s6
s_addc_u32 s1, s3, s7
s_clause 0x1
global_store_b64 v2, v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8init_gpuPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 18
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8init_gpuPdS_i, .Lfunc_end0-_Z8init_gpuPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11compute_gpuPdS_i
.globl _Z11compute_gpuPdS_i
.p2align 8
.type _Z11compute_gpuPdS_i,@function
_Z11compute_gpuPdS_i:
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_add_i32 s5, s15, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v0, 1, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 31
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 1
s_add_i32 s6, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s5, s6
s_cselect_b32 s7, -1, 0
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_2
v_cmp_ne_u32_e32 vcc_lo, s6, v0
v_cmp_ne_u32_e64 s2, s3, v0
s_and_not1_b32 s7, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s7, s2
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB1_7
s_cmp_lg_u32 s5, s3
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB1_5
v_cmp_ne_u32_e32 vcc_lo, s6, v0
v_cmp_ne_u32_e64 s2, s3, v0
s_and_not1_b32 s3, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s7, s3, s2
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB1_7
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s6, s15, s4
v_add_nc_u32_e32 v18, 2, v1
v_add_nc_u32_e32 v2, s6, v1
v_add_nc_u32_e32 v4, s6, v0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, s6, v18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v8, s5, v1
v_add_nc_u32_e32 v10, s5, v0
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_nc_u32_e32 v14, s5, v18
s_add_i32 s5, s15, 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_ashrrev_i32_e32 v15, 31, v14
global_load_b64 v[6:7], v[6:7], off
s_mul_i32 s5, s5, s4
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
global_load_b64 v[8:9], v[8:9], off
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_add_nc_u32_e32 v16, s5, v1
global_load_b64 v[12:13], v[12:13], off
v_add_nc_u32_e32 v0, s5, v0
v_add_nc_u32_e32 v18, s5, v18
v_add_co_u32 v14, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v19, 31, v18
global_load_b64 v[14:15], v[14:15], off
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[18:19], 3, v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v16, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v18, vcc_lo, s0, v18
global_load_b64 v[0:1], v[0:1], off
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(7)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(5)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[12:13]
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[2:3], v[14:15]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[16:17]
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[18:19]
v_div_scale_f64 v[2:3], null, 0x40220000, 0x40220000, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
v_div_scale_f64 v[6:7], vcc_lo, v[0:1], 0x40220000, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[6:7], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
v_div_fixup_f64 v[0:1], v[2:3], 0x40220000, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v11, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11compute_gpuPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11compute_gpuPdS_i, .Lfunc_end1-_Z11compute_gpuPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8init_gpuPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8init_gpuPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11compute_gpuPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11compute_gpuPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008ec3_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z30__device_stub__Z8init_gpuPdS_iPdS_i
.type _Z30__device_stub__Z8init_gpuPdS_iPdS_i, @function
_Z30__device_stub__Z8init_gpuPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8init_gpuPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z30__device_stub__Z8init_gpuPdS_iPdS_i, .-_Z30__device_stub__Z8init_gpuPdS_iPdS_i
.globl _Z8init_gpuPdS_i
.type _Z8init_gpuPdS_i, @function
_Z8init_gpuPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8init_gpuPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z8init_gpuPdS_i, .-_Z8init_gpuPdS_i
.globl _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
.type _Z34__device_stub__Z11compute_gpuPdS_iPdS_i, @function
_Z34__device_stub__Z11compute_gpuPdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11compute_gpuPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z34__device_stub__Z11compute_gpuPdS_iPdS_i, .-_Z34__device_stub__Z11compute_gpuPdS_iPdS_i
.globl _Z11compute_gpuPdS_i
.type _Z11compute_gpuPdS_i, @function
_Z11compute_gpuPdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z11compute_gpuPdS_i, .-_Z11compute_gpuPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host to Device MemCpy takes "
.LC4:
.string "s"
.LC5:
.string "Computation takes "
.LC6:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %r14
movl %edx, %r13d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %r13d, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
salq $3, %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq %r12, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movq %r12, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L29:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leal -2(%r13), %eax
movl $1, 80(%rsp)
movl %eax, 84(%rsp)
movl $1, 88(%rsp)
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
testl %ebp, %ebp
jle .L30
movl $0, %ebx
jmp .L32
.L48:
movl %r13d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z30__device_stub__Z8init_gpuPdS_iPdS_i
jmp .L29
.L31:
movq 64(%rsp), %rax
movq 72(%rsp), %rdx
movq %rdx, 64(%rsp)
movq %rax, 72(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L30
.L32:
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L31
movl %r13d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z34__device_stub__Z11compute_gpuPdS_iPdS_i
jmp .L31
.L30:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r12, %rdx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %rdi
call cudaFree@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L49
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %esi
.L40:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 12(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 12(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L51
cmpb $0, 56(%rbp)
je .L43
movzbl 67(%rbp), %esi
.L44:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
call _ZSt16__throw_bad_castv@PLT
.L53:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L50:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
call _ZSt16__throw_bad_castv@PLT
.L54:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L51:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L43:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L44
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC7:
.string "_Z11compute_gpuPdS_i"
.LC8:
.string "_Z8init_gpuPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11compute_gpuPdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8init_gpuPdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__init_gpuPdS_i # -- Begin function _Z23__device_stub__init_gpuPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__init_gpuPdS_i,@function
_Z23__device_stub__init_gpuPdS_i: # @_Z23__device_stub__init_gpuPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8init_gpuPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__init_gpuPdS_i, .Lfunc_end1-_Z23__device_stub__init_gpuPdS_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__compute_gpuPdS_i # -- Begin function _Z26__device_stub__compute_gpuPdS_i
.p2align 4, 0x90
.type _Z26__device_stub__compute_gpuPdS_i,@function
_Z26__device_stub__compute_gpuPdS_i: # @_Z26__device_stub__compute_gpuPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11compute_gpuPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z26__device_stub__compute_gpuPdS_i, .Lfunc_end2-_Z26__device_stub__compute_gpuPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, 192(%rsp) # 8-byte Spill
movabsq $4294967297, %r12 # imm = 0x100000001
leaq 176(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
movq %rbx, 64(%rsp) # 8-byte Spill
# kill: def $ebx killed $ebx killed $rbx def $rbx
imull %ebx, %ebx
shlq $3, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq hipMemset
movq 176(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8init_gpuPdS_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
callq hipEventSynchronize
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %ebp, %ebp
jle .LBB3_7
# %bb.3:
movq 64(%rsp), %rax # 8-byte Reload
leal -2(%rax), %r13d
addq %r13, %r12
decq %r12
shlq $32, %r13
orq $1, %r13
leaq 104(%rsp), %r14
leaq 96(%rsp), %rbx
leaq 32(%rsp), %r15
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rcx, 24(%rsp)
movq %rax, 8(%rsp)
decl %ebp
je .LBB3_7
.LBB3_4: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=1
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z11compute_gpuPdS_i, %edi
movq %r15, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_6
.LBB3_7: # %._crit_edge
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi
callq hipEventSynchronize
movq 160(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq 192(%rsp), %rdi # 8-byte Reload
movq 184(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 72(%rsp), %rdi
callq hipEventSynchronize
leaq 24(%rsp), %rdi
callq hipFree
leaq 8(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB3_10
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB3_11
.LBB3_10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 168(%rsp), %rsi
movq 80(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%r14)
je .LBB3_14
# %bb.13:
movzbl 67(%r14), %eax
jmp .LBB3_15
.LBB3_14:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 160(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_20
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r14)
je .LBB3_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB3_19
.LBB3_18:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_20:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end3-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8init_gpuPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11compute_gpuPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8init_gpuPdS_i,@object # @_Z8init_gpuPdS_i
.section .rodata,"a",@progbits
.globl _Z8init_gpuPdS_i
.p2align 3, 0x0
_Z8init_gpuPdS_i:
.quad _Z23__device_stub__init_gpuPdS_i
.size _Z8init_gpuPdS_i, 8
.type _Z11compute_gpuPdS_i,@object # @_Z11compute_gpuPdS_i
.globl _Z11compute_gpuPdS_i
.p2align 3, 0x0
_Z11compute_gpuPdS_i:
.quad _Z26__device_stub__compute_gpuPdS_i
.size _Z11compute_gpuPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8init_gpuPdS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11compute_gpuPdS_i"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__init_gpuPdS_i
.addrsig_sym _Z26__device_stub__compute_gpuPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8init_gpuPdS_i
.addrsig_sym _Z11compute_gpuPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} | code for sm_80
Function : _Z10avg_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R0, 0x400, R3 ; /* 0x0000040000047824 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R6, R4.reuse, 0x200, RZ ; /* 0x0000020004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff07a424 */
/* 0x000fe400078e00ff */
/*00a0*/ @P1 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff021224 */
/* 0x000fe400078e00ff */
/*00b0*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff082224 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004049625 */
/* 0x000fc800078e0005 */
/*00d0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x000058000606a625 */
/* 0x000fe200078e0007 */
/*00e0*/ @!P1 LDG.E R2, [R4.64] ; /* 0x0000000404029981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @!P2 LDG.E R8, [R6.64] ; /* 0x000000040608a981 */
/* 0x000ee2000c1e1900 */
/*0100*/ ISETP.GT.U32.AND P3, PT, R3.reuse, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x040fe40003f64070 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fe20003f04070 */
/*0120*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0130*/ @P2 STS [R3.X4+0x800], RZ ; /* 0x000800ff03002388 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x004fe20000004800 */
/*0150*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fe20003f24070 */
/*0160*/ @!P3 FADD R10, R8, R2 ; /* 0x00000002080ab221 */
/* 0x008fc40000000000 */
/*0170*/ @!P2 STS [R3.X4+0x800], R8 ; /* 0x000800080300a388 */
/* 0x000fe80000004800 */
/*0180*/ @!P3 STS [R3.X4], R10 ; /* 0x0000000a0300b388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*01b0*/ @!P0 LDS R5, [R3.X4+0x400] ; /* 0x0004000003058984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f04070 */
/*0200*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0230*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f24070 */
/*0260*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0270*/ @!P0 LDS R6, [R3.X4+0x100] ; /* 0x0001000003068984 */
/* 0x000e240000004800 */
/*0280*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0290*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f04070 */
/*02c0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*02d0*/ @!P1 LDS R5, [R3.X4+0x80] ; /* 0x0000800003059984 */
/* 0x000e240000004800 */
/*02e0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*02f0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f24070 */
/*0320*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0330*/ @!P0 LDS R5, [R3.X4+0x40] ; /* 0x0000400003058984 */
/* 0x000e240000004800 */
/*0340*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0350*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0370*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f04070 */
/*0380*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0390*/ @!P1 LDS R6, [R3.X4+0x20] ; /* 0x0000200003069984 */
/* 0x000e240000004800 */
/*03a0*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*03b0*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f24070 */
/*03e0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*03f0*/ @!P0 LDS R5, [R3.X4+0x10] ; /* 0x0000100003058984 */
/* 0x000e240000004800 */
/*0400*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0410*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0440*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R5, [R3.X4+0x8] ; /* 0x0000080003059984 */
/* 0x000e240000004800 */
/*0460*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 LDS R5, [0x4] ; /* 0x00000400ff058984 */
/* 0x000fe80000000800 */
/*04a0*/ @!P0 LDS R6, [R3.X4] ; /* 0x0000000003068984 */
/* 0x000e240000004800 */
/*04b0*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*04c0*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x0001e80000004800 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ I2F.F64 R4, c[0x0][0x170] ; /* 0x00005c0000047b12 */
/* 0x001e220000201c00 */
/*0500*/ LDS R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000e620000000800 */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0520*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e240000001800 */
/*0530*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*0540*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0550*/ DFMA R2, R2, R6, R2 ; /* 0x000000060202722b */
/* 0x0012080000000002 */
/*0560*/ F2F.F64.F32 R6, R12 ; /* 0x0000000c00067310 */
/* 0x002e640000201800 */
/*0570*/ DFMA R8, -R4, R2, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000102 */
/*0580*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e4c0000000002 */
/*0590*/ DMUL R2, R6, R8 ; /* 0x0000000806027228 */
/* 0x002e220000000000 */
/*05a0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*05b0*/ DFMA R10, -R4, R2, R6 ; /* 0x00000002040a722b */
/* 0x001e0c0000000106 */
/*05c0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x001e140000000002 */
/*05d0*/ FFMA R8, RZ, R5, R3 ; /* 0x00000005ff087223 */
/* 0x001fca0000000003 */
/*05e0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*05f0*/ @P0 BRA P1, 0x620 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0600*/ MOV R8, 0x620 ; /* 0x0000062000087802 */
/* 0x000fe40000000f00 */
/*0610*/ CALL.REL.NOINC 0x670 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0620*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x000e220000301000 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0650*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0680*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0690*/ LOP3.LUT R2, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x040fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff097424 */
/* 0x000fe200078e00ff */
/*06b0*/ LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005107812 */
/* 0x000fe400078ec0ff */
/*06c0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*06d0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*06e0*/ LOP3.LUT R14, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070e7812 */
/* 0x000fc800078ec0ff */
/*06f0*/ ISETP.GE.U32.AND P1, PT, R14, R16, PT ; /* 0x000000100e00720c */
/* 0x000fe20003f26070 */
/*0700*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*0710*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000e */
/*0720*/ SEL R15, R9, 0x63400000, !P1 ; /* 0x63400000090f7807 */
/* 0x000fe40004800000 */
/*0730*/ FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x000fe20003f2e200 */
/*0740*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x001e280000001800 */
/*0750*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe200078ec0ff */
/*0760*/ DFMA R12, R10, -R2, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000802 */
/*0770*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0780*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0790*/ DFMA R10, R12, -R2, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000802 */
/*07a0*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*07b0*/ LOP3.LUT R11, R15, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0f0b7812 */
/* 0x001fe200078ef807 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*07d0*/ @P1 BRA 0x860 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x002fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0800*/ ISETP.GE.U32.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720c */
/* 0x000fc80003f06070 */
/*0810*/ SEL R15, R9, 0x63400000, !P0 ; /* 0x63400000090f7807 */
/* 0x000fc80004000000 */
/*0820*/ LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0f7812 */
/* 0x000fc800078ef807 */
/*0830*/ LOP3.LUT R19, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f137812 */
/* 0x000fcc00078efcff */
/*0840*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*0850*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*0860*/ IADD3 R15, R17, -0x1, RZ ; /* 0xffffffff110f7810 */
/* 0x002fe20007ffe0ff */
/*0870*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*0880*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0890*/ ISETP.GT.U32.AND P0, PT, R15, 0x7feffffe, PT ; /* 0x7feffffe0f00780c */
/* 0x000fc60003f04070 */
/*08a0*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e22000000000a */
/*08b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*08c0*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*08d0*/ @P0 BRA 0xaa0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005077812 */
/* 0x003fc800078ec0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720c */
/* 0x040fe20003f06070 */
/*0900*/ IMAD.IADD R6, R14, 0x1, -R7 ; /* 0x000000010e067824 */
/* 0x000fc600078e0a07 */
/*0910*/ SEL R9, R9, 0x63400000, !P0 ; /* 0x6340000009097807 */
/* 0x000fe40004000000 */
/*0920*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0940*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe400078e0a09 */
/*0950*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0960*/ IADD3 R7, R9, 0x7fe00000, RZ ; /* 0x7fe0000009077810 */
/* 0x000fcc0007ffe0ff */
/*0970*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x000e140000000000 */
/*0980*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0990*/ @P0 BRA 0xbf0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09a0*/ DFMA R2, R12, -R2, R10 ; /* 0x800000020c02722b */
/* 0x000e22000000000a */
/*09b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*09c0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*09d0*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*09e0*/ LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; /* 0x0000000705077212 */
/* 0x000fce00078efcff */
/*09f0*/ @!P0 BRA 0xbf0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a09 */
/*0a10*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*0a20*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0a30*/ IADD3 R9, -R9, -0x43300000, RZ ; /* 0xbcd0000009097810 */
/* 0x000fca0007ffe1ff */
/*0a40*/ DFMA R2, R14, -R2, R12 ; /* 0x800000020e02722b */
/* 0x000e46000000000c */
/*0a50*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x001fce00078e3cff */
/*0a60*/ FSETP.NEU.AND P0, PT, |R3|, R9, PT ; /* 0x000000090300720b */
/* 0x002fc80003f0d200 */
/*0a70*/ FSEL R14, R6, R14, !P0 ; /* 0x0000000e060e7208 */
/* 0x000fe40004000000 */
/*0a80*/ FSEL R15, R5, R15, !P0 ; /* 0x0000000f050f7208 */
/* 0x000fe20004000000 */
/*0a90*/ BRA 0xbf0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0ab0*/ @P0 BRA 0xbd0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0ac0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*0ad0*/ @P0 BRA 0xba0 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0ae0*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0af0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0b10*/ @!P0 BRA 0xbf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0b30*/ LOP3.LUT R15, R7, 0x80000000, R5, 0x48, !PT ; /* 0x80000000070f7812 */
/* 0x000fe400078e4805 */
/*0b40*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0b50*/ @P0 LOP3.LUT R2, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f020812 */
/* 0x000fe200078efcff */
/*0b60*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*0b70*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0b80*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R2 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0002 */
/*0b90*/ BRA 0xbf0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ba0*/ LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050f7812 */
/* 0x000fe200078efcff */
/*0bb0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0bc0*/ BRA 0xbf0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT R15, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070f7812 */
/* 0x000fe200078efcff */
/*0be0*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0006 */
/*0bf0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fc400078e000e */
/*0c10*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*0c20*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff3d008007950 */
/* 0x000fec0003c3ffff */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} | .file "tmpxft_00165400_00000000-6_avg_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10avg_kernelPfS_iPfS_i
.type _Z33__device_stub__Z10avg_kernelPfS_iPfS_i, @function
_Z33__device_stub__Z10avg_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10avg_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10avg_kernelPfS_iPfS_i, .-_Z33__device_stub__Z10avg_kernelPfS_iPfS_i
.globl _Z10avg_kernelPfS_i
.type _Z10avg_kernelPfS_i, @function
_Z10avg_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10avg_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10avg_kernelPfS_i, .-_Z10avg_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10avg_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10avg_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10avg_kernelPfS_i
.globl _Z10avg_kernelPfS_i
.p2align 8
.type _Z10avg_kernelPfS_i,@function
_Z10avg_kernelPfS_i:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_lshl_b32 s3, s15, 10
s_mov_b32 s7, 0
s_mov_b32 s8, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
v_add_lshl_u32 v1, s7, v0, 2
s_xor_b32 s8, s8, -1
s_movk_i32 s7, 0x200
s_and_not1_b32 vcc_lo, exec_lo, s8
s_mov_b32 s8, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_cbranch_vccz .LBB0_4
.LBB0_2:
v_add3_u32 v1, s3, s7, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v1, 2, v0
s_movk_i32 s3, 0x200
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v2, v0
v_cvt_f64_i32_e32 v[0:1], s6
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], v[0:1], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3]
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10avg_kernelPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10avg_kernelPfS_i, .Lfunc_end0-_Z10avg_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10avg_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10avg_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 512
#define BLOCK_MASK (BLOCK_SIZE)*2
__global__ void avg_kernel(float* in_vec, float* out_vec, int len)
{
__shared__ float shared_seg_sum[2 * BLOCK_SIZE];
unsigned int p = 0;
do {
if (len > blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE)
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = in_vec[blockIdx.x * BLOCK_MASK + threadIdx.x + p * BLOCK_SIZE];
else
shared_seg_sum[threadIdx.x + p * BLOCK_SIZE] = 0.0f;
p++;
} while (p <= 1);
for (unsigned int m = BLOCK_SIZE; m >= 1; m /= 2) {
if (m > threadIdx.x) {
shared_seg_sum[threadIdx.x] += shared_seg_sum[threadIdx.x + m];
}
__syncthreads();
}
(threadIdx.x == 0) ? out_vec[blockIdx.x] = shared_seg_sum[threadIdx.x] / (1.0*len) : 0.0f;
} | .text
.file "avg_kernel.hip"
.globl _Z25__device_stub__avg_kernelPfS_i # -- Begin function _Z25__device_stub__avg_kernelPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__avg_kernelPfS_i,@function
_Z25__device_stub__avg_kernelPfS_i: # @_Z25__device_stub__avg_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10avg_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__avg_kernelPfS_i, .Lfunc_end0-_Z25__device_stub__avg_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10avg_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10avg_kernelPfS_i,@object # @_Z10avg_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z10avg_kernelPfS_i
.p2align 3, 0x0
_Z10avg_kernelPfS_i:
.quad _Z25__device_stub__avg_kernelPfS_i
.size _Z10avg_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10avg_kernelPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__avg_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10avg_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10avg_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R4, R0, 0x400, R3 ; /* 0x0000040000047824 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R6, R4.reuse, 0x200, RZ ; /* 0x0000020004067810 */
/* 0x040fe40007ffe0ff */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f26070 */
/*0070*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f46070 */
/*0080*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fe400078e00ff */
/*0090*/ @!P2 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff07a424 */
/* 0x000fe400078e00ff */
/*00a0*/ @P1 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff021224 */
/* 0x000fe400078e00ff */
/*00b0*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff082224 */
/* 0x000fe400078e00ff */
/*00c0*/ @!P1 IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004049625 */
/* 0x000fc800078e0005 */
/*00d0*/ @!P2 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x000058000606a625 */
/* 0x000fe200078e0007 */
/*00e0*/ @!P1 LDG.E R2, [R4.64] ; /* 0x0000000404029981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @!P2 LDG.E R8, [R6.64] ; /* 0x000000040608a981 */
/* 0x000ee2000c1e1900 */
/*0100*/ ISETP.GT.U32.AND P3, PT, R3.reuse, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x040fe40003f64070 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fe20003f04070 */
/*0120*/ @P1 STS [R3.X4], RZ ; /* 0x000000ff03001388 */
/* 0x000fe80000004800 */
/*0130*/ @P2 STS [R3.X4+0x800], RZ ; /* 0x000800ff03002388 */
/* 0x000fe80000004800 */
/*0140*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x004fe20000004800 */
/*0150*/ ISETP.GT.U32.AND P1, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fe20003f24070 */
/*0160*/ @!P3 FADD R10, R8, R2 ; /* 0x00000002080ab221 */
/* 0x008fc40000000000 */
/*0170*/ @!P2 STS [R3.X4+0x800], R8 ; /* 0x000800080300a388 */
/* 0x000fe80000004800 */
/*0180*/ @!P3 STS [R3.X4], R10 ; /* 0x0000000a0300b388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*01b0*/ @!P0 LDS R5, [R3.X4+0x400] ; /* 0x0004000003058984 */
/* 0x000e240000004800 */
/*01c0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*01d0*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01f0*/ ISETP.GT.U32.AND P0, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f04070 */
/*0200*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R3.X4+0x200] ; /* 0x0002000003059984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0230*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f24070 */
/*0260*/ @!P0 LDS R5, [R3.X4] ; /* 0x0000000003058984 */
/* 0x000fe80000004800 */
/*0270*/ @!P0 LDS R6, [R3.X4+0x100] ; /* 0x0001000003068984 */
/* 0x000e240000004800 */
/*0280*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*0290*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x000fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f04070 */
/*02c0*/ @!P1 LDS R4, [R3.X4] ; /* 0x0000000003049984 */
/* 0x000fe80000004800 */
/*02d0*/ @!P1 LDS R5, [R3.X4+0x80] ; /* 0x0000800003059984 */
/* 0x000e240000004800 */
/*02e0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*02f0*/ @!P1 STS [R3.X4], R4 ; /* 0x0000000403009388 */
/* 0x000fe80000004800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0310*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f24070 */
/*0320*/ @!P0 LDS R2, [R3.X4] ; /* 0x0000000003028984 */
/* 0x000fe80000004800 */
/*0330*/ @!P0 LDS R5, [R3.X4+0x40] ; /* 0x0000400003058984 */
/* 0x000e240000004800 */
/*0340*/ @!P0 FADD R2, R2, R5 ; /* 0x0000000502028221 */
/* 0x001fca0000000000 */
/*0350*/ @!P0 STS [R3.X4], R2 ; /* 0x0000000203008388 */
/* 0x000fe80000004800 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0370*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f04070 */
/*0380*/ @!P1 LDS R5, [R3.X4] ; /* 0x0000000003059984 */
/* 0x000fe80000004800 */
/*0390*/ @!P1 LDS R6, [R3.X4+0x20] ; /* 0x0000200003069984 */
/* 0x000e240000004800 */
/*03a0*/ @!P1 FADD R6, R5, R6 ; /* 0x0000000605069221 */
/* 0x001fca0000000000 */
/*03b0*/ @!P1 STS [R3.X4], R6 ; /* 0x0000000603009388 */
/* 0x000fe80000004800 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03d0*/ ISETP.GT.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f24070 */
/*03e0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000fe80000004800 */
/*03f0*/ @!P0 LDS R5, [R3.X4+0x10] ; /* 0x0000100003058984 */
/* 0x000e240000004800 */
/*0400*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0410*/ @!P0 STS [R3.X4], R4 ; /* 0x0000000403008388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0440*/ @!P1 LDS R2, [R3.X4] ; /* 0x0000000003029984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R5, [R3.X4+0x8] ; /* 0x0000080003059984 */
/* 0x000e240000004800 */
/*0460*/ @!P1 FADD R2, R2, R5 ; /* 0x0000000502029221 */
/* 0x001fca0000000000 */
/*0470*/ @!P1 STS [R3.X4], R2 ; /* 0x0000000203009388 */
/* 0x000fe80000004800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @!P0 LDS R5, [0x4] ; /* 0x00000400ff058984 */
/* 0x000fe80000000800 */
/*04a0*/ @!P0 LDS R6, [R3.X4] ; /* 0x0000000003068984 */
/* 0x000e240000004800 */
/*04b0*/ @!P0 FADD R6, R5, R6 ; /* 0x0000000605068221 */
/* 0x001fca0000000000 */
/*04c0*/ @!P0 STS [R3.X4], R6 ; /* 0x0000000603008388 */
/* 0x0001e80000004800 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ I2F.F64 R4, c[0x0][0x170] ; /* 0x00005c0000047b12 */
/* 0x001e220000201c00 */
/*0500*/ LDS R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000e620000000800 */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0520*/ MUFU.RCP64H R3, R5 ; /* 0x0000000500037308 */
/* 0x001e240000001800 */
/*0530*/ DFMA R6, -R4, R2, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000102 */
/*0540*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0550*/ DFMA R2, R2, R6, R2 ; /* 0x000000060202722b */
/* 0x0012080000000002 */
/*0560*/ F2F.F64.F32 R6, R12 ; /* 0x0000000c00067310 */
/* 0x002e640000201800 */
/*0570*/ DFMA R8, -R4, R2, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000102 */
/*0580*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e4c0000000002 */
/*0590*/ DMUL R2, R6, R8 ; /* 0x0000000806027228 */
/* 0x002e220000000000 */
/*05a0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*05b0*/ DFMA R10, -R4, R2, R6 ; /* 0x00000002040a722b */
/* 0x001e0c0000000106 */
/*05c0*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x001e140000000002 */
/*05d0*/ FFMA R8, RZ, R5, R3 ; /* 0x00000005ff087223 */
/* 0x001fca0000000003 */
/*05e0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*05f0*/ @P0 BRA P1, 0x620 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0600*/ MOV R8, 0x620 ; /* 0x0000062000087802 */
/* 0x000fe40000000f00 */
/*0610*/ CALL.REL.NOINC 0x670 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0620*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x000e220000301000 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0650*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0680*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0690*/ LOP3.LUT R2, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05027812 */
/* 0x040fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff097424 */
/* 0x000fe200078e00ff */
/*06b0*/ LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005107812 */
/* 0x000fe400078ec0ff */
/*06c0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*06d0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*06e0*/ LOP3.LUT R14, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070e7812 */
/* 0x000fc800078ec0ff */
/*06f0*/ ISETP.GE.U32.AND P1, PT, R14, R16, PT ; /* 0x000000100e00720c */
/* 0x000fe20003f26070 */
/*0700*/ @!P0 DMUL R2, R4, 8.98846567431157953865e+307 ; /* 0x7fe0000004028828 */
/* 0x000e220000000000 */
/*0710*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000e */
/*0720*/ SEL R15, R9, 0x63400000, !P1 ; /* 0x63400000090f7807 */
/* 0x000fe40004800000 */
/*0730*/ FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x000fe20003f2e200 */
/*0740*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x001e280000001800 */
/*0750*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe200078ec0ff */
/*0760*/ DFMA R12, R10, -R2, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000802 */
/*0770*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0780*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0790*/ DFMA R10, R12, -R2, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000802 */
/*07a0*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*07b0*/ LOP3.LUT R11, R15, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0f0b7812 */
/* 0x001fe200078ef807 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*07d0*/ @P1 BRA 0x860 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x002fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0800*/ ISETP.GE.U32.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720c */
/* 0x000fc80003f06070 */
/*0810*/ SEL R15, R9, 0x63400000, !P0 ; /* 0x63400000090f7807 */
/* 0x000fc80004000000 */
/*0820*/ LOP3.LUT R15, R15, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000f0f7812 */
/* 0x000fc800078ef807 */
/*0830*/ LOP3.LUT R19, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f137812 */
/* 0x000fcc00078efcff */
/*0840*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*0850*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*0860*/ IADD3 R15, R17, -0x1, RZ ; /* 0xffffffff110f7810 */
/* 0x002fe20007ffe0ff */
/*0870*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*0880*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0890*/ ISETP.GT.U32.AND P0, PT, R15, 0x7feffffe, PT ; /* 0x7feffffe0f00780c */
/* 0x000fc60003f04070 */
/*08a0*/ DFMA R20, R18, -R2, R10 ; /* 0x800000021214722b */
/* 0x001e22000000000a */
/*08b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*08c0*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*08d0*/ @P0 BRA 0xaa0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005077812 */
/* 0x003fc800078ec0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720c */
/* 0x040fe20003f06070 */
/*0900*/ IMAD.IADD R6, R14, 0x1, -R7 ; /* 0x000000010e067824 */
/* 0x000fc600078e0a07 */
/*0910*/ SEL R9, R9, 0x63400000, !P0 ; /* 0x6340000009097807 */
/* 0x000fe40004000000 */
/*0920*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0940*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe400078e0a09 */
/*0950*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0960*/ IADD3 R7, R9, 0x7fe00000, RZ ; /* 0x7fe0000009077810 */
/* 0x000fcc0007ffe0ff */
/*0970*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x000e140000000000 */
/*0980*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0990*/ @P0 BRA 0xbf0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*09a0*/ DFMA R2, R12, -R2, R10 ; /* 0x800000020c02722b */
/* 0x000e22000000000a */
/*09b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*09c0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*09d0*/ LOP3.LUT R5, R3, 0x80000000, R5, 0x48, !PT ; /* 0x8000000003057812 */
/* 0x000fc800078e4805 */
/*09e0*/ LOP3.LUT R7, R5, R7, RZ, 0xfc, !PT ; /* 0x0000000705077212 */
/* 0x000fce00078efcff */
/*09f0*/ @!P0 BRA 0xbf0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a09 */
/*0a10*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*0a20*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0a30*/ IADD3 R9, -R9, -0x43300000, RZ ; /* 0xbcd0000009097810 */
/* 0x000fca0007ffe1ff */
/*0a40*/ DFMA R2, R14, -R2, R12 ; /* 0x800000020e02722b */
/* 0x000e46000000000c */
/*0a50*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x001fce00078e3cff */
/*0a60*/ FSETP.NEU.AND P0, PT, |R3|, R9, PT ; /* 0x000000090300720b */
/* 0x002fc80003f0d200 */
/*0a70*/ FSEL R14, R6, R14, !P0 ; /* 0x0000000e060e7208 */
/* 0x000fe40004000000 */
/*0a80*/ FSEL R15, R5, R15, !P0 ; /* 0x0000000f050f7208 */
/* 0x000fe20004000000 */
/*0a90*/ BRA 0xbf0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0ab0*/ @P0 BRA 0xbd0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0ac0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e1c0003f08000 */
/*0ad0*/ @P0 BRA 0xba0 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0ae0*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0af0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0b10*/ @!P0 BRA 0xbf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b20*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0b30*/ LOP3.LUT R15, R7, 0x80000000, R5, 0x48, !PT ; /* 0x80000000070f7812 */
/* 0x000fe400078e4805 */
/*0b40*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0b50*/ @P0 LOP3.LUT R2, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f020812 */
/* 0x000fe200078efcff */
/*0b60*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*0b70*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0b80*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R2 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0002 */
/*0b90*/ BRA 0xbf0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ba0*/ LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050f7812 */
/* 0x000fe200078efcff */
/*0bb0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*0bc0*/ BRA 0xbf0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT R15, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070f7812 */
/* 0x000fe200078efcff */
/*0be0*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0006 */
/*0bf0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fc400078e000e */
/*0c10*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*0c20*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff3d008007950 */
/* 0x000fec0003c3ffff */
/*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10avg_kernelPfS_i
.globl _Z10avg_kernelPfS_i
.p2align 8
.type _Z10avg_kernelPfS_i,@function
_Z10avg_kernelPfS_i:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s2, s15
s_lshl_b32 s3, s15, 10
s_mov_b32 s7, 0
s_mov_b32 s8, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
v_add_lshl_u32 v1, s7, v0, 2
s_xor_b32 s8, s8, -1
s_movk_i32 s7, 0x200
s_and_not1_b32 vcc_lo, exec_lo, s8
s_mov_b32 s8, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_cbranch_vccz .LBB0_4
.LBB0_2:
v_add3_u32 v1, s3, s7, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_1
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_lshlrev_b32_e32 v1, 2, v0
s_movk_i32 s3, 0x200
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v2, v0
v_cvt_f64_i32_e32 v[0:1], s6
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, v[0:1], v[0:1], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], v[0:1], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[4:5], v[0:1], v[2:3]
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10avg_kernelPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10avg_kernelPfS_i, .Lfunc_end0-_Z10avg_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10avg_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10avg_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00165400_00000000-6_avg_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10avg_kernelPfS_iPfS_i
.type _Z33__device_stub__Z10avg_kernelPfS_iPfS_i, @function
_Z33__device_stub__Z10avg_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10avg_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10avg_kernelPfS_iPfS_i, .-_Z33__device_stub__Z10avg_kernelPfS_iPfS_i
.globl _Z10avg_kernelPfS_i
.type _Z10avg_kernelPfS_i, @function
_Z10avg_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10avg_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10avg_kernelPfS_i, .-_Z10avg_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10avg_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10avg_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "avg_kernel.hip"
.globl _Z25__device_stub__avg_kernelPfS_i # -- Begin function _Z25__device_stub__avg_kernelPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__avg_kernelPfS_i,@function
_Z25__device_stub__avg_kernelPfS_i: # @_Z25__device_stub__avg_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10avg_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__avg_kernelPfS_i, .Lfunc_end0-_Z25__device_stub__avg_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10avg_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10avg_kernelPfS_i,@object # @_Z10avg_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z10avg_kernelPfS_i
.p2align 3, 0x0
_Z10avg_kernelPfS_i:
.quad _Z25__device_stub__avg_kernelPfS_i
.size _Z10avg_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10avg_kernelPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__avg_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10avg_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
cudaMalloc((void**)&d_a,memSize);
cudaMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
cudaMemcpy(d_a, h_a,memSize, cudaMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
cudaMemcpy(h_c,d_b,memSize, cudaMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} | code for sm_80
Function : _Z15multiply_devicePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0070*/ @P0 BRA 0x100 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fcc00000001ff */
/*0090*/ IMAD R2, R6, c[0x0][0x170], R7 ; /* 0x00005c0006027a24 */
/* 0x001fe200078e0207 */
/*00a0*/ IADD3 R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a10 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0205 */
/*00c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06270 */
/*00d0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101b04 */
/*00e0*/ @!P0 BRA 0x90 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0110*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fc40000000f00 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R0, R5.reuse, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0160*/ IMAD.WIDE R8, R6, R9, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x001fe200078e0209 */
/*0170*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe40000000f00 */
/*0180*/ IADD3 R2, -R5, c[0x0][0x170], RZ ; /* 0x00005c0005027a10 */
/* 0x000fce0007ffe1ff */
/*0190*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*01a0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x001fe2000001ff00 */
/*01b0*/ @!P1 BRA 0xc80 ; /* 0x00000ac000009947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f04270 */
/*01d0*/ HFMA2.MMA R27, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff1b7435 */
/* 0x000fe200000001ff */
/*01e0*/ IMAD R26, R4, c[0x0][0xc], R7 ; /* 0x00000300041a7a24 */
/* 0x000fe200078e0207 */
/*01f0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0200*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0210*/ MOV R28, R2 ; /* 0x00000002001c7202 */
/* 0x000fc40000000f00 */
/*0220*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe40000000f00 */
/*0240*/ IMAD.WIDE R26, R26, R27, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fe400078e021b */
/*0250*/ @!P0 BRA 0xaf0 ; /* 0x0000089000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.AND P2, PT, R28, 0xc, PT ; /* 0x0000000c1c00780c */
/* 0x000fe40003f44270 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0280*/ @!P2 BRA 0x7f0 ; /* 0x000005600000a947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*02b0*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0000a8000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0002a2000c1e1b00 */
/*02d0*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x000fc800078e021a */
/*02e0*/ IMAD.WIDE R20, R29.reuse, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x040fe200078e020c */
/*02f0*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000728000c1e1b00 */
/*0300*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000b22000c1e1b00 */
/*0310*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0320*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*0330*/ IMAD.WIDE R12, R29, 0x8, R18 ; /* 0x000000081d0c7825 */
/* 0x002fc800078e0212 */
/*0340*/ IMAD.WIDE R26, R29, 0x8, R20 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e0214 */
/*0350*/ DFMA R16, R10, R14, R16 ; /* 0x0000000e0a10722b */
/* 0x0041240000000010 */
/*0360*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*0380*/ DFMA R24, R24, R22, R16 ; /* 0x000000161818722b */
/* 0x0106860000000010 */
/*0390*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x008728000c1e1b00 */
/*03a0*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000b22000c1e1b00 */
/*03b0*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x008fc800078e021a */
/*03c0*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x020fc800078e020c */
/*03d0*/ IMAD.WIDE R20, R29, 0x8, R26 ; /* 0x000000081d147825 */
/* 0x002fc800078e021a */
/*03e0*/ IMAD.WIDE R18, R29, 0x8, R12 ; /* 0x000000081d127825 */
/* 0x001fe200078e020c */
/*03f0*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0400*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0010a8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0002a2000c1e1b00 */
/*0420*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0430*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*0450*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0460*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*0470*/ IMAD.WIDE R26, R29, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x002fc800078e0212 */
/*0480*/ IMAD.WIDE R12, R29, 0x8, R20 ; /* 0x000000081d0c7825 */
/* 0x001fe200078e0214 */
/*0490*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*04a0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*04b0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*04c0*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*04d0*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x008728000c1e1b00 */
/*04e0*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000b22000c1e1b00 */
/*04f0*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x008fc800078e020c */
/*0500*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x020fc800078e021a */
/*0510*/ IMAD.WIDE R20, R29, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x002fc800078e020c */
/*0520*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x001fe200078e021a */
/*0530*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0540*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x0010a8000c1e1b00 */
/*0550*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x0002a2000c1e1b00 */
/*0560*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0570*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*0580*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*0590*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*05a0*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*05b0*/ IMAD.WIDE R26, R29, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x001fc800078e0212 */
/*05c0*/ IMAD.WIDE R12, R29, 0x8, R20 ; /* 0x000000081d0c7825 */
/* 0x002fe200078e0214 */
/*05d0*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*05e0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*05f0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*0600*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0610*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x008728000c1e1b00 */
/*0620*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000b22000c1e1b00 */
/*0630*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x008fc800078e020c */
/*0640*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x020fc800078e021a */
/*0650*/ IMAD.WIDE R20, R29, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x002fc800078e020c */
/*0660*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x001fe200078e021a */
/*0670*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0680*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x0010a8000c1e1b00 */
/*0690*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1b00 */
/*06a0*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0102860000000018 */
/*06b0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x0022e8000c1e1b00 */
/*06c0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0008e2000c1e1b00 */
/*06d0*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x002fc800078e0212 */
/*06e0*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x010fc800078e0214 */
/*06f0*/ IMAD.WIDE R26, R29.reuse, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x041fe200078e0212 */
/*0700*/ DFMA R12, R14, R10, R24 ; /* 0x0000000a0e0c722b */
/* 0x0040e40000000018 */
/*0710*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x001ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R10, R29, 0x8, R20 ; /* 0x000000081d0a7825 */
/* 0x000fc600078e0214 */
/*0730*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ DFMA R22, R22, R16, R12 ; /* 0x000000101616722b */
/* 0x008086000000000c */
/*0750*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x001ee8000c1e1b00 */
/*0760*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x0000e2000c1e1b00 */
/*0770*/ IADD3 R28, R28, -0x10, RZ ; /* 0xfffffff01c1c7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.GT.AND P2, PT, R28, 0xc, PT ; /* 0x0000000c1c00780c */
/* 0x000fe20003f44270 */
/*07a0*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*07b0*/ DFMA R14, R24, R14, R22 ; /* 0x0000000e180e722b */
/* 0x004ecc0000000016 */
/*07c0*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x008064000000000e */
/*07d0*/ IMAD.WIDE R12, R29, 0x8, R10 ; /* 0x000000081d0c7825 */
/* 0x001fc600078e020a */
/*07e0*/ @P2 BRA 0x2a0 ; /* 0xfffffab000002947 */
/* 0x002fea000383ffff */
/*07f0*/ ISETP.GT.AND P2, PT, R28, 0x4, PT ; /* 0x000000041c00780c */
/* 0x000fda0003f44270 */
/*0800*/ @!P2 BRA 0xad0 ; /* 0x000002c00000a947 */
/* 0x000fea0003800000 */
/*0810*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*0820*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0000a8000c1e1b00 */
/*0830*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0002a2000c1e1b00 */
/*0840*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x000fc800078e021a */
/*0850*/ IMAD.WIDE R20, R29.reuse, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x040fe200078e020c */
/*0860*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000728000c1e1b00 */
/*0870*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000b22000c1e1b00 */
/*0880*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0890*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*08a0*/ IMAD.WIDE R12, R29, 0x8, R18 ; /* 0x000000081d0c7825 */
/* 0x002fc800078e0212 */
/*08b0*/ IMAD.WIDE R26, R29, 0x8, R20 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e0214 */
/*08c0*/ DFMA R16, R10, R14, R16 ; /* 0x0000000e0a10722b */
/* 0x0041240000000010 */
/*08d0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*08e0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*08f0*/ DFMA R24, R24, R22, R16 ; /* 0x000000161818722b */
/* 0x0106860000000010 */
/*0900*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x008728000c1e1b00 */
/*0910*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000b22000c1e1b00 */
/*0920*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x008fc800078e021a */
/*0930*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x020fc800078e020c */
/*0940*/ IMAD.WIDE R20, R29, 0x8, R26 ; /* 0x000000081d147825 */
/* 0x002fc800078e021a */
/*0950*/ IMAD.WIDE R18, R29, 0x8, R12 ; /* 0x000000081d127825 */
/* 0x001fe200078e020c */
/*0960*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0970*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0010a8000c1e1b00 */
/*0980*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0002a2000c1e1b00 */
/*0990*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*09a0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*09b0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*09c0*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*09d0*/ IMAD.WIDE R20, R29.reuse, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x060fe200078e0214 */
/*09e0*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x001ee6000c1e1b00 */
/*09f0*/ IMAD.WIDE R26, R29.reuse, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x042fe200078e0212 */
/*0a00*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0a10*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ IMAD.WIDE R10, R29, 0x8, R20 ; /* 0x000000081d0a7825 */
/* 0x000fc600078e0214 */
/*0a30*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0100e40000000018 */
/*0a40*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x001ea8000c1e1b00 */
/*0a50*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0000a2000c1e1b00 */
/*0a60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a70*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R28, R28, -0x8, RZ ; /* 0xfffffff81c1c7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*0aa0*/ DFMA R12, R12, R14, R24 ; /* 0x0000000e0c0c722b */
/* 0x008e8c0000000018 */
/*0ab0*/ DFMA R16, R22, R16, R12 ; /* 0x000000101610722b */
/* 0x004064000000000c */
/*0ac0*/ IMAD.WIDE R12, R29, 0x8, R10 ; /* 0x000000081d0c7825 */
/* 0x001fc800078e020a */
/*0ad0*/ ISETP.NE.OR P0, PT, R28, RZ, P0 ; /* 0x000000ff1c00720c */
/* 0x002fda0000705670 */
/*0ae0*/ @!P0 BRA 0xc80 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*0b00*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x0000a8000c1e1b00 */
/*0b10*/ LDG.E.64 R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x0002a2000c1e1b00 */
/*0b20*/ IMAD.WIDE R10, R29, 0x8, R26 ; /* 0x000000081d0a7825 */
/* 0x000fc800078e021a */
/*0b30*/ IMAD.WIDE R24, R29.reuse, 0x8, R12 ; /* 0x000000081d187825 */
/* 0x040fe400078e020c */
/*0b40*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x0022e8000c1e1b00 */
/*0b50*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x0008e2000c1e1b00 */
/*0b60*/ IMAD.WIDE R10, R29, 0x8, R10 ; /* 0x000000081d0a7825 */
/* 0x002fc800078e020a */
/*0b70*/ IMAD.WIDE R24, R29, 0x8, R24 ; /* 0x000000081d187825 */
/* 0x010fc800078e0218 */
/*0b80*/ IMAD.WIDE R26, R29, 0x8, R10 ; /* 0x000000081d1a7825 */
/* 0x001fc800078e020a */
/*0b90*/ IMAD.WIDE R22, R29, 0x8, R24 ; /* 0x000000081d167825 */
/* 0x000fe200078e0218 */
/*0ba0*/ DFMA R16, R20, R18, R16 ; /* 0x000000121410722b */
/* 0x0040e40000000010 */
/*0bb0*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x001ea8000c1e1b00 */
/*0bc0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ DFMA R14, R12, R14, R16 ; /* 0x0000000e0c0e722b */
/* 0x0080860000000010 */
/*0be0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x001ee8000c1e1b00 */
/*0bf0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x0000e2000c1e1b00 */
/*0c00*/ IADD3 R28, R28, -0x4, RZ ; /* 0xfffffffc1c1c7810 */
/* 0x000fe40007ffe0ff */
/*0c10*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ ISETP.NE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003f05270 */
/*0c30*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*0c40*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x004ecc000000000e */
/*0c50*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x008064000000000e */
/*0c60*/ IMAD.WIDE R12, R29, 0x8, R22 ; /* 0x000000081d0c7825 */
/* 0x001fc600078e0216 */
/*0c70*/ @P0 BRA 0xaf0 ; /* 0xfffffe7000000947 */
/* 0x002fea000383ffff */
/*0c80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0c90*/ @!P0 BRA 0xe60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ MOV R10, 0x8 ; /* 0x00000008000a7802 */
/* 0x000fe20000000f00 */
/*0cb0*/ IMAD R15, R0.reuse, c[0x0][0x170], R3 ; /* 0x00005c00000f7a24 */
/* 0x040fe400078e0203 */
/*0cc0*/ IMAD R13, R0, c[0x0][0x170], R6 ; /* 0x00005c00000d7a24 */
/* 0x000fe400078e0206 */
/*0cd0*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e020a */
/*0ce0*/ IMAD.WIDE R12, R13, R10, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e020a */
/*0cf0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0d00*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0d10*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0d20*/ DFMA R16, R14, R12, R16 ; /* 0x0000000c0e10722b */
/* 0x0040580000000010 */
/*0d30*/ @!P0 BRA 0xe60 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0d40*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f05270 */
/*0d50*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fca0000000f00 */
/*0d60*/ IMAD R0, R0, R11, c[0x0][0x170] ; /* 0x00005c0000007624 */
/* 0x000fca00078e020b */
/*0d70*/ IADD3 R13, R0.reuse, R3, RZ ; /* 0x00000003000d7210 */
/* 0x041fe40007ffe0ff */
/*0d80*/ IADD3 R15, R0.reuse, R6, RZ ; /* 0x00000006000f7210 */
/* 0x040fe40007ffe0ff */
/*0d90*/ @P0 IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000000a10 */
/* 0x000fe20007ffe0ff */
/*0da0*/ IMAD.WIDE R12, R13, R10, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc600078e020a */
/*0db0*/ @P0 IADD3 R19, R0.reuse, R3, RZ ; /* 0x0000000300130210 */
/* 0x040fe20007ffe0ff */
/*0dc0*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e020a */
/*0dd0*/ @P0 IADD3 R11, R0, R6, RZ ; /* 0x00000006000b0210 */
/* 0x000fe20007ffe0ff */
/*0de0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0df0*/ @P0 IMAD.WIDE R18, R19, R10.reuse, c[0x0][0x160] ; /* 0x0000580013120625 */
/* 0x080fe400078e020a */
/*0e00*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0e10*/ @P0 IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a0625 */
/* 0x000fe400078e020a */
/*0e20*/ @P0 LDG.E.64 R18, [R18.64] ; /* 0x0000000412120981 */
/* 0x000ee8000c1e1b00 */
/*0e30*/ @P0 LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a0981 */
/* 0x000ee2000c1e1b00 */
/*0e40*/ DFMA R16, R12, R14, R16 ; /* 0x0000000e0c10722b */
/* 0x006ecc0000000010 */
/*0e50*/ @P0 DFMA R16, R18, R10, R16 ; /* 0x0000000a1210022b */
/* 0x0080480000000010 */
/*0e60*/ IMAD R10, R6, c[0x0][0x170], R3 ; /* 0x00005c00060a7a24 */
/* 0x001fe200078e0203 */
/*0e70*/ IADD3 R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a10 */
/* 0x000fe40007ffe0ff */
/*0e80*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fe40000000f00 */
/*0e90*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06270 */
/*0ea0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe20007ffe0ff */
/*0eb0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e020b */
/*0ec0*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0021ea000c101b04 */
/*0ed0*/ @!P0 BRA 0x190 ; /* 0xfffff2b000008947 */
/* 0x000fea000383ffff */
/*0ee0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
cudaMalloc((void**)&d_a,memSize);
cudaMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
cudaMemcpy(d_a, h_a,memSize, cudaMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
cudaMemcpy(h_c,d_b,memSize, cudaMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} | .file "tmpxft_000c4d33_00000000-6_serial_mult1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5randdv
.type _Z5randdv, @function
_Z5randdv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addsd .LC1(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5randdv, .-_Z5randdv
.globl _Z15multiply_serialPdS_i
.type _Z15multiply_serialPdS_i, @function
_Z15multiply_serialPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r8
movq %rsi, %r9
movl %edx, %esi
movslq %edx, %rbx
leaq 8(,%rbx,8), %rbp
leaq 0(,%rbx,8), %rdi
movq %rbx, %r10
movl $0, %r11d
.L7:
movq %r11, %rcx
negq %rcx
.L10:
movq %r8, %rax
pxor %xmm1, %xmm1
movl $0, %edx
.L8:
pxor %xmm0, %xmm0
cvtsd2ss (%rax), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss (%rax,%rcx,8), %xmm2
mulss %xmm2, %xmm0
addss %xmm0, %xmm1
addl $1, %edx
addq %rdi, %rax
cmpl %edx, %esi
jne .L8
cvtss2sd %xmm1, %xmm1
movsd %xmm1, (%r9,%rcx,8)
addq $1, %rcx
cmpq %r10, %rcx
jne .L10
addq $1, %r11
addq %rbp, %r9
subq $1, %r10
addq $8, %r8
cmpq %rbx, %r11
jne .L7
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15multiply_serialPdS_i, .-_Z15multiply_serialPdS_i
.globl _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
.type _Z38__device_stub__Z15multiply_devicePdS_iPdS_i, @function
_Z38__device_stub__Z15multiply_devicePdS_iPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15multiply_devicePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z15multiply_devicePdS_iPdS_i, .-_Z38__device_stub__Z15multiply_devicePdS_iPdS_i
.globl _Z15multiply_devicePdS_i
.type _Z15multiply_devicePdS_i, @function
_Z15multiply_devicePdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15multiply_devicePdS_i, .-_Z15multiply_devicePdS_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $72, %edi
call malloc@PLT
movq %rax, %r13
movl $72, %edi
call malloc@PLT
movq %rax, %r15
movl $72, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
movq %r13, %rbp
movl $0, %r12d
jmp .L25
.L32:
addq $3, %r12
addq $24, %rbp
cmpq $9, %r12
je .L27
.L25:
movl $0, %ebx
.L26:
call _Z5randdv
movsd %xmm0, 0(%rbp,%rbx,8)
addq $1, %rbx
cmpq $3, %rbx
jne .L26
jmp .L32
.L27:
movl $3, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z15multiply_serialPdS_i
movl $1, %ecx
movl $72, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl $2, %ecx
movl $72, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $3, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
jmp .L28
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z15multiply_devicePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15multiply_devicePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
cudaMalloc((void**)&d_a,memSize);
cudaMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
cudaMemcpy(d_a, h_a,memSize, cudaMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
cudaMemcpy(h_c,d_b,memSize, cudaMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
hipMalloc((void**)&d_a,memSize);
hipMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
hipMemcpy(d_a, h_a,memSize, hipMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
hipMemcpy(h_c,d_b,memSize, hipMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
hipMalloc((void**)&d_a,memSize);
hipMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
hipMemcpy(d_a, h_a,memSize, hipMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
hipMemcpy(h_c,d_b,memSize, hipMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15multiply_devicePdS_i
.globl _Z15multiply_devicePdS_i
.p2align 8
.type _Z15multiply_devicePdS_i,@function
_Z15multiply_devicePdS_i:
s_load_b32 s8, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s8
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_cmp_gt_i32 s8, 0
v_mul_lo_u32 v5, v0, s8
s_cselect_b32 s0, -1, 0
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v1, 0, 1, s0
s_ashr_i32 s9, s8, 31
s_mov_b32 s2, s15
s_lshl_b64 s[10:11], s[8:9], 3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_3:
v_add_nc_u32_e32 v6, s2, v5
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s2, s8
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b64 v[6:7], v[3:4], off
s_cbranch_scc0 .LBB0_7
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v3, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, v0
s_lshl_b64 s[12:13], s[2:3], 3
s_mov_b32 s3, s8
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
.p2align 6
.LBB0_6:
v_lshlrev_b64 v[6:7], 3, v[1:2]
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[8:9], v2, s[12:13]
global_load_b64 v[6:7], v[6:7], off
s_add_u32 s12, s12, s10
s_addc_u32 s13, s13, s11
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[6:7], v[8:9], v[3:4]
s_cbranch_scc1 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15multiply_devicePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15multiply_devicePdS_i, .Lfunc_end0-_Z15multiply_devicePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15multiply_devicePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15multiply_devicePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
// Function to generate random number between 1 and 2
double randd() {
return (double)rand() / (RAND_MAX) + 1.0;
}
//Serial function To multiply matrix with it's transpose
void multiply_serial(double *h_a,double *h_b, int dim)
{
int i,j,k;
float a, b, sum;
//Start the computation of matrix with it's transpose.
for(i=0; i<dim; i++)
{
for(j=0; j<dim; j++)
{
sum = 0;
for(k=0; k<dim; k++)
{
a =h_a[(k *dim)+i];
b =h_a[k*dim+j ]; // Interchange indices to get the transpose
sum = sum +( a * b);
}
h_b[ i * dim + j ] = sum; //Assign teh value to Matrix B's element.
}
}
}
/*
* The kernel function. Runs on the device(GPU).
* d_a - Source matrix.
* d_b - Destination matrix.
* dim - Dimension.
*/
__global__ void multiply_device (double *d_a, double *d_b,int dim) {
//Declaration of required variables.
double a, b, sum;
//Retrive the thread and block specific information.
int i = threadIdx.x,j,k;
// Begine Matrix Computation.
for (j = blockIdx.x; j < dim; j += gridDim.x) {
sum = 0;
for(k=0; k<dim; k++) {
a =d_a[k *dim+i];
b =d_a[k*dim+j];
sum = sum + a * b;
}
d_b[ i * dim + j ] = sum;
}
}
//Main function which invokes serial & parallel multiplication functions.
int main()
{
//Declare the required pointers.
double *h_a; //Pointer1 for host memory
double *h_b; //Pointer2 for host memory
double *h_c; //Pointer3 for host memory
double *d_a; //Pointer1 for device memory
double *d_b; //Pointer2 for device memory
//dim of vector
int dimA = 3;
int i,j;
//define thread hierarchy
int nblocks = 4;
int tpb = 1024;
//allocate host and device memory.
size_t memSize;
//Define the memSize and allocate required memory.
memSize = dimA*dimA * sizeof(double);
h_a = (double*)malloc(dimA*dimA*sizeof(double));
h_b = (double*)malloc(dimA*dimA*sizeof(double));
h_c = (double*)malloc(dimA*dimA*sizeof(double));
//h_b = (double*)malloc(memSize);
//cudaMalloc((void**)&h_a,memSize);
hipMalloc((void**)&d_a,memSize);
hipMalloc((void**)&d_b,memSize);
//Tested the program works fine for 3*3 matrix.
//So we find many print statements.
//initialize host array
//printf("Initialising host array\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
*(h_a+(i * dimA) + j)= randd();
//printf("%lf ", *(h_a+(i * dimA) + j));
}
//printf("\n");
}
//printf("'\n");
//Call the Serial function to multiply Matrices.
multiply_serial(h_a,h_b,dimA);
//printf("Serial output is\n");
/*for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*((h_b+i*dimA)+j));
}
printf("\n");
}*/
//printf("Copying to device");
//Copy contents to device
hipMemcpy(d_a, h_a,memSize, hipMemcpyHostToDevice);
//printf("Launching kernel");
//Launch kernel
dim3 dimGrid(nblocks);
dim3 dimBlock(tpb);
multiply_device<<<dimGrid,dimBlock>>>(d_a,d_b,dimA);
//get the output
hipMemcpy(h_c,d_b,memSize, hipMemcpyDeviceToHost);
// Print the ouput(i.e final result after multiplication)
/*printf("Parallel output is\n");
for(i=0;i<dimA;i++)
{
for(j=0;j<dimA;j++)
{
printf("%lf ",*(h_c+i*dimA+j));
}
printf("\n");
}*/
//free up the allocated memory
free(h_a);
free(h_b);
free(h_c);
//free(d_a);
//free(d_b);
return 0;
} | .text
.file "serial_mult1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5randdv
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z5randdv
.p2align 4, 0x90
.type _Z5randdv,@function
_Z5randdv: # @_Z5randdv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd .LCPI0_1(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5randdv, .Lfunc_end0-_Z5randdv
.cfi_endproc
# -- End function
.globl _Z15multiply_serialPdS_i # -- Begin function _Z15multiply_serialPdS_i
.p2align 4, 0x90
.type _Z15multiply_serialPdS_i,@function
_Z15multiply_serialPdS_i: # @_Z15multiply_serialPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_8
# %bb.1: # %.preheader28.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movq %r8, %r9
imulq %rax, %r9
leaq (%rsi,%r9,8), %r9
xorl %r10d, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorps %xmm0, %xmm0
movq %rax, %rbx
movq %rdi, %r14
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r14,%rdx), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd (%r14,%r10), %xmm2 # xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
mulss %xmm1, %xmm2
addss %xmm2, %xmm0
addq %rcx, %r14
decq %rbx
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%r11,8)
incq %r11
addq $8, %r10
cmpq %rax, %r11
jne .LBB1_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB1_2 Depth=1
incq %r8
addq $8, %rdx
cmpq %rax, %r8
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_8: # %._crit_edge34
retq
.Lfunc_end1:
.size _Z15multiply_serialPdS_i, .Lfunc_end1-_Z15multiply_serialPdS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__multiply_devicePdS_i # -- Begin function _Z30__device_stub__multiply_devicePdS_i
.p2align 4, 0x90
.type _Z30__device_stub__multiply_devicePdS_i,@function
_Z30__device_stub__multiply_devicePdS_i: # @_Z30__device_stub__multiply_devicePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15multiply_devicePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__multiply_devicePdS_i, .Lfunc_end2-_Z30__device_stub__multiply_devicePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $72, %edi
callq malloc
movq %rax, %rbx
movl $72, %edi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r13,8)
incq %r13
cmpq $3, %r13
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $24, %r12
cmpq $3, %r15
jne .LBB3_1
# %bb.4: # %_Z15multiply_serialPdS_i.exit
movq 24(%rsp), %rdi
movl $72, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 1020(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $3, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15multiply_devicePdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 16(%rsp), %rsi
movl $72, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15multiply_devicePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15multiply_devicePdS_i,@object # @_Z15multiply_devicePdS_i
.section .rodata,"a",@progbits
.globl _Z15multiply_devicePdS_i
.p2align 3, 0x0
_Z15multiply_devicePdS_i:
.quad _Z30__device_stub__multiply_devicePdS_i
.size _Z15multiply_devicePdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15multiply_devicePdS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__multiply_devicePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15multiply_devicePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15multiply_devicePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0070*/ @P0 BRA 0x100 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fcc00000001ff */
/*0090*/ IMAD R2, R6, c[0x0][0x170], R7 ; /* 0x00005c0006027a24 */
/* 0x001fe200078e0207 */
/*00a0*/ IADD3 R7, R7, c[0x0][0xc], RZ ; /* 0x0000030007077a10 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0205 */
/*00c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06270 */
/*00d0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101b04 */
/*00e0*/ @!P0 BRA 0x90 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0110*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fc40000000f00 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R0, R5.reuse, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*0160*/ IMAD.WIDE R8, R6, R9, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x001fe200078e0209 */
/*0170*/ MOV R3, R7 ; /* 0x0000000700037202 */
/* 0x000fe40000000f00 */
/*0180*/ IADD3 R2, -R5, c[0x0][0x170], RZ ; /* 0x00005c0005027a10 */
/* 0x000fce0007ffe1ff */
/*0190*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*01a0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x001fe2000001ff00 */
/*01b0*/ @!P1 BRA 0xc80 ; /* 0x00000ac000009947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f04270 */
/*01d0*/ HFMA2.MMA R27, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff1b7435 */
/* 0x000fe200000001ff */
/*01e0*/ IMAD R26, R4, c[0x0][0xc], R7 ; /* 0x00000300041a7a24 */
/* 0x000fe200078e0207 */
/*01f0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0200*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0210*/ MOV R28, R2 ; /* 0x00000002001c7202 */
/* 0x000fc40000000f00 */
/*0220*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe40000000f00 */
/*0240*/ IMAD.WIDE R26, R26, R27, c[0x0][0x160] ; /* 0x000058001a1a7625 */
/* 0x000fe400078e021b */
/*0250*/ @!P0 BRA 0xaf0 ; /* 0x0000089000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.AND P2, PT, R28, 0xc, PT ; /* 0x0000000c1c00780c */
/* 0x000fe40003f44270 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0280*/ @!P2 BRA 0x7f0 ; /* 0x000005600000a947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*02b0*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0000a8000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0002a2000c1e1b00 */
/*02d0*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x000fc800078e021a */
/*02e0*/ IMAD.WIDE R20, R29.reuse, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x040fe200078e020c */
/*02f0*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000728000c1e1b00 */
/*0300*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000b22000c1e1b00 */
/*0310*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0320*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*0330*/ IMAD.WIDE R12, R29, 0x8, R18 ; /* 0x000000081d0c7825 */
/* 0x002fc800078e0212 */
/*0340*/ IMAD.WIDE R26, R29, 0x8, R20 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e0214 */
/*0350*/ DFMA R16, R10, R14, R16 ; /* 0x0000000e0a10722b */
/* 0x0041240000000010 */
/*0360*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*0380*/ DFMA R24, R24, R22, R16 ; /* 0x000000161818722b */
/* 0x0106860000000010 */
/*0390*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x008728000c1e1b00 */
/*03a0*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000b22000c1e1b00 */
/*03b0*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x008fc800078e021a */
/*03c0*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x020fc800078e020c */
/*03d0*/ IMAD.WIDE R20, R29, 0x8, R26 ; /* 0x000000081d147825 */
/* 0x002fc800078e021a */
/*03e0*/ IMAD.WIDE R18, R29, 0x8, R12 ; /* 0x000000081d127825 */
/* 0x001fe200078e020c */
/*03f0*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0400*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0010a8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0002a2000c1e1b00 */
/*0420*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0430*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*0450*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0460*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*0470*/ IMAD.WIDE R26, R29, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x002fc800078e0212 */
/*0480*/ IMAD.WIDE R12, R29, 0x8, R20 ; /* 0x000000081d0c7825 */
/* 0x001fe200078e0214 */
/*0490*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*04a0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*04b0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*04c0*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*04d0*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x008728000c1e1b00 */
/*04e0*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000b22000c1e1b00 */
/*04f0*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x008fc800078e020c */
/*0500*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x020fc800078e021a */
/*0510*/ IMAD.WIDE R20, R29, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x002fc800078e020c */
/*0520*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x001fe200078e021a */
/*0530*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0540*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x0010a8000c1e1b00 */
/*0550*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x0002a2000c1e1b00 */
/*0560*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0570*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*0580*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*0590*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*05a0*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*05b0*/ IMAD.WIDE R26, R29, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x001fc800078e0212 */
/*05c0*/ IMAD.WIDE R12, R29, 0x8, R20 ; /* 0x000000081d0c7825 */
/* 0x002fe200078e0214 */
/*05d0*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*05e0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*05f0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*0600*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*0610*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x008728000c1e1b00 */
/*0620*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000b22000c1e1b00 */
/*0630*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x008fc800078e020c */
/*0640*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x020fc800078e021a */
/*0650*/ IMAD.WIDE R20, R29, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x002fc800078e020c */
/*0660*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x001fe200078e021a */
/*0670*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0680*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x0010a8000c1e1b00 */
/*0690*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1b00 */
/*06a0*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0102860000000018 */
/*06b0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x0022e8000c1e1b00 */
/*06c0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0008e2000c1e1b00 */
/*06d0*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x002fc800078e0212 */
/*06e0*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x010fc800078e0214 */
/*06f0*/ IMAD.WIDE R26, R29.reuse, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x041fe200078e0212 */
/*0700*/ DFMA R12, R14, R10, R24 ; /* 0x0000000a0e0c722b */
/* 0x0040e40000000018 */
/*0710*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x001ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R10, R29, 0x8, R20 ; /* 0x000000081d0a7825 */
/* 0x000fc600078e0214 */
/*0730*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ DFMA R22, R22, R16, R12 ; /* 0x000000101616722b */
/* 0x008086000000000c */
/*0750*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x001ee8000c1e1b00 */
/*0760*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x0000e2000c1e1b00 */
/*0770*/ IADD3 R28, R28, -0x10, RZ ; /* 0xfffffff01c1c7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.GT.AND P2, PT, R28, 0xc, PT ; /* 0x0000000c1c00780c */
/* 0x000fe20003f44270 */
/*07a0*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*07b0*/ DFMA R14, R24, R14, R22 ; /* 0x0000000e180e722b */
/* 0x004ecc0000000016 */
/*07c0*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x008064000000000e */
/*07d0*/ IMAD.WIDE R12, R29, 0x8, R10 ; /* 0x000000081d0c7825 */
/* 0x001fc600078e020a */
/*07e0*/ @P2 BRA 0x2a0 ; /* 0xfffffab000002947 */
/* 0x002fea000383ffff */
/*07f0*/ ISETP.GT.AND P2, PT, R28, 0x4, PT ; /* 0x000000041c00780c */
/* 0x000fda0003f44270 */
/*0800*/ @!P2 BRA 0xad0 ; /* 0x000002c00000a947 */
/* 0x000fea0003800000 */
/*0810*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*0820*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0000a8000c1e1b00 */
/*0830*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0002a2000c1e1b00 */
/*0840*/ IMAD.WIDE R18, R29, 0x8, R26 ; /* 0x000000081d127825 */
/* 0x000fc800078e021a */
/*0850*/ IMAD.WIDE R20, R29.reuse, 0x8, R12 ; /* 0x000000081d147825 */
/* 0x040fe200078e020c */
/*0860*/ LDG.E.64 R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000728000c1e1b00 */
/*0870*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000b22000c1e1b00 */
/*0880*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*0890*/ IMAD.WIDE R20, R29, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x020fc800078e0214 */
/*08a0*/ IMAD.WIDE R12, R29, 0x8, R18 ; /* 0x000000081d0c7825 */
/* 0x002fc800078e0212 */
/*08b0*/ IMAD.WIDE R26, R29, 0x8, R20 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e0214 */
/*08c0*/ DFMA R16, R10, R14, R16 ; /* 0x0000000e0a10722b */
/* 0x0041240000000010 */
/*08d0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x0010a8000c1e1b00 */
/*08e0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0002a2000c1e1b00 */
/*08f0*/ DFMA R24, R24, R22, R16 ; /* 0x000000161818722b */
/* 0x0106860000000010 */
/*0900*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x008728000c1e1b00 */
/*0910*/ LDG.E.64 R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000b22000c1e1b00 */
/*0920*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x008fc800078e021a */
/*0930*/ IMAD.WIDE R12, R29, 0x8, R12 ; /* 0x000000081d0c7825 */
/* 0x020fc800078e020c */
/*0940*/ IMAD.WIDE R20, R29, 0x8, R26 ; /* 0x000000081d147825 */
/* 0x002fc800078e021a */
/*0950*/ IMAD.WIDE R18, R29, 0x8, R12 ; /* 0x000000081d127825 */
/* 0x001fe200078e020c */
/*0960*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0970*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0010a8000c1e1b00 */
/*0980*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x0002a2000c1e1b00 */
/*0990*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0106860000000018 */
/*09a0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x008728000c1e1b00 */
/*09b0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000b22000c1e1b00 */
/*09c0*/ IMAD.WIDE R18, R29, 0x8, R18 ; /* 0x000000081d127825 */
/* 0x008fc800078e0212 */
/*09d0*/ IMAD.WIDE R20, R29.reuse, 0x8, R20 ; /* 0x000000081d147825 */
/* 0x060fe200078e0214 */
/*09e0*/ LDG.E.64 R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x001ee6000c1e1b00 */
/*09f0*/ IMAD.WIDE R26, R29.reuse, 0x8, R18 ; /* 0x000000081d1a7825 */
/* 0x042fe200078e0212 */
/*0a00*/ DFMA R24, R14, R10, R24 ; /* 0x0000000a0e18722b */
/* 0x0041240000000018 */
/*0a10*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ IMAD.WIDE R10, R29, 0x8, R20 ; /* 0x000000081d0a7825 */
/* 0x000fc600078e0214 */
/*0a30*/ DFMA R24, R22, R16, R24 ; /* 0x000000101618722b */
/* 0x0100e40000000018 */
/*0a40*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x001ea8000c1e1b00 */
/*0a50*/ LDG.E.64 R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0000a2000c1e1b00 */
/*0a60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a70*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R28, R28, -0x8, RZ ; /* 0xfffffff81c1c7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*0aa0*/ DFMA R12, R12, R14, R24 ; /* 0x0000000e0c0c722b */
/* 0x008e8c0000000018 */
/*0ab0*/ DFMA R16, R22, R16, R12 ; /* 0x000000101610722b */
/* 0x004064000000000c */
/*0ac0*/ IMAD.WIDE R12, R29, 0x8, R10 ; /* 0x000000081d0c7825 */
/* 0x001fc800078e020a */
/*0ad0*/ ISETP.NE.OR P0, PT, R28, RZ, P0 ; /* 0x000000ff1c00720c */
/* 0x002fda0000705670 */
/*0ae0*/ @!P0 BRA 0xc80 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R29, c[0x0][0x170] ; /* 0x00005c00001d7a02 */
/* 0x000fe20000000f00 */
/*0b00*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x0000a8000c1e1b00 */
/*0b10*/ LDG.E.64 R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x0002a2000c1e1b00 */
/*0b20*/ IMAD.WIDE R10, R29, 0x8, R26 ; /* 0x000000081d0a7825 */
/* 0x000fc800078e021a */
/*0b30*/ IMAD.WIDE R24, R29.reuse, 0x8, R12 ; /* 0x000000081d187825 */
/* 0x040fe400078e020c */
/*0b40*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x0022e8000c1e1b00 */
/*0b50*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x0008e2000c1e1b00 */
/*0b60*/ IMAD.WIDE R10, R29, 0x8, R10 ; /* 0x000000081d0a7825 */
/* 0x002fc800078e020a */
/*0b70*/ IMAD.WIDE R24, R29, 0x8, R24 ; /* 0x000000081d187825 */
/* 0x010fc800078e0218 */
/*0b80*/ IMAD.WIDE R26, R29, 0x8, R10 ; /* 0x000000081d1a7825 */
/* 0x001fc800078e020a */
/*0b90*/ IMAD.WIDE R22, R29, 0x8, R24 ; /* 0x000000081d167825 */
/* 0x000fe200078e0218 */
/*0ba0*/ DFMA R16, R20, R18, R16 ; /* 0x000000121410722b */
/* 0x0040e40000000010 */
/*0bb0*/ LDG.E.64 R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x001ea8000c1e1b00 */
/*0bc0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ DFMA R14, R12, R14, R16 ; /* 0x0000000e0c0e722b */
/* 0x0080860000000010 */
/*0be0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x001ee8000c1e1b00 */
/*0bf0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x0000e2000c1e1b00 */
/*0c00*/ IADD3 R28, R28, -0x4, RZ ; /* 0xfffffffc1c1c7810 */
/* 0x000fe40007ffe0ff */
/*0c10*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ ISETP.NE.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003f05270 */
/*0c30*/ IMAD.WIDE R26, R29, 0x8, R26 ; /* 0x000000081d1a7825 */
/* 0x001fe200078e021a */
/*0c40*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x004ecc000000000e */
/*0c50*/ DFMA R16, R12, R16, R14 ; /* 0x000000100c10722b */
/* 0x008064000000000e */
/*0c60*/ IMAD.WIDE R12, R29, 0x8, R22 ; /* 0x000000081d0c7825 */
/* 0x001fc600078e0216 */
/*0c70*/ @P0 BRA 0xaf0 ; /* 0xfffffe7000000947 */
/* 0x002fea000383ffff */
/*0c80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0c90*/ @!P0 BRA 0xe60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ MOV R10, 0x8 ; /* 0x00000008000a7802 */
/* 0x000fe20000000f00 */
/*0cb0*/ IMAD R15, R0.reuse, c[0x0][0x170], R3 ; /* 0x00005c00000f7a24 */
/* 0x040fe400078e0203 */
/*0cc0*/ IMAD R13, R0, c[0x0][0x170], R6 ; /* 0x00005c00000d7a24 */
/* 0x000fe400078e0206 */
/*0cd0*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e020a */
/*0ce0*/ IMAD.WIDE R12, R13, R10, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e020a */
/*0cf0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0d00*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0d10*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0d20*/ DFMA R16, R14, R12, R16 ; /* 0x0000000c0e10722b */
/* 0x0040580000000010 */
/*0d30*/ @!P0 BRA 0xe60 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0d40*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f05270 */
/*0d50*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fca0000000f00 */
/*0d60*/ IMAD R0, R0, R11, c[0x0][0x170] ; /* 0x00005c0000007624 */
/* 0x000fca00078e020b */
/*0d70*/ IADD3 R13, R0.reuse, R3, RZ ; /* 0x00000003000d7210 */
/* 0x041fe40007ffe0ff */
/*0d80*/ IADD3 R15, R0.reuse, R6, RZ ; /* 0x00000006000f7210 */
/* 0x040fe40007ffe0ff */
/*0d90*/ @P0 IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000000a10 */
/* 0x000fe20007ffe0ff */
/*0da0*/ IMAD.WIDE R12, R13, R10, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fc600078e020a */
/*0db0*/ @P0 IADD3 R19, R0.reuse, R3, RZ ; /* 0x0000000300130210 */
/* 0x040fe20007ffe0ff */
/*0dc0*/ IMAD.WIDE R14, R15, R10, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e020a */
/*0dd0*/ @P0 IADD3 R11, R0, R6, RZ ; /* 0x00000006000b0210 */
/* 0x000fe20007ffe0ff */
/*0de0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0df0*/ @P0 IMAD.WIDE R18, R19, R10.reuse, c[0x0][0x160] ; /* 0x0000580013120625 */
/* 0x080fe400078e020a */
/*0e00*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0e10*/ @P0 IMAD.WIDE R10, R11, R10, c[0x0][0x160] ; /* 0x000058000b0a0625 */
/* 0x000fe400078e020a */
/*0e20*/ @P0 LDG.E.64 R18, [R18.64] ; /* 0x0000000412120981 */
/* 0x000ee8000c1e1b00 */
/*0e30*/ @P0 LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a0981 */
/* 0x000ee2000c1e1b00 */
/*0e40*/ DFMA R16, R12, R14, R16 ; /* 0x0000000e0c10722b */
/* 0x006ecc0000000010 */
/*0e50*/ @P0 DFMA R16, R18, R10, R16 ; /* 0x0000000a1210022b */
/* 0x0080480000000010 */
/*0e60*/ IMAD R10, R6, c[0x0][0x170], R3 ; /* 0x00005c00060a7a24 */
/* 0x001fe200078e0203 */
/*0e70*/ IADD3 R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a10 */
/* 0x000fe40007ffe0ff */
/*0e80*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fe40000000f00 */
/*0e90*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f06270 */
/*0ea0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe20007ffe0ff */
/*0eb0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e020b */
/*0ec0*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0021ea000c101b04 */
/*0ed0*/ @!P0 BRA 0x190 ; /* 0xfffff2b000008947 */
/* 0x000fea000383ffff */
/*0ee0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15multiply_devicePdS_i
.globl _Z15multiply_devicePdS_i
.p2align 8
.type _Z15multiply_devicePdS_i,@function
_Z15multiply_devicePdS_i:
s_load_b32 s8, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s8
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x18
s_cmp_gt_i32 s8, 0
v_mul_lo_u32 v5, v0, s8
s_cselect_b32 s0, -1, 0
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v1, 0, 1, s0
s_ashr_i32 s9, s8, 31
s_mov_b32 s2, s15
s_lshl_b64 s[10:11], s[8:9], 3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_3:
v_add_nc_u32_e32 v6, s2, v5
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s2, s8
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_store_b64 v[6:7], v[3:4], off
s_cbranch_scc0 .LBB0_7
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v3, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, v0
s_lshl_b64 s[12:13], s[2:3], 3
s_mov_b32 s3, s8
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
.p2align 6
.LBB0_6:
v_lshlrev_b64 v[6:7], 3, v[1:2]
s_add_i32 s3, s3, -1
v_add_nc_u32_e32 v1, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b64 v[8:9], v2, s[12:13]
global_load_b64 v[6:7], v[6:7], off
s_add_u32 s12, s12, s10
s_addc_u32 s13, s13, s11
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[6:7], v[8:9], v[3:4]
s_cbranch_scc1 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15multiply_devicePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15multiply_devicePdS_i, .Lfunc_end0-_Z15multiply_devicePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15multiply_devicePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15multiply_devicePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c4d33_00000000-6_serial_mult1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5randdv
.type _Z5randdv, @function
_Z5randdv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
addsd .LC1(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5randdv, .-_Z5randdv
.globl _Z15multiply_serialPdS_i
.type _Z15multiply_serialPdS_i, @function
_Z15multiply_serialPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %r8
movq %rsi, %r9
movl %edx, %esi
movslq %edx, %rbx
leaq 8(,%rbx,8), %rbp
leaq 0(,%rbx,8), %rdi
movq %rbx, %r10
movl $0, %r11d
.L7:
movq %r11, %rcx
negq %rcx
.L10:
movq %r8, %rax
pxor %xmm1, %xmm1
movl $0, %edx
.L8:
pxor %xmm0, %xmm0
cvtsd2ss (%rax), %xmm0
pxor %xmm2, %xmm2
cvtsd2ss (%rax,%rcx,8), %xmm2
mulss %xmm2, %xmm0
addss %xmm0, %xmm1
addl $1, %edx
addq %rdi, %rax
cmpl %edx, %esi
jne .L8
cvtss2sd %xmm1, %xmm1
movsd %xmm1, (%r9,%rcx,8)
addq $1, %rcx
cmpq %r10, %rcx
jne .L10
addq $1, %r11
addq %rbp, %r9
subq $1, %r10
addq $8, %r8
cmpq %rbx, %r11
jne .L7
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15multiply_serialPdS_i, .-_Z15multiply_serialPdS_i
.globl _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
.type _Z38__device_stub__Z15multiply_devicePdS_iPdS_i, @function
_Z38__device_stub__Z15multiply_devicePdS_iPdS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15multiply_devicePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z15multiply_devicePdS_iPdS_i, .-_Z38__device_stub__Z15multiply_devicePdS_iPdS_i
.globl _Z15multiply_devicePdS_i
.type _Z15multiply_devicePdS_i, @function
_Z15multiply_devicePdS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15multiply_devicePdS_i, .-_Z15multiply_devicePdS_i
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $72, %edi
call malloc@PLT
movq %rax, %r13
movl $72, %edi
call malloc@PLT
movq %rax, %r15
movl $72, %edi
call malloc@PLT
movq %rax, %r14
movq %rsp, %rdi
movl $72, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $72, %esi
call cudaMalloc@PLT
movq %r13, %rbp
movl $0, %r12d
jmp .L25
.L32:
addq $3, %r12
addq $24, %rbp
cmpq $9, %r12
je .L27
.L25:
movl $0, %ebx
.L26:
call _Z5randdv
movsd %xmm0, 0(%rbp,%rbx,8)
addq $1, %rbx
cmpq $3, %rbx
jne .L26
jmp .L32
.L27:
movl $3, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z15multiply_serialPdS_i
movl $1, %ecx
movl $72, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl $2, %ecx
movl $72, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $3, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z15multiply_devicePdS_iPdS_i
jmp .L28
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z15multiply_devicePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15multiply_devicePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "serial_mult1.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5randdv
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z5randdv
.p2align 4, 0x90
.type _Z5randdv,@function
_Z5randdv: # @_Z5randdv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq rand
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd .LCPI0_1(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5randdv, .Lfunc_end0-_Z5randdv
.cfi_endproc
# -- End function
.globl _Z15multiply_serialPdS_i # -- Begin function _Z15multiply_serialPdS_i
.p2align 4, 0x90
.type _Z15multiply_serialPdS_i,@function
_Z15multiply_serialPdS_i: # @_Z15multiply_serialPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_8
# %bb.1: # %.preheader28.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader28
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
movq %r8, %r9
imulq %rax, %r9
leaq (%rsi,%r9,8), %r9
xorl %r10d, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
xorps %xmm0, %xmm0
movq %rax, %rbx
movq %rdi, %r14
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r14,%rdx), %xmm1 # xmm1 = mem[0],zero
cvtsd2ss %xmm1, %xmm1
movsd (%r14,%r10), %xmm2 # xmm2 = mem[0],zero
cvtsd2ss %xmm2, %xmm2
mulss %xmm1, %xmm2
addss %xmm2, %xmm0
addq %rcx, %r14
decq %rbx
jne .LBB1_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB1_3 Depth=2
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%r9,%r11,8)
incq %r11
addq $8, %r10
cmpq %rax, %r11
jne .LBB1_3
# %bb.6: # %._crit_edge32
# in Loop: Header=BB1_2 Depth=1
incq %r8
addq $8, %rdx
cmpq %rax, %r8
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB1_8: # %._crit_edge34
retq
.Lfunc_end1:
.size _Z15multiply_serialPdS_i, .Lfunc_end1-_Z15multiply_serialPdS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__multiply_devicePdS_i # -- Begin function _Z30__device_stub__multiply_devicePdS_i
.p2align 4, 0x90
.type _Z30__device_stub__multiply_devicePdS_i,@function
_Z30__device_stub__multiply_devicePdS_i: # @_Z30__device_stub__multiply_devicePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15multiply_devicePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__multiply_devicePdS_i, .Lfunc_end2-_Z30__device_stub__multiply_devicePdS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $72, %edi
callq malloc
movq %rax, %rbx
movl $72, %edi
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $72, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $72, %esi
callq hipMalloc
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%r13,8)
incq %r13
cmpq $3, %r13
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r15
addq $24, %r12
cmpq $3, %r15
jne .LBB3_1
# %bb.4: # %_Z15multiply_serialPdS_i.exit
movq 24(%rsp), %rdi
movl $72, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 1020(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $3, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15multiply_devicePdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 16(%rsp), %rsi
movl $72, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15multiply_devicePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15multiply_devicePdS_i,@object # @_Z15multiply_devicePdS_i
.section .rodata,"a",@progbits
.globl _Z15multiply_devicePdS_i
.p2align 3, 0x0
_Z15multiply_devicePdS_i:
.quad _Z30__device_stub__multiply_devicePdS_i
.size _Z15multiply_devicePdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15multiply_devicePdS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__multiply_devicePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15multiply_devicePdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
cudaDeviceProp deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
cudaError_t cudaError;
// 获取当前的设备总数
cudaError = cudaGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
cudaError = cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
cudaDeviceProp deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
cudaError_t cudaError;
// 获取当前的设备总数
cudaError = cudaGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
cudaError = cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} | .file "tmpxft_00060274_00000000-6_look_up.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "We have "
.LC1:
.string " device(s)."
.LC2:
.string "\350\256\276\345\244\207 "
.LC3:
.string " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.LC4:
.string "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC6:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC7:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.align 8
.LC8:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.align 8
.LC9:
.string "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.section .rodata.str1.1
.LC10:
.string "."
.section .rodata.str1.8
.align 8
.LC11:
.string "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC3(%rip), %r13
jmp .L37
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L51:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L52:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L57:
movzbl 67(%r15), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl 12(%rsp), %r12d
jge .L4
.L37:
leaq 16(%rsp), %rdi
movl %r12d, %esi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $48, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
shrq $20, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L51
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $89, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
shrq $10, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $71, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $69, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $64, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC10(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $34, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
jne .L57
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
cudaDeviceProp deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
cudaError_t cudaError;
// 获取当前的设备总数
cudaError = cudaGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
cudaError = cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "hip/hip_runtime.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
hipDeviceProp_t deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
hipError_t hipError_t;
// 获取当前的设备总数
hipError_t = hipGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
hipError_t = hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "hip/hip_runtime.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
hipDeviceProp_t deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
hipError_t hipError_t;
// 获取当前的设备总数
hipError_t = hipGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
hipError_t = hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // 程序功能：查看当前服务器上具有的显卡数目，并且分别获取他们的详细属性。
// 必要的CUDA 包含文件
#include "hip/hip_runtime.h"
// 传统 C++ 流输入输出支持
#include <iostream>
using namespace std;
// 主函数
int main()
{
// 设备属性的变量
hipDeviceProp_t deviceProp;
// 设备计数
int deviceCount;
// 保存调用函数的输出结果
hipError_t hipError_t;
// 获取当前的设备总数
hipError_t = hipGetDeviceCount(&deviceCount);
cout<<"We have "<<deviceCount<<" device(s)."<<endl;
// 获得每一个设备的属性
for (int i = 0; i < deviceCount; i++)
{
// 获得属性
hipError_t = hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
} | .text
.file "look_up.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_40
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB0_4
.LBB0_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB0_39
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_37: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl 4(%rsp), %ebx
jge .LBB0_39
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_40
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i5
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r12)
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_6 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit8
# in Loop: Header=BB0_6 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_40
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_13
# %bb.12: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
# in Loop: Header=BB0_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_17
# %bb.16: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $89, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_21
# %bb.20: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $71, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 312(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_26
.p2align 4, 0x90
.LBB0_25: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $69, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_29
# %bb.28: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $64, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_33
# %bb.32: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_38
.LBB0_39: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_40:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "We have "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " device(s)."
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\350\256\276\345\244\207 "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.6, 90
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.size .L.str.7, 72
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.size .L.str.8, 70
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.size .L.str.9, 65
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "."
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.size .L.str.11, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00060274_00000000-6_look_up.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "We have "
.LC1:
.string " device(s)."
.LC2:
.string "\350\256\276\345\244\207 "
.LC3:
.string " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.LC4:
.string "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC6:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC7:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.align 8
.LC8:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.align 8
.LC9:
.string "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.section .rodata.str1.1
.LC10:
.string "."
.section .rodata.str1.8
.align 8
.LC11:
.string "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC2(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC3(%rip), %r13
jmp .L37
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L51:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L52:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L57:
movzbl 67(%r15), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl 12(%rsp), %r12d
jge .L4
.L37:
leaq 16(%rsp), %rdi
movl %r12d, %esi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $48, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
shrq $20, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L51
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $89, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
shrq $10, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $71, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $69, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $64, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC10(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $34, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
jne .L57
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "look_up.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_40
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB0_4
.LBB0_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB0_39
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_37: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl 4(%rsp), %ebx
jge .LBB0_39
.LBB0_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_40
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i5
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r12)
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_6 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit8
# in Loop: Header=BB0_6 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_40
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_13
# %bb.12: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_14
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
# in Loop: Header=BB0_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_17
# %bb.16: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $89, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_21
# %bb.20: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $71, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 312(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_26
.p2align 4, 0x90
.LBB0_25: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $69, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_29
# %bb.28: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_30
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $64, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_33
# %bb.32: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_34
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB0_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_40
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB0_6 Depth=1
cmpb $0, 56(%r15)
je .LBB0_37
# %bb.36: # in Loop: Header=BB0_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_38
.LBB0_39: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_40:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "We have "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " device(s)."
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\350\256\276\345\244\207 "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.size .L.str.3, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.6, 90
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.size .L.str.7, 72
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.size .L.str.8, 70
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.size .L.str.9, 65
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "."
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.size .L.str.11, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} | code for sm_80
Function : _Z8constantPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} | .file "tmpxft_00079fe4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8constantPiPi
.type _Z27__device_stub__Z8constantPiPi, @function
_Z27__device_stub__Z8constantPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8constantPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8constantPiPi, .-_Z27__device_stub__Z8constantPiPi
.globl _Z8constantPi
.type _Z8constantPi, @function
_Z8constantPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8constantPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8constantPi, .-_Z8constantPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8constantPi"
.LC1:
.string "global_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8constantPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15global_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15global_constant
.comm _ZL15global_constant,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} | #include <hip/hip_runtime.h>
//xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8constantPi
.globl _Z8constantPi
.p2align 8
.type _Z8constantPi,@function
_Z8constantPi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8constantPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8constantPi, .Lfunc_end0-_Z8constantPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected global_constant
.type global_constant,@object
.section .bss,"aw",@nobits
.globl global_constant
.p2align 4, 0x0
global_constant:
.zero 16
.size global_constant, 16
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym global_constant
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8constantPi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8constantPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//xfail:ASSERTION_ERROR
//--gridDim=1 --blockDim=4 --no-inline
__constant__ int global_constant[4];
__global__ void constant(int *in) {
global_constant[threadIdx.x] = in[threadIdx.x];
} | .text
.file "kernel.hip"
.globl _Z23__device_stub__constantPi # -- Begin function _Z23__device_stub__constantPi
.p2align 4, 0x90
.type _Z23__device_stub__constantPi,@function
_Z23__device_stub__constantPi: # @_Z23__device_stub__constantPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8constantPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__constantPi, .Lfunc_end0-_Z23__device_stub__constantPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8constantPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $global_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type global_constant,@object # @global_constant
.local global_constant
.comm global_constant,16,16
.type _Z8constantPi,@object # @_Z8constantPi
.section .rodata,"a",@progbits
.globl _Z8constantPi
.p2align 3, 0x0
_Z8constantPi:
.quad _Z23__device_stub__constantPi
.size _Z8constantPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8constantPi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "global_constant"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__constantPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym global_constant
.addrsig_sym _Z8constantPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8constantPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BPT.TRAP 0x1 ; /* 0x000000040000795c */
/* 0x000fea0000300000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8constantPi
.globl _Z8constantPi
.p2align 8
.type _Z8constantPi,@function
_Z8constantPi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8constantPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8constantPi, .Lfunc_end0-_Z8constantPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected global_constant
.type global_constant,@object
.section .bss,"aw",@nobits
.globl global_constant
.p2align 4, 0x0
global_constant:
.zero 16
.size global_constant, 16
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym global_constant
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8constantPi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8constantPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00079fe4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8constantPiPi
.type _Z27__device_stub__Z8constantPiPi, @function
_Z27__device_stub__Z8constantPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8constantPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8constantPiPi, .-_Z27__device_stub__Z8constantPiPi
.globl _Z8constantPi
.type _Z8constantPi, @function
_Z8constantPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8constantPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8constantPi, .-_Z8constantPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8constantPi"
.LC1:
.string "global_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8constantPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15global_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL15global_constant
.comm _ZL15global_constant,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z23__device_stub__constantPi # -- Begin function _Z23__device_stub__constantPi
.p2align 4, 0x90
.type _Z23__device_stub__constantPi,@function
_Z23__device_stub__constantPi: # @_Z23__device_stub__constantPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8constantPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__constantPi, .Lfunc_end0-_Z23__device_stub__constantPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8constantPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $global_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $16, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type global_constant,@object # @global_constant
.local global_constant
.comm global_constant,16,16
.type _Z8constantPi,@object # @_Z8constantPi
.section .rodata,"a",@progbits
.globl _Z8constantPi
.p2align 3, 0x0
_Z8constantPi:
.quad _Z23__device_stub__constantPi
.size _Z8constantPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8constantPi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "global_constant"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__constantPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym global_constant
.addrsig_sym _Z8constantPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int main(void)
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int main(void)
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} | .file "tmpxft_0004e59d_00000000-6_getDeviceProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Le GPU ne g\303\250re pas les recouvrement !\n"
.align 8
.LC1:
.string "Pas d'acc\303\251l\303\251ration possible avec les flux...\n"
.align 8
.LC2:
.string "Le GPU g\303\250re les recouvrement :)\n"
.align 8
.LC3:
.string "Utilise les Flux, et que ca saute !\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 400(%rsp)
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int main(void)
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(void)
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(void)
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(void)
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (! prop.deviceOverlap)
{
printf("Le GPU ne gère pas les recouvrement !\n");
printf("Pas d'accélération possible avec les flux...\n");
}
else
{
printf("Le GPU gère les recouvrement :)\n");
printf("Utilise les Flux, et que ca saute !\n");
}
return 0;
} | .text
.file "getDeviceProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 400(%rsp)
movl $.Lstr, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
movl $.Lstr.1, %eax
movl $.Lstr.3, %ebx
cmoveq %rax, %rbx
callq puts@PLT
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Le GPU ne g\303\250re pas les recouvrement !"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Pas d'acc\303\251l\303\251ration possible avec les flux..."
.size .Lstr.1, 47
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Le GPU g\303\250re les recouvrement :)"
.size .Lstr.2, 33
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Utilise les Flux, et que ca saute !"
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004e59d_00000000-6_getDeviceProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Le GPU ne g\303\250re pas les recouvrement !\n"
.align 8
.LC1:
.string "Pas d'acc\303\251l\303\251ration possible avec les flux...\n"
.align 8
.LC2:
.string "Le GPU g\303\250re les recouvrement :)\n"
.align 8
.LC3:
.string "Utilise les Flux, et que ca saute !\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1064, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 400(%rsp)
jne .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getDeviceProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 16(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 400(%rsp)
movl $.Lstr, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
movl $.Lstr.1, %eax
movl $.Lstr.3, %ebx
cmoveq %rax, %rbx
callq puts@PLT
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Le GPU ne g\303\250re pas les recouvrement !"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Pas d'acc\303\251l\303\251ration possible avec les flux..."
.size .Lstr.1, 47
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Le GPU g\303\250re les recouvrement :)"
.size .Lstr.2, 33
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Utilise les Flux, et que ca saute !"
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
using namespace std;
__device__ void print(int a, int b, int sum){
printf("Printing sum inside DEVICE\n");
printf("\n%d\t%d + %d = %d", threadIdx.x, a, b, sum);
}
__global__ void add(int *a, int *b, int* sum){
*sum = *a + *b;
print(*a, *b, *sum);
}
int main(){
int *a, *b, *sum;
cudaMallocManaged(&a, sizeof(int));
cudaMallocManaged(&b, sizeof(int));
cudaMallocManaged(&sum , sizeof(int));
cout<<"Enter A: "; cin>>*a;
cout<<"Enter B: "; cin>>*b;
add<<<1,10>>>(a,b,sum);
cudaDeviceSynchronize();
cout<<"\nPrinting sum in HOST: Sum is "<<*sum<<endl;
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0c7624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0d7624 */
/* 0x000fe200078e00ff */
/*0070*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R0, [R12.64] ; /* 0x000000040c007981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fc400078e00ff */
/*00a0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R23, 0x0 ; /* 0x0000000000177802 */
/* 0x000fc80000000f00 */
/*00c0*/ LDC.64 R8, c[0x4][R23] ; /* 0x0100000017087b82 */
/* 0x0000620000000a00 */
/*00d0*/ IMAD.IADD R19, R19, 0x1, R0 ; /* 0x0000000113137824 */
/* 0x004fca00078e0200 */
/*00e0*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0001e8000c101904 */
/*00f0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000168000c1e1900 */
/*0100*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000162000c1e1900 */
/*0110*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fe20007f1e0ff */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0130*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*0150*/ IMAD.X R22, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff167624 */
/* 0x000fe400000e06ff */
/*0160*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fcc0000000000 */
/*0170*/ MOV R3, 0x1e0 ; /* 0x000001e000037802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01c0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x020fea0003c00000 */
/*01e0*/ S2R R16, SR_TID.X ; /* 0x0000000000107919 */
/* 0x000e220000002100 */
/*01f0*/ LDC.64 R8, c[0x4][R23] ; /* 0x0100000017087b82 */
/* 0x0002a20000000a00 */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, R22 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0016 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0240*/ STL.128 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0013e80000100c00 */
/*0250*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x000fe40000000000 */
/*0260*/ MOV R11, 0x2d0 ; /* 0x000002d0000b7802 */
/* 0x000fe40000000f00 */
/*0270*/ MOV R20, 0x250 ; /* 0x0000025000147802 */
/* 0x000fc40000000f00 */
/*0280*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0290*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02a0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02b0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*02c0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x006fea0003c00000 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
using namespace std;
__device__ void print(int a, int b, int sum){
printf("Printing sum inside DEVICE\n");
printf("\n%d\t%d + %d = %d", threadIdx.x, a, b, sum);
}
__global__ void add(int *a, int *b, int* sum){
*sum = *a + *b;
print(*a, *b, *sum);
}
int main(){
int *a, *b, *sum;
cudaMallocManaged(&a, sizeof(int));
cudaMallocManaged(&b, sizeof(int));
cudaMallocManaged(&sum , sizeof(int));
cout<<"Enter A: "; cin>>*a;
cout<<"Enter B: "; cin>>*b;
add<<<1,10>>>(a,b,sum);
cudaDeviceSynchronize();
cout<<"\nPrinting sum in HOST: Sum is "<<*sum<<endl;
return 0;
} | .file "tmpxft_00077c45_00000000-6_device_func.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5printiii
.type _Z5printiii, @function
_Z5printiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z5printiii, .-_Z5printiii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter A: "
.LC1:
.string "Enter B: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nPrinting sum in HOST: Sum is "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbx
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC1(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 24(%rsp), %rax
movl (%rax), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<cuda.h>
#include<cuda_runtime.h>
using namespace std;
__device__ void print(int a, int b, int sum){
printf("Printing sum inside DEVICE\n");
printf("\n%d\t%d + %d = %d", threadIdx.x, a, b, sum);
}
__global__ void add(int *a, int *b, int* sum){
*sum = *a + *b;
print(*a, *b, *sum);
}
int main(){
int *a, *b, *sum;
cudaMallocManaged(&a, sizeof(int));
cudaMallocManaged(&b, sizeof(int));
cudaMallocManaged(&sum , sizeof(int));
cout<<"Enter A: "; cin>>*a;
cout<<"Enter B: "; cin>>*b;
add<<<1,10>>>(a,b,sum);
cudaDeviceSynchronize();
cout<<"\nPrinting sum in HOST: Sum is "<<*sum<<endl;
return 0;
} | #include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
__device__ void print(int a, int b, int sum){
printf("Printing sum inside DEVICE\n");
printf("\n%d\t%d + %d = %d", threadIdx.x, a, b, sum);
}
__global__ void add(int *a, int *b, int* sum){
*sum = *a + *b;
print(*a, *b, *sum);
}
int main(){
int *a, *b, *sum;
hipMallocManaged(&a, sizeof(int));
hipMallocManaged(&b, sizeof(int));
hipMallocManaged(&sum , sizeof(int));
cout<<"Enter A: "; cin>>*a;
cout<<"Enter B: "; cin>>*b;
add<<<1,10>>>(a,b,sum);
hipDeviceSynchronize();
cout<<"\nPrinting sum in HOST: Sum is "<<*sum<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
__device__ void print(int a, int b, int sum){
printf("Printing sum inside DEVICE\n");
printf("\n%d\t%d + %d = %d", threadIdx.x, a, b, sum);
}
__global__ void add(int *a, int *b, int* sum){
*sum = *a + *b;
print(*a, *b, *sum);
}
int main(){
int *a, *b, *sum;
hipMallocManaged(&a, sizeof(int));
hipMallocManaged(&b, sizeof(int));
hipMallocManaged(&sum , sizeof(int));
cout<<"Enter A: "; cin>>*a;
cout<<"Enter B: "; cin>>*b;
add<<<1,10>>>(a,b,sum);
hipDeviceSynchronize();
cout<<"\nPrinting sum in HOST: Sum is "<<*sum<<endl;
return 0;
} | .text
.file "device_func.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rax
movl (%rax), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter A: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter B: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nPrinting sum in HOST: Sum is "
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00077c45_00000000-6_device_func.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5printiii
.type _Z5printiii, @function
_Z5printiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z5printiii, .-_Z5printiii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter A: "
.LC1:
.string "Enter B: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nPrinting sum in HOST: Sum is "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbx
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC1(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 24(%rsp), %rax
movl (%rax), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device_func.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rax
movl (%rax), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter A: "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter B: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nPrinting sum in HOST: Sum is "
.size .L.str.2, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
#define GPUJOULE_DIR ""
#define SHARED_MEM_ELEMENTS 1024
int num_blocks;
int num_threads_per_block;
int num_iterations;
int divergence;
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div, int stride) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
__shared__ unsigned long long sdata[SHARED_MEM_ELEMENTS];
__shared__ void **tmp_ptr;
__shared__ void *arr[SHARED_MEM_ELEMENTS];
if (threadIdx.x == 0) {
for (int i = 0; i < SHARED_MEM_ELEMENTS; i++) {
arr[i] = (void *)&sdata[i];
}
for (int i = 0; i < (SHARED_MEM_ELEMENTS - 1); i++) {
sdata[i] = (unsigned long long) arr[i + 1];
}
sdata[SHARED_MEM_ELEMENTS - 1] = (unsigned long long) arr[0];
}
__syncthreads();
tmp_ptr = (void **)(&(arr[(threadIdx.x + stride) % SHARED_MEM_ELEMENTS]));
double f1, f2, f3;
f1 = 1.1;
f2 = 2.5;
if (thread_id < div) {
/* __asm volatile (
".reg .f32 %r14;\n\t"
"mov.f32 %r14, 2.2;\n\t"
);
*/
for (int k = 0; k < n; k++) {
/* __asm volatile (
"add.rn.f32 %r14, %r11, %r14;\n\t"
);
*/
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = f1 * tid;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 6) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
int stride = atoi(argv[5]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
std::string cmd = "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &";
std::system(cmd.c_str());
std::system("sleep 5");
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence, stride);
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::system("killall power_monitor");
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_001acf0e_00000000-6_fadd_shd_mem_64p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z29__device_stub__Z7computePfiiiPfiii
.type _Z29__device_stub__Z7computePfiiiPfiii, @function
_Z29__device_stub__Z7computePfiiiPfiii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7computePfiiiPfiii, .-_Z29__device_stub__Z7computePfiiiPfiii
.globl _Z7computePfiii
.type _Z7computePfiii, @function
_Z7computePfiii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfiii, .-_Z7computePfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "sleep 5"
.LC2:
.string "killall power_monitor"
.LC3:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3670
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L26
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 32(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl $4, %esi
leaq d_res(%rip), %rdi
.LEHB0:
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
movq $157, 32(%rsp)
leaq 32(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, 48(%rsp)
movq 32(%rsp), %rdx
movq %rdx, 64(%rsp)
movabsq $4993459885884919879, %rdx
movabsq $7887612946909054047, %rcx
movq %rdx, (%rax)
movq %rcx, 8(%rax)
movabsq $7813865618886963052, %rdx
movabsq $6877671144593305445, %rcx
movq %rdx, 16(%rax)
movq %rcx, 24(%rax)
movabsq $2338053702334443373, %rdx
movabsq $5356275598240915509, %rcx
movq %rdx, 32(%rax)
movq %rcx, 40(%rax)
movabsq $5929345560385181007, %rdx
movabsq $6879643646810809647, %rcx
movq %rdx, 48(%rax)
movq %rcx, 56(%rax)
movabsq $7094681707154272109, %rsi
movabsq $7308890499558108773, %rdi
movq %rsi, 64(%rax)
movq %rdi, 72(%rax)
movabsq $7306087011045697394, %rdx
movabsq $7147038286138335084, %rcx
movq %rdx, 80(%rax)
movq %rcx, 88(%rax)
movabsq $6873730456163085679, %rsi
movabsq $7809653381184843369, %rdi
movq %rsi, 96(%rax)
movq %rdi, 104(%rax)
movabsq $6876556179756115049, %rdx
movabsq $7233174830218240356, %rcx
movq %rdx, 112(%rax)
movq %rcx, 120(%rax)
movabsq $7308602655145942884, %rsi
movabsq $8314031322619600749, %rdi
movq %rsi, 128(%rax)
movq %rdi, 136(%rax)
movabsq $8606220968088789343, %rdx
movabsq $2747323833390101093, %rcx
movq %rdx, 141(%rax)
movq %rcx, 149(%rax)
movq 32(%rsp), %rax
movq %rax, 56(%rsp)
movq 48(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 48(%rsp), %rdi
.LEHB1:
call system@PLT
.LEHE1:
jmp .L27
.L26:
.LEHB2:
call _Z5usagev
.LEHE2:
movl $1, %edi
call exit@PLT
.L27:
leaq .LC1(%rip), %rdi
.LEHB3:
call system@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %r13d, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movl %r12d, %ecx
movl %ebp, %edx
movl %ebx, %esi
movq d_res(%rip), %rdi
call _Z29__device_stub__Z7computePfiiiPfiii
.L19:
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 32(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rdi
call system@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
.LEHE3:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3670:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3670-.LLSDACSB3670
.LLSDACSB3670:
.uleb128 .LEHB0-.LFB3670
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3670
.uleb128 .LEHE1-.LEHB1
.uleb128 .L23-.LFB3670
.uleb128 0
.uleb128 .LEHB2-.LFB3670
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3670
.uleb128 .LEHE3-.LEHB3
.uleb128 .L23-.LFB3670
.uleb128 0
.uleb128 .LEHB4-.LFB3670
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3670:
.text
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7computePfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.globl divergence
.align 4
.type divergence, @object
.size divergence, 4
divergence:
.zero 4
.globl num_iterations
.align 4
.type num_iterations, @object
.size num_iterations, 4
num_iterations:
.zero 4
.globl num_threads_per_block
.align 4
.type num_threads_per_block, @object
.size num_threads_per_block, 4
num_threads_per_block:
.zero 4
.globl num_blocks
.align 4
.type num_blocks, @object
.size num_blocks, 4
num_blocks:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
#define GPUJOULE_DIR ""
#define SHARED_MEM_ELEMENTS 1024
int num_blocks;
int num_threads_per_block;
int num_iterations;
int divergence;
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div, int stride) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
__shared__ unsigned long long sdata[SHARED_MEM_ELEMENTS];
__shared__ void **tmp_ptr;
__shared__ void *arr[SHARED_MEM_ELEMENTS];
if (threadIdx.x == 0) {
for (int i = 0; i < SHARED_MEM_ELEMENTS; i++) {
arr[i] = (void *)&sdata[i];
}
for (int i = 0; i < (SHARED_MEM_ELEMENTS - 1); i++) {
sdata[i] = (unsigned long long) arr[i + 1];
}
sdata[SHARED_MEM_ELEMENTS - 1] = (unsigned long long) arr[0];
}
__syncthreads();
tmp_ptr = (void **)(&(arr[(threadIdx.x + stride) % SHARED_MEM_ELEMENTS]));
double f1, f2, f3;
f1 = 1.1;
f2 = 2.5;
if (thread_id < div) {
/* __asm volatile (
".reg .f32 %r14;\n\t"
"mov.f32 %r14, 2.2;\n\t"
);
*/
for (int k = 0; k < n; k++) {
/* __asm volatile (
"add.rn.f32 %r14, %r11, %r14;\n\t"
);
*/
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = f1 * tid;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 6) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
int stride = atoi(argv[5]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
std::string cmd = "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &";
std::system(cmd.c_str());
std::system("sleep 5");
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence, stride);
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::system("killall power_monitor");
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
#define GPUJOULE_DIR ""
#define SHARED_MEM_ELEMENTS 1024
int num_blocks;
int num_threads_per_block;
int num_iterations;
int divergence;
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div, int stride) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
__shared__ unsigned long long sdata[SHARED_MEM_ELEMENTS];
__shared__ void **tmp_ptr;
__shared__ void *arr[SHARED_MEM_ELEMENTS];
if (threadIdx.x == 0) {
for (int i = 0; i < SHARED_MEM_ELEMENTS; i++) {
arr[i] = (void *)&sdata[i];
}
for (int i = 0; i < (SHARED_MEM_ELEMENTS - 1); i++) {
sdata[i] = (unsigned long long) arr[i + 1];
}
sdata[SHARED_MEM_ELEMENTS - 1] = (unsigned long long) arr[0];
}
__syncthreads();
tmp_ptr = (void **)(&(arr[(threadIdx.x + stride) % SHARED_MEM_ELEMENTS]));
double f1, f2, f3;
f1 = 1.1;
f2 = 2.5;
if (thread_id < div) {
/* __asm volatile (
".reg .f32 %r14;\n\t"
"mov.f32 %r14, 2.2;\n\t"
);
*/
for (int k = 0; k < n; k++) {
/* __asm volatile (
"add.rn.f32 %r14, %r11, %r14;\n\t"
);
*/
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = f1 * tid;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 6) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
int stride = atoi(argv[5]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
std::string cmd = "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &";
std::system(cmd.c_str());
std::system("sleep 5");
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence, stride);
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::system("killall power_monitor");
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
#define GPUJOULE_DIR ""
#define SHARED_MEM_ELEMENTS 1024
int num_blocks;
int num_threads_per_block;
int num_iterations;
int divergence;
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div, int stride) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
__shared__ unsigned long long sdata[SHARED_MEM_ELEMENTS];
__shared__ void **tmp_ptr;
__shared__ void *arr[SHARED_MEM_ELEMENTS];
if (threadIdx.x == 0) {
for (int i = 0; i < SHARED_MEM_ELEMENTS; i++) {
arr[i] = (void *)&sdata[i];
}
for (int i = 0; i < (SHARED_MEM_ELEMENTS - 1); i++) {
sdata[i] = (unsigned long long) arr[i + 1];
}
sdata[SHARED_MEM_ELEMENTS - 1] = (unsigned long long) arr[0];
}
__syncthreads();
tmp_ptr = (void **)(&(arr[(threadIdx.x + stride) % SHARED_MEM_ELEMENTS]));
double f1, f2, f3;
f1 = 1.1;
f2 = 2.5;
if (thread_id < div) {
/* __asm volatile (
".reg .f32 %r14;\n\t"
"mov.f32 %r14, 2.2;\n\t"
);
*/
for (int k = 0; k < n; k++) {
/* __asm volatile (
"add.rn.f32 %r14, %r11, %r14;\n\t"
);
*/
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
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tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
tmp_ptr = (void**)(*tmp_ptr);
f1 = f1 + k;
}
}
// __syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = f1 * tid;
// __syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 6) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
int stride = atoi(argv[5]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
std::string cmd = "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &";
std::system(cmd.c_str());
std::system("sleep 5");
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence, stride);
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::system("killall power_monitor");
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.file "fadd_shd_mem_64p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfiii # -- Begin function _Z22__device_stub__computePfiii
.p2align 4, 0x90
.type _Z22__device_stub__computePfiii,@function
_Z22__device_stub__computePfiii: # @_Z22__device_stub__computePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfiii, .Lfunc_end0-_Z22__device_stub__computePfiii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB2_35
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movq %rsi, %r15
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 40(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
movl $158, %edi
callq _Znwm
movq %rax, %rbp
movq %rax, 40(%rsp)
movq $157, 56(%rsp)
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $157, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $157, 48(%rsp)
movb $0, 157(%rbp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq system
.Ltmp1:
# %bb.2:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq system
.Ltmp3:
# %bb.3:
movq 16(%rsp), %rdi
.Ltmp4:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp5:
# %bb.4:
.Ltmp6:
.cfi_escape 0x2e, 0x00
callq hipProfilerStart
.Ltmp7:
# %bb.5:
movl %r12d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r13d, %edx
orq %rax, %rdx
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp9:
# %bb.6:
testl %eax, %eax
jne .LBB2_9
# %bb.7:
movq d_res(%rip), %rax
movq %rax, 120(%rsp)
movl %ebx, 36(%rsp)
movl %r14d, 32(%rsp)
movl %r15d, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp11:
# %bb.8: # %.noexc20
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
.Ltmp12:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z7computePfiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp13:
.LBB2_9:
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq hipProfilerStop
.Ltmp15:
# %bb.10:
movq 8(%rsp), %rdi
.Ltmp16:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp17:
# %bb.11:
movq 8(%rsp), %rdi
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp19:
# %bb.12:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp21:
# %bb.13:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq system
.Ltmp23:
# %bb.14:
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.16: # %_ZNSolsEf.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_17
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_24
# %bb.23:
movzbl 67(%r14), %eax
jmp .LBB2_26
.LBB2_24:
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.25: # %.noexc29
movq (%r14), %rax
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB2_26: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp32:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.27: # %.noexc31
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.28: # %_ZNSolsEPFRSoS_E.exit
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp37:
# %bb.29:
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp39:
# %bb.30:
.Ltmp40:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp41:
# %bb.31:
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp43:
# %bb.32:
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_34
# %bb.33: # %.critedge.i.i25
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit27
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_35:
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
callq _Z5usagev
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB2_17:
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp45:
# %bb.21: # %.noexc28
.LBB2_18:
.Ltmp46:
movq %rax, %rbx
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp43-.Ltmp0 # Call between .Ltmp0 and .Ltmp43
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end2-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_blocks,@object # @num_blocks
.bss
.globl num_blocks
.p2align 2, 0x0
num_blocks:
.long 0 # 0x0
.size num_blocks, 4
.type num_threads_per_block,@object # @num_threads_per_block
.globl num_threads_per_block
.p2align 2, 0x0
num_threads_per_block:
.long 0 # 0x0
.size num_threads_per_block, 4
.type num_iterations,@object # @num_iterations
.globl num_iterations
.p2align 2, 0x0
num_iterations:
.long 0 # 0x0
.size num_iterations, 4
.type divergence,@object # @divergence
.globl divergence
.p2align 2, 0x0
divergence:
.long 0 # 0x0
.size divergence, 4
.type h_A,@object # @h_A
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfiii,@object # @_Z7computePfiii
.section .rodata,"a",@progbits
.globl _Z7computePfiii
.p2align 3, 0x0
_Z7computePfiii:
.quad _Z22__device_stub__computePfiii
.size _Z7computePfiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &"
.size .L.str.1, 158
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sleep 5"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "killall power_monitor"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Elapsed Time = "
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym d_res
.addrsig_sym _Z7computePfiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001acf0e_00000000-6_fadd_shd_mem_64p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z29__device_stub__Z7computePfiiiPfiii
.type _Z29__device_stub__Z7computePfiiiPfiii, @function
_Z29__device_stub__Z7computePfiiiPfiii:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z29__device_stub__Z7computePfiiiPfiii, .-_Z29__device_stub__Z7computePfiiiPfiii
.globl _Z7computePfiii
.type _Z7computePfiii, @function
_Z7computePfiii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7computePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfiii, .-_Z7computePfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "sleep 5"
.LC2:
.string "killall power_monitor"
.LC3:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3670
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $96, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L26
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 32(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl $4, %esi
leaq d_res(%rip), %rdi
.LEHB0:
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
movq $157, 32(%rsp)
leaq 32(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, 48(%rsp)
movq 32(%rsp), %rdx
movq %rdx, 64(%rsp)
movabsq $4993459885884919879, %rdx
movabsq $7887612946909054047, %rcx
movq %rdx, (%rax)
movq %rcx, 8(%rax)
movabsq $7813865618886963052, %rdx
movabsq $6877671144593305445, %rcx
movq %rdx, 16(%rax)
movq %rcx, 24(%rax)
movabsq $2338053702334443373, %rdx
movabsq $5356275598240915509, %rcx
movq %rdx, 32(%rax)
movq %rcx, 40(%rax)
movabsq $5929345560385181007, %rdx
movabsq $6879643646810809647, %rcx
movq %rdx, 48(%rax)
movq %rcx, 56(%rax)
movabsq $7094681707154272109, %rsi
movabsq $7308890499558108773, %rdi
movq %rsi, 64(%rax)
movq %rdi, 72(%rax)
movabsq $7306087011045697394, %rdx
movabsq $7147038286138335084, %rcx
movq %rdx, 80(%rax)
movq %rcx, 88(%rax)
movabsq $6873730456163085679, %rsi
movabsq $7809653381184843369, %rdi
movq %rsi, 96(%rax)
movq %rdi, 104(%rax)
movabsq $6876556179756115049, %rdx
movabsq $7233174830218240356, %rcx
movq %rdx, 112(%rax)
movq %rcx, 120(%rax)
movabsq $7308602655145942884, %rsi
movabsq $8314031322619600749, %rdi
movq %rsi, 128(%rax)
movq %rdi, 136(%rax)
movabsq $8606220968088789343, %rdx
movabsq $2747323833390101093, %rcx
movq %rdx, 141(%rax)
movq %rcx, 149(%rax)
movq 32(%rsp), %rax
movq %rax, 56(%rsp)
movq 48(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 48(%rsp), %rdi
.LEHB1:
call system@PLT
.LEHE1:
jmp .L27
.L26:
.LEHB2:
call _Z5usagev
.LEHE2:
movl $1, %edi
call exit@PLT
.L27:
leaq .LC1(%rip), %rdi
.LEHB3:
call system@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r14d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %r13d, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L19
movl %r12d, %ecx
movl %ebp, %edx
movl %ebx, %esi
movq d_res(%rip), %rdi
call _Z29__device_stub__Z7computePfiiiPfiii
.L19:
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 32(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC2(%rip), %rdi
call system@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
.LEHE3:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L21
call __stack_chk_fail@PLT
.L21:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3670:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3670-.LLSDACSB3670
.LLSDACSB3670:
.uleb128 .LEHB0-.LFB3670
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3670
.uleb128 .LEHE1-.LEHB1
.uleb128 .L23-.LFB3670
.uleb128 0
.uleb128 .LEHB2-.LFB3670
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3670
.uleb128 .LEHE3-.LEHB3
.uleb128 .L23-.LFB3670
.uleb128 0
.uleb128 .LEHB4-.LFB3670
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3670:
.text
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7computePfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.globl divergence
.align 4
.type divergence, @object
.size divergence, 4
divergence:
.zero 4
.globl num_iterations
.align 4
.type num_iterations, @object
.size num_iterations, 4
num_iterations:
.zero 4
.globl num_threads_per_block
.align 4
.type num_threads_per_block, @object
.size num_threads_per_block, 4
num_threads_per_block:
.zero 4
.globl num_blocks
.align 4
.type num_blocks, @object
.size num_blocks, 4
num_blocks:
.zero 4
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fadd_shd_mem_64p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfiii # -- Begin function _Z22__device_stub__computePfiii
.p2align 4, 0x90
.type _Z22__device_stub__computePfiii,@function
_Z22__device_stub__computePfiii: # @_Z22__device_stub__computePfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfiii, .Lfunc_end0-_Z22__device_stub__computePfiii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB2_35
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
movq %rsi, %r15
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 24(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 40(%r15), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rax
movq %rax, 40(%rsp)
.cfi_escape 0x2e, 0x00
movl $158, %edi
callq _Znwm
movq %rax, %rbp
movq %rax, 40(%rsp)
movq $157, 56(%rsp)
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $157, %edx
movq %rax, %rdi
callq memcpy@PLT
movq $157, 48(%rsp)
movb $0, 157(%rbp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq system
.Ltmp1:
# %bb.2:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq system
.Ltmp3:
# %bb.3:
movq 16(%rsp), %rdi
.Ltmp4:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp5:
# %bb.4:
.Ltmp6:
.cfi_escape 0x2e, 0x00
callq hipProfilerStart
.Ltmp7:
# %bb.5:
movl %r12d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r13d, %edx
orq %rax, %rdx
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp9:
# %bb.6:
testl %eax, %eax
jne .LBB2_9
# %bb.7:
movq d_res(%rip), %rax
movq %rax, 120(%rsp)
movl %ebx, 36(%rsp)
movl %r14d, 32(%rsp)
movl %r15d, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp11:
# %bb.8: # %.noexc20
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
.Ltmp12:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z7computePfiii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp13:
.LBB2_9:
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq hipProfilerStop
.Ltmp15:
# %bb.10:
movq 8(%rsp), %rdi
.Ltmp16:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp17:
# %bb.11:
movq 8(%rsp), %rdi
.Ltmp18:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp19:
# %bb.12:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp20:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp21:
# %bb.13:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq system
.Ltmp23:
# %bb.14:
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.16: # %_ZNSolsEf.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_17
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_24
# %bb.23:
movzbl 67(%r14), %eax
jmp .LBB2_26
.LBB2_24:
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.25: # %.noexc29
movq (%r14), %rax
.Ltmp30:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB2_26: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp32:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.27: # %.noexc31
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.28: # %_ZNSolsEPFRSoS_E.exit
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp37:
# %bb.29:
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp39:
# %bb.30:
.Ltmp40:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp41:
# %bb.31:
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp43:
# %bb.32:
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_34
# %bb.33: # %.critedge.i.i25
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit27
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_35:
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
callq _Z5usagev
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB2_17:
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp45:
# %bb.21: # %.noexc28
.LBB2_18:
.Ltmp46:
movq %rax, %rbx
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp43-.Ltmp0 # Call between .Ltmp0 and .Ltmp43
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp44-.Ltmp43 # Call between .Ltmp43 and .Ltmp44
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end2-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_blocks,@object # @num_blocks
.bss
.globl num_blocks
.p2align 2, 0x0
num_blocks:
.long 0 # 0x0
.size num_blocks, 4
.type num_threads_per_block,@object # @num_threads_per_block
.globl num_threads_per_block
.p2align 2, 0x0
num_threads_per_block:
.long 0 # 0x0
.size num_threads_per_block, 4
.type num_iterations,@object # @num_iterations
.globl num_iterations
.p2align 2, 0x0
num_iterations:
.long 0 # 0x0
.size num_iterations, 4
.type divergence,@object # @divergence
.globl divergence
.p2align 2, 0x0
divergence:
.long 0 # 0x0
.size divergence, 4
.type h_A,@object # @h_A
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfiii,@object # @_Z7computePfiii
.section .rodata,"a",@progbits
.globl _Z7computePfiii
.p2align 3, 0x0
_Z7computePfiii:
.quad _Z22__device_stub__computePfiii
.size _Z7computePfiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUJOULE_DIR/nvml/example/power_monitor 5 > GPUJOULE_DIR/energy_model_ubench/energy_model_data/combined_inst_validation_data/fadd_shd_mem_64p_asm_power.txt &"
.size .L.str.1, 158
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sleep 5"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "killall power_monitor"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Elapsed Time = "
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym d_res
.addrsig_sym _Z7computePfiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
cudaMalloc((void**) &device_A, sizeof(float)*N*length);
cudaMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
cudaMemcpy(device_A, host_A, sizeof(float)*N*length,
cudaMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
cudaMemcpy(host_B, device_B, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(device_A);
cudaFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} | code for sm_80
Function : _Z10vector_sumPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011f40000004800 */
/*0060*/ @!P0 BRA 0x7a0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0090*/ IADD3 R0, R6.reuse, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*00d0*/ @!P0 BRA 0x6c0 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R11, -R6, c[0x0][0x170], RZ ; /* 0x00005c00060b7a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0110*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*0120*/ @!P0 BRA 0x5e0 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x430 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE.U32 R4, R10, R25, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fca00078e0019 */
/*0190*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x0002a2000c1e1900 */
/*01a0*/ IADD3 R8, R10, 0x4, RZ ; /* 0x000000040a087810 */
/* 0x000fc60007ffe0ff */
/*01b0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0002e8000c1e1900 */
/*01c0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000322000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R8, R8, R25, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc600078e0019 */
/*01e0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000368000c1e1900 */
/*01f0*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000f62000c1e1900 */
/*0200*/ IADD3 R2, R10, 0x8, RZ ; /* 0x000000080a027810 */
/* 0x000fc60007ffe0ff */
/*0210*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000404080f7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R8.64+0x8] ; /* 0x00000804080e7981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD.WIDE.U32 R2, R2, R25, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0019 */
/*0240*/ LDG.E R22, [R8.64+0xc] ; /* 0x00000c0408167981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000f62000c1e1900 */
/*0260*/ IADD3 R23, R10, 0xc, RZ ; /* 0x0000000c0a177810 */
/* 0x000fc60007ffe0ff */
/*0270*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f62000c1e1900 */
/*0290*/ IMAD.WIDE.U32 R4, R23, R25, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x002fc600078e0019 */
/*02a0*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R27, [R4.64+0xc] ; /* 0x00000c04041b7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc40007ffe0ff */
/*0300*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0320*/ FADD R0, R19, R0 ; /* 0x0000000013007221 */
/* 0x004fc80000000000 */
/*0330*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fc80000000000 */
/*0340*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x010fc80000000000 */
/*0350*/ FADD R17, R12, R17 ; /* 0x000000110c117221 */
/* 0x020fc80000000000 */
/*0360*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R15, R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R15, R15, R14 ; /* 0x0000000e0f0f7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R22, R15, R22 ; /* 0x000000160f167221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R21, R22, R21 ; /* 0x0000001516157221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R21, R21, R18 ; /* 0x0000001215157221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R26, R26, R25 ; /* 0x000000191a1a7221 */
/* 0x000fc80000000000 */
/*03f0*/ FADD R23, R26, R23 ; /* 0x000000171a177221 */
/* 0x000fc80000000000 */
/*0400*/ FADD R24, R23, R24 ; /* 0x0000001817187221 */
/* 0x000fc80000000000 */
/*0410*/ FADD R0, R24, R27 ; /* 0x0000001b18007221 */
/* 0x000fe20000000000 */
/*0420*/ @P1 BRA 0x170 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x5c0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0450*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0460*/ IMAD.WIDE.U32 R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0005 */
/*0470*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R4, R10, 0x4, RZ ; /* 0x000000040a047810 */
/* 0x000fc60007ffe0ff */
/*0490*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f22000c1e1900 */
/*04b0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0005 */
/*04c0*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000f62000c1e1900 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0520*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fc80000000000 */
/*0550*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fc80000000000 */
/*0560*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x010fc80000000000 */
/*0570*/ FADD R8, R8, R15 ; /* 0x0000000f08087221 */
/* 0x020fc80000000000 */
/*0580*/ FADD R8, R8, R17 ; /* 0x0000001108087221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R8, R8, R19 ; /* 0x0000001308087221 */
/* 0x000fc80000000000 */
/*05a0*/ FADD R8, R8, R21 ; /* 0x0000001508087221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R0, R8, R23 ; /* 0x0000001708007221 */
/* 0x000fe40000000000 */
/*05c0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*05d0*/ @!P0 BRA 0x6c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*05f0*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0003 */
/*0600*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000f62000c1e1900 */
/*0640*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc40007ffe0ff */
/*0650*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0670*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fc80000000000 */
/*0680*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x008fc80000000000 */
/*0690*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x010fc80000000000 */
/*06a0*/ FADD R0, R4, R13 ; /* 0x0000000d04007221 */
/* 0x020fe20000000000 */
/*06b0*/ @P0 BRA 0x5e0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*06c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*06d0*/ @!P0 BRA 0x790 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000b */
/*0700*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0710*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fca0000000f00 */
/*0720*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0750*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0760*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0770*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd40000000000 */
/*0780*/ @P0 BRA 0x700 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0790*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0003e40000004800 */
/*07a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*07b0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*07c0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
cudaMalloc((void**) &device_A, sizeof(float)*N*length);
cudaMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
cudaMemcpy(device_A, host_A, sizeof(float)*N*length,
cudaMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
cudaMemcpy(host_B, device_B, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(device_A);
cudaFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} | .file "tmpxft_001b2cde_00000000-6_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
.type _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii, @function
_Z34__device_stub__Z10vector_sumPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_sumPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii, .-_Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
.globl _Z10vector_sumPfS_ii
.type _Z10vector_sumPfS_ii, @function
_Z10vector_sumPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_sumPfS_ii, .-_Z10vector_sumPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A = ["
.LC1:
.string "\n"
.LC2:
.string "%G,"
.LC3:
.string "]\n"
.LC4:
.string "B = ["
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edx
.L12:
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $50, %eax, %eax
movl %edx, %ecx
subl %eax, %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $500, %rdx
jne .L12
movq %rsp, %rdi
movl $2000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r12
jmp .L15
.L22:
movl $10, %ecx
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
jmp .L13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $500, %rbx
je .L23
.L15:
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $50, %eax, %eax
cmpl %ebx, %eax
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L23:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
addq $40, %r14
leaq .LC2(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10vector_sumPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_sumPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
cudaMalloc((void**) &device_A, sizeof(float)*N*length);
cudaMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
cudaMemcpy(device_A, host_A, sizeof(float)*N*length,
cudaMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
cudaMemcpy(host_B, device_B, sizeof(float)*N, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(device_A);
cudaFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
hipMalloc((void**) &device_A, sizeof(float)*N*length);
hipMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
hipMemcpy(device_A, host_A, sizeof(float)*N*length,
hipMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
hipMemcpy(host_B, device_B, sizeof(float)*N, hipMemcpyDeviceToHost);
// Free device memory
hipFree(device_A);
hipFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
hipMalloc((void**) &device_A, sizeof(float)*N*length);
hipMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
hipMemcpy(device_A, host_A, sizeof(float)*N*length,
hipMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
hipMemcpy(host_B, device_B, sizeof(float)*N, hipMemcpyDeviceToHost);
// Free device memory
hipFree(device_A);
hipFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_sumPfS_ii
.globl _Z10vector_sumPfS_ii
.p2align 8
.type _Z10vector_sumPfS_ii,@function
_Z10vector_sumPfS_ii:
s_load_b32 s4, s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
ds_store_b32 v0, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
ds_load_b32 v1, v0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, s5, v1
s_cbranch_scc0 .LBB0_2
ds_store_b32 v0, v1
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_sumPfS_ii
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_sumPfS_ii, .Lfunc_end0-_Z10vector_sumPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_sumPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10vector_sumPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Hello world for CUDA, with access to the shared memory of the multiprocessors
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__shared__ float sums[10];
// Define a kernel function
__global__ void vector_sum(float* A, float* B, int length, const int N) {
// Take a vector A of length "length" and sum it, putting the result in
// the vector B
// Declare some shared memory to store the sums.
// We need enough floats for each thread to have one
//__shared__ float sums[N];
// Our ID is unique to our thread, so use it as our index
// Initialise our sum
sums[threadIdx.x] = 0;
// Calculate the sum
for (unsigned int i = 0; i < length; i++) {
sums[threadIdx.x] += A[i];
}
B[threadIdx.x] = sums[threadIdx.x];
}
int main() {
// This is the size of our output vector, and the number of threads
const int N = 10;
// This will be the length of our input vectors
int length = 50;
// These will be our vectors on the host
float* host_A; // This contains all input vectors
float* host_B;
// Use this for indices
int i;
// Define our vectors on the host
host_A = (float*) malloc(N*length*sizeof(float));
host_B = (float*) malloc(N*sizeof(float));
// Initialise them
for (i = 0; i < N*length; i++) {
host_A[i] = (float)(i%length);
//host_B[i] = 0.0;
}
// Define our vectors on the GPU
float* device_A;
float* device_B;
hipMalloc((void**) &device_A, sizeof(float)*N*length);
hipMalloc((void**) &device_B, sizeof(float)*N);
// Transfer data to the GPU
hipMemcpy(device_A, host_A, sizeof(float)*N*length,
hipMemcpyHostToDevice);
//cudaMemcpy(device_B, host_B, sizeof(float)*N, cudaMemcpyHostToDevice);
// Call our function; second number is how many threads to use
// The first number is to do with thread blocks...
vector_sum<<<1, N>>>(device_A, device_B, length, N);
// Copy memory back
hipMemcpy(host_B, device_B, sizeof(float)*N, hipMemcpyDeviceToHost);
// Free device memory
hipFree(device_A);
hipFree(device_B);
// Output our results
printf("A = [");
for (i = 0; i < N*length; i++) {
if (i%length == 0) {
printf("\n");
}
printf("%G,", host_A[i]);
}
printf("]\n");
printf("B = [");
for (i = 0; i < N; i++) {
printf("%G,", host_B[i]);
}
printf("]\n");
return 0;
} | .text
.file "shared_memory.hip"
.globl _Z25__device_stub__vector_sumPfS_ii # -- Begin function _Z25__device_stub__vector_sumPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__vector_sumPfS_ii,@function
_Z25__device_stub__vector_sumPfS_ii: # @_Z25__device_stub__vector_sumPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_sumPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_sumPfS_ii, .Lfunc_end0-_Z25__device_stub__vector_sumPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $36, %rcx
imull $50, %ecx, %ecx
movl %eax, %edx
subl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $500, %rax # imm = 0x1F4
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
xorl %r15d, %r15d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 28(%rsp)
movl $10, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_sumPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
decl %r15d
cmpq $500, %r12 # imm = 0x1F4
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $36, %rax
imull $50, %eax, %eax
addl %r15d, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_9
# %bb.10:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_sumPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_sumPfS_ii,@object # @_Z10vector_sumPfS_ii
.section .rodata,"a",@progbits
.globl _Z10vector_sumPfS_ii
.p2align 3, 0x0
_Z10vector_sumPfS_ii:
.quad _Z25__device_stub__vector_sumPfS_ii
.size _Z10vector_sumPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A = ["
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%G,"
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "B = ["
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_sumPfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_sumPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_sumPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10vector_sumPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ STS [R7.X4], RZ ; /* 0x000000ff07007388 */
/* 0x0011f40000004800 */
/*0060*/ @!P0 BRA 0x7a0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0090*/ IADD3 R0, R6.reuse, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*00d0*/ @!P0 BRA 0x6c0 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R11, -R6, c[0x0][0x170], RZ ; /* 0x00005c00060b7a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0110*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*0120*/ @!P0 BRA 0x5e0 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x430 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE.U32 R4, R10, R25, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fca00078e0019 */
/*0190*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x0002a2000c1e1900 */
/*01a0*/ IADD3 R8, R10, 0x4, RZ ; /* 0x000000040a087810 */
/* 0x000fc60007ffe0ff */
/*01b0*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x0002e8000c1e1900 */
/*01c0*/ LDG.E R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000322000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R8, R8, R25, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc600078e0019 */
/*01e0*/ LDG.E R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000368000c1e1900 */
/*01f0*/ LDG.E R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x000f62000c1e1900 */
/*0200*/ IADD3 R2, R10, 0x8, RZ ; /* 0x000000080a027810 */
/* 0x000fc60007ffe0ff */
/*0210*/ LDG.E R15, [R8.64+0x4] ; /* 0x00000404080f7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R8.64+0x8] ; /* 0x00000804080e7981 */
/* 0x000f62000c1e1900 */
/*0230*/ IMAD.WIDE.U32 R2, R2, R25, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0019 */
/*0240*/ LDG.E R22, [R8.64+0xc] ; /* 0x00000c0408167981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000f62000c1e1900 */
/*0260*/ IADD3 R23, R10, 0xc, RZ ; /* 0x0000000c0a177810 */
/* 0x000fc60007ffe0ff */
/*0270*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f62000c1e1900 */
/*0290*/ IMAD.WIDE.U32 R4, R23, R25, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x002fc600078e0019 */
/*02a0*/ LDG.E R26, [R2.64+0xc] ; /* 0x00000c04021a7981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R24, [R4.64+0x8] ; /* 0x0000080404187981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R27, [R4.64+0xc] ; /* 0x00000c04041b7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc40007ffe0ff */
/*0300*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0320*/ FADD R0, R19, R0 ; /* 0x0000000013007221 */
/* 0x004fc80000000000 */
/*0330*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x008fc80000000000 */
/*0340*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x010fc80000000000 */
/*0350*/ FADD R17, R12, R17 ; /* 0x000000110c117221 */
/* 0x020fc80000000000 */
/*0360*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R15, R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R15, R15, R14 ; /* 0x0000000e0f0f7221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R22, R15, R22 ; /* 0x000000160f167221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R21, R22, R21 ; /* 0x0000001516157221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R21, R21, R20 ; /* 0x0000001415157221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R21, R21, R18 ; /* 0x0000001215157221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R26, R21, R26 ; /* 0x0000001a151a7221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R26, R26, R25 ; /* 0x000000191a1a7221 */
/* 0x000fc80000000000 */
/*03f0*/ FADD R23, R26, R23 ; /* 0x000000171a177221 */
/* 0x000fc80000000000 */
/*0400*/ FADD R24, R23, R24 ; /* 0x0000001817187221 */
/* 0x000fc80000000000 */
/*0410*/ FADD R0, R24, R27 ; /* 0x0000001b18007221 */
/* 0x000fe20000000000 */
/*0420*/ @P1 BRA 0x170 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0430*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x5c0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0450*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0460*/ IMAD.WIDE.U32 R2, R10, R5, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0005 */
/*0470*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IADD3 R4, R10, 0x4, RZ ; /* 0x000000040a047810 */
/* 0x000fc60007ffe0ff */
/*0490*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f22000c1e1900 */
/*04b0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0005 */
/*04c0*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000f68000c1e1900 */
/*04e0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R21, [R4.64+0x8] ; /* 0x0000080404157981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R23, [R4.64+0xc] ; /* 0x00000c0404177981 */
/* 0x000f62000c1e1900 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0520*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fc80000000000 */
/*0550*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fc80000000000 */
/*0560*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x010fc80000000000 */
/*0570*/ FADD R8, R8, R15 ; /* 0x0000000f08087221 */
/* 0x020fc80000000000 */
/*0580*/ FADD R8, R8, R17 ; /* 0x0000001108087221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R8, R8, R19 ; /* 0x0000001308087221 */
/* 0x000fc80000000000 */
/*05a0*/ FADD R8, R8, R21 ; /* 0x0000001508087221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R0, R8, R23 ; /* 0x0000001708007221 */
/* 0x000fe40000000000 */
/*05c0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*05d0*/ @!P0 BRA 0x6c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05e0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*05f0*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fca00078e0003 */
/*0600*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000f62000c1e1900 */
/*0640*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc40007ffe0ff */
/*0650*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0670*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fc80000000000 */
/*0680*/ FADD R4, R5, R4 ; /* 0x0000000405047221 */
/* 0x008fc80000000000 */
/*0690*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x010fc80000000000 */
/*06a0*/ FADD R0, R4, R13 ; /* 0x0000000d04007221 */
/* 0x020fe20000000000 */
/*06b0*/ @P0 BRA 0x5e0 ; /* 0xffffff2000000947 */
/* 0x001fea000383ffff */
/*06c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*06d0*/ @!P0 BRA 0x790 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*06f0*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e000b */
/*0700*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0710*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fca0000000f00 */
/*0720*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0750*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0760*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0770*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x004fd40000000000 */
/*0780*/ @P0 BRA 0x700 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0790*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0003e40000004800 */
/*07a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*07b0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*07c0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_sumPfS_ii
.globl _Z10vector_sumPfS_ii
.p2align 8
.type _Z10vector_sumPfS_ii,@function
_Z10vector_sumPfS_ii:
s_load_b32 s4, s[0:1], 0x10
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
ds_store_b32 v0, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
ds_load_b32 v1, v0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, s5, v1
s_cbranch_scc0 .LBB0_2
ds_store_b32 v0, v1
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_sumPfS_ii
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_sumPfS_ii, .Lfunc_end0-_Z10vector_sumPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_sumPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z10vector_sumPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2cde_00000000-6_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
.type _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii, @function
_Z34__device_stub__Z10vector_sumPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_sumPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii, .-_Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
.globl _Z10vector_sumPfS_ii
.type _Z10vector_sumPfS_ii, @function
_Z10vector_sumPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_sumPfS_ii, .-_Z10vector_sumPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A = ["
.LC1:
.string "\n"
.LC2:
.string "%G,"
.LC3:
.string "]\n"
.LC4:
.string "B = ["
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edx
.L12:
movslq %edx, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $50, %eax, %eax
movl %edx, %ecx
subl %eax, %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $500, %rdx
jne .L12
movq %rsp, %rdi
movl $2000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r12
jmp .L15
.L22:
movl $10, %ecx
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10vector_sumPfS_iiPfS_ii
jmp .L13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $500, %rbx
je .L23
.L15:
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $50, %eax, %eax
cmpl %ebx, %eax
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L23:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rbx
addq $40, %r14
leaq .LC2(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10vector_sumPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_sumPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared_memory.hip"
.globl _Z25__device_stub__vector_sumPfS_ii # -- Begin function _Z25__device_stub__vector_sumPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__vector_sumPfS_ii,@function
_Z25__device_stub__vector_sumPfS_ii: # @_Z25__device_stub__vector_sumPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_sumPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_sumPfS_ii, .Lfunc_end0-_Z25__device_stub__vector_sumPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2000, %edi # imm = 0x7D0
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $36, %rcx
imull $50, %ecx, %ecx
movl %eax, %edx
subl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $500, %rax # imm = 0x1F4
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $2000, %edx # imm = 0x7D0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
xorl %r15d, %r15d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 28(%rsp)
movl $10, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_sumPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
decl %r15d
cmpq $500, %r12 # imm = 0x1F4
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $36, %rax
imull $50, %eax, %eax
addl %r15d, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_9
# %bb.10:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_sumPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_sumPfS_ii,@object # @_Z10vector_sumPfS_ii
.section .rodata,"a",@progbits
.globl _Z10vector_sumPfS_ii
.p2align 3, 0x0
_Z10vector_sumPfS_ii:
.quad _Z25__device_stub__vector_sumPfS_ii
.size _Z10vector_sumPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "A = ["
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%G,"
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "B = ["
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_sumPfS_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_sumPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_sumPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} | code for sm_80
Function : _Z6dividePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x004e300000001000 */
/*00e0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x008e620000000000 */
/*00f0*/ FFMA R6, -R4, R7, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000107 */
/*0100*/ FFMA R6, R7, R6, R7 ; /* 0x0000000607067223 */
/* 0x000fc80000000007 */
/*0110*/ FFMA R7, R3, R6, RZ ; /* 0x0000000603077223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R8, -R4, R7, R3 ; /* 0x0000000704087223 */
/* 0x000fc80000000103 */
/*0130*/ FFMA R7, R6, R8, R7 ; /* 0x0000000806077223 */
/* 0x000fe20000000007 */
/*0140*/ @!P0 BRA 0x170 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0150*/ MOV R2, 0x170 ; /* 0x0000017000027802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01d0*/ BSSY B1, 0x820 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01e0*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0200*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0260*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0270*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0280*/ @!P0 BRA 0x400 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02c0*/ @P0 BRA 0x800 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02e0*/ @!P0 BRA 0x7e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0300*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0320*/ @!P1 BRA !P2, 0x7e0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0330*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0340*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0350*/ @P1 BRA 0x7c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0370*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0380*/ @P0 BRA 0x790 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03a0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03b0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*03e0*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*03f0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0410*/ BSSY B2, 0x780 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0420*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0440*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0450*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0460*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0470*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0480*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0490*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04a0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04b0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04d0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*04e0*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0500*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0520*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0530*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0550*/ @!P0 BRA 0x760 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0570*/ @P0 BRA 0x730 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0590*/ @P0 BRA 0x770 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05e0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*05f0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0600*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0610*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0620*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0650*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0660*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0670*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0680*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0690*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06a0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06c0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06d0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06e0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*06f0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0700*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0710*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x770 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x770 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0770*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x810 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07d0*/ BRA 0x810 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07e0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} | .file "tmpxft_001a90bb_00000000-6_divide.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6dividePfS_S_iPfS_S_i
.type _Z30__device_stub__Z6dividePfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6dividePfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6dividePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6dividePfS_S_iPfS_S_i, .-_Z30__device_stub__Z6dividePfS_S_iPfS_S_i
.globl _Z6dividePfS_S_i
.type _Z6dividePfS_S_i, @function
_Z6dividePfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6dividePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6dividePfS_S_i, .-_Z6dividePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6dividePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dividePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6dividePfS_S_i
.globl _Z6dividePfS_S_i
.p2align 8
.type _Z6dividePfS_S_i,@function
_Z6dividePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6dividePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6dividePfS_S_i, .Lfunc_end0-_Z6dividePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6dividePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6dividePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void divide(float *x, float* y ,float* out ,const int size)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < size)
{
out[index] = x[index]/y[index] ;
}
} | .text
.file "divide.hip"
.globl _Z21__device_stub__dividePfS_S_i # -- Begin function _Z21__device_stub__dividePfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__dividePfS_S_i,@function
_Z21__device_stub__dividePfS_S_i: # @_Z21__device_stub__dividePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6dividePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__dividePfS_S_i, .Lfunc_end0-_Z21__device_stub__dividePfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dividePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6dividePfS_S_i,@object # @_Z6dividePfS_S_i
.section .rodata,"a",@progbits
.globl _Z6dividePfS_S_i
.p2align 3, 0x0
_Z6dividePfS_S_i:
.quad _Z21__device_stub__dividePfS_S_i
.size _Z6dividePfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6dividePfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__dividePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6dividePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6dividePfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R4, R0, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x004e300000001000 */
/*00e0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x008e620000000000 */
/*00f0*/ FFMA R6, -R4, R7, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000107 */
/*0100*/ FFMA R6, R7, R6, R7 ; /* 0x0000000607067223 */
/* 0x000fc80000000007 */
/*0110*/ FFMA R7, R3, R6, RZ ; /* 0x0000000603077223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R8, -R4, R7, R3 ; /* 0x0000000704087223 */
/* 0x000fc80000000103 */
/*0130*/ FFMA R7, R6, R8, R7 ; /* 0x0000000806077223 */
/* 0x000fe20000000007 */
/*0140*/ @!P0 BRA 0x170 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0150*/ MOV R2, 0x170 ; /* 0x0000017000027802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01d0*/ BSSY B1, 0x820 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01e0*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0200*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0260*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0270*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0280*/ @!P0 BRA 0x400 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02c0*/ @P0 BRA 0x800 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02e0*/ @!P0 BRA 0x7e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0300*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0320*/ @!P1 BRA !P2, 0x7e0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0330*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0340*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0350*/ @P1 BRA 0x7c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0370*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0380*/ @P0 BRA 0x790 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03a0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03b0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*03e0*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*03f0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0410*/ BSSY B2, 0x780 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0420*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0440*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0450*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0460*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0470*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0480*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0490*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04a0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04b0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04d0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*04e0*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0500*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0520*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0530*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0550*/ @!P0 BRA 0x760 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0570*/ @P0 BRA 0x730 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0590*/ @P0 BRA 0x770 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05e0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*05f0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0600*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0610*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0620*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0650*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0660*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0670*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0680*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0690*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06a0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06c0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06d0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06e0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*06f0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0700*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0710*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x770 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x770 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0770*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x810 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07d0*/ BRA 0x810 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07e0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6dividePfS_S_i
.globl _Z6dividePfS_S_i
.p2align 8
.type _Z6dividePfS_S_i,@function
_Z6dividePfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6dividePfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6dividePfS_S_i, .Lfunc_end0-_Z6dividePfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6dividePfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6dividePfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a90bb_00000000-6_divide.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6dividePfS_S_iPfS_S_i
.type _Z30__device_stub__Z6dividePfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6dividePfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6dividePfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6dividePfS_S_iPfS_S_i, .-_Z30__device_stub__Z6dividePfS_S_iPfS_S_i
.globl _Z6dividePfS_S_i
.type _Z6dividePfS_S_i, @function
_Z6dividePfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6dividePfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6dividePfS_S_i, .-_Z6dividePfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6dividePfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6dividePfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "divide.hip"
.globl _Z21__device_stub__dividePfS_S_i # -- Begin function _Z21__device_stub__dividePfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__dividePfS_S_i,@function
_Z21__device_stub__dividePfS_S_i: # @_Z21__device_stub__dividePfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6dividePfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__dividePfS_S_i, .Lfunc_end0-_Z21__device_stub__dividePfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6dividePfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6dividePfS_S_i,@object # @_Z6dividePfS_S_i
.section .rodata,"a",@progbits
.globl _Z6dividePfS_S_i
.p2align 3, 0x0
_Z6dividePfS_S_i:
.quad _Z21__device_stub__dividePfS_S_i
.size _Z6dividePfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6dividePfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__dividePfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6dividePfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#ifdef LARGE
#define RENDER_WIDTH 1024
#define RENDER_HEIGHT 1024
#else
#define RENDER_WIDTH 128
#define RENDER_HEIGHT 128
#endif
#define TILE_SIZE 16
#define STACK_CAPACITY 128
#define SHARED_MEM_CAP STACK_CAPACITY * RENDER_WIDTH * RENDER_HEIGHT
#define SPP 1024
#define RR_RATE 0.9
#define PI 3.1415926
// BMP Operation
// 文件信息头结构体
typedef struct
{
unsigned int bfSize; // 文件大小 以字节为单位(2-5字节)
unsigned short bfReserved1; // 保留，必须设置为0 (6-7字节)
unsigned short bfReserved2; // 保留，必须设置为0 (8-9字节)
unsigned int bfOffBits; // 从文件头到像素数据的偏移 (10-13字节)
} _BITMAPFILEHEADER;
//图像信息头结构体
typedef struct
{
unsigned int biSize; // 此结构体的大小 (14-17字节)
int biWidth; // 图像的宽 (18-21字节)
int biHeight; // 图像的高 (22-25字节)
unsigned short biPlanes; // 表示bmp图片的平面属，显然显示器只有一个平面，所以恒等于1 (26-27字节)
unsigned short biBitCount; // 一像素所占的位数，一般为24 (28-29字节)
unsigned int biCompression; // 说明图象数据压缩的类型，0为不压缩。 (30-33字节)
unsigned int biSizeImage; // 像素数据所占大小, 这个值应该等于上面文件头结构中bfSize-bfOffBits (34-37字节)
int biXPelsPerMeter; // 说明水平分辨率，用象素/米表示。一般为0 (38-41字节)
int biYPelsPerMeter; // 说明垂直分辨率，用象素/米表示。一般为0 (42-45字节)
unsigned int biClrUsed; // 说明位图实际使用的彩色表中的颜色索引数（设为0的话，则说明使用所有调色板项）。 (46-49字节)
unsigned int biClrImportant; // 说明对图象显示有重要影响的颜色索引的数目，如果是0，表示都重要。(50-53字节)
} _BITMAPINFOHEADER;
__host__ void save_image(unsigned char* target_img, int width, int height)
{
FILE* file_ptr = fopen("RenderResult.bmp", "wb+");
unsigned short fileType = 0x4d42;
_BITMAPFILEHEADER fileHeader;
_BITMAPINFOHEADER infoHeader;
fileHeader.bfSize = (width) * (height) * 3 + 54;
fileHeader.bfReserved1 = 0;
fileHeader.bfReserved2 = 0;
fileHeader.bfOffBits = 54;
infoHeader.biSize = 40;
infoHeader.biWidth = width;
infoHeader.biHeight = height;
infoHeader.biPlanes = 1;
infoHeader.biBitCount = 24;
infoHeader.biCompression = 0;
infoHeader.biSizeImage = (width) * (height) * 3;
infoHeader.biXPelsPerMeter = 0;
infoHeader.biYPelsPerMeter = 0;
infoHeader.biClrUsed = 0;
infoHeader.biClrImportant = 0;
fwrite(&fileType, sizeof(unsigned short), 1, file_ptr);
fwrite(&fileHeader, sizeof(_BITMAPFILEHEADER), 1, file_ptr);
fwrite(&infoHeader, sizeof(_BITMAPINFOHEADER), 1, file_ptr);
fwrite(target_img, sizeof(unsigned char), (height) * (width) * 3, file_ptr);
fclose(file_ptr);
}
// 3D resources
struct Trianle {
float3 tri_a;
float3 tri_b;
float3 tri_c;
float3 normal_line;
bool is_light;
float brdf_rate;
};
/*
// test scene
// Light triagles
#define LIGHT_TRI_COUNT 2
__constant__ float d_light_irradiance = 40;
// object triagles
// No BVH
#define BRDF_rate 0.6
#define OBJ_TRI_COUNT 24
Trianle h_scene_objects[] = {
// light tri
Trianle{float3{110, 110, 300}, float3{110, 190, 300}, float3{190, 110, 300}, float3{0, 0, -1}, true, BRDF_rate},
Trianle{float3{190, 110, 300}, float3{110, 190, 300}, float3{190, 190, 300}, float3{0, 0, -1}, true, BRDF_rate},
// Trianle{float3{110, 110, 301}, float3{110, 190, 301}, float3{190, 110, 301}, float3{0, 0, 1}, true, BRDF_rate},
// Trianle{float3{190, 110, 301}, float3{110, 190, 301}, float3{190, 190, 301}, float3{0, 0, 1}, true, BRDF_rate},
// internal box 100 * 100 * 30
// top
Trianle{float3{100, 100, 100}, float3{200, 100, 100}, float3{100, 200, 100}, float3{0, 0, 1}, false, BRDF_rate},
Trianle{float3{200, 100, 100}, float3{200, 200, 100}, float3{100, 200, 100}, float3{0, 0, 1}, false, BRDF_rate},
// bottom
Trianle{float3{100, 100, 70}, float3{200, 100, 70}, float3{100, 200, 70}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{200, 100, 70}, float3{200, 200, 70}, float3{100, 200, 70}, float3{0, 0, -1}, false, BRDF_rate},
// front
Trianle{float3{100, 100, 100}, float3{200, 100, 100}, float3{100, 100, 70}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{100, 100, 70}, float3{200, 100, 70}, float3{200, 100, 100}, float3{0, -1, 0}, false, BRDF_rate},
// behind
Trianle{float3{100, 200, 100}, float3{200, 200, 100}, float3{100, 200, 70}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{100, 200, 70}, float3{200, 200, 70}, float3{200, 200, 100}, float3{0, 1, 0}, false, BRDF_rate},
// left
Trianle{float3{100, 100, 100}, float3{100, 200, 100}, float3{100, 100, 70}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{100, 100, 70}, float3{100, 200, 70}, float3{100, 200, 100}, float3{-1, 0, 0}, false, BRDF_rate},
// right
Trianle{float3{200, 100, 100}, float3{200, 200, 100}, float3{200, 100, 70}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{200, 100, 70}, float3{200, 200, 70}, float3{200, 200, 100}, float3{1, 0, 0}, false, BRDF_rate},
// general box 300 * 300 * 300.001
// top
Trianle{float3{0, 0, 300.001}, float3{0, 300, 300.001}, float3{300, 0, 300.001}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{0, 300, 300.001}, float3{300, 0, 300.001}, float3{300, 300, 300.001}, float3{0, 0, -1}, false, BRDF_rate},
// bottom
Trianle{float3{0, 0, 0}, float3{0, 300, 0}, float3{300, 0, 0}, float3{0, 0, 1}, false, BRDF_rate},
Trianle{float3{0, 300, 0}, float3{300, 0, 0}, float3{300, 300, 0}, float3{0, 0, 1}, false, BRDF_rate},
// left
Trianle{float3{0, 0, 0}, float3{0, 0, 300.001}, float3{0, 300, 300.001}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{0, 300, 300.001}, float3{0, 300, 0}, float3{0, 0, 0}, float3{1, 0, 0}, false, BRDF_rate},
// right
Trianle{float3{300, 0, 0}, float3{300, 0, 300.001}, float3{300, 300, 300.001}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{300, 300, 300.001}, float3{300, 300, 0}, float3{300, 0, 0}, float3{-1, 0, 0}, false, BRDF_rate},
// behind
Trianle{float3{0, 300, 0}, float3{0, 300, 300.001}, float3{300, 300, 0}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{300, 300, 0}, float3{300, 300, 300.001}, float3{0, 300, 300.001}, float3{0, -1, 0}, false, BRDF_rate}
};
__constant__ Trianle d_scene_objects[OBJ_TRI_COUNT];
// camera position
__constant__ float3 d_camera_position = float3{150, -400, 150};
__constant__ float3 d_camera_direction = float3{0, 1, 0};
__constant__ float3 d_camera_up_direction = float3{0, 0, 1};
__constant__ float3 d_camera_left_direction = float3{1, 0, 0};
// 浮点精度考虑，设置较大焦距和成像平面
__constant__ float d_camera_focal_length = 200;
__constant__ float d_camera_width = 150;
__constant__ float d_camera_height = 150;
__constant__ float d_camera_pixel_width = 150.0 / RENDER_WIDTH;
__constant__ float d_camera_pixel_height= 150.0 / RENDER_HEIGHT;
*/
// Cornell box
#define LIGHT_TRI_COUNT 2
__constant__ float d_light_irradiance = 42;
#define BRDF_rate 0.74
#define OBJ_TRI_COUNT 32
// Trianle{float3{}, float3{}, float3{}, float3{}, false, BRDF_rate},
Trianle h_scene_objects[] = {
// Light triagles
Trianle{float3{343.0, 548.799, 227.0}, float3{343.0, 548.799, 332.0}, float3{213.0, 548.799, 332.0}, float3{0, -1, 0}, true, BRDF_rate},
Trianle{float3{343.0, 548.799, 227.0}, float3{213.0, 548.799, 227.0}, float3{213.0, 548.799, 332.0}, float3{0, -1, 0}, true, BRDF_rate},
// Floor
Trianle{float3{552.8, 0.0, 0.0}, float3{0.0, 0.0, 0.0}, float3{0.0, 0.0, 559.2}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{552.8, 0.0, 0.0}, float3{549.6, 0.0, 559.2}, float3{0.0, 0.0, 559.2}, float3{0, 1, 0}, false, BRDF_rate},
// Ceiling
Trianle{float3{556.0, 548.8, 0.0}, float3{556.0, 548.8, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{556.0, 548.8, 0.0}, float3{0.0, 548.8, 0.0}, float3{0.0, 548.8, 559.2}, float3{0, -1, 0}, false, BRDF_rate},
// Back wall
Trianle{float3{549.6, 0.0, 559.2}, float3{0.0, 0.0, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{549.6, 0.0, 559.2}, float3{556.0, 548.8, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, 0, -1}, false, BRDF_rate},
// Right wall
Trianle{float3{0.0, 0.0, 559.2}, float3{0.0, 0.0, 0.0}, float3{0.0, 548.8, 0.0}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{0.0, 0.0, 559.2}, float3{0.0, 548.8, 559.2}, float3{0.0, 548.8, 0.0}, float3{1, 0, 0}, false, BRDF_rate},
// Left wall
Trianle{float3{552.8, 0.0, 0.0}, float3{549.6, 0.0, 559.2}, float3{556.0, 548.8, 559.2}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{552.8, 0.0, 0.0}, float3{556.0, 548.8, 0.0}, float3{556.0, 548.8, 559.2}, float3{-1, 0, 0}, false, BRDF_rate},
// Short block
// Top
Trianle{float3{130.0, 165.0, 65.0}, float3{82.0, 165.0, 225.0}, float3{240.0, 165.0, 272.0}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{130.0, 165.0, 65.0}, float3{290.0, 165.0, 114.0}, float3{240.0, 165.0, 272.0}, float3{0, 1, 0}, false, BRDF_rate},
// Left
Trianle{float3{290.0, 0.0, 114.0}, float3{290.0, 165.0, 114.0}, float3{240.0, 165.0, 272.0}, float3{-0.9534, 0, -0.301709}, false, BRDF_rate},
Trianle{float3{290.0, 0.0, 114.0}, float3{240.0, 0.0, 272.0}, float3{240.0, 165.0, 272.0}, float3{-0.9534, 0, -0.301709}, false, BRDF_rate},
// Front
Trianle{float3{130.0, 0.0, 65.0}, float3{130.0, 165.0, 65.0}, float3{290.0, 165.0, 114.0}, float3{-0.292826, 0, -0.956166}, false, BRDF_rate},
Trianle{float3{130.0, 0.0, 65.0}, float3{290.0, 0.0, 114.0}, float3{290.0, 165.0, 114.0}, float3{-0.292826, 0, -0.956166}, false, BRDF_rate},
// Right
Trianle{float3{82.0, 0.0, 225.0}, float3{82.0, 165.0, 225.0}, float3{130.0, 165.0, 65.0}, float3{-0.957826, 0, -0.287348}, false, BRDF_rate},
Trianle{float3{82.0, 0.0, 225.0}, float3{130.0, 0.0, 65.0}, float3{130.0, 165.0, 65.0}, float3{-0.957826, 0, -0.287348}, false, BRDF_rate},
// Behind
Trianle{float3{240.0, 0.0, 272.0}, float3{240.0, 165.0, 272.0}, float3{82.0, 165.0, 225.0}, float3{-0.285121, 0, -0.958492}, false, BRDF_rate},
Trianle{float3{240.0, 0.0, 272.0}, float3{82.0, 0.0, 225.0}, float3{82.0, 165.0, 225.0}, float3{-0.285121, 0, -0.958492}, false, BRDF_rate},
// Tall block
// Top
Trianle{float3{423.0, 330.0, 247.0}, float3{265.0, 330.0, 296.0}, float3{314.0, 330.0, 456.0}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{423.0, 330.0, 247.0}, float3{472.0, 330.0, 406.0}, float3{314.0, 330.0, 456.0}, float3{0, 1, 0}, false, BRDF_rate},
// Left
Trianle{float3{423.0, 0.0, 247.0}, float3{423.0, 330.0, 247.0}, float3{472.0, 330.0, 406.0}, float3{0.955649, 0, -0.294508}, false, BRDF_rate},
Trianle{float3{423.0, 0.0, 247.0}, float3{472.0, 0.0, 406.0}, float3{472.0, 330.0, 406.0}, float3{0.955649, 0, -0.294508}, false, BRDF_rate},
// Behind
Trianle{float3{472.0, 0.0, 406.0}, float3{472.0, 330.0, 406.0}, float3{314.0, 330.0, 456.0}, float3{-0.301709, 0, -0.953400}, false, BRDF_rate},
Trianle{float3{472.0, 0.0, 406.0}, float3{314.0, 0.0, 456.0}, float3{314.0, 330.0, 456.0}, float3{-0.301709, 0, -0.953400}, false, BRDF_rate},
// Right
Trianle{float3{314.0, 0.0, 456.0}, float3{314.0, 330.0, 456.0}, float3{265.0, 330.0, 296.0}, float3{0.956166, 0, -0.292826}, false, BRDF_rate},
Trianle{float3{314.0, 0.0, 456.0}, float3{265.0, 0.0, 296.0}, float3{265.0, 330.0, 296.0}, float3{0.956166, 0, -0.292826}, false, BRDF_rate},
// Front
Trianle{float3{265.0, 0.0, 296.0}, float3{265.0, 330.0, 296.0}, float3{423.0, 330.0, 247.0}, float3{0.296209, 0, 0.955123}, false, BRDF_rate},
Trianle{float3{265.0, 0.0, 296.0}, float3{423.0, 0.0, 247.0}, float3{423.0, 330.0, 247.0}, float3{-0.296209, 0, -0.955123}, false, BRDF_rate}
};
__constant__ Trianle d_scene_objects[OBJ_TRI_COUNT];
// camera position
__constant__ float3 d_camera_position = float3{278, 273, -800};
__constant__ float3 d_camera_direction = float3{0, 0, 1};
__constant__ float3 d_camera_up_direction = float3{0, 1, 0};
__constant__ float3 d_camera_left_direction = float3{-1, 0, 0};
__constant__ float d_camera_focal_length = 3.5;
__constant__ float d_camera_width = 2.5;
__constant__ float d_camera_height = 2.5;
__constant__ float d_camera_pixel_width = 2.5 / RENDER_WIDTH;
__constant__ float d_camera_pixel_height= 2.5 / RENDER_HEIGHT;
__device__ inline float mixed_product(float3 vec_a, float3 vec_b, float3 vec_c)
{
return vec_a.x * (vec_b.y * vec_c.z - vec_b.z * vec_c.y) +
vec_a.y * (vec_b.z * vec_c.x - vec_b.x * vec_c.z) +
vec_a.z * (vec_b.x * vec_c.y - vec_b.y * vec_c.x);
}
__device__ inline float3 sub_float3(float3 opr1, float3 opr2)
{
return make_float3(opr1.x - opr2.x, opr1.y - opr2.y, opr1.z - opr2.z);
}
__device__ inline float3 scalar_mult_float3(float3 vec, float scalar)
{
return make_float3(vec.x * scalar, vec.y * scalar, vec.z * scalar);
}
__device__ float dot(float3 opr1, float3 opr2)
{
return opr1.x * opr2.x + opr1.y * opr2.y + opr1.z * opr2.z;
}
__device__ inline float3 add_float3(float3 opr1, float3 opr2)
{
return make_float3(opr1.x + opr2.x, opr1.y + opr2.y, opr1.z + opr2.z);
}
__device__ float size(Trianle triangle)
{
float3 vec1 = sub_float3(triangle.tri_b, triangle.tri_a);
float3 vec2 = sub_float3(triangle.tri_c, triangle.tri_a);
float3 cross_product = make_float3(vec1.y * vec2.z - vec1.z * vec2.y, vec1.z * vec2.x - vec1.x * vec2.z, vec1.x * vec2.y - vec1.y * vec2.x);
return 0.5 * norm3df(cross_product.x, cross_product.y, cross_product.z);
}
__device__ float3 check_obj_hit(int src_tri_idx, float3 src_point, float3 direction, int& hit_obj_idx)
{
// normalize direction
float div_length = 1 / norm3df(direction.x, direction.y, direction.z);
float3 normal_direction = make_float3(direction.x * div_length, direction.y * div_length, direction.z * div_length);
hit_obj_idx = -1;
float3 hit_point;
float min_distance = 2147483647;
for (int i = 0; i < OBJ_TRI_COUNT; ++i) {
if (i == src_tri_idx) {
continue;
}
// make shadow
Trianle shadow_tri = Trianle{sub_float3(d_scene_objects[i].tri_a, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_a, src_point)))),
sub_float3(d_scene_objects[i].tri_b, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_b, src_point)))),
sub_float3(d_scene_objects[i].tri_c, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_c, src_point)))),
normal_direction};
// check in center
float3 vec_pa = sub_float3(shadow_tri.tri_a, src_point);
float3 vec_pb = sub_float3(shadow_tri.tri_b, src_point);
float3 vec_pc = sub_float3(shadow_tri.tri_c, src_point);
float papb = mixed_product(normal_direction, vec_pa, vec_pb);
float pbpc = mixed_product(normal_direction, vec_pb, vec_pc);
float pcpa = mixed_product(normal_direction, vec_pc, vec_pa);
if ((papb > 0 && pbpc > 0 && pcpa > 0) || (papb < 0 && pbpc < 0 && pcpa < 0)) {
// in center
// get hit point
// get coordinary, reuse vec_pb ,vec_pc
vec_pb = sub_float3(shadow_tri.tri_b, shadow_tri.tri_a);
vec_pc = sub_float3(shadow_tri.tri_c, shadow_tri.tri_a);
vec_pa = sub_float3(src_point, shadow_tri.tri_a);
float divider = vec_pb.x * vec_pc.y - vec_pb.y * vec_pc.x;
float rate_a = (vec_pc.y * vec_pa.x - vec_pc.x * vec_pa.y) / divider;
float rate_b = (-vec_pb.y * vec_pa.x + vec_pb.x * vec_pa.y) / divider;
vec_pb = sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a);
vec_pc = sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a);
vec_pa.x = d_scene_objects[i].tri_a.x + rate_a * vec_pb.x + rate_b * vec_pc.x;
vec_pa.y = d_scene_objects[i].tri_a.y + rate_a * vec_pb.y + rate_b * vec_pc.y;
vec_pa.z = d_scene_objects[i].tri_a.z + rate_a * vec_pb.z + rate_b * vec_pc.z;
float distance = dot(sub_float3(vec_pa, src_point), normal_direction);
// printf("Rate : %f %f %f\n", rate_a, rate_b, distance / norm3df(vec_pa.x - src_point.x, vec_pa.y - src_point.y, vec_pa.z - src_point.z));
if (distance > 0) {
// printf("In Center : %f, %f, %f %f\n", papb, pbpc, pcpa, distance);
// ray will hit object
if (distance < min_distance) {
min_distance = distance;
hit_point = vec_pa;
hit_obj_idx = i;
}
}
}
}
// printf("Src : %d Dst : %d Direction : %f, %f, %f\n", src_tri_idx, hit_obj_idx, direction.x, direction.y, direction.z);
return hit_point;
}
__device__ float3 check_light_hit(int src_tri_idx, float3 src_point, float3 direction, int& hit_obj_idx)
{
float3 hit_point = check_obj_hit(src_tri_idx, src_point, direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
hit_obj_idx = -1;
}
return hit_point;
}
/*
__device__ float shade_recurse(int object_idx, float3 src_point, float3 direction, curandState* curand_state)
{
// Contribution from the light source.
float l_dir = 0;
for (int i = 0; i < LIGHT_TRI_COUNT; ++i) {
// random select a point on light triangle
float rand_x = curand_uniform(curand_state);
float rand_y = curand_uniform(curand_state);
if (rand_x + rand_y > 1) {
rand_x = 1 - rand_x;
rand_y = 1 - rand_y;
}
float3 random_point = add_float3(d_scene_objects[i].tri_a, add_float3(scalar_mult_float3(sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a), rand_x), scalar_mult_float3(sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a), rand_y)));
// test block
float3 obj_light_direction = sub_float3(random_point, src_point);
int test_block_idx;
check_obj_hit(-1, src_point, obj_light_direction, test_block_idx);
// printf("Direction %f %f %f %d\n", obj_light_direction.x, obj_light_direction.y, obj_light_direction.z, test_block_idx);
if (test_block_idx == i) {
// printf("Hit Light!\n");
float direction_length_square = obj_light_direction.x * obj_light_direction.x + obj_light_direction.y * obj_light_direction.y + obj_light_direction.z * obj_light_direction.z;
l_dir += d_light_irradiance * BRDF_rate * dot(d_scene_objects[object_idx].normal_line, obj_light_direction) * -1 * dot(d_scene_objects[i].normal_line, obj_light_direction)
/ direction_length_square / direction_length_square * size(d_scene_objects[i]);
// printf("Shade %d %f %f\n", i, dot(d_light_triangle[i].normal_line, obj_light_direction), l_dir);
}
}
return l_dir;
// Contribution from other reflectors.
float l_indir = 0;
// test Russian Roulette
float rr_result = curand_uniform(curand_state);
if (rr_result < RR_RATE) {
// random select a ray from src_point
float cosine_theta = 2 * (curand_uniform(curand_state) - 0.5);
float sine_theta = sqrtf(1 - cosine_theta * cosine_theta);
float fai_value = 2 * PI * curand_uniform(curand_state);
float3 ray_direction = make_float3(sine_theta * cosf(fai_value), sine_theta * sinf(fai_value), cosine_theta);
if (dot(ray_direction, d_scene_objects[object_idx].normal_line) < 0) {
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
cosine_theta *= -1;
}
int hit_obj_idx;
float3 hit_point = check_obj_hit(object_idx, src_point, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
// printf("Hit Object!\n");
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
l_indir = shade(hit_obj_idx, hit_point, ray_direction, curand_state) * BRDF_rate * dot(ray_direction, d_scene_objects[hit_obj_idx].normal_line) * 2 * PI / RR_RATE;
}
}
// printf("Shade %f\n", l_dir + l_indir);
return l_dir + l_indir;
}
*/
__device__ float stack_dir[SHARED_MEM_CAP];
__device__ float stack_indir_rate[SHARED_MEM_CAP];
__device__ float shade(int object_idx, float3 src_point, float3 direction, curandState* curand_state)
{
// __shared__ float stack_dir[SHARED_MEM_CAP];
// __shared__ float stack_indir_rate[SHARED_MEM_CAP];
// int stack_size = 0;
float l_dir = 0;
int stack_offset = ((blockIdx.y * TILE_SIZE + threadIdx.y) * RENDER_WIDTH + (blockIdx.x * TILE_SIZE + threadIdx.x)) * STACK_CAPACITY;
int stack_ori = stack_offset;
float3 out_direction = direction; // use in BRDF, here is ignored.
float3 ray_src = src_point;
int src_object_idx = object_idx;
while (true) {
// Contribution from the light source.
l_dir = 0;
for (int i = 0; i < LIGHT_TRI_COUNT; ++i) {
// random select a point on light triangle
float rand_x = curand_uniform(curand_state);
float rand_y = curand_uniform(curand_state);
if (rand_x + rand_y > 1) {
rand_x = 1 - rand_x;
rand_y = 1 - rand_y;
}
float3 random_point = add_float3(d_scene_objects[i].tri_a, add_float3(scalar_mult_float3(sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a), rand_x), scalar_mult_float3(sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a), rand_y)));
// test block
float3 obj_light_direction = sub_float3(random_point, ray_src);
int test_block_idx;
check_obj_hit(-1, ray_src, obj_light_direction, test_block_idx);
// printf("Direction %f %f %f %d\n", obj_light_direction.x, obj_light_direction.y, obj_light_direction.z, test_block_idx);
if (test_block_idx == i) {
// printf("Hit Light!\n");
float direction_length_square = obj_light_direction.x * obj_light_direction.x + obj_light_direction.y * obj_light_direction.y + obj_light_direction.z * obj_light_direction.z;
l_dir += d_light_irradiance * d_scene_objects[src_object_idx].brdf_rate * fabs(dot(d_scene_objects[src_object_idx].normal_line, obj_light_direction) * dot(d_scene_objects[i].normal_line, obj_light_direction))
/ direction_length_square / direction_length_square * size(d_scene_objects[i]);
}
}
// Contribution from other reflectors.
// test Russian Roulette
float rr_result = curand_uniform(curand_state);
if (rr_result < RR_RATE) {
float indir_rate = 0;
// random select a ray from src_point
float cosine_theta = 2 * (curand_uniform(curand_state) - 0.5);
float sine_theta = sqrtf(1 - cosine_theta * cosine_theta);
float fai_value = 2 * PI * curand_uniform(curand_state);
float3 ray_direction = make_float3(sine_theta * cosf(fai_value), sine_theta * sinf(fai_value), cosine_theta);
if (dot(ray_direction, d_scene_objects[src_object_idx].normal_line) * dot(out_direction, d_scene_objects[src_object_idx].normal_line) < 0) {
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
cosine_theta *= -1;
}
int hit_obj_idx;
float3 hit_point = check_obj_hit(src_object_idx, ray_src, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
// printf("Hit Object!\n");
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
indir_rate = d_scene_objects[hit_obj_idx].brdf_rate * fabs(dot(ray_direction, d_scene_objects[hit_obj_idx].normal_line)) / RR_RATE;
src_object_idx = hit_obj_idx;
ray_src = hit_point;
out_direction = ray_direction;
stack_dir[stack_offset] = l_dir;
stack_indir_rate[stack_offset] = indir_rate;
++stack_offset;
}
else {
// stack_dir[stack_offset] = l_dir;
// stack_indir_rate[stack_offset] = indir_rate;
// ++stack_offset;
break;
}
}
else {
break;
}
}
// calc final irradiance
for (int i = stack_offset - 1; i >= stack_ori; --i) {
// printf("%f %f\n", stack_indir_rate[i], stack_dir[i]);
l_dir *= stack_indir_rate[i];
l_dir += stack_dir[i];
}
return l_dir;
}
__device__ __forceinline__ float ray_generation(float3 pixel_center_position, curandState* curand_states)
{
float pixel_radiance = 0;
for (int i = 0; i < SPP; ++i) {
float width_bias = d_camera_pixel_width * (curand_uniform(&curand_states[threadIdx.x]) - 0.5);
float height_bias = d_camera_pixel_height * (curand_uniform(&curand_states[threadIdx.x]) - 0.5);
int hit_obj_idx;
// printf("Pixel bias : %f %f\n", width_bias, height_bias);
float3 ray_direction = sub_float3(add_float3(pixel_center_position, make_float3(width_bias, 0, height_bias)), d_camera_position);
float3 hit_light_point = check_light_hit(-1, d_camera_position, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1) {
// printf("Ray Hit!\n");
pixel_radiance += 1.0 / SPP * d_light_irradiance;
}
else {
float3 hit_point = check_obj_hit(-1, d_camera_position, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1) {
// printf("Obj Hit!\n");
float3 reverse_ray_direction = make_float3(-ray_direction.x, -ray_direction.y, -ray_direction.z);
pixel_radiance += 1.0 / SPP * shade(hit_obj_idx, hit_point, reverse_ray_direction, &curand_states[threadIdx.x]);
// printf("Ray Obj General : %f\n", pixel_radiance);
}
}
}
// printf("Ray General : %f\n", 1.0 / SPP * d_light_irradiance);
return pixel_radiance;
}
__global__ void render_pixel(unsigned char* target_img, curandState* curand_states)
{
int target_pixel_width = blockIdx.x * TILE_SIZE + threadIdx.x;
int target_pixel_height = blockIdx.y * TILE_SIZE + threadIdx.y;
// printf("%d, %d\n", target_pixel_width, target_pixel_height);
// printf("%f %f %f\n", d_camera_position.x, d_camera_position.y, d_camera_position.z);
float3 delta_left = scalar_mult_float3(d_camera_left_direction, (target_pixel_width + 0.5 - RENDER_WIDTH / 2.0) * d_camera_pixel_width);
float3 delta_up = scalar_mult_float3(d_camera_up_direction, (target_pixel_height + 0.5 - RENDER_HEIGHT / 2.0) * d_camera_pixel_height);
float3 delta = add_float3(delta_left, add_float3(delta_up, scalar_mult_float3(d_camera_direction, d_camera_focal_length)));
// float3 delta = make_float3((target_pixel_width + 0.5 - RENDER_WIDTH / 2.0) * d_camera_pixel_width, d_camera_focal_length, (target_pixel_height + 0.5 - RENDER_HEIGHT / 2.0) * d_camera_pixel_height);
float3 pixel_center = make_float3(d_camera_position.x + delta.x, d_camera_position.y + delta.y, d_camera_position.z + delta.z);
float pixel_radiance = ray_generation(pixel_center, curand_states);
// float pixel_radiance = d_light_irradiance * curand_uniform(&curand_states[threadIdx.x]);
// Gamma correction
pixel_radiance /= d_light_irradiance;
if (pixel_radiance > 1) {
pixel_radiance = 1;
}
pixel_radiance = powf(pixel_radiance, 0.454545454545);
unsigned char rgb_value = (unsigned char)(pixel_radiance * 255);
// printf("%d, %d : %d\n", target_pixel_width, target_pixel_height, rgb_value);
int base_idx = 3 * (target_pixel_height * RENDER_WIDTH + target_pixel_width);
target_img[base_idx] = rgb_value;
target_img[base_idx + 1] = rgb_value;
target_img[base_idx + 2] = rgb_value;
}
__global__ void init_curand(curandState* curand_states, int seed)
{
curand_init(seed, threadIdx.x, 0, &(curand_states[threadIdx.x]));
}
int main()
{
dim3 grid{RENDER_WIDTH / TILE_SIZE, RENDER_HEIGHT / TILE_SIZE, 1};
dim3 block{TILE_SIZE, TILE_SIZE, 1};
unsigned char* d_target_img;
cudaMalloc(&d_target_img, RENDER_WIDTH * RENDER_HEIGHT * 3);
curandState* curand_states;
cudaMalloc(&curand_states, TILE_SIZE * sizeof(curandState));
init_curand <<<1, TILE_SIZE>>> (curand_states, 0);
cudaDeviceSynchronize();
cudaError_t cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "curand init launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
// cudaMemcpyToSymbol(d_light_triangle, h_light_triangle, sizeof(Trianle) * LIGHT_TRI_COUNT, cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_scene_objects, h_scene_objects, sizeof(h_scene_objects));
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "before render launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
render_pixel <<<grid, block>>> (d_target_img, curand_states);
unsigned char* h_target_img = (unsigned char*)malloc(RENDER_WIDTH * RENDER_HEIGHT * 3);
cudaDeviceSynchronize();
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "render launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
cudaMemcpy(h_target_img, d_target_img, RENDER_WIDTH * RENDER_HEIGHT * 3, cudaMemcpyDeviceToHost);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "copy launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
save_image(h_target_img, RENDER_WIDTH, RENDER_HEIGHT);
free(h_target_img);
cudaFree(d_target_img);
cudaFree(curand_states);
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#ifdef LARGE
#define RENDER_WIDTH 1024
#define RENDER_HEIGHT 1024
#else
#define RENDER_WIDTH 128
#define RENDER_HEIGHT 128
#endif
#define TILE_SIZE 16
#define STACK_CAPACITY 128
#define SHARED_MEM_CAP STACK_CAPACITY * RENDER_WIDTH * RENDER_HEIGHT
#define SPP 1024
#define RR_RATE 0.9
#define PI 3.1415926
// BMP Operation
// 文件信息头结构体
typedef struct
{
unsigned int bfSize; // 文件大小 以字节为单位(2-5字节)
unsigned short bfReserved1; // 保留，必须设置为0 (6-7字节)
unsigned short bfReserved2; // 保留，必须设置为0 (8-9字节)
unsigned int bfOffBits; // 从文件头到像素数据的偏移 (10-13字节)
} _BITMAPFILEHEADER;
//图像信息头结构体
typedef struct
{
unsigned int biSize; // 此结构体的大小 (14-17字节)
int biWidth; // 图像的宽 (18-21字节)
int biHeight; // 图像的高 (22-25字节)
unsigned short biPlanes; // 表示bmp图片的平面属，显然显示器只有一个平面，所以恒等于1 (26-27字节)
unsigned short biBitCount; // 一像素所占的位数，一般为24 (28-29字节)
unsigned int biCompression; // 说明图象数据压缩的类型，0为不压缩。 (30-33字节)
unsigned int biSizeImage; // 像素数据所占大小, 这个值应该等于上面文件头结构中bfSize-bfOffBits (34-37字节)
int biXPelsPerMeter; // 说明水平分辨率，用象素/米表示。一般为0 (38-41字节)
int biYPelsPerMeter; // 说明垂直分辨率，用象素/米表示。一般为0 (42-45字节)
unsigned int biClrUsed; // 说明位图实际使用的彩色表中的颜色索引数（设为0的话，则说明使用所有调色板项）。 (46-49字节)
unsigned int biClrImportant; // 说明对图象显示有重要影响的颜色索引的数目，如果是0，表示都重要。(50-53字节)
} _BITMAPINFOHEADER;
__host__ void save_image(unsigned char* target_img, int width, int height)
{
FILE* file_ptr = fopen("RenderResult.bmp", "wb+");
unsigned short fileType = 0x4d42;
_BITMAPFILEHEADER fileHeader;
_BITMAPINFOHEADER infoHeader;
fileHeader.bfSize = (width) * (height) * 3 + 54;
fileHeader.bfReserved1 = 0;
fileHeader.bfReserved2 = 0;
fileHeader.bfOffBits = 54;
infoHeader.biSize = 40;
infoHeader.biWidth = width;
infoHeader.biHeight = height;
infoHeader.biPlanes = 1;
infoHeader.biBitCount = 24;
infoHeader.biCompression = 0;
infoHeader.biSizeImage = (width) * (height) * 3;
infoHeader.biXPelsPerMeter = 0;
infoHeader.biYPelsPerMeter = 0;
infoHeader.biClrUsed = 0;
infoHeader.biClrImportant = 0;
fwrite(&fileType, sizeof(unsigned short), 1, file_ptr);
fwrite(&fileHeader, sizeof(_BITMAPFILEHEADER), 1, file_ptr);
fwrite(&infoHeader, sizeof(_BITMAPINFOHEADER), 1, file_ptr);
fwrite(target_img, sizeof(unsigned char), (height) * (width) * 3, file_ptr);
fclose(file_ptr);
}
// 3D resources
struct Trianle {
float3 tri_a;
float3 tri_b;
float3 tri_c;
float3 normal_line;
bool is_light;
float brdf_rate;
};
/*
// test scene
// Light triagles
#define LIGHT_TRI_COUNT 2
__constant__ float d_light_irradiance = 40;
// object triagles
// No BVH
#define BRDF_rate 0.6
#define OBJ_TRI_COUNT 24
Trianle h_scene_objects[] = {
// light tri
Trianle{float3{110, 110, 300}, float3{110, 190, 300}, float3{190, 110, 300}, float3{0, 0, -1}, true, BRDF_rate},
Trianle{float3{190, 110, 300}, float3{110, 190, 300}, float3{190, 190, 300}, float3{0, 0, -1}, true, BRDF_rate},
// Trianle{float3{110, 110, 301}, float3{110, 190, 301}, float3{190, 110, 301}, float3{0, 0, 1}, true, BRDF_rate},
// Trianle{float3{190, 110, 301}, float3{110, 190, 301}, float3{190, 190, 301}, float3{0, 0, 1}, true, BRDF_rate},
// internal box 100 * 100 * 30
// top
Trianle{float3{100, 100, 100}, float3{200, 100, 100}, float3{100, 200, 100}, float3{0, 0, 1}, false, BRDF_rate},
Trianle{float3{200, 100, 100}, float3{200, 200, 100}, float3{100, 200, 100}, float3{0, 0, 1}, false, BRDF_rate},
// bottom
Trianle{float3{100, 100, 70}, float3{200, 100, 70}, float3{100, 200, 70}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{200, 100, 70}, float3{200, 200, 70}, float3{100, 200, 70}, float3{0, 0, -1}, false, BRDF_rate},
// front
Trianle{float3{100, 100, 100}, float3{200, 100, 100}, float3{100, 100, 70}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{100, 100, 70}, float3{200, 100, 70}, float3{200, 100, 100}, float3{0, -1, 0}, false, BRDF_rate},
// behind
Trianle{float3{100, 200, 100}, float3{200, 200, 100}, float3{100, 200, 70}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{100, 200, 70}, float3{200, 200, 70}, float3{200, 200, 100}, float3{0, 1, 0}, false, BRDF_rate},
// left
Trianle{float3{100, 100, 100}, float3{100, 200, 100}, float3{100, 100, 70}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{100, 100, 70}, float3{100, 200, 70}, float3{100, 200, 100}, float3{-1, 0, 0}, false, BRDF_rate},
// right
Trianle{float3{200, 100, 100}, float3{200, 200, 100}, float3{200, 100, 70}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{200, 100, 70}, float3{200, 200, 70}, float3{200, 200, 100}, float3{1, 0, 0}, false, BRDF_rate},
// general box 300 * 300 * 300.001
// top
Trianle{float3{0, 0, 300.001}, float3{0, 300, 300.001}, float3{300, 0, 300.001}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{0, 300, 300.001}, float3{300, 0, 300.001}, float3{300, 300, 300.001}, float3{0, 0, -1}, false, BRDF_rate},
// bottom
Trianle{float3{0, 0, 0}, float3{0, 300, 0}, float3{300, 0, 0}, float3{0, 0, 1}, false, BRDF_rate},
Trianle{float3{0, 300, 0}, float3{300, 0, 0}, float3{300, 300, 0}, float3{0, 0, 1}, false, BRDF_rate},
// left
Trianle{float3{0, 0, 0}, float3{0, 0, 300.001}, float3{0, 300, 300.001}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{0, 300, 300.001}, float3{0, 300, 0}, float3{0, 0, 0}, float3{1, 0, 0}, false, BRDF_rate},
// right
Trianle{float3{300, 0, 0}, float3{300, 0, 300.001}, float3{300, 300, 300.001}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{300, 300, 300.001}, float3{300, 300, 0}, float3{300, 0, 0}, float3{-1, 0, 0}, false, BRDF_rate},
// behind
Trianle{float3{0, 300, 0}, float3{0, 300, 300.001}, float3{300, 300, 0}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{300, 300, 0}, float3{300, 300, 300.001}, float3{0, 300, 300.001}, float3{0, -1, 0}, false, BRDF_rate}
};
__constant__ Trianle d_scene_objects[OBJ_TRI_COUNT];
// camera position
__constant__ float3 d_camera_position = float3{150, -400, 150};
__constant__ float3 d_camera_direction = float3{0, 1, 0};
__constant__ float3 d_camera_up_direction = float3{0, 0, 1};
__constant__ float3 d_camera_left_direction = float3{1, 0, 0};
// 浮点精度考虑，设置较大焦距和成像平面
__constant__ float d_camera_focal_length = 200;
__constant__ float d_camera_width = 150;
__constant__ float d_camera_height = 150;
__constant__ float d_camera_pixel_width = 150.0 / RENDER_WIDTH;
__constant__ float d_camera_pixel_height= 150.0 / RENDER_HEIGHT;
*/
// Cornell box
#define LIGHT_TRI_COUNT 2
__constant__ float d_light_irradiance = 42;
#define BRDF_rate 0.74
#define OBJ_TRI_COUNT 32
// Trianle{float3{}, float3{}, float3{}, float3{}, false, BRDF_rate},
Trianle h_scene_objects[] = {
// Light triagles
Trianle{float3{343.0, 548.799, 227.0}, float3{343.0, 548.799, 332.0}, float3{213.0, 548.799, 332.0}, float3{0, -1, 0}, true, BRDF_rate},
Trianle{float3{343.0, 548.799, 227.0}, float3{213.0, 548.799, 227.0}, float3{213.0, 548.799, 332.0}, float3{0, -1, 0}, true, BRDF_rate},
// Floor
Trianle{float3{552.8, 0.0, 0.0}, float3{0.0, 0.0, 0.0}, float3{0.0, 0.0, 559.2}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{552.8, 0.0, 0.0}, float3{549.6, 0.0, 559.2}, float3{0.0, 0.0, 559.2}, float3{0, 1, 0}, false, BRDF_rate},
// Ceiling
Trianle{float3{556.0, 548.8, 0.0}, float3{556.0, 548.8, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, -1, 0}, false, BRDF_rate},
Trianle{float3{556.0, 548.8, 0.0}, float3{0.0, 548.8, 0.0}, float3{0.0, 548.8, 559.2}, float3{0, -1, 0}, false, BRDF_rate},
// Back wall
Trianle{float3{549.6, 0.0, 559.2}, float3{0.0, 0.0, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, 0, -1}, false, BRDF_rate},
Trianle{float3{549.6, 0.0, 559.2}, float3{556.0, 548.8, 559.2}, float3{0.0, 548.8, 559.2}, float3{0, 0, -1}, false, BRDF_rate},
// Right wall
Trianle{float3{0.0, 0.0, 559.2}, float3{0.0, 0.0, 0.0}, float3{0.0, 548.8, 0.0}, float3{1, 0, 0}, false, BRDF_rate},
Trianle{float3{0.0, 0.0, 559.2}, float3{0.0, 548.8, 559.2}, float3{0.0, 548.8, 0.0}, float3{1, 0, 0}, false, BRDF_rate},
// Left wall
Trianle{float3{552.8, 0.0, 0.0}, float3{549.6, 0.0, 559.2}, float3{556.0, 548.8, 559.2}, float3{-1, 0, 0}, false, BRDF_rate},
Trianle{float3{552.8, 0.0, 0.0}, float3{556.0, 548.8, 0.0}, float3{556.0, 548.8, 559.2}, float3{-1, 0, 0}, false, BRDF_rate},
// Short block
// Top
Trianle{float3{130.0, 165.0, 65.0}, float3{82.0, 165.0, 225.0}, float3{240.0, 165.0, 272.0}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{130.0, 165.0, 65.0}, float3{290.0, 165.0, 114.0}, float3{240.0, 165.0, 272.0}, float3{0, 1, 0}, false, BRDF_rate},
// Left
Trianle{float3{290.0, 0.0, 114.0}, float3{290.0, 165.0, 114.0}, float3{240.0, 165.0, 272.0}, float3{-0.9534, 0, -0.301709}, false, BRDF_rate},
Trianle{float3{290.0, 0.0, 114.0}, float3{240.0, 0.0, 272.0}, float3{240.0, 165.0, 272.0}, float3{-0.9534, 0, -0.301709}, false, BRDF_rate},
// Front
Trianle{float3{130.0, 0.0, 65.0}, float3{130.0, 165.0, 65.0}, float3{290.0, 165.0, 114.0}, float3{-0.292826, 0, -0.956166}, false, BRDF_rate},
Trianle{float3{130.0, 0.0, 65.0}, float3{290.0, 0.0, 114.0}, float3{290.0, 165.0, 114.0}, float3{-0.292826, 0, -0.956166}, false, BRDF_rate},
// Right
Trianle{float3{82.0, 0.0, 225.0}, float3{82.0, 165.0, 225.0}, float3{130.0, 165.0, 65.0}, float3{-0.957826, 0, -0.287348}, false, BRDF_rate},
Trianle{float3{82.0, 0.0, 225.0}, float3{130.0, 0.0, 65.0}, float3{130.0, 165.0, 65.0}, float3{-0.957826, 0, -0.287348}, false, BRDF_rate},
// Behind
Trianle{float3{240.0, 0.0, 272.0}, float3{240.0, 165.0, 272.0}, float3{82.0, 165.0, 225.0}, float3{-0.285121, 0, -0.958492}, false, BRDF_rate},
Trianle{float3{240.0, 0.0, 272.0}, float3{82.0, 0.0, 225.0}, float3{82.0, 165.0, 225.0}, float3{-0.285121, 0, -0.958492}, false, BRDF_rate},
// Tall block
// Top
Trianle{float3{423.0, 330.0, 247.0}, float3{265.0, 330.0, 296.0}, float3{314.0, 330.0, 456.0}, float3{0, 1, 0}, false, BRDF_rate},
Trianle{float3{423.0, 330.0, 247.0}, float3{472.0, 330.0, 406.0}, float3{314.0, 330.0, 456.0}, float3{0, 1, 0}, false, BRDF_rate},
// Left
Trianle{float3{423.0, 0.0, 247.0}, float3{423.0, 330.0, 247.0}, float3{472.0, 330.0, 406.0}, float3{0.955649, 0, -0.294508}, false, BRDF_rate},
Trianle{float3{423.0, 0.0, 247.0}, float3{472.0, 0.0, 406.0}, float3{472.0, 330.0, 406.0}, float3{0.955649, 0, -0.294508}, false, BRDF_rate},
// Behind
Trianle{float3{472.0, 0.0, 406.0}, float3{472.0, 330.0, 406.0}, float3{314.0, 330.0, 456.0}, float3{-0.301709, 0, -0.953400}, false, BRDF_rate},
Trianle{float3{472.0, 0.0, 406.0}, float3{314.0, 0.0, 456.0}, float3{314.0, 330.0, 456.0}, float3{-0.301709, 0, -0.953400}, false, BRDF_rate},
// Right
Trianle{float3{314.0, 0.0, 456.0}, float3{314.0, 330.0, 456.0}, float3{265.0, 330.0, 296.0}, float3{0.956166, 0, -0.292826}, false, BRDF_rate},
Trianle{float3{314.0, 0.0, 456.0}, float3{265.0, 0.0, 296.0}, float3{265.0, 330.0, 296.0}, float3{0.956166, 0, -0.292826}, false, BRDF_rate},
// Front
Trianle{float3{265.0, 0.0, 296.0}, float3{265.0, 330.0, 296.0}, float3{423.0, 330.0, 247.0}, float3{0.296209, 0, 0.955123}, false, BRDF_rate},
Trianle{float3{265.0, 0.0, 296.0}, float3{423.0, 0.0, 247.0}, float3{423.0, 330.0, 247.0}, float3{-0.296209, 0, -0.955123}, false, BRDF_rate}
};
__constant__ Trianle d_scene_objects[OBJ_TRI_COUNT];
// camera position
__constant__ float3 d_camera_position = float3{278, 273, -800};
__constant__ float3 d_camera_direction = float3{0, 0, 1};
__constant__ float3 d_camera_up_direction = float3{0, 1, 0};
__constant__ float3 d_camera_left_direction = float3{-1, 0, 0};
__constant__ float d_camera_focal_length = 3.5;
__constant__ float d_camera_width = 2.5;
__constant__ float d_camera_height = 2.5;
__constant__ float d_camera_pixel_width = 2.5 / RENDER_WIDTH;
__constant__ float d_camera_pixel_height= 2.5 / RENDER_HEIGHT;
__device__ inline float mixed_product(float3 vec_a, float3 vec_b, float3 vec_c)
{
return vec_a.x * (vec_b.y * vec_c.z - vec_b.z * vec_c.y) +
vec_a.y * (vec_b.z * vec_c.x - vec_b.x * vec_c.z) +
vec_a.z * (vec_b.x * vec_c.y - vec_b.y * vec_c.x);
}
__device__ inline float3 sub_float3(float3 opr1, float3 opr2)
{
return make_float3(opr1.x - opr2.x, opr1.y - opr2.y, opr1.z - opr2.z);
}
__device__ inline float3 scalar_mult_float3(float3 vec, float scalar)
{
return make_float3(vec.x * scalar, vec.y * scalar, vec.z * scalar);
}
__device__ float dot(float3 opr1, float3 opr2)
{
return opr1.x * opr2.x + opr1.y * opr2.y + opr1.z * opr2.z;
}
__device__ inline float3 add_float3(float3 opr1, float3 opr2)
{
return make_float3(opr1.x + opr2.x, opr1.y + opr2.y, opr1.z + opr2.z);
}
__device__ float size(Trianle triangle)
{
float3 vec1 = sub_float3(triangle.tri_b, triangle.tri_a);
float3 vec2 = sub_float3(triangle.tri_c, triangle.tri_a);
float3 cross_product = make_float3(vec1.y * vec2.z - vec1.z * vec2.y, vec1.z * vec2.x - vec1.x * vec2.z, vec1.x * vec2.y - vec1.y * vec2.x);
return 0.5 * norm3df(cross_product.x, cross_product.y, cross_product.z);
}
__device__ float3 check_obj_hit(int src_tri_idx, float3 src_point, float3 direction, int& hit_obj_idx)
{
// normalize direction
float div_length = 1 / norm3df(direction.x, direction.y, direction.z);
float3 normal_direction = make_float3(direction.x * div_length, direction.y * div_length, direction.z * div_length);
hit_obj_idx = -1;
float3 hit_point;
float min_distance = 2147483647;
for (int i = 0; i < OBJ_TRI_COUNT; ++i) {
if (i == src_tri_idx) {
continue;
}
// make shadow
Trianle shadow_tri = Trianle{sub_float3(d_scene_objects[i].tri_a, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_a, src_point)))),
sub_float3(d_scene_objects[i].tri_b, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_b, src_point)))),
sub_float3(d_scene_objects[i].tri_c, scalar_mult_float3(normal_direction, dot(normal_direction, sub_float3(d_scene_objects[i].tri_c, src_point)))),
normal_direction};
// check in center
float3 vec_pa = sub_float3(shadow_tri.tri_a, src_point);
float3 vec_pb = sub_float3(shadow_tri.tri_b, src_point);
float3 vec_pc = sub_float3(shadow_tri.tri_c, src_point);
float papb = mixed_product(normal_direction, vec_pa, vec_pb);
float pbpc = mixed_product(normal_direction, vec_pb, vec_pc);
float pcpa = mixed_product(normal_direction, vec_pc, vec_pa);
if ((papb > 0 && pbpc > 0 && pcpa > 0) || (papb < 0 && pbpc < 0 && pcpa < 0)) {
// in center
// get hit point
// get coordinary, reuse vec_pb ,vec_pc
vec_pb = sub_float3(shadow_tri.tri_b, shadow_tri.tri_a);
vec_pc = sub_float3(shadow_tri.tri_c, shadow_tri.tri_a);
vec_pa = sub_float3(src_point, shadow_tri.tri_a);
float divider = vec_pb.x * vec_pc.y - vec_pb.y * vec_pc.x;
float rate_a = (vec_pc.y * vec_pa.x - vec_pc.x * vec_pa.y) / divider;
float rate_b = (-vec_pb.y * vec_pa.x + vec_pb.x * vec_pa.y) / divider;
vec_pb = sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a);
vec_pc = sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a);
vec_pa.x = d_scene_objects[i].tri_a.x + rate_a * vec_pb.x + rate_b * vec_pc.x;
vec_pa.y = d_scene_objects[i].tri_a.y + rate_a * vec_pb.y + rate_b * vec_pc.y;
vec_pa.z = d_scene_objects[i].tri_a.z + rate_a * vec_pb.z + rate_b * vec_pc.z;
float distance = dot(sub_float3(vec_pa, src_point), normal_direction);
// printf("Rate : %f %f %f\n", rate_a, rate_b, distance / norm3df(vec_pa.x - src_point.x, vec_pa.y - src_point.y, vec_pa.z - src_point.z));
if (distance > 0) {
// printf("In Center : %f, %f, %f %f\n", papb, pbpc, pcpa, distance);
// ray will hit object
if (distance < min_distance) {
min_distance = distance;
hit_point = vec_pa;
hit_obj_idx = i;
}
}
}
}
// printf("Src : %d Dst : %d Direction : %f, %f, %f\n", src_tri_idx, hit_obj_idx, direction.x, direction.y, direction.z);
return hit_point;
}
__device__ float3 check_light_hit(int src_tri_idx, float3 src_point, float3 direction, int& hit_obj_idx)
{
float3 hit_point = check_obj_hit(src_tri_idx, src_point, direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
hit_obj_idx = -1;
}
return hit_point;
}
/*
__device__ float shade_recurse(int object_idx, float3 src_point, float3 direction, curandState* curand_state)
{
// Contribution from the light source.
float l_dir = 0;
for (int i = 0; i < LIGHT_TRI_COUNT; ++i) {
// random select a point on light triangle
float rand_x = curand_uniform(curand_state);
float rand_y = curand_uniform(curand_state);
if (rand_x + rand_y > 1) {
rand_x = 1 - rand_x;
rand_y = 1 - rand_y;
}
float3 random_point = add_float3(d_scene_objects[i].tri_a, add_float3(scalar_mult_float3(sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a), rand_x), scalar_mult_float3(sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a), rand_y)));
// test block
float3 obj_light_direction = sub_float3(random_point, src_point);
int test_block_idx;
check_obj_hit(-1, src_point, obj_light_direction, test_block_idx);
// printf("Direction %f %f %f %d\n", obj_light_direction.x, obj_light_direction.y, obj_light_direction.z, test_block_idx);
if (test_block_idx == i) {
// printf("Hit Light!\n");
float direction_length_square = obj_light_direction.x * obj_light_direction.x + obj_light_direction.y * obj_light_direction.y + obj_light_direction.z * obj_light_direction.z;
l_dir += d_light_irradiance * BRDF_rate * dot(d_scene_objects[object_idx].normal_line, obj_light_direction) * -1 * dot(d_scene_objects[i].normal_line, obj_light_direction)
/ direction_length_square / direction_length_square * size(d_scene_objects[i]);
// printf("Shade %d %f %f\n", i, dot(d_light_triangle[i].normal_line, obj_light_direction), l_dir);
}
}
return l_dir;
// Contribution from other reflectors.
float l_indir = 0;
// test Russian Roulette
float rr_result = curand_uniform(curand_state);
if (rr_result < RR_RATE) {
// random select a ray from src_point
float cosine_theta = 2 * (curand_uniform(curand_state) - 0.5);
float sine_theta = sqrtf(1 - cosine_theta * cosine_theta);
float fai_value = 2 * PI * curand_uniform(curand_state);
float3 ray_direction = make_float3(sine_theta * cosf(fai_value), sine_theta * sinf(fai_value), cosine_theta);
if (dot(ray_direction, d_scene_objects[object_idx].normal_line) < 0) {
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
cosine_theta *= -1;
}
int hit_obj_idx;
float3 hit_point = check_obj_hit(object_idx, src_point, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
// printf("Hit Object!\n");
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
l_indir = shade(hit_obj_idx, hit_point, ray_direction, curand_state) * BRDF_rate * dot(ray_direction, d_scene_objects[hit_obj_idx].normal_line) * 2 * PI / RR_RATE;
}
}
// printf("Shade %f\n", l_dir + l_indir);
return l_dir + l_indir;
}
*/
__device__ float stack_dir[SHARED_MEM_CAP];
__device__ float stack_indir_rate[SHARED_MEM_CAP];
__device__ float shade(int object_idx, float3 src_point, float3 direction, hiprandState* curand_state)
{
// __shared__ float stack_dir[SHARED_MEM_CAP];
// __shared__ float stack_indir_rate[SHARED_MEM_CAP];
// int stack_size = 0;
float l_dir = 0;
int stack_offset = ((blockIdx.y * TILE_SIZE + threadIdx.y) * RENDER_WIDTH + (blockIdx.x * TILE_SIZE + threadIdx.x)) * STACK_CAPACITY;
int stack_ori = stack_offset;
float3 out_direction = direction; // use in BRDF, here is ignored.
float3 ray_src = src_point;
int src_object_idx = object_idx;
while (true) {
// Contribution from the light source.
l_dir = 0;
for (int i = 0; i < LIGHT_TRI_COUNT; ++i) {
// random select a point on light triangle
float rand_x = hiprand_uniform(curand_state);
float rand_y = hiprand_uniform(curand_state);
if (rand_x + rand_y > 1) {
rand_x = 1 - rand_x;
rand_y = 1 - rand_y;
}
float3 random_point = add_float3(d_scene_objects[i].tri_a, add_float3(scalar_mult_float3(sub_float3(d_scene_objects[i].tri_b, d_scene_objects[i].tri_a), rand_x), scalar_mult_float3(sub_float3(d_scene_objects[i].tri_c, d_scene_objects[i].tri_a), rand_y)));
// test block
float3 obj_light_direction = sub_float3(random_point, ray_src);
int test_block_idx;
check_obj_hit(-1, ray_src, obj_light_direction, test_block_idx);
// printf("Direction %f %f %f %d\n", obj_light_direction.x, obj_light_direction.y, obj_light_direction.z, test_block_idx);
if (test_block_idx == i) {
// printf("Hit Light!\n");
float direction_length_square = obj_light_direction.x * obj_light_direction.x + obj_light_direction.y * obj_light_direction.y + obj_light_direction.z * obj_light_direction.z;
l_dir += d_light_irradiance * d_scene_objects[src_object_idx].brdf_rate * fabs(dot(d_scene_objects[src_object_idx].normal_line, obj_light_direction) * dot(d_scene_objects[i].normal_line, obj_light_direction))
/ direction_length_square / direction_length_square * size(d_scene_objects[i]);
}
}
// Contribution from other reflectors.
// test Russian Roulette
float rr_result = hiprand_uniform(curand_state);
if (rr_result < RR_RATE) {
float indir_rate = 0;
// random select a ray from src_point
float cosine_theta = 2 * (hiprand_uniform(curand_state) - 0.5);
float sine_theta = sqrtf(1 - cosine_theta * cosine_theta);
float fai_value = 2 * PI * hiprand_uniform(curand_state);
float3 ray_direction = make_float3(sine_theta * cosf(fai_value), sine_theta * sinf(fai_value), cosine_theta);
if (dot(ray_direction, d_scene_objects[src_object_idx].normal_line) * dot(out_direction, d_scene_objects[src_object_idx].normal_line) < 0) {
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
cosine_theta *= -1;
}
int hit_obj_idx;
float3 hit_point = check_obj_hit(src_object_idx, ray_src, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1 && !d_scene_objects[hit_obj_idx].is_light) {
// printf("Hit Object!\n");
ray_direction.x *= -1;
ray_direction.y *= -1;
ray_direction.z *= -1;
indir_rate = d_scene_objects[hit_obj_idx].brdf_rate * fabs(dot(ray_direction, d_scene_objects[hit_obj_idx].normal_line)) / RR_RATE;
src_object_idx = hit_obj_idx;
ray_src = hit_point;
out_direction = ray_direction;
stack_dir[stack_offset] = l_dir;
stack_indir_rate[stack_offset] = indir_rate;
++stack_offset;
}
else {
// stack_dir[stack_offset] = l_dir;
// stack_indir_rate[stack_offset] = indir_rate;
// ++stack_offset;
break;
}
}
else {
break;
}
}
// calc final irradiance
for (int i = stack_offset - 1; i >= stack_ori; --i) {
// printf("%f %f\n", stack_indir_rate[i], stack_dir[i]);
l_dir *= stack_indir_rate[i];
l_dir += stack_dir[i];
}
return l_dir;
}
__device__ __forceinline__ float ray_generation(float3 pixel_center_position, hiprandState* curand_states)
{
float pixel_radiance = 0;
for (int i = 0; i < SPP; ++i) {
float width_bias = d_camera_pixel_width * (hiprand_uniform(&curand_states[threadIdx.x]) - 0.5);
float height_bias = d_camera_pixel_height * (hiprand_uniform(&curand_states[threadIdx.x]) - 0.5);
int hit_obj_idx;
// printf("Pixel bias : %f %f\n", width_bias, height_bias);
float3 ray_direction = sub_float3(add_float3(pixel_center_position, make_float3(width_bias, 0, height_bias)), d_camera_position);
float3 hit_light_point = check_light_hit(-1, d_camera_position, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1) {
// printf("Ray Hit!\n");
pixel_radiance += 1.0 / SPP * d_light_irradiance;
}
else {
float3 hit_point = check_obj_hit(-1, d_camera_position, ray_direction, hit_obj_idx);
if (hit_obj_idx > -1) {
// printf("Obj Hit!\n");
float3 reverse_ray_direction = make_float3(-ray_direction.x, -ray_direction.y, -ray_direction.z);
pixel_radiance += 1.0 / SPP * shade(hit_obj_idx, hit_point, reverse_ray_direction, &curand_states[threadIdx.x]);
// printf("Ray Obj General : %f\n", pixel_radiance);
}
}
}
// printf("Ray General : %f\n", 1.0 / SPP * d_light_irradiance);
return pixel_radiance;
}
__global__ void render_pixel(unsigned char* target_img, hiprandState* curand_states)
{
int target_pixel_width = blockIdx.x * TILE_SIZE + threadIdx.x;
int target_pixel_height = blockIdx.y * TILE_SIZE + threadIdx.y;
// printf("%d, %d\n", target_pixel_width, target_pixel_height);
// printf("%f %f %f\n", d_camera_position.x, d_camera_position.y, d_camera_position.z);
float3 delta_left = scalar_mult_float3(d_camera_left_direction, (target_pixel_width + 0.5 - RENDER_WIDTH / 2.0) * d_camera_pixel_width);
float3 delta_up = scalar_mult_float3(d_camera_up_direction, (target_pixel_height + 0.5 - RENDER_HEIGHT / 2.0) * d_camera_pixel_height);
float3 delta = add_float3(delta_left, add_float3(delta_up, scalar_mult_float3(d_camera_direction, d_camera_focal_length)));
// float3 delta = make_float3((target_pixel_width + 0.5 - RENDER_WIDTH / 2.0) * d_camera_pixel_width, d_camera_focal_length, (target_pixel_height + 0.5 - RENDER_HEIGHT / 2.0) * d_camera_pixel_height);
float3 pixel_center = make_float3(d_camera_position.x + delta.x, d_camera_position.y + delta.y, d_camera_position.z + delta.z);
float pixel_radiance = ray_generation(pixel_center, curand_states);
// float pixel_radiance = d_light_irradiance * curand_uniform(&curand_states[threadIdx.x]);
// Gamma correction
pixel_radiance /= d_light_irradiance;
if (pixel_radiance > 1) {
pixel_radiance = 1;
}
pixel_radiance = powf(pixel_radiance, 0.454545454545);
unsigned char rgb_value = (unsigned char)(pixel_radiance * 255);
// printf("%d, %d : %d\n", target_pixel_width, target_pixel_height, rgb_value);
int base_idx = 3 * (target_pixel_height * RENDER_WIDTH + target_pixel_width);
target_img[base_idx] = rgb_value;
target_img[base_idx + 1] = rgb_value;
target_img[base_idx + 2] = rgb_value;
}
__global__ void init_curand(hiprandState* curand_states, int seed)
{
hiprand_init(seed, threadIdx.x, 0, &(curand_states[threadIdx.x]));
}
int main()
{
dim3 grid{RENDER_WIDTH / TILE_SIZE, RENDER_HEIGHT / TILE_SIZE, 1};
dim3 block{TILE_SIZE, TILE_SIZE, 1};
unsigned char* d_target_img;
hipMalloc(&d_target_img, RENDER_WIDTH * RENDER_HEIGHT * 3);
hiprandState* curand_states;
hipMalloc(&curand_states, TILE_SIZE * sizeof(hiprandState));
init_curand <<<1, TILE_SIZE>>> (curand_states, 0);
hipDeviceSynchronize();
hipError_t cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hiprand init launch failed: %s\n", hipGetErrorString(cudaStatus));
}
// cudaMemcpyToSymbol(d_light_triangle, h_light_triangle, sizeof(Trianle) * LIGHT_TRI_COUNT, cudaMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_scene_objects), h_scene_objects, sizeof(h_scene_objects));
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "before render launch failed: %s\n", hipGetErrorString(cudaStatus));
}
render_pixel <<<grid, block>>> (d_target_img, curand_states);
unsigned char* h_target_img = (unsigned char*)malloc(RENDER_WIDTH * RENDER_HEIGHT * 3);
hipDeviceSynchronize();
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "render launch failed: %s\n", hipGetErrorString(cudaStatus));
}
hipMemcpy(h_target_img, d_target_img, RENDER_WIDTH * RENDER_HEIGHT * 3, hipMemcpyDeviceToHost);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "copy launch failed: %s\n", hipGetErrorString(cudaStatus));
}
save_image(h_target_img, RENDER_WIDTH, RENDER_HEIGHT);
free(h_target_img);
hipFree(d_target_img);
hipFree(curand_states);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Colour Sine wave Kernal
// Based on kernal_colour in kernelVBO.cpp by Rob Farber
__global__ void kernel(float4* dVertexArray, uchar4 *dColorArray,
unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// Each thread is unique point (u,v) in interval [-1,1],[-1,1]
const float u = 2.0f* (x/(float)width) - 1.0f;
const float v = 2.0f* (y/(float)height) - 1.0f;
const float w = 0.5f * sinf(4.0f*u + time) * cosf(4.0f*v + time);
// Update vertex array for point
dVertexArray[y*width+x] = make_float4(u, w, v, 1.0f);
// Update colour array for point
dColorArray[y*width+x].w = 0.0f;
dColorArray[y*width+x].x = 255.0f *0.5f*(1.f+sinf(w+x));
dColorArray[y*width+x].y = 255.0f *0.5f*(1.f+sinf(x)*cosf(y));
dColorArray[y*width+x].z = 255.0f *0.5f*(1.f+sinf(w+time/10.0f));
}
extern "C" void launch_kernel(float4* dVertexArray, uchar4* dColourArray,
unsigned int width, unsigned int height, float time)
{
dim3 block(8, 8, 1);
dim3 grid(width / block.x, height / block.y, 1);
kernel<<< grid, block>>>(dVertexArray, dColourArray, width, height, time);
} | .file "tmpxft_000bfa6f_00000000-6_kernal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
.type _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf, @function
_Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP6float4P6uchar4jjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf, .-_Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
.globl _Z6kernelP6float4P6uchar4jjf
.type _Z6kernelP6float4P6uchar4jjf, @function
_Z6kernelP6float4P6uchar4jjf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6kernelP6float4P6uchar4jjf, .-_Z6kernelP6float4P6uchar4jjf
.globl launch_kernel
.type launch_kernel, @function
launch_kernel:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movss %xmm0, 12(%rsp)
movl %edx, %eax
shrl $3, %eax
movl %eax, 36(%rsp)
movl %ecx, %eax
shrl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
jmp .L11
.cfi_endproc
.LFE2027:
.size launch_kernel, .-launch_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP6float4P6uchar4jjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP6float4P6uchar4jjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Colour Sine wave Kernal
// Based on kernal_colour in kernelVBO.cpp by Rob Farber
__global__ void kernel(float4* dVertexArray, uchar4 *dColorArray,
unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// Each thread is unique point (u,v) in interval [-1,1],[-1,1]
const float u = 2.0f* (x/(float)width) - 1.0f;
const float v = 2.0f* (y/(float)height) - 1.0f;
const float w = 0.5f * sinf(4.0f*u + time) * cosf(4.0f*v + time);
// Update vertex array for point
dVertexArray[y*width+x] = make_float4(u, w, v, 1.0f);
// Update colour array for point
dColorArray[y*width+x].w = 0.0f;
dColorArray[y*width+x].x = 255.0f *0.5f*(1.f+sinf(w+x));
dColorArray[y*width+x].y = 255.0f *0.5f*(1.f+sinf(x)*cosf(y));
dColorArray[y*width+x].z = 255.0f *0.5f*(1.f+sinf(w+time/10.0f));
}
extern "C" void launch_kernel(float4* dVertexArray, uchar4* dColourArray,
unsigned int width, unsigned int height, float time)
{
dim3 block(8, 8, 1);
dim3 grid(width / block.x, height / block.y, 1);
kernel<<< grid, block>>>(dVertexArray, dColourArray, width, height, time);
} | #include <hip/hip_runtime.h>
// Colour Sine wave Kernal
// Based on kernal_colour in kernelVBO.cpp by Rob Farber
__global__ void kernel(float4* dVertexArray, uchar4 *dColorArray,
unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// Each thread is unique point (u,v) in interval [-1,1],[-1,1]
const float u = 2.0f* (x/(float)width) - 1.0f;
const float v = 2.0f* (y/(float)height) - 1.0f;
const float w = 0.5f * sinf(4.0f*u + time) * cosf(4.0f*v + time);
// Update vertex array for point
dVertexArray[y*width+x] = make_float4(u, w, v, 1.0f);
// Update colour array for point
dColorArray[y*width+x].w = 0.0f;
dColorArray[y*width+x].x = 255.0f *0.5f*(1.f+sinf(w+x));
dColorArray[y*width+x].y = 255.0f *0.5f*(1.f+sinf(x)*cosf(y));
dColorArray[y*width+x].z = 255.0f *0.5f*(1.f+sinf(w+time/10.0f));
}
extern "C" void launch_kernel(float4* dVertexArray, uchar4* dColourArray,
unsigned int width, unsigned int height, float time)
{
dim3 block(8, 8, 1);
dim3 grid(width / block.x, height / block.y, 1);
kernel<<< grid, block>>>(dVertexArray, dColourArray, width, height, time);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Colour Sine wave Kernal
// Based on kernal_colour in kernelVBO.cpp by Rob Farber
__global__ void kernel(float4* dVertexArray, uchar4 *dColorArray,
unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// Each thread is unique point (u,v) in interval [-1,1],[-1,1]
const float u = 2.0f* (x/(float)width) - 1.0f;
const float v = 2.0f* (y/(float)height) - 1.0f;
const float w = 0.5f * sinf(4.0f*u + time) * cosf(4.0f*v + time);
// Update vertex array for point
dVertexArray[y*width+x] = make_float4(u, w, v, 1.0f);
// Update colour array for point
dColorArray[y*width+x].w = 0.0f;
dColorArray[y*width+x].x = 255.0f *0.5f*(1.f+sinf(w+x));
dColorArray[y*width+x].y = 255.0f *0.5f*(1.f+sinf(x)*cosf(y));
dColorArray[y*width+x].z = 255.0f *0.5f*(1.f+sinf(w+time/10.0f));
}
extern "C" void launch_kernel(float4* dVertexArray, uchar4* dColourArray,
unsigned int width, unsigned int height, float time)
{
dim3 block(8, 8, 1);
dim3 grid(width / block.x, height / block.y, 1);
kernel<<< grid, block>>>(dVertexArray, dColourArray, width, height, time);
} | .text
.file "kernal.hip"
.globl _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf # -- Begin function _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.p2align 4, 0x90
.type _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf,@function
_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf: # @_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, .Lfunc_end0-_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.cfi_endproc
# -- End function
.globl launch_kernel # -- Begin function launch_kernel
.p2align 4, 0x90
.type launch_kernel,@function
launch_kernel: # @launch_kernel
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, (%rsp) # 4-byte Spill
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %eax
shrl $3, %eax
movl %ecx, %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size launch_kernel, .Lfunc_end1-launch_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf,@object # @_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.section .rodata,"a",@progbits
.globl _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.p2align 3, 0x0
_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf:
.quad _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.size _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bfa6f_00000000-6_kernal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
.type _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf, @function
_Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP6float4P6uchar4jjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf, .-_Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
.globl _Z6kernelP6float4P6uchar4jjf
.type _Z6kernelP6float4P6uchar4jjf, @function
_Z6kernelP6float4P6uchar4jjf:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6kernelP6float4P6uchar4jjf, .-_Z6kernelP6float4P6uchar4jjf
.globl launch_kernel
.type launch_kernel, @function
launch_kernel:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movss %xmm0, 12(%rsp)
movl %edx, %eax
shrl $3, %eax
movl %eax, 36(%rsp)
movl %ecx, %eax
shrl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z42__device_stub__Z6kernelP6float4P6uchar4jjfP6float4P6uchar4jjf
jmp .L11
.cfi_endproc
.LFE2027:
.size launch_kernel, .-launch_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP6float4P6uchar4jjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP6float4P6uchar4jjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernal.hip"
.globl _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf # -- Begin function _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.p2align 4, 0x90
.type _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf,@function
_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf: # @_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, .Lfunc_end0-_Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.cfi_endproc
# -- End function
.globl launch_kernel # -- Begin function launch_kernel
.p2align 4, 0x90
.type launch_kernel,@function
launch_kernel: # @launch_kernel
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movss %xmm0, (%rsp) # 4-byte Spill
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %eax
shrl $3, %eax
movl %ecx, %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size launch_kernel, .Lfunc_end1-launch_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf,@object # @_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.section .rodata,"a",@progbits
.globl _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.p2align 3, 0x0
_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf:
.quad _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.size _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP15HIP_vector_typeIfLj4EEPS_IhLj4EEjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <cstdio>
#include <iostream>
#include "canny.cuh"
using namespace std;
// __global__ functions can't be inlined actually
__forceinline__ __global__ void generateGaussian(float *filter, float sigma) {
int x_idx = threadIdx.x + blockDim.x * blockIdx.x;
int y_idx = threadIdx.y + blockDim.y * blockIdx.y;
int sz = blockDim.x; // always odd
__shared__ float arr[2]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// float deno = arr[0];
// float sum = arr[1];
if (threadIdx.x == 0 && threadIdx.y == 0) {
arr[1] = 0;
arr[0] = 2 * sigma * sigma; // memory transaction takes place immediately since volatile
}
__syncthreads(); // all should get the sum and deno values populated
filter[y_idx*sz + x_idx] = 1.0/( exp( ( (y_idx-sz/2) * (y_idx-sz/2) + (x_idx-sz/2)*(x_idx-sz/2) )/arr[0] ) * (arr[0] * M_PI) );
/* Effectively serializing the next part of code. Hurts parallelism massively */
// Protection against all threads trying to modify this variable
atomicAdd(&arr[1], filter[y_idx*sz + x_idx]); // memory transaction takes place immediately since volatile
__syncthreads(); // wiat for all threads to have updated the "sum" variable
filter[y_idx*sz + x_idx] /= arr[1];
}
// template <int sig>
// __global__ void generateGaussian(float *filter) {
// float sigma = sig/100;
// int x_idx = threadIdx.x + blockDim.x * blockIdx.x;
// int y_idx = threadIdx.y + blockDim.y * blockIdx.y;
// int sz = blockDim.x; // always odd
// __shared__ float arr[2]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// // float deno = arr[0];
// // float sum = arr[1];
// if (threadIdx.x == 0 && threadIdx.y == 0) {
// arr[1] = 0;
// arr[0] = 2 * sigma * sigma; // memory transaction takes place immediately since volatile
// }
// __syncthreads(); // all should get the sum and deno values populated
// filter[y_idx*sz + x_idx] = 1.0/( exp( ( (y_idx-sz/2) * (y_idx-sz/2) + (x_idx-sz/2)*(x_idx-sz/2) )/arr[0] ) * (arr[0] * M_PI) );
// /* Effectively serializing the next part of code. Hurts parallelism massively */
// // Protection against all threads trying to modify this variable
// atomicAdd(&arr[1], filter[y_idx*sz + x_idx]); // memory transaction takes place immediately since volatile
// __syncthreads(); // wiat for all threads to have updated the "sum" variable
// filter[y_idx*sz + x_idx] /= arr[1];
// }
__global__ void NonMaxSuppression(float *grad, float* magn, float* supp, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int bdx = blockDim.x, bdy = blockDim.y;
int idx = i*c+j; // code motion
int tidx = threadIdx.x, tidy = threadIdx.y;
float avg_intensity = 0.0;
extern __shared__ float img[]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// load image elements in-place
if (j < c && i < r)
img[(tidy+1)*(bdx+2) + tidx+1] = magn[idx];
else
img[(tidy+1)*(bdx+2) + tidx+1] = avg_intensity;
if (tidx == 0 && tidy == 0) { // leftmost top corner
if (j >= 1 && i >= 1)
img[tidy*(bdx+2) + tidx] = magn[idx-c-1];
else
img[tidy*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == 0 && tidy == bdy - 1) { // leftmost bottom corner
if (j >= 1 && i < r-1)
img[(tidy+2)*(bdx+2) + tidx] = magn[idx+c-1];
else
img[(tidy+2)*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == bdx - 1 && tidy == 0) { // rightmost top corner
if (j < c -1 && i >= 1)
img[tidy*(bdx+2) + tidx+2] = magn[idx-c+1];
else
img[tidy*(bdx+2) + tidx+2] = avg_intensity;
}
else if (tidx == bdx - 1 && tidy == bdy -1) { // rightmost bottom corner
if (j < c -1 && i < r-1)
img[(tidy+2)*(bdx+2) + tidx+2] = magn[idx+c+1];
else
img[(tidy+2)*(bdx+2) + tidx+2] = avg_intensity;
}
if (tidx == 0) { // leftmost col
if (j >= 1)
img[(tidy+1)*(bdx+2) + tidx] = magn[idx-1];
else
img[(tidy+1)*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == bdx - 1) { // rightmost col
if (j < c-1)
img[(tidy+1)*(bdx+2) + tidx+2] = magn[idx+1];
else
img[(tidy+1)*(bdx+2) + tidx+2] = avg_intensity;
}
if (tidy == 0) { // top row
if (i >= 1)
img[tidy*(bdx+2) + tidx+1] = magn[idx-c];
else
img[tidy*(bdx+2) + tidx+1] = avg_intensity;
}
else if (tidy == bdy - 1) { // bottom row
if (i < r-1)
img[(tidy+2)*(bdx+2) + tidx+1] = magn[idx+c];
else
img[(tidy+2)*(bdx+2) + tidx+1] = avg_intensity;
}
__syncthreads();
// check for out of bounds
if (i > 0 && j > 0 && j < c-1 && i < r-1) {
float angle = grad[idx];
int idx1 = (tidy+1)*(bdx+2) + tidx+1;
if ((-22.5 < angle && angle <= 22.5) || (157.5 < angle && angle <= -157.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-1], img[idx1+1]);
if (img[idx1] < img[idx1+1] || img[idx1] < img[idx1-1])
supp[idx] = 0.0;
}
if ((-112.5 < angle && angle <= -67.5) || (67.5 < angle && angle <= 112.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-c], img[idx1+c]);
if (img[idx1] < img[idx1+(bdx+2)] || img[idx1] < img[idx1-(bdx+2)])
supp[idx] = 0.0;
}
if ((-67.5 < angle && angle <= -22.5) || (112.5 < angle && angle <= 157.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-c+1], img[idx1+c-1]);
if (img[idx1] < img[idx1-(bdx+2)+1] || img[idx1] < img[idx1+(bdx+2)-1])
supp[idx] = 0.0;
}
if ((-157.5 < angle && angle <= -112.5) || (22.5 < angle && angle <= 67.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1+c+1], img[idx1-c-1]);
if (img[idx1] < img[idx1+(bdx+2)+1] || img[idx1] < img[idx1-(bdx+2)-1])
supp[idx] = 0.0;
}
}
}
__global__ void mag_grad(float *Gx, float *Gy, float *magn, float *grad, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
// check for out of bounds
if (j < c && i < r) {
magn[idx] = sqrt(Gx[idx] * Gx[idx] + Gy[idx] * Gy[idx]);
// if (Gx[idx] == 0)
// grad[idx] = 90;
// else
// grad[idx] = atan2(Gy[idx], Gx[idx]) * 180.0/M_PI;
grad[idx] = (Gx[idx] == 0) * 90.0 + (Gx[idx] != 0) * (atan2(Gy[idx], Gx[idx]) * 180.0/M_PI); // Avoids thread divergence
}
}
__device__ void lock(volatile int *mutex) { // spinlock
while (atomicCAS((int*)mutex, 0, 1) != 0);
// other threads in the warp keep spinning, so thread in critical section can't be scheduled to release mutesx. Warp-level semantics
}
__device__ void unlock(volatile int *mutex) {
atomicExch((int*)mutex, 0);
}
__global__ void q_init(float* supp, float high, float *q, int *back, size_t r, size_t c, int* mutex) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
__shared__ int arr[1];
if (i == 0 && j == 0) {
arr[0] = *back;
}
__syncthreads();
if (i < r && j < c && supp[idx] > high) {
supp[idx] = 1.0;
lock(mutex);
// push {i,j} into queue if its value > high
q[arr[0]] = i;
q[arr[0] + 1] = j;
printf("Value of back is %d from idx %d %d\n", arr[0], i, j);
arr[0] += 2;
unlock(mutex);
}
}
__global__ void hysteresis(float* supp, size_t r, size_t c, float low, float high, int* ctr) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
volatile __shared__ int arr[1];
if (threadIdx.x == 0 && threadIdx.y == 0)
arr[0] = *ctr;
__syncthreads();
if (i < r && j < c) {
if (supp[idx] > high) {
supp[idx] = 1.0;
// unroll loops
if (i+1 < r && j+1 < c && supp[(i+1)*c+(j+1)] > low && supp[(i+1)*c+(j+1)] != 1.0) { // southeast
supp[(i+1)*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (j+1 < c && supp[i*c+(j+1)] > low && supp[i*c+(j+1)] != 1.0) { // east
supp[i*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i+1 < r && supp[(i+1)*c+j] > low && supp[(i+1)*c+j] != 1.0) { // south
supp[(i+1)*c+j] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && supp[(i-1)*c+j] > low && supp[(i-1)*c+j] != 1.0) { // north
supp[(i-1)*c+j] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (j-1 >= 0 && supp[i*c+(j-1)] > low && supp[i*c+(j-1)] != 1.0) { // west
supp[i*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i+1 < r && j-1 >= 0 && supp[(i+1)*c+(j-1)] > low && supp[(i+1)*c+(j-1)] != 1.0) { // southwest
supp[(i+1)*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && j+1 < c && supp[(i-1)*c+(j+1)] > low && supp[(i-1)*c+(j+1)] != 1.0) { // northeast
supp[(i-1)*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && j-1 >= 0 && supp[(i-1)*c+(j-1)] > low && supp[(i-1)*c+(j-1)] != 1.0) { // northwest
supp[(i-1)*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
}
}
__syncthreads(); // need all other threads in warp to increment arr[0] to get correct value of *ctr
if (threadIdx.x == 0 && threadIdx.y == 0)
*ctr = arr[0];
}
// template <int l, int h>
// __global__ void hysteresis(float* supp, size_t r, size_t c, int* ctr) {
// float low = l/100, high = h/100;
// int j = threadIdx.x + blockDim.x * blockIdx.x;
// int i = threadIdx.y + blockDim.y * blockIdx.y;
// int idx = i*c+j;
// volatile __shared__ int arr[1];
// if (threadIdx.x == 0 && threadIdx.y == 0)
// arr[0] = *ctr;
// __syncthreads();
// if (i < r && j < c) {
// if (supp[idx] > high) {
// supp[idx] = 1.0;
// // unroll loops
// if (i+1 < r && j+1 < c && supp[(i+1)*c+(j+1)] > low && supp[(i+1)*c+(j+1)] != 1.0) { // southeast
// supp[(i+1)*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (j+1 < c && supp[i*c+(j+1)] > low && supp[i*c+(j+1)] != 1.0) { // east
// supp[i*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i+1 < r && supp[(i+1)*c+j] > low && supp[(i+1)*c+j] != 1.0) { // south
// supp[(i+1)*c+j] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && supp[(i-1)*c+j] > low && supp[(i-1)*c+j] != 1.0) { // north
// supp[(i-1)*c+j] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (j-1 >= 0 && supp[i*c+(j-1)] > low && supp[i*c+(j-1)] != 1.0) { // west
// supp[i*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i+1 < r && j-1 >= 0 && supp[(i+1)*c+(j-1)] > low && supp[(i+1)*c+(j-1)] != 1.0) { // southwest
// supp[(i+1)*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && j+1 < c && supp[(i-1)*c+(j+1)] > low && supp[(i-1)*c+(j+1)] != 1.0) { // northeast
// supp[(i-1)*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && j-1 >= 0 && supp[(i-1)*c+(j-1)] > low && supp[(i-1)*c+(j-1)] != 1.0) { // northwest
// supp[(i-1)*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// }
// }
// __syncthreads(); // need all other threads in warp to increment arr[0] to get correct value of *ctr
// if (threadIdx.x == 0 && threadIdx.y == 0)
// *ctr = arr[0];
// }
__global__ void weak_disconnected_edge_removal(float* supp, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
if (j < c && i < r)
supp[idx] = (supp[idx] != 1.0) * 0.0 + (supp[idx] == 1.0) * supp[idx];
} | .file "tmpxft_000bb74b_00000000-6_canny.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z16generateGaussianPff,"axG",@progbits,_Z16generateGaussianPff,comdat
.weak _Z16generateGaussianPff
.type _Z16generateGaussianPff, @function
_Z16generateGaussianPff:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq _Z16generateGaussianPff(%rip), %rax
movq %rax, _ZZ37__device_stub__Z16generateGaussianPffPffE3__f(%rip)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16generateGaussianPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z16generateGaussianPff, .-_Z16generateGaussianPff
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4lockPVi
.type _Z4lockPVi, @function
_Z4lockPVi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z4lockPVi, .-_Z4lockPVi
.globl _Z6unlockPVi
.type _Z6unlockPVi, @function
_Z6unlockPVi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z6unlockPVi, .-_Z6unlockPVi
.globl _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
.type _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm, @function
_Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm:
.LFB3697:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17NonMaxSuppressionPfS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm, .-_Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
.globl _Z17NonMaxSuppressionPfS_S_mm
.type _Z17NonMaxSuppressionPfS_S_mm, @function
_Z17NonMaxSuppressionPfS_S_mm:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z17NonMaxSuppressionPfS_S_mm, .-_Z17NonMaxSuppressionPfS_S_mm
.globl _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
.type _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm, @function
_Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm:
.LFB3699:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mag_gradPfS_S_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm, .-_Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
.globl _Z8mag_gradPfS_S_S_mm
.type _Z8mag_gradPfS_S_S_mm, @function
_Z8mag_gradPfS_S_S_mm:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z8mag_gradPfS_S_S_mm, .-_Z8mag_gradPfS_S_S_mm
.globl _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
.type _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_, @function
_Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_:
.LFB3701:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6q_initPffS_PimmS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_, .-_Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
.globl _Z6q_initPffS_PimmS0_
.type _Z6q_initPffS_PimmS0_, @function
_Z6q_initPffS_PimmS0_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z6q_initPffS_PimmS0_, .-_Z6q_initPffS_PimmS0_
.globl _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
.type _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi, @function
_Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi:
.LFB3703:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10hysteresisPfmmffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi, .-_Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
.globl _Z10hysteresisPfmmffPi
.type _Z10hysteresisPfmmffPi, @function
_Z10hysteresisPfmmffPi:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z10hysteresisPfmmffPi, .-_Z10hysteresisPfmmffPi
.globl _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
.type _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm, @function
_Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm:
.LFB3705:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30weak_disconnected_edge_removalPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm, .-_Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
.globl _Z30weak_disconnected_edge_removalPfmm
.type _Z30weak_disconnected_edge_removalPfmm, @function
_Z30weak_disconnected_edge_removalPfmm:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z30weak_disconnected_edge_removalPfmm, .-_Z30weak_disconnected_edge_removalPfmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30weak_disconnected_edge_removalPfmm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10hysteresisPfmmffPi"
.LC2:
.string "_Z6q_initPffS_PimmS0_"
.LC3:
.string "_Z8mag_gradPfS_S_S_mm"
.LC4:
.string "_Z17NonMaxSuppressionPfS_S_mm"
.LC5:
.string "_Z16generateGaussianPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3708:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30weak_disconnected_edge_removalPfmm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hysteresisPfmmffPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6q_initPffS_PimmS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mag_gradPfS_S_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17NonMaxSuppressionPfS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16generateGaussianPff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZZ37__device_stub__Z16generateGaussianPffPffE3__f
.section .bss._ZZ37__device_stub__Z16generateGaussianPffPffE3__f,"awG",@nobits,_ZZ37__device_stub__Z16generateGaussianPffPffE3__f,comdat
.align 8
.type _ZZ37__device_stub__Z16generateGaussianPffPffE3__f, @gnu_unique_object
.size _ZZ37__device_stub__Z16generateGaussianPffPffE3__f, 8
_ZZ37__device_stub__Z16generateGaussianPffPffE3__f:
.zero 8
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <cstdio>
#include <iostream>
#include "canny.cuh"
using namespace std;
// __global__ functions can't be inlined actually
__forceinline__ __global__ void generateGaussian(float *filter, float sigma) {
int x_idx = threadIdx.x + blockDim.x * blockIdx.x;
int y_idx = threadIdx.y + blockDim.y * blockIdx.y;
int sz = blockDim.x; // always odd
__shared__ float arr[2]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// float deno = arr[0];
// float sum = arr[1];
if (threadIdx.x == 0 && threadIdx.y == 0) {
arr[1] = 0;
arr[0] = 2 * sigma * sigma; // memory transaction takes place immediately since volatile
}
__syncthreads(); // all should get the sum and deno values populated
filter[y_idx*sz + x_idx] = 1.0/( exp( ( (y_idx-sz/2) * (y_idx-sz/2) + (x_idx-sz/2)*(x_idx-sz/2) )/arr[0] ) * (arr[0] * M_PI) );
/* Effectively serializing the next part of code. Hurts parallelism massively */
// Protection against all threads trying to modify this variable
atomicAdd(&arr[1], filter[y_idx*sz + x_idx]); // memory transaction takes place immediately since volatile
__syncthreads(); // wiat for all threads to have updated the "sum" variable
filter[y_idx*sz + x_idx] /= arr[1];
}
// template <int sig>
// __global__ void generateGaussian(float *filter) {
// float sigma = sig/100;
// int x_idx = threadIdx.x + blockDim.x * blockIdx.x;
// int y_idx = threadIdx.y + blockDim.y * blockIdx.y;
// int sz = blockDim.x; // always odd
// __shared__ float arr[2]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// // float deno = arr[0];
// // float sum = arr[1];
// if (threadIdx.x == 0 && threadIdx.y == 0) {
// arr[1] = 0;
// arr[0] = 2 * sigma * sigma; // memory transaction takes place immediately since volatile
// }
// __syncthreads(); // all should get the sum and deno values populated
// filter[y_idx*sz + x_idx] = 1.0/( exp( ( (y_idx-sz/2) * (y_idx-sz/2) + (x_idx-sz/2)*(x_idx-sz/2) )/arr[0] ) * (arr[0] * M_PI) );
// /* Effectively serializing the next part of code. Hurts parallelism massively */
// // Protection against all threads trying to modify this variable
// atomicAdd(&arr[1], filter[y_idx*sz + x_idx]); // memory transaction takes place immediately since volatile
// __syncthreads(); // wiat for all threads to have updated the "sum" variable
// filter[y_idx*sz + x_idx] /= arr[1];
// }
__global__ void NonMaxSuppression(float *grad, float* magn, float* supp, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int bdx = blockDim.x, bdy = blockDim.y;
int idx = i*c+j; // code motion
int tidx = threadIdx.x, tidy = threadIdx.y;
float avg_intensity = 0.0;
extern __shared__ float img[]; // Can't use "volatile" to prevent shmem data from being directly loaded onto registers
// load image elements in-place
if (j < c && i < r)
img[(tidy+1)*(bdx+2) + tidx+1] = magn[idx];
else
img[(tidy+1)*(bdx+2) + tidx+1] = avg_intensity;
if (tidx == 0 && tidy == 0) { // leftmost top corner
if (j >= 1 && i >= 1)
img[tidy*(bdx+2) + tidx] = magn[idx-c-1];
else
img[tidy*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == 0 && tidy == bdy - 1) { // leftmost bottom corner
if (j >= 1 && i < r-1)
img[(tidy+2)*(bdx+2) + tidx] = magn[idx+c-1];
else
img[(tidy+2)*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == bdx - 1 && tidy == 0) { // rightmost top corner
if (j < c -1 && i >= 1)
img[tidy*(bdx+2) + tidx+2] = magn[idx-c+1];
else
img[tidy*(bdx+2) + tidx+2] = avg_intensity;
}
else if (tidx == bdx - 1 && tidy == bdy -1) { // rightmost bottom corner
if (j < c -1 && i < r-1)
img[(tidy+2)*(bdx+2) + tidx+2] = magn[idx+c+1];
else
img[(tidy+2)*(bdx+2) + tidx+2] = avg_intensity;
}
if (tidx == 0) { // leftmost col
if (j >= 1)
img[(tidy+1)*(bdx+2) + tidx] = magn[idx-1];
else
img[(tidy+1)*(bdx+2) + tidx] = avg_intensity;
}
else if (tidx == bdx - 1) { // rightmost col
if (j < c-1)
img[(tidy+1)*(bdx+2) + tidx+2] = magn[idx+1];
else
img[(tidy+1)*(bdx+2) + tidx+2] = avg_intensity;
}
if (tidy == 0) { // top row
if (i >= 1)
img[tidy*(bdx+2) + tidx+1] = magn[idx-c];
else
img[tidy*(bdx+2) + tidx+1] = avg_intensity;
}
else if (tidy == bdy - 1) { // bottom row
if (i < r-1)
img[(tidy+2)*(bdx+2) + tidx+1] = magn[idx+c];
else
img[(tidy+2)*(bdx+2) + tidx+1] = avg_intensity;
}
__syncthreads();
// check for out of bounds
if (i > 0 && j > 0 && j < c-1 && i < r-1) {
float angle = grad[idx];
int idx1 = (tidy+1)*(bdx+2) + tidx+1;
if ((-22.5 < angle && angle <= 22.5) || (157.5 < angle && angle <= -157.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-1], img[idx1+1]);
if (img[idx1] < img[idx1+1] || img[idx1] < img[idx1-1])
supp[idx] = 0.0;
}
if ((-112.5 < angle && angle <= -67.5) || (67.5 < angle && angle <= 112.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-c], img[idx1+c]);
if (img[idx1] < img[idx1+(bdx+2)] || img[idx1] < img[idx1-(bdx+2)])
supp[idx] = 0.0;
}
if ((-67.5 < angle && angle <= -22.5) || (112.5 < angle && angle <= 157.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1-c+1], img[idx1+c-1]);
if (img[idx1] < img[idx1-(bdx+2)+1] || img[idx1] < img[idx1+(bdx+2)-1])
supp[idx] = 0.0;
}
if ((-157.5 < angle && angle <= -112.5) || (22.5 < angle && angle <= 67.5)) {
// printf("%f %f %f\n", img[idx1], img[idx1+c+1], img[idx1-c-1]);
if (img[idx1] < img[idx1+(bdx+2)+1] || img[idx1] < img[idx1-(bdx+2)-1])
supp[idx] = 0.0;
}
}
}
__global__ void mag_grad(float *Gx, float *Gy, float *magn, float *grad, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
// check for out of bounds
if (j < c && i < r) {
magn[idx] = sqrt(Gx[idx] * Gx[idx] + Gy[idx] * Gy[idx]);
// if (Gx[idx] == 0)
// grad[idx] = 90;
// else
// grad[idx] = atan2(Gy[idx], Gx[idx]) * 180.0/M_PI;
grad[idx] = (Gx[idx] == 0) * 90.0 + (Gx[idx] != 0) * (atan2(Gy[idx], Gx[idx]) * 180.0/M_PI); // Avoids thread divergence
}
}
__device__ void lock(volatile int *mutex) { // spinlock
while (atomicCAS((int*)mutex, 0, 1) != 0);
// other threads in the warp keep spinning, so thread in critical section can't be scheduled to release mutesx. Warp-level semantics
}
__device__ void unlock(volatile int *mutex) {
atomicExch((int*)mutex, 0);
}
__global__ void q_init(float* supp, float high, float *q, int *back, size_t r, size_t c, int* mutex) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
__shared__ int arr[1];
if (i == 0 && j == 0) {
arr[0] = *back;
}
__syncthreads();
if (i < r && j < c && supp[idx] > high) {
supp[idx] = 1.0;
lock(mutex);
// push {i,j} into queue if its value > high
q[arr[0]] = i;
q[arr[0] + 1] = j;
printf("Value of back is %d from idx %d %d\n", arr[0], i, j);
arr[0] += 2;
unlock(mutex);
}
}
__global__ void hysteresis(float* supp, size_t r, size_t c, float low, float high, int* ctr) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
volatile __shared__ int arr[1];
if (threadIdx.x == 0 && threadIdx.y == 0)
arr[0] = *ctr;
__syncthreads();
if (i < r && j < c) {
if (supp[idx] > high) {
supp[idx] = 1.0;
// unroll loops
if (i+1 < r && j+1 < c && supp[(i+1)*c+(j+1)] > low && supp[(i+1)*c+(j+1)] != 1.0) { // southeast
supp[(i+1)*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (j+1 < c && supp[i*c+(j+1)] > low && supp[i*c+(j+1)] != 1.0) { // east
supp[i*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i+1 < r && supp[(i+1)*c+j] > low && supp[(i+1)*c+j] != 1.0) { // south
supp[(i+1)*c+j] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && supp[(i-1)*c+j] > low && supp[(i-1)*c+j] != 1.0) { // north
supp[(i-1)*c+j] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (j-1 >= 0 && supp[i*c+(j-1)] > low && supp[i*c+(j-1)] != 1.0) { // west
supp[i*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i+1 < r && j-1 >= 0 && supp[(i+1)*c+(j-1)] > low && supp[(i+1)*c+(j-1)] != 1.0) { // southwest
supp[(i+1)*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && j+1 < c && supp[(i-1)*c+(j+1)] > low && supp[(i-1)*c+(j+1)] != 1.0) { // northeast
supp[(i-1)*c+(j+1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
if (i-1 >= 0 && j-1 >= 0 && supp[(i-1)*c+(j-1)] > low && supp[(i-1)*c+(j-1)] != 1.0) { // northwest
supp[(i-1)*c+(j-1)] = 1.0;
atomicAdd((int*)&arr[0], 1);
}
}
}
__syncthreads(); // need all other threads in warp to increment arr[0] to get correct value of *ctr
if (threadIdx.x == 0 && threadIdx.y == 0)
*ctr = arr[0];
}
// template <int l, int h>
// __global__ void hysteresis(float* supp, size_t r, size_t c, int* ctr) {
// float low = l/100, high = h/100;
// int j = threadIdx.x + blockDim.x * blockIdx.x;
// int i = threadIdx.y + blockDim.y * blockIdx.y;
// int idx = i*c+j;
// volatile __shared__ int arr[1];
// if (threadIdx.x == 0 && threadIdx.y == 0)
// arr[0] = *ctr;
// __syncthreads();
// if (i < r && j < c) {
// if (supp[idx] > high) {
// supp[idx] = 1.0;
// // unroll loops
// if (i+1 < r && j+1 < c && supp[(i+1)*c+(j+1)] > low && supp[(i+1)*c+(j+1)] != 1.0) { // southeast
// supp[(i+1)*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (j+1 < c && supp[i*c+(j+1)] > low && supp[i*c+(j+1)] != 1.0) { // east
// supp[i*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i+1 < r && supp[(i+1)*c+j] > low && supp[(i+1)*c+j] != 1.0) { // south
// supp[(i+1)*c+j] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && supp[(i-1)*c+j] > low && supp[(i-1)*c+j] != 1.0) { // north
// supp[(i-1)*c+j] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (j-1 >= 0 && supp[i*c+(j-1)] > low && supp[i*c+(j-1)] != 1.0) { // west
// supp[i*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i+1 < r && j-1 >= 0 && supp[(i+1)*c+(j-1)] > low && supp[(i+1)*c+(j-1)] != 1.0) { // southwest
// supp[(i+1)*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && j+1 < c && supp[(i-1)*c+(j+1)] > low && supp[(i-1)*c+(j+1)] != 1.0) { // northeast
// supp[(i-1)*c+(j+1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// if (i-1 >= 0 && j-1 >= 0 && supp[(i-1)*c+(j-1)] > low && supp[(i-1)*c+(j-1)] != 1.0) { // northwest
// supp[(i-1)*c+(j-1)] = 1.0;
// atomicAdd((int*)&arr[0], 1);
// }
// }
// }
// __syncthreads(); // need all other threads in warp to increment arr[0] to get correct value of *ctr
// if (threadIdx.x == 0 && threadIdx.y == 0)
// *ctr = arr[0];
// }
__global__ void weak_disconnected_edge_removal(float* supp, size_t r, size_t c) {
int j = threadIdx.x + blockDim.x * blockIdx.x;
int i = threadIdx.y + blockDim.y * blockIdx.y;
int idx = i*c+j;
if (j < c && i < r)
supp[idx] = (supp[idx] != 1.0) * 0.0 + (supp[idx] == 1.0) * supp[idx];
} | #ifndef CANNY_CUH
#define CANNY_CUH
#include <cstdlib>
using namespace std;
__device__ void lock(volatile int *mutex);
__device__ void unlock(volatile int *mutex);
__global__ void generateGaussian(float *filter, float sigma);
__global__ void NonMaxSuppression(float *grad, float* magn, float* supp, size_t r, size_t c);
__global__ void mag_grad(float *Gx, float *Gy, float *magn, float *grad, size_t r, size_t c);
__global__ void q_init(float* supp, float high, float *q, int *back, size_t r, size_t c, int* mutex);
__global__ void hysteresis(float* supp, size_t r, size_t c, float low, float high, int* ctr);
__global__ void weak_disconnected_edge_removal(float* supp, size_t r, size_t c);
// // template params in percentages
// template __global__ void generateGaussian<100>(float *filter);
// template __global__ void hysteresis<8, 11>(float* supp, size_t r, size_t c, int* ctr);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef CANNY_CUH
#define CANNY_CUH
#include <cstdlib>
using namespace std;
__device__ void lock(volatile int *mutex);
__device__ void unlock(volatile int *mutex);
__global__ void generateGaussian(float *filter, float sigma);
__global__ void NonMaxSuppression(float *grad, float* magn, float* supp, size_t r, size_t c);
__global__ void mag_grad(float *Gx, float *Gy, float *magn, float *grad, size_t r, size_t c);
__global__ void q_init(float* supp, float high, float *q, int *back, size_t r, size_t c, int* mutex);
__global__ void hysteresis(float* supp, size_t r, size_t c, float low, float high, int* ctr);
__global__ void weak_disconnected_edge_removal(float* supp, size_t r, size_t c);
// // template params in percentages
// template __global__ void generateGaussian<100>(float *filter);
// template __global__ void hysteresis<8, 11>(float* supp, size_t r, size_t c, int* ctr);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef CANNY_CUH
#define CANNY_CUH
#include <cstdlib>
using namespace std;
__device__ void lock(volatile int *mutex);
__device__ void unlock(volatile int *mutex);
__global__ void generateGaussian(float *filter, float sigma);
__global__ void NonMaxSuppression(float *grad, float* magn, float* supp, size_t r, size_t c);
__global__ void mag_grad(float *Gx, float *Gy, float *magn, float *grad, size_t r, size_t c);
__global__ void q_init(float* supp, float high, float *q, int *back, size_t r, size_t c, int* mutex);
__global__ void hysteresis(float* supp, size_t r, size_t c, float low, float high, int* ctr);
__global__ void weak_disconnected_edge_removal(float* supp, size_t r, size_t c);
// // template params in percentages
// template __global__ void generateGaussian<100>(float *filter);
// template __global__ void hysteresis<8, 11>(float* supp, size_t r, size_t c, int* ctr);
#endif | .text
.file "canny.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bb74b_00000000-6_canny.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z16generateGaussianPff,"axG",@progbits,_Z16generateGaussianPff,comdat
.weak _Z16generateGaussianPff
.type _Z16generateGaussianPff, @function
_Z16generateGaussianPff:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq _Z16generateGaussianPff(%rip), %rax
movq %rax, _ZZ37__device_stub__Z16generateGaussianPffPffE3__f(%rip)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16generateGaussianPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z16generateGaussianPff, .-_Z16generateGaussianPff
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4lockPVi
.type _Z4lockPVi, @function
_Z4lockPVi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z4lockPVi, .-_Z4lockPVi
.globl _Z6unlockPVi
.type _Z6unlockPVi, @function
_Z6unlockPVi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z6unlockPVi, .-_Z6unlockPVi
.globl _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
.type _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm, @function
_Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm:
.LFB3697:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17NonMaxSuppressionPfS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm, .-_Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
.globl _Z17NonMaxSuppressionPfS_S_mm
.type _Z17NonMaxSuppressionPfS_S_mm, @function
_Z17NonMaxSuppressionPfS_S_mm:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17NonMaxSuppressionPfS_S_mmPfS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z17NonMaxSuppressionPfS_S_mm, .-_Z17NonMaxSuppressionPfS_S_mm
.globl _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
.type _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm, @function
_Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm:
.LFB3699:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mag_gradPfS_S_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm, .-_Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
.globl _Z8mag_gradPfS_S_S_mm
.type _Z8mag_gradPfS_S_S_mm, @function
_Z8mag_gradPfS_S_S_mm:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8mag_gradPfS_S_S_mmPfS_S_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z8mag_gradPfS_S_S_mm, .-_Z8mag_gradPfS_S_S_mm
.globl _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
.type _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_, @function
_Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_:
.LFB3701:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movss %xmm0, 52(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z6q_initPffS_PimmS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_, .-_Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
.globl _Z6q_initPffS_PimmS0_
.type _Z6q_initPffS_PimmS0_, @function
_Z6q_initPffS_PimmS0_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z6q_initPffS_PimmS0_PffS_PimmS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z6q_initPffS_PimmS0_, .-_Z6q_initPffS_PimmS0_
.globl _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
.type _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi, @function
_Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi:
.LFB3703:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10hysteresisPfmmffPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi, .-_Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
.globl _Z10hysteresisPfmmffPi
.type _Z10hysteresisPfmmffPi, @function
_Z10hysteresisPfmmffPi:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10hysteresisPfmmffPiPfmmffPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z10hysteresisPfmmffPi, .-_Z10hysteresisPfmmffPi
.globl _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
.type _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm, @function
_Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm:
.LFB3705:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z30weak_disconnected_edge_removalPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3705:
.size _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm, .-_Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
.globl _Z30weak_disconnected_edge_removalPfmm
.type _Z30weak_disconnected_edge_removalPfmm, @function
_Z30weak_disconnected_edge_removalPfmm:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z30weak_disconnected_edge_removalPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _Z30weak_disconnected_edge_removalPfmm, .-_Z30weak_disconnected_edge_removalPfmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30weak_disconnected_edge_removalPfmm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10hysteresisPfmmffPi"
.LC2:
.string "_Z6q_initPffS_PimmS0_"
.LC3:
.string "_Z8mag_gradPfS_S_S_mm"
.LC4:
.string "_Z17NonMaxSuppressionPfS_S_mm"
.LC5:
.string "_Z16generateGaussianPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3708:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30weak_disconnected_edge_removalPfmm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hysteresisPfmmffPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6q_initPffS_PimmS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mag_gradPfS_S_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z17NonMaxSuppressionPfS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16generateGaussianPff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZZ37__device_stub__Z16generateGaussianPffPffE3__f
.section .bss._ZZ37__device_stub__Z16generateGaussianPffPffE3__f,"awG",@nobits,_ZZ37__device_stub__Z16generateGaussianPffPffE3__f,comdat
.align 8
.type _ZZ37__device_stub__Z16generateGaussianPffPffE3__f, @gnu_unique_object
.size _ZZ37__device_stub__Z16generateGaussianPffPffE3__f, 8
_ZZ37__device_stub__Z16generateGaussianPffPffE3__f:
.zero 8
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "canny.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} | code for sm_80
Function : _Z8update_hiiiPfS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0020*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0030*/ IABS R2, c[0x0][0x168] ; /* 0x00005a0000027a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0070*/ I2F.RP R9, R2 ; /* 0x0000000200097306 */
/* 0x000e640000209400 */
/*0080*/ IABS R3, R0 ; /* 0x0000000000037213 */
/* 0x000fcc0000000000 */
/*0090*/ I2F.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000eb00000209400 */
/*00a0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e700000001000 */
/*00b0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x004ea20000001000 */
/*00c0*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x002fe20007ffe0ff */
/*00d0*/ IMAD R9, R10, c[0x0][0x0], R11 ; /* 0x000000000a097a24 */
/* 0x001fcc00078e020b */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000062000021f000 */
/*00f0*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fe40000000000 */
/*0100*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x004fca0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0004e2000021f000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R13, RZ, RZ, -R7 ; /* 0x000000ffff0d7224 */
/* 0x002fe400078e0a07 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x004fe400078e00ff */
/*0150*/ IMAD R11, R13, R2, RZ ; /* 0x000000020d0b7224 */
/* 0x000fe200078e02ff */
/*0160*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x008fc60007ffe0ff */
/*0170*/ IMAD.HI.U32 R6, R7, R11, R6 ; /* 0x0000000b07067227 */
/* 0x000fe200078e0006 */
/*0180*/ MOV R11, R10 ; /* 0x0000000a000b7202 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD R7, R8, R3, RZ ; /* 0x0000000308077224 */
/* 0x000fe200078e02ff */
/*01a0*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc60000000000 */
/*01b0*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fe200078e0004 */
/*01c0*/ IADD3 R8, RZ, -R8, RZ ; /* 0x80000008ff087210 */
/* 0x000fc60007ffe0ff */
/*01d0*/ IMAD.HI.U32 R5, R6, R11, RZ ; /* 0x0000000b06057227 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*01f0*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fe20007ffe1ff */
/*0200*/ IMAD.HI.U32 R4, R4, R11, RZ ; /* 0x0000000b04047227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD R6, R4, R6, R11.reuse ; /* 0x0000000604067224 */
/* 0x100fe400078e020b */
/*0220*/ IMAD R7, R2, R7, R11 ; /* 0x0000000702077224 */
/* 0x000fc600078e020b */
/*0230*/ ISETP.GT.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f04070 */
/*0240*/ ISETP.GT.U32.AND P4, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fd60003f84070 */
/*0250*/ @!P0 IMAD.IADD R6, R6, 0x1, -R3 ; /* 0x0000000106068824 */
/* 0x000fe200078e0a03 */
/*0260*/ @!P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104048810 */
/* 0x000fe40007ffe0ff */
/*0270*/ @!P4 IADD3 R7, R7, -R2.reuse, RZ ; /* 0x800000020707c210 */
/* 0x080fe40007ffe0ff */
/*0280*/ ISETP.GE.U32.AND P5, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003fa6070 */
/*0290*/ ISETP.GE.U32.AND P3, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f66070 */
/*02a0*/ LOP3.LUT R2, R9.reuse, R0, RZ, 0x3c, !PT ; /* 0x0000000009027212 */
/* 0x040fe400078e3cff */
/*02b0*/ LOP3.LUT R3, R9, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0009037a12 */
/* 0x000fc400078e3cff */
/*02c0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f46270 */
/*02d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*02e0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f26270 */
/*02f0*/ @!P4 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505c810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f85270 */
/*0310*/ @P5 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104045810 */
/* 0x000fc40007ffe0ff */
/*0320*/ @P3 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105053810 */
/* 0x000fe40007ffe0ff */
/*0330*/ IADD3 R9, R9, c[0x0][0x160], RZ ; /* 0x0000580009097a10 */
/* 0x000fe20007ffe0ff */
/*0340*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0350*/ @!P0 LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff048212 */
/* 0x000fe400078e33ff */
/*0360*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*0370*/ IADD3 R0, R4, c[0x0][0x164], R9 ; /* 0x0000590004007a10 */
/* 0x000fe40007ffe009 */
/*0380*/ @!P4 LOP3.LUT R5, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff05ca12 */
/* 0x000fca00078e33ff */
/*0390*/ IMAD R21, R5, c[0x0][0x160], R0 ; /* 0x0000580005157a24 */
/* 0x000fe400078e0200 */
/*03a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc600078e00ff */
/*03b0*/ IADD3 R7, R21, 0x1, RZ ; /* 0x0000000115077810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ IADD3 R5, R7.reuse, -c[0x0][0x160], RZ ; /* 0x8000580007057a10 */
/* 0x040fe20007ffe0ff */
/*03d0*/ IMAD.WIDE R10, R7, R0, c[0x0][0x180] ; /* 0x00006000070a7625 */
/* 0x000fc800078e0200 */
/*03e0*/ IMAD.WIDE R8, R5, R0.reuse, c[0x0][0x180] ; /* 0x0000600005087625 */
/* 0x080fe200078e0200 */
/*03f0*/ LDG.E R4, [R10.64] ; /* 0x000000040a047981 */
/* 0x000ea6000c1e1900 */
/*0400*/ IMAD.WIDE R2, R21, R0.reuse, c[0x0][0x178] ; /* 0x00005e0015027625 */
/* 0x080fe400078e0200 */
/*0410*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea4000c1e1900 */
/*0420*/ IMAD.WIDE R12, R7, R0, c[0x0][0x188] ; /* 0x00006200070c7625 */
/* 0x000fe400078e0200 */
/*0430*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee8000c1e1900 */
/*0440*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000f62000c1e1900 */
/*0460*/ FADD R4, R4, -R9 ; /* 0x8000000904047221 */
/* 0x004fc80000000000 */
/*0470*/ FADD R4, R4, -R15 ; /* 0x8000000f04047221 */
/* 0x008fc80000000000 */
/*0480*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x010fe20000000000 */
/*0490*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x020ff00000201800 */
/*04a0*/ F2F.F64.F32 R14, R4 ; /* 0x00000004000e7310 */
/* 0x000e240000201800 */
/*04b0*/ DFMA R18, R14, -0.5, R16 ; /* 0xbfe000000e12782b */
/* 0x001e0c0000000010 */
/*04c0*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x001e220000301000 */
/*04d0*/ IMAD.WIDE R8, R21, R0, c[0x0][0x170] ; /* 0x00005c0015087625 */
/* 0x000fe200078e0200 */
/*04e0*/ IADD3 R17, R7, -c[0x0][0x164], RZ ; /* 0x8000590007117a10 */
/* 0x000fca0007ffe0ff */
/*04f0*/ IMAD.WIDE R20, R17, R0.reuse, c[0x0][0x180] ; /* 0x0000600011147625 */
/* 0x080fe200078e0200 */
/*0500*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0011e8000c101904 */
/*0510*/ LDG.E R6, [R8.64+0x4] ; /* 0x0000040408067981 */
/* 0x000ea8000c1e1900 */
/*0520*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R14, R7, R0, c[0x0][0x190] ; /* 0x00006400070e7625 */
/* 0x000fc600078e0200 */
/*0540*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee8000c1e1900 */
/*0550*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000f28000c1e1900 */
/*0560*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000f62000c1e1900 */
/*0570*/ IMAD.WIDE R16, R17, R0, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fc800078e0200 */
/*0580*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fc800078e0200 */
/*0590*/ FADD R6, R6, -R25 ; /* 0x8000001906067221 */
/* 0x004fc80000000000 */
/*05a0*/ FADD R6, R6, -R11 ; /* 0x8000000b06067221 */
/* 0x008fc80000000000 */
/*05b0*/ FADD R22, R6, R21 ; /* 0x0000001506167221 */
/* 0x010fe20000000000 */
/*05c0*/ F2F.F64.F32 R18, R24 ; /* 0x0000001800127310 */
/* 0x020ff00000201800 */
/*05d0*/ F2F.F64.F32 R12, R22 ; /* 0x00000016000c7310 */
/* 0x001e240000201800 */
/*05e0*/ DFMA R12, R12, -0.5, R18 ; /* 0xbfe000000c0c782b */
/* 0x001e0c0000000012 */
/*05f0*/ F2F.F32.F64 R19, R12 ; /* 0x0000000c00137310 */
/* 0x001e220000301000 */
/*0600*/ IMAD.WIDE R6, R7, R0, c[0x0][0x198] ; /* 0x0000660007067625 */
/* 0x000fe200078e0200 */
/*0610*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x001fe8000c101904 */
/*0620*/ LDG.E R2, [R2.64+0x4] ; /* 0x0000040402027981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R9, [R8.64+0x4] ; /* 0x0000040408097981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000f62000c1e1900 */
/*0670*/ FADD R0, R2, -R17 ; /* 0x8000001102007221 */
/* 0x004fc80000000000 */
/*0680*/ FADD R0, R0, -R9 ; /* 0x8000000900007221 */
/* 0x008fc80000000000 */
/*0690*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x010fe20000000000 */
/*06a0*/ F2F.F64.F32 R12, R18 ; /* 0x00000012000c7310 */
/* 0x020ff00000201800 */
/*06b0*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000e240000201800 */
/*06c0*/ DFMA R10, R10, -0.5, R12 ; /* 0xbfe000000a0a782b */
/* 0x001e14000000000c */
/*06d0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*06e0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x001fe2000c101904 */
/*06f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0700*/ BRA 0x700; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0020*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0030*/ IABS R3, c[0x0][0x168] ; /* 0x00005a0000037a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*0060*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0070*/ I2F.RP R5, R3 ; /* 0x0000000300057306 */
/* 0x000e640000209400 */
/*0080*/ IABS R4, R2 ; /* 0x0000000200047213 */
/* 0x000fcc0000000000 */
/*0090*/ I2F.RP R10, R4 ; /* 0x00000004000a7306 */
/* 0x000eb00000209400 */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x002e700000001000 */
/*00b0*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x004ea20000001000 */
/*00c0*/ IADD3 R8, R5, 0xffffffe, RZ ; /* 0x0ffffffe05087810 */
/* 0x002fe20007ffe0ff */
/*00d0*/ IMAD R5, R11, c[0x0][0x0], R12 ; /* 0x000000000b057a24 */
/* 0x001fe200078e020c */
/*00e0*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x000fca0000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0100*/ IADD3 R6, R10, 0xffffffe, RZ ; /* 0x0ffffffe0a067810 */
/* 0x004fe40007ffe0ff */
/*0110*/ IABS R10, R5 ; /* 0x00000005000a7213 */
/* 0x000fca0000000000 */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0004e2000021f000 */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*0140*/ IADD3 R14, RZ, -R9, RZ ; /* 0x80000009ff0e7210 */
/* 0x002fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x004fc800078e00ff */
/*0160*/ IMAD R11, R14, R3, RZ ; /* 0x000000030e0b7224 */
/* 0x000fe200078e02ff */
/*0170*/ IADD3 R13, RZ, -R7, RZ ; /* 0x80000007ff0d7210 */
/* 0x008fc60007ffe0ff */
/*0180*/ IMAD.HI.U32 R8, R9, R11, R8 ; /* 0x0000000b09087227 */
/* 0x000fe200078e0008 */
/*0190*/ MOV R11, R10 ; /* 0x0000000a000b7202 */
/* 0x000fc60000000f00 */
/*01a0*/ IMAD R9, R13, R4, RZ ; /* 0x000000040d097224 */
/* 0x000fe400078e02ff */
/*01b0*/ IMAD.HI.U32 R8, R8, R11, RZ ; /* 0x0000000b08087227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.HI.U32 R6, R7, R9, R6 ; /* 0x0000000907067227 */
/* 0x000fe200078e0006 */
/*01d0*/ IADD3 R10, -R8, RZ, RZ ; /* 0x000000ff080a7210 */
/* 0x000fe40007ffe1ff */
/*01e0*/ IADD3 R7, RZ, -R12, RZ ; /* 0x8000000cff077210 */
/* 0x000fc60007ffe0ff */
/*01f0*/ IMAD.HI.U32 R6, R6, R11, RZ ; /* 0x0000000b06067227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R10, R3, R10, R11.reuse ; /* 0x0000000a030a7224 */
/* 0x100fe400078e020b */
/*0210*/ IMAD R7, R6, R7, R11 ; /* 0x0000000706077224 */
/* 0x000fc600078e020b */
/*0220*/ ISETP.GT.U32.AND P4, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe40003f84070 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fd60003f04070 */
/*0240*/ @!P4 IMAD.IADD R10, R10, 0x1, -R3 ; /* 0x000000010a0ac824 */
/* 0x000fe200078e0a03 */
/*0250*/ @!P4 IADD3 R8, R8, 0x1, RZ ; /* 0x000000010808c810 */
/* 0x000fe40007ffe0ff */
/*0260*/ @!P0 IADD3 R7, R7, -R4.reuse, RZ ; /* 0x8000000407078210 */
/* 0x080fe40007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P3, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fe40003f66070 */
/*0280*/ ISETP.GE.U32.AND P5, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe40003fa6070 */
/*0290*/ LOP3.LUT R3, R5.reuse, R2, RZ, 0x3c, !PT ; /* 0x0000000205037212 */
/* 0x040fe400078e3cff */
/*02a0*/ LOP3.LUT R4, R5, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0005047a12 */
/* 0x000fc400078e3cff */
/*02b0*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f46270 */
/*02c0*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*02e0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f26270 */
/*02f0*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f85270 */
/*0300*/ @P5 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106065810 */
/* 0x000fc40007ffe0ff */
/*0310*/ @P3 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108083810 */
/* 0x000fe40007ffe0ff */
/*0320*/ @!P2 IADD3 R6, -R6, RZ, RZ ; /* 0x000000ff0606a210 */
/* 0x000fe40007ffe1ff */
/*0330*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fe40007ffe0ff */
/*0340*/ @!P0 LOP3.LUT R6, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff068212 */
/* 0x000fe400078e33ff */
/*0350*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*0360*/ @!P4 LOP3.LUT R8, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff08ca12 */
/* 0x000fc400078e33ff */
/*0370*/ IADD3 R5, R6, c[0x0][0x164], R5 ; /* 0x0000590006057a10 */
/* 0x000fe20007ffe005 */
/*0380*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc800000001ff */
/*0390*/ IMAD R15, R8, c[0x0][0x160], R5 ; /* 0x00005800080f7a24 */
/* 0x000fca00078e0205 */
/*03a0*/ IADD3 R7, R15.reuse, 0x1, RZ ; /* 0x000000010f077810 */
/* 0x040fe20007ffe0ff */
/*03b0*/ IMAD.WIDE R2, R15, R6, c[0x0][0x190] ; /* 0x000064000f027625 */
/* 0x000fc600078e0206 */
/*03c0*/ IADD3 R5, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007057a10 */
/* 0x040fe20007ffe0ff */
/*03d0*/ IMAD.WIDE R8, R7, R6.reuse, c[0x0][0x198] ; /* 0x0000660007087625 */
/* 0x080fe200078e0206 */
/*03e0*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea6000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R5, R6.reuse, c[0x0][0x198] ; /* 0x0000660005047625 */
/* 0x080fe200078e0206 */
/*0400*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee6000c1e1900 */
/*0410*/ IMAD.WIDE R12, R7.reuse, R6.reuse, c[0x0][0x1a0] ; /* 0x00006800070c7625 */
/* 0x0c0fe200078e0206 */
/*0420*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*0440*/ IMAD.WIDE R10, R7, R6, c[0x0][0x170] ; /* 0x00005c00070a7625 */
/* 0x000fc600078e0206 */
/*0450*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f68000c1e1900 */
/*0460*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000f62000c1e1900 */
/*0470*/ FADD R17, R4, -R17 ; /* 0x8000001104117221 */
/* 0x008fc80000000000 */
/*0480*/ FADD R14, R17, -R14 ; /* 0x8000000e110e7221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x010fe40000000000 */
/*04a0*/ IMAD.WIDE R4, R15, R6, c[0x0][0x188] ; /* 0x000062000f047625 */
/* 0x000fc800078e0206 */
/*04b0*/ FFMA R17, R12, R19, R16 ; /* 0x000000130c117223 */
/* 0x020fe40000000010 */
/*04c0*/ IMAD.WIDE R18, R6, c[0x0][0x164], R8 ; /* 0x0000590006127a25 */
/* 0x000fc600078e0208 */
/*04d0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R21, [R4.64+0x4] ; /* 0x0000040404157981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE R14, R7, R6, c[0x0][0x1a8] ; /* 0x00006a00070e7625 */
/* 0x000fc600078e0206 */
/*0510*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ee2000c1e1900 */
/*0520*/ IMAD.WIDE R12, R7, R6, c[0x0][0x178] ; /* 0x00005e00070c7625 */
/* 0x000fc600078e0206 */
/*0530*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000f28000c1e1900 */
/*0540*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000f62000c1e1900 */
/*0560*/ IMAD.WIDE R10, R7, R6, c[0x0][0x190] ; /* 0x00006400070a7625 */
/* 0x001fcc00078e0206 */
/*0570*/ IMAD.WIDE R10, R6, c[0x0][0x164], R10 ; /* 0x00005900060a7a25 */
/* 0x000fc800078e020a */
/*0580*/ FADD R16, R16, -R21 ; /* 0x8000001510107221 */
/* 0x004fc80000000000 */
/*0590*/ FADD R16, R16, -R19 ; /* 0x8000001310107221 */
/* 0x008fc80000000000 */
/*05a0*/ FADD R21, R16, R9 ; /* 0x0000000910157221 */
/* 0x010fe40000000000 */
/*05b0*/ IMAD.WIDE R16, R7, R6, c[0x0][0x188] ; /* 0x0000620007107625 */
/* 0x000fc800078e0206 */
/*05c0*/ FFMA R21, R14, R21, R20 ; /* 0x000000150e157223 */
/* 0x020fe40000000014 */
/*05d0*/ IMAD.WIDE R16, R0, 0x4, R16 ; /* 0x0000000400107825 */
/* 0x000fc600078e0210 */
/*05e0*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0001e8000c101904 */
/*05f0*/ LDG.E R3, [R2.64+0x4] ; /* 0x0000040402037981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD.WIDE R8, R7, R6, c[0x0][0x1b0] ; /* 0x00006c0007087625 */
/* 0x000fc600078e0206 */
/*0620*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1900 */
/*0630*/ IMAD.WIDE R6, R7, R6, c[0x0][0x180] ; /* 0x0000600007067625 */
/* 0x000fc600078e0206 */
/*0640*/ LDG.E R5, [R4.64+0x4] ; /* 0x0000040404057981 */
/* 0x000e28000c1e1900 */
/*0650*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000f22000c1e1900 */
/*0670*/ FADD R0, R10, -R3 ; /* 0x800000030a007221 */
/* 0x004fc80000000000 */
/*0680*/ FADD R0, R0, -R17 ; /* 0x8000001100007221 */
/* 0x008fc80000000000 */
/*0690*/ FADD R13, R0, R5 ; /* 0x00000005000d7221 */
/* 0x001fc80000000000 */
/*06a0*/ FFMA R13, R8, R13, R14 ; /* 0x0000000d080d7223 */
/* 0x010fca000000000e */
/*06b0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} | .file "tmpxft_0005a9ac_00000000-6_non_aligned-args-Nx+1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq 288(%rsp), %rax
movq %rax, 48(%rsp)
movq 296(%rsp), %rax
movq %rax, 40(%rsp)
movq 304(%rsp), %rax
movq %rax, 32(%rsp)
movq 312(%rsp), %rax
movq %rax, 24(%rsp)
movq 320(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.type _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, @function
_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, .-_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.type _Z8update_hiiiPfS_S_S_S_S_, @function
_Z8update_hiiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiiPfS_S_S_S_S_, .-_Z8update_hiiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} | #include <hip/hip_runtime.h>
__global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 8
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[20:21], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x64
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_add_i32 s5, s20, -1
s_add_i32 s2, s2, s4
s_ashr_i32 s6, s5, 31
s_xor_b32 s7, s2, s4
s_add_i32 s5, s5, s6
v_cvt_f32_u32_e32 v1, s7
s_xor_b32 s5, s5, s6
s_and_b32 s2, s3, 0xffff
v_cvt_f32_u32_e32 v2, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s7
s_load_b256 s[12:19], s[0:1], 0x10
v_mul_lo_u32 v2, s2, v4
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v1, v5
v_cvt_u32_f32_e32 v0, v3
v_xor_b32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_add_nc_u32_e32 v2, v4, v2
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v7, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v3, v2, s7
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_mul_hi_u32 v0, v6, v0
v_xor_b32_e32 v8, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s5
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s5, v4
v_cndmask_b32_e64 v0, v0, v6, s2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_subrev_nc_u32_e32 v7, s5, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_xor_b32_e32 v3, s6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v7, s2
v_add_nc_u32_e32 v7, 1, v0
v_add_nc_u32_e32 v6, 1, v2
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x30
s_load_b64 s[0:1], s[0:1], 0x50
v_xor_b32_e32 v2, v2, v8
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s20
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s21, s20, v0
v_add3_u32 v0, v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, s20, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_nc_u32_e32 v2, s21, v2
v_add_co_u32 v14, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v15, vcc_lo
s_clause 0x1
global_load_b32 v5, v[10:11], off
global_load_b32 v16, v[8:9], off
v_add_co_u32 v10, vcc_lo, s4, v6
global_load_b32 v17, v[12:13], off
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v12, vcc_lo, s12, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v7, vcc_lo
global_load_b32 v18, v[10:11], off
global_load_b32 v19, v[3:4], off
global_load_b32 v20, v[12:13], off
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt vmcnt(4)
v_sub_f32_e32 v4, v5, v16
s_waitcnt vmcnt(3)
v_sub_f32_e32 v16, v4, v17
v_add_co_u32 v4, vcc_lo, s18, v14
v_add_co_ci_u32_e32 v5, vcc_lo, s19, v15, vcc_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f32_e32 v16, v16, v18
v_add_co_u32 v14, vcc_lo, s18, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s19, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v20, v19, v16
v_add_co_u32 v16, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v17, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[12:13], v20, off
s_clause 0x1
global_load_b32 v18, v[4:5], off
global_load_b32 v19, v[14:15], off
v_add_co_u32 v4, vcc_lo, s10, v6
global_load_b32 v16, v[16:17], off
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v12, vcc_lo, s14, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s15, v7, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[12:13], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
s_waitcnt vmcnt(4)
v_sub_f32_e32 v9, v18, v19
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v16
s_waitcnt vmcnt(2)
v_add_f32_e32 v8, v9, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v8
global_store_b32 v[12:13], v5, off
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[10:11], off
v_add_co_u32 v2, vcc_lo, s0, v6
s_clause 0x1
global_load_b32 v8, v[0:1], off
global_load_b32 v9, v[14:15], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s16, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s17, v7, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v4, v4, v5
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v8
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, v4, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v4
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 8
.type _Z8update_hiiiPfS_S_S_S_S_,@function
_Z8update_hiiiPfS_S_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[12:13], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_add_i32 s5, s12, -1
s_add_i32 s2, s2, s4
s_ashr_i32 s6, s5, 31
s_xor_b32 s7, s2, s4
s_add_i32 s5, s5, s6
v_cvt_f32_u32_e32 v1, s7
s_xor_b32 s5, s5, s6
s_and_b32 s2, s3, 0xffff
v_cvt_f32_u32_e32 v2, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_mul_f32_e32 v3, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2)
v_cvt_u32_f32_e32 v4, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s2, v4
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v1, v5
v_cvt_u32_f32_e32 v0, v3
v_xor_b32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s2, v0
v_add_nc_u32_e32 v2, v4, v2
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v7, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v3, v2, s7
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_mul_hi_u32 v0, v6, v0
v_xor_b32_e32 v8, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s5
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s5, v4
v_cndmask_b32_e64 v0, v0, v6, s2
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_subrev_nc_u32_e32 v7, s5, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_xor_b32_e32 v3, s6, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v7, s2
v_add_nc_u32_e32 v7, 1, v0
v_add_nc_u32_e32 v6, 1, v2
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x30
v_xor_b32_e32 v2, v2, v8
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v8
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s12
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s13, s12, v0
v_add3_u32 v0, v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_subrev_nc_u32_e32 v4, s12, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v7, vcc_lo
s_clause 0x1
global_load_b32 v5, v[8:9], off
global_load_b32 v16, v[10:11], off
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
global_load_b32 v17, v[12:13], off
v_add_co_u32 v14, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s11, v7, vcc_lo
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[14:15], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v5, v5, v16
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v17
s_waitcnt vmcnt(1)
v_add_f32_e32 v5, v5, v10
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[16:17], v5
v_fma_f64 v[10:11], v[16:17], -0.5, v[10:11]
v_add_co_u32 v16, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cvt_f32_f64_e32 v5, v[10:11]
v_subrev_nc_u32_e32 v10, s13, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
global_store_b32 v[14:15], v5, off
s_clause 0x1
global_load_b32 v2, v[16:17], off
global_load_b32 v5, v[0:1], off
v_add_co_u32 v0, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v11, vcc_lo
global_load_b32 v14, v[8:9], off
v_add_co_u32 v8, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v2, v5
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v14
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[14:15], v2
v_fma_f64 v[0:1], v[14:15], -0.5, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v11, vcc_lo
global_store_b32 v[8:9], v2, off
s_clause 0x1
global_load_b32 v2, v[12:13], off
global_load_b32 v5, v[0:1], off
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v3, v[16:17], off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v7, vcc_lo
global_load_b32 v6, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v2, v2, v5
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v2, v3
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_fma_f64 v[2:3], v[2:3], -0.5, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_hiiiPfS_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z8update_hiiiPfS_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z8update_eiiiPfS_S_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_hiiiPfS_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8update_hiiiPfS_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Ex[fidx] += CEx[fidx]*( Hz[fidx+Nz] - Hz[fidx] - Hy[fidx+1] + Hy[fidx] );
Ey[fidx] += CEy[fidx]*( Hx[fidx+1] - Hx[fidx] - Hz[fidx+Nyz] + Hz[fidx] );
Ez[fidx] += CEz[fidx]*( Hy[fidx+Nyz] - Hy[fidx] - Hx[fidx+Nz] + Hx[fidx] );
}
__global__ void update_h( int Nz, int Nyz, int Nyzm, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int fidx = idx + idx/(Nz-1) + idx/Nyzm*Nz + Nyz + Nz + 1;
Hx[fidx] -= 0.5*( Ez[fidx] - Ez[fidx-Nz] - Ey[fidx] + Ey[fidx-1] );
Hy[fidx] -= 0.5*( Ex[fidx] - Ex[fidx-1] - Ez[fidx] + Ez[fidx-Nyz] );
Hz[fidx] -= 0.5*( Ey[fidx] - Ey[fidx-Nyz] - Ex[fidx] + Ex[fidx-Nz] );
} | .text
.file "non_aligned-args-Nx+1.hip"
.globl _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiiPfS_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiiPfS_S_S_S_S_,@object # @_Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.size _Z8update_hiiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiiPfS_S_S_S_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005a9ac_00000000-6_non_aligned-args-Nx+1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq 288(%rsp), %rax
movq %rax, 48(%rsp)
movq 296(%rsp), %rax
movq %rax, 40(%rsp)
movq 304(%rsp), %rax
movq %rax, 32(%rsp)
movq 312(%rsp), %rax
movq %rax, 24(%rsp)
movq 320(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.type _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, @function
_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, .-_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.type _Z8update_hiiiPfS_S_S_S_S_, @function
_Z8update_hiiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiiPfS_S_S_S_S_, .-_Z8update_hiiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "non_aligned-args-Nx+1.hip"
.globl _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiiPfS_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiiPfS_S_S_S_S_,@object # @_Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.size _Z8update_hiiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiiPfS_S_S_S_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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