system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define BLOCKSIZE 32
//Sigmoid function for logistic regression
float sigmoid(float in){
return 1.0 / (1 + exp(-1 * in));
}
//Tiled version of matrix multiply
__global__ void MatrixMultiplyKernel(float *devA, float *devB, float *devC, int rows, int cols, int k, float alpha, float beta)
{
//Get the thread's x and y locations for its run
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = threadIdx.y + blockIdx.y * blockDim.y;
//Allocate shared memory to hold parts of A and B
__shared__ float tileA[BLOCKSIZE][BLOCKSIZE];
__shared__ float tileB[BLOCKSIZE][BLOCKSIZE];
//Use sum to get the result for a specific element
float sum = 0.0;
//Use iter to see if the loop should be run again
int iter = 0;
do{
//Check if the x thread falls within bounds of the matrices
if ((idy < rows) && (threadIdx.x + BLOCKSIZE*iter < k)){
tileA[threadIdx.y][threadIdx.x] = devA[threadIdx.x + idy*k + BLOCKSIZE*iter];
}
else {
tileA[threadIdx.y][threadIdx.x] = 0.0;
}
//Check if the y thread falls within bounds of the matrices
if ((threadIdx.y + BLOCKSIZE*iter < k) && (idx < cols)){
tileB[threadIdx.y][threadIdx.x] = devB[idx + (threadIdx.y + BLOCKSIZE*iter)*cols];
}
else {
tileB[threadIdx.y][threadIdx.x] = 0.0;
}
//Sync to ensure that all of the data has been grabbed for the tiles in this warp
__syncthreads();
//Sum the elements related to the element in C corresponding to idx and idy
for (int i = 0; i < BLOCKSIZE; i++){
sum += tileA[threadIdx.y][i] * tileB[i][threadIdx.x];
}
//Iterate the number done
iter++;
//Sync the threads again to ensure they have all done their work before going through the loop to get data
__syncthreads();
//Check if the tiles have covered all of C
} while (BLOCKSIZE*iter < k);
//If the thread falls within the matrix C, fill in its element, scaled by alpha and beta
if ((idy < rows) && (idx < cols)){
devC[idx + idy*cols] = sum * alpha + devC[idx + idy*cols] * beta;
}
}
__global__ void distKernel(float *devA, float *devB, float *devC, int K)
{
int idy = threadIdx.y + blockIdx.y * blockDim.y;
if ((idy < K)){
devC[idy] = (devA[idy] - devB[idy])*(devA[idy] - devB[idy]);
}
}
//Element wise subtraction of matrix A and B, stored in matrix C
__global__ void sub_sigKernel(float *A, float *B, float *C, int rows)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
//Ensure the thread is in bounds
if (i < rows){
C[i] = (1.0 / (1 + exp(-1 * B[i])));
C[i] = A[i] - C[i];
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 32
//Sigmoid function for logistic regression
float sigmoid(float in){
return 1.0 / (1 + exp(-1 * in));
}
//Tiled version of matrix multiply
__global__ void MatrixMultiplyKernel(float *devA, float *devB, float *devC, int rows, int cols, int k, float alpha, float beta)
{
//Get the thread's x and y locations for its run
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = threadIdx.y + blockIdx.y * blockDim.y;
//Allocate shared memory to hold parts of A and B
__shared__ float tileA[BLOCKSIZE][BLOCKSIZE];
__shared__ float tileB[BLOCKSIZE][BLOCKSIZE];
//Use sum to get the result for a specific element
float sum = 0.0;
//Use iter to see if the loop should be run again
int iter = 0;
do{
//Check if the x thread falls within bounds of the matrices
if ((idy < rows) && (threadIdx.x + BLOCKSIZE*iter < k)){
tileA[threadIdx.y][threadIdx.x] = devA[threadIdx.x + idy*k + BLOCKSIZE*iter];
}
else {
tileA[threadIdx.y][threadIdx.x] = 0.0;
}
//Check if the y thread falls within bounds of the matrices
if ((threadIdx.y + BLOCKSIZE*iter < k) && (idx < cols)){
tileB[threadIdx.y][threadIdx.x] = devB[idx + (threadIdx.y + BLOCKSIZE*iter)*cols];
}
else {
tileB[threadIdx.y][threadIdx.x] = 0.0;
}
//Sync to ensure that all of the data has been grabbed for the tiles in this warp
__syncthreads();
//Sum the elements related to the element in C corresponding to idx and idy
for (int i = 0; i < BLOCKSIZE; i++){
sum += tileA[threadIdx.y][i] * tileB[i][threadIdx.x];
}
//Iterate the number done
iter++;
//Sync the threads again to ensure they have all done their work before going through the loop to get data
__syncthreads();
//Check if the tiles have covered all of C
} while (BLOCKSIZE*iter < k);
//If the thread falls within the matrix C, fill in its element, scaled by alpha and beta
if ((idy < rows) && (idx < cols)){
devC[idx + idy*cols] = sum * alpha + devC[idx + idy*cols] * beta;
}
}
__global__ void distKernel(float *devA, float *devB, float *devC, int K)
{
int idy = threadIdx.y + blockIdx.y * blockDim.y;
if ((idy < K)){
devC[idy] = (devA[idy] - devB[idy])*(devA[idy] - devB[idy]);
}
}
//Element wise subtraction of matrix A and B, stored in matrix C
__global__ void sub_sigKernel(float *A, float *B, float *C, int rows)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
//Ensure the thread is in bounds
if (i < rows){
C[i] = (1.0 / (1 + exp(-1 * B[i])));
C[i] = A[i] - C[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 32
//Sigmoid function for logistic regression
float sigmoid(float in){
return 1.0 / (1 + exp(-1 * in));
}
//Tiled version of matrix multiply
__global__ void MatrixMultiplyKernel(float *devA, float *devB, float *devC, int rows, int cols, int k, float alpha, float beta)
{
//Get the thread's x and y locations for its run
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = threadIdx.y + blockIdx.y * blockDim.y;
//Allocate shared memory to hold parts of A and B
__shared__ float tileA[BLOCKSIZE][BLOCKSIZE];
__shared__ float tileB[BLOCKSIZE][BLOCKSIZE];
//Use sum to get the result for a specific element
float sum = 0.0;
//Use iter to see if the loop should be run again
int iter = 0;
do{
//Check if the x thread falls within bounds of the matrices
if ((idy < rows) && (threadIdx.x + BLOCKSIZE*iter < k)){
tileA[threadIdx.y][threadIdx.x] = devA[threadIdx.x + idy*k + BLOCKSIZE*iter];
}
else {
tileA[threadIdx.y][threadIdx.x] = 0.0;
}
//Check if the y thread falls within bounds of the matrices
if ((threadIdx.y + BLOCKSIZE*iter < k) && (idx < cols)){
tileB[threadIdx.y][threadIdx.x] = devB[idx + (threadIdx.y + BLOCKSIZE*iter)*cols];
}
else {
tileB[threadIdx.y][threadIdx.x] = 0.0;
}
//Sync to ensure that all of the data has been grabbed for the tiles in this warp
__syncthreads();
//Sum the elements related to the element in C corresponding to idx and idy
for (int i = 0; i < BLOCKSIZE; i++){
sum += tileA[threadIdx.y][i] * tileB[i][threadIdx.x];
}
//Iterate the number done
iter++;
//Sync the threads again to ensure they have all done their work before going through the loop to get data
__syncthreads();
//Check if the tiles have covered all of C
} while (BLOCKSIZE*iter < k);
//If the thread falls within the matrix C, fill in its element, scaled by alpha and beta
if ((idy < rows) && (idx < cols)){
devC[idx + idy*cols] = sum * alpha + devC[idx + idy*cols] * beta;
}
}
__global__ void distKernel(float *devA, float *devB, float *devC, int K)
{
int idy = threadIdx.y + blockIdx.y * blockDim.y;
if ((idy < K)){
devC[idy] = (devA[idy] - devB[idy])*(devA[idy] - devB[idy]);
}
}
//Element wise subtraction of matrix A and B, stored in matrix C
__global__ void sub_sigKernel(float *A, float *B, float *C, int rows)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
//Ensure the thread is in bounds
if (i < rows){
C[i] = (1.0 / (1 + exp(-1 * B[i])));
C[i] = A[i] - C[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20MatrixMultiplyKernelPfS_S_iiiff
.globl _Z20MatrixMultiplyKernelPfS_S_iiiff
.p2align 8
.type _Z20MatrixMultiplyKernelPfS_S_iiiff,@function
_Z20MatrixMultiplyKernelPfS_S_iiiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x18
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_clause 0x1
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v7, 0
v_lshlrev_b32_e32 v5, 2, v1
s_mov_b32 s11, 0
v_lshlrev_b32_e32 v8, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v10, 0x1000, v5
v_add_nc_u32_e32 v9, v8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, v10, v8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[4:5], null, v2, s10, v[1:2]
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_cmp_le_i32_e64 s8, s8, v2
v_cmp_gt_i32_e64 s2, s9, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s12, s2, -1
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2)
s_mov_b32 s3, s8
s_mov_b32 s13, 0
s_and_saveexec_b32 s14, vcc_lo
s_lshl_b32 s15, s11, 5
s_mov_b32 s13, exec_lo
v_dual_mov_b32 v12, s15 :: v_dual_add_nc_u32 v5, s15, v1
s_and_not1_b32 s15, s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s3, s10, v5
s_and_b32 s3, s3, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s15, s3
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s14
s_cbranch_execz .LBB0_5
s_and_not1_b32 s13, s13, exec_lo
ds_store_b32 v9, v6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s14, s13
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v5, v4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_add_co_u32 v13, s3, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s3, s5, v14, s3
global_load_b32 v5, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
v_lshl_add_u32 v5, s11, 5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s3, s10, v5
s_or_b32 s3, s12, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s3
s_xor_b32 s3, exec_lo, s13
s_cbranch_execz .LBB0_9
ds_store_b32 v11, v6
.LBB0_9:
s_and_not1_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[13:14], null, v5, s9, v[3:4]
v_mov_b32_e32 v14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v13, s3, s6, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s3, s7, v14, s3
global_load_b32 v5, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v5, v10
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_12:
v_add_nc_u32_e32 v13, s3, v8
s_add_i32 s3, s3, 4
ds_load_b32 v14, v5
ds_load_b32 v13, v13
v_add_nc_u32_e32 v5, 0x80, v5
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v7, v13, v14
s_cbranch_scc0 .LBB0_12
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s3, s11, 5
s_barrier
s_cmp_ge_i32 s3, s10
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v2, s9, v[3:4]
s_load_b64 s[0:1], s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v7
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20MatrixMultiplyKernelPfS_S_iiiff
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20MatrixMultiplyKernelPfS_S_iiiff, .Lfunc_end0-_Z20MatrixMultiplyKernelPfS_S_iiiff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10distKernelPfS_S_i
.globl _Z10distKernelPfS_S_i
.p2align 8
.type _Z10distKernelPfS_S_i,@function
_Z10distKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10distKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10distKernelPfS_S_i, .Lfunc_end1-_Z10distKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13sub_sigKernelPfS_S_i
.globl _Z13sub_sigKernelPfS_S_i
.p2align 8
.type _Z13sub_sigKernelPfS_S_i,@function
_Z13sub_sigKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_add_f32_e32 v4, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v4, v4, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v3
v_mul_f32_e32 v5, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v2, v5, v6
v_fmac_f32_e32 v5, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v5, v6
v_div_fmas_f32 v5, v2, v3, v5
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v4, v5, v4, 1.0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13sub_sigKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13sub_sigKernelPfS_S_i, .Lfunc_end2-_Z13sub_sigKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20MatrixMultiplyKernelPfS_S_iiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20MatrixMultiplyKernelPfS_S_iiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10distKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10distKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13sub_sigKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13sub_sigKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKSIZE 32
//Sigmoid function for logistic regression
float sigmoid(float in){
return 1.0 / (1 + exp(-1 * in));
}
//Tiled version of matrix multiply
__global__ void MatrixMultiplyKernel(float *devA, float *devB, float *devC, int rows, int cols, int k, float alpha, float beta)
{
//Get the thread's x and y locations for its run
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = threadIdx.y + blockIdx.y * blockDim.y;
//Allocate shared memory to hold parts of A and B
__shared__ float tileA[BLOCKSIZE][BLOCKSIZE];
__shared__ float tileB[BLOCKSIZE][BLOCKSIZE];
//Use sum to get the result for a specific element
float sum = 0.0;
//Use iter to see if the loop should be run again
int iter = 0;
do{
//Check if the x thread falls within bounds of the matrices
if ((idy < rows) && (threadIdx.x + BLOCKSIZE*iter < k)){
tileA[threadIdx.y][threadIdx.x] = devA[threadIdx.x + idy*k + BLOCKSIZE*iter];
}
else {
tileA[threadIdx.y][threadIdx.x] = 0.0;
}
//Check if the y thread falls within bounds of the matrices
if ((threadIdx.y + BLOCKSIZE*iter < k) && (idx < cols)){
tileB[threadIdx.y][threadIdx.x] = devB[idx + (threadIdx.y + BLOCKSIZE*iter)*cols];
}
else {
tileB[threadIdx.y][threadIdx.x] = 0.0;
}
//Sync to ensure that all of the data has been grabbed for the tiles in this warp
__syncthreads();
//Sum the elements related to the element in C corresponding to idx and idy
for (int i = 0; i < BLOCKSIZE; i++){
sum += tileA[threadIdx.y][i] * tileB[i][threadIdx.x];
}
//Iterate the number done
iter++;
//Sync the threads again to ensure they have all done their work before going through the loop to get data
__syncthreads();
//Check if the tiles have covered all of C
} while (BLOCKSIZE*iter < k);
//If the thread falls within the matrix C, fill in its element, scaled by alpha and beta
if ((idy < rows) && (idx < cols)){
devC[idx + idy*cols] = sum * alpha + devC[idx + idy*cols] * beta;
}
}
__global__ void distKernel(float *devA, float *devB, float *devC, int K)
{
int idy = threadIdx.y + blockIdx.y * blockDim.y;
if ((idy < K)){
devC[idy] = (devA[idy] - devB[idy])*(devA[idy] - devB[idy]);
}
}
//Element wise subtraction of matrix A and B, stored in matrix C
__global__ void sub_sigKernel(float *A, float *B, float *C, int rows)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
//Ensure the thread is in bounds
if (i < rows){
C[i] = (1.0 / (1 + exp(-1 * B[i])));
C[i] = A[i] - C[i];
}
} | .text
.file "kernel.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7sigmoidf
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z7sigmoidf
.p2align 4, 0x90
.type _Z7sigmoidf,@function
_Z7sigmoidf: # @_Z7sigmoidf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorps .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq exp
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7sigmoidf, .Lfunc_end0-_Z7sigmoidf
.cfi_endproc
# -- End function
.globl _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff # -- Begin function _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.p2align 4, 0x90
.type _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff,@function
_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff: # @_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20MatrixMultiplyKernelPfS_S_iiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff, .Lfunc_end1-_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.cfi_endproc
# -- End function
.globl _Z25__device_stub__distKernelPfS_S_i # -- Begin function _Z25__device_stub__distKernelPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__distKernelPfS_S_i,@function
_Z25__device_stub__distKernelPfS_S_i: # @_Z25__device_stub__distKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10distKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__distKernelPfS_S_i, .Lfunc_end2-_Z25__device_stub__distKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__sub_sigKernelPfS_S_i # -- Begin function _Z28__device_stub__sub_sigKernelPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__sub_sigKernelPfS_S_i,@function
_Z28__device_stub__sub_sigKernelPfS_S_i: # @_Z28__device_stub__sub_sigKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sub_sigKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z28__device_stub__sub_sigKernelPfS_S_i, .Lfunc_end3-_Z28__device_stub__sub_sigKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20MatrixMultiplyKernelPfS_S_iiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10distKernelPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sub_sigKernelPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20MatrixMultiplyKernelPfS_S_iiiff,@object # @_Z20MatrixMultiplyKernelPfS_S_iiiff
.section .rodata,"a",@progbits
.globl _Z20MatrixMultiplyKernelPfS_S_iiiff
.p2align 3, 0x0
_Z20MatrixMultiplyKernelPfS_S_iiiff:
.quad _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.size _Z20MatrixMultiplyKernelPfS_S_iiiff, 8
.type _Z10distKernelPfS_S_i,@object # @_Z10distKernelPfS_S_i
.globl _Z10distKernelPfS_S_i
.p2align 3, 0x0
_Z10distKernelPfS_S_i:
.quad _Z25__device_stub__distKernelPfS_S_i
.size _Z10distKernelPfS_S_i, 8
.type _Z13sub_sigKernelPfS_S_i,@object # @_Z13sub_sigKernelPfS_S_i
.globl _Z13sub_sigKernelPfS_S_i
.p2align 3, 0x0
_Z13sub_sigKernelPfS_S_i:
.quad _Z28__device_stub__sub_sigKernelPfS_S_i
.size _Z13sub_sigKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20MatrixMultiplyKernelPfS_S_iiiff"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10distKernelPfS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13sub_sigKernelPfS_S_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.addrsig_sym _Z25__device_stub__distKernelPfS_S_i
.addrsig_sym _Z28__device_stub__sub_sigKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20MatrixMultiplyKernelPfS_S_iiiff
.addrsig_sym _Z10distKernelPfS_S_i
.addrsig_sym _Z13sub_sigKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6260_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7sigmoidf
.type _Z7sigmoidf, @function
_Z7sigmoidf:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
xorps .LC0(%rip), %xmm0
call expf@PLT
movss .LC1(%rip), %xmm1
addss %xmm1, %xmm0
divss %xmm0, %xmm1
movaps %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7sigmoidf, .-_Z7sigmoidf
.globl _Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff
.type _Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff, @function
_Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20MatrixMultiplyKernelPfS_S_iiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff, .-_Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff
.globl _Z20MatrixMultiplyKernelPfS_S_iiiff
.type _Z20MatrixMultiplyKernelPfS_S_iiiff, @function
_Z20MatrixMultiplyKernelPfS_S_iiiff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z20MatrixMultiplyKernelPfS_S_iiiffPfS_S_iiiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20MatrixMultiplyKernelPfS_S_iiiff, .-_Z20MatrixMultiplyKernelPfS_S_iiiff
.globl _Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10distKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i
.globl _Z10distKernelPfS_S_i
.type _Z10distKernelPfS_S_i, @function
_Z10distKernelPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10distKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10distKernelPfS_S_i, .-_Z10distKernelPfS_S_i
.globl _Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i
.type _Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i, @function
_Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13sub_sigKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i, .-_Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i
.globl _Z13sub_sigKernelPfS_S_i
.type _Z13sub_sigKernelPfS_S_i, @function
_Z13sub_sigKernelPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13sub_sigKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13sub_sigKernelPfS_S_i, .-_Z13sub_sigKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z13sub_sigKernelPfS_S_i"
.LC3:
.string "_Z10distKernelPfS_S_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z20MatrixMultiplyKernelPfS_S_iiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13sub_sigKernelPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10distKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z20MatrixMultiplyKernelPfS_S_iiiff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7sigmoidf
.LCPI0_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z7sigmoidf
.p2align 4, 0x90
.type _Z7sigmoidf,@function
_Z7sigmoidf: # @_Z7sigmoidf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
xorps .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
callq exp
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7sigmoidf, .Lfunc_end0-_Z7sigmoidf
.cfi_endproc
# -- End function
.globl _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff # -- Begin function _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.p2align 4, 0x90
.type _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff,@function
_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff: # @_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20MatrixMultiplyKernelPfS_S_iiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff, .Lfunc_end1-_Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.cfi_endproc
# -- End function
.globl _Z25__device_stub__distKernelPfS_S_i # -- Begin function _Z25__device_stub__distKernelPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__distKernelPfS_S_i,@function
_Z25__device_stub__distKernelPfS_S_i: # @_Z25__device_stub__distKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10distKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z25__device_stub__distKernelPfS_S_i, .Lfunc_end2-_Z25__device_stub__distKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__sub_sigKernelPfS_S_i # -- Begin function _Z28__device_stub__sub_sigKernelPfS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__sub_sigKernelPfS_S_i,@function
_Z28__device_stub__sub_sigKernelPfS_S_i: # @_Z28__device_stub__sub_sigKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13sub_sigKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z28__device_stub__sub_sigKernelPfS_S_i, .Lfunc_end3-_Z28__device_stub__sub_sigKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20MatrixMultiplyKernelPfS_S_iiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10distKernelPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13sub_sigKernelPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20MatrixMultiplyKernelPfS_S_iiiff,@object # @_Z20MatrixMultiplyKernelPfS_S_iiiff
.section .rodata,"a",@progbits
.globl _Z20MatrixMultiplyKernelPfS_S_iiiff
.p2align 3, 0x0
_Z20MatrixMultiplyKernelPfS_S_iiiff:
.quad _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.size _Z20MatrixMultiplyKernelPfS_S_iiiff, 8
.type _Z10distKernelPfS_S_i,@object # @_Z10distKernelPfS_S_i
.globl _Z10distKernelPfS_S_i
.p2align 3, 0x0
_Z10distKernelPfS_S_i:
.quad _Z25__device_stub__distKernelPfS_S_i
.size _Z10distKernelPfS_S_i, 8
.type _Z13sub_sigKernelPfS_S_i,@object # @_Z13sub_sigKernelPfS_S_i
.globl _Z13sub_sigKernelPfS_S_i
.p2align 3, 0x0
_Z13sub_sigKernelPfS_S_i:
.quad _Z28__device_stub__sub_sigKernelPfS_S_i
.size _Z13sub_sigKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20MatrixMultiplyKernelPfS_S_iiiff"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10distKernelPfS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13sub_sigKernelPfS_S_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__MatrixMultiplyKernelPfS_S_iiiff
.addrsig_sym _Z25__device_stub__distKernelPfS_S_i
.addrsig_sym _Z28__device_stub__sub_sigKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20MatrixMultiplyKernelPfS_S_iiiff
.addrsig_sym _Z10distKernelPfS_S_i
.addrsig_sym _Z13sub_sigKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} | code for sm_80
Function : _Z11matrix_multPfjjS_jjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ MOV R6, 0xffffffff ; /* 0xffffffff00067802 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0090*/ USHF.R.U32.HI UR4, URZ, 0x5, UR4 ; /* 0x000000053f047899 */
/* 0x000fc60008011604 */
/*00a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002500 */
/*00b0*/ IMAD R21, R0, c[0x0][0x4], R7 ; /* 0x0000010000157a24 */
/* 0x001fe200078e0207 */
/*00c0*/ SHF.L.U32 R19, R7, 0x7, RZ ; /* 0x0000000707137819 */
/* 0x000fe400000006ff */
/*00d0*/ MOV R16, R2 ; /* 0x0000000200107202 */
/* 0x002fe20000000f00 */
/*00e0*/ IMAD R4, R2.reuse, c[0x0][0x168], R21 ; /* 0x00005a0002047a24 */
/* 0x040fe200078e0215 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R21, c[0x0][0x168], PT ; /* 0x00005a0015007a0c */
/* 0x000fe20003f26070 */
/*0100*/ IMAD R18, R3, c[0x0][0x0], R2 ; /* 0x0000000003127a24 */
/* 0x004fe200078e0202 */
/*0110*/ LEA R17, R2, R19, 0x2 ; /* 0x0000001302117211 */
/* 0x000fc600078e10ff */
/*0120*/ IMAD R5, R18, c[0x0][0x178], R7 ; /* 0x00005e0012057a24 */
/* 0x000fe400078e0207 */
/*0130*/ ISETP.GE.U32.OR P0, PT, R16, c[0x0][0x178], P1 ; /* 0x00005e0010007a0c */
/* 0x000fe40000f06470 */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0150*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fca0000000f00 */
/*0160*/ @!P0 IMAD.WIDE.U32 R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004088625 */
/* 0x000fca00078e0009 */
/*0170*/ @!P0 LDG.E R10, [R8.64] ; /* 0x00000006080a8981 */
/* 0x000ea2000c1e1900 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R18, c[0x0][0x17c], PT ; /* 0x00005f0012007a0c */
/* 0x000fe40003f06070 */
/*0190*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GE.U32.OR P2, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000746470 */
/*01b0*/ @!P2 MOV R26, 0x4 ; /* 0x00000004001aa802 */
/* 0x000fca0000000f00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R26, R5, R26, c[0x0][0x170] ; /* 0x00005c00051aa625 */
/* 0x000fe200078e001a */
/*01d0*/ STS [R17], R10 ; /* 0x0000000a11007388 */
/* 0x004fe80000000800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @!P2 LDG.E R24, [R26.64] ; /* 0x000000061a18a981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc40007ffe0ff */
/*0210*/ IADD3 R16, R16, 0x20, RZ ; /* 0x0000002010107810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P2, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe4000bf46070 */
/*0230*/ IADD3 R7, R7, 0x20, RZ ; /* 0x0000002007077810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x000fe20007ffe0ff */
/*0250*/ STS [R17+0x1000], R24 ; /* 0x0010001811007388 */
/* 0x004fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R22, [R2.X4+0x1000] ; /* 0x0010000002167984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R20, [R2.X4+0x1180] ; /* 0x0011800002147984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R23, [R2.X4+0x1200] ; /* 0x0012000002177984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R24, [R2.X4+0x1380] ; /* 0x0013800002187984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS R27, [R2.X4+0x1400] ; /* 0x00140000021b7984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R26, [R2.X4+0x1580] ; /* 0x00158000021a7984 */
/* 0x000fe20000004800 */
/*0310*/ FFMA R12, R22, R12, R25 ; /* 0x0000000c160c7223 */
/* 0x001fc60000000019 */
/*0320*/ LDS R22, [R2.X4+0x1280] ; /* 0x0012800002167984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*0340*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000e620000004800 */
/*0350*/ FFMA R12, R29, R14, R12 ; /* 0x0000000e1d0c7223 */
/* 0x004fc6000000000c */
/*0360*/ LDS R29, [R2.X4+0x1900] ; /* 0x00190000021d7984 */
/* 0x000fe20000004800 */
/*0370*/ FFMA R20, R20, R15, R12 ; /* 0x0000000f14147223 */
/* 0x008fc6000000000c */
/*0380*/ LDS.128 R12, [R19+0x20] ; /* 0x00002000130c7984 */
/* 0x000ea20000000c00 */
/*0390*/ FFMA R8, R23, R8, R20 ; /* 0x0000000817087223 */
/* 0x010fc60000000014 */
/*03a0*/ LDS R20, [R2.X4+0x1480] ; /* 0x0014800002147984 */
/* 0x000ee80000004800 */
/*03b0*/ LDS R23, [R2.X4+0x1500] ; /* 0x0015000002177984 */
/* 0x000f220000004800 */
/*03c0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x001fc60000000008 */
/*03d0*/ LDS R22, [R2.X4+0x1680] ; /* 0x0016800002167984 */
/* 0x000fe20000004800 */
/*03e0*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x002fc60000000008 */
/*03f0*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0400*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x000fc60000000008 */
/*0410*/ LDS.128 R8, [R19+0x30] ; /* 0x0000300013087984 */
/* 0x000e220000000c00 */
/*0420*/ FFMA R12, R27, R12, R24 ; /* 0x0000000c1b0c7223 */
/* 0x004fc60000000018 */
/*0430*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000e680000004800 */
/*0440*/ LDS R24, [R2.X4+0x1780] ; /* 0x0017800002187984 */
/* 0x000ea20000004800 */
/*0450*/ FFMA R12, R20, R13, R12 ; /* 0x0000000d140c7223 */
/* 0x008fc6000000000c */
/*0460*/ LDS R20, [R2.X4+0x1880] ; /* 0x0018800002147984 */
/* 0x000fe20000004800 */
/*0470*/ FFMA R12, R23, R14, R12 ; /* 0x0000000e170c7223 */
/* 0x010fc6000000000c */
/*0480*/ LDS R23, [R2.X4+0x1800] ; /* 0x0018000002177984 */
/* 0x000fe20000004800 */
/*0490*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x000fc6000000000c */
/*04a0*/ LDS.128 R12, [R19+0x40] ; /* 0x00004000130c7984 */
/* 0x000ee20000000c00 */
/*04b0*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R26, [R2.X4+0x1980] ; /* 0x00198000021a7984 */
/* 0x000e220000004800 */
/*04d0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x000fc60000000008 */
/*04e0*/ LDS R25, [R2.X4+0x1a00] ; /* 0x001a000002197984 */
/* 0x000fe20000004800 */
/*04f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x002fc60000000008 */
/*0500*/ LDS R22, [R2.X4+0x1a80] ; /* 0x001a800002167984 */
/* 0x000fe20000004800 */
/*0510*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x004fc60000000008 */
/*0520*/ LDS.128 R8, [R19+0x50] ; /* 0x0000500013087984 */
/* 0x000e680000000c00 */
/*0530*/ LDS R27, [R2.X4+0x1c00] ; /* 0x001c0000021b7984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R12, R23, R12, R24 ; /* 0x0000000c170c7223 */
/* 0x008fc60000000018 */
/*0550*/ LDS R23, [R2.X4+0x1b00] ; /* 0x001b000002177984 */
/* 0x000ea20000004800 */
/*0560*/ FFMA R12, R20, R13, R12 ; /* 0x0000000d140c7223 */
/* 0x000fc6000000000c */
/*0570*/ LDS R24, [R2.X4+0x1b80] ; /* 0x001b800002187984 */
/* 0x000ee20000004800 */
/*0580*/ FFMA R12, R29, R14, R12 ; /* 0x0000000e1d0c7223 */
/* 0x000fc6000000000c */
/*0590*/ LDS R20, [R2.X4+0x1c80] ; /* 0x001c800002147984 */
/* 0x000fe20000004800 */
/*05a0*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x001fc6000000000c */
/*05b0*/ LDS.128 R12, [R19+0x60] ; /* 0x00006000130c7984 */
/* 0x000e220000000c00 */
/*05c0*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x002fc6000000001a */
/*05d0*/ LDS R25, [R2.X4+0x1d00] ; /* 0x001d000002197984 */
/* 0x000e620000004800 */
/*05e0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x000fc60000000008 */
/*05f0*/ LDS R22, [R2.X4+0x1d80] ; /* 0x001d800002167984 */
/* 0x000f220000004800 */
/*0600*/ FFMA R8, R23, R10, R8 ; /* 0x0000000a17087223 */
/* 0x004fc60000000008 */
/*0610*/ LDS R23, [R2.X4+0x1e00] ; /* 0x001e000002177984 */
/* 0x000fe20000004800 */
/*0620*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x008fc60000000008 */
/*0630*/ LDS.128 R8, [R19+0x70] ; /* 0x0000700013087984 */
/* 0x000ea20000000c00 */
/*0640*/ FFMA R24, R27, R12, R24 ; /* 0x0000000c1b187223 */
/* 0x001fc60000000018 */
/*0650*/ LDS R12, [R2.X4+0x1e80] ; /* 0x001e8000020c7984 */
/* 0x000e220000004800 */
/*0660*/ FFMA R24, R20, R13, R24 ; /* 0x0000000d14187223 */
/* 0x000fc60000000018 */
/*0670*/ LDS R13, [R2.X4+0x1f00] ; /* 0x001f0000020d7984 */
/* 0x000ee80000004800 */
/*0680*/ LDS R20, [R2.X4+0x1f80] ; /* 0x001f800002147984 */
/* 0x000f620000004800 */
/*0690*/ FFMA R14, R25, R14, R24 ; /* 0x0000000e190e7223 */
/* 0x002fc80000000018 */
/*06a0*/ FFMA R14, R22, R15, R14 ; /* 0x0000000f160e7223 */
/* 0x010fc8000000000e */
/*06b0*/ FFMA R8, R23, R8, R14 ; /* 0x0000000817087223 */
/* 0x004fc8000000000e */
/*06c0*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x001fe20000000008 */
/*06d0*/ MOV R9, 0x20 ; /* 0x0000002000097802 */
/* 0x000fc60000000f00 */
/*06e0*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x008fe40000000008 */
/*06f0*/ IMAD R4, R9, c[0x0][0x168], R4 ; /* 0x00005a0009047a24 */
/* 0x000fe400078e0204 */
/*0700*/ FFMA R25, R20, R11, R8 ; /* 0x0000000b14197223 */
/* 0x020fe20000000008 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @!P2 BRA 0x130 ; /* 0xfffffa000000a947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.GE.U32.OR P0, PT, R21, c[0x0][0x168], P0 ; /* 0x00005a0015007a0c */
/* 0x000fda0000706470 */
/*0740*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0750*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0760*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0770*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0202 */
/*0780*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0790*/ IMAD R5, R0, c[0x0][0x4], R5 ; /* 0x0000010000057a24 */
/* 0x002fc800078e0205 */
/*07a0*/ IMAD R2, R2, c[0x0][0x168], R5 ; /* 0x00005a0002027a24 */
/* 0x000fca00078e0205 */
/*07b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0003 */
/*07c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101906 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} | .file "tmpxft_00074011_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
.type _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_, @function
_Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11matrix_multPfjjS_jjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_, .-_Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
.globl _Z11matrix_multPfjjS_jjS_
.type _Z11matrix_multPfjjS_jjS_, @function
_Z11matrix_multPfjjS_jjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11matrix_multPfjjS_jjS_, .-_Z11matrix_multPfjjS_jjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matrix_multPfjjS_jjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multPfjjS_jjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} | #include <hip/hip_runtime.h>
#include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multPfjjS_jjS_
.globl _Z11matrix_multPfjjS_jjS_
.p2align 8
.type _Z11matrix_multPfjjS_jjS_,@function
_Z11matrix_multPfjjS_jjS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x8
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v1
v_lshlrev_b32_e32 v7, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 0x1000, v5
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, v9, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s6, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s14, s10, v[1:2]
s_lshr_b32 s10, s2, 5
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_xor_b32 s11, vcc_lo, -1
v_mul_lo_u32 v10, v3, s6
v_cmp_gt_u32_e64 s2, s7, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s2, s2, -1
.LBB0_1:
s_lshl_b32 s13, s12, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s13, v1
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_or_b32 s14, s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_3
ds_store_b32 v8, v5
.LBB0_3:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[12:13], null, v4, s3, v[2:3]
v_mov_b32_e32 v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s8, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
global_load_b32 v4, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v4, s13, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_or_b32 s13, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s13
s_xor_b32 s13, exec_lo, s14
s_cbranch_execz .LBB0_7
ds_store_b32 v11, v5
.LBB0_7:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v4, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v4, v9
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_10:
v_add_nc_u32_e32 v12, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v13, v4
ds_load_b32 v12, v12
v_add_nc_u32_e32 v4, 0x80, v4
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, v12, v13
s_cbranch_scc0 .LBB0_10
s_add_i32 s13, s12, 1
s_cmp_eq_u32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_mov_b32 s12, s13
s_branch .LBB0_1
.LBB0_13:
v_cmp_gt_u32_e32 vcc_lo, s3, v2
v_cmp_gt_u32_e64 s2, s7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multPfjjS_jjS_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multPfjjS_jjS_, .Lfunc_end0-_Z11matrix_multPfjjS_jjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multPfjjS_jjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_multPfjjS_jjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//header files included
//declaring the tile width and height
//for tile based matrix multiplication
#define TILE_WIDTH 32
#define TILE_HEIGHT 32
//Namespace for std
using namespace std;
//structure declaration for storing rows and columns for a matrix
struct matrix{
unsigned int rows; //storing rows of a matrix
unsigned int cols; //storing columns of a matrix
};
//handlerror declaration : to display file and line numbers of erroneous lines
__global__ void matrix_mult(float* array1, unsigned int rows1, unsigned int cols1, float* array2, unsigned int rows2, unsigned int cols2, float* array3)
{
//shared memory takes one tile at a time
__shared__ float S1[TILE_WIDTH][TILE_HEIGHT]; //to store tiles for array 1
__shared__ float S2[TILE_HEIGHT][TILE_WIDTH]; //to store tiles for array 2
//threads x and y index for the current block
unsigned int tx=threadIdx.x;
unsigned int ty=threadIdx.y;
unsigned int c=blockIdx.x*blockDim.x + threadIdx.x; //row value using x-index of current thread
unsigned int r=blockIdx.y*blockDim.y + threadIdx.y; //column value using y-index of current thread
unsigned int idx=c*rows1+r; //column major index, using row and column value
float val=0; //register to store multiplication result initialized to zero
for(int m=0; m<1+((rows2-1)/TILE_WIDTH);m++) //going over all tiles one by one, with each m
{
int var1=m*TILE_WIDTH+tx ; //x thread value for current tile
int var2=m*TILE_WIDTH+ty ; //y thread value for current tile
//copying a tile from array1
if (r < rows1 && var1 < rows2) //if the value is associated to a valid matrix coordinate in array1 then store it to shared memory S1
S1[ty][tx]=array1[r + var1*rows1];//storing a "valid" value from array to shared memory
else
S1[ty][tx]=0; //storing zero, since there is no valid value
__syncthreads(); //syncing all threads once shared memory S1 is stored
//copying a tile from array2
if(c < cols2 && var2 < rows2) //if value is associates to a valid matrix coordinate in array2 then store it to shared memory S2
S2[ty][tx]=array2[var2+rows2*c]; //storing the valid value
else
S2[ty][tx]=0; //storing zero, since no valid value
__syncthreads(); //synchronizing threads
for(int i=0; i<TILE_WIDTH;i++) //going over entire tile, ty row in S1 and tx column in S2
val+=S1[ty][i]*S2[i][tx]; //and multiplying elements
__syncthreads(); //synchronizing threads
}
if(r < rows1 && c< cols2) //removing degenerate cases
array3[idx]=val; //saving multiplication result to global memory
} | .text
.file "matrix_mult.hip"
.globl _Z26__device_stub__matrix_multPfjjS_jjS_ # -- Begin function _Z26__device_stub__matrix_multPfjjS_jjS_
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multPfjjS_jjS_,@function
_Z26__device_stub__matrix_multPfjjS_jjS_: # @_Z26__device_stub__matrix_multPfjjS_jjS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multPfjjS_jjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multPfjjS_jjS_, .Lfunc_end0-_Z26__device_stub__matrix_multPfjjS_jjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multPfjjS_jjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multPfjjS_jjS_,@object # @_Z11matrix_multPfjjS_jjS_
.section .rodata,"a",@progbits
.globl _Z11matrix_multPfjjS_jjS_
.p2align 3, 0x0
_Z11matrix_multPfjjS_jjS_:
.quad _Z26__device_stub__matrix_multPfjjS_jjS_
.size _Z11matrix_multPfjjS_jjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matrix_multPfjjS_jjS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multPfjjS_jjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multPfjjS_jjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11matrix_multPfjjS_jjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0060*/ MOV R6, 0xffffffff ; /* 0xffffffff00067802 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0090*/ USHF.R.U32.HI UR4, URZ, 0x5, UR4 ; /* 0x000000053f047899 */
/* 0x000fc60008011604 */
/*00a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002500 */
/*00b0*/ IMAD R21, R0, c[0x0][0x4], R7 ; /* 0x0000010000157a24 */
/* 0x001fe200078e0207 */
/*00c0*/ SHF.L.U32 R19, R7, 0x7, RZ ; /* 0x0000000707137819 */
/* 0x000fe400000006ff */
/*00d0*/ MOV R16, R2 ; /* 0x0000000200107202 */
/* 0x002fe20000000f00 */
/*00e0*/ IMAD R4, R2.reuse, c[0x0][0x168], R21 ; /* 0x00005a0002047a24 */
/* 0x040fe200078e0215 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R21, c[0x0][0x168], PT ; /* 0x00005a0015007a0c */
/* 0x000fe20003f26070 */
/*0100*/ IMAD R18, R3, c[0x0][0x0], R2 ; /* 0x0000000003127a24 */
/* 0x004fe200078e0202 */
/*0110*/ LEA R17, R2, R19, 0x2 ; /* 0x0000001302117211 */
/* 0x000fc600078e10ff */
/*0120*/ IMAD R5, R18, c[0x0][0x178], R7 ; /* 0x00005e0012057a24 */
/* 0x000fe400078e0207 */
/*0130*/ ISETP.GE.U32.OR P0, PT, R16, c[0x0][0x178], P1 ; /* 0x00005e0010007a0c */
/* 0x000fe40000f06470 */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0150*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fca0000000f00 */
/*0160*/ @!P0 IMAD.WIDE.U32 R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004088625 */
/* 0x000fca00078e0009 */
/*0170*/ @!P0 LDG.E R10, [R8.64] ; /* 0x00000006080a8981 */
/* 0x000ea2000c1e1900 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R18, c[0x0][0x17c], PT ; /* 0x00005f0012007a0c */
/* 0x000fe40003f06070 */
/*0190*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GE.U32.OR P2, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000746470 */
/*01b0*/ @!P2 MOV R26, 0x4 ; /* 0x00000004001aa802 */
/* 0x000fca0000000f00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R26, R5, R26, c[0x0][0x170] ; /* 0x00005c00051aa625 */
/* 0x000fe200078e001a */
/*01d0*/ STS [R17], R10 ; /* 0x0000000a11007388 */
/* 0x004fe80000000800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @!P2 LDG.E R24, [R26.64] ; /* 0x000000061a18a981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc40007ffe0ff */
/*0210*/ IADD3 R16, R16, 0x20, RZ ; /* 0x0000002010107810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P2, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe4000bf46070 */
/*0230*/ IADD3 R7, R7, 0x20, RZ ; /* 0x0000002007077810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x000fe20007ffe0ff */
/*0250*/ STS [R17+0x1000], R24 ; /* 0x0010001811007388 */
/* 0x004fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R22, [R2.X4+0x1000] ; /* 0x0010000002167984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R12, [R19] ; /* 0x00000000130c7984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R28, [R2.X4+0x1080] ; /* 0x00108000021c7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R29, [R2.X4+0x1100] ; /* 0x00110000021d7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R20, [R2.X4+0x1180] ; /* 0x0011800002147984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R23, [R2.X4+0x1200] ; /* 0x0012000002177984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R24, [R2.X4+0x1380] ; /* 0x0013800002187984 */
/* 0x000fe80000004800 */
/*02f0*/ LDS R27, [R2.X4+0x1400] ; /* 0x00140000021b7984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R26, [R2.X4+0x1580] ; /* 0x00158000021a7984 */
/* 0x000fe20000004800 */
/*0310*/ FFMA R12, R22, R12, R25 ; /* 0x0000000c160c7223 */
/* 0x001fc60000000019 */
/*0320*/ LDS R22, [R2.X4+0x1280] ; /* 0x0012800002167984 */
/* 0x000e220000004800 */
/*0330*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*0340*/ LDS R25, [R2.X4+0x1300] ; /* 0x0013000002197984 */
/* 0x000e620000004800 */
/*0350*/ FFMA R12, R29, R14, R12 ; /* 0x0000000e1d0c7223 */
/* 0x004fc6000000000c */
/*0360*/ LDS R29, [R2.X4+0x1900] ; /* 0x00190000021d7984 */
/* 0x000fe20000004800 */
/*0370*/ FFMA R20, R20, R15, R12 ; /* 0x0000000f14147223 */
/* 0x008fc6000000000c */
/*0380*/ LDS.128 R12, [R19+0x20] ; /* 0x00002000130c7984 */
/* 0x000ea20000000c00 */
/*0390*/ FFMA R8, R23, R8, R20 ; /* 0x0000000817087223 */
/* 0x010fc60000000014 */
/*03a0*/ LDS R20, [R2.X4+0x1480] ; /* 0x0014800002147984 */
/* 0x000ee80000004800 */
/*03b0*/ LDS R23, [R2.X4+0x1500] ; /* 0x0015000002177984 */
/* 0x000f220000004800 */
/*03c0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x001fc60000000008 */
/*03d0*/ LDS R22, [R2.X4+0x1680] ; /* 0x0016800002167984 */
/* 0x000fe20000004800 */
/*03e0*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x002fc60000000008 */
/*03f0*/ LDS R25, [R2.X4+0x1600] ; /* 0x0016000002197984 */
/* 0x000fe20000004800 */
/*0400*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x000fc60000000008 */
/*0410*/ LDS.128 R8, [R19+0x30] ; /* 0x0000300013087984 */
/* 0x000e220000000c00 */
/*0420*/ FFMA R12, R27, R12, R24 ; /* 0x0000000c1b0c7223 */
/* 0x004fc60000000018 */
/*0430*/ LDS R27, [R2.X4+0x1700] ; /* 0x00170000021b7984 */
/* 0x000e680000004800 */
/*0440*/ LDS R24, [R2.X4+0x1780] ; /* 0x0017800002187984 */
/* 0x000ea20000004800 */
/*0450*/ FFMA R12, R20, R13, R12 ; /* 0x0000000d140c7223 */
/* 0x008fc6000000000c */
/*0460*/ LDS R20, [R2.X4+0x1880] ; /* 0x0018800002147984 */
/* 0x000fe20000004800 */
/*0470*/ FFMA R12, R23, R14, R12 ; /* 0x0000000e170c7223 */
/* 0x010fc6000000000c */
/*0480*/ LDS R23, [R2.X4+0x1800] ; /* 0x0018000002177984 */
/* 0x000fe20000004800 */
/*0490*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x000fc6000000000c */
/*04a0*/ LDS.128 R12, [R19+0x40] ; /* 0x00004000130c7984 */
/* 0x000ee20000000c00 */
/*04b0*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R26, [R2.X4+0x1980] ; /* 0x00198000021a7984 */
/* 0x000e220000004800 */
/*04d0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x000fc60000000008 */
/*04e0*/ LDS R25, [R2.X4+0x1a00] ; /* 0x001a000002197984 */
/* 0x000fe20000004800 */
/*04f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x002fc60000000008 */
/*0500*/ LDS R22, [R2.X4+0x1a80] ; /* 0x001a800002167984 */
/* 0x000fe20000004800 */
/*0510*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x004fc60000000008 */
/*0520*/ LDS.128 R8, [R19+0x50] ; /* 0x0000500013087984 */
/* 0x000e680000000c00 */
/*0530*/ LDS R27, [R2.X4+0x1c00] ; /* 0x001c0000021b7984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R12, R23, R12, R24 ; /* 0x0000000c170c7223 */
/* 0x008fc60000000018 */
/*0550*/ LDS R23, [R2.X4+0x1b00] ; /* 0x001b000002177984 */
/* 0x000ea20000004800 */
/*0560*/ FFMA R12, R20, R13, R12 ; /* 0x0000000d140c7223 */
/* 0x000fc6000000000c */
/*0570*/ LDS R24, [R2.X4+0x1b80] ; /* 0x001b800002187984 */
/* 0x000ee20000004800 */
/*0580*/ FFMA R12, R29, R14, R12 ; /* 0x0000000e1d0c7223 */
/* 0x000fc6000000000c */
/*0590*/ LDS R20, [R2.X4+0x1c80] ; /* 0x001c800002147984 */
/* 0x000fe20000004800 */
/*05a0*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x001fc6000000000c */
/*05b0*/ LDS.128 R12, [R19+0x60] ; /* 0x00006000130c7984 */
/* 0x000e220000000c00 */
/*05c0*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x002fc6000000001a */
/*05d0*/ LDS R25, [R2.X4+0x1d00] ; /* 0x001d000002197984 */
/* 0x000e620000004800 */
/*05e0*/ FFMA R8, R22, R9, R8 ; /* 0x0000000916087223 */
/* 0x000fc60000000008 */
/*05f0*/ LDS R22, [R2.X4+0x1d80] ; /* 0x001d800002167984 */
/* 0x000f220000004800 */
/*0600*/ FFMA R8, R23, R10, R8 ; /* 0x0000000a17087223 */
/* 0x004fc60000000008 */
/*0610*/ LDS R23, [R2.X4+0x1e00] ; /* 0x001e000002177984 */
/* 0x000fe20000004800 */
/*0620*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x008fc60000000008 */
/*0630*/ LDS.128 R8, [R19+0x70] ; /* 0x0000700013087984 */
/* 0x000ea20000000c00 */
/*0640*/ FFMA R24, R27, R12, R24 ; /* 0x0000000c1b187223 */
/* 0x001fc60000000018 */
/*0650*/ LDS R12, [R2.X4+0x1e80] ; /* 0x001e8000020c7984 */
/* 0x000e220000004800 */
/*0660*/ FFMA R24, R20, R13, R24 ; /* 0x0000000d14187223 */
/* 0x000fc60000000018 */
/*0670*/ LDS R13, [R2.X4+0x1f00] ; /* 0x001f0000020d7984 */
/* 0x000ee80000004800 */
/*0680*/ LDS R20, [R2.X4+0x1f80] ; /* 0x001f800002147984 */
/* 0x000f620000004800 */
/*0690*/ FFMA R14, R25, R14, R24 ; /* 0x0000000e190e7223 */
/* 0x002fc80000000018 */
/*06a0*/ FFMA R14, R22, R15, R14 ; /* 0x0000000f160e7223 */
/* 0x010fc8000000000e */
/*06b0*/ FFMA R8, R23, R8, R14 ; /* 0x0000000817087223 */
/* 0x004fc8000000000e */
/*06c0*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x001fe20000000008 */
/*06d0*/ MOV R9, 0x20 ; /* 0x0000002000097802 */
/* 0x000fc60000000f00 */
/*06e0*/ FFMA R8, R13, R10, R8 ; /* 0x0000000a0d087223 */
/* 0x008fe40000000008 */
/*06f0*/ IMAD R4, R9, c[0x0][0x168], R4 ; /* 0x00005a0009047a24 */
/* 0x000fe400078e0204 */
/*0700*/ FFMA R25, R20, R11, R8 ; /* 0x0000000b14197223 */
/* 0x020fe20000000008 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ @!P2 BRA 0x130 ; /* 0xfffffa000000a947 */
/* 0x000fea000383ffff */
/*0730*/ ISETP.GE.U32.OR P0, PT, R21, c[0x0][0x168], P0 ; /* 0x00005a0015007a0c */
/* 0x000fda0000706470 */
/*0740*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0750*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0760*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0770*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0202 */
/*0780*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0790*/ IMAD R5, R0, c[0x0][0x4], R5 ; /* 0x0000010000057a24 */
/* 0x002fc800078e0205 */
/*07a0*/ IMAD R2, R2, c[0x0][0x168], R5 ; /* 0x00005a0002027a24 */
/* 0x000fca00078e0205 */
/*07b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0003 */
/*07c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101906 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x7e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multPfjjS_jjS_
.globl _Z11matrix_multPfjjS_jjS_
.p2align 8
.type _Z11matrix_multPfjjS_jjS_,@function
_Z11matrix_multPfjjS_jjS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x8
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v1
v_lshlrev_b32_e32 v7, 7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v9, 0x1000, v5
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, v9, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s6, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s14, s10, v[1:2]
s_lshr_b32 s10, s2, 5
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_xor_b32 s11, vcc_lo, -1
v_mul_lo_u32 v10, v3, s6
v_cmp_gt_u32_e64 s2, s7, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s2, s2, -1
.LBB0_1:
s_lshl_b32 s13, s12, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s13, v1
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_or_b32 s14, s11, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_3
ds_store_b32 v8, v5
.LBB0_3:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[12:13], null, v4, s3, v[2:3]
v_mov_b32_e32 v13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s8, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
global_load_b32 v4, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v4, s13, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_or_b32 s13, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s13
s_xor_b32 s13, exec_lo, s14
s_cbranch_execz .LBB0_7
ds_store_b32 v11, v5
.LBB0_7:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v4, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v4, v9
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_10:
v_add_nc_u32_e32 v12, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v13, v4
ds_load_b32 v12, v12
v_add_nc_u32_e32 v4, 0x80, v4
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, v12, v13
s_cbranch_scc0 .LBB0_10
s_add_i32 s13, s12, 1
s_cmp_eq_u32 s12, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_mov_b32 s12, s13
s_branch .LBB0_1
.LBB0_13:
v_cmp_gt_u32_e32 vcc_lo, s3, v2
v_cmp_gt_u32_e64 s2, s7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_15
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multPfjjS_jjS_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multPfjjS_jjS_, .Lfunc_end0-_Z11matrix_multPfjjS_jjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multPfjjS_jjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_multPfjjS_jjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074011_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
.type _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_, @function
_Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11matrix_multPfjjS_jjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_, .-_Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
.globl _Z11matrix_multPfjjS_jjS_
.type _Z11matrix_multPfjjS_jjS_, @function
_Z11matrix_multPfjjS_jjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z11matrix_multPfjjS_jjS_PfjjS_jjS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11matrix_multPfjjS_jjS_, .-_Z11matrix_multPfjjS_jjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matrix_multPfjjS_jjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multPfjjS_jjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult.hip"
.globl _Z26__device_stub__matrix_multPfjjS_jjS_ # -- Begin function _Z26__device_stub__matrix_multPfjjS_jjS_
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multPfjjS_jjS_,@function
_Z26__device_stub__matrix_multPfjjS_jjS_: # @_Z26__device_stub__matrix_multPfjjS_jjS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multPfjjS_jjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multPfjjS_jjS_, .Lfunc_end0-_Z26__device_stub__matrix_multPfjjS_jjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multPfjjS_jjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multPfjjS_jjS_,@object # @_Z11matrix_multPfjjS_jjS_
.section .rodata,"a",@progbits
.globl _Z11matrix_multPfjjS_jjS_
.p2align 3, 0x0
_Z11matrix_multPfjjS_jjS_:
.quad _Z26__device_stub__matrix_multPfjjS_jjS_
.size _Z11matrix_multPfjjS_jjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matrix_multPfjjS_jjS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multPfjjS_jjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multPfjjS_jjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
cudaMalloc(&da, bytes);
cudaMalloc(&db, bytes);
cudaMalloc(&dc, bytes);
cudaError_t err = cudaSuccess;
err = cudaMemcpy(da, a.data(), bytes, cudaMemcpyHostToDevice);
err = cudaMemcpy(db, b.data(), bytes, cudaMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
cudaDeviceSynchronize();
err = cudaMemcpy(c.data(), dc, bytes, cudaMemcpyDeviceToHost);
if(err == cudaSuccess)
cout << "cudaMemcpyDeviceToHost ok." << endl;
else
cout << err << " cudaMemcpyDeviceToHost failed." << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} | code for sm_80
Function : _Z6addVecPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
cudaMalloc(&da, bytes);
cudaMalloc(&db, bytes);
cudaMalloc(&dc, bytes);
cudaError_t err = cudaSuccess;
err = cudaMemcpy(da, a.data(), bytes, cudaMemcpyHostToDevice);
err = cudaMemcpy(db, b.data(), bytes, cudaMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
cudaDeviceSynchronize();
err = cudaMemcpy(c.data(), dc, bytes, cudaMemcpyDeviceToHost);
if(err == cudaSuccess)
cout << "cudaMemcpyDeviceToHost ok." << endl;
else
cout << err << " cudaMemcpyDeviceToHost failed." << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} | .file "tmpxft_0007a3bb_00000000-6_myAddVec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addVecPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.globl _Z6addVecPiS_S_i
.type _Z6addVecPiS_S_i, @function
_Z6addVecPiS_S_i:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z6addVecPiS_S_i, .-_Z6addVecPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6addVecPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addVecPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4373:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4373:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string "Demo: CUDA add vector"
.LC2:
.string "GridSize="
.LC3:
.string "BlockSize="
.LC4:
.string "cudaMemcpyDeviceToHost ok."
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " cudaMemcpyDeviceToHost failed."
.section .rodata.str1.1
.LC6:
.string "c[0]:"
.LC7:
.string "c[100]:"
.LC8:
.string "CUDA add vector successfully!"
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 64(%rsp)
.L20:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $4000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 80(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 96(%rsp)
.L21:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $4000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r12
movq %rax, 112(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 128(%rsp)
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq %rdx, 120(%rsp)
movq %rsp, %rdi
movl $4000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $4, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movl $1000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.L23:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L24
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L25
.L24:
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L25:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 400(%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L27:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L28:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L32:
endbr64
movq %rax, %rbx
jmp .L27
.L31:
endbr64
movq %rax, %rbx
jmp .L28
.L29:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L31-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L32-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L33-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
cudaMalloc(&da, bytes);
cudaMalloc(&db, bytes);
cudaMalloc(&dc, bytes);
cudaError_t err = cudaSuccess;
err = cudaMemcpy(da, a.data(), bytes, cudaMemcpyHostToDevice);
err = cudaMemcpy(db, b.data(), bytes, cudaMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
cudaDeviceSynchronize();
err = cudaMemcpy(c.data(), dc, bytes, cudaMemcpyDeviceToHost);
if(err == cudaSuccess)
cout << "cudaMemcpyDeviceToHost ok." << endl;
else
cout << err << " cudaMemcpyDeviceToHost failed." << endl;
cudaFree(da);
cudaFree(db);
cudaFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
hipMalloc(&da, bytes);
hipMalloc(&db, bytes);
hipMalloc(&dc, bytes);
hipError_t err = hipSuccess;
err = hipMemcpy(da, a.data(), bytes, hipMemcpyHostToDevice);
err = hipMemcpy(db, b.data(), bytes, hipMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
hipDeviceSynchronize();
err = hipMemcpy(c.data(), dc, bytes, hipMemcpyDeviceToHost);
if(err == hipSuccess)
cout << "hipMemcpyDeviceToHost ok." << endl;
else
cout << err << " hipMemcpyDeviceToHost failed." << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
hipMalloc(&da, bytes);
hipMalloc(&db, bytes);
hipMalloc(&dc, bytes);
hipError_t err = hipSuccess;
err = hipMemcpy(da, a.data(), bytes, hipMemcpyHostToDevice);
err = hipMemcpy(db, b.data(), bytes, hipMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
hipDeviceSynchronize();
err = hipMemcpy(c.data(), dc, bytes, hipMemcpyDeviceToHost);
if(err == hipSuccess)
cout << "hipMemcpyDeviceToHost ok." << endl;
else
cout << err << " hipMemcpyDeviceToHost failed." << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addVecPiS_S_i
.globl _Z6addVecPiS_S_i
.p2align 8
.type _Z6addVecPiS_S_i,@function
_Z6addVecPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addVecPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addVecPiS_S_i, .Lfunc_end0-_Z6addVecPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addVecPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addVecPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // test cuda programming
// nvcc myAddVec.cu -o myAddVec
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <assert.h>
using namespace std;
__global__ void addVec(int* da, int* db, int* dc, int n) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < n) {
dc[tid] = da[tid] + db[tid];
}
}
int main() {
cout << "Demo: CUDA add vector" << endl;
const int n = 1000;
size_t bytes = n*sizeof(int);
vector<int> a = vector<int>(n, 1);
vector<int> b = vector<int>(n, 2);
vector<int> c = vector<int>(n, 0);
int* da;
int* db;
int* dc;
hipMalloc(&da, bytes);
hipMalloc(&db, bytes);
hipMalloc(&dc, bytes);
hipError_t err = hipSuccess;
err = hipMemcpy(da, a.data(), bytes, hipMemcpyHostToDevice);
err = hipMemcpy(db, b.data(), bytes, hipMemcpyHostToDevice);
int BlockSize = 256;
int GridSize = (n + BlockSize - 1)/BlockSize;
cout << "GridSize=" << GridSize << endl;
cout << "BlockSize=" << BlockSize << endl;
addVec<<<GridSize, BlockSize>>>(da, db, dc, n);
hipDeviceSynchronize();
err = hipMemcpy(c.data(), dc, bytes, hipMemcpyDeviceToHost);
if(err == hipSuccess)
cout << "hipMemcpyDeviceToHost ok." << endl;
else
cout << err << " hipMemcpyDeviceToHost failed." << endl;
hipFree(da);
hipFree(db);
hipFree(dc);
cout << "c[0]:" << c[0] << endl;
cout << "c[100]:" << c[100] << endl;
assert(c[0] == 3);
assert(c[500] == 3);
cout << "CUDA add vector successfully!" << endl;
} | .text
.file "myAddVec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__addVecPiS_S_i # -- Begin function _Z21__device_stub__addVecPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addVecPiS_S_i,@function
_Z21__device_stub__addVecPiS_S_i: # @_Z21__device_stub__addVecPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addVecPiS_S_i, .Lfunc_end0-_Z21__device_stub__addVecPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_95
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_5
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp1:
# %bb.7: # %.lr.ph.i.i.i.i.i.i.i.i.i29.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph.i.i.i.i.i.i.i.i.i29
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_8
# %bb.9: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit33
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp4:
# %bb.10: # %.lr.ph.i.i.i.i.i.i.i.i.i34.preheader
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp7:
# %bb.11: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp9:
# %bb.12: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit41
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp11:
# %bb.13: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit43
movq 24(%rsp), %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.14:
movq 16(%rsp), %rdi
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.15:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $4, %esi
callq _ZNSolsEi
.Ltmp21:
# %bb.17:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r13)
je .LBB1_20
# %bb.19:
movzbl 67(%r13), %eax
jmp .LBB1_22
.LBB1_20:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp23:
# %bb.21: # %.noexc88
movq (%r13), %rax
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp25:
.LBB1_22: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp26:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp27:
# %bb.23: # %.noexc90
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp29:
# %bb.24: # %_ZNSolsEPFRSoS_E.exit
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $256, %esi # imm = 0x100
callq _ZNSolsEi
.Ltmp33:
# %bb.26:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r13)
je .LBB1_29
# %bb.28:
movzbl 67(%r13), %eax
jmp .LBB1_31
.LBB1_29:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.30: # %.noexc99
movq (%r13), %rax
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB1_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i96
.Ltmp38:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp39:
# %bb.32: # %.noexc101
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit49
.Ltmp42:
.cfi_escape 0x2e, 0x00
movabsq $4294967300, %rdi # imm = 0x100000004
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp43:
# %bb.34:
testl %eax, %eax
jne .LBB1_37
# %bb.35:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
.Ltmp44:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp45:
# %bb.36: # %.noexc50
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp46:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp47:
.LBB1_37:
.Ltmp48:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp49:
# %bb.38:
movq 8(%rsp), %rsi
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp51:
# %bb.39:
testl %eax, %eax
je .LBB1_40
# %bb.50:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp53:
# %bb.51:
.Ltmp54:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $30, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i116
cmpb $0, 56(%r13)
jne .LBB1_56
# %bb.54:
.Ltmp56:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp57:
# %bb.55: # %.noexc121
movq (%r13), %rax
.Ltmp58:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp59:
jmp .LBB1_57
.LBB1_40:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
movl $_ZSt4cout, %r12d
cmpb $0, 56(%r13)
je .LBB1_43
.LBB1_56: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118.invoke.sink.split
movzbl 67(%r13), %eax
.LBB1_57: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118.invoke
.Ltmp66:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp67:
# %bb.58: # %.noexc123.invoke
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp69:
# %bb.59: # %_ZNSolsEPFRSoS_E.exit55
movq 24(%rsp), %rdi
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp71:
# %bb.60:
movq 16(%rsp), %rdi
.Ltmp72:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp73:
# %bb.61:
movq 8(%rsp), %rdi
.Ltmp74:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp75:
# %bb.62:
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit61
movl (%r15), %esi
.Ltmp78:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp79:
# %bb.64:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127
cmpb $0, 56(%r13)
je .LBB1_67
# %bb.66:
movzbl 67(%r13), %eax
jmp .LBB1_69
.LBB1_67:
.Ltmp80:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp81:
# %bb.68: # %.noexc132
movq (%r13), %rax
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp83:
.LBB1_69: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i129
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp85:
# %bb.70: # %.noexc134
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.71: # %_ZNSolsEPFRSoS_E.exit63
.Ltmp88:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp89:
# %bb.72: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
movl 400(%r15), %esi
.Ltmp90:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp91:
# %bb.73:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
cmpb $0, 56(%r13)
je .LBB1_76
# %bb.75:
movzbl 67(%r13), %eax
jmp .LBB1_78
.LBB1_76:
.Ltmp92:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp93:
# %bb.77: # %.noexc143
movq (%r13), %rax
.Ltmp94:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp95:
.LBB1_78: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i140
.Ltmp96:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp97:
# %bb.79: # %.noexc145
.Ltmp98:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp99:
# %bb.80: # %_ZNSolsEPFRSoS_E.exit67
.Ltmp100:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp101:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit69
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_82
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
cmpb $0, 56(%r12)
je .LBB1_86
# %bb.85:
movzbl 67(%r12), %eax
jmp .LBB1_88
.LBB1_86:
.Ltmp102:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp103:
# %bb.87: # %.noexc154
movq (%r12), %rax
.Ltmp104:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp105:
.LBB1_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i151
.Ltmp106:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp107:
# %bb.89: # %.noexc156
.Ltmp108:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp109:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit71
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_43:
.cfi_def_cfa_offset 192
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp63:
# %bb.44: # %.noexc110
movq (%r13), %rax
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp65:
# %bb.45:
movl $_ZSt4cout, %r12d
jmp .LBB1_57
.LBB1_82: # %.invoke
.Ltmp110:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp111:
# %bb.83: # %.cont
.LBB1_95:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_47:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_93
.LBB1_46:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_94
.LBB1_48:
.Ltmp17:
jmp .LBB1_92
.LBB1_91:
.Ltmp12:
jmp .LBB1_92
.LBB1_49:
.Ltmp112:
.LBB1_92: # %_ZNSt6vectorIiSaIiEED2Ev.exit77
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_93: # %_ZNSt6vectorIiSaIiEED2Ev.exit79
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_94: # %_ZNSt6vectorIiSaIiEED2Ev.exit81
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp11-.Ltmp6 # Call between .Ltmp6 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp111-.Ltmp18 # Call between .Ltmp18 and .Ltmp111
.uleb128 .Ltmp112-.Lfunc_begin0 # jumps to .Ltmp112
.byte 0 # On action: cleanup
.uleb128 .Ltmp111-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp111 # Call between .Ltmp111 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addVecPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addVecPiS_S_i,@object # @_Z6addVecPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6addVecPiS_S_i
.p2align 3, 0x0
_Z6addVecPiS_S_i:
.quad _Z21__device_stub__addVecPiS_S_i
.size _Z6addVecPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Demo: CUDA add vector"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GridSize="
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "BlockSize="
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMemcpyDeviceToHost ok."
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " hipMemcpyDeviceToHost failed."
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "c[0]:"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "c[100]:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA add vector successfully!"
.size .L.str.7, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addVecPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addVecPiS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6addVecPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addVecPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addVecPiS_S_i
.globl _Z6addVecPiS_S_i
.p2align 8
.type _Z6addVecPiS_S_i,@function
_Z6addVecPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addVecPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addVecPiS_S_i, .Lfunc_end0-_Z6addVecPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addVecPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addVecPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a3bb_00000000-6_myAddVec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.type _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, @function
_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addVecPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i, .-_Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.globl _Z6addVecPiS_S_i
.type _Z6addVecPiS_S_i, @function
_Z6addVecPiS_S_i:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z6addVecPiS_S_i, .-_Z6addVecPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6addVecPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addVecPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4373:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4373:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string "Demo: CUDA add vector"
.LC2:
.string "GridSize="
.LC3:
.string "BlockSize="
.LC4:
.string "cudaMemcpyDeviceToHost ok."
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " cudaMemcpyDeviceToHost failed."
.section .rodata.str1.1
.LC6:
.string "c[0]:"
.LC7:
.string "c[100]:"
.LC8:
.string "CUDA add vector successfully!"
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 64(%rsp)
.L20:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $4000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbp
movq %rax, 80(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 96(%rsp)
.L21:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $4000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r12
movq %rax, 112(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 128(%rsp)
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq %rdx, 120(%rsp)
movq %rsp, %rdi
movl $4000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $4, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movl $1000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z6addVecPiS_S_iPiS_S_i
.L23:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L24
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L25
.L24:
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L25:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 400(%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L27:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L28:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L32:
endbr64
movq %rax, %rbx
jmp .L27
.L31:
endbr64
movq %rax, %rbx
jmp .L28
.L29:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L31-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L32-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L33-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "myAddVec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__addVecPiS_S_i # -- Begin function _Z21__device_stub__addVecPiS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addVecPiS_S_i,@function
_Z21__device_stub__addVecPiS_S_i: # @_Z21__device_stub__addVecPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addVecPiS_S_i, .Lfunc_end0-_Z21__device_stub__addVecPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_95
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_5
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp1:
# %bb.7: # %.lr.ph.i.i.i.i.i.i.i.i.i29.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_8: # %.lr.ph.i.i.i.i.i.i.i.i.i29
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_8
# %bb.9: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit33
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp4:
# %bb.10: # %.lr.ph.i.i.i.i.i.i.i.i.i34.preheader
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp7:
# %bb.11: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp9:
# %bb.12: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit41
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.Ltmp11:
# %bb.13: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit43
movq 24(%rsp), %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.14:
movq 16(%rsp), %rdi
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.15:
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $4, %esi
callq _ZNSolsEi
.Ltmp21:
# %bb.17:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r13)
je .LBB1_20
# %bb.19:
movzbl 67(%r13), %eax
jmp .LBB1_22
.LBB1_20:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp23:
# %bb.21: # %.noexc88
movq (%r13), %rax
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp25:
.LBB1_22: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp26:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp27:
# %bb.23: # %.noexc90
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp29:
# %bb.24: # %_ZNSolsEPFRSoS_E.exit
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47
.Ltmp32:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $256, %esi # imm = 0x100
callq _ZNSolsEi
.Ltmp33:
# %bb.26:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r13)
je .LBB1_29
# %bb.28:
movzbl 67(%r13), %eax
jmp .LBB1_31
.LBB1_29:
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.30: # %.noexc99
movq (%r13), %rax
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB1_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i96
.Ltmp38:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp39:
# %bb.32: # %.noexc101
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit49
.Ltmp42:
.cfi_escape 0x2e, 0x00
movabsq $4294967300, %rdi # imm = 0x100000004
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp43:
# %bb.34:
testl %eax, %eax
jne .LBB1_37
# %bb.35:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
.Ltmp44:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp45:
# %bb.36: # %.noexc50
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp46:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z6addVecPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp47:
.LBB1_37:
.Ltmp48:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp49:
# %bb.38:
movq 8(%rsp), %rsi
.Ltmp50:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp51:
# %bb.39:
testl %eax, %eax
je .LBB1_40
# %bb.50:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp53:
# %bb.51:
.Ltmp54:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %esi
movl $30, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i116
cmpb $0, 56(%r13)
jne .LBB1_56
# %bb.54:
.Ltmp56:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp57:
# %bb.55: # %.noexc121
movq (%r13), %rax
.Ltmp58:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp59:
jmp .LBB1_57
.LBB1_40:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.41: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.42: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
movl $_ZSt4cout, %r12d
cmpb $0, 56(%r13)
je .LBB1_43
.LBB1_56: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118.invoke.sink.split
movzbl 67(%r13), %eax
.LBB1_57: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i118.invoke
.Ltmp66:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp67:
# %bb.58: # %.noexc123.invoke
.Ltmp68:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp69:
# %bb.59: # %_ZNSolsEPFRSoS_E.exit55
movq 24(%rsp), %rdi
.Ltmp70:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp71:
# %bb.60:
movq 16(%rsp), %rdi
.Ltmp72:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp73:
# %bb.61:
movq 8(%rsp), %rdi
.Ltmp74:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp75:
# %bb.62:
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit61
movl (%r15), %esi
.Ltmp78:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp79:
# %bb.64:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i127
cmpb $0, 56(%r13)
je .LBB1_67
# %bb.66:
movzbl 67(%r13), %eax
jmp .LBB1_69
.LBB1_67:
.Ltmp80:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp81:
# %bb.68: # %.noexc132
movq (%r13), %rax
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp83:
.LBB1_69: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i129
.Ltmp84:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp85:
# %bb.70: # %.noexc134
.Ltmp86:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp87:
# %bb.71: # %_ZNSolsEPFRSoS_E.exit63
.Ltmp88:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp89:
# %bb.72: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit65
movl 400(%r15), %esi
.Ltmp90:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp91:
# %bb.73:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_82
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i138
cmpb $0, 56(%r13)
je .LBB1_76
# %bb.75:
movzbl 67(%r13), %eax
jmp .LBB1_78
.LBB1_76:
.Ltmp92:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp93:
# %bb.77: # %.noexc143
movq (%r13), %rax
.Ltmp94:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp95:
.LBB1_78: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i140
.Ltmp96:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp97:
# %bb.79: # %.noexc145
.Ltmp98:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp99:
# %bb.80: # %_ZNSolsEPFRSoS_E.exit67
.Ltmp100:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp101:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit69
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_82
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
cmpb $0, 56(%r12)
je .LBB1_86
# %bb.85:
movzbl 67(%r12), %eax
jmp .LBB1_88
.LBB1_86:
.Ltmp102:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp103:
# %bb.87: # %.noexc154
movq (%r12), %rax
.Ltmp104:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp105:
.LBB1_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i151
.Ltmp106:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp107:
# %bb.89: # %.noexc156
.Ltmp108:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp109:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit71
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_43:
.cfi_def_cfa_offset 192
.Ltmp62:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp63:
# %bb.44: # %.noexc110
movq (%r13), %rax
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp65:
# %bb.45:
movl $_ZSt4cout, %r12d
jmp .LBB1_57
.LBB1_82: # %.invoke
.Ltmp110:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp111:
# %bb.83: # %.cont
.LBB1_95:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_47:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_93
.LBB1_46:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_94
.LBB1_48:
.Ltmp17:
jmp .LBB1_92
.LBB1_91:
.Ltmp12:
jmp .LBB1_92
.LBB1_49:
.Ltmp112:
.LBB1_92: # %_ZNSt6vectorIiSaIiEED2Ev.exit77
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_93: # %_ZNSt6vectorIiSaIiEED2Ev.exit79
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_94: # %_ZNSt6vectorIiSaIiEED2Ev.exit81
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp11-.Ltmp6 # Call between .Ltmp6 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp111-.Ltmp18 # Call between .Ltmp18 and .Ltmp111
.uleb128 .Ltmp112-.Lfunc_begin0 # jumps to .Ltmp112
.byte 0 # On action: cleanup
.uleb128 .Ltmp111-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp111 # Call between .Ltmp111 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addVecPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addVecPiS_S_i,@object # @_Z6addVecPiS_S_i
.section .rodata,"a",@progbits
.globl _Z6addVecPiS_S_i
.p2align 3, 0x0
_Z6addVecPiS_S_i:
.quad _Z21__device_stub__addVecPiS_S_i
.size _Z6addVecPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Demo: CUDA add vector"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GridSize="
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "BlockSize="
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMemcpyDeviceToHost ok."
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " hipMemcpyDeviceToHost failed."
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "c[0]:"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "c[100]:"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA add vector successfully!"
.size .L.str.7, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addVecPiS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addVecPiS_S_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6addVecPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>
#include <curand.h>
#include <curand_kernel.h>
//to get data yahoo finance
//time period: Apr 01 2016 -> Apr 01 2019
//freq: Weekly
#define NUM_ELEMENTS 100 //why when I change this everything breaks & this should not change because constant memory
#define NUM_PORTFOLIOS atoi(argv[argc])
#define MAX_NUM_OF_STOCKS 85
#define DEBUG 0
float* readFile(char* filename){
float* ret = (float*) malloc(NUM_ELEMENTS*sizeof(float));
FILE* ptr = fopen(filename,"r");
if (ptr==NULL)
{
printf("Error reading file");
return 0;
}
char line[255];
char* token;
int lineCount = 0;
fgets(line, 255, ptr); //grab the first line and do nothing
while (fgets(line, 255, ptr) != 0 && lineCount < NUM_ELEMENTS){ //for each line
int dataCount = 0;
token = strtok(line, ",");
while (token != 0) { //for each word in line
if (dataCount == 5) {
ret[lineCount] = atof(token);
}
token = strtok(0, ",");
dataCount++;
}
lineCount++;
}
fclose(ptr);
return ret;
}
void writeFile(char* filename, float* returns, float* risk, int len){
FILE* ptr = fopen(filename, "w");
for (int a = 0; a < len; a++){
fprintf(ptr, "%f %f\n", risk[a], returns[a]);
}
fclose(ptr);
}
float getAverage(float* nums, int len){
float sum = 0;
for (int a = 0; a < len; a++){
sum += nums[a];
}
return sum/len;
}
float* getPercentReturns(float* nums, int len){
float* ret = (float*) malloc(sizeof(float)*(len-1));
for (int a = 0; a < len-1; a++){
ret[a] = (nums[a+1]-nums[a])/nums[a];
}
return ret;
}
//a few possible errors in here
//still need to plot
//why am I mallocing
void gold(int argc, char* argv[]){
argc--;
if (argc < 3) {
printf("%s\n", "Expected more arguments");
exit(0);
}
float** closingPrices = (float**) malloc(sizeof(float*)*(argc-1));
float** returns = (float**) malloc(sizeof(float*)*(argc-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
for (int a = 1; a < argc; a++){
closingPrices[a-1] = readFile(argv[a]);
returns[a-1] = getPercentReturns(closingPrices[a-1], NUM_ELEMENTS);
averages[a-1] = getAverage(returns[a-1], NUM_ELEMENTS-1);
}
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a][b]);
}
}
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
//calculate the covariances for each of the stocks
//doing extra things [0][4] will be the same as [4][0]
float** covariance = (float**) malloc(sizeof(float*)*(argc-1));
for (int a = 0; a < argc-1; a++){
covariance[a] = (float*) malloc(sizeof(float)*(argc-1));
for (int b = 0; b < argc-1; b++){
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++){
sum += (returns[a][c] - averages[a]) * (returns[b][c] - averages[b]);
}
sum /= NUM_ELEMENTS-2;
covariance[a][b] = sum;
}
}
//retiming -malloc, transfers -constant *
//transpose data array vs constant *
//cutting down on local variables in portfolios
//remove std all together *
//move all the constants to pt2
//dont double calculate for the covariance *
//where do you put the write file *
//time to choose the weights for the given portfolios
//PSUDEO:
//for doing random weights
//if x stocks
//then choose x numbers
//then find the sum of the randoms
//then divide each random number by sum
clock_t start = clock(), diff;
srand(time(NULL)); // Initialization, should only be called once.
float* risk = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
for (int a = 0; a < NUM_PORTFOLIOS; a++){//find the risk & reward for each portfolio
float randomWeights[argc-1]; //may actually want to save this for later
int totalWeight = 0;
for (int b = 0; b < argc-1; b++){//choose random weights
int r = rand() % 100; //RAND MIGHT BE DOING THE SAME VAL EVERYTIME
totalWeight += r;
randomWeights[b] = (float) r;
}
for (int b = 0; b < argc-1; b++){//now random weight has the correct weights
randomWeights[b] /= totalWeight;
}
//first find the reward
float totalReward = 0;
for (int b = 0; b < argc-1; b++){
totalReward += averages[b]*randomWeights[b];
}
reward[a] = totalReward;
//find the risk of the portfolio
float totalRisk = 0;
float work[argc-1];
for (int b = 0; b < argc-1; b++){
work[b] = 0;
for (int c = 0; c < argc-1; c++){
work[b] += randomWeights[c]*covariance[c][b];
}
}
for (int b = 0; b < argc-1; b++){
totalRisk += work[b] * randomWeights[b];
}
risk[a] = sqrt(totalRisk);
if (a==0 && DEBUG){
for (int r = 0; r < argc-1;r++) printf("randomWeights: %f\n", randomWeights[r]);
printf("Risk: %f\n", risk[a]);
for (int r = 0; r < argc-1; r++){
for (int rr = 0; rr < argc-1; rr++){
printf("Cov of %d %d : %f\n", r, rr, covariance[r][rr]);
}
}
}
}
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("CPU time portfolio %f seconds\n", msec/1000);
//plot the data
if (DEBUG) writeFile("riskreturngold.txt", reward, risk, NUM_PORTFOLIOS);
}
__constant__ float c_returns[MAX_NUM_OF_STOCKS * 99];
__constant__ float c_averages[MAX_NUM_OF_STOCKS];
__constant__ float c_covariance[MAX_NUM_OF_STOCKS*MAX_NUM_OF_STOCKS];
__global__ void GPercentReturns(float* closingPrices, float* returns, int numOfStocks)
{
__shared__ float closing[NUM_ELEMENTS];
int stockId = blockIdx.x;
int returnId = threadIdx.x;
int grab = returnId + (stockId * NUM_ELEMENTS); //also write 2
//everyone load into shared
closing[returnId] = closingPrices[grab];
__syncthreads();
if (returnId != NUM_ELEMENTS-1){//last thread should do this
int to = returnId + (stockId*(NUM_ELEMENTS-1));
returns[to] = (closing[returnId+1]-closing[returnId])/closing[returnId];
}
}
__global__ void GReduceAverageR(float* average, int numOfStocks, int mid){
__shared__ float reduce[99];
int returnId = threadIdx.x;
int stockId = blockIdx.x;
int dim = blockDim.x;
reduce[returnId] = c_returns[returnId + (stockId*dim)];
__syncthreads();
if (returnId>=mid){
reduce[returnId-mid]+=reduce[returnId];
}
__syncthreads();
for (int s = mid/2; s > 0; s/=2){
if (returnId < s) {
reduce[returnId] += reduce[returnId+s];
}
__syncthreads();
}
//REMOVED IF
if (returnId == 0) average[stockId] = reduce[0]/99.0;
}
//try flipping the memory
__global__ void GCovariance(float* covariance, int numberOfStocks){
int b = threadIdx.x;
int a = blockIdx.x;
if (a > b) return;
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++)
sum += (c_returns[a*(NUM_ELEMENTS-1)+c] - c_averages[a]) * (c_returns[b*(NUM_ELEMENTS-1)+c] - c_averages[b]);
sum /= NUM_ELEMENTS-2;
covariance[a*numberOfStocks+b] = sum;
covariance[b*numberOfStocks+a] = sum;
}
__global__ void GPortfolio(float* risk, float* reward, int numberOfStocks, int mid){
//obscene amount of global calls here
//only one call to risk[] and reward[] at the end
//also there might be a GPU version of sqrt()
extern __shared__ float sharedMemory[];
float* randomWeights = (float*) &sharedMemory[0];
float* scratch = (float*) &sharedMemory[numberOfStocks];
//__shared__ float randomWeights[16];
//__shared__ float scratch[16];
int tid = threadIdx.x;
int bid = blockIdx.x;
curandState state;
curand_init(tid+bid*blockDim.x,10,0,&state);
float r = curand_uniform(&state);
//RAN WEIGHT
//FAST- WORKS
randomWeights[tid] = r;
__syncthreads();
//quick reduce
if (tid >= mid){
randomWeights[tid-mid] += randomWeights[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
randomWeights[tid] += randomWeights[tid+s];
__syncthreads();
}
float totalWeight = randomWeights[0];
__syncthreads();
randomWeights[tid] = (float) r/ totalWeight;
//RETURN
//FAST
scratch[tid] = c_averages[tid]*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
if (tid >= numberOfStocks) printf("%d\n", tid);
if (tid-mid < 0) printf("%d", tid-mid);
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s) {
scratch[tid] += scratch[tid+s];
}
__syncthreads();
}
if (tid == 0) reward[bid] = scratch[0];
__syncthreads();
//RISK
//FAST
float work = 0;
for (int c = 0; c < numberOfStocks; c++){
work += randomWeights[c]*c_covariance[c*numberOfStocks+tid];
}
scratch[tid] = work*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
scratch[tid] += scratch[tid+s];
__syncthreads();
}
if (tid == 0) risk[bid] = sqrt(scratch[0]);
}
void gpu (int argc, char* argv[]) {
argc--;
float* closingPrices = (float*) malloc(sizeof(float)*(argc-1)*NUM_ELEMENTS);
float* returns = (float*) malloc(sizeof(float)*(argc-1)*(NUM_ELEMENTS-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
float* std = (float*) malloc(sizeof(float)*(argc-1));
float* covariance = (float*) malloc(sizeof(float)*(argc-1)*(argc-1));
for (int a = 1; a < argc; a++){
float* add = readFile(argv[a]);
for (int b = 0; b < NUM_ELEMENTS; b++){
closingPrices[(a-1)*NUM_ELEMENTS+b] = add[b];
}
}
float* d_closingPrices;
cudaMalloc(&d_closingPrices, sizeof(float) * (argc-1)*NUM_ELEMENTS);
float* d_all;
cudaMalloc(&d_all, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
cudaMemcpy(d_closingPrices, closingPrices, sizeof(float)*(argc-1)*NUM_ELEMENTS, cudaMemcpyHostToDevice);
GPercentReturns<<<argc-1,NUM_ELEMENTS>>>(d_closingPrices, d_all, argc-1);
cudaMemcpy(returns, d_all, sizeof(float)*(argc-1)*(NUM_ELEMENTS-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_returns, returns, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a*(NUM_ELEMENTS-1)+b]);
}
}
}
int mid = 1;
while (mid * 2 <= NUM_ELEMENTS-1) {
mid *= 2;
}
GReduceAverageR<<<argc-1, NUM_ELEMENTS-1>>>(d_all, argc-1, mid);
cudaMemcpy(averages, d_all, sizeof(float)*(argc-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_averages, averages, sizeof(float) * (argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
GCovariance<<<argc-1,argc-1>>>(d_all, argc-1);
cudaMemcpy(covariance, d_all, sizeof(float)*(argc-1)*(argc-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_covariance, covariance, sizeof(float) * (argc-1)*(argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
for (int b = 0; b <argc-1; b++){
printf("Cov %d %d: %f\n", a, b, covariance[a*(argc-1)+b]);
}
}
}
//timing just for portfolio
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//END
float* risk = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* d_risk;
float* d_reward;
cudaMalloc(&d_risk, sizeof(float)*NUM_PORTFOLIOS);
cudaMalloc(&d_reward, sizeof(float)*NUM_PORTFOLIOS);
mid = 1;
while (mid * 2 <= argc-1){
mid *= 2;
}
GPortfolio<<<NUM_PORTFOLIOS, argc-1, (sizeof(float)*(argc-1))*2>>>(d_risk, d_reward, argc-1, mid);
cudaMemcpy(risk, d_risk, sizeof(float)*NUM_PORTFOLIOS, cudaMemcpyDeviceToHost);
cudaMemcpy(reward, d_reward, sizeof(float)*NUM_PORTFOLIOS, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
//START
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaError_t code = cudaEventElapsedTime(&time, start, stop);
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s\n", cudaGetErrorName(code));
}
//END
printf("Time for portfolio: %f s\n", time/1000);
if (DEBUG) writeFile("riskreturn.txt", reward, risk, NUM_PORTFOLIOS);
}
//to plot
//in terminal do
//gnuplot
//plot 'riskreturn.txt' with points pt 3
int main( int argc, char* argv[])
{
printf("Num stocks: %i \n", argc-2);
printf("Num port: %i \n", atoi(argv[argc-1]));
clock_t start = clock(), diff;
gold(argc, argv);
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("Total CPU time taken %f seconds\n", msec/1000);
clock_t start2 = clock(), diff2;
gpu(argc, argv);
diff2 = clock() - start2;
float msec2 = (float) diff2 * 1000 / (float) CLOCKS_PER_SEC;
printf("Total GPU time taken %f seconds \n", msec2/1000);
return 0;
} | .file "tmpxft_000a99e0_00000000-6_portfolio.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2280:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2280:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "Error reading file"
.LC2:
.string ","
.text
.globl _Z8readFilePc
.type _Z8readFilePc, @function
_Z8readFilePc:
.LFB2271:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $272, %rsp
.cfi_def_cfa_offset 320
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r13
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r14
testq %rax, %rax
je .L16
movq %rsp, %rdi
movq %rax, %rcx
movl $255, %edx
movl $255, %esi
call __fgets_chk@PLT
movl $0, %r12d
leaq .LC2(%rip), %rbp
jmp .L6
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %r13
jmp .L3
.L17:
movl $0, %esi
movq %rax, %rdi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%r12,4)
.L10:
movq %rbp, %rsi
movl $0, %edi
call strtok@PLT
addl $1, %ebx
testq %rax, %rax
je .L11
cmpl $5, %ebx
jne .L10
jmp .L17
.L11:
addq $1, %r12
.L6:
movq %rsp, %rdi
movq %r14, %rcx
movl $255, %edx
movl $255, %esi
call __fgets_chk@PLT
cmpl $99, %r12d
jg .L9
testq %rax, %rax
je .L9
movq %rsp, %rdi
movq %rbp, %rsi
call strtok@PLT
movl $0, %ebx
testq %rax, %rax
jne .L10
jmp .L11
.L9:
movq %r14, %rdi
call fclose@PLT
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L18
movq %r13, %rax
addq $272, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z8readFilePc, .-_Z8readFilePc
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "%f %f\n"
.text
.globl _Z9writeFilePcPfS0_i
.type _Z9writeFilePcPfS0_i, @function
_Z9writeFilePcPfS0_i:
.LFB2272:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r14
movq %rdx, %rbp
movl %ecx, %r13d
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L20
movq %r14, %rbx
movslq %r13d, %r13
leaq (%r14,%r13,4), %r14
leaq .LC4(%rip), %r13
.L21:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%rbx), %xmm1
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq $4, %rbx
addq $4, %rbp
cmpq %r14, %rbx
jne .L21
.L20:
movq %r12, %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size _Z9writeFilePcPfS0_i, .-_Z9writeFilePcPfS0_i
.globl _Z10getAveragePfi
.type _Z10getAveragePfi, @function
_Z10getAveragePfi:
.LFB2273:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L27
movq %rdi, %rax
movslq %esi, %rdx
leaq (%rdi,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L26:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L26
.L25:
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.L27:
pxor %xmm0, %xmm0
jmp .L25
.cfi_endproc
.LFE2273:
.size _Z10getAveragePfi, .-_Z10getAveragePfi
.globl _Z17getPercentReturnsPfi
.type _Z17getPercentReturnsPfi, @function
_Z17getPercentReturnsPfi:
.LFB2274:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
leal -1(%rsi), %r12d
movslq %r12d, %rdi
salq $2, %rdi
call malloc@PLT
testl %r12d, %r12d
jle .L29
leal -1(%rbp), %ecx
movl $0, %edx
.L31:
movss (%rbx,%rdx,4), %xmm1
movss 4(%rbx,%rdx,4), %xmm0
subss %xmm1, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $1, %rdx
cmpq %rcx, %rdx
jne .L31
.L29:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _Z17getPercentReturnsPfi, .-_Z17getPercentReturnsPfi
.section .rodata.str1.1
.LC6:
.string "Expected more arguments"
.LC7:
.string "%s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "CPU time portfolio %f seconds\n"
.text
.globl _Z4goldiPPc
.type _Z4goldiPPc, @function
_Z4goldiPPc:
.LFB2275:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, -88(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jg .L35
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movl %edi, %r15d
leal -2(%rdi), %r14d
movslq %r14d, %r12
leaq 0(,%r12,8), %rbx
movq %rbx, -72(%rbp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, -96(%rbp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 0(,%r12,4), %rax
movq %rax, -80(%rbp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
leal -3(%r15), %r15d
movl $0, %r12d
.L36:
movq -88(%rbp), %rax
movq 8(%rax,%r12,8), %rdi
call _Z8readFilePc
movq %rax, %rdi
movq -96(%rbp), %rax
movq %rdi, (%rax,%r12,8)
movl $100, %esi
call _Z17getPercentReturnsPfi
movq %rax, %rdi
movq %rax, (%rbx,%r12,8)
movl $99, %esi
call _Z10getAveragePfi
movss %xmm0, 0(%r13,%r12,4)
movq %r12, %rax
addq $1, %r12
cmpq %r15, %rax
jne .L36
movq -72(%rbp), %rdi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movl %r14d, -96(%rbp)
movq %rax, %r14
jmp .L40
.L39:
leaq 1(%r14), %rax
cmpq %r15, %r14
je .L71
movq %rax, %r14
.L40:
movq -80(%rbp), %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, (%r12,%r14,8)
movq (%rbx,%r14,8), %rcx
movss 0(%r13,%r14,4), %xmm4
movl $0, %esi
.L37:
movq (%rbx,%rsi,8), %rdx
movss 0(%r13,%rsi,4), %xmm3
movl $0, %eax
pxor %xmm2, %xmm2
.L38:
movss (%rcx,%rax), %xmm0
subss %xmm4, %xmm0
movss (%rdx,%rax), %xmm1
subss %xmm3, %xmm1
mulss %xmm1, %xmm0
addss %xmm0, %xmm2
addq $4, %rax
cmpq $396, %rax
jne .L38
divss .LC8(%rip), %xmm2
movss %xmm2, (%rdi,%rsi,4)
leaq 1(%rsi), %rax
cmpq %r15, %rsi
je .L39
movq %rax, %rsi
jmp .L37
.L71:
movl -96(%rbp), %r14d
call clock@PLT
movq %rax, %rbx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq -88(%rbp), %rax
movq -72(%rbp), %rdi
leaq 8(%rax,%rdi), %rax
movq %rax, -88(%rbp)
movq (%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, -96(%rbp)
movq -88(%rbp), %rax
movq (%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, -104(%rbp)
movq $0, -72(%rbp)
movq -80(%rbp), %rax
addq $15, %rax
movq %rax, -80(%rbp)
leaq 4(,%r15,4), %rax
movq %rax, -120(%rbp)
movq %rbx, -128(%rbp)
movq %r15, -136(%rbp)
jmp .L41
.L43:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L44
orq $0, -8(%rsp,%rdx)
.L44:
movq %rsp, %rcx
movq -120(%rbp), %rax
leaq (%rcx,%rax), %rdi
movq %rcx, %rbx
movl $0, %r15d
movl %r14d, -140(%rbp)
movq %rcx, -152(%rbp)
movq %rdi, %r14
movq %rcx, -160(%rbp)
.L45:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
addl %eax, %r15d
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbx, %r14
jne .L45
movq -152(%rbp), %rsi
movq %r14, %rdi
movl -140(%rbp), %r14d
movq -160(%rbp), %rcx
pxor %xmm1, %xmm1
cvtsi2ssl %r15d, %xmm1
.L46:
movss (%rsi), %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rsi)
addq $4, %rsi
cmpq %rdi, %rsi
jne .L46
movl $0, %eax
pxor %xmm1, %xmm1
movq -136(%rbp), %rsi
.L47:
movss 0(%r13,%rax,4), %xmm0
mulss (%rcx,%rax,4), %xmm0
addss %xmm0, %xmm1
movq %rax, %rdx
addq $1, %rax
cmpq %rsi, %rdx
jne .L47
movq -104(%rbp), %rax
movq -72(%rbp), %rbx
movss %xmm1, (%rax,%rbx,4)
movq -80(%rbp), %rax
movl $16, %ebx
movl $0, %edx
divq %rbx
salq $4, %rax
movq %rax, %rsi
andq $-4096, %rsi
movq %rsp, %rdx
subq %rsi, %rdx
.L48:
cmpq %rdx, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L50
orq $0, -8(%rsp,%rdx)
.L50:
movq %rsp, %r8
movl $0, %edi
.L52:
leaq 0(,%rdi,4), %rsi
movl $0, %eax
pxor %xmm1, %xmm1
.L51:
movq (%r12,%rax,8), %rdx
movss (%rdx,%rsi), %xmm0
mulss (%rcx,%rax,4), %xmm0
addss %xmm0, %xmm1
addq $1, %rax
cmpl %eax, %r14d
jg .L51
movss %xmm1, (%r8,%rdi,4)
addq $1, %rdi
cmpl %edi, %r14d
jg .L52
movl $0, %eax
pxor %xmm1, %xmm1
.L53:
movss (%r8,%rax,4), %xmm0
mulss (%rcx,%rax,4), %xmm0
addss %xmm0, %xmm1
addq $1, %rax
cmpl %eax, %r14d
jg .L53
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L69
sqrtss %xmm1, %xmm1
movaps %xmm1, %xmm0
.L56:
movq -96(%rbp), %rbx
movq -72(%rbp), %rax
movss %xmm0, (%rbx,%rax,4)
movq -112(%rbp), %rsp
addq $1, %rax
movq %rax, -72(%rbp)
.L41:
movq -88(%rbp), %rax
movq (%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl -72(%rbp), %ebx
cmpl %ebx, %eax
jle .L72
movq %rsp, -112(%rbp)
movq -80(%rbp), %rax
movl $16, %ebx
movl $0, %edx
divq %rbx
salq $4, %rax
movq %rax, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L42:
cmpq %rdx, %rsp
je .L43
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L42
.L69:
movaps %xmm1, %xmm0
call sqrtf@PLT
jmp .L56
.L72:
movq -128(%rbp), %rbx
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss .LC9(%rip), %xmm1
mulss %xmm1, %xmm0
divss .LC10(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L73
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L73:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2275:
.size _Z4goldiPPc, .-_Z4goldiPPc
.globl _Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i
.type _Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i, @function
_Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i:
.LFB2302:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L78
.L74:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L79
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15GPercentReturnsPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L74
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2302:
.size _Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i, .-_Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i
.globl _Z15GPercentReturnsPfS_i
.type _Z15GPercentReturnsPfS_i, @function
_Z15GPercentReturnsPfS_i:
.LFB2303:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2303:
.size _Z15GPercentReturnsPfS_i, .-_Z15GPercentReturnsPfS_i
.globl _Z37__device_stub__Z15GReduceAverageRPfiiPfii
.type _Z37__device_stub__Z15GReduceAverageRPfiiPfii, @function
_Z37__device_stub__Z15GReduceAverageRPfiiPfii:
.LFB2304:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15GReduceAverageRPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2304:
.size _Z37__device_stub__Z15GReduceAverageRPfiiPfii, .-_Z37__device_stub__Z15GReduceAverageRPfiiPfii
.globl _Z15GReduceAverageRPfii
.type _Z15GReduceAverageRPfii, @function
_Z15GReduceAverageRPfii:
.LFB2305:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15GReduceAverageRPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2305:
.size _Z15GReduceAverageRPfii, .-_Z15GReduceAverageRPfii
.globl _Z32__device_stub__Z11GCovariancePfiPfi
.type _Z32__device_stub__Z11GCovariancePfiPfi, @function
_Z32__device_stub__Z11GCovariancePfiPfi:
.LFB2306:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11GCovariancePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2306:
.size _Z32__device_stub__Z11GCovariancePfiPfi, .-_Z32__device_stub__Z11GCovariancePfiPfi
.globl _Z11GCovariancePfi
.type _Z11GCovariancePfi, @function
_Z11GCovariancePfi:
.LFB2307:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11GCovariancePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2307:
.size _Z11GCovariancePfi, .-_Z11GCovariancePfi
.globl _Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii
.type _Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii, @function
_Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii:
.LFB2308:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10GPortfolioPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2308:
.size _Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii, .-_Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii
.globl _Z10GPortfolioPfS_ii
.type _Z10GPortfolioPfS_ii, @function
_Z10GPortfolioPfS_ii:
.LFB2309:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2309:
.size _Z10GPortfolioPfS_ii, .-_Z10GPortfolioPfS_ii
.section .rodata.str1.1
.LC12:
.string "GPUassert: %s\n"
.LC13:
.string "Time for portfolio: %f s\n"
.text
.globl _Z3gpuiPPc
.type _Z3gpuiPPc, @function
_Z3gpuiPPc:
.LFB2276:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %r13d
movq %rsi, %r12
movq %rsi, 48(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leal -1(%rdi), %ebx
leal -2(%rdi), %r14d
movslq %r14d, %rbp
leaq 0(,%rbp,4), %r15
leaq (%r15,%rbp), %rax
leaq (%rax,%rax,4), %rax
salq $4, %rax
movq %rax, 56(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
imulq $396, %rbp, %rcx
movq %rcx, (%rsp)
movq %rcx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
imulq %rbp, %rbp
leaq 0(,%rbp,4), %rcx
movq %rcx, 16(%rsp)
movq %rcx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
cmpl $1, %ebx
jle .L107
movq %r12, %rcx
leaq 8(%r12), %r12
movq 8(%rsp), %rax
leaq 400(%rax), %rbp
leal -3(%r13), %eax
leaq 16(%rcx,%rax,8), %r13
.L109:
movq (%r12), %rdi
call _Z8readFilePc
movl $0, %edx
.L108:
movss (%rax,%rdx), %xmm0
movss %xmm0, -400(%rbp,%rdx)
addq $4, %rdx
cmpq $400, %rdx
jne .L108
addq $8, %r12
addq $400, %rbp
cmpq %r13, %r12
jne .L109
.L107:
leaq 64(%rsp), %rdi
movq 56(%rsp), %rbp
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq (%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %r14d, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L121
.L110:
movl $2, %ecx
movq (%rsp), %r13
movq %r13, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %r13, %rdx
movq %rbp, %rsi
leaq _ZL9c_returns(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $99, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %r14d, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L111:
movl $2, %ecx
movq %r15, %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %r15, %rdx
movq %rbp, %rsi
leaq _ZL10c_averages(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %r14d, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %r14d, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L123
.L112:
movl $2, %ecx
movq 16(%rsp), %rbp
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %rbp, %rdx
movq %r15, %rsi
leaq _ZL12c_covariance(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movslq %ebx, %r13
salq $3, %r13
movq 48(%rsp), %rbp
addq %r13, %rbp
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rsi
salq $2, %rsi
leaq 104(%rsp), %rdi
call cudaMalloc@PLT
movl $1, %eax
.L113:
movl %eax, %r12d
addl %eax, %eax
cmpl %eax, %ebx
jg .L113
movl %r14d, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl 132(%rsp), %ecx
movl $0, %r9d
leaq -8(%r13), %r8
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L124
.L114:
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 96(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq 0(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 124(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
testl %eax, %eax
jne .L125
.L115:
movss 124(%rsp), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L126
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L121:
.cfi_restore_state
movl %r14d, %edx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z38__device_stub__Z15GPercentReturnsPfS_iPfS_i
jmp .L110
.L122:
movl $64, %edx
movl %r14d, %esi
movq 72(%rsp), %rdi
call _Z37__device_stub__Z15GReduceAverageRPfiiPfii
jmp .L111
.L123:
movl %r14d, %esi
movq 72(%rsp), %rdi
call _Z32__device_stub__Z11GCovariancePfiPfi
jmp .L112
.L124:
movl %r12d, %ecx
movl %r14d, %edx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z34__device_stub__Z10GPortfolioPfS_iiPfS_ii
jmp .L114
.L125:
call cudaGetErrorName@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L115
.L126:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2276:
.size _Z3gpuiPPc, .-_Z3gpuiPPc
.section .rodata.str1.1
.LC14:
.string "Num stocks: %i \n"
.LC15:
.string "Num port: %i \n"
.section .rodata.str1.8
.align 8
.LC16:
.string "Total CPU time taken %f seconds\n"
.align 8
.LC17:
.string "Total GPU time taken %f seconds \n"
.text
.globl main
.type main, @function
main:
.LFB2277:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebx
movq %rsi, %rbp
leal -2(%rdi), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
movq -8(%rbp,%rax,8), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r12
movq %rbp, %rsi
movl %ebx, %edi
call _Z4goldiPPc
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC9(%rip), %xmm0
divss .LC10(%rip), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r12
movq %rbp, %rsi
movl %ebx, %edi
call _Z3gpuiPPc
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
mulss .LC9(%rip), %xmm0
divss .LC10(%rip), %xmm0
divss .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2277:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z10GPortfolioPfS_ii"
.LC19:
.string "_Z11GCovariancePfi"
.LC20:
.string "_Z15GReduceAverageRPfii"
.LC21:
.string "_Z15GPercentReturnsPfS_i"
.LC22:
.string "precalc_xorwow_matrix"
.LC23:
.string "precalc_xorwow_offset_matrix"
.LC24:
.string "mrg32k3aM1"
.LC25:
.string "mrg32k3aM2"
.LC26:
.string "mrg32k3aM1SubSeq"
.LC27:
.string "mrg32k3aM2SubSeq"
.LC28:
.string "mrg32k3aM1Seq"
.LC29:
.string "mrg32k3aM2Seq"
.LC30:
.string "__cr_lgamma_table"
.LC31:
.string "c_returns"
.LC32:
.string "c_averages"
.LC33:
.string "c_covariance"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2311:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10GPortfolioPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z11GCovariancePfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z15GReduceAverageRPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z15GPercentReturnsPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $33660, %r9d
movl $0, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9c_returns(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $340, %r9d
movl $0, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10c_averages(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $28900, %r9d
movl $0, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12c_covariance(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2311:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL12c_covariance
.comm _ZL12c_covariance,28900,32
.local _ZL10c_averages
.comm _ZL10c_averages,340,32
.local _ZL9c_returns
.comm _ZL9c_returns,33660,32
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1120141312
.align 4
.LC9:
.long 1148846080
.align 4
.LC10:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>
#include <curand.h>
#include <curand_kernel.h>
//to get data yahoo finance
//time period: Apr 01 2016 -> Apr 01 2019
//freq: Weekly
#define NUM_ELEMENTS 100 //why when I change this everything breaks & this should not change because constant memory
#define NUM_PORTFOLIOS atoi(argv[argc])
#define MAX_NUM_OF_STOCKS 85
#define DEBUG 0
float* readFile(char* filename){
float* ret = (float*) malloc(NUM_ELEMENTS*sizeof(float));
FILE* ptr = fopen(filename,"r");
if (ptr==NULL)
{
printf("Error reading file");
return 0;
}
char line[255];
char* token;
int lineCount = 0;
fgets(line, 255, ptr); //grab the first line and do nothing
while (fgets(line, 255, ptr) != 0 && lineCount < NUM_ELEMENTS){ //for each line
int dataCount = 0;
token = strtok(line, ",");
while (token != 0) { //for each word in line
if (dataCount == 5) {
ret[lineCount] = atof(token);
}
token = strtok(0, ",");
dataCount++;
}
lineCount++;
}
fclose(ptr);
return ret;
}
void writeFile(char* filename, float* returns, float* risk, int len){
FILE* ptr = fopen(filename, "w");
for (int a = 0; a < len; a++){
fprintf(ptr, "%f %f\n", risk[a], returns[a]);
}
fclose(ptr);
}
float getAverage(float* nums, int len){
float sum = 0;
for (int a = 0; a < len; a++){
sum += nums[a];
}
return sum/len;
}
float* getPercentReturns(float* nums, int len){
float* ret = (float*) malloc(sizeof(float)*(len-1));
for (int a = 0; a < len-1; a++){
ret[a] = (nums[a+1]-nums[a])/nums[a];
}
return ret;
}
//a few possible errors in here
//still need to plot
//why am I mallocing
void gold(int argc, char* argv[]){
argc--;
if (argc < 3) {
printf("%s\n", "Expected more arguments");
exit(0);
}
float** closingPrices = (float**) malloc(sizeof(float*)*(argc-1));
float** returns = (float**) malloc(sizeof(float*)*(argc-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
for (int a = 1; a < argc; a++){
closingPrices[a-1] = readFile(argv[a]);
returns[a-1] = getPercentReturns(closingPrices[a-1], NUM_ELEMENTS);
averages[a-1] = getAverage(returns[a-1], NUM_ELEMENTS-1);
}
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a][b]);
}
}
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
//calculate the covariances for each of the stocks
//doing extra things [0][4] will be the same as [4][0]
float** covariance = (float**) malloc(sizeof(float*)*(argc-1));
for (int a = 0; a < argc-1; a++){
covariance[a] = (float*) malloc(sizeof(float)*(argc-1));
for (int b = 0; b < argc-1; b++){
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++){
sum += (returns[a][c] - averages[a]) * (returns[b][c] - averages[b]);
}
sum /= NUM_ELEMENTS-2;
covariance[a][b] = sum;
}
}
//retiming -malloc, transfers -constant *
//transpose data array vs constant *
//cutting down on local variables in portfolios
//remove std all together *
//move all the constants to pt2
//dont double calculate for the covariance *
//where do you put the write file *
//time to choose the weights for the given portfolios
//PSUDEO:
//for doing random weights
//if x stocks
//then choose x numbers
//then find the sum of the randoms
//then divide each random number by sum
clock_t start = clock(), diff;
srand(time(NULL)); // Initialization, should only be called once.
float* risk = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
for (int a = 0; a < NUM_PORTFOLIOS; a++){//find the risk & reward for each portfolio
float randomWeights[argc-1]; //may actually want to save this for later
int totalWeight = 0;
for (int b = 0; b < argc-1; b++){//choose random weights
int r = rand() % 100; //RAND MIGHT BE DOING THE SAME VAL EVERYTIME
totalWeight += r;
randomWeights[b] = (float) r;
}
for (int b = 0; b < argc-1; b++){//now random weight has the correct weights
randomWeights[b] /= totalWeight;
}
//first find the reward
float totalReward = 0;
for (int b = 0; b < argc-1; b++){
totalReward += averages[b]*randomWeights[b];
}
reward[a] = totalReward;
//find the risk of the portfolio
float totalRisk = 0;
float work[argc-1];
for (int b = 0; b < argc-1; b++){
work[b] = 0;
for (int c = 0; c < argc-1; c++){
work[b] += randomWeights[c]*covariance[c][b];
}
}
for (int b = 0; b < argc-1; b++){
totalRisk += work[b] * randomWeights[b];
}
risk[a] = sqrt(totalRisk);
if (a==0 && DEBUG){
for (int r = 0; r < argc-1;r++) printf("randomWeights: %f\n", randomWeights[r]);
printf("Risk: %f\n", risk[a]);
for (int r = 0; r < argc-1; r++){
for (int rr = 0; rr < argc-1; rr++){
printf("Cov of %d %d : %f\n", r, rr, covariance[r][rr]);
}
}
}
}
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("CPU time portfolio %f seconds\n", msec/1000);
//plot the data
if (DEBUG) writeFile("riskreturngold.txt", reward, risk, NUM_PORTFOLIOS);
}
__constant__ float c_returns[MAX_NUM_OF_STOCKS * 99];
__constant__ float c_averages[MAX_NUM_OF_STOCKS];
__constant__ float c_covariance[MAX_NUM_OF_STOCKS*MAX_NUM_OF_STOCKS];
__global__ void GPercentReturns(float* closingPrices, float* returns, int numOfStocks)
{
__shared__ float closing[NUM_ELEMENTS];
int stockId = blockIdx.x;
int returnId = threadIdx.x;
int grab = returnId + (stockId * NUM_ELEMENTS); //also write 2
//everyone load into shared
closing[returnId] = closingPrices[grab];
__syncthreads();
if (returnId != NUM_ELEMENTS-1){//last thread should do this
int to = returnId + (stockId*(NUM_ELEMENTS-1));
returns[to] = (closing[returnId+1]-closing[returnId])/closing[returnId];
}
}
__global__ void GReduceAverageR(float* average, int numOfStocks, int mid){
__shared__ float reduce[99];
int returnId = threadIdx.x;
int stockId = blockIdx.x;
int dim = blockDim.x;
reduce[returnId] = c_returns[returnId + (stockId*dim)];
__syncthreads();
if (returnId>=mid){
reduce[returnId-mid]+=reduce[returnId];
}
__syncthreads();
for (int s = mid/2; s > 0; s/=2){
if (returnId < s) {
reduce[returnId] += reduce[returnId+s];
}
__syncthreads();
}
//REMOVED IF
if (returnId == 0) average[stockId] = reduce[0]/99.0;
}
//try flipping the memory
__global__ void GCovariance(float* covariance, int numberOfStocks){
int b = threadIdx.x;
int a = blockIdx.x;
if (a > b) return;
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++)
sum += (c_returns[a*(NUM_ELEMENTS-1)+c] - c_averages[a]) * (c_returns[b*(NUM_ELEMENTS-1)+c] - c_averages[b]);
sum /= NUM_ELEMENTS-2;
covariance[a*numberOfStocks+b] = sum;
covariance[b*numberOfStocks+a] = sum;
}
__global__ void GPortfolio(float* risk, float* reward, int numberOfStocks, int mid){
//obscene amount of global calls here
//only one call to risk[] and reward[] at the end
//also there might be a GPU version of sqrt()
extern __shared__ float sharedMemory[];
float* randomWeights = (float*) &sharedMemory[0];
float* scratch = (float*) &sharedMemory[numberOfStocks];
//__shared__ float randomWeights[16];
//__shared__ float scratch[16];
int tid = threadIdx.x;
int bid = blockIdx.x;
curandState state;
curand_init(tid+bid*blockDim.x,10,0,&state);
float r = curand_uniform(&state);
//RAN WEIGHT
//FAST- WORKS
randomWeights[tid] = r;
__syncthreads();
//quick reduce
if (tid >= mid){
randomWeights[tid-mid] += randomWeights[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
randomWeights[tid] += randomWeights[tid+s];
__syncthreads();
}
float totalWeight = randomWeights[0];
__syncthreads();
randomWeights[tid] = (float) r/ totalWeight;
//RETURN
//FAST
scratch[tid] = c_averages[tid]*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
if (tid >= numberOfStocks) printf("%d\n", tid);
if (tid-mid < 0) printf("%d", tid-mid);
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s) {
scratch[tid] += scratch[tid+s];
}
__syncthreads();
}
if (tid == 0) reward[bid] = scratch[0];
__syncthreads();
//RISK
//FAST
float work = 0;
for (int c = 0; c < numberOfStocks; c++){
work += randomWeights[c]*c_covariance[c*numberOfStocks+tid];
}
scratch[tid] = work*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
scratch[tid] += scratch[tid+s];
__syncthreads();
}
if (tid == 0) risk[bid] = sqrt(scratch[0]);
}
void gpu (int argc, char* argv[]) {
argc--;
float* closingPrices = (float*) malloc(sizeof(float)*(argc-1)*NUM_ELEMENTS);
float* returns = (float*) malloc(sizeof(float)*(argc-1)*(NUM_ELEMENTS-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
float* std = (float*) malloc(sizeof(float)*(argc-1));
float* covariance = (float*) malloc(sizeof(float)*(argc-1)*(argc-1));
for (int a = 1; a < argc; a++){
float* add = readFile(argv[a]);
for (int b = 0; b < NUM_ELEMENTS; b++){
closingPrices[(a-1)*NUM_ELEMENTS+b] = add[b];
}
}
float* d_closingPrices;
cudaMalloc(&d_closingPrices, sizeof(float) * (argc-1)*NUM_ELEMENTS);
float* d_all;
cudaMalloc(&d_all, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
cudaMemcpy(d_closingPrices, closingPrices, sizeof(float)*(argc-1)*NUM_ELEMENTS, cudaMemcpyHostToDevice);
GPercentReturns<<<argc-1,NUM_ELEMENTS>>>(d_closingPrices, d_all, argc-1);
cudaMemcpy(returns, d_all, sizeof(float)*(argc-1)*(NUM_ELEMENTS-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_returns, returns, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a*(NUM_ELEMENTS-1)+b]);
}
}
}
int mid = 1;
while (mid * 2 <= NUM_ELEMENTS-1) {
mid *= 2;
}
GReduceAverageR<<<argc-1, NUM_ELEMENTS-1>>>(d_all, argc-1, mid);
cudaMemcpy(averages, d_all, sizeof(float)*(argc-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_averages, averages, sizeof(float) * (argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
GCovariance<<<argc-1,argc-1>>>(d_all, argc-1);
cudaMemcpy(covariance, d_all, sizeof(float)*(argc-1)*(argc-1), cudaMemcpyDeviceToHost);
cudaMemcpyToSymbol(c_covariance, covariance, sizeof(float) * (argc-1)*(argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
for (int b = 0; b <argc-1; b++){
printf("Cov %d %d: %f\n", a, b, covariance[a*(argc-1)+b]);
}
}
}
//timing just for portfolio
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//END
float* risk = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* d_risk;
float* d_reward;
cudaMalloc(&d_risk, sizeof(float)*NUM_PORTFOLIOS);
cudaMalloc(&d_reward, sizeof(float)*NUM_PORTFOLIOS);
mid = 1;
while (mid * 2 <= argc-1){
mid *= 2;
}
GPortfolio<<<NUM_PORTFOLIOS, argc-1, (sizeof(float)*(argc-1))*2>>>(d_risk, d_reward, argc-1, mid);
cudaMemcpy(risk, d_risk, sizeof(float)*NUM_PORTFOLIOS, cudaMemcpyDeviceToHost);
cudaMemcpy(reward, d_reward, sizeof(float)*NUM_PORTFOLIOS, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
//START
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaError_t code = cudaEventElapsedTime(&time, start, stop);
if (code != cudaSuccess) {
fprintf(stderr,"GPUassert: %s\n", cudaGetErrorName(code));
}
//END
printf("Time for portfolio: %f s\n", time/1000);
if (DEBUG) writeFile("riskreturn.txt", reward, risk, NUM_PORTFOLIOS);
}
//to plot
//in terminal do
//gnuplot
//plot 'riskreturn.txt' with points pt 3
int main( int argc, char* argv[])
{
printf("Num stocks: %i \n", argc-2);
printf("Num port: %i \n", atoi(argv[argc-1]));
clock_t start = clock(), diff;
gold(argc, argv);
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("Total CPU time taken %f seconds\n", msec/1000);
clock_t start2 = clock(), diff2;
gpu(argc, argv);
diff2 = clock() - start2;
float msec2 = (float) diff2 * 1000 / (float) CLOCKS_PER_SEC;
printf("Total GPU time taken %f seconds \n", msec2/1000);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
//to get data yahoo finance
//time period: Apr 01 2016 -> Apr 01 2019
//freq: Weekly
#define NUM_ELEMENTS 100 //why when I change this everything breaks & this should not change because constant memory
#define NUM_PORTFOLIOS atoi(argv[argc])
#define MAX_NUM_OF_STOCKS 85
#define DEBUG 0
float* readFile(char* filename){
float* ret = (float*) malloc(NUM_ELEMENTS*sizeof(float));
FILE* ptr = fopen(filename,"r");
if (ptr==NULL)
{
printf("Error reading file");
return 0;
}
char line[255];
char* token;
int lineCount = 0;
fgets(line, 255, ptr); //grab the first line and do nothing
while (fgets(line, 255, ptr) != 0 && lineCount < NUM_ELEMENTS){ //for each line
int dataCount = 0;
token = strtok(line, ",");
while (token != 0) { //for each word in line
if (dataCount == 5) {
ret[lineCount] = atof(token);
}
token = strtok(0, ",");
dataCount++;
}
lineCount++;
}
fclose(ptr);
return ret;
}
void writeFile(char* filename, float* returns, float* risk, int len){
FILE* ptr = fopen(filename, "w");
for (int a = 0; a < len; a++){
fprintf(ptr, "%f %f\n", risk[a], returns[a]);
}
fclose(ptr);
}
float getAverage(float* nums, int len){
float sum = 0;
for (int a = 0; a < len; a++){
sum += nums[a];
}
return sum/len;
}
float* getPercentReturns(float* nums, int len){
float* ret = (float*) malloc(sizeof(float)*(len-1));
for (int a = 0; a < len-1; a++){
ret[a] = (nums[a+1]-nums[a])/nums[a];
}
return ret;
}
//a few possible errors in here
//still need to plot
//why am I mallocing
void gold(int argc, char* argv[]){
argc--;
if (argc < 3) {
printf("%s\n", "Expected more arguments");
exit(0);
}
float** closingPrices = (float**) malloc(sizeof(float*)*(argc-1));
float** returns = (float**) malloc(sizeof(float*)*(argc-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
for (int a = 1; a < argc; a++){
closingPrices[a-1] = readFile(argv[a]);
returns[a-1] = getPercentReturns(closingPrices[a-1], NUM_ELEMENTS);
averages[a-1] = getAverage(returns[a-1], NUM_ELEMENTS-1);
}
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a][b]);
}
}
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
//calculate the covariances for each of the stocks
//doing extra things [0][4] will be the same as [4][0]
float** covariance = (float**) malloc(sizeof(float*)*(argc-1));
for (int a = 0; a < argc-1; a++){
covariance[a] = (float*) malloc(sizeof(float)*(argc-1));
for (int b = 0; b < argc-1; b++){
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++){
sum += (returns[a][c] - averages[a]) * (returns[b][c] - averages[b]);
}
sum /= NUM_ELEMENTS-2;
covariance[a][b] = sum;
}
}
//retiming -malloc, transfers -constant *
//transpose data array vs constant *
//cutting down on local variables in portfolios
//remove std all together *
//move all the constants to pt2
//dont double calculate for the covariance *
//where do you put the write file *
//time to choose the weights for the given portfolios
//PSUDEO:
//for doing random weights
//if x stocks
//then choose x numbers
//then find the sum of the randoms
//then divide each random number by sum
clock_t start = clock(), diff;
srand(time(NULL)); // Initialization, should only be called once.
float* risk = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
for (int a = 0; a < NUM_PORTFOLIOS; a++){//find the risk & reward for each portfolio
float randomWeights[argc-1]; //may actually want to save this for later
int totalWeight = 0;
for (int b = 0; b < argc-1; b++){//choose random weights
int r = rand() % 100; //RAND MIGHT BE DOING THE SAME VAL EVERYTIME
totalWeight += r;
randomWeights[b] = (float) r;
}
for (int b = 0; b < argc-1; b++){//now random weight has the correct weights
randomWeights[b] /= totalWeight;
}
//first find the reward
float totalReward = 0;
for (int b = 0; b < argc-1; b++){
totalReward += averages[b]*randomWeights[b];
}
reward[a] = totalReward;
//find the risk of the portfolio
float totalRisk = 0;
float work[argc-1];
for (int b = 0; b < argc-1; b++){
work[b] = 0;
for (int c = 0; c < argc-1; c++){
work[b] += randomWeights[c]*covariance[c][b];
}
}
for (int b = 0; b < argc-1; b++){
totalRisk += work[b] * randomWeights[b];
}
risk[a] = sqrt(totalRisk);
if (a==0 && DEBUG){
for (int r = 0; r < argc-1;r++) printf("randomWeights: %f\n", randomWeights[r]);
printf("Risk: %f\n", risk[a]);
for (int r = 0; r < argc-1; r++){
for (int rr = 0; rr < argc-1; rr++){
printf("Cov of %d %d : %f\n", r, rr, covariance[r][rr]);
}
}
}
}
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("CPU time portfolio %f seconds\n", msec/1000);
//plot the data
if (DEBUG) writeFile("riskreturngold.txt", reward, risk, NUM_PORTFOLIOS);
}
__constant__ float c_returns[MAX_NUM_OF_STOCKS * 99];
__constant__ float c_averages[MAX_NUM_OF_STOCKS];
__constant__ float c_covariance[MAX_NUM_OF_STOCKS*MAX_NUM_OF_STOCKS];
__global__ void GPercentReturns(float* closingPrices, float* returns, int numOfStocks)
{
__shared__ float closing[NUM_ELEMENTS];
int stockId = blockIdx.x;
int returnId = threadIdx.x;
int grab = returnId + (stockId * NUM_ELEMENTS); //also write 2
//everyone load into shared
closing[returnId] = closingPrices[grab];
__syncthreads();
if (returnId != NUM_ELEMENTS-1){//last thread should do this
int to = returnId + (stockId*(NUM_ELEMENTS-1));
returns[to] = (closing[returnId+1]-closing[returnId])/closing[returnId];
}
}
__global__ void GReduceAverageR(float* average, int numOfStocks, int mid){
__shared__ float reduce[99];
int returnId = threadIdx.x;
int stockId = blockIdx.x;
int dim = blockDim.x;
reduce[returnId] = c_returns[returnId + (stockId*dim)];
__syncthreads();
if (returnId>=mid){
reduce[returnId-mid]+=reduce[returnId];
}
__syncthreads();
for (int s = mid/2; s > 0; s/=2){
if (returnId < s) {
reduce[returnId] += reduce[returnId+s];
}
__syncthreads();
}
//REMOVED IF
if (returnId == 0) average[stockId] = reduce[0]/99.0;
}
//try flipping the memory
__global__ void GCovariance(float* covariance, int numberOfStocks){
int b = threadIdx.x;
int a = blockIdx.x;
if (a > b) return;
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++)
sum += (c_returns[a*(NUM_ELEMENTS-1)+c] - c_averages[a]) * (c_returns[b*(NUM_ELEMENTS-1)+c] - c_averages[b]);
sum /= NUM_ELEMENTS-2;
covariance[a*numberOfStocks+b] = sum;
covariance[b*numberOfStocks+a] = sum;
}
__global__ void GPortfolio(float* risk, float* reward, int numberOfStocks, int mid){
//obscene amount of global calls here
//only one call to risk[] and reward[] at the end
//also there might be a GPU version of sqrt()
extern __shared__ float sharedMemory[];
float* randomWeights = (float*) &sharedMemory[0];
float* scratch = (float*) &sharedMemory[numberOfStocks];
//__shared__ float randomWeights[16];
//__shared__ float scratch[16];
int tid = threadIdx.x;
int bid = blockIdx.x;
hiprandState state;
hiprand_init(tid+bid*blockDim.x,10,0,&state);
float r = hiprand_uniform(&state);
//RAN WEIGHT
//FAST- WORKS
randomWeights[tid] = r;
__syncthreads();
//quick reduce
if (tid >= mid){
randomWeights[tid-mid] += randomWeights[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
randomWeights[tid] += randomWeights[tid+s];
__syncthreads();
}
float totalWeight = randomWeights[0];
__syncthreads();
randomWeights[tid] = (float) r/ totalWeight;
//RETURN
//FAST
scratch[tid] = c_averages[tid]*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
if (tid >= numberOfStocks) printf("%d\n", tid);
if (tid-mid < 0) printf("%d", tid-mid);
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s) {
scratch[tid] += scratch[tid+s];
}
__syncthreads();
}
if (tid == 0) reward[bid] = scratch[0];
__syncthreads();
//RISK
//FAST
float work = 0;
for (int c = 0; c < numberOfStocks; c++){
work += randomWeights[c]*c_covariance[c*numberOfStocks+tid];
}
scratch[tid] = work*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
scratch[tid] += scratch[tid+s];
__syncthreads();
}
if (tid == 0) risk[bid] = sqrt(scratch[0]);
}
void gpu (int argc, char* argv[]) {
argc--;
float* closingPrices = (float*) malloc(sizeof(float)*(argc-1)*NUM_ELEMENTS);
float* returns = (float*) malloc(sizeof(float)*(argc-1)*(NUM_ELEMENTS-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
float* std = (float*) malloc(sizeof(float)*(argc-1));
float* covariance = (float*) malloc(sizeof(float)*(argc-1)*(argc-1));
for (int a = 1; a < argc; a++){
float* add = readFile(argv[a]);
for (int b = 0; b < NUM_ELEMENTS; b++){
closingPrices[(a-1)*NUM_ELEMENTS+b] = add[b];
}
}
float* d_closingPrices;
hipMalloc(&d_closingPrices, sizeof(float) * (argc-1)*NUM_ELEMENTS);
float* d_all;
hipMalloc(&d_all, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
hipMemcpy(d_closingPrices, closingPrices, sizeof(float)*(argc-1)*NUM_ELEMENTS, hipMemcpyHostToDevice);
GPercentReturns<<<argc-1,NUM_ELEMENTS>>>(d_closingPrices, d_all, argc-1);
hipMemcpy(returns, d_all, sizeof(float)*(argc-1)*(NUM_ELEMENTS-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_returns), returns, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a*(NUM_ELEMENTS-1)+b]);
}
}
}
int mid = 1;
while (mid * 2 <= NUM_ELEMENTS-1) {
mid *= 2;
}
GReduceAverageR<<<argc-1, NUM_ELEMENTS-1>>>(d_all, argc-1, mid);
hipMemcpy(averages, d_all, sizeof(float)*(argc-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_averages), averages, sizeof(float) * (argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
GCovariance<<<argc-1,argc-1>>>(d_all, argc-1);
hipMemcpy(covariance, d_all, sizeof(float)*(argc-1)*(argc-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_covariance), covariance, sizeof(float) * (argc-1)*(argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
for (int b = 0; b <argc-1; b++){
printf("Cov %d %d: %f\n", a, b, covariance[a*(argc-1)+b]);
}
}
}
//timing just for portfolio
float time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//END
float* risk = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* d_risk;
float* d_reward;
hipMalloc(&d_risk, sizeof(float)*NUM_PORTFOLIOS);
hipMalloc(&d_reward, sizeof(float)*NUM_PORTFOLIOS);
mid = 1;
while (mid * 2 <= argc-1){
mid *= 2;
}
GPortfolio<<<NUM_PORTFOLIOS, argc-1, (sizeof(float)*(argc-1))*2>>>(d_risk, d_reward, argc-1, mid);
hipMemcpy(risk, d_risk, sizeof(float)*NUM_PORTFOLIOS, hipMemcpyDeviceToHost);
hipMemcpy(reward, d_reward, sizeof(float)*NUM_PORTFOLIOS, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
//START
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipError_t code = hipEventElapsedTime(&time, start, stop);
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s\n", hipGetErrorName(code));
}
//END
printf("Time for portfolio: %f s\n", time/1000);
if (DEBUG) writeFile("riskreturn.txt", reward, risk, NUM_PORTFOLIOS);
}
//to plot
//in terminal do
//gnuplot
//plot 'riskreturn.txt' with points pt 3
int main( int argc, char* argv[])
{
printf("Num stocks: %i \n", argc-2);
printf("Num port: %i \n", atoi(argv[argc-1]));
clock_t start = clock(), diff;
gold(argc, argv);
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("Total CPU time taken %f seconds\n", msec/1000);
clock_t start2 = clock(), diff2;
gpu(argc, argv);
diff2 = clock() - start2;
float msec2 = (float) diff2 * 1000 / (float) CLOCKS_PER_SEC;
printf("Total GPU time taken %f seconds \n", msec2/1000);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
#include <string.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
//to get data yahoo finance
//time period: Apr 01 2016 -> Apr 01 2019
//freq: Weekly
#define NUM_ELEMENTS 100 //why when I change this everything breaks & this should not change because constant memory
#define NUM_PORTFOLIOS atoi(argv[argc])
#define MAX_NUM_OF_STOCKS 85
#define DEBUG 0
float* readFile(char* filename){
float* ret = (float*) malloc(NUM_ELEMENTS*sizeof(float));
FILE* ptr = fopen(filename,"r");
if (ptr==NULL)
{
printf("Error reading file");
return 0;
}
char line[255];
char* token;
int lineCount = 0;
fgets(line, 255, ptr); //grab the first line and do nothing
while (fgets(line, 255, ptr) != 0 && lineCount < NUM_ELEMENTS){ //for each line
int dataCount = 0;
token = strtok(line, ",");
while (token != 0) { //for each word in line
if (dataCount == 5) {
ret[lineCount] = atof(token);
}
token = strtok(0, ",");
dataCount++;
}
lineCount++;
}
fclose(ptr);
return ret;
}
void writeFile(char* filename, float* returns, float* risk, int len){
FILE* ptr = fopen(filename, "w");
for (int a = 0; a < len; a++){
fprintf(ptr, "%f %f\n", risk[a], returns[a]);
}
fclose(ptr);
}
float getAverage(float* nums, int len){
float sum = 0;
for (int a = 0; a < len; a++){
sum += nums[a];
}
return sum/len;
}
float* getPercentReturns(float* nums, int len){
float* ret = (float*) malloc(sizeof(float)*(len-1));
for (int a = 0; a < len-1; a++){
ret[a] = (nums[a+1]-nums[a])/nums[a];
}
return ret;
}
//a few possible errors in here
//still need to plot
//why am I mallocing
void gold(int argc, char* argv[]){
argc--;
if (argc < 3) {
printf("%s\n", "Expected more arguments");
exit(0);
}
float** closingPrices = (float**) malloc(sizeof(float*)*(argc-1));
float** returns = (float**) malloc(sizeof(float*)*(argc-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
for (int a = 1; a < argc; a++){
closingPrices[a-1] = readFile(argv[a]);
returns[a-1] = getPercentReturns(closingPrices[a-1], NUM_ELEMENTS);
averages[a-1] = getAverage(returns[a-1], NUM_ELEMENTS-1);
}
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a][b]);
}
}
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
//calculate the covariances for each of the stocks
//doing extra things [0][4] will be the same as [4][0]
float** covariance = (float**) malloc(sizeof(float*)*(argc-1));
for (int a = 0; a < argc-1; a++){
covariance[a] = (float*) malloc(sizeof(float)*(argc-1));
for (int b = 0; b < argc-1; b++){
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++){
sum += (returns[a][c] - averages[a]) * (returns[b][c] - averages[b]);
}
sum /= NUM_ELEMENTS-2;
covariance[a][b] = sum;
}
}
//retiming -malloc, transfers -constant *
//transpose data array vs constant *
//cutting down on local variables in portfolios
//remove std all together *
//move all the constants to pt2
//dont double calculate for the covariance *
//where do you put the write file *
//time to choose the weights for the given portfolios
//PSUDEO:
//for doing random weights
//if x stocks
//then choose x numbers
//then find the sum of the randoms
//then divide each random number by sum
clock_t start = clock(), diff;
srand(time(NULL)); // Initialization, should only be called once.
float* risk = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)* NUM_PORTFOLIOS);
for (int a = 0; a < NUM_PORTFOLIOS; a++){//find the risk & reward for each portfolio
float randomWeights[argc-1]; //may actually want to save this for later
int totalWeight = 0;
for (int b = 0; b < argc-1; b++){//choose random weights
int r = rand() % 100; //RAND MIGHT BE DOING THE SAME VAL EVERYTIME
totalWeight += r;
randomWeights[b] = (float) r;
}
for (int b = 0; b < argc-1; b++){//now random weight has the correct weights
randomWeights[b] /= totalWeight;
}
//first find the reward
float totalReward = 0;
for (int b = 0; b < argc-1; b++){
totalReward += averages[b]*randomWeights[b];
}
reward[a] = totalReward;
//find the risk of the portfolio
float totalRisk = 0;
float work[argc-1];
for (int b = 0; b < argc-1; b++){
work[b] = 0;
for (int c = 0; c < argc-1; c++){
work[b] += randomWeights[c]*covariance[c][b];
}
}
for (int b = 0; b < argc-1; b++){
totalRisk += work[b] * randomWeights[b];
}
risk[a] = sqrt(totalRisk);
if (a==0 && DEBUG){
for (int r = 0; r < argc-1;r++) printf("randomWeights: %f\n", randomWeights[r]);
printf("Risk: %f\n", risk[a]);
for (int r = 0; r < argc-1; r++){
for (int rr = 0; rr < argc-1; rr++){
printf("Cov of %d %d : %f\n", r, rr, covariance[r][rr]);
}
}
}
}
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("CPU time portfolio %f seconds\n", msec/1000);
//plot the data
if (DEBUG) writeFile("riskreturngold.txt", reward, risk, NUM_PORTFOLIOS);
}
__constant__ float c_returns[MAX_NUM_OF_STOCKS * 99];
__constant__ float c_averages[MAX_NUM_OF_STOCKS];
__constant__ float c_covariance[MAX_NUM_OF_STOCKS*MAX_NUM_OF_STOCKS];
__global__ void GPercentReturns(float* closingPrices, float* returns, int numOfStocks)
{
__shared__ float closing[NUM_ELEMENTS];
int stockId = blockIdx.x;
int returnId = threadIdx.x;
int grab = returnId + (stockId * NUM_ELEMENTS); //also write 2
//everyone load into shared
closing[returnId] = closingPrices[grab];
__syncthreads();
if (returnId != NUM_ELEMENTS-1){//last thread should do this
int to = returnId + (stockId*(NUM_ELEMENTS-1));
returns[to] = (closing[returnId+1]-closing[returnId])/closing[returnId];
}
}
__global__ void GReduceAverageR(float* average, int numOfStocks, int mid){
__shared__ float reduce[99];
int returnId = threadIdx.x;
int stockId = blockIdx.x;
int dim = blockDim.x;
reduce[returnId] = c_returns[returnId + (stockId*dim)];
__syncthreads();
if (returnId>=mid){
reduce[returnId-mid]+=reduce[returnId];
}
__syncthreads();
for (int s = mid/2; s > 0; s/=2){
if (returnId < s) {
reduce[returnId] += reduce[returnId+s];
}
__syncthreads();
}
//REMOVED IF
if (returnId == 0) average[stockId] = reduce[0]/99.0;
}
//try flipping the memory
__global__ void GCovariance(float* covariance, int numberOfStocks){
int b = threadIdx.x;
int a = blockIdx.x;
if (a > b) return;
float sum = 0;
for (int c = 0; c < NUM_ELEMENTS-1; c++)
sum += (c_returns[a*(NUM_ELEMENTS-1)+c] - c_averages[a]) * (c_returns[b*(NUM_ELEMENTS-1)+c] - c_averages[b]);
sum /= NUM_ELEMENTS-2;
covariance[a*numberOfStocks+b] = sum;
covariance[b*numberOfStocks+a] = sum;
}
__global__ void GPortfolio(float* risk, float* reward, int numberOfStocks, int mid){
//obscene amount of global calls here
//only one call to risk[] and reward[] at the end
//also there might be a GPU version of sqrt()
extern __shared__ float sharedMemory[];
float* randomWeights = (float*) &sharedMemory[0];
float* scratch = (float*) &sharedMemory[numberOfStocks];
//__shared__ float randomWeights[16];
//__shared__ float scratch[16];
int tid = threadIdx.x;
int bid = blockIdx.x;
hiprandState state;
hiprand_init(tid+bid*blockDim.x,10,0,&state);
float r = hiprand_uniform(&state);
//RAN WEIGHT
//FAST- WORKS
randomWeights[tid] = r;
__syncthreads();
//quick reduce
if (tid >= mid){
randomWeights[tid-mid] += randomWeights[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
randomWeights[tid] += randomWeights[tid+s];
__syncthreads();
}
float totalWeight = randomWeights[0];
__syncthreads();
randomWeights[tid] = (float) r/ totalWeight;
//RETURN
//FAST
scratch[tid] = c_averages[tid]*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
if (tid >= numberOfStocks) printf("%d\n", tid);
if (tid-mid < 0) printf("%d", tid-mid);
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s) {
scratch[tid] += scratch[tid+s];
}
__syncthreads();
}
if (tid == 0) reward[bid] = scratch[0];
__syncthreads();
//RISK
//FAST
float work = 0;
for (int c = 0; c < numberOfStocks; c++){
work += randomWeights[c]*c_covariance[c*numberOfStocks+tid];
}
scratch[tid] = work*randomWeights[tid];
__syncthreads();
if (tid >= mid){
scratch[tid-mid] += scratch[tid];
}
__syncthreads();
for (int s = mid/2; s > 0; s /= 2){
if (tid < s)
scratch[tid] += scratch[tid+s];
__syncthreads();
}
if (tid == 0) risk[bid] = sqrt(scratch[0]);
}
void gpu (int argc, char* argv[]) {
argc--;
float* closingPrices = (float*) malloc(sizeof(float)*(argc-1)*NUM_ELEMENTS);
float* returns = (float*) malloc(sizeof(float)*(argc-1)*(NUM_ELEMENTS-1));
float* averages = (float*) malloc(sizeof(float)*(argc-1));
float* std = (float*) malloc(sizeof(float)*(argc-1));
float* covariance = (float*) malloc(sizeof(float)*(argc-1)*(argc-1));
for (int a = 1; a < argc; a++){
float* add = readFile(argv[a]);
for (int b = 0; b < NUM_ELEMENTS; b++){
closingPrices[(a-1)*NUM_ELEMENTS+b] = add[b];
}
}
float* d_closingPrices;
hipMalloc(&d_closingPrices, sizeof(float) * (argc-1)*NUM_ELEMENTS);
float* d_all;
hipMalloc(&d_all, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
hipMemcpy(d_closingPrices, closingPrices, sizeof(float)*(argc-1)*NUM_ELEMENTS, hipMemcpyHostToDevice);
GPercentReturns<<<argc-1,NUM_ELEMENTS>>>(d_closingPrices, d_all, argc-1);
hipMemcpy(returns, d_all, sizeof(float)*(argc-1)*(NUM_ELEMENTS-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_returns), returns, sizeof(float) * (argc-1)*(NUM_ELEMENTS-1));
if (DEBUG){
for (int a = 0; a < (argc-1); a++){
for (int b = 0; b < (NUM_ELEMENTS-1); b++){
printf("Returns %d %d: %f \n", a, b, returns[a*(NUM_ELEMENTS-1)+b]);
}
}
}
int mid = 1;
while (mid * 2 <= NUM_ELEMENTS-1) {
mid *= 2;
}
GReduceAverageR<<<argc-1, NUM_ELEMENTS-1>>>(d_all, argc-1, mid);
hipMemcpy(averages, d_all, sizeof(float)*(argc-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_averages), averages, sizeof(float) * (argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
printf("avg %d: %f\n", a, averages[a]);
}
}
GCovariance<<<argc-1,argc-1>>>(d_all, argc-1);
hipMemcpy(covariance, d_all, sizeof(float)*(argc-1)*(argc-1), hipMemcpyDeviceToHost);
hipMemcpyToSymbol(HIP_SYMBOL(c_covariance), covariance, sizeof(float) * (argc-1)*(argc-1));
if (DEBUG){
for (int a = 0; a < argc-1; a++){
for (int b = 0; b <argc-1; b++){
printf("Cov %d %d: %f\n", a, b, covariance[a*(argc-1)+b]);
}
}
}
//timing just for portfolio
float time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//END
float* risk = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* reward = (float*) malloc(sizeof(float)*NUM_PORTFOLIOS);
float* d_risk;
float* d_reward;
hipMalloc(&d_risk, sizeof(float)*NUM_PORTFOLIOS);
hipMalloc(&d_reward, sizeof(float)*NUM_PORTFOLIOS);
mid = 1;
while (mid * 2 <= argc-1){
mid *= 2;
}
GPortfolio<<<NUM_PORTFOLIOS, argc-1, (sizeof(float)*(argc-1))*2>>>(d_risk, d_reward, argc-1, mid);
hipMemcpy(risk, d_risk, sizeof(float)*NUM_PORTFOLIOS, hipMemcpyDeviceToHost);
hipMemcpy(reward, d_reward, sizeof(float)*NUM_PORTFOLIOS, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
//START
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipError_t code = hipEventElapsedTime(&time, start, stop);
if (code != hipSuccess) {
fprintf(stderr,"GPUassert: %s\n", hipGetErrorName(code));
}
//END
printf("Time for portfolio: %f s\n", time/1000);
if (DEBUG) writeFile("riskreturn.txt", reward, risk, NUM_PORTFOLIOS);
}
//to plot
//in terminal do
//gnuplot
//plot 'riskreturn.txt' with points pt 3
int main( int argc, char* argv[])
{
printf("Num stocks: %i \n", argc-2);
printf("Num port: %i \n", atoi(argv[argc-1]));
clock_t start = clock(), diff;
gold(argc, argv);
diff = clock() - start;
float msec = (float) diff * 1000 / (float) CLOCKS_PER_SEC;
printf("Total CPU time taken %f seconds\n", msec/1000);
clock_t start2 = clock(), diff2;
gpu(argc, argv);
diff2 = clock() - start2;
float msec2 = (float) diff2 * 1000 / (float) CLOCKS_PER_SEC;
printf("Total GPU time taken %f seconds \n", msec2/1000);
return 0;
} | .text
.file "portfolio.hip"
.globl _Z8readFilePc # -- Begin function _Z8readFilePc
.p2align 4, 0x90
.type _Z8readFilePc,@function
_Z8readFilePc: # @_Z8readFilePc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
testq %rax, %rax
je .LBB0_1
# %bb.2:
movq %rax, %r14
movq %rsp, %r15
movq %r15, %rdi
movl $255, %esi
movq %rax, %rdx
callq fgets
movq %r15, %rdi
movl $255, %esi
movq %r14, %rdx
callq fgets
testq %rax, %rax
je .LBB0_11
# %bb.3: # %.lr.ph23.preheader
xorl %r12d, %r12d
movq %rsp, %r15
.p2align 4, 0x90
.LBB0_4: # %.lr.ph23
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
movl $.L.str.2, %esi
movq %r15, %rdi
callq strtok
testq %rax, %rax
je .LBB0_9
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=1
movl $5, %ebp
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_6 Depth=2
movl $.L.str.2, %esi
xorl %edi, %edi
callq strtok
testq %rax, %rax
je .LBB0_9
.LBB0_6: # Parent Loop BB0_4 Depth=1
# => This Inner Loop Header: Depth=2
subl $1, %ebp
jae .LBB0_8
# %bb.7: # in Loop: Header=BB0_6 Depth=2
movq %rax, %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_9: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
movq %r15, %rdi
movl $255, %esi
movq %r14, %rdx
callq fgets
testq %rax, %rax
je .LBB0_11
# %bb.10: # %._crit_edge
# in Loop: Header=BB0_4 Depth=1
leaq 1(%r12), %rax
cmpq $99, %r12
movq %rax, %r12
jb .LBB0_4
.LBB0_11: # %._crit_edge24
movq %r14, %rdi
callq fclose
jmp .LBB0_12
.LBB0_1:
xorl %ebx, %ebx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
.LBB0_12:
movq %rbx, %rax
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8readFilePc, .Lfunc_end0-_Z8readFilePc
.cfi_endproc
# -- End function
.globl _Z9writeFilePcPfS0_i # -- Begin function _Z9writeFilePcPfS0_i
.p2align 4, 0x90
.type _Z9writeFilePcPfS0_i,@function
_Z9writeFilePcPfS0_i: # @_Z9writeFilePcPfS0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movq %r15, %rdi
movb $2, %al
callq fprintf
incq %r13
cmpq %r13, %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r15, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z9writeFilePcPfS0_i, .Lfunc_end1-_Z9writeFilePcPfS0_i
.cfi_endproc
# -- End function
.globl _Z10getAveragePfi # -- Begin function _Z10getAveragePfi
.p2align 4, 0x90
.type _Z10getAveragePfi,@function
_Z10getAveragePfi: # @_Z10getAveragePfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdi,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB2_4
jmp .LBB2_2
.LBB2_1:
xorps %xmm0, %xmm0
.LBB2_2: # %._crit_edge
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end2:
.size _Z10getAveragePfi, .Lfunc_end2-_Z10getAveragePfi
.cfi_endproc
# -- End function
.globl _Z17getPercentReturnsPfi # -- Begin function _Z17getPercentReturnsPfi
.p2align 4, 0x90
.type _Z17getPercentReturnsPfi,@function
_Z17getPercentReturnsPfi: # @_Z17getPercentReturnsPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %rax
leaq -4(,%rax,4), %rdi
callq malloc
cmpl $2, %ebp
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
decl %ebp
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rbx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rax,%rdx,4)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq %rsi, %rcx
jne .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17getPercentReturnsPfi, .Lfunc_end3-_Z17getPercentReturnsPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4goldiPPc
.LCPI4_0:
.long 0x42c60000 # float 99
.LCPI4_1:
.long 0x42c40000 # float 98
.LCPI4_2:
.long 0x447a0000 # float 1000
.LCPI4_3:
.long 0x49742400 # float 1.0E+6
.LCPI4_4:
.long 0x00000000 # float 0
.text
.globl _Z4goldiPPc
.p2align 4, 0x90
.type _Z4goldiPPc,@function
_Z4goldiPPc: # @_Z4goldiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $3, %edi
jle .LBB4_30
# %bb.1: # %.lr.ph.preheader
movq %rsi, %r13
movl %edi, %r14d
leal -1(%r14), %ebx
addl $-2, %r14d
leaq (,%r14,8), %rdi
movq %rdi, -56(%rbp) # 8-byte Spill
callq malloc
movq %rax, %r12
movq %r14, -48(%rbp) # 8-byte Spill
leaq (,%r14,4), %rdi
movq %rdi, -64(%rbp) # 8-byte Spill
callq malloc
movq %rax, %r15
movl %ebx, %eax
movq %rax, -72(%rbp) # 8-byte Spill
movl $1, %ebx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
# Child Loop BB4_5 Depth 2
movq (%r13,%rbx,8), %rdi
callq _Z8readFilePc
movq %rax, %r14
movl $396, %edi # imm = 0x18C
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rax,%rcx,4)
leaq 1(%rcx), %rdx
movq %rdx, %rcx
cmpq $99, %rdx
jne .LBB4_3
# %bb.4: # %_Z17getPercentReturnsPfi.exit
# in Loop: Header=BB4_2 Depth=1
movq %rax, -8(%r12,%rbx,8)
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_5: # %.lr.ph.i121
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rax,%rcx,4), %xmm0
incq %rcx
cmpq $99, %rcx
jne .LBB4_5
# %bb.6: # %_Z10getAveragePfi.exit
# in Loop: Header=BB4_2 Depth=1
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, -4(%r15,%rbx,4)
incq %rbx
cmpq -72(%rbp), %rbx # 8-byte Folded Reload
jne .LBB4_2
# %bb.7: # %._crit_edge
movq %r13, -80(%rbp) # 8-byte Spill
movq -56(%rbp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r14
movq -48(%rbp), %rax # 8-byte Reload
cmpl $2, %eax
movl $1, %ebx
cmovgel %eax, %ebx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_8: # %.preheader127.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
# Child Loop BB4_10 Depth 3
movq -64(%rbp), %rdi # 8-byte Reload
callq malloc
movss .LCPI4_1(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movq %rax, (%r14,%r13,8)
movq (%r12,%r13,8), %rcx
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_9: # %.preheader127
# Parent Loop BB4_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_10 Depth 3
movq (%r12,%rdx,8), %rsi
movss (%r15,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_8 Depth=1
# Parent Loop BB4_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rcx,%rdi,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss %xmm0, %xmm3
movss (%rsi,%rdi,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
subss %xmm2, %xmm4
mulss %xmm3, %xmm4
addss %xmm4, %xmm1
incq %rdi
cmpq $99, %rdi
jne .LBB4_10
# %bb.11: # in Loop: Header=BB4_9 Depth=2
divss %xmm5, %xmm1
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq %rbx, %rdx
jne .LBB4_9
# %bb.12: # %._crit_edge132
# in Loop: Header=BB4_8 Depth=1
incq %r13
cmpq %rbx, %r13
jne .LBB4_8
# %bb.13: # %._crit_edge136
callq clock
movq %rax, -88(%rbp) # 8-byte Spill
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq -80(%rbp), %rax # 8-byte Reload
movq -72(%rbp), %rcx # 8-byte Reload
movq (%rax,%rcx,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB4_29
# %bb.14: # %.lr.ph158
movq -48(%rbp), %rax # 8-byte Reload
cmpl $2, %eax
movl $1, %r13d
cmovgel %eax, %r13d
leaq 15(,%rax,4), %r15
andq $-16, %r15
movq %r15, -56(%rbp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_15: # %.lr.ph140.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_16 Depth 2
# Child Loop BB4_18 Depth 2
# Child Loop BB4_20 Depth 2
# Child Loop BB4_21 Depth 3
# Child Loop BB4_24 Depth 2
movq %rbx, -64(%rbp) # 8-byte Spill
movq %rsp, -48(%rbp) # 8-byte Spill
movq %rsp, %r12
subq %r15, %r12
movq %r12, %rsp
xorl %ebx, %ebx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph140
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addl %eax, %r15d
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %r13
jne .LBB4_16
# %bb.17: # %.lr.ph142
# in Loop: Header=BB4_15 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, (%r12,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB4_18
# %bb.19: # %.preheader125
# in Loop: Header=BB4_15 Depth=1
movq %rsp, %rax
movq -56(%rbp), %r15 # 8-byte Reload
subq %r15, %rax
movq %rax, %rsp
xorl %ecx, %ecx
movq -64(%rbp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB4_20: # %.lr.ph150
# Parent Loop BB4_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_21 Depth 3
movl $0, (%rax,%rcx,4)
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_21: # Parent Loop BB4_15 Depth=1
# Parent Loop BB4_20 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq (%r14,%rdx,8), %rsi
mulss (%rsi,%rcx,4), %xmm1
addss %xmm1, %xmm0
incq %rdx
cmpq %rdx, %r13
jne .LBB4_21
# %bb.22: # %._crit_edge146
# in Loop: Header=BB4_20 Depth=2
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq %r13, %rcx
jne .LBB4_20
# %bb.23: # %.lr.ph153.preheader
# in Loop: Header=BB4_15 Depth=1
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_24: # %.lr.ph153
# Parent Loop BB4_15 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12,%rcx,4), %xmm1
addss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %r13
jne .LBB4_24
# %bb.25: # %._crit_edge154
# in Loop: Header=BB4_15 Depth=1
xorps %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .LBB4_26
.LBB4_28: # %cdce.end
# in Loop: Header=BB4_15 Depth=1
movq -48(%rbp), %rsp # 8-byte Reload
incl %ebx
movq -80(%rbp), %rax # 8-byte Reload
movq -72(%rbp), %rcx # 8-byte Reload
movq (%rax,%rcx,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl %eax, %ebx
jl .LBB4_15
jmp .LBB4_29
.LBB4_26: # %cdce.call
# in Loop: Header=BB4_15 Depth=1
ucomiss .LCPI4_4(%rip), %xmm0
jae .LBB4_28
# %bb.27: # %call.sqrt
# in Loop: Header=BB4_15 Depth=1
callq sqrtf
jmp .LBB4_28
.LBB4_29: # %._crit_edge159
callq clock
subq -88(%rbp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
divss .LCPI4_3(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
jmp printf # TAILCALL
.LBB4_30:
.cfi_def_cfa %rbp, 16
movl $.L.str.6, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size _Z4goldiPPc, .Lfunc_end4-_Z4goldiPPc
.cfi_endproc
# -- End function
.globl _Z30__device_stub__GPercentReturnsPfS_i # -- Begin function _Z30__device_stub__GPercentReturnsPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__GPercentReturnsPfS_i,@function
_Z30__device_stub__GPercentReturnsPfS_i: # @_Z30__device_stub__GPercentReturnsPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15GPercentReturnsPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z30__device_stub__GPercentReturnsPfS_i, .Lfunc_end5-_Z30__device_stub__GPercentReturnsPfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__GReduceAverageRPfii # -- Begin function _Z30__device_stub__GReduceAverageRPfii
.p2align 4, 0x90
.type _Z30__device_stub__GReduceAverageRPfii,@function
_Z30__device_stub__GReduceAverageRPfii: # @_Z30__device_stub__GReduceAverageRPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15GReduceAverageRPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size _Z30__device_stub__GReduceAverageRPfii, .Lfunc_end6-_Z30__device_stub__GReduceAverageRPfii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__GCovariancePfi # -- Begin function _Z26__device_stub__GCovariancePfi
.p2align 4, 0x90
.type _Z26__device_stub__GCovariancePfi,@function
_Z26__device_stub__GCovariancePfi: # @_Z26__device_stub__GCovariancePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11GCovariancePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z26__device_stub__GCovariancePfi, .Lfunc_end7-_Z26__device_stub__GCovariancePfi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__GPortfolioPfS_ii # -- Begin function _Z25__device_stub__GPortfolioPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__GPortfolioPfS_ii,@function
_Z25__device_stub__GPortfolioPfS_ii: # @_Z25__device_stub__GPortfolioPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10GPortfolioPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z25__device_stub__GPortfolioPfS_ii, .Lfunc_end8-_Z25__device_stub__GPortfolioPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3gpuiPPc
.LCPI9_0:
.long 0x447a0000 # float 1000
.text
.globl _Z3gpuiPPc
.p2align 4, 0x90
.type _Z3gpuiPPc,@function
_Z3gpuiPPc: # @_Z3gpuiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %r12d
movslq %edi, %rbx
addl $-2, %r12d
leaq -2(%rbx), %r15
leaq -8(,%rbx,4), %r13
imulq $400, %r15, %rdi # imm = 0x190
movq %rdi, 8(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbp
imulq $396, %r15, %rdi # imm = 0x18C
movq %rdi, 184(%rsp) # 8-byte Spill
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
movq %r13, 200(%rsp) # 8-byte Spill
movq %r15, 216(%rsp) # 8-byte Spill
imulq %r15, %r13
movq %r13, 128(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 208(%rsp) # 8-byte Spill
movq %rbx, 224(%rsp) # 8-byte Spill
cmpl $3, %ebx
jl .LBB9_3
# %bb.1: # %.lr.ph.preheader
xorl %r15d, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB9_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %r13
sarq $30, %r13
addq %rbp, %r13
movq 8(%r14,%rbx,8), %rdi
callq _Z8readFilePc
movl $400, %edx # imm = 0x190
movq %r13, %rdi
movq %rax, %rsi
callq memcpy@PLT
incq %rbx
movabsq $429496729600, %rax # imm = 0x6400000000
addq %rax, %r15
cmpq %rbx, %r12
jne .LBB9_2
.LBB9_3: # %._crit_edge
movq %r14, %rbx
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 168(%rsp), %rdi
movq 8(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq 184(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
movq 168(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 8(%rsp) # 8-byte Spill
movl %r12d, %r12d
orq %r14, %r12
leaq 100(%r14), %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_5
# %bb.4:
movq 168(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15GPercentReturnsPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_5:
movq 88(%rsp), %rsi
movq 176(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $c_returns, %edi
movq %r13, %rsi
movq %r15, %rdx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 99(%r14), %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 224(%rsp), %r14 # 8-byte Reload
jne .LBB9_7
# %bb.6:
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 16(%rsp)
movl $64, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15GReduceAverageRPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_7:
movq 88(%rsp), %rsi
movq 192(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq 200(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $1, %ebp
movl $c_averages, %edi
movq %r13, %rsi
movq %r15, %rdx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_9
# %bb.8:
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11GCovariancePfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_9:
movq 88(%rsp), %rsi
movq 208(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movq 128(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $c_covariance, %edi
movq %r13, %rsi
movq %r15, %rdx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 80(%rsp), %rdi
callq hipEventCreate
leaq 136(%rsp), %rdi
callq hipEventCreate
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -8(%rbx,%r14,8), %r15
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 128(%rsp) # 8-byte Spill
movq -8(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rsi
shlq $2, %rsi
leaq 160(%rsp), %rdi
callq hipMalloc
movq -8(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rsi
shlq $2, %rsi
leaq 152(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB9_10: # =>This Inner Loop Header: Depth=1
movl %ebp, %r15d
leal (%r15,%r15), %ebp
cmpl %eax, %ebp
jle .LBB9_10
# %bb.11:
movq -8(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq 216(%rsp), %r8 # 8-byte Reload
shlq $3, %r8
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq %r14, %r12
jne .LBB9_13
# %bb.12:
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 148(%rsp)
movl %r15d, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 148(%rsp), %rax
movq %rax, 112(%rsp)
leaq 144(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10GPortfolioPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_13:
movq 160(%rsp), %r14
movq -8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdx
shlq $2, %rdx
movq %r13, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
movq 152(%rsp), %r14
movq -8(%rbx,%r12,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rdx
shlq $2, %rdx
movq 128(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 136(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 136(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rsi
movq 136(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB9_14
.LBB9_15:
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI9_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB9_14:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorName
movl $.L.str.11, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB9_15
.Lfunc_end9:
.size _Z3gpuiPPc, .Lfunc_end9-_Z3gpuiPPc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI10_0:
.long 0x447a0000 # float 1000
.LCPI10_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
leal -2(%r14), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movslq %r14d, %r14
movq -8(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $.L.str.14, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
callq clock
movq %rax, %r15
movl %r14d, %edi
movq %rbx, %rsi
callq _Z4goldiPPc
callq clock
subq %r15, %rax
cvtsi2ss %rax, %xmm0
movss .LCPI10_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
divss .LCPI10_1(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r15
movl %r14d, %edi
movq %rbx, %rsi
callq _Z3gpuiPPc
callq clock
subq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss .LCPI10_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
divss .LCPI10_1(%rip), %xmm0
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15GPercentReturnsPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15GReduceAverageRPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11GCovariancePfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10GPortfolioPfS_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_returns, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $33660, %r9d # imm = 0x837C
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_averages, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $340, %r9d # imm = 0x154
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_covariance, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $28900, %r9d # imm = 0x70E4
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error reading file"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ","
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f %f\n"
.size .L.str.4, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Expected more arguments"
.size .L.str.6, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CPU time portfolio %f seconds\n"
.size .L.str.10, 31
.type c_returns,@object # @c_returns
.local c_returns
.comm c_returns,33660,16
.type c_averages,@object # @c_averages
.local c_averages
.comm c_averages,340,16
.type c_covariance,@object # @c_covariance
.local c_covariance
.comm c_covariance,28900,16
.type _Z15GPercentReturnsPfS_i,@object # @_Z15GPercentReturnsPfS_i
.section .rodata,"a",@progbits
.globl _Z15GPercentReturnsPfS_i
.p2align 3, 0x0
_Z15GPercentReturnsPfS_i:
.quad _Z30__device_stub__GPercentReturnsPfS_i
.size _Z15GPercentReturnsPfS_i, 8
.type _Z15GReduceAverageRPfii,@object # @_Z15GReduceAverageRPfii
.globl _Z15GReduceAverageRPfii
.p2align 3, 0x0
_Z15GReduceAverageRPfii:
.quad _Z30__device_stub__GReduceAverageRPfii
.size _Z15GReduceAverageRPfii, 8
.type _Z11GCovariancePfi,@object # @_Z11GCovariancePfi
.globl _Z11GCovariancePfi
.p2align 3, 0x0
_Z11GCovariancePfi:
.quad _Z26__device_stub__GCovariancePfi
.size _Z11GCovariancePfi, 8
.type _Z10GPortfolioPfS_ii,@object # @_Z10GPortfolioPfS_ii
.globl _Z10GPortfolioPfS_ii
.p2align 3, 0x0
_Z10GPortfolioPfS_ii:
.quad _Z25__device_stub__GPortfolioPfS_ii
.size _Z10GPortfolioPfS_ii, 8
.type .L.str.11,@object # @.str.11
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.11:
.asciz "GPUassert: %s\n"
.size .L.str.11, 15
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Time for portfolio: %f s\n"
.size .L.str.12, 26
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Num stocks: %i \n"
.size .L.str.13, 17
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Num port: %i \n"
.size .L.str.14, 15
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Total CPU time taken %f seconds\n"
.size .L.str.15, 33
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Total GPU time taken %f seconds \n"
.size .L.str.16, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15GPercentReturnsPfS_i"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15GReduceAverageRPfii"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11GCovariancePfi"
.size .L__unnamed_3, 19
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10GPortfolioPfS_ii"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "c_returns"
.size .L__unnamed_5, 10
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "c_averages"
.size .L__unnamed_6, 11
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "c_covariance"
.size .L__unnamed_7, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__GPercentReturnsPfS_i
.addrsig_sym _Z30__device_stub__GReduceAverageRPfii
.addrsig_sym _Z26__device_stub__GCovariancePfi
.addrsig_sym _Z25__device_stub__GPortfolioPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_returns
.addrsig_sym c_averages
.addrsig_sym c_covariance
.addrsig_sym _Z15GPercentReturnsPfS_i
.addrsig_sym _Z15GReduceAverageRPfii
.addrsig_sym _Z11GCovariancePfi
.addrsig_sym _Z10GPortfolioPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include "cuda.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(cudaError_t e){
assert(e == cudaSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(cudaMalloc(&a, N * N * sizeof(int)));
check_error(cudaMalloc(&b, N * N * sizeof(int)));
check_error(cudaMalloc(&c, N * N * sizeof(int)));
check_error(cudaMemcpy(a,local_a,N * N * sizeof(int),cudaMemcpyHostToDevice));
check_error(cudaMemcpy(b,local_b,N * N * sizeof(int),cudaMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(cudaMemcpy(local_c,c,N * N * sizeof(int),cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} | code for sm_80
Function : _Z10matmul_gpuPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R9, R9, 0xb, RZ ; /* 0x0000000b09097819 */
/* 0x001fd000000006ff */
/*0050*/ MOV R8, R0.reuse ; /* 0x0000000000087202 */
/* 0x080fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R2, R9, R0, RZ ; /* 0x0000000009027210 */
/* 0x001fe40007ffe0ff */
/*0080*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe40000000f00 */
/*0090*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ MOV R10, c[0x0][0x160] ; /* 0x00005800000a7a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00c0*/ ISETP.GE.U32.AND P3, PT, R0, 0x800, PT ; /* 0x000008000000780c */
/* 0x000fc40003f66070 */
/*00d0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0120*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R6, R8, 0x4, R6 ; /* 0x0000000408067825 */
/* 0x000fe200078e0206 */
/*0160*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x001ea4000c1e1900 */
/*0180*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x004fca00078e02ff */
/*0190*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*01a0*/ LDG.E R16, [R6.64+0x2000] ; /* 0x0020000406107981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x004fca00078e02ff */
/*01d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*01e0*/ LDG.E R16, [R6.64+0x4000] ; /* 0x0040000406107981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080404137981 */
/* 0x000ea4000c1e1900 */
/*0200*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x004fca00078e02ff */
/*0210*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0220*/ LDG.E R16, [R6.64+0x6000] ; /* 0x0060000406107981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000ee4000c1e1900 */
/*0240*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fca00078e02ff */
/*0250*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0260*/ LDG.E R15, [R6.64+0x8000] ; /* 0x00800004060f7981 */
/* 0x001f28000c1e1900 */
/*0270*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f24000c1e1900 */
/*0280*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0290*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R16, [R6.64+0xa000] ; /* 0x00a0000406107981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140404117981 */
/* 0x002f24000c1e1900 */
/*02c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*02d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R16, [R6.64+0xc000] ; /* 0x00c0000406107981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R19, [R4.64+0x18] ; /* 0x0000180404137981 */
/* 0x004f24000c1e1900 */
/*0300*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0310*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R16, [R6.64+0xe000] ; /* 0x00e0000406107981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x008f24000c1e1900 */
/*0340*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x010fca00078e02ff */
/*0350*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R15, [R6.64+0x10000] ; /* 0x01000004060f7981 */
/* 0x001f28000c1e1900 */
/*0370*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000f24000c1e1900 */
/*0380*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0390*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R16, [R6.64+0x12000] ; /* 0x0120000406107981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x002f24000c1e1900 */
/*03c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*03d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R16, [R6.64+0x14000] ; /* 0x0140000406107981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R19, [R4.64+0x28] ; /* 0x0000280404137981 */
/* 0x004f24000c1e1900 */
/*0400*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R16, [R6.64+0x16000] ; /* 0x0160000406107981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x008f24000c1e1900 */
/*0440*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x010fca00078e02ff */
/*0450*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0460*/ LDG.E R15, [R6.64+0x18000] ; /* 0x01800004060f7981 */
/* 0x001f28000c1e1900 */
/*0470*/ LDG.E R16, [R4.64+0x30] ; /* 0x0000300404107981 */
/* 0x000f24000c1e1900 */
/*0480*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0490*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R16, [R6.64+0x1a000] ; /* 0x01a0000406107981 */
/* 0x000f28000c1e1900 */
/*04b0*/ LDG.E R17, [R4.64+0x34] ; /* 0x0000340404117981 */
/* 0x002f24000c1e1900 */
/*04c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*04d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R16, [R6.64+0x1c000] ; /* 0x01c0000406107981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R19, [R4.64+0x38] ; /* 0x0000380404137981 */
/* 0x004f22000c1e1900 */
/*0500*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0520*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0530*/ LDG.E R16, [R6.64+0x1e000] ; /* 0x01e0000406107981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R21, [R4.64+0x3c] ; /* 0x00003c0404157981 */
/* 0x008ea2000c1e1900 */
/*0550*/ ISETP.NE.AND P0, PT, R14, 0x800, PT ; /* 0x000008000e00780c */
/* 0x000fe40003f05270 */
/*0560*/ IADD3 R12, P1, R12, 0x20000, RZ ; /* 0x000200000c0c7810 */
/* 0x000fc40007f3e0ff */
/*0570*/ IADD3 R10, P2, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x000fe40007f5e0ff */
/*0580*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe40000ffe4ff */
/*0590*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05a0*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x004fca00078e02ff */
/*05b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e2000c101904 */
/*05c0*/ @P0 BRA 0x100 ; /* 0xfffffb3000000947 */
/* 0x000fea000383ffff */
/*05d0*/ @!P3 BRA 0x50 ; /* 0xfffffa700000b947 */
/* 0x000fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include "cuda.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(cudaError_t e){
assert(e == cudaSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(cudaMalloc(&a, N * N * sizeof(int)));
check_error(cudaMalloc(&b, N * N * sizeof(int)));
check_error(cudaMalloc(&c, N * N * sizeof(int)));
check_error(cudaMemcpy(a,local_a,N * N * sizeof(int),cudaMemcpyHostToDevice));
check_error(cudaMemcpy(b,local_b,N * N * sizeof(int),cudaMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(cudaMemcpy(local_c,c,N * N * sizeof(int),cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} | .file "tmpxft_00070d2b_00000000-6_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3776:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13local_executePiS_S_
.type _Z13local_executePiS_S_, @function
_Z13local_executePiS_S_:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %rbp
movq %rdx, %rbx
movq %rdi, %r10
movl $0, %r11d
.L4:
leaq 16777216(%rbx), %rsi
movq %r11, %r9
salq $13, %r9
addq %rbp, %r9
movq %r10, %rdi
movl $0, %r8d
.L8:
leaq -16777216(%rsi), %rax
movq %r9, %rcx
.L5:
movl (%rcx), %edx
imull (%rax), %edx
movl %edx, (%rdi)
addq $4, %rcx
addq $8192, %rax
cmpq %rsi, %rax
jne .L5
addl $1, %r8d
addq $4, %rdi
addq $4, %rsi
cmpl $2048, %r8d
jne .L8
addq $1, %r11
addq $8192, %r10
cmpq $2048, %r11
jne .L4
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size _Z13local_executePiS_S_, .-_Z13local_executePiS_S_
.globl _Z11check_error9cudaError
.type _Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB3769:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3769:
.size _Z11check_error9cudaError, .-_Z11check_error9cudaError
.globl _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
.type _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_, @function
_Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_:
.LFB3798:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matmul_gpuPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_, .-_Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
.globl _Z10matmul_gpuPiS_S_
.type _Z10matmul_gpuPiS_S_, @function
_Z10matmul_gpuPiS_S_:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _Z10matmul_gpuPiS_S_, .-_Z10matmul_gpuPiS_S_
.globl _Z11gpu_executePiS_S_
.type _Z11gpu_executePiS_S_, @function
_Z11gpu_executePiS_S_:
.LFB3770:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $2048, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z11gpu_executePiS_S_, .-_Z11gpu_executePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix Size"
.LC1:
.string "MB\n"
.LC2:
.string "GPU Run time "
.LC3:
.string "ms \n"
.LC4:
.string "Local run time "
.text
.globl main
.type main, @function
main:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $0, %eax
.L27:
movl $1, 0(%rbp,%rax)
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L27
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call _Z11gpu_executePiS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r15, %rcx
subq %r13, %rcx
movabsq $4835703278458516699, %r12
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %r15
movq %r15, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call _Z13local_executePiS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
leaq .LC4(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rcx
subq %r13, %rcx
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
movq %r15, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10matmul_gpuPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matmul_gpuPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include "cuda.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(cudaError_t e){
assert(e == cudaSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(cudaMalloc(&a, N * N * sizeof(int)));
check_error(cudaMalloc(&b, N * N * sizeof(int)));
check_error(cudaMalloc(&c, N * N * sizeof(int)));
check_error(cudaMemcpy(a,local_a,N * N * sizeof(int),cudaMemcpyHostToDevice));
check_error(cudaMemcpy(b,local_b,N * N * sizeof(int),cudaMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(cudaMemcpy(local_c,c,N * N * sizeof(int),cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} | #include<iostream>
#include "hip/hip_runtime.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(hipError_t e){
assert(e == hipSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(hipMalloc(&a, N * N * sizeof(int)));
check_error(hipMalloc(&b, N * N * sizeof(int)));
check_error(hipMalloc(&c, N * N * sizeof(int)));
check_error(hipMemcpy(a,local_a,N * N * sizeof(int),hipMemcpyHostToDevice));
check_error(hipMemcpy(b,local_b,N * N * sizeof(int),hipMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(hipMemcpy(local_c,c,N * N * sizeof(int),hipMemcpyDeviceToHost));
hipDeviceSynchronize();
hipFree(a);
hipFree(b);
hipFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<iostream>
#include "hip/hip_runtime.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(hipError_t e){
assert(e == hipSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(hipMalloc(&a, N * N * sizeof(int)));
check_error(hipMalloc(&b, N * N * sizeof(int)));
check_error(hipMalloc(&c, N * N * sizeof(int)));
check_error(hipMemcpy(a,local_a,N * N * sizeof(int),hipMemcpyHostToDevice));
check_error(hipMemcpy(b,local_b,N * N * sizeof(int),hipMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(hipMemcpy(local_c,c,N * N * sizeof(int),hipMemcpyDeviceToHost));
hipDeviceSynchronize();
hipFree(a);
hipFree(b);
hipFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matmul_gpuPiS_S_
.globl _Z10matmul_gpuPiS_S_
.p2align 8
.type _Z10matmul_gpuPiS_S_,@function
_Z10matmul_gpuPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b32 s2, s15, 11
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_mov_b32 s13, 0
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s8
s_addc_u32 s12, s5, s9
.p2align 6
.LBB0_1:
s_or_b32 s4, s13, s2
s_mov_b64 s[10:11], s[6:7]
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[4:5], 2
s_mov_b64 s[4:5], 0
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
.p2align 6
.LBB0_2:
s_add_u32 s14, s3, s4
s_addc_u32 s15, s12, s5
s_add_u32 s4, s4, 4
s_clause 0x1
global_load_b32 v1, v0, s[14:15]
global_load_b32 v2, v0, s[10:11]
s_addc_u32 s5, s5, 0
s_add_u32 s10, s10, 0x2000
s_addc_u32 s11, s11, 0
s_cmpk_eq_i32 s4, 0x2000
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[8:9]
s_cbranch_scc0 .LBB0_2
s_add_i32 s13, s13, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s13, 0x800
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matmul_gpuPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matmul_gpuPiS_S_, .Lfunc_end0-_Z10matmul_gpuPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matmul_gpuPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10matmul_gpuPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include "hip/hip_runtime.h"
#include "assert.h"
#include <chrono>
#define N (1<<11)
void local_execute(int *c, int *local_a, int *local_b){
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + local_a[i*N + k]*local_b[j + k*N];
}
}
}
}
//
//int verify(int *c){
// int error = 0;
// for(int i=0;i<size;i++){
// error = error + abs(4-c[i]);
// }
// return error;
//}
//
void check_error(hipError_t e){
assert(e == hipSuccess);
}
//
__global__ void matmul_gpu(int *a,int *b,int *c){
int i = blockIdx.x;
for(int j=0;j<N;j++){
int s =0;
for(int k=0;k<N;k++){
c[i*N+j] = s + a[i*N + k]*b[j + k*N];
}
}
}
//
void gpu_execute(int *local_a, int* local_b, int *local_c){
int *a,*b,*c;
check_error(hipMalloc(&a, N * N * sizeof(int)));
check_error(hipMalloc(&b, N * N * sizeof(int)));
check_error(hipMalloc(&c, N * N * sizeof(int)));
check_error(hipMemcpy(a,local_a,N * N * sizeof(int),hipMemcpyHostToDevice));
check_error(hipMemcpy(b,local_b,N * N * sizeof(int),hipMemcpyHostToDevice));
matmul_gpu<<<N,1>>>(a,b,c);
check_error(hipMemcpy(local_c,c,N * N * sizeof(int),hipMemcpyDeviceToHost));
hipDeviceSynchronize();
hipFree(a);
hipFree(b);
hipFree(c);
}
/*
* Current Speed UP:
* GPU Run time 3904ms
* Local run time 80398ms
*/
int main(){
int * local_a = (int *)malloc(sizeof(int) * N * N);
int * local_b = (int *)malloc(sizeof(int) * N * N);
int * c = (int *)malloc(sizeof(int) * N * N);
for(int i=0;i<N;i++){
local_a[i]= 1;
local_b[i]= 1;
}
std::cout << "Matrix Size" << ((N * N * 4)/(1<<20)) <<"MB\n";
auto start_time = std::chrono::high_resolution_clock::now();
gpu_execute(c,local_a,local_b);
auto end_time = std::chrono::high_resolution_clock::now();
std::cout << "GPU Run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
start_time = std::chrono::high_resolution_clock::now();
local_execute(c,local_a,local_b);
end_time = std::chrono::high_resolution_clock::now();
std::cout << "Local run time " << (end_time - start_time)/std::chrono::milliseconds(1) <<"ms \n";
free(local_a);
free(local_b);
free(c);
// gpu_execute(local_a,local_b,c);
// std::cout << "Max Error" << verify(c) <<"\n";
} | .text
.file "matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13local_executePiS_S_ # -- Begin function _Z13local_executePiS_S_
.p2align 4, 0x90
.type _Z13local_executePiS_S_,@function
_Z13local_executePiS_S_: # @_Z13local_executePiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader17
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
movq %rax, %rcx
shlq $11, %rcx
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
movq %r9, %r10
orq %rcx, %r10
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %ebp
imull (%rsi,%rbx,4), %ebp
movl %ebp, (%rdi,%r10,4)
incq %rbx
addq $8192, %r11 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=2
incq %r9
addq $4, %r8
cmpq $2048, %r9 # imm = 0x800
jne .LBB0_2
# %bb.5: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $8192, %rsi # imm = 0x2000
cmpq $2048, %rax # imm = 0x800
jne .LBB0_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13local_executePiS_S_, .Lfunc_end0-_Z13local_executePiS_S_
.cfi_endproc
# -- End function
.globl _Z11check_error10hipError_t # -- Begin function _Z11check_error10hipError_t
.p2align 4, 0x90
.type _Z11check_error10hipError_t,@function
_Z11check_error10hipError_t: # @_Z11check_error10hipError_t
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z11check_error10hipError_t, .Lfunc_end1-_Z11check_error10hipError_t
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matmul_gpuPiS_S_ # -- Begin function _Z25__device_stub__matmul_gpuPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matmul_gpuPiS_S_,@function
_Z25__device_stub__matmul_gpuPiS_S_: # @_Z25__device_stub__matmul_gpuPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matmul_gpuPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__matmul_gpuPiS_S_, .Lfunc_end2-_Z25__device_stub__matmul_gpuPiS_S_
.cfi_endproc
# -- End function
.globl _Z11gpu_executePiS_S_ # -- Begin function _Z11gpu_executePiS_S_
.p2align 4, 0x90
.type _Z11gpu_executePiS_S_,@function
_Z11gpu_executePiS_S_: # @_Z11gpu_executePiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 2047(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matmul_gpuPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11gpu_executePiS_S_, .Lfunc_end3-_Z11gpu_executePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
movl $1, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB4_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $16, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq _Z11gpu_executePiS_S_
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movabsq $4835703278458516699, %rbp # imm = 0x431BDE82D7B634DB
movq %r13, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq %r15, %rax
.p2align 4, 0x90
.LBB4_3: # %.preheader17.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %r13, %rcx
shlq $13, %rcx
movl 8188(%rbx,%rcx), %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movl 16769024(%r14,%rdx,4), %esi
imull %ecx, %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq $2048, %rdx # imm = 0x800
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
incq %r13
addq $8192, %rax # imm = 0x2000
cmpq $2048, %r13 # imm = 0x800
jne .LBB4_3
# %bb.6: # %_Z13local_executePiS_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movq %r13, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matmul_gpuPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matmul_gpuPiS_S_,@object # @_Z10matmul_gpuPiS_S_
.section .rodata,"a",@progbits
.globl _Z10matmul_gpuPiS_S_
.p2align 3, 0x0
_Z10matmul_gpuPiS_S_:
.quad _Z25__device_stub__matmul_gpuPiS_S_
.size _Z10matmul_gpuPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix Size"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "MB\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Run time "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms \n"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Local run time "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matmul_gpuPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matmul_gpuPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matmul_gpuPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matmul_gpuPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R9, R9, 0xb, RZ ; /* 0x0000000b09097819 */
/* 0x001fd000000006ff */
/*0050*/ MOV R8, R0.reuse ; /* 0x0000000000087202 */
/* 0x080fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R2, R9, R0, RZ ; /* 0x0000000009027210 */
/* 0x001fe40007ffe0ff */
/*0080*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe40000000f00 */
/*0090*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ MOV R10, c[0x0][0x160] ; /* 0x00005800000a7a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*00c0*/ ISETP.GE.U32.AND P3, PT, R0, 0x800, PT ; /* 0x000008000000780c */
/* 0x000fc40003f66070 */
/*00d0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0120*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fc800078e0204 */
/*0150*/ IMAD.WIDE R6, R8, 0x4, R6 ; /* 0x0000000408067825 */
/* 0x000fe200078e0206 */
/*0160*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x001ea4000c1e1900 */
/*0180*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x004fca00078e02ff */
/*0190*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*01a0*/ LDG.E R16, [R6.64+0x2000] ; /* 0x0020000406107981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x004fca00078e02ff */
/*01d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*01e0*/ LDG.E R16, [R6.64+0x4000] ; /* 0x0040000406107981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R19, [R4.64+0x8] ; /* 0x0000080404137981 */
/* 0x000ea4000c1e1900 */
/*0200*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x004fca00078e02ff */
/*0210*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0220*/ LDG.E R16, [R6.64+0x6000] ; /* 0x0060000406107981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0404157981 */
/* 0x000ee4000c1e1900 */
/*0240*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x008fca00078e02ff */
/*0250*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0260*/ LDG.E R15, [R6.64+0x8000] ; /* 0x00800004060f7981 */
/* 0x001f28000c1e1900 */
/*0270*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f24000c1e1900 */
/*0280*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0290*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R16, [R6.64+0xa000] ; /* 0x00a0000406107981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140404117981 */
/* 0x002f24000c1e1900 */
/*02c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*02d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R16, [R6.64+0xc000] ; /* 0x00c0000406107981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R19, [R4.64+0x18] ; /* 0x0000180404137981 */
/* 0x004f24000c1e1900 */
/*0300*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0310*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0320*/ LDG.E R16, [R6.64+0xe000] ; /* 0x00e0000406107981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x008f24000c1e1900 */
/*0340*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x010fca00078e02ff */
/*0350*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R15, [R6.64+0x10000] ; /* 0x01000004060f7981 */
/* 0x001f28000c1e1900 */
/*0370*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000f24000c1e1900 */
/*0380*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0390*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R16, [R6.64+0x12000] ; /* 0x0120000406107981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R17, [R4.64+0x24] ; /* 0x0000240404117981 */
/* 0x002f24000c1e1900 */
/*03c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*03d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R16, [R6.64+0x14000] ; /* 0x0140000406107981 */
/* 0x000f28000c1e1900 */
/*03f0*/ LDG.E R19, [R4.64+0x28] ; /* 0x0000280404137981 */
/* 0x004f24000c1e1900 */
/*0400*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0410*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R16, [R6.64+0x16000] ; /* 0x0160000406107981 */
/* 0x000f28000c1e1900 */
/*0430*/ LDG.E R21, [R4.64+0x2c] ; /* 0x00002c0404157981 */
/* 0x008f24000c1e1900 */
/*0440*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x010fca00078e02ff */
/*0450*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*0460*/ LDG.E R15, [R6.64+0x18000] ; /* 0x01800004060f7981 */
/* 0x001f28000c1e1900 */
/*0470*/ LDG.E R16, [R4.64+0x30] ; /* 0x0000300404107981 */
/* 0x000f24000c1e1900 */
/*0480*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x010fca00078e02ff */
/*0490*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R16, [R6.64+0x1a000] ; /* 0x01a0000406107981 */
/* 0x000f28000c1e1900 */
/*04b0*/ LDG.E R17, [R4.64+0x34] ; /* 0x0000340404117981 */
/* 0x002f24000c1e1900 */
/*04c0*/ IMAD R17, R16, R17, RZ ; /* 0x0000001110117224 */
/* 0x010fca00078e02ff */
/*04d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*04e0*/ LDG.E R16, [R6.64+0x1c000] ; /* 0x01c0000406107981 */
/* 0x000f28000c1e1900 */
/*04f0*/ LDG.E R19, [R4.64+0x38] ; /* 0x0000380404137981 */
/* 0x004f22000c1e1900 */
/*0500*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ IMAD R19, R16, R19, RZ ; /* 0x0000001310137224 */
/* 0x010fca00078e02ff */
/*0520*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0530*/ LDG.E R16, [R6.64+0x1e000] ; /* 0x01e0000406107981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R21, [R4.64+0x3c] ; /* 0x00003c0404157981 */
/* 0x008ea2000c1e1900 */
/*0550*/ ISETP.NE.AND P0, PT, R14, 0x800, PT ; /* 0x000008000e00780c */
/* 0x000fe40003f05270 */
/*0560*/ IADD3 R12, P1, R12, 0x20000, RZ ; /* 0x000200000c0c7810 */
/* 0x000fc40007f3e0ff */
/*0570*/ IADD3 R10, P2, R10, 0x40, RZ ; /* 0x000000400a0a7810 */
/* 0x000fe40007f5e0ff */
/*0580*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe40000ffe4ff */
/*0590*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05a0*/ IMAD R21, R16, R21, RZ ; /* 0x0000001510157224 */
/* 0x004fca00078e02ff */
/*05b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e2000c101904 */
/*05c0*/ @P0 BRA 0x100 ; /* 0xfffffb3000000947 */
/* 0x000fea000383ffff */
/*05d0*/ @!P3 BRA 0x50 ; /* 0xfffffa700000b947 */
/* 0x000fea000383ffff */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ BRA 0x5f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matmul_gpuPiS_S_
.globl _Z10matmul_gpuPiS_S_
.p2align 8
.type _Z10matmul_gpuPiS_S_,@function
_Z10matmul_gpuPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b32 s2, s15, 11
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_mov_b32 s13, 0
s_lshl_b64 s[8:9], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, s8
s_addc_u32 s12, s5, s9
.p2align 6
.LBB0_1:
s_or_b32 s4, s13, s2
s_mov_b64 s[10:11], s[6:7]
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[4:5], 2
s_mov_b64 s[4:5], 0
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
.p2align 6
.LBB0_2:
s_add_u32 s14, s3, s4
s_addc_u32 s15, s12, s5
s_add_u32 s4, s4, 4
s_clause 0x1
global_load_b32 v1, v0, s[14:15]
global_load_b32 v2, v0, s[10:11]
s_addc_u32 s5, s5, 0
s_add_u32 s10, s10, 0x2000
s_addc_u32 s11, s11, 0
s_cmpk_eq_i32 s4, 0x2000
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[8:9]
s_cbranch_scc0 .LBB0_2
s_add_i32 s13, s13, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s13, 0x800
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matmul_gpuPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matmul_gpuPiS_S_, .Lfunc_end0-_Z10matmul_gpuPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matmul_gpuPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10matmul_gpuPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070d2b_00000000-6_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3776:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13local_executePiS_S_
.type _Z13local_executePiS_S_, @function
_Z13local_executePiS_S_:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %rbp
movq %rdx, %rbx
movq %rdi, %r10
movl $0, %r11d
.L4:
leaq 16777216(%rbx), %rsi
movq %r11, %r9
salq $13, %r9
addq %rbp, %r9
movq %r10, %rdi
movl $0, %r8d
.L8:
leaq -16777216(%rsi), %rax
movq %r9, %rcx
.L5:
movl (%rcx), %edx
imull (%rax), %edx
movl %edx, (%rdi)
addq $4, %rcx
addq $8192, %rax
cmpq %rsi, %rax
jne .L5
addl $1, %r8d
addq $4, %rdi
addq $4, %rsi
cmpl $2048, %r8d
jne .L8
addq $1, %r11
addq $8192, %r10
cmpq $2048, %r11
jne .L4
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size _Z13local_executePiS_S_, .-_Z13local_executePiS_S_
.globl _Z11check_error9cudaError
.type _Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB3769:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3769:
.size _Z11check_error9cudaError, .-_Z11check_error9cudaError
.globl _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
.type _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_, @function
_Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_:
.LFB3798:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matmul_gpuPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_, .-_Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
.globl _Z10matmul_gpuPiS_S_
.type _Z10matmul_gpuPiS_S_, @function
_Z10matmul_gpuPiS_S_:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _Z10matmul_gpuPiS_S_, .-_Z10matmul_gpuPiS_S_
.globl _Z11gpu_executePiS_S_
.type _Z11gpu_executePiS_S_, @function
_Z11gpu_executePiS_S_:
.LFB3770:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $2048, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10matmul_gpuPiS_S_PiS_S_
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z11gpu_executePiS_S_, .-_Z11gpu_executePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix Size"
.LC1:
.string "MB\n"
.LC2:
.string "GPU Run time "
.LC3:
.string "ms \n"
.LC4:
.string "Local run time "
.text
.globl main
.type main, @function
main:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $0, %eax
.L27:
movl $1, 0(%rbp,%rax)
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $8192, %rax
jne .L27
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call _Z11gpu_executePiS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r15
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r15, %rcx
subq %r13, %rcx
movabsq $4835703278458516699, %r12
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %r15
movq %r15, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call _Z13local_executePiS_S_
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
leaq .LC4(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rcx
subq %r13, %rcx
movq %rcx, %rax
imulq %r12
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
movq %r15, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10matmul_gpuPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matmul_gpuPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13local_executePiS_S_ # -- Begin function _Z13local_executePiS_S_
.p2align 4, 0x90
.type _Z13local_executePiS_S_,@function
_Z13local_executePiS_S_: # @_Z13local_executePiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader17
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
# Child Loop BB0_3 Depth 3
movq %rax, %rcx
shlq $11, %rcx
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# Parent Loop BB0_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_3 Depth 3
movq %r9, %r10
orq %rcx, %r10
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_1 Depth=1
# Parent Loop BB0_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r11), %ebp
imull (%rsi,%rbx,4), %ebp
movl %ebp, (%rdi,%r10,4)
incq %rbx
addq $8192, %r11 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=2
incq %r9
addq $4, %r8
cmpq $2048, %r9 # imm = 0x800
jne .LBB0_2
# %bb.5: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $8192, %rsi # imm = 0x2000
cmpq $2048, %rax # imm = 0x800
jne .LBB0_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13local_executePiS_S_, .Lfunc_end0-_Z13local_executePiS_S_
.cfi_endproc
# -- End function
.globl _Z11check_error10hipError_t # -- Begin function _Z11check_error10hipError_t
.p2align 4, 0x90
.type _Z11check_error10hipError_t,@function
_Z11check_error10hipError_t: # @_Z11check_error10hipError_t
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z11check_error10hipError_t, .Lfunc_end1-_Z11check_error10hipError_t
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matmul_gpuPiS_S_ # -- Begin function _Z25__device_stub__matmul_gpuPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matmul_gpuPiS_S_,@function
_Z25__device_stub__matmul_gpuPiS_S_: # @_Z25__device_stub__matmul_gpuPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matmul_gpuPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__matmul_gpuPiS_S_, .Lfunc_end2-_Z25__device_stub__matmul_gpuPiS_S_
.cfi_endproc
# -- End function
.globl _Z11gpu_executePiS_S_ # -- Begin function _Z11gpu_executePiS_S_
.p2align 4, 0x90
.type _Z11gpu_executePiS_S_,@function
_Z11gpu_executePiS_S_: # @_Z11gpu_executePiS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 2047(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10matmul_gpuPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11gpu_executePiS_S_, .Lfunc_end3-_Z11gpu_executePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
movl $1, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB4_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $16, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq %r15, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq _Z11gpu_executePiS_S_
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movabsq $4835703278458516699, %rbp # imm = 0x431BDE82D7B634DB
movq %r13, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq %r15, %rax
.p2align 4, 0x90
.LBB4_3: # %.preheader17.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movq %r13, %rcx
shlq $13, %rcx
movl 8188(%rbx,%rcx), %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movl 16769024(%r14,%rdx,4), %esi
imull %ecx, %esi
movl %esi, (%rax,%rdx,4)
incq %rdx
cmpq $2048, %rdx # imm = 0x800
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
incq %r13
addq $8192, %rax # imm = 0x2000
cmpq $2048, %r13 # imm = 0x800
jne .LBB4_3
# %bb.6: # %_Z13local_executePiS_S_.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movq %r13, %rax
imulq %rbp
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matmul_gpuPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matmul_gpuPiS_S_,@object # @_Z10matmul_gpuPiS_S_
.section .rodata,"a",@progbits
.globl _Z10matmul_gpuPiS_S_
.p2align 3, 0x0
_Z10matmul_gpuPiS_S_:
.quad _Z25__device_stub__matmul_gpuPiS_S_
.size _Z10matmul_gpuPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix Size"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "MB\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Run time "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ms \n"
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Local run time "
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matmul_gpuPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matmul_gpuPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matmul_gpuPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
cudaMemcpy( h_a, d_a, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | code for sm_80
Function : _Z7isPrimePdy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, P1, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007f3e0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ LOP3.LUT R4, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100047812 */
/* 0x000fe200078ec0ff */
/*00b0*/ BSSY B0, 0x430 ; /* 0x0000037000007945 */
/* 0x000fe20003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06070 */
/*00d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00e0*/ IADD3.X R2, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03027810 */
/* 0x000fe40000ffe4ff */
/*00f0*/ ISETP.NE.U32.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f25070 */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80003f06100 */
/*0110*/ ISETP.NE.U32.OR.EX P0, PT, RZ, RZ, !P0, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0004705510 */
/*0120*/ @P0 BRA 0x420 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe20003f06070 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff077424 */
/* 0x000fd400078e00ff */
/*0160*/ @!P0 BRA 0x420 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*0170*/ SHF.R.U64 R2, R0, 0x1, R3.reuse ; /* 0x0000000100027819 */
/* 0x100fe20000001203 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.U32.HI R4, RZ, 0x1, R3 ; /* 0x00000001ff047819 */
/* 0x000fe20000011603 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*01b0*/ LOP3.LUT R6, R3, R5, RZ, 0xfc, !PT ; /* 0x0000000503067212 */
/* 0x000fe200078efcff */
/*01c0*/ BSSY B1, 0x380 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*01e0*/ @!P0 BRA 0x240 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*01f0*/ MOV R6, 0x210 ; /* 0x0000021000067802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x470 ; /* 0x0000026000007944 */
/* 0x000fea0003c00000 */
/*0210*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f05070 */
/*0220*/ ISETP.NE.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05300 */
/*0230*/ BRA 0x370 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0240*/ I2F.U32.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209000 */
/*0250*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0260*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a09 */
/*02b0*/ IMAD R11, R10, R7, RZ ; /* 0x000000070a0b7224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*02d0*/ IMAD.HI.U32 R9, R9, R0, RZ ; /* 0x0000000009097227 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fca0007ffe1ff */
/*02f0*/ IMAD R10, R7, R9, R0 ; /* 0x00000009070a7224 */
/* 0x000fca00078e0200 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*0310*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fca00078e0a07 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*0330*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fe200078e0a07 */
/*0340*/ @!P1 LOP3.LUT R10, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0a9212 */
/* 0x000fc800078e33ff */
/*0350*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f05070 */
/*0360*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R8, P1, R7, 0x2, RZ ; /* 0x0000000207087810 */
/* 0x000fe40007f3e0ff */
/*0390*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fc6000001ff00 */
/*03a0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*03b0*/ @!P0 BRA 0x420 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0008 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R5, R4, PT, P0 ; /* 0x000000040500720c */
/* 0x000fda0003f06100 */
/*03f0*/ @!P0 BRA 0x1b0 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*0400*/ HFMA2.MMA R7, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff077435 */
/* 0x000fe200000001ff */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fca00078e00ff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fc800078018ff */
/*0440*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1c03 */
/*0450*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0007 */
/*0480*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0005 */
/*0490*/ I2F.U64.RP R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000e300000309000 */
/*04a0*/ MUFU.RCP R8, R12 ; /* 0x0000000c00087308 */
/* 0x001e240000001000 */
/*04b0*/ IADD3 R8, R8, 0x1ffffffe, RZ ; /* 0x1ffffffe08087810 */
/* 0x001fcc0007ffe0ff */
/*04c0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*04d0*/ IMAD.WIDE.U32 R10, R8, R7, RZ ; /* 0x00000007080a7225 */
/* 0x001fc800078e00ff */
/*04e0*/ IMAD R11, R8, R5, R11 ; /* 0x00000005080b7224 */
/* 0x000fe200078e020b */
/*04f0*/ IADD3 R15, P0, RZ, -R10, RZ ; /* 0x8000000aff0f7210 */
/* 0x000fc60007f1e0ff */
/*0500*/ IMAD R11, R9, R7, R11 ; /* 0x00000007090b7224 */
/* 0x000fe400078e020b */
/*0510*/ IMAD.HI.U32 R10, R8, R15, RZ ; /* 0x0000000f080a7227 */
/* 0x000fc800078e00ff */
/*0520*/ IMAD.X R17, RZ, RZ, ~R11, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0e0b */
/*0530*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0540*/ IMAD R13, R9, R17.reuse, RZ ; /* 0x00000011090d7224 */
/* 0x080fe400078e02ff */
/*0550*/ IMAD.WIDE.U32 R10, P0, R8, R17, R10 ; /* 0x00000011080a7225 */
/* 0x000fc8000780000a */
/*0560*/ IMAD.HI.U32 R17, R9, R17, RZ ; /* 0x0000001109117227 */
/* 0x000fc800078e00ff */
/*0570*/ IMAD.HI.U32 R10, P1, R9, R15, R10 ; /* 0x0000000f090a7227 */
/* 0x000fca000782000a */
/*0580*/ IADD3 R11, P2, R13, R10, RZ ; /* 0x0000000a0d0b7210 */
/* 0x000fe20007f5e0ff */
/*0590*/ IMAD.X R10, R17, 0x1, R9, P0 ; /* 0x00000001110a7824 */
/* 0x000fc800000e0609 */
/*05a0*/ IMAD.WIDE.U32 R8, R11, R7, RZ ; /* 0x000000070b087225 */
/* 0x000fe200078e00ff */
/*05b0*/ IADD3.X R12, RZ, RZ, R10, P2, P1 ; /* 0x000000ffff0c7210 */
/* 0x000fc600017e240a */
/*05c0*/ IMAD R9, R11, R5, R9 ; /* 0x000000050b097224 */
/* 0x000fe200078e0209 */
/*05d0*/ IADD3 R13, P0, RZ, -R8, RZ ; /* 0x80000008ff0d7210 */
/* 0x000fc60007f1e0ff */
/*05e0*/ IMAD R9, R12, R7, R9 ; /* 0x000000070c097224 */
/* 0x000fe400078e0209 */
/*05f0*/ IMAD.HI.U32 R10, R11, R13, RZ ; /* 0x0000000d0b0a7227 */
/* 0x000fc600078e00ff */
/*0600*/ IADD3.X R9, RZ, ~R9, RZ, P0, !PT ; /* 0x80000009ff097210 */
/* 0x000fca00007fe4ff */
/*0610*/ IMAD.WIDE.U32 R10, P0, R11, R9, R10 ; /* 0x000000090b0a7225 */
/* 0x000fc8000780000a */
/*0620*/ IMAD R8, R12.reuse, R9, RZ ; /* 0x000000090c087224 */
/* 0x040fe400078e02ff */
/*0630*/ IMAD.HI.U32 R11, P1, R12, R13, R10 ; /* 0x0000000d0c0b7227 */
/* 0x000fc8000782000a */
/*0640*/ IMAD.HI.U32 R9, R12, R9, RZ ; /* 0x000000090c097227 */
/* 0x000fe200078e00ff */
/*0650*/ IADD3 R11, P2, R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x000fc60007f5e0ff */
/*0660*/ IMAD.X R12, R9, 0x1, R12, P0 ; /* 0x00000001090c7824 */
/* 0x000fe400000e060c */
/*0670*/ IMAD.HI.U32 R8, R11, R0, RZ ; /* 0x000000000b087227 */
/* 0x000fc600078e00ff */
/*0680*/ IADD3.X R12, RZ, RZ, R12, P2, P1 ; /* 0x000000ffff0c7210 */
/* 0x000fe200017e240c */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE.U32 R8, R11, R3, R8 ; /* 0x000000030b087225 */
/* 0x000fc800078e0008 */
/*06b0*/ IMAD R11, R12.reuse, R3, RZ ; /* 0x000000030c0b7224 */
/* 0x040fe400078e02ff */
/*06c0*/ IMAD.HI.U32 R8, P0, R12, R0, R8 ; /* 0x000000000c087227 */
/* 0x000fc80007800008 */
/*06d0*/ IMAD.HI.U32 R10, R12, R3, RZ ; /* 0x000000030c0a7227 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3 R12, P1, R11, R8, RZ ; /* 0x000000080b0c7210 */
/* 0x000fc60007f3e0ff */
/*06f0*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400000e060a */
/*0700*/ IMAD.WIDE.U32 R8, R12, R7, RZ ; /* 0x000000070c087225 */
/* 0x000fc800078e00ff */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0720*/ IADD3 R14, P1, -R8, R0, RZ ; /* 0x00000000080e7210 */
/* 0x000fe20007f3e1ff */
/*0730*/ IMAD R12, R12, R5, R9 ; /* 0x000000050c0c7224 */
/* 0x000fe400078e0209 */
/*0740*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe200078e00ff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe20003f06070 */
/*0760*/ IMAD R10, R10, R7, R12 ; /* 0x000000070a0a7224 */
/* 0x000fc800078e020c */
/*0770*/ IMAD.X R10, R3, 0x1, ~R10, P1 ; /* 0x00000001030a7824 */
/* 0x000fe200008e0e0a */
/*0780*/ IADD3 R8, P1, -R7, R14, RZ ; /* 0x0000000e07087210 */
/* 0x000fc80007f3e1ff */
/*0790*/ ISETP.GE.U32.AND.EX P0, PT, R10, R5, PT, P0 ; /* 0x000000050a00720c */
/* 0x000fe40003f06100 */
/*07a0*/ IADD3.X R12, ~R5, R10, RZ, P1, !PT ; /* 0x0000000a050c7210 */
/* 0x000fe40000ffe5ff */
/*07b0*/ SEL R8, R8, R14, P0 ; /* 0x0000000e08087207 */
/* 0x000fe40000000000 */
/*07c0*/ SEL R12, R12, R10, P0 ; /* 0x0000000a0c0c7207 */
/* 0x000fe40000000000 */
/*07d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06070 */
/*07e0*/ IADD3 R10, P2, -R7, R8, RZ ; /* 0x00000008070a7210 */
/* 0x000fc40007f5e1ff */
/*07f0*/ ISETP.GE.U32.AND.EX P0, PT, R12.reuse, R5, PT, P0 ; /* 0x000000050c00720c */
/* 0x040fe40003f06100 */
/*0800*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25070 */
/*0810*/ IMAD.X R11, R12, 0x1, ~R5, P2 ; /* 0x000000010c0b7824 */
/* 0x000fe200010e0e05 */
/*0820*/ SEL R10, R10, R8, P0 ; /* 0x000000080a0a7207 */
/* 0x000fe20000000000 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0840*/ ISETP.NE.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40003f25310 */
/*0850*/ SEL R11, R11, R12, P0 ; /* 0x0000000c0b0b7207 */
/* 0x000fe40000000000 */
/*0860*/ SEL R10, R10, 0xffffffff, P1 ; /* 0xffffffff0a0a7807 */
/* 0x000fc40000800000 */
/*0870*/ SEL R11, R11, 0xffffffff, P1 ; /* 0xffffffff0b0b7807 */
/* 0x000fe20000800000 */
/*0880*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff77008007950 */
/* 0x000fec0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
cudaMemcpy( h_a, d_a, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .file "tmpxft_0006bc5f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17checkIfValIsPrimey
.type _Z17checkIfValIsPrimey, @function
_Z17checkIfValIsPrimey:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rsi
leaq -1(%rdi), %rax
movl $0, %r9d
cmpq $1, %rax
jbe .L3
movq %rdi, %r9
andl $1, %r9d
je .L3
movq %rdi, %r8
shrq %r8
cmpq $7, %rdi
jbe .L3
movabsq $-6148914691236517205, %rdx
movq %rdi, %rax
mulq %rdx
movq %rdx, %rax
shrq %rax
andq $-2, %rdx
addq %rax, %rdx
movq %rdi, %rax
subq %rdx, %rax
je .L8
movl $3, %ecx
.L5:
addq $2, %rcx
movq %rcx, %rdi
cmpq %r8, %rcx
jnb .L3
movq %rsi, %rax
movl $0, %edx
divq %rdi
testq %rdx, %rdx
jne .L5
movq %rdx, %r9
.L3:
movq %r9, %rax
ret
.L8:
movq %rax, %r9
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z17checkIfValIsPrimey, .-_Z17checkIfValIsPrimey
.globl _Z27__device_stub__Z7isPrimePdyPdy
.type _Z27__device_stub__Z7isPrimePdyPdy, @function
_Z27__device_stub__Z7isPrimePdyPdy:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7isPrimePdy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z7isPrimePdyPdy, .-_Z27__device_stub__Z7isPrimePdyPdy
.globl _Z7isPrimePdy
.type _Z7isPrimePdy, @function
_Z7isPrimePdy:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7isPrimePdyPdy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7isPrimePdy, .-_Z7isPrimePdy
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Usage: prime upbound\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Usage: prime upbound, you input invalid upbound number!\n"
.align 8
.LC3:
.string "Made it past the allocation of memory\n"
.section .rodata.str1.1
.LC4:
.string "Initialize array with 0's\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "In the for block adding up sum\n"
.section .rodata.str1.1
.LC10:
.string "In position %d "
.LC11:
.string "We have %f\n"
.LC12:
.string "Final result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L33
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r12
testq %r13, %r13
je .L34
leaq 0(,%r13,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rax
leaq (%rbx,%rbp), %rdx
.L21:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L21
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rax
addq $1, %rax
js .L22
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L23:
mulss .LC5(%rip), %xmm0
testq %r12, %r12
js .L24
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
.L25:
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC13(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC6(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L26
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC8(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L26:
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L27:
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $0x000000000, %r12d
leaq .LC10(%rip), %r15
leaq .LC11(%rip), %r14
.L28:
movq %r12, %xmm5
addsd 0(%rbp,%rbx,8), %xmm5
movq %xmm5, %r12
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%rbp,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L28
movq %r12, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L23
.L24:
movq %r12, %rax
shrq %rax
movq %r12, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L25
.L35:
movq %r13, %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z7isPrimePdyPdy
jmp .L27
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z7isPrimePdy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7isPrimePdy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1056964608
.align 4
.LC6:
.long 1258291200
.align 4
.LC8:
.long 1065353216
.align 4
.LC13:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
cudaMemcpy( h_a, d_a, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
hipMemcpy( h_a, d_a, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
hipMemcpy( h_a, d_a, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7isPrimePdy
.globl _Z7isPrimePdy
.p2align 8
.type _Z7isPrimePdy,@function
_Z7isPrimePdy:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_13
v_add_co_u32 v3, vcc_lo, v1, -1
v_add_co_ci_u32_e32 v4, vcc_lo, -1, v2, vcc_lo
v_and_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_lt_u64_e32 vcc_lo, 1, v[3:4]
v_mov_b32_e32 v3, 0
v_cmp_eq_u32_e64 s2, 1, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_12
v_mul_hi_u32 v0, v1, 0x55555555
v_cmp_gt_u32_e64 s7, 8, v1
s_mov_b32 s8, 0
s_mov_b64 s[4:5], 5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 1, v0
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -3, v0
v_cmp_lt_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -3, v0
v_cmp_lt_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 7, v1
v_lshrrev_b64 v[3:4], 1, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execnz .LBB0_5
s_branch .LBB0_11
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_add_u32 s4, s4, 2
s_addc_u32 s5, s5, 0
s_and_not1_b32 s3, s11, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_or_b32 s11, s3, s11
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s11
s_or_b32 s8, s3, s8
s_and_not1_b32 s3, s10, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_10
.LBB0_5:
v_cmp_ge_u64_e64 s2, s[4:5], v[3:4]
s_or_b32 s11, s11, exec_lo
s_mov_b32 s12, exec_lo
v_cmpx_lt_u64_e64 s[4:5], v[3:4]
s_cbranch_execz .LBB0_4
v_or_b32_e32 v6, s5, v2
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
s_and_saveexec_b32 s3, vcc_lo
s_xor_b32 s13, exec_lo, s3
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v0, s4
v_cvt_f32_u32_e32 v5, s5
s_sub_u32 s3, 0, s4
s_subb_u32 s14, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v5, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v0
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v5, 0xcf800000, v0
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s3, v5
v_mul_hi_u32 v7, s3, v0
v_mul_lo_u32 v8, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s3, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s3, v0
v_mul_lo_u32 v8, s14, v0
v_mul_lo_u32 v7, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s3, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v11, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, v1, v0
v_mad_u64_u32 v[7:8], null, v2, v0, 0
v_mad_u64_u32 v[5:6], null, v1, v11, 0
v_mad_u64_u32 v[9:10], null, v2, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v12, v5
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v0, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s5, v0
v_mad_u64_u32 v[5:6], null, s4, v0, 0
v_mul_lo_u32 v0, s4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v5, vcc_lo, v1, v5
v_add3_u32 v0, v6, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v2, v0
v_subrev_co_ci_u32_e64 v6, s3, s5, v6, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v2, v0, vcc_lo
v_sub_co_u32 v7, vcc_lo, v5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s3, 0, v6, vcc_lo
v_cmp_le_u32_e64 s3, s4, v5
v_subrev_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
v_cndmask_b32_e64 v9, 0, -1, s3
v_cmp_le_u32_e64 s3, s4, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s3
v_cmp_le_u32_e64 s3, s5, v8
v_cndmask_b32_e64 v11, 0, -1, s3
v_cmp_eq_u32_e64 s3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s4
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v6, v0, v6 :: v_dual_cndmask_b32 v5, v5, v7
.LBB0_8:
s_and_not1_saveexec_b32 s3, s13
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s13, 0, s4
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s13, v0
v_mul_hi_u32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v5
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v5, v0, v5, vcc_lo
s_branch .LBB0_3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s7, s2, s3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
v_cndmask_b32_e64 v0, 0, 1, s7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_u32_e32 v[3:4], v0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7isPrimePdy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7isPrimePdy, .Lfunc_end0-_Z7isPrimePdy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7isPrimePdy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7isPrimePdy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
//return 1 if it is a prime else return 0
//save as main.cu
// CUDA kernel. Each thread takes care of one element of c
__host__ __device__ bignum checkIfValIsPrime(bignum number)
{
if(number ==1) return (bignum) 0;
if (number == 2) return (bignum) 0;
if (number % 2 == 0) return (bignum) 0;
for (long divisor = 3; divisor < (number / 2); divisor += 2)
{
if (number % divisor == 0)
{
return (bignum) 0;
}
}
return (bignum) 1;
}
__global__ void isPrime(double *a, bignum length)
{
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id<length){
a[id] = checkIfValIsPrime((bignum) id);
}
}
int main( int argc, char* argv[] )
{
if(argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum N = (bignum) atoi(argv[1]);
bignum blockSize = (bignum) atoi(argv[2]);
if(N <= 0)
{
printf("Usage: prime upbound, you input invalid upbound number!\n");
exit(-1);
}
// Host input
double *h_a;
// Host output
double *h_c;
// Device input
double *d_a;
// Device output
double *d_c;
// Size, in bytes, of each vector
size_t bytes = N*sizeof(double);
// Allocate memory for vector on host
h_a = (double*)malloc(bytes);
h_c = (double*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_c, bytes);
printf("Made it past the allocation of memory\n");
int i;
// Initialize array with 0's to show that it is empty
printf("Initialize array with 0's\n");
for( i = 0; i < N; i++ ) {
h_a[i] = 0;
}
// Copy host vectors to device
hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
//Number of threads blocks in grid.
int gridSize = (int)ceil((float)(N+1)/2/blockSize);
// Execute the kernel
isPrime<<<gridSize, blockSize>>>(d_a, N);
// Copy array back to host
hipMemcpy( h_a, d_a, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 without error
double sum = 0;
printf("In the for block adding up sum\n");
for(i=0; i<N; i++){
sum += h_a[i];
printf("In position %d ", i);
printf("We have %f\n", h_a[i]);
}
printf("Final result: %f\n", sum);
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_a);
free(h_c);
return 0;
} | .text
.file "main.hip"
.globl _Z17checkIfValIsPrimey # -- Begin function _Z17checkIfValIsPrimey
.p2align 4, 0x90
.type _Z17checkIfValIsPrimey,@function
_Z17checkIfValIsPrimey: # @_Z17checkIfValIsPrimey
.cfi_startproc
# %bb.0:
leaq -1(%rdi), %rcx
xorl %eax, %eax
cmpq $2, %rcx
jb .LBB0_8
# %bb.1:
movl %edi, %ecx
andl $1, %ecx
je .LBB0_8
# %bb.2: # %.preheader
movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB
movq %rdi, %rax
mulq %rcx
cmpq $8, %rdi
setb %cl
jb .LBB0_7
# %bb.3: # %.preheader
shrq %rdx
leaq (%rdx,%rdx,2), %rax
movq %rdi, %rdx
subq %rax, %rdx
je .LBB0_7
# %bb.4: # %.lr.ph21.preheader
movq %rdi, %rsi
shrq %rsi
movl $5, %r8d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %r8
setae %cl
jae .LBB0_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB0_5 Depth=1
movq %rdi, %rax
xorl %edx, %edx
divq %r8
addq $2, %r8
testq %rdx, %rdx
jne .LBB0_5
.LBB0_7: # %._crit_edge
movzbl %cl, %eax
.LBB0_8:
retq
.Lfunc_end0:
.size _Z17checkIfValIsPrimey, .Lfunc_end0-_Z17checkIfValIsPrimey
.cfi_endproc
# -- End function
.globl _Z22__device_stub__isPrimePdy # -- Begin function _Z22__device_stub__isPrimePdy
.p2align 4, 0x90
.type _Z22__device_stub__isPrimePdy,@function
_Z22__device_stub__isPrimePdy: # @_Z22__device_stub__isPrimePdy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7isPrimePdy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__isPrimePdy, .Lfunc_end1-_Z22__device_stub__isPrimePdy
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB2_1
# %bb.3:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %ebx, %ebx
je .LBB2_4
# %bb.5:
movq %rax, %r12
movq %rbx, %r15
shlq $32, %r15
movslq %ebx, %r13
movslq %r12d, %rbp
sarq $29, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl %ebx, %edx
shlq $3, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rax
incq %rax
js .LBB2_6
# %bb.7:
cvtsi2ss %rax, %xmm0
jmp .LBB2_8
.LBB2_6:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB2_8:
mulss .LCPI2_0(%rip), %xmm0
testq %rbp, %rbp
js .LBB2_9
# %bb.10:
cvtsi2ss %r12d, %xmm1
jmp .LBB2_11
.LBB2_9:
shrq %rbp
movl %r12d, %eax
andl $1, %eax
orq %rbp, %rax
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB2_11:
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %r13, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7isPrimePdy, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $1, %ebx
adcl $0, %ebx
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
addsd (%r14,%r15,8), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incq %r15
cmpq %r15, %rbx
jne .LBB2_14
# %bb.15:
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 176
movl $.Lstr.4, %edi
jmp .LBB2_2
.LBB2_4:
movl $.Lstr.3, %edi
.LBB2_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7isPrimePdy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7isPrimePdy,@object # @_Z7isPrimePdy
.section .rodata,"a",@progbits
.globl _Z7isPrimePdy
.p2align 3, 0x0
_Z7isPrimePdy:
.quad _Z22__device_stub__isPrimePdy
.size _Z7isPrimePdy, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "In position %d "
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "We have %f\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Final result: %f\n"
.size .L.str.7, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7isPrimePdy"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Made it past the allocation of memory"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize array with 0's"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "In the for block adding up sum"
.size .Lstr.2, 31
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Usage: prime upbound, you input invalid upbound number!"
.size .Lstr.3, 56
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Usage: prime upbound"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__isPrimePdy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7isPrimePdy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7isPrimePdy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R2, P1, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007f3e0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ LOP3.LUT R4, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100047812 */
/* 0x000fe200078ec0ff */
/*00b0*/ BSSY B0, 0x430 ; /* 0x0000037000007945 */
/* 0x000fe20003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06070 */
/*00d0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00e0*/ IADD3.X R2, R3, -0x1, RZ, P1, !PT ; /* 0xffffffff03027810 */
/* 0x000fe40000ffe4ff */
/*00f0*/ ISETP.NE.U32.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f25070 */
/*0100*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80003f06100 */
/*0110*/ ISETP.NE.U32.OR.EX P0, PT, RZ, RZ, !P0, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0004705510 */
/*0120*/ @P0 BRA 0x420 ; /* 0x000002f000000947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe20003f06070 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff077424 */
/* 0x000fd400078e00ff */
/*0160*/ @!P0 BRA 0x420 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*0170*/ SHF.R.U64 R2, R0, 0x1, R3.reuse ; /* 0x0000000100027819 */
/* 0x100fe20000001203 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fe200078e00ff */
/*0190*/ SHF.R.U32.HI R4, RZ, 0x1, R3 ; /* 0x00000001ff047819 */
/* 0x000fe20000011603 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*01b0*/ LOP3.LUT R6, R3, R5, RZ, 0xfc, !PT ; /* 0x0000000503067212 */
/* 0x000fe200078efcff */
/*01c0*/ BSSY B1, 0x380 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*01e0*/ @!P0 BRA 0x240 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*01f0*/ MOV R6, 0x210 ; /* 0x0000021000067802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0x470 ; /* 0x0000026000007944 */
/* 0x000fea0003c00000 */
/*0210*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f05070 */
/*0220*/ ISETP.NE.AND.EX P0, PT, R11, RZ, PT, P0 ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05300 */
/*0230*/ BRA 0x370 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0240*/ I2F.U32.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209000 */
/*0250*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0260*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0270*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fcc0007ffe0ff */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a09 */
/*02b0*/ IMAD R11, R10, R7, RZ ; /* 0x000000070a0b7224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*02d0*/ IMAD.HI.U32 R9, R9, R0, RZ ; /* 0x0000000009097227 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fca0007ffe1ff */
/*02f0*/ IMAD R10, R7, R9, R0 ; /* 0x00000009070a7224 */
/* 0x000fca00078e0200 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*0310*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fca00078e0a07 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*0330*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fe200078e0a07 */
/*0340*/ @!P1 LOP3.LUT R10, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0a9212 */
/* 0x000fc800078e33ff */
/*0350*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f05070 */
/*0360*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R8, P1, R7, 0x2, RZ ; /* 0x0000000207087810 */
/* 0x000fe40007f3e0ff */
/*0390*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fc6000001ff00 */
/*03a0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*03b0*/ @!P0 BRA 0x420 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0008 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R5, R4, PT, P0 ; /* 0x000000040500720c */
/* 0x000fda0003f06100 */
/*03f0*/ @!P0 BRA 0x1b0 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*0400*/ HFMA2.MMA R7, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff077435 */
/* 0x000fe200000001ff */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fca00078e00ff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ LEA R2, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000027a11 */
/* 0x000fc800078018ff */
/*0440*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1c03 */
/*0450*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0007 */
/*0480*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e0005 */
/*0490*/ I2F.U64.RP R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000e300000309000 */
/*04a0*/ MUFU.RCP R8, R12 ; /* 0x0000000c00087308 */
/* 0x001e240000001000 */
/*04b0*/ IADD3 R8, R8, 0x1ffffffe, RZ ; /* 0x1ffffffe08087810 */
/* 0x001fcc0007ffe0ff */
/*04c0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*04d0*/ IMAD.WIDE.U32 R10, R8, R7, RZ ; /* 0x00000007080a7225 */
/* 0x001fc800078e00ff */
/*04e0*/ IMAD R11, R8, R5, R11 ; /* 0x00000005080b7224 */
/* 0x000fe200078e020b */
/*04f0*/ IADD3 R15, P0, RZ, -R10, RZ ; /* 0x8000000aff0f7210 */
/* 0x000fc60007f1e0ff */
/*0500*/ IMAD R11, R9, R7, R11 ; /* 0x00000007090b7224 */
/* 0x000fe400078e020b */
/*0510*/ IMAD.HI.U32 R10, R8, R15, RZ ; /* 0x0000000f080a7227 */
/* 0x000fc800078e00ff */
/*0520*/ IMAD.X R17, RZ, RZ, ~R11, P0 ; /* 0x000000ffff117224 */
/* 0x000fe400000e0e0b */
/*0530*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0540*/ IMAD R13, R9, R17.reuse, RZ ; /* 0x00000011090d7224 */
/* 0x080fe400078e02ff */
/*0550*/ IMAD.WIDE.U32 R10, P0, R8, R17, R10 ; /* 0x00000011080a7225 */
/* 0x000fc8000780000a */
/*0560*/ IMAD.HI.U32 R17, R9, R17, RZ ; /* 0x0000001109117227 */
/* 0x000fc800078e00ff */
/*0570*/ IMAD.HI.U32 R10, P1, R9, R15, R10 ; /* 0x0000000f090a7227 */
/* 0x000fca000782000a */
/*0580*/ IADD3 R11, P2, R13, R10, RZ ; /* 0x0000000a0d0b7210 */
/* 0x000fe20007f5e0ff */
/*0590*/ IMAD.X R10, R17, 0x1, R9, P0 ; /* 0x00000001110a7824 */
/* 0x000fc800000e0609 */
/*05a0*/ IMAD.WIDE.U32 R8, R11, R7, RZ ; /* 0x000000070b087225 */
/* 0x000fe200078e00ff */
/*05b0*/ IADD3.X R12, RZ, RZ, R10, P2, P1 ; /* 0x000000ffff0c7210 */
/* 0x000fc600017e240a */
/*05c0*/ IMAD R9, R11, R5, R9 ; /* 0x000000050b097224 */
/* 0x000fe200078e0209 */
/*05d0*/ IADD3 R13, P0, RZ, -R8, RZ ; /* 0x80000008ff0d7210 */
/* 0x000fc60007f1e0ff */
/*05e0*/ IMAD R9, R12, R7, R9 ; /* 0x000000070c097224 */
/* 0x000fe400078e0209 */
/*05f0*/ IMAD.HI.U32 R10, R11, R13, RZ ; /* 0x0000000d0b0a7227 */
/* 0x000fc600078e00ff */
/*0600*/ IADD3.X R9, RZ, ~R9, RZ, P0, !PT ; /* 0x80000009ff097210 */
/* 0x000fca00007fe4ff */
/*0610*/ IMAD.WIDE.U32 R10, P0, R11, R9, R10 ; /* 0x000000090b0a7225 */
/* 0x000fc8000780000a */
/*0620*/ IMAD R8, R12.reuse, R9, RZ ; /* 0x000000090c087224 */
/* 0x040fe400078e02ff */
/*0630*/ IMAD.HI.U32 R11, P1, R12, R13, R10 ; /* 0x0000000d0c0b7227 */
/* 0x000fc8000782000a */
/*0640*/ IMAD.HI.U32 R9, R12, R9, RZ ; /* 0x000000090c097227 */
/* 0x000fe200078e00ff */
/*0650*/ IADD3 R11, P2, R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x000fc60007f5e0ff */
/*0660*/ IMAD.X R12, R9, 0x1, R12, P0 ; /* 0x00000001090c7824 */
/* 0x000fe400000e060c */
/*0670*/ IMAD.HI.U32 R8, R11, R0, RZ ; /* 0x000000000b087227 */
/* 0x000fc600078e00ff */
/*0680*/ IADD3.X R12, RZ, RZ, R12, P2, P1 ; /* 0x000000ffff0c7210 */
/* 0x000fe200017e240c */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE.U32 R8, R11, R3, R8 ; /* 0x000000030b087225 */
/* 0x000fc800078e0008 */
/*06b0*/ IMAD R11, R12.reuse, R3, RZ ; /* 0x000000030c0b7224 */
/* 0x040fe400078e02ff */
/*06c0*/ IMAD.HI.U32 R8, P0, R12, R0, R8 ; /* 0x000000000c087227 */
/* 0x000fc80007800008 */
/*06d0*/ IMAD.HI.U32 R10, R12, R3, RZ ; /* 0x000000030c0a7227 */
/* 0x000fe200078e00ff */
/*06e0*/ IADD3 R12, P1, R11, R8, RZ ; /* 0x000000080b0c7210 */
/* 0x000fc60007f3e0ff */
/*06f0*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400000e060a */
/*0700*/ IMAD.WIDE.U32 R8, R12, R7, RZ ; /* 0x000000070c087225 */
/* 0x000fc800078e00ff */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0720*/ IADD3 R14, P1, -R8, R0, RZ ; /* 0x00000000080e7210 */
/* 0x000fe20007f3e1ff */
/*0730*/ IMAD R12, R12, R5, R9 ; /* 0x000000050c0c7224 */
/* 0x000fe400078e0209 */
/*0740*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fe200078e00ff */
/*0750*/ ISETP.GE.U32.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe20003f06070 */
/*0760*/ IMAD R10, R10, R7, R12 ; /* 0x000000070a0a7224 */
/* 0x000fc800078e020c */
/*0770*/ IMAD.X R10, R3, 0x1, ~R10, P1 ; /* 0x00000001030a7824 */
/* 0x000fe200008e0e0a */
/*0780*/ IADD3 R8, P1, -R7, R14, RZ ; /* 0x0000000e07087210 */
/* 0x000fc80007f3e1ff */
/*0790*/ ISETP.GE.U32.AND.EX P0, PT, R10, R5, PT, P0 ; /* 0x000000050a00720c */
/* 0x000fe40003f06100 */
/*07a0*/ IADD3.X R12, ~R5, R10, RZ, P1, !PT ; /* 0x0000000a050c7210 */
/* 0x000fe40000ffe5ff */
/*07b0*/ SEL R8, R8, R14, P0 ; /* 0x0000000e08087207 */
/* 0x000fe40000000000 */
/*07c0*/ SEL R12, R12, R10, P0 ; /* 0x0000000a0c0c7207 */
/* 0x000fe40000000000 */
/*07d0*/ ISETP.GE.U32.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06070 */
/*07e0*/ IADD3 R10, P2, -R7, R8, RZ ; /* 0x00000008070a7210 */
/* 0x000fc40007f5e1ff */
/*07f0*/ ISETP.GE.U32.AND.EX P0, PT, R12.reuse, R5, PT, P0 ; /* 0x000000050c00720c */
/* 0x040fe40003f06100 */
/*0800*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25070 */
/*0810*/ IMAD.X R11, R12, 0x1, ~R5, P2 ; /* 0x000000010c0b7824 */
/* 0x000fe200010e0e05 */
/*0820*/ SEL R10, R10, R8, P0 ; /* 0x000000080a0a7207 */
/* 0x000fe20000000000 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0840*/ ISETP.NE.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40003f25310 */
/*0850*/ SEL R11, R11, R12, P0 ; /* 0x0000000c0b0b7207 */
/* 0x000fe40000000000 */
/*0860*/ SEL R10, R10, 0xffffffff, P1 ; /* 0xffffffff0a0a7807 */
/* 0x000fc40000800000 */
/*0870*/ SEL R11, R11, 0xffffffff, P1 ; /* 0xffffffff0b0b7807 */
/* 0x000fe20000800000 */
/*0880*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff77008007950 */
/* 0x000fec0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7isPrimePdy
.globl _Z7isPrimePdy
.p2align 8
.type _Z7isPrimePdy,@function
_Z7isPrimePdy:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_13
v_add_co_u32 v3, vcc_lo, v1, -1
v_add_co_ci_u32_e32 v4, vcc_lo, -1, v2, vcc_lo
v_and_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_lt_u64_e32 vcc_lo, 1, v[3:4]
v_mov_b32_e32 v3, 0
v_cmp_eq_u32_e64 s2, 1, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_12
v_mul_hi_u32 v0, v1, 0x55555555
v_cmp_gt_u32_e64 s7, 8, v1
s_mov_b32 s8, 0
s_mov_b64 s[4:5], 5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 1, v0
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -3, v0
v_cmp_lt_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -3, v0
v_cmp_lt_u32_e32 vcc_lo, 2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 7, v1
v_lshrrev_b64 v[3:4], 1, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execnz .LBB0_5
s_branch .LBB0_11
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[5:6]
s_add_u32 s4, s4, 2
s_addc_u32 s5, s5, 0
s_and_not1_b32 s3, s11, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_or_b32 s11, s3, s11
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s11
s_or_b32 s8, s3, s8
s_and_not1_b32 s3, s10, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_10
.LBB0_5:
v_cmp_ge_u64_e64 s2, s[4:5], v[3:4]
s_or_b32 s11, s11, exec_lo
s_mov_b32 s12, exec_lo
v_cmpx_lt_u64_e64 s[4:5], v[3:4]
s_cbranch_execz .LBB0_4
v_or_b32_e32 v6, s5, v2
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[5:6]
s_and_saveexec_b32 s3, vcc_lo
s_xor_b32 s13, exec_lo, s3
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v0, s4
v_cvt_f32_u32_e32 v5, s5
s_sub_u32 s3, 0, s4
s_subb_u32 s14, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v5, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v0
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v5, 0xcf800000, v0
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s3, v5
v_mul_hi_u32 v7, s3, v0
v_mul_lo_u32 v8, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s3, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s3, v0
v_mul_lo_u32 v8, s14, v0
v_mul_lo_u32 v7, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s3, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v11, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v12, v1, v0
v_mad_u64_u32 v[7:8], null, v2, v0, 0
v_mad_u64_u32 v[5:6], null, v1, v11, 0
v_mad_u64_u32 v[9:10], null, v2, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v12, v5
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v0, vcc_lo, v5, v8, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s5, v0
v_mad_u64_u32 v[5:6], null, s4, v0, 0
v_mul_lo_u32 v0, s4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v5, vcc_lo, v1, v5
v_add3_u32 v0, v6, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v2, v0
v_subrev_co_ci_u32_e64 v6, s3, s5, v6, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v2, v0, vcc_lo
v_sub_co_u32 v7, vcc_lo, v5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s3, 0, v6, vcc_lo
v_cmp_le_u32_e64 s3, s4, v5
v_subrev_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
v_cndmask_b32_e64 v9, 0, -1, s3
v_cmp_le_u32_e64 s3, s4, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s3
v_cmp_le_u32_e64 s3, s5, v8
v_cndmask_b32_e64 v11, 0, -1, s3
v_cmp_eq_u32_e64 s3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s4
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v6, v0, v6 :: v_dual_cndmask_b32 v5, v5, v7
.LBB0_8:
s_and_not1_saveexec_b32 s3, s13
s_cbranch_execz .LBB0_3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s13, 0, s4
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s13, v0
v_mul_hi_u32 v5, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v5
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v5, v0, v5, vcc_lo
s_branch .LBB0_3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s7, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s7, s2, s3
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
v_cndmask_b32_e64 v0, 0, 1, s7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_u32_e32 v[3:4], v0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7isPrimePdy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7isPrimePdy, .Lfunc_end0-_Z7isPrimePdy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7isPrimePdy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7isPrimePdy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006bc5f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17checkIfValIsPrimey
.type _Z17checkIfValIsPrimey, @function
_Z17checkIfValIsPrimey:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rsi
leaq -1(%rdi), %rax
movl $0, %r9d
cmpq $1, %rax
jbe .L3
movq %rdi, %r9
andl $1, %r9d
je .L3
movq %rdi, %r8
shrq %r8
cmpq $7, %rdi
jbe .L3
movabsq $-6148914691236517205, %rdx
movq %rdi, %rax
mulq %rdx
movq %rdx, %rax
shrq %rax
andq $-2, %rdx
addq %rax, %rdx
movq %rdi, %rax
subq %rdx, %rax
je .L8
movl $3, %ecx
.L5:
addq $2, %rcx
movq %rcx, %rdi
cmpq %r8, %rcx
jnb .L3
movq %rsi, %rax
movl $0, %edx
divq %rdi
testq %rdx, %rdx
jne .L5
movq %rdx, %r9
.L3:
movq %r9, %rax
ret
.L8:
movq %rax, %r9
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z17checkIfValIsPrimey, .-_Z17checkIfValIsPrimey
.globl _Z27__device_stub__Z7isPrimePdyPdy
.type _Z27__device_stub__Z7isPrimePdyPdy, @function
_Z27__device_stub__Z7isPrimePdyPdy:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7isPrimePdy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z7isPrimePdyPdy, .-_Z27__device_stub__Z7isPrimePdyPdy
.globl _Z7isPrimePdy
.type _Z7isPrimePdy, @function
_Z7isPrimePdy:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7isPrimePdyPdy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7isPrimePdy, .-_Z7isPrimePdy
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Usage: prime upbound\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Usage: prime upbound, you input invalid upbound number!\n"
.align 8
.LC3:
.string "Made it past the allocation of memory\n"
.section .rodata.str1.1
.LC4:
.string "Initialize array with 0's\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "In the for block adding up sum\n"
.section .rodata.str1.1
.LC10:
.string "In position %d "
.LC11:
.string "We have %f\n"
.LC12:
.string "Final result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L33
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r12
testq %r13, %r13
je .L34
leaq 0(,%r13,8), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rax
leaq (%rbx,%rbp), %rdx
.L21:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L21
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rax
addq $1, %rax
js .L22
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L23:
mulss .LC5(%rip), %xmm0
testq %r12, %r12
js .L24
pxor %xmm1, %xmm1
cvtsi2ssq %r12, %xmm1
.L25:
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC13(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC6(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L26
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC8(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L26:
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L27:
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movl $0x000000000, %r12d
leaq .LC10(%rip), %r15
leaq .LC11(%rip), %r14
.L28:
movq %r12, %xmm5
addsd 0(%rbp,%rbx,8), %xmm5
movq %xmm5, %r12
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%rbp,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L28
movq %r12, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L23
.L24:
movq %r12, %rax
shrq %rax
movq %r12, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L25
.L35:
movq %r13, %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z7isPrimePdyPdy
jmp .L27
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z7isPrimePdy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7isPrimePdy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1056964608
.align 4
.LC6:
.long 1258291200
.align 4
.LC8:
.long 1065353216
.align 4
.LC13:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z17checkIfValIsPrimey # -- Begin function _Z17checkIfValIsPrimey
.p2align 4, 0x90
.type _Z17checkIfValIsPrimey,@function
_Z17checkIfValIsPrimey: # @_Z17checkIfValIsPrimey
.cfi_startproc
# %bb.0:
leaq -1(%rdi), %rcx
xorl %eax, %eax
cmpq $2, %rcx
jb .LBB0_8
# %bb.1:
movl %edi, %ecx
andl $1, %ecx
je .LBB0_8
# %bb.2: # %.preheader
movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB
movq %rdi, %rax
mulq %rcx
cmpq $8, %rdi
setb %cl
jb .LBB0_7
# %bb.3: # %.preheader
shrq %rdx
leaq (%rdx,%rdx,2), %rax
movq %rdi, %rdx
subq %rax, %rdx
je .LBB0_7
# %bb.4: # %.lr.ph21.preheader
movq %rdi, %rsi
shrq %rsi
movl $5, %r8d
.p2align 4, 0x90
.LBB0_5: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %r8
setae %cl
jae .LBB0_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB0_5 Depth=1
movq %rdi, %rax
xorl %edx, %edx
divq %r8
addq $2, %r8
testq %rdx, %rdx
jne .LBB0_5
.LBB0_7: # %._crit_edge
movzbl %cl, %eax
.LBB0_8:
retq
.Lfunc_end0:
.size _Z17checkIfValIsPrimey, .Lfunc_end0-_Z17checkIfValIsPrimey
.cfi_endproc
# -- End function
.globl _Z22__device_stub__isPrimePdy # -- Begin function _Z22__device_stub__isPrimePdy
.p2align 4, 0x90
.type _Z22__device_stub__isPrimePdy,@function
_Z22__device_stub__isPrimePdy: # @_Z22__device_stub__isPrimePdy
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7isPrimePdy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__isPrimePdy, .Lfunc_end1-_Z22__device_stub__isPrimePdy
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB2_1
# %bb.3:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %ebx, %ebx
je .LBB2_4
# %bb.5:
movq %rax, %r12
movq %rbx, %r15
shlq $32, %r15
movslq %ebx, %r13
movslq %r12d, %rbp
sarq $29, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl %ebx, %edx
shlq $3, %rdx
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r13, %rax
incq %rax
js .LBB2_6
# %bb.7:
cvtsi2ss %rax, %xmm0
jmp .LBB2_8
.LBB2_6:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB2_8:
mulss .LCPI2_0(%rip), %xmm0
testq %rbp, %rbp
js .LBB2_9
# %bb.10:
cvtsi2ss %r12d, %xmm1
jmp .LBB2_11
.LBB2_9:
shrq %rbp
movl %r12d, %eax
andl $1, %eax
orq %rbp, %rax
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB2_11:
divss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %r13, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7isPrimePdy, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
cmpl $1, %ebx
adcl $0, %ebx
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
addsd (%r14,%r15,8), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
incq %r15
cmpq %r15, %rbx
jne .LBB2_14
# %bb.15:
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 176
movl $.Lstr.4, %edi
jmp .LBB2_2
.LBB2_4:
movl $.Lstr.3, %edi
.LBB2_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7isPrimePdy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7isPrimePdy,@object # @_Z7isPrimePdy
.section .rodata,"a",@progbits
.globl _Z7isPrimePdy
.p2align 3, 0x0
_Z7isPrimePdy:
.quad _Z22__device_stub__isPrimePdy
.size _Z7isPrimePdy, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "In position %d "
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "We have %f\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Final result: %f\n"
.size .L.str.7, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7isPrimePdy"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Made it past the allocation of memory"
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize array with 0's"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "In the for block adding up sum"
.size .Lstr.2, 31
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Usage: prime upbound, you input invalid upbound number!"
.size .Lstr.3, 56
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Usage: prime upbound"
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__isPrimePdy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7isPrimePdy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
cudaFree(d_str);
printf("%s\n", str);
return 0;
} | code for sm_80
Function : _Z10helloWorldPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
cudaFree(d_str);
printf("%s\n", str);
return 0;
} | .file "tmpxft_0003efc0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10helloWorldPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl _Z10helloWorldPc
.type _Z10helloWorldPc, @function
_Z10helloWorldPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldPc, .-_Z10helloWorldPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.LC1:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movabsq $478560413000, %rax
movq %rax, 47(%rsp)
movl $0, 55(%rsp)
movabsq $8022916924116329800, %rax
movq %rax, 59(%rsp)
movabsq $9399091170596640, %rax
movq %rax, 64(%rsp)
leaq 47(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 59(%rsp), %rdx
movl $0, %eax
.L12:
subb %al, (%rdx)
addl $1, %eax
addq $1, %rdx
cmpl $12, %eax
jne .L12
leaq 59(%rsp), %rbx
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $13, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $13, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $6, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 59(%rsp), %rbx
movl $2, %ecx
movl $13, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10helloWorldPcPc
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10helloWorldPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <cuda.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
cudaFree(d_str);
printf("%s\n", str);
return 0;
} | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <hip/hip_runtime.h>
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
hipFree(d_str);
printf("%s\n", str);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <hip/hip_runtime.h>
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
hipFree(d_str);
printf("%s\n", str);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10helloWorldPc
.globl _Z10helloWorldPc
.p2align 8
.type _Z10helloWorldPc,@function
_Z10helloWorldPc:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v0, 31, v1
v_add_co_u32 v2, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, v1
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10helloWorldPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10helloWorldPc, .Lfunc_end0-_Z10helloWorldPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10helloWorldPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10helloWorldPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <hip/hip_runtime.h>
//2015253039 ±ÇÁø¿ì
__global__ void helloWorld(char* str) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
str[idx] += idx;
}
int main(int argc, char** argv)
{
int i;
char strin[12] = "Hello";
char str[] = "Hello World!";
printf("%s", strin);
for (i = 0; i < 12; i++)
{
str[i] -= i;
}
printf("%s\n", str);
char* d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
dim3 dimBlock(2);
dim3 dimThread(6);
helloWorld<<< dimBlock, dimThread >>>(d_str);
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
hipFree(d_str);
printf("%s\n", str);
return 0;
} | .text
.file "kernel.hip"
.globl _Z25__device_stub__helloWorldPc # -- Begin function _Z25__device_stub__helloWorldPc
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldPc,@function
_Z25__device_stub__helloWorldPc: # @_Z25__device_stub__helloWorldPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10helloWorldPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldPc, .Lfunc_end0-_Z25__device_stub__helloWorldPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $1819043144, 36(%rsp) # imm = 0x6C6C6548
movb $111, 40(%rsp)
movl $0, 41(%rsp)
movl $0, 44(%rsp)
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
movq %rax, 23(%rsp)
movl $560229490, 31(%rsp) # imm = 0x21646C72
movb $0, 35(%rsp)
xorl %ebx, %ebx
leaq 36(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 23(%rsp), %rax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%rax), %ecx
addl %ebx, %ecx
movb %cl, (%rax)
decq %rbx
incq %rax
cmpq $-12, %rbx
jne .LBB1_1
# %bb.2:
leaq 23(%rsp), %rbx
movq %rbx, %rdi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $13, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $13, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldPc, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 23(%rsp), %rbx
movl $13, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldPc,@object # @_Z10helloWorldPc
.section .rodata,"a",@progbits
.globl _Z10helloWorldPc
.p2align 3, 0x0
_Z10helloWorldPc:
.quad _Z25__device_stub__helloWorldPc
.size _Z10helloWorldPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10helloWorldPc"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10helloWorldPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10helloWorldPc
.globl _Z10helloWorldPc
.p2align 8
.type _Z10helloWorldPc,@function
_Z10helloWorldPc:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v0, 31, v1
v_add_co_u32 v2, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, v1
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10helloWorldPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10helloWorldPc, .Lfunc_end0-_Z10helloWorldPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10helloWorldPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10helloWorldPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003efc0_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10helloWorldPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl _Z10helloWorldPc
.type _Z10helloWorldPc, @function
_Z10helloWorldPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldPc, .-_Z10helloWorldPc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s"
.LC1:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movabsq $478560413000, %rax
movq %rax, 47(%rsp)
movl $0, 55(%rsp)
movabsq $8022916924116329800, %rax
movq %rax, 59(%rsp)
movabsq $9399091170596640, %rax
movq %rax, 64(%rsp)
leaq 47(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 59(%rsp), %rdx
movl $0, %eax
.L12:
subb %al, (%rdx)
addl $1, %eax
addq $1, %rdx
cmpl $12, %eax
jne .L12
leaq 59(%rsp), %rbx
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $13, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $13, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $6, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 59(%rsp), %rbx
movl $2, %ecx
movl $13, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10helloWorldPcPc
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10helloWorldPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z25__device_stub__helloWorldPc # -- Begin function _Z25__device_stub__helloWorldPc
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldPc,@function
_Z25__device_stub__helloWorldPc: # @_Z25__device_stub__helloWorldPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10helloWorldPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldPc, .Lfunc_end0-_Z25__device_stub__helloWorldPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $1819043144, 36(%rsp) # imm = 0x6C6C6548
movb $111, 40(%rsp)
movl $0, 41(%rsp)
movl $0, 44(%rsp)
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
movq %rax, 23(%rsp)
movl $560229490, 31(%rsp) # imm = 0x21646C72
movb $0, 35(%rsp)
xorl %ebx, %ebx
leaq 36(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 23(%rsp), %rax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%rax), %ecx
addl %ebx, %ecx
movb %cl, (%rax)
decq %rbx
incq %rax
cmpq $-12, %rbx
jne .LBB1_1
# %bb.2:
leaq 23(%rsp), %rbx
movq %rbx, %rdi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $13, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $13, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldPc, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 23(%rsp), %rbx
movl $13, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldPc,@object # @_Z10helloWorldPc
.section .rodata,"a",@progbits
.globl _Z10helloWorldPc
.p2align 3, 0x0
_Z10helloWorldPc:
.quad _Z25__device_stub__helloWorldPc
.size _Z10helloWorldPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10helloWorldPc"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 256
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
cudaMallocManaged(&ha,numBytes);
cudaMallocManaged(&hb,numBytes);
cudaMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
cudaDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
cudaFreeHost(ha); cudaFreeHost(hb); cudaFreeHost(hc);
} | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 256
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
cudaMallocManaged(&ha,numBytes);
cudaMallocManaged(&hb,numBytes);
cudaMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
cudaDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
cudaFreeHost(ha); cudaFreeHost(hb); cudaFreeHost(hc);
} | .file "tmpxft_001137a2_00000000-6_vecAddManagedKaboom.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "invalid managed memory reference: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c[%d]: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L12
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $4, %ebp
movl $1, %ebx
leaq .LC1(%rip), %r12
.L14:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $256, %ebx
jne .L14
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 256
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
cudaMallocManaged(&ha,numBytes);
cudaMallocManaged(&hb,numBytes);
cudaMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
cudaDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
cudaFreeHost(ha); cudaFreeHost(hb); cudaFreeHost(hc);
} | #define N 256
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
hipMallocManaged(&ha,numBytes);
hipMallocManaged(&hb,numBytes);
hipMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
hipDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
hipHostFree(ha); hipHostFree(hb); hipHostFree(hc);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define N 256
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
hipMallocManaged(&ha,numBytes);
hipMallocManaged(&hb,numBytes);
hipMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
hipDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
hipHostFree(ha); hipHostFree(hb); hipHostFree(hc);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define N 256
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void vecAdd(float *a, float *b, float *c){
c[threadIdx.x] = a[threadIdx.x]+b[threadIdx.x];
}
int main(void){
// number of bytes to alloc for arrays
size_t numBytes = N*sizeof(float);
// init host and device pointers
float *ha, *hb, *hc;
// alloc host memory/arrays
hipMallocManaged(&ha,numBytes);
hipMallocManaged(&hb,numBytes);
hipMallocManaged(&hc,numBytes);
// init host arrays
for(int i=0; i<N; i++){ ha[i]=(float)i; hb[i]=(float)i; }
// launch configuration
dim3 gridSz(1,1,1), blockSz(N,1,1);
// launch CUDA kernel
vecAdd<<<gridSz,blockSz>>>(ha,hb,hc);
printf("invalid managed memory reference: %f\n",ha[0]);
// wait for kernel to finish
hipDeviceSynchronize();
// kernel result (no memcpy!)
for (int i=1; i<N; i++){ printf("c[%d]: %f\n",i,hc[i]);}
// free host memory
hipHostFree(ha); hipHostFree(hb); hipHostFree(hc);
} | .text
.file "vecAddManagedKaboom.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movl $1, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 8(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "invalid managed memory reference: %f\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c[%d]: %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001137a2_00000000-6_vecAddManagedKaboom.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "invalid managed memory reference: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c[%d]: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1024, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L12
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $4, %ebp
movl $1, %ebx
leaq .LC1(%rip), %r12
.L14:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $256, %ebx
jne .L14
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAddManagedKaboom.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rax,%rcx,4)
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movl $1, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipHostFree
movq 16(%rsp), %rdi
callq hipHostFree
movq 8(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "invalid managed memory reference: %f\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c[%d]: %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} | .file "tmpxft_00044730_00000000-6_density.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7densitydddddd
.type _Z7densitydddddd, @function
_Z7densitydddddd:
.LFB3857:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3857:
.size _Z7densitydddddd, .-_Z7densitydddddd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3883:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>
#define PI 3.14159265358979323846
__device__ double density(double Xold, double Xnew, double sigma, double r, double delta, double delta_t){
double f=0, x=0;
//x=(1/(sigma*sqrt(delta_t)))*(log(Xnew)-log(Xold)-(r-delta-0.5*sigma*sigma)*delta_t);
x=(1/(sigma*sqrt(delta_t)))*(Xnew-Xold-(r-delta-0.5*sigma*sigma)*delta_t);
//f= (1/(sigma*sqrt(delta_t)*Xnew))*(1/(sqrt(2*PI)))*exp(-0.5*x*x); // this is the transition density
f= (1/(sigma*sqrt(delta_t)))*(1/(sqrt(2*PI)))*exp(-0.5*x*x);
return f;
} | .text
.file "density.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00044730_00000000-6_density.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3860:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3860:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7densitydddddd
.type _Z7densitydddddd, @function
_Z7densitydddddd:
.LFB3857:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3857:
.size _Z7densitydddddd, .-_Z7densitydddddd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3883:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3883:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "density.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <cuda.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
cudaMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
CUevent event;
cuEventCreate(&event, CU_EVENT_DISABLE_TIMING);
CUstream stream;
cuStreamCreate(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
cuEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
cuEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
cuStreamDestroy(stream);
cuEventDestroy(event);
cudaFree(gpufloats);
cout << "finished" << endl;
return 0;
} | code for sm_80
Function : _Z10longKernelPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x830 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*00f0*/ @!P0 BRA 0x6f0 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0110*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0120*/ @!P1 BRA 0x4c0 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0140*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000808020e7981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000408020c7981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180802167981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R6, [R2.64+0x3c] ; /* 0x00003c0802067981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0802107981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100802127981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R2.64+0x14] ; /* 0x0000140802147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R23, [R2.64+0x1c] ; /* 0x00001c0802177981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R24, [R2.64+0x20] ; /* 0x0000200802187981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R26, [R2.64+0x24] ; /* 0x00002408021a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R10, [R2.64+0x28] ; /* 0x00002808020a7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0802097981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R5, [R2.64+0x30] ; /* 0x0000300802057981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340802087981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R7, [R2.64+0x38] ; /* 0x0000380802077981 */
/* 0x000f62000c1e1900 */
/*0240*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0250*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0260*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0270*/ FADD R11, R11, c[0x0][0x16c] ; /* 0x00005b000b0b7621 */
/* 0x004fe40000000000 */
/*0280*/ FADD R15, R14, c[0x0][0x16c] ; /* 0x00005b000e0f7621 */
/* 0x008fc60000000000 */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000be2000c101908 */
/*02a0*/ FADD R13, R12, c[0x0][0x16c] ; /* 0x00005b000c0d7621 */
/* 0x010fc60000000000 */
/*02b0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0001e8000c101908 */
/*02c0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0003e2000c101908 */
/*02d0*/ FADD R11, R22, c[0x0][0x16c] ; /* 0x00005b00160b7621 */
/* 0x020fe40000000000 */
/*02e0*/ FADD R17, R16, c[0x0][0x16c] ; /* 0x00005b0010117621 */
/* 0x000fe40000000000 */
/*02f0*/ FADD R15, R6, c[0x0][0x16c] ; /* 0x00005b00060f7621 */
/* 0x001fe20000000000 */
/*0300*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe20007f5e0ff */
/*0310*/ FADD R19, R18, c[0x0][0x16c] ; /* 0x00005b0012137621 */
/* 0x000fe20000000000 */
/*0320*/ STG.E [R2.64+0x18], R11 ; /* 0x0000180b02007986 */
/* 0x0001e2000c101908 */
/*0330*/ FADD R21, R20, c[0x0][0x16c] ; /* 0x00005b0014157621 */
/* 0x000fc40000000000 */
/*0340*/ FADD R23, R23, c[0x0][0x16c] ; /* 0x00005b0017177621 */
/* 0x000fe40000000000 */
/*0350*/ FADD R25, R24, c[0x0][0x16c] ; /* 0x00005b0018197621 */
/* 0x000fe40000000000 */
/*0360*/ FADD R27, R26, c[0x0][0x16c] ; /* 0x00005b001a1b7621 */
/* 0x000fe40000000000 */
/*0370*/ FADD R29, R10, c[0x0][0x16c] ; /* 0x00005b000a1d7621 */
/* 0x000fe40000000000 */
/*0380*/ FADD R9, R9, c[0x0][0x16c] ; /* 0x00005b0009097621 */
/* 0x000fe40000000000 */
/*0390*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x000fc40000000000 */
/*03a0*/ FADD R13, R8, c[0x0][0x16c] ; /* 0x00005b00080d7621 */
/* 0x002fe40000000000 */
/*03b0*/ FADD R7, R7, c[0x0][0x16c] ; /* 0x00005b0007077621 */
/* 0x000fe20000000000 */
/*03c0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200017fe4ff */
/*03d0*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe8000c101908 */
/*03e0*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe8000c101908 */
/*03f0*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x000fe8000c101908 */
/*0400*/ STG.E [R2.64+0x1c], R23 ; /* 0x00001c1702007986 */
/* 0x000fe8000c101908 */
/*0410*/ STG.E [R2.64+0x20], R25 ; /* 0x0000201902007986 */
/* 0x000fe8000c101908 */
/*0420*/ STG.E [R2.64+0x24], R27 ; /* 0x0000241b02007986 */
/* 0x000fe8000c101908 */
/*0430*/ STG.E [R2.64+0x28], R29 ; /* 0x0000281d02007986 */
/* 0x000fe8000c101908 */
/*0440*/ STG.E [R2.64+0x2c], R9 ; /* 0x00002c0902007986 */
/* 0x000fe8000c101908 */
/*0450*/ STG.E [R2.64+0x30], R5 ; /* 0x0000300502007986 */
/* 0x000fe8000c101908 */
/*0460*/ STG.E [R2.64+0x34], R13 ; /* 0x0000340d02007986 */
/* 0x000fe8000c101908 */
/*0470*/ STG.E [R2.64+0x38], R7 ; /* 0x0000380702007986 */
/* 0x000fe8000c101908 */
/*0480*/ STG.E [R2.64+0x3c], R15 ; /* 0x00003c0f02007986 */
/* 0x0001e4000c101908 */
/*0490*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0006 */
/*04a0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*04b0*/ @P1 BRA 0x140 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x6d0 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080802087981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c08020a7981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001008020c7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001408020e7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R16, [R2.64+0x18] ; /* 0x0000180802107981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R18, [R2.64+0x1c] ; /* 0x00001c0802127981 */
/* 0x000f62000c1e1900 */
/*0560*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0570*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0590*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x004fc40000000000 */
/*05a0*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x008fc60000000000 */
/*05b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101908 */
/*05c0*/ FADD R9, R8, c[0x0][0x16c] ; /* 0x00005b0008097621 */
/* 0x010fc60000000000 */
/*05d0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101908 */
/*05e0*/ FADD R11, R10, c[0x0][0x16c] ; /* 0x00005b000a0b7621 */
/* 0x020fc60000000000 */
/*05f0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101908 */
/*0600*/ FADD R13, R12, c[0x0][0x16c] ; /* 0x00005b000c0d7621 */
/* 0x000fe20000000000 */
/*0610*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x001fe40007f3e0ff */
/*0620*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101908 */
/*0630*/ FADD R15, R14, c[0x0][0x16c] ; /* 0x00005b000e0f7621 */
/* 0x000fe40000000000 */
/*0640*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0650*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101908 */
/*0660*/ FADD R17, R16, c[0x0][0x16c] ; /* 0x00005b0010117621 */
/* 0x000fc60000000000 */
/*0670*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe2000c101908 */
/*0680*/ FADD R19, R18, c[0x0][0x16c] ; /* 0x00005b0012137621 */
/* 0x000fc60000000000 */
/*0690*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101908 */
/*06a0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0001e4000c101908 */
/*06b0*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x001fe20000000f00 */
/*06c0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*06d0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*06e0*/ @!P0 BRA 0x830 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*06f0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080802087981 */
/* 0x000f28000c1e1900 */
/*0720*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c08020a7981 */
/* 0x000f62000c1e1900 */
/*0730*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0750*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0760*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x004fe20000000000 */
/*0770*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe20007f3e0ff */
/*0780*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x008fc60000000000 */
/*0790*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe20000ffe4ff */
/*07a0*/ FADD R9, R8, c[0x0][0x16c] ; /* 0x00005b0008097621 */
/* 0x010fe40000000000 */
/*07b0*/ FADD R11, R10, c[0x0][0x16c] ; /* 0x00005b000a0b7621 */
/* 0x020fe20000000000 */
/*07c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101908 */
/*07d0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101908 */
/*07e0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101908 */
/*07f0*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x0001e4000c101908 */
/*0800*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0820*/ @P0 BRA 0x6f0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0840*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0850*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0860*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0870*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0880*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*08a0*/ MOV R3, UR5 ; /* 0x0000000500037c02 */
/* 0x000fe40008000f00 */
/*08b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe40008000f00 */
/*08c0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fca0000000f00 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*08e0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fca0000000f00 */
/*08f0*/ LDG.E R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0920*/ FADD R5, R4, c[0x0][0x16c] ; /* 0x00005b0004057621 */
/* 0x004fe20000000000 */
/*0930*/ IADD3 R4, P1, R2, 0x4, RZ ; /* 0x0000000402047810 */
/* 0x000fc80007f3e0ff */
/*0940*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101908 */
/*0950*/ IADD3.X R5, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff057210 */
/* 0x001fca0000ffe4ff */
/*0960*/ @P0 BRA 0x8d0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <cuda.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
cudaMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
CUevent event;
cuEventCreate(&event, CU_EVENT_DISABLE_TIMING);
CUstream stream;
cuStreamCreate(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
cuEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
cuEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
cuStreamDestroy(stream);
cuEventDestroy(event);
cudaFree(gpufloats);
cout << "finished" << endl;
return 0;
} | .file "tmpxft_000c39c2_00000000-6_testevents2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10longKernelPfifPfif
.type _Z32__device_stub__Z10longKernelPfifPfif, @function
_Z32__device_stub__Z10longKernelPfifPfif:
.LFB4338:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10longKernelPfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z32__device_stub__Z10longKernelPfifPfif, .-_Z32__device_stub__Z10longKernelPfifPfif
.globl _Z10longKernelPfif
.type _Z10longKernelPfif, @function
_Z10longKernelPfif:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10longKernelPfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z10longKernelPfif, .-_Z10longKernelPfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "queued kernel x"
.LC2:
.string "created event"
.LC3:
.string "i "
.LC4:
.string "finished"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $809600, %esi
call cudaMalloc@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3200, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
movl $2, %esi
call cuEventCreate@PLT
leaq 24(%rsp), %rdi
movl $0, %esi
call cuStreamCreate@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC3(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L19
.L23:
movss .LC0(%rip), %xmm0
movl $202400, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10longKernelPfifPfif
jmp .L12
.L27:
movl $2, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L24
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L13
.L24:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
call _ZSt16__throw_bad_castv@PLT
.L25:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L18:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cuEventRecord@PLT
movq 16(%rsp), %rdi
call cuEventSynchronize@PLT
addl $1, %ebx
cmpl $5, %ebx
je .L26
.L19:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
je .L27
.L13:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3200, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movss .LC0(%rip), %xmm0
movl $202400, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10longKernelPfifPfif
jmp .L18
.L26:
movq 24(%rsp), %rdi
call cuStreamDestroy_v2@PLT
movq 16(%rsp), %rdi
call cuEventDestroy_v2@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10longKernelPfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10longKernelPfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <cuda.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
cudaMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
CUevent event;
cuEventCreate(&event, CU_EVENT_DISABLE_TIMING);
CUstream stream;
cuStreamCreate(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
cuEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
cuEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
cuStreamDestroy(stream);
cuEventDestroy(event);
cudaFree(gpufloats);
cout << "finished" << endl;
return 0;
} | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
hipMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
hipEvent_t event;
hipEventCreateWithFlags(&event, hipEventDisableTiming);
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
hipEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
hipEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
hipStreamDestroy(stream);
hipEventDestroy(event);
hipFree(gpufloats);
cout << "finished" << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
hipMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
hipEvent_t event;
hipEventCreateWithFlags(&event, hipEventDisableTiming);
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
hipEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
hipEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
hipStreamDestroy(stream);
hipEventDestroy(event);
hipFree(gpufloats);
cout << "finished" << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10longKernelPfif
.globl _Z10longKernelPfif
.p2align 8
.type _Z10longKernelPfif,@function
_Z10longKernelPfif:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, s0, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10longKernelPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10longKernelPfif, .Lfunc_end0-_Z10longKernelPfif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10longKernelPfif
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z10longKernelPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // tests cuEventCreate
#include <iostream>
#include <memory>
using namespace std;
#include <hip/hip_runtime.h>
__global__ void longKernel(float *data, int N, float value) {
for(int i = 0; i < N; i++) {
data[i] += value;
}
}
int main(int argc, char *argv[]) {
int N = 202400; // * 1024;
float *hostfloats = new float[N];
float *gpufloats;
hipMalloc((void **)&gpufloats, N * sizeof(float));
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
cout << "queued kernel x" << endl;
hipEvent_t event;
hipEventCreateWithFlags(&event, hipEventDisableTiming);
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
cout << "created event" << endl;
for(int i = 0; i < 5; i++) {
if(i % 10 == 0) {
cout << "i " << i << endl;
}
longKernel<<<dim3(102400 / 32, 1, 1), dim3(32, 1, 1)>>>(gpufloats, N, 3.0f);
// cout << "queued kernel x" << endl;
hipEventRecord(event, stream);
// cout << "recoreded event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
hipEventSynchronize(event);
// cout << "synchronized event" << endl;
// cout << "event finished? " << (cuEventQuery(event) == 0) << endl;
}
hipStreamDestroy(stream);
hipEventDestroy(event);
hipFree(gpufloats);
cout << "finished" << endl;
return 0;
} | .text
.file "testevents2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__longKernelPfif # -- Begin function _Z25__device_stub__longKernelPfif
.p2align 4, 0x90
.type _Z25__device_stub__longKernelPfif,@function
_Z25__device_stub__longKernelPfif: # @_Z25__device_stub__longKernelPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10longKernelPfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__longKernelPfif, .Lfunc_end0-_Z25__device_stub__longKernelPfif
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 24(%rsp), %rdi
movl $809600, %esi # imm = 0xC5A80
callq hipMalloc
leaq 3168(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
movl $202400, 8(%rsp) # imm = 0x316A0
movl $1077936128, 16(%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10longKernelPfif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_25
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $2, %esi
callq hipEventCreateWithFlags
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipStreamCreateWithFlags
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_25
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %eax
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
leaq 96(%rsp), %r13
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_24: # in Loop: Header=BB1_11 Depth=1
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
incl %r15d
cmpl $5, %r15d
je .LBB1_15
.LBB1_11: # =>This Inner Loop Header: Depth=1
testl %r15d, %r15d
jne .LBB1_22
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .LBB1_25
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB1_11 Depth=1
cmpb $0, 56(%r12)
je .LBB1_20
# %bb.14: # in Loop: Header=BB1_11 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_21
.LBB1_20: # in Loop: Header=BB1_11 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB1_11 Depth=1
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_22: # in Loop: Header=BB1_11 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
movl $202400, 92(%rsp) # imm = 0x316A0
movl $1077936128, 88(%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 92(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10longKernelPfif, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_24
.LBB1_15:
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_25
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_18
# %bb.17:
movzbl 67(%rbx), %eax
jmp .LBB1_19
.LBB1_18:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10longKernelPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10longKernelPfif,@object # @_Z10longKernelPfif
.section .rodata,"a",@progbits
.globl _Z10longKernelPfif
.p2align 3, 0x0
_Z10longKernelPfif:
.quad _Z25__device_stub__longKernelPfif
.size _Z10longKernelPfif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "queued kernel x"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "created event"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "i "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "finished"
.size .L.str.3, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10longKernelPfif"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__longKernelPfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10longKernelPfif
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10longKernelPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0x830 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*00f0*/ @!P0 BRA 0x6f0 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0110*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0120*/ @!P1 BRA 0x4c0 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0140*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000808020e7981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000408020c7981 */
/* 0x000f28000c1e1900 */
/*0170*/ LDG.E R22, [R2.64+0x18] ; /* 0x0000180802167981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R6, [R2.64+0x3c] ; /* 0x00003c0802067981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0802107981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100802127981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R20, [R2.64+0x14] ; /* 0x0000140802147981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R23, [R2.64+0x1c] ; /* 0x00001c0802177981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R24, [R2.64+0x20] ; /* 0x0000200802187981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R26, [R2.64+0x24] ; /* 0x00002408021a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R10, [R2.64+0x28] ; /* 0x00002808020a7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0802097981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R5, [R2.64+0x30] ; /* 0x0000300802057981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340802087981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R7, [R2.64+0x38] ; /* 0x0000380802077981 */
/* 0x000f62000c1e1900 */
/*0240*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0250*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0260*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0270*/ FADD R11, R11, c[0x0][0x16c] ; /* 0x00005b000b0b7621 */
/* 0x004fe40000000000 */
/*0280*/ FADD R15, R14, c[0x0][0x16c] ; /* 0x00005b000e0f7621 */
/* 0x008fc60000000000 */
/*0290*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000be2000c101908 */
/*02a0*/ FADD R13, R12, c[0x0][0x16c] ; /* 0x00005b000c0d7621 */
/* 0x010fc60000000000 */
/*02b0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x0001e8000c101908 */
/*02c0*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x0003e2000c101908 */
/*02d0*/ FADD R11, R22, c[0x0][0x16c] ; /* 0x00005b00160b7621 */
/* 0x020fe40000000000 */
/*02e0*/ FADD R17, R16, c[0x0][0x16c] ; /* 0x00005b0010117621 */
/* 0x000fe40000000000 */
/*02f0*/ FADD R15, R6, c[0x0][0x16c] ; /* 0x00005b00060f7621 */
/* 0x001fe20000000000 */
/*0300*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe20007f5e0ff */
/*0310*/ FADD R19, R18, c[0x0][0x16c] ; /* 0x00005b0012137621 */
/* 0x000fe20000000000 */
/*0320*/ STG.E [R2.64+0x18], R11 ; /* 0x0000180b02007986 */
/* 0x0001e2000c101908 */
/*0330*/ FADD R21, R20, c[0x0][0x16c] ; /* 0x00005b0014157621 */
/* 0x000fc40000000000 */
/*0340*/ FADD R23, R23, c[0x0][0x16c] ; /* 0x00005b0017177621 */
/* 0x000fe40000000000 */
/*0350*/ FADD R25, R24, c[0x0][0x16c] ; /* 0x00005b0018197621 */
/* 0x000fe40000000000 */
/*0360*/ FADD R27, R26, c[0x0][0x16c] ; /* 0x00005b001a1b7621 */
/* 0x000fe40000000000 */
/*0370*/ FADD R29, R10, c[0x0][0x16c] ; /* 0x00005b000a1d7621 */
/* 0x000fe40000000000 */
/*0380*/ FADD R9, R9, c[0x0][0x16c] ; /* 0x00005b0009097621 */
/* 0x000fe40000000000 */
/*0390*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x000fc40000000000 */
/*03a0*/ FADD R13, R8, c[0x0][0x16c] ; /* 0x00005b00080d7621 */
/* 0x002fe40000000000 */
/*03b0*/ FADD R7, R7, c[0x0][0x16c] ; /* 0x00005b0007077621 */
/* 0x000fe20000000000 */
/*03c0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200017fe4ff */
/*03d0*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe8000c101908 */
/*03e0*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe8000c101908 */
/*03f0*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x000fe8000c101908 */
/*0400*/ STG.E [R2.64+0x1c], R23 ; /* 0x00001c1702007986 */
/* 0x000fe8000c101908 */
/*0410*/ STG.E [R2.64+0x20], R25 ; /* 0x0000201902007986 */
/* 0x000fe8000c101908 */
/*0420*/ STG.E [R2.64+0x24], R27 ; /* 0x0000241b02007986 */
/* 0x000fe8000c101908 */
/*0430*/ STG.E [R2.64+0x28], R29 ; /* 0x0000281d02007986 */
/* 0x000fe8000c101908 */
/*0440*/ STG.E [R2.64+0x2c], R9 ; /* 0x00002c0902007986 */
/* 0x000fe8000c101908 */
/*0450*/ STG.E [R2.64+0x30], R5 ; /* 0x0000300502007986 */
/* 0x000fe8000c101908 */
/*0460*/ STG.E [R2.64+0x34], R13 ; /* 0x0000340d02007986 */
/* 0x000fe8000c101908 */
/*0470*/ STG.E [R2.64+0x38], R7 ; /* 0x0000380702007986 */
/* 0x000fe8000c101908 */
/*0480*/ STG.E [R2.64+0x3c], R15 ; /* 0x00003c0f02007986 */
/* 0x0001e4000c101908 */
/*0490*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0006 */
/*04a0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*04b0*/ @P1 BRA 0x140 ; /* 0xfffffc8000001947 */
/* 0x000fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x6d0 ; /* 0x000001f000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080802087981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c08020a7981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001008020c7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001408020e7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R16, [R2.64+0x18] ; /* 0x0000180802107981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R18, [R2.64+0x1c] ; /* 0x00001c0802127981 */
/* 0x000f62000c1e1900 */
/*0560*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0570*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0590*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x004fc40000000000 */
/*05a0*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x008fc60000000000 */
/*05b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101908 */
/*05c0*/ FADD R9, R8, c[0x0][0x16c] ; /* 0x00005b0008097621 */
/* 0x010fc60000000000 */
/*05d0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101908 */
/*05e0*/ FADD R11, R10, c[0x0][0x16c] ; /* 0x00005b000a0b7621 */
/* 0x020fc60000000000 */
/*05f0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101908 */
/*0600*/ FADD R13, R12, c[0x0][0x16c] ; /* 0x00005b000c0d7621 */
/* 0x000fe20000000000 */
/*0610*/ IADD3 R5, P1, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x001fe40007f3e0ff */
/*0620*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x000fe2000c101908 */
/*0630*/ FADD R15, R14, c[0x0][0x16c] ; /* 0x00005b000e0f7621 */
/* 0x000fe40000000000 */
/*0640*/ IMAD.X R6, RZ, RZ, R3, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0603 */
/*0650*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101908 */
/*0660*/ FADD R17, R16, c[0x0][0x16c] ; /* 0x00005b0010117621 */
/* 0x000fc60000000000 */
/*0670*/ STG.E [R2.64+0x14], R15 ; /* 0x0000140f02007986 */
/* 0x000fe2000c101908 */
/*0680*/ FADD R19, R18, c[0x0][0x16c] ; /* 0x00005b0012137621 */
/* 0x000fc60000000000 */
/*0690*/ STG.E [R2.64+0x18], R17 ; /* 0x0000181102007986 */
/* 0x000fe8000c101908 */
/*06a0*/ STG.E [R2.64+0x1c], R19 ; /* 0x00001c1302007986 */
/* 0x0001e4000c101908 */
/*06b0*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x001fe20000000f00 */
/*06c0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*06d0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*06e0*/ @!P0 BRA 0x830 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*06f0*/ LDG.E R6, [R2.64+0x4] ; /* 0x0000040802067981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080802087981 */
/* 0x000f28000c1e1900 */
/*0720*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c08020a7981 */
/* 0x000f62000c1e1900 */
/*0730*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0750*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0760*/ FADD R7, R6, c[0x0][0x16c] ; /* 0x00005b0006077621 */
/* 0x004fe20000000000 */
/*0770*/ IADD3 R6, P1, R2, 0x10, RZ ; /* 0x0000001002067810 */
/* 0x000fe20007f3e0ff */
/*0780*/ FADD R5, R5, c[0x0][0x16c] ; /* 0x00005b0005057621 */
/* 0x008fc60000000000 */
/*0790*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe20000ffe4ff */
/*07a0*/ FADD R9, R8, c[0x0][0x16c] ; /* 0x00005b0008097621 */
/* 0x010fe40000000000 */
/*07b0*/ FADD R11, R10, c[0x0][0x16c] ; /* 0x00005b000a0b7621 */
/* 0x020fe20000000000 */
/*07c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101908 */
/*07d0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101908 */
/*07e0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101908 */
/*07f0*/ STG.E [R2.64+0xc], R11 ; /* 0x00000c0b02007986 */
/* 0x0001e4000c101908 */
/*0800*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x001fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0820*/ @P0 BRA 0x6f0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0840*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0850*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0860*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0870*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0880*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*0890*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*08a0*/ MOV R3, UR5 ; /* 0x0000000500037c02 */
/* 0x000fe40008000f00 */
/*08b0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe40008000f00 */
/*08c0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fca0000000f00 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*08e0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fca0000000f00 */
/*08f0*/ LDG.E R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000ea2000c1e1900 */
/*0900*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0910*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0920*/ FADD R5, R4, c[0x0][0x16c] ; /* 0x00005b0004057621 */
/* 0x004fe20000000000 */
/*0930*/ IADD3 R4, P1, R2, 0x4, RZ ; /* 0x0000000402047810 */
/* 0x000fc80007f3e0ff */
/*0940*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101908 */
/*0950*/ IADD3.X R5, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff057210 */
/* 0x001fca0000ffe4ff */
/*0960*/ @P0 BRA 0x8d0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ BRA 0x980; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10longKernelPfif
.globl _Z10longKernelPfif
.p2align 8
.type _Z10longKernelPfif,@function
_Z10longKernelPfif:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, s0, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10longKernelPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10longKernelPfif, .Lfunc_end0-_Z10longKernelPfif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10longKernelPfif
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z10longKernelPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c39c2_00000000-6_testevents2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4316:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10longKernelPfifPfif
.type _Z32__device_stub__Z10longKernelPfifPfif, @function
_Z32__device_stub__Z10longKernelPfifPfif:
.LFB4338:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10longKernelPfif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4338:
.size _Z32__device_stub__Z10longKernelPfifPfif, .-_Z32__device_stub__Z10longKernelPfifPfif
.globl _Z10longKernelPfif
.type _Z10longKernelPfif, @function
_Z10longKernelPfif:
.LFB4339:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10longKernelPfifPfif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4339:
.size _Z10longKernelPfif, .-_Z10longKernelPfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "queued kernel x"
.LC2:
.string "created event"
.LC3:
.string "i "
.LC4:
.string "finished"
.text
.globl main
.type main, @function
main:
.LFB4313:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $809600, %esi
call cudaMalloc@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3200, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L12:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
movl $2, %esi
call cuEventCreate@PLT
leaq 24(%rsp), %rdi
movl $0, %esi
call cuStreamCreate@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
leaq .LC3(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L19
.L23:
movss .LC0(%rip), %xmm0
movl $202400, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10longKernelPfifPfif
jmp .L12
.L27:
movl $2, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L24
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L13
.L24:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
call _ZSt16__throw_bad_castv@PLT
.L25:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L18:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cuEventRecord@PLT
movq 16(%rsp), %rdi
call cuEventSynchronize@PLT
addl $1, %ebx
cmpl $5, %ebx
je .L26
.L19:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %eax, %ebx
je .L27
.L13:
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $3200, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movss .LC0(%rip), %xmm0
movl $202400, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10longKernelPfifPfif
jmp .L18
.L26:
movq 24(%rsp), %rdi
call cuStreamDestroy_v2@PLT
movq 16(%rsp), %rdi
call cuEventDestroy_v2@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4313:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10longKernelPfif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10longKernelPfif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4341:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testevents2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__longKernelPfif # -- Begin function _Z25__device_stub__longKernelPfif
.p2align 4, 0x90
.type _Z25__device_stub__longKernelPfif,@function
_Z25__device_stub__longKernelPfif: # @_Z25__device_stub__longKernelPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10longKernelPfif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__longKernelPfif, .Lfunc_end0-_Z25__device_stub__longKernelPfif
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 24(%rsp), %rdi
movl $809600, %esi # imm = 0xC5A80
callq hipMalloc
leaq 3168(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
movl $202400, 8(%rsp) # imm = 0x316A0
movl $1077936128, 16(%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10longKernelPfif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_25
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $2, %esi
callq hipEventCreateWithFlags
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipStreamCreateWithFlags
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_25
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %eax
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
leaq 96(%rsp), %r13
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_24: # in Loop: Header=BB1_11 Depth=1
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
incl %r15d
cmpl $5, %r15d
je .LBB1_15
.LBB1_11: # =>This Inner Loop Header: Depth=1
testl %r15d, %r15d
jne .LBB1_22
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .LBB1_25
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB1_11 Depth=1
cmpb $0, 56(%r12)
je .LBB1_20
# %bb.14: # in Loop: Header=BB1_11 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_21
.LBB1_20: # in Loop: Header=BB1_11 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB1_11 Depth=1
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_22: # in Loop: Header=BB1_11 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rax
movq %rax, 80(%rsp)
movl $202400, 92(%rsp) # imm = 0x316A0
movl $1077936128, 88(%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 92(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10longKernelPfif, %edi
movq %r13, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_24
.LBB1_15:
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_25
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB1_18
# %bb.17:
movzbl 67(%rbx), %eax
jmp .LBB1_19
.LBB1_18:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10longKernelPfif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10longKernelPfif,@object # @_Z10longKernelPfif
.section .rodata,"a",@progbits
.globl _Z10longKernelPfif
.p2align 3, 0x0
_Z10longKernelPfif:
.quad _Z25__device_stub__longKernelPfif
.size _Z10longKernelPfif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "queued kernel x"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "created event"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "i "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "finished"
.size .L.str.3, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10longKernelPfif"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__longKernelPfif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10longKernelPfif
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} | code for sm_80
Function : leven
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06270 */
/*0050*/ ISETP.LT.OR P0, PT, R5, 0x1, P0 ; /* 0x000000010500780c */
/* 0x000fda0000701670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f2000c101104 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x001fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R9, R5, -0x1, RZ ; /* 0xffffffff05097810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3 R2, P1, R9.reuse, c[0x0][0x160], RZ ; /* 0x0000580009027a10 */
/* 0x040fe40007f3e0ff */
/*0130*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0140*/ LEA.HI.X.SX32 R3, R9, c[0x0][0x164], 0x1, P1 ; /* 0x0000590009037a11 */
/* 0x000fce00008f0eff */
/*0150*/ @!P0 BRA 0x8e0 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0160*/ PRMT R6, R5, 0x7610, R6 ; /* 0x0000761005067816 */
/* 0x000fe20000000006 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0f7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff107624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0e7624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000b */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000e */
/*01f0*/ PRMT R6, R6, 0x8880, RZ ; /* 0x0000888006067816 */
/* 0x000fe200000000ff */
/*0200*/ LDG.E.U8 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea8000c1e1100 */
/*0210*/ LDG.E.S8 R13, [R4.64+0x1] ; /* 0x00000104040d7981 */
/* 0x000ee2000c1e1300 */
/*0220*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc60007ffe0ff */
/*0230*/ LDG.E.S8 R11, [R4.64+0x2] ; /* 0x00000204040b7981 */
/* 0x000162000c1e1300 */
/*0240*/ ISETP.GE.AND P0, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x008fc80003f06270 */
/*0250*/ SEL R7, R10, R7, !P0 ; /* 0x000000070a077207 */
/* 0x000fc80004000000 */
/*0260*/ IADD3 R6, P0, R7, c[0x0][0x170], RZ ; /* 0x00005c0007067a10 */
/* 0x000fc80007f1e0ff */
/*0270*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x174], 0x1, P0 ; /* 0x00005d0007077a11 */
/* 0x000fca00000f0eff */
/*0280*/ LDG.E.S8 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x0002e4000c1e1300 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R15 ; /* 0x000000ffff067224 */
/* 0x002fe400078e000f */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0010 */
/*02b0*/ LDG.E.U8 R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000f22000c1e1100 */
/*02c0*/ PRMT R14, R18, 0x8880, RZ ; /* 0x00008880120e7816 */
/* 0x004fe200000000ff */
/*02d0*/ BSSY B0, 0x390 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02e0*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x008fc80007ffe0ff */
/*02f0*/ ISETP.GE.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x000fc80003f06270 */
/*0300*/ SEL R12, RZ, 0x1, P0 ; /* 0x00000001ff0c7807 */
/* 0x000fe40000000000 */
/*0310*/ PRMT R15, R19, 0x8880, RZ ; /* 0x00008880130f7816 */
/* 0x010fc800000000ff */
/*0320*/ ISETP.NE.AND P0, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x380 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x001fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0011 */
/*0360*/ @!P0 ISETP.NE.AND P1, PT, R18, R19, PT ; /* 0x000000131200820c */
/* 0x000fc80003f25270 */
/*0370*/ @!P0 SEL R9, RZ, 0xffffffff, P1 ; /* 0xffffffffff098807 */
/* 0x000fc80000800000 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0390*/ PRMT R12, R9, 0x8880, RZ ; /* 0x00008880090c7816 */
/* 0x000fe200000000ff */
/*03a0*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0001e2000c101104 */
/*03b0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f06270 */
/*03d0*/ LDG.E.U8 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea6000c1e1100 */
/*03e0*/ SEL R12, R15, R10, !P0 ; /* 0x0000000a0f0c7207 */
/* 0x000fe20004000000 */
/*03f0*/ LDG.E.U8 R21, [R6.64+0x1] ; /* 0x0000010406157981 */
/* 0x000ee6000c1e1100 */
/*0400*/ IADD3 R16, P0, R12, c[0x0][0x170], RZ ; /* 0x00005c000c107a10 */
/* 0x000fc80007f1e0ff */
/*0410*/ LEA.HI.X.SX32 R17, R12, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000c117a11 */
/* 0x000fe400000f0eff */
/*0420*/ LDG.E.S8 R12, [R4.64+0x3] ; /* 0x00000304040c7981 */
/* 0x000368000c1e1300 */
/*0430*/ LDG.E.S8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f22000c1e1300 */
/*0440*/ BSSY B0, 0x520 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0450*/ PRMT R14, R18, 0x8880, RZ ; /* 0x00008880120e7816 */
/* 0x004fe400000000ff */
/*0460*/ PRMT R20, R21, 0x8880, RZ ; /* 0x0000888015147816 */
/* 0x008fc400000000ff */
/*0470*/ IADD3 R19, R16, 0x1, RZ ; /* 0x0000000110137810 */
/* 0x010fc80007ffe0ff */
/*0480*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fe20003f06270 */
/*0490*/ IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0014 */
/*04a0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x001fc80000000000 */
/*04b0*/ ISETP.NE.AND P0, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fda0003f05270 */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.AND P0, PT, R13, -0x1, PT ; /* 0xffffffff0d00780c */
/* 0x002fe20003f05270 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fd800078e0013 */
/*04f0*/ @!P0 ISETP.NE.AND P1, PT, R18, R21, PT ; /* 0x000000151200820c */
/* 0x000fc80003f25270 */
/*0500*/ @!P0 SEL R13, RZ, 0xffffffff, P1 ; /* 0xffffffffff0d8807 */
/* 0x000fc80000800000 */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0520*/ PRMT R9, R13, 0x8880, RZ ; /* 0x000088800d097816 */
/* 0x000fe200000000ff */
/*0530*/ STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04007986 */
/* 0x0001e2000c101104 */
/*0540*/ IADD3 R14, R10, 0x2, RZ ; /* 0x000000020a0e7810 */
/* 0x000fe40007ffe0ff */
/*0550*/ ISETP.GE.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x020fe20003f06270 */
/*0560*/ LDG.E.U8 R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea6000c1e1100 */
/*0570*/ SEL R15, R14, R15, !P0 ; /* 0x0000000f0e0f7207 */
/* 0x000fe20004000000 */
/*0580*/ LDG.E.U8 R22, [R6.64+0x2] ; /* 0x0000020406167981 */
/* 0x000ee6000c1e1100 */
/*0590*/ IADD3 R16, P0, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f107a10 */
/* 0x040fe20007f1e0ff */
/*05a0*/ LDG.E.S8 R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000366000c1e1300 */
/*05b0*/ LEA.HI.X.SX32 R17, R15, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000f117a11 */
/* 0x000fca00000f0eff */
/*05c0*/ LDG.E.S8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f22000c1e1300 */
/*05d0*/ BSSY B0, 0x6a0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*05e0*/ PRMT R15, R19, 0x8880, RZ ; /* 0x00008880130f7816 */
/* 0x004fe400000000ff */
/*05f0*/ PRMT R18, R22, 0x8880, RZ ; /* 0x0000888016127816 */
/* 0x008fe400000000ff */
/*0600*/ IADD3 R20, R16, 0x1, RZ ; /* 0x0000000110147810 */
/* 0x010fc80007ffe0ff */
/*0610*/ ISETP.GE.AND P0, PT, R20, R15, PT ; /* 0x0000000f1400720c */
/* 0x000fc80003f06270 */
/*0620*/ SEL R13, RZ, 0x1, P0 ; /* 0x00000001ff0d7807 */
/* 0x001fc80000000000 */
/*0630*/ ISETP.NE.AND P0, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fda0003f05270 */
/*0640*/ @!P0 BRA 0x690 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.NE.AND P0, PT, R11, -0x1, PT ; /* 0xffffffff0b00780c */
/* 0x002fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R11, RZ, RZ, R20 ; /* 0x000000ffff0b7224 */
/* 0x000fd800078e0014 */
/*0670*/ @!P0 ISETP.NE.AND P1, PT, R19, R22, PT ; /* 0x000000161300820c */
/* 0x000fc80003f25270 */
/*0680*/ @!P0 SEL R11, RZ, 0xffffffff, P1 ; /* 0xffffffffff0b8807 */
/* 0x000fc80000800000 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*06a0*/ PRMT R16, R11, 0x8880, RZ ; /* 0x000088800b107816 */
/* 0x000fe200000000ff */
/*06b0*/ STG.E.U8 [R4.64+0x3], R11 ; /* 0x0000030b04007986 */
/* 0x0001e6000c101104 */
/*06c0*/ ISETP.GE.AND P0, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x020fe20003f06270 */
/*06d0*/ LDG.E.U8 R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1100 */
/*06e0*/ LDG.E.U8 R20, [R6.64+0x3] ; /* 0x0000030406147981 */
/* 0x000ef0000c1e1100 */
/*06f0*/ @!P0 IADD3 R14, R10, 0x3, RZ ; /* 0x000000030a0e8810 */
/* 0x000fc80007ffe0ff */
/*0700*/ SHF.R.S32.HI R13, RZ, 0x1f, R14 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140e */
/*0710*/ IADD3 R14, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e0e7a10 */
/* 0x000fc80007f1e0ff */
/*0720*/ IADD3.X R15, R13, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d0f7a10 */
/* 0x000fca00007fe4ff */
/*0730*/ LDG.E.S8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1300 */
/*0740*/ LOP3.LUT R9, R9, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff09097812 */
/* 0x000fe200078ec0ff */
/*0750*/ BSSY B0, 0x830 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0760*/ PRMT R9, R9, 0x8880, RZ ; /* 0x0000888009097816 */
/* 0x000fe400000000ff */
/*0770*/ PRMT R13, R17, 0x8880, RZ ; /* 0x00008880110d7816 */
/* 0x004fe400000000ff */
/*0780*/ PRMT R16, R20, 0x8880, RZ ; /* 0x0000888014107816 */
/* 0x008fe400000000ff */
/*0790*/ IADD3 R18, R14, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x010fc80007ffe0ff */
/*07a0*/ ISETP.GE.AND P0, PT, R18, R13, PT ; /* 0x0000000d1200720c */
/* 0x000fc80003f06270 */
/*07b0*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x001fc80000000000 */
/*07c0*/ ISETP.NE.AND P0, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fda0003f05270 */
/*07d0*/ @!P0 BRA 0x820 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x000fe20003f05270 */
/*07f0*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fd800078e0012 */
/*0800*/ @!P0 ISETP.NE.AND P1, PT, R17, R20, PT ; /* 0x000000141100820c */
/* 0x000fc80003f25270 */
/*0810*/ @!P0 SEL R12, RZ, 0xffffffff, P1 ; /* 0xffffffffff0c8807 */
/* 0x000fc80000800000 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ STG.E.U8 [R4.64+0x4], R12 ; /* 0x0000040c04007986 */
/* 0x0001e2000c101104 */
/*0840*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R15, P1, R6, 0x4, RZ ; /* 0x00000004060f7810 */
/* 0x000fe40007f3e0ff */
/*0860*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0870*/ IADD3 R11, P2, R4, 0x4, RZ ; /* 0x00000004040b7810 */
/* 0x000fe20007f5e0ff */
/*0880*/ IMAD.X R16, RZ, RZ, R7, P1 ; /* 0x000000ffff107224 */
/* 0x000fe200008e0607 */
/*0890*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ PRMT R6, R12, 0x7610, R6 ; /* 0x000076100c067816 */
/* 0x000fe20000000006 */
/*08b0*/ IMAD.X R14, RZ, RZ, R5, P2 ; /* 0x000000ffff0e7224 */
/* 0x000fcc00010e0605 */
/*08c0*/ @P0 BRA 0x1d0 ; /* 0xfffff90000000947 */
/* 0x001fea000383ffff */
/*08d0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*08e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0900*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x040fe40007ffe0ff */
/*0910*/ IADD3 R7, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a10 */
/* 0x000fe40007f3e0ff */
/*0920*/ IADD3 R12, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a00040c7a10 */
/* 0x000fe40007f1e0ff */
/*0930*/ LEA.HI.X.SX32 R8, R6, c[0x0][0x174], 0x1, P1 ; /* 0x00005d0006087a11 */
/* 0x000fe400008f0eff */
/*0940*/ LEA.HI.X.SX32 R13, R4, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00040d7a11 */
/* 0x000fe400000f0eff */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*0970*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe20007ffe0ff */
/*0980*/ LDG.E.U8 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1100 */
/*0990*/ LDG.E.S8 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee8000c1e1300 */
/*09a0*/ LDG.E.S8 R7, [R4.64+-0x1] ; /* 0xffffff0404077981 */
/* 0x000ee4000c1e1300 */
/*09b0*/ ISETP.GE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x008fc80003f06270 */
/*09c0*/ SEL R11, R6, R11, !P0 ; /* 0x0000000b060b7207 */
/* 0x000fc80004000000 */
/*09d0*/ IADD3 R10, P0, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0a7a10 */
/* 0x000fc80007f1e0ff */
/*09e0*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00000f0eff */
/*09f0*/ LDG.E.S8 R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0000e4000c1e1300 */
/*0a00*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*0a10*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000d */
/*0a20*/ LDG.E.U8 R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f22000c1e1100 */
/*0a30*/ PRMT R8, R16, 0x8880, RZ ; /* 0x0000888010087816 */
/* 0x004fe200000000ff */
/*0a40*/ BSSY B0, 0xb10 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0a50*/ IADD3 R15, R7, 0x1, RZ ; /* 0x00000001070f7810 */
/* 0x008fc80007ffe0ff */
/*0a60*/ ISETP.GE.AND P0, PT, R15, R8, PT ; /* 0x000000080f00720c */
/* 0x000fe40003f06270 */
/*0a70*/ PRMT R7, R17, 0x8880, RZ ; /* 0x0000888011077816 */
/* 0x010fca00000000ff */
/*0a80*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0a90*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fc80000000000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 BRA 0xb00 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P1, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x000fe20003f25270 */
/*0ad0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fd800078e000f */
/*0ae0*/ @!P1 ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000920c */
/* 0x000fc80003f05270 */
/*0af0*/ @!P1 SEL R9, RZ, 0xffffffff, P0 ; /* 0xffffffffff099807 */
/* 0x000fc80000000000 */
/*0b00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b10*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101104 */
/*0b30*/ IADD3 R12, P1, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007f3e0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0b50*/ IADD3 R7, P2, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fe20007f5e0ff */
/*0b60*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0b70*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*0b80*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0605 */
/*0b90*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x001fc800078e000e */
/*0ba0*/ @P0 BRA 0x950 ; /* 0xfffffda000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} | .file "tmpxft_0000ee7e_00000000-6_JCudaLevenstein.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5levenPcS_S_iPcS_S_i
.type _Z29__device_stub__Z5levenPcS_S_iPcS_S_i, @function
_Z29__device_stub__Z5levenPcS_S_iPcS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq leven(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5levenPcS_S_iPcS_S_i, .-_Z29__device_stub__Z5levenPcS_S_iPcS_S_i
.globl leven
.type leven, @function
leven:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5levenPcS_S_iPcS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size leven, .-leven
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "leven"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq leven(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected leven
.globl leven
.p2align 8
.type leven,@function
leven:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s6, 1
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v1, s[4:5]
s_cbranch_scc1 .LBB0_8
global_load_u8 v5, v2, s[4:5]
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, -1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v3
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_add_u32 s0, s4, 1
s_addc_u32 s1, s5, 0
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_bfe_i32 v4, v4, 0, 16
s_add_u32 s2, s2, 1
global_store_b8 v2, v3, s[0:1]
s_addc_u32 s3, s3, 0
s_add_i32 s6, s6, -1
v_mov_b32_e32 v5, v3
v_mov_b32_e32 v3, v4
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
s_cbranch_scc0 .LBB0_8
.LBB0_5:
global_load_i8 v4, v2, s[0:1]
global_load_u8 v6, v[0:1], off
global_load_u8 v7, v2, s[2:3]
s_waitcnt vmcnt(3)
v_bfe_i32 v5, v5, 0, 8
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1)
v_min_i16 v5, v4, v5
s_waitcnt vmcnt(1)
v_bfe_i32 v8, v6, 0, 8
s_waitcnt vmcnt(0)
v_bfe_i32 v9, v7, 0, 8
v_bfe_i32 v5, v5, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v5
v_cmp_lt_i32_e32 vcc_lo, v5, v8
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 v8, v9
s_cbranch_execz .LBB0_4
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 -1, v3
s_cbranch_execz .LBB0_3
v_and_b32_e32 v5, 0xff, v7
v_and_b32_e32 v6, 0xff, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u16_e32 vcc_lo, v6, v5
v_cndmask_b32_e32 v5, 0, v3, vcc_lo
s_branch .LBB0_3
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel leven
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size leven, .Lfunc_end0-leven
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: leven
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: leven.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void leven(char* a, char* b, char* costs, int size) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i > 0 && i < size) {
costs[0] = i;
int nw = i - 1;
for(int j = 1; j <= size; j++) {
int firstMin = costs[j] < costs[j-1] ? costs[j] : costs[j-1];
// This line is hard to read due to the lack of min() function
int secondMin = 1 + firstMin < a[i - 1] == b[j - 1] ? nw : nw + 1 ? 1 + firstMin : a[i - 1] == b[j - 1] ? nw : nw + 1;
int cj = secondMin;
nw = costs[j];
costs[j] = cj;
}
}
} | .text
.file "JCudaLevenstein.hip"
.globl __device_stub__leven # -- Begin function __device_stub__leven
.p2align 4, 0x90
.type __device_stub__leven,@function
__device_stub__leven: # @__device_stub__leven
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $leven, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__leven, .Lfunc_end0-__device_stub__leven
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $leven, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type leven,@object # @leven
.section .rodata,"a",@progbits
.globl leven
.p2align 3, 0x0
leven:
.quad __device_stub__leven
.size leven, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "leven"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__leven
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym leven
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : leven
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc80003f06270 */
/*0050*/ ISETP.LT.OR P0, PT, R5, 0x1, P0 ; /* 0x000000010500780c */
/* 0x000fda0000701670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*00c0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001f2000c101104 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x001fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R9, R5, -0x1, RZ ; /* 0xffffffff05097810 */
/* 0x000fc40007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0120*/ IADD3 R2, P1, R9.reuse, c[0x0][0x160], RZ ; /* 0x0000580009027a10 */
/* 0x040fe40007f3e0ff */
/*0130*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*0140*/ LEA.HI.X.SX32 R3, R9, c[0x0][0x164], 0x1, P1 ; /* 0x0000590009037a11 */
/* 0x000fce00008f0eff */
/*0150*/ @!P0 BRA 0x8e0 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0160*/ PRMT R6, R5, 0x7610, R6 ; /* 0x0000761005067816 */
/* 0x000fe20000000006 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0f7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff107624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0e7624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000b */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R14 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000e */
/*01f0*/ PRMT R6, R6, 0x8880, RZ ; /* 0x0000888006067816 */
/* 0x000fe200000000ff */
/*0200*/ LDG.E.U8 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea8000c1e1100 */
/*0210*/ LDG.E.S8 R13, [R4.64+0x1] ; /* 0x00000104040d7981 */
/* 0x000ee2000c1e1300 */
/*0220*/ IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x000fc60007ffe0ff */
/*0230*/ LDG.E.S8 R11, [R4.64+0x2] ; /* 0x00000204040b7981 */
/* 0x000162000c1e1300 */
/*0240*/ ISETP.GE.AND P0, PT, R13, R6, PT ; /* 0x000000060d00720c */
/* 0x008fc80003f06270 */
/*0250*/ SEL R7, R10, R7, !P0 ; /* 0x000000070a077207 */
/* 0x000fc80004000000 */
/*0260*/ IADD3 R6, P0, R7, c[0x0][0x170], RZ ; /* 0x00005c0007067a10 */
/* 0x000fc80007f1e0ff */
/*0270*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x174], 0x1, P0 ; /* 0x00005d0007077a11 */
/* 0x000fca00000f0eff */
/*0280*/ LDG.E.S8 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x0002e4000c1e1300 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R15 ; /* 0x000000ffff067224 */
/* 0x002fe400078e000f */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0010 */
/*02b0*/ LDG.E.U8 R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000f22000c1e1100 */
/*02c0*/ PRMT R14, R18, 0x8880, RZ ; /* 0x00008880120e7816 */
/* 0x004fe200000000ff */
/*02d0*/ BSSY B0, 0x390 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*02e0*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x008fc80007ffe0ff */
/*02f0*/ ISETP.GE.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x000fc80003f06270 */
/*0300*/ SEL R12, RZ, 0x1, P0 ; /* 0x00000001ff0c7807 */
/* 0x000fe40000000000 */
/*0310*/ PRMT R15, R19, 0x8880, RZ ; /* 0x00008880130f7816 */
/* 0x010fc800000000ff */
/*0320*/ ISETP.NE.AND P0, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fda0003f05270 */
/*0330*/ @!P0 BRA 0x380 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x001fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fd800078e0011 */
/*0360*/ @!P0 ISETP.NE.AND P1, PT, R18, R19, PT ; /* 0x000000131200820c */
/* 0x000fc80003f25270 */
/*0370*/ @!P0 SEL R9, RZ, 0xffffffff, P1 ; /* 0xffffffffff098807 */
/* 0x000fc80000800000 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0390*/ PRMT R12, R9, 0x8880, RZ ; /* 0x00008880090c7816 */
/* 0x000fe200000000ff */
/*03a0*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x0001e2000c101104 */
/*03b0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x020fe20003f06270 */
/*03d0*/ LDG.E.U8 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea6000c1e1100 */
/*03e0*/ SEL R12, R15, R10, !P0 ; /* 0x0000000a0f0c7207 */
/* 0x000fe20004000000 */
/*03f0*/ LDG.E.U8 R21, [R6.64+0x1] ; /* 0x0000010406157981 */
/* 0x000ee6000c1e1100 */
/*0400*/ IADD3 R16, P0, R12, c[0x0][0x170], RZ ; /* 0x00005c000c107a10 */
/* 0x000fc80007f1e0ff */
/*0410*/ LEA.HI.X.SX32 R17, R12, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000c117a11 */
/* 0x000fe400000f0eff */
/*0420*/ LDG.E.S8 R12, [R4.64+0x3] ; /* 0x00000304040c7981 */
/* 0x000368000c1e1300 */
/*0430*/ LDG.E.S8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f22000c1e1300 */
/*0440*/ BSSY B0, 0x520 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0450*/ PRMT R14, R18, 0x8880, RZ ; /* 0x00008880120e7816 */
/* 0x004fe400000000ff */
/*0460*/ PRMT R20, R21, 0x8880, RZ ; /* 0x0000888015147816 */
/* 0x008fc400000000ff */
/*0470*/ IADD3 R19, R16, 0x1, RZ ; /* 0x0000000110137810 */
/* 0x010fc80007ffe0ff */
/*0480*/ ISETP.GE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x000fe20003f06270 */
/*0490*/ IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0014 */
/*04a0*/ SEL R9, RZ, 0x1, P0 ; /* 0x00000001ff097807 */
/* 0x001fc80000000000 */
/*04b0*/ ISETP.NE.AND P0, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fda0003f05270 */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.AND P0, PT, R13, -0x1, PT ; /* 0xffffffff0d00780c */
/* 0x002fe20003f05270 */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x000fd800078e0013 */
/*04f0*/ @!P0 ISETP.NE.AND P1, PT, R18, R21, PT ; /* 0x000000151200820c */
/* 0x000fc80003f25270 */
/*0500*/ @!P0 SEL R13, RZ, 0xffffffff, P1 ; /* 0xffffffffff0d8807 */
/* 0x000fc80000800000 */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0520*/ PRMT R9, R13, 0x8880, RZ ; /* 0x000088800d097816 */
/* 0x000fe200000000ff */
/*0530*/ STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04007986 */
/* 0x0001e2000c101104 */
/*0540*/ IADD3 R14, R10, 0x2, RZ ; /* 0x000000020a0e7810 */
/* 0x000fe40007ffe0ff */
/*0550*/ ISETP.GE.AND P0, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x020fe20003f06270 */
/*0560*/ LDG.E.U8 R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea6000c1e1100 */
/*0570*/ SEL R15, R14, R15, !P0 ; /* 0x0000000f0e0f7207 */
/* 0x000fe20004000000 */
/*0580*/ LDG.E.U8 R22, [R6.64+0x2] ; /* 0x0000020406167981 */
/* 0x000ee6000c1e1100 */
/*0590*/ IADD3 R16, P0, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f107a10 */
/* 0x040fe20007f1e0ff */
/*05a0*/ LDG.E.S8 R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000366000c1e1300 */
/*05b0*/ LEA.HI.X.SX32 R17, R15, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000f117a11 */
/* 0x000fca00000f0eff */
/*05c0*/ LDG.E.S8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f22000c1e1300 */
/*05d0*/ BSSY B0, 0x6a0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*05e0*/ PRMT R15, R19, 0x8880, RZ ; /* 0x00008880130f7816 */
/* 0x004fe400000000ff */
/*05f0*/ PRMT R18, R22, 0x8880, RZ ; /* 0x0000888016127816 */
/* 0x008fe400000000ff */
/*0600*/ IADD3 R20, R16, 0x1, RZ ; /* 0x0000000110147810 */
/* 0x010fc80007ffe0ff */
/*0610*/ ISETP.GE.AND P0, PT, R20, R15, PT ; /* 0x0000000f1400720c */
/* 0x000fc80003f06270 */
/*0620*/ SEL R13, RZ, 0x1, P0 ; /* 0x00000001ff0d7807 */
/* 0x001fc80000000000 */
/*0630*/ ISETP.NE.AND P0, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fda0003f05270 */
/*0640*/ @!P0 BRA 0x690 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.NE.AND P0, PT, R11, -0x1, PT ; /* 0xffffffff0b00780c */
/* 0x002fe20003f05270 */
/*0660*/ IMAD.MOV.U32 R11, RZ, RZ, R20 ; /* 0x000000ffff0b7224 */
/* 0x000fd800078e0014 */
/*0670*/ @!P0 ISETP.NE.AND P1, PT, R19, R22, PT ; /* 0x000000161300820c */
/* 0x000fc80003f25270 */
/*0680*/ @!P0 SEL R11, RZ, 0xffffffff, P1 ; /* 0xffffffffff0b8807 */
/* 0x000fc80000800000 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*06a0*/ PRMT R16, R11, 0x8880, RZ ; /* 0x000088800b107816 */
/* 0x000fe200000000ff */
/*06b0*/ STG.E.U8 [R4.64+0x3], R11 ; /* 0x0000030b04007986 */
/* 0x0001e6000c101104 */
/*06c0*/ ISETP.GE.AND P0, PT, R9, R16, PT ; /* 0x000000100900720c */
/* 0x020fe20003f06270 */
/*06d0*/ LDG.E.U8 R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1100 */
/*06e0*/ LDG.E.U8 R20, [R6.64+0x3] ; /* 0x0000030406147981 */
/* 0x000ef0000c1e1100 */
/*06f0*/ @!P0 IADD3 R14, R10, 0x3, RZ ; /* 0x000000030a0e8810 */
/* 0x000fc80007ffe0ff */
/*0700*/ SHF.R.S32.HI R13, RZ, 0x1f, R14 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140e */
/*0710*/ IADD3 R14, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e0e7a10 */
/* 0x000fc80007f1e0ff */
/*0720*/ IADD3.X R15, R13, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d0f7a10 */
/* 0x000fca00007fe4ff */
/*0730*/ LDG.E.S8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1300 */
/*0740*/ LOP3.LUT R9, R9, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff09097812 */
/* 0x000fe200078ec0ff */
/*0750*/ BSSY B0, 0x830 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0760*/ PRMT R9, R9, 0x8880, RZ ; /* 0x0000888009097816 */
/* 0x000fe400000000ff */
/*0770*/ PRMT R13, R17, 0x8880, RZ ; /* 0x00008880110d7816 */
/* 0x004fe400000000ff */
/*0780*/ PRMT R16, R20, 0x8880, RZ ; /* 0x0000888014107816 */
/* 0x008fe400000000ff */
/*0790*/ IADD3 R18, R14, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x010fc80007ffe0ff */
/*07a0*/ ISETP.GE.AND P0, PT, R18, R13, PT ; /* 0x0000000d1200720c */
/* 0x000fc80003f06270 */
/*07b0*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x001fc80000000000 */
/*07c0*/ ISETP.NE.AND P0, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fda0003f05270 */
/*07d0*/ @!P0 BRA 0x820 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x000fe20003f05270 */
/*07f0*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fd800078e0012 */
/*0800*/ @!P0 ISETP.NE.AND P1, PT, R17, R20, PT ; /* 0x000000141100820c */
/* 0x000fc80003f25270 */
/*0810*/ @!P0 SEL R12, RZ, 0xffffffff, P1 ; /* 0xffffffffff0c8807 */
/* 0x000fc80000800000 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ STG.E.U8 [R4.64+0x4], R12 ; /* 0x0000040c04007986 */
/* 0x0001e2000c101104 */
/*0840*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R15, P1, R6, 0x4, RZ ; /* 0x00000004060f7810 */
/* 0x000fe40007f3e0ff */
/*0860*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0870*/ IADD3 R11, P2, R4, 0x4, RZ ; /* 0x00000004040b7810 */
/* 0x000fe20007f5e0ff */
/*0880*/ IMAD.X R16, RZ, RZ, R7, P1 ; /* 0x000000ffff107224 */
/* 0x000fe200008e0607 */
/*0890*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ PRMT R6, R12, 0x7610, R6 ; /* 0x000076100c067816 */
/* 0x000fe20000000006 */
/*08b0*/ IMAD.X R14, RZ, RZ, R5, P2 ; /* 0x000000ffff0e7224 */
/* 0x000fcc00010e0605 */
/*08c0*/ @P0 BRA 0x1d0 ; /* 0xfffff90000000947 */
/* 0x001fea000383ffff */
/*08d0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*08e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0900*/ IADD3 R4, R6.reuse, -0x1, RZ ; /* 0xffffffff06047810 */
/* 0x040fe40007ffe0ff */
/*0910*/ IADD3 R7, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a10 */
/* 0x000fe40007f3e0ff */
/*0920*/ IADD3 R12, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a00040c7a10 */
/* 0x000fe40007f1e0ff */
/*0930*/ LEA.HI.X.SX32 R8, R6, c[0x0][0x174], 0x1, P1 ; /* 0x00005d0006087a11 */
/* 0x000fe400008f0eff */
/*0940*/ LEA.HI.X.SX32 R13, R4, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00040d7a11 */
/* 0x000fe400000f0eff */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*0970*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe20007ffe0ff */
/*0980*/ LDG.E.U8 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1100 */
/*0990*/ LDG.E.S8 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee8000c1e1300 */
/*09a0*/ LDG.E.S8 R7, [R4.64+-0x1] ; /* 0xffffff0404077981 */
/* 0x000ee4000c1e1300 */
/*09b0*/ ISETP.GE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x008fc80003f06270 */
/*09c0*/ SEL R11, R6, R11, !P0 ; /* 0x0000000b060b7207 */
/* 0x000fc80004000000 */
/*09d0*/ IADD3 R10, P0, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0a7a10 */
/* 0x000fc80007f1e0ff */
/*09e0*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x174], 0x1, P0 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00000f0eff */
/*09f0*/ LDG.E.S8 R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0000e4000c1e1300 */
/*0a00*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*0a10*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e000d */
/*0a20*/ LDG.E.U8 R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f22000c1e1100 */
/*0a30*/ PRMT R8, R16, 0x8880, RZ ; /* 0x0000888010087816 */
/* 0x004fe200000000ff */
/*0a40*/ BSSY B0, 0xb10 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0a50*/ IADD3 R15, R7, 0x1, RZ ; /* 0x00000001070f7810 */
/* 0x008fc80007ffe0ff */
/*0a60*/ ISETP.GE.AND P0, PT, R15, R8, PT ; /* 0x000000080f00720c */
/* 0x000fe40003f06270 */
/*0a70*/ PRMT R7, R17, 0x8880, RZ ; /* 0x0000888011077816 */
/* 0x010fca00000000ff */
/*0a80*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0a90*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fc80000000000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 BRA 0xb00 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P1, PT, R9, -0x1, PT ; /* 0xffffffff0900780c */
/* 0x000fe20003f25270 */
/*0ad0*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fd800078e000f */
/*0ae0*/ @!P1 ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000920c */
/* 0x000fc80003f05270 */
/*0af0*/ @!P1 SEL R9, RZ, 0xffffffff, P0 ; /* 0xffffffffff099807 */
/* 0x000fc80000000000 */
/*0b00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b10*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e2000c101104 */
/*0b30*/ IADD3 R12, P1, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007f3e0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0b50*/ IADD3 R7, P2, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fe20007f5e0ff */
/*0b60*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0b70*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe0ff */
/*0b80*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0605 */
/*0b90*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x001fc800078e000e */
/*0ba0*/ @P0 BRA 0x950 ; /* 0xfffffda000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected leven
.globl leven
.p2align 8
.type leven,@function
leven:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s6, 1
s_waitcnt lgkmcnt(0)
global_store_b8 v2, v1, s[4:5]
s_cbranch_scc1 .LBB0_8
global_load_u8 v5, v2, s[4:5]
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v3, -1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v3
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
s_add_u32 s0, s4, 1
s_addc_u32 s1, s5, 0
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
v_bfe_i32 v4, v4, 0, 16
s_add_u32 s2, s2, 1
global_store_b8 v2, v3, s[0:1]
s_addc_u32 s3, s3, 0
s_add_i32 s6, s6, -1
v_mov_b32_e32 v5, v3
v_mov_b32_e32 v3, v4
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s6, 0
s_cbranch_scc0 .LBB0_8
.LBB0_5:
global_load_i8 v4, v2, s[0:1]
global_load_u8 v6, v[0:1], off
global_load_u8 v7, v2, s[2:3]
s_waitcnt vmcnt(3)
v_bfe_i32 v5, v5, 0, 8
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1)
v_min_i16 v5, v4, v5
s_waitcnt vmcnt(1)
v_bfe_i32 v8, v6, 0, 8
s_waitcnt vmcnt(0)
v_bfe_i32 v9, v7, 0, 8
v_bfe_i32 v5, v5, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v5
v_cmp_lt_i32_e32 vcc_lo, v5, v8
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 v8, v9
s_cbranch_execz .LBB0_4
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 -1, v3
s_cbranch_execz .LBB0_3
v_and_b32_e32 v5, 0xff, v7
v_and_b32_e32 v6, 0xff, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u16_e32 vcc_lo, v6, v5
v_cndmask_b32_e32 v5, 0, v3, vcc_lo
s_branch .LBB0_3
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel leven
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size leven, .Lfunc_end0-leven
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: leven
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: leven.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000ee7e_00000000-6_JCudaLevenstein.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5levenPcS_S_iPcS_S_i
.type _Z29__device_stub__Z5levenPcS_S_iPcS_S_i, @function
_Z29__device_stub__Z5levenPcS_S_iPcS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq leven(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5levenPcS_S_iPcS_S_i, .-_Z29__device_stub__Z5levenPcS_S_iPcS_S_i
.globl leven
.type leven, @function
leven:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5levenPcS_S_iPcS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size leven, .-leven
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "leven"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq leven(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaLevenstein.hip"
.globl __device_stub__leven # -- Begin function __device_stub__leven
.p2align 4, 0x90
.type __device_stub__leven,@function
__device_stub__leven: # @__device_stub__leven
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $leven, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__leven, .Lfunc_end0-__device_stub__leven
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $leven, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type leven,@object # @leven
.section .rodata,"a",@progbits
.globl leven
.p2align 3, 0x0
leven:
.quad __device_stub__leven
.size leven, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "leven"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__leven
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym leven
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
cudaMemcpy(A,d_A,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} | code for sm_80
Function : _Z12sumRedKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f05270 */
/*00b0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*00c0*/ STS.64 [R7.X8], R4 ; /* 0x0000000407007388 */
/* 0x0041f40000008a00 */
/*00d0*/ @!P0 BRA 0x1c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.L.U32 R3, R7, 0x2, RZ ; /* 0x0000000207037819 */
/* 0x000fc600000006ff */
/*0100*/ IMAD.IADD R2, R7, 0x1, R0 ; /* 0x0000000107027824 */
/* 0x000fe200078e0200 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.OR P0, PT, R7, R0, P0 ; /* 0x000000000700720c */
/* 0x000fda0000706470 */
/*0140*/ @!P0 LEA R2, R0, R3, 0x2 ; /* 0x0000000300028211 */
/* 0x000fe400078e10ff */
/*0150*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0160*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x001fe80000004800 */
/*0170*/ @!P0 LDS R5, [R2] ; /* 0x0000000002058984 */
/* 0x000e240000000800 */
/*0180*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0190*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x0001e20000004800 */
/*01a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01b0*/ @P0 BRA 0x100 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
cudaMemcpy(A,d_A,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} | .file "tmpxft_0000af3a_00000000-6_retuctionSum2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12sumRedKernelPfiPfi
.type _Z33__device_stub__Z12sumRedKernelPfiPfi, @function
_Z33__device_stub__Z12sumRedKernelPfiPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12sumRedKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12sumRedKernelPfiPfi, .-_Z33__device_stub__Z12sumRedKernelPfiPfi
.globl _Z12sumRedKernelPfi
.type _Z12sumRedKernelPfi, @function
_Z12sumRedKernelPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12sumRedKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12sumRedKernelPfi, .-_Z12sumRedKernelPfi
.globl _Z6sumRedPfi
.type _Z6sumRedPfi, @function
_Z6sumRedPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12sumRedKernelPfiPfi
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6sumRedPfi, .-_Z6sumRedPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%d"
.LC7:
.string "%f"
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC5(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %ebx
movslq %ebx, %rdx
leaq 0(,%rdx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testl %ebx, %ebx
jle .L19
leaq (%r12,%rax), %rdx
movss .LC6(%rip), %xmm0
.L20:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
cmpl $1, %ebx
jg .L22
.L19:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
cvttsd2sil %xmm2, %ebx
movl %ebx, 4(%rsp)
cmpl $1, %ebx
jle .L19
.L22:
movl %ebx, %esi
movq %rbp, %rdi
call _Z6sumRedPfi
pxor %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm2
movsd .LC4(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC1(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L21
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm2
addsd %xmm2, %xmm1
movsd .LC4(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
jmp .L21
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12sumRedKernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumRedKernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
cudaMalloc((void **) &d_A, size);
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
cudaMemcpy(A,d_A,size,cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
hipMemcpy(A,d_A,size,hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
hipMemcpy(A,d_A,size,hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sumRedKernelPfi
.globl _Z12sumRedKernelPfi
.p2align 8
.type _Z12sumRedKernelPfi,@function
_Z12sumRedKernelPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s6, s15, s3
s_cmp_eq_u32 s3, 0
v_add_lshl_u32 v1, s6, v0, 1
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
v_lshlrev_b32_e32 v3, 3, v0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v1, v2 offset1:1
s_cbranch_scc1 .LBB0_5
s_load_b32 s1, s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v2, s3, v0
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e64 s0, s1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s0
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_add_u32 s0, s4, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s5, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumRedKernelPfi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sumRedKernelPfi, .Lfunc_end0-_Z12sumRedKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumRedKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sumRedKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 128
#define BLOCK_SIZE_F 128.0
__global__
void sumRedKernel(float *A, int n){
__shared__ float partialSum[BLOCK_SIZE*2];
int i = (threadIdx.x + blockDim.x * blockIdx.x)*2;
unsigned int t = threadIdx.x * 2;
partialSum[t] = A[i];
partialSum[t+1] = A[i+1];
t = threadIdx.x;
for(unsigned int stride = blockDim.x; stride > 0; stride /= 2){
__syncthreads();
if(t < stride && (t+stride) < n) partialSum[t] += partialSum[t+stride];
}
__syncthreads();
if(threadIdx.x == 0){
A[blockIdx.x] = partialSum[0];
}
}
void sumRed(float* A, int n){
int size = n*sizeof(float);
float *d_A;
hipMalloc((void **) &d_A, size);
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
sumRedKernel<<<ceil(n/(BLOCK_SIZE_F*2)), BLOCK_SIZE>>>(d_A,n);
hipMemcpy(A,d_A,size,hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main(){
int n,i;
float *h_A;
scanf("%d", &n);
h_A = (float*) malloc(n*sizeof(float));
for(i = 0; i < n; i++){
//scanf("%f", &h_A[i]);
h_A[i] = 1;
}
while(n > 1){
sumRed(h_A,n);
n = ceil(n/(BLOCK_SIZE_F*2));
}
printf("%f", h_A[0]);
printf("\n");
return 0;
} | .text
.file "retuctionSum2.hip"
.globl _Z27__device_stub__sumRedKernelPfi # -- Begin function _Z27__device_stub__sumRedKernelPfi
.p2align 4, 0x90
.type _Z27__device_stub__sumRedKernelPfi,@function
_Z27__device_stub__sumRedKernelPfi: # @_Z27__device_stub__sumRedKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12sumRedKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__sumRedKernelPfi, .Lfunc_end0-_Z27__device_stub__sumRedKernelPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6sumRedPfi
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6sumRedPfi
.p2align 4, 0x90
.type _Z6sumRedPfi,@function
_Z6sumRedPfi: # @_Z6sumRedPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r15d
movq %rdi, %rbx
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumRedKernelPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6sumRedPfi, .Lfunc_end1-_Z6sumRedPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
leaq (,%r14,4), %rdi
callq malloc
movq %rax, %rbx
testq %r14, %r14
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %.preheader
movl 4(%rsp), %esi
cmpl $2, %esi
jl .LBB2_5
.p2align 4, 0x90
.LBB2_4: # %.lr.ph7
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq _Z6sumRedPfi
xorps %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %esi
movl %esi, 4(%rsp)
cmpl $1, %esi
jg .LBB2_4
.LBB2_5: # %._crit_edge
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumRedKernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sumRedKernelPfi,@object # @_Z12sumRedKernelPfi
.section .rodata,"a",@progbits
.globl _Z12sumRedKernelPfi
.p2align 3, 0x0
_Z12sumRedKernelPfi:
.quad _Z27__device_stub__sumRedKernelPfi
.size _Z12sumRedKernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sumRedKernelPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sumRedKernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sumRedKernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12sumRedKernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f05270 */
/*00b0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25270 */
/*00c0*/ STS.64 [R7.X8], R4 ; /* 0x0000000407007388 */
/* 0x0041f40000008a00 */
/*00d0*/ @!P0 BRA 0x1c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ SHF.L.U32 R3, R7, 0x2, RZ ; /* 0x0000000207037819 */
/* 0x000fc600000006ff */
/*0100*/ IMAD.IADD R2, R7, 0x1, R0 ; /* 0x0000000107027824 */
/* 0x000fe200078e0200 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f06070 */
/*0130*/ ISETP.GE.U32.OR P0, PT, R7, R0, P0 ; /* 0x000000000700720c */
/* 0x000fda0000706470 */
/*0140*/ @!P0 LEA R2, R0, R3, 0x2 ; /* 0x0000000300028211 */
/* 0x000fe400078e10ff */
/*0150*/ SHF.R.U32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fe20000011600 */
/*0160*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x001fe80000004800 */
/*0170*/ @!P0 LDS R5, [R2] ; /* 0x0000000002058984 */
/* 0x000e240000000800 */
/*0180*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*0190*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x0001e20000004800 */
/*01a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01b0*/ @P0 BRA 0x100 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sumRedKernelPfi
.globl _Z12sumRedKernelPfi
.p2align 8
.type _Z12sumRedKernelPfi,@function
_Z12sumRedKernelPfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s6, s15, s3
s_cmp_eq_u32 s3, 0
v_add_lshl_u32 v1, s6, v0, 1
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
v_lshlrev_b32_e32 v3, 3, v0
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v1, v2 offset1:1
s_cbranch_scc1 .LBB0_5
s_load_b32 s1, s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
v_add_nc_u32_e32 v2, s3, v0
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e64 s0, s1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s0
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_add_u32 s0, s4, s0
ds_load_b32 v1, v0
s_addc_u32 s1, s5, s1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumRedKernelPfi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sumRedKernelPfi, .Lfunc_end0-_Z12sumRedKernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumRedKernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sumRedKernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000af3a_00000000-6_retuctionSum2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12sumRedKernelPfiPfi
.type _Z33__device_stub__Z12sumRedKernelPfiPfi, @function
_Z33__device_stub__Z12sumRedKernelPfiPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12sumRedKernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z12sumRedKernelPfiPfi, .-_Z33__device_stub__Z12sumRedKernelPfiPfi
.globl _Z12sumRedKernelPfi
.type _Z12sumRedKernelPfi, @function
_Z12sumRedKernelPfi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12sumRedKernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12sumRedKernelPfi, .-_Z12sumRedKernelPfi
.globl _Z6sumRedPfi
.type _Z6sumRedPfi, @function
_Z6sumRedPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z12sumRedKernelPfiPfi
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6sumRedPfi, .-_Z6sumRedPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%d"
.LC7:
.string "%f"
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC5(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %ebx
movslq %ebx, %rdx
leaq 0(,%rdx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testl %ebx, %ebx
jle .L19
leaq (%r12,%rax), %rdx
movss .LC6(%rip), %xmm0
.L20:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
cmpl $1, %ebx
jg .L22
.L19:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
cvttsd2sil %xmm2, %ebx
movl %ebx, 4(%rsp)
cmpl $1, %ebx
jle .L19
.L22:
movl %ebx, %esi
movq %rbp, %rdi
call _Z6sumRedPfi
pxor %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm2
movsd .LC4(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC1(%rip), %xmm3
ucomisd %xmm1, %xmm3
jbe .L21
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm2
addsd %xmm2, %xmm1
movsd .LC4(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
jmp .L21
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12sumRedKernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumRedKernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "retuctionSum2.hip"
.globl _Z27__device_stub__sumRedKernelPfi # -- Begin function _Z27__device_stub__sumRedKernelPfi
.p2align 4, 0x90
.type _Z27__device_stub__sumRedKernelPfi,@function
_Z27__device_stub__sumRedKernelPfi: # @_Z27__device_stub__sumRedKernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12sumRedKernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__sumRedKernelPfi, .Lfunc_end0-_Z27__device_stub__sumRedKernelPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6sumRedPfi
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6sumRedPfi
.p2align 4, 0x90
.type _Z6sumRedPfi,@function
_Z6sumRedPfi: # @_Z6sumRedPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r15d
movq %rdi, %rbx
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumRedKernelPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6sumRedPfi, .Lfunc_end1-_Z6sumRedPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
leaq (,%r14,4), %rdi
callq malloc
movq %rax, %rbx
testq %r14, %r14
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %.preheader
movl 4(%rsp), %esi
cmpl $2, %esi
jl .LBB2_5
.p2align 4, 0x90
.LBB2_4: # %.lr.ph7
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
callq _Z6sumRedPfi
xorps %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %esi
movl %esi, 4(%rsp)
cmpl $1, %esi
jg .LBB2_4
.LBB2_5: # %._crit_edge
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumRedKernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12sumRedKernelPfi,@object # @_Z12sumRedKernelPfi
.section .rodata,"a",@progbits
.globl _Z12sumRedKernelPfi
.p2align 3, 0x0
_Z12sumRedKernelPfi:
.quad _Z27__device_stub__sumRedKernelPfi
.size _Z12sumRedKernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sumRedKernelPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sumRedKernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sumRedKernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
__global__ void comps_wave(int **wave, int s_min, int s_max, int *flit_ary, size_t num)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y + threadIdx.y;
if (tidx < s_max - s_min && tidy < 32)
{
wave[tidx][tidy] = flit_ary[(tidx + s_min) * 32 + tidy];
}
}
/****************************************************normalize²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
}
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void compute_masks(float **wave, float *mask_bin, float *masks, float tw, float ts, size_t num)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < 32) masks[tid] = wave[0][tid];
if (tid < num/32)
for (int i = 0; i < 32; i++)
{
if (wave[tid][i] > masks[tid])
masks[tid] = wave[tid][i];
}
__syncthreads();
if (tid < 32)
{
if (mask_bin[tid] == 0)
masks[tid] = 0;
}
} | .file "tmpxft_001a37a4_00000000-6_waveform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
.type _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m, @function
_Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10comps_wavePPiiiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m, .-_Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
.globl _Z10comps_wavePPiiiS_m
.type _Z10comps_wavePPiiiS_m, @function
_Z10comps_wavePPiiiS_m:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10comps_wavePPiiiS_m, .-_Z10comps_wavePPiiiS_m
.globl _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.type _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, @function
_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizePfS_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, .-_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.globl _Z9normalizePfS_ffm
.type _Z9normalizePfS_ffm, @function
_Z9normalizePfS_ffm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9normalizePfS_ffm, .-_Z9normalizePfS_ffm
.globl _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
.type _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm, @function
_Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13compute_masksPPfS_S_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm, .-_Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
.globl _Z13compute_masksPPfS_S_ffm
.type _Z13compute_masksPPfS_S_ffm, @function
_Z13compute_masksPPfS_S_ffm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13compute_masksPPfS_S_ffm, .-_Z13compute_masksPPfS_S_ffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13compute_masksPPfS_S_ffm"
.LC1:
.string "_Z9normalizePfS_ffm"
.LC2:
.string "_Z10comps_wavePPiiiS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13compute_masksPPfS_S_ffm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizePfS_ffm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10comps_wavePPiiiS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
__global__ void comps_wave(int **wave, int s_min, int s_max, int *flit_ary, size_t num)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y + threadIdx.y;
if (tidx < s_max - s_min && tidy < 32)
{
wave[tidx][tidy] = flit_ary[(tidx + s_min) * 32 + tidy];
}
}
/****************************************************normalize²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
}
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void compute_masks(float **wave, float *mask_bin, float *masks, float tw, float ts, size_t num)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < 32) masks[tid] = wave[0][tid];
if (tid < num/32)
for (int i = 0; i < 32; i++)
{
if (wave[tid][i] > masks[tid])
masks[tid] = wave[tid][i];
}
__syncthreads();
if (tid < 32)
{
if (mask_bin[tid] == 0)
masks[tid] = 0;
}
} | #include "hip/hip_runtime.h"
#include <stdio.h>
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
__global__ void comps_wave(int **wave, int s_min, int s_max, int *flit_ary, size_t num)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y + threadIdx.y;
if (tidx < s_max - s_min && tidy < 32)
{
wave[tidx][tidy] = flit_ary[(tidx + s_min) * 32 + tidy];
}
}
/****************************************************normalize²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
}
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void compute_masks(float **wave, float *mask_bin, float *masks, float tw, float ts, size_t num)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < 32) masks[tid] = wave[0][tid];
if (tid < num/32)
for (int i = 0; i < 32; i++)
{
if (wave[tid][i] > masks[tid])
masks[tid] = wave[tid][i];
}
__syncthreads();
if (tid < 32)
{
if (mask_bin[tid] == 0)
masks[tid] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
__global__ void comps_wave(int **wave, int s_min, int s_max, int *flit_ary, size_t num)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y + threadIdx.y;
if (tidx < s_max - s_min && tidy < 32)
{
wave[tidx][tidy] = flit_ary[(tidx + s_min) * 32 + tidy];
}
}
/****************************************************normalize²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
}
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void compute_masks(float **wave, float *mask_bin, float *masks, float tw, float ts, size_t num)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < 32) masks[tid] = wave[0][tid];
if (tid < num/32)
for (int i = 0; i < 32; i++)
{
if (wave[tid][i] > masks[tid])
masks[tid] = wave[tid][i];
}
__syncthreads();
if (tid < 32)
{
if (mask_bin[tid] == 0)
masks[tid] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10comps_wavePPiiiS_m
.globl _Z10comps_wavePPiiiS_m
.p2align 8
.type _Z10comps_wavePPiiiS_m,@function
_Z10comps_wavePPiiiS_m:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_sub_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, 32, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v1, s4, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, v1, 5, v0
v_lshlrev_b64 v[3:4], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[3:4], v[3:4], off
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt vmcnt(1)
v_add_co_u32 v0, vcc_lo, v3, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10comps_wavePPiiiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10comps_wavePPiiiS_m, .Lfunc_end0-_Z10comps_wavePPiiiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9normalizePfS_ffm
.globl _Z9normalizePfS_ffm
.p2align 8
.type _Z9normalizePfS_ffm,@function
_Z9normalizePfS_ffm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x14
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v3, 1.0
s_waitcnt vmcnt(0)
v_cmpx_nle_f32_e32 s3, v2
s_cbranch_execz .LBB1_5
global_load_b32 v3, v[0:1], off
s_load_b32 s1, s[0:1], 0x10
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, s1, v3
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_4
v_subrev_f32_e32 v2, s1, v2
v_sub_f32_e64 v3, s3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v4, v3, v2
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v3, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9normalizePfS_ffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9normalizePfS_ffm, .Lfunc_end1-_Z9normalizePfS_ffm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13compute_masksPPfS_S_ffm
.globl _Z13compute_masksPPfS_S_ffm
.p2align 8
.type _Z13compute_masksPPfS_S_ffm,@function
_Z13compute_masksPPfS_S_ffm:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, 32, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b64 s[8:9], s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s9, v4, s2
v_add_co_u32 v3, s2, s4, v3
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
flat_load_b32 v0, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b32 v[3:4], v0, off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_lshr_b64 s[2:3], s[2:3], 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[2:3], v[1:2]
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_7
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s6, v3
v_add_co_ci_u32_e64 v8, s2, s7, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s4, v5
v_add_co_ci_u32_e64 v4, s2, s5, v6, s2
s_mov_b64 s[6:7], 0
global_load_b64 v[5:6], v[7:8], off
global_load_b32 v0, v[3:4], off
s_branch .LBB2_5
.p2align 6
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s8
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmpk_lg_i32 s6, 0x80
s_cbranch_scc0 .LBB2_7
.LBB2_5:
s_waitcnt vmcnt(1)
v_add_co_u32 v7, s2, v5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s7, v6, s2
s_mov_b32 s8, exec_lo
flat_load_b32 v7, v[7:8]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_gt_f32_e32 v7, v0
s_cbranch_execz .LBB2_4
v_mov_b32_e32 v0, v7
global_store_b32 v[3:4], v7, off
s_branch .LBB2_4
.LBB2_7:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_10
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_10
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB2_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13compute_masksPPfS_S_ffm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13compute_masksPPfS_S_ffm, .Lfunc_end2-_Z13compute_masksPPfS_S_ffm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10comps_wavePPiiiS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10comps_wavePPiiiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9normalizePfS_ffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9normalizePfS_ffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13compute_masksPPfS_S_ffm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13compute_masksPPfS_S_ffm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
/*
waveform.cu:°üº¬µÄº¯ÊýÖ÷ÒªÊǶÔÓ¦SpikeDetect²¿·ÖµÄwaveformµÄһЩ²Ù×÷
º¯Êý×÷ÓÃÈçÏ£º
comps_wave()£º¶ÔÓÚdetect²¿·ÖÌáÈ¡µ½µÄcomponents£¬´Ó±ä»»ºóµÄ²¨ÐÎdata_tÖÐÌáÈ¡¶ÔÓ¦µÄwave
normalize()£º¶ÔÓÚ²¨ÐÎÖеĵçλֵ£¬Í¨¹ý¸ßãÐÖµtsºÍµÍãÐÖµtw½øÐйéÒ»»¯£¬·½±ãÖ®ºó¼ÆËãmasksºÍ¼â·åµÄÖÐÐÄʱ¼ä
compute_masks():¶ÔÓÚÿһ¸öÌáÈ¡µ½µÄwave£¬¼ÆËãÆämasksµÄÖµ
*/
/*******************************************************copy the components to the wave**************************************************************/
__global__ void comps_wave(int **wave, int s_min, int s_max, int *flit_ary, size_t num)
{
int tidx = blockIdx.x * blockDim.x + threadIdx.x;
int tidy = blockIdx.y * blockDim.y + threadIdx.y;
if (tidx < s_max - s_min && tidy < 32)
{
wave[tidx][tidy] = flit_ary[(tidx + s_min) * 32 + tidy];
}
}
/****************************************************normalize²Ù×÷*************************************************************/
__global__ void normalize(float *nor_ary, float *flit_ary,float tw,float ts, size_t N)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < N)
{
if (flit_ary[tid] >= ts) nor_ary[tid] = 1;
else if (nor_ary[tid] < tw) nor_ary[tid] = 0;
else nor_ary[tid] = (flit_ary[tid] - tw) / (ts - tw);
}
}
/****************************************************compute_masks²Ù×÷*************************************************************/
__global__ void compute_masks(float **wave, float *mask_bin, float *masks, float tw, float ts, size_t num)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < 32) masks[tid] = wave[0][tid];
if (tid < num/32)
for (int i = 0; i < 32; i++)
{
if (wave[tid][i] > masks[tid])
masks[tid] = wave[tid][i];
}
__syncthreads();
if (tid < 32)
{
if (mask_bin[tid] == 0)
masks[tid] = 0;
}
} | .text
.file "waveform.hip"
.globl _Z25__device_stub__comps_wavePPiiiS_m # -- Begin function _Z25__device_stub__comps_wavePPiiiS_m
.p2align 4, 0x90
.type _Z25__device_stub__comps_wavePPiiiS_m,@function
_Z25__device_stub__comps_wavePPiiiS_m: # @_Z25__device_stub__comps_wavePPiiiS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10comps_wavePPiiiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__comps_wavePPiiiS_m, .Lfunc_end0-_Z25__device_stub__comps_wavePPiiiS_m
.cfi_endproc
# -- End function
.globl _Z24__device_stub__normalizePfS_ffm # -- Begin function _Z24__device_stub__normalizePfS_ffm
.p2align 4, 0x90
.type _Z24__device_stub__normalizePfS_ffm,@function
_Z24__device_stub__normalizePfS_ffm: # @_Z24__device_stub__normalizePfS_ffm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_ffm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__normalizePfS_ffm, .Lfunc_end1-_Z24__device_stub__normalizePfS_ffm
.cfi_endproc
# -- End function
.globl _Z28__device_stub__compute_masksPPfS_S_ffm # -- Begin function _Z28__device_stub__compute_masksPPfS_S_ffm
.p2align 4, 0x90
.type _Z28__device_stub__compute_masksPPfS_S_ffm,@function
_Z28__device_stub__compute_masksPPfS_S_ffm: # @_Z28__device_stub__compute_masksPPfS_S_ffm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13compute_masksPPfS_S_ffm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__compute_masksPPfS_S_ffm, .Lfunc_end2-_Z28__device_stub__compute_masksPPfS_S_ffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10comps_wavePPiiiS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizePfS_ffm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13compute_masksPPfS_S_ffm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10comps_wavePPiiiS_m,@object # @_Z10comps_wavePPiiiS_m
.section .rodata,"a",@progbits
.globl _Z10comps_wavePPiiiS_m
.p2align 3, 0x0
_Z10comps_wavePPiiiS_m:
.quad _Z25__device_stub__comps_wavePPiiiS_m
.size _Z10comps_wavePPiiiS_m, 8
.type _Z9normalizePfS_ffm,@object # @_Z9normalizePfS_ffm
.globl _Z9normalizePfS_ffm
.p2align 3, 0x0
_Z9normalizePfS_ffm:
.quad _Z24__device_stub__normalizePfS_ffm
.size _Z9normalizePfS_ffm, 8
.type _Z13compute_masksPPfS_S_ffm,@object # @_Z13compute_masksPPfS_S_ffm
.globl _Z13compute_masksPPfS_S_ffm
.p2align 3, 0x0
_Z13compute_masksPPfS_S_ffm:
.quad _Z28__device_stub__compute_masksPPfS_S_ffm
.size _Z13compute_masksPPfS_S_ffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10comps_wavePPiiiS_m"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9normalizePfS_ffm"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13compute_masksPPfS_S_ffm"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__comps_wavePPiiiS_m
.addrsig_sym _Z24__device_stub__normalizePfS_ffm
.addrsig_sym _Z28__device_stub__compute_masksPPfS_S_ffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10comps_wavePPiiiS_m
.addrsig_sym _Z9normalizePfS_ffm
.addrsig_sym _Z13compute_masksPPfS_S_ffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a37a4_00000000-6_waveform.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
.type _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m, @function
_Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10comps_wavePPiiiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m, .-_Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
.globl _Z10comps_wavePPiiiS_m
.type _Z10comps_wavePPiiiS_m, @function
_Z10comps_wavePPiiiS_m:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10comps_wavePPiiiS_mPPiiiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10comps_wavePPiiiS_m, .-_Z10comps_wavePPiiiS_m
.globl _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.type _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, @function
_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizePfS_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm, .-_Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
.globl _Z9normalizePfS_ffm
.type _Z9normalizePfS_ffm, @function
_Z9normalizePfS_ffm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9normalizePfS_ffmPfS_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9normalizePfS_ffm, .-_Z9normalizePfS_ffm
.globl _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
.type _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm, @function
_Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13compute_masksPPfS_S_ffm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm, .-_Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
.globl _Z13compute_masksPPfS_S_ffm
.type _Z13compute_masksPPfS_S_ffm, @function
_Z13compute_masksPPfS_S_ffm:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13compute_masksPPfS_S_ffmPPfS_S_ffm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13compute_masksPPfS_S_ffm, .-_Z13compute_masksPPfS_S_ffm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13compute_masksPPfS_S_ffm"
.LC1:
.string "_Z9normalizePfS_ffm"
.LC2:
.string "_Z10comps_wavePPiiiS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13compute_masksPPfS_S_ffm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizePfS_ffm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10comps_wavePPiiiS_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "waveform.hip"
.globl _Z25__device_stub__comps_wavePPiiiS_m # -- Begin function _Z25__device_stub__comps_wavePPiiiS_m
.p2align 4, 0x90
.type _Z25__device_stub__comps_wavePPiiiS_m,@function
_Z25__device_stub__comps_wavePPiiiS_m: # @_Z25__device_stub__comps_wavePPiiiS_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10comps_wavePPiiiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__comps_wavePPiiiS_m, .Lfunc_end0-_Z25__device_stub__comps_wavePPiiiS_m
.cfi_endproc
# -- End function
.globl _Z24__device_stub__normalizePfS_ffm # -- Begin function _Z24__device_stub__normalizePfS_ffm
.p2align 4, 0x90
.type _Z24__device_stub__normalizePfS_ffm,@function
_Z24__device_stub__normalizePfS_ffm: # @_Z24__device_stub__normalizePfS_ffm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_ffm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__normalizePfS_ffm, .Lfunc_end1-_Z24__device_stub__normalizePfS_ffm
.cfi_endproc
# -- End function
.globl _Z28__device_stub__compute_masksPPfS_S_ffm # -- Begin function _Z28__device_stub__compute_masksPPfS_S_ffm
.p2align 4, 0x90
.type _Z28__device_stub__compute_masksPPfS_S_ffm,@function
_Z28__device_stub__compute_masksPPfS_S_ffm: # @_Z28__device_stub__compute_masksPPfS_S_ffm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13compute_masksPPfS_S_ffm, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__compute_masksPPfS_S_ffm, .Lfunc_end2-_Z28__device_stub__compute_masksPPfS_S_ffm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10comps_wavePPiiiS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizePfS_ffm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13compute_masksPPfS_S_ffm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10comps_wavePPiiiS_m,@object # @_Z10comps_wavePPiiiS_m
.section .rodata,"a",@progbits
.globl _Z10comps_wavePPiiiS_m
.p2align 3, 0x0
_Z10comps_wavePPiiiS_m:
.quad _Z25__device_stub__comps_wavePPiiiS_m
.size _Z10comps_wavePPiiiS_m, 8
.type _Z9normalizePfS_ffm,@object # @_Z9normalizePfS_ffm
.globl _Z9normalizePfS_ffm
.p2align 3, 0x0
_Z9normalizePfS_ffm:
.quad _Z24__device_stub__normalizePfS_ffm
.size _Z9normalizePfS_ffm, 8
.type _Z13compute_masksPPfS_S_ffm,@object # @_Z13compute_masksPPfS_S_ffm
.globl _Z13compute_masksPPfS_S_ffm
.p2align 3, 0x0
_Z13compute_masksPPfS_S_ffm:
.quad _Z28__device_stub__compute_masksPPfS_S_ffm
.size _Z13compute_masksPPfS_S_ffm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10comps_wavePPiiiS_m"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9normalizePfS_ffm"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13compute_masksPPfS_S_ffm"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__comps_wavePPiiiS_m
.addrsig_sym _Z24__device_stub__normalizePfS_ffm
.addrsig_sym _Z28__device_stub__compute_masksPPfS_S_ffm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10comps_wavePPiiiS_m
.addrsig_sym _Z9normalizePfS_ffm
.addrsig_sym _Z13compute_masksPPfS_S_ffm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} | code for sm_80
Function : _Z15Vector_AdditionPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R2, R0, 0xfff0, RZ, 0xc0, !PT ; /* 0x0000fff000027812 */
/* 0x000fc800078ec0ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, 0x270f, PT ; /* 0x0000270f0200780c */
/* 0x000fda0003f04070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ LOP3.LUT R0, R0, 0x3fffc, RZ, 0xc0, !PT ; /* 0x0003fffc00007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc60007f3e0ff */
/*00c0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fe200000e06ff */
/*00d0*/ IADD3.X R3, RZ, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b00ff037a10 */
/* 0x000fca0000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fca0007f1e0ff */
/*0110*/ IMAD.X R7, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff077624 */
/* 0x000fe200000e06ff */
/*0120*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} | .file "tmpxft_0010da20_00000000-6_Vector_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.type _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, @function
_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, .-_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.type _Z15Vector_AdditionPKiS0_Pi, @function
_Z15Vector_AdditionPKiS0_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Vector_AdditionPKiS0_Pi, .-_Z15Vector_AdditionPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Vector_AdditionPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 8
.type _Z15Vector_AdditionPKiS0_Pi,@function
_Z15Vector_AdditionPKiS0_Pi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_and_b32_e32 v0, 0xfff0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x2710, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v0, 0xffff, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z15Vector_AdditionPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Vector_Addition ( const int *dev_a , const int *dev_b , int *dev_c)
{
//Get the id of thread within a block
unsigned short tid = blockDim.x*blockIdx.x+threadIdx.x;
if ( tid < N ) // check the boundry condition for the threads
dev_c [tid] = dev_a[tid] + dev_b[tid] ;
} | .text
.file "Vector_Addition.hip"
.globl _Z30__device_stub__Vector_AdditionPKiS0_Pi # -- Begin function _Z30__device_stub__Vector_AdditionPKiS0_Pi
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPKiS0_Pi,@function
_Z30__device_stub__Vector_AdditionPKiS0_Pi: # @_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPKiS0_Pi,@object # @_Z15Vector_AdditionPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 3, 0x0
_Z15Vector_AdditionPKiS0_Pi:
.quad _Z30__device_stub__Vector_AdditionPKiS0_Pi
.size _Z15Vector_AdditionPKiS0_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPKiS0_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15Vector_AdditionPKiS0_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LOP3.LUT R2, R0, 0xfff0, RZ, 0xc0, !PT ; /* 0x0000fff000027812 */
/* 0x000fc800078ec0ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, 0x270f, PT ; /* 0x0000270f0200780c */
/* 0x000fda0003f04070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ LOP3.LUT R0, R0, 0x3fffc, RZ, 0xc0, !PT ; /* 0x0003fffc00007812 */
/* 0x000fc800078ec0ff */
/*00a0*/ IADD3 R4, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc60007f3e0ff */
/*00c0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fe200000e06ff */
/*00d0*/ IADD3.X R3, RZ, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b00ff037a10 */
/* 0x000fca0000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fca0007f1e0ff */
/*0110*/ IMAD.X R7, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff077624 */
/* 0x000fe200000e06ff */
/*0120*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 8
.type _Z15Vector_AdditionPKiS0_Pi,@function
_Z15Vector_AdditionPKiS0_Pi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_and_b32_e32 v0, 0xfff0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x2710, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v0, 0xffff, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPKiS0_Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z15Vector_AdditionPKiS0_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPKiS0_Pi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPKiS0_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010da20_00000000-6_Vector_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.type _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, @function
_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi, .-_Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
.globl _Z15Vector_AdditionPKiS0_Pi
.type _Z15Vector_AdditionPKiS0_Pi, @function
_Z15Vector_AdditionPKiS0_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15Vector_AdditionPKiS0_PiPKiS0_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Vector_AdditionPKiS0_Pi, .-_Z15Vector_AdditionPKiS0_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Vector_AdditionPKiS0_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPKiS0_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Vector_Addition.hip"
.globl _Z30__device_stub__Vector_AdditionPKiS0_Pi # -- Begin function _Z30__device_stub__Vector_AdditionPKiS0_Pi
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPKiS0_Pi,@function
_Z30__device_stub__Vector_AdditionPKiS0_Pi: # @_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPKiS0_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPKiS0_Pi, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPKiS0_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPKiS0_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPKiS0_Pi,@object # @_Z15Vector_AdditionPKiS0_Pi
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPKiS0_Pi
.p2align 3, 0x0
_Z15Vector_AdditionPKiS0_Pi:
.quad _Z30__device_stub__Vector_AdditionPKiS0_Pi
.size _Z15Vector_AdditionPKiS0_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPKiS0_Pi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPKiS0_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} | code for sm_80
Function : _Z29generic_CUDA_function__kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} | .file "tmpxft_001af559_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
.type _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm, @function
_Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29generic_CUDA_function__kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm, .-_Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
.globl _Z29generic_CUDA_function__kernelPfm
.type _Z29generic_CUDA_function__kernelPfm, @function
_Z29generic_CUDA_function__kernelPfm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z29generic_CUDA_function__kernelPfm, .-_Z29generic_CUDA_function__kernelPfm
.globl _Z21generic_CUDA_functionPfm
.type _Z21generic_CUDA_functionPfm, @function
_Z21generic_CUDA_functionPfm:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 12(%rsp)
movl $1, 16(%rsp)
testq %rsi, %rsi
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
.L13:
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L14
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L14:
cvttss2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rsi, %rax
shrq %rax
movq %rsi, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L13
.L17:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z21generic_CUDA_functionPfm, .-_Z21generic_CUDA_functionPfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z29generic_CUDA_function__kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z29generic_CUDA_function__kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1031798784
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <hip/hip_runtime.h>
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <hip/hip_runtime.h>
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29generic_CUDA_function__kernelPfm
.globl _Z29generic_CUDA_function__kernelPfm
.p2align 8
.type _Z29generic_CUDA_function__kernelPfm,@function
_Z29generic_CUDA_function__kernelPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29generic_CUDA_function__kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29generic_CUDA_function__kernelPfm, .Lfunc_end0-_Z29generic_CUDA_function__kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29generic_CUDA_function__kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29generic_CUDA_function__kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Author: Nikolaus Mayer, 2014 (mayern@informatik.uni-freiburg.de)
* CUDA kernels
*/
#include <hip/hip_runtime.h>
#include <cmath> // std::ceil
/**
* Kernel
*/
__global__ void generic_CUDA_function__kernel( float* DATA,
size_t data_size
)
{
const size_t x = blockIdx.x * blockDim.x + threadIdx.x;
if ( x >= data_size )
return;
DATA[x] *= 2.0f;
}
/**
* Function
*/
void generic_CUDA_function( float* DATA,
size_t data_size
)
{
/// CUDA kernel parameters
const dim3 block(16, 1, 1);
const dim3 grid(std::ceil(data_size/(float)block.x), 1, 1);
/// Call kernel
generic_CUDA_function__kernel<<<grid,block>>>( DATA, data_size );
} | .text
.file "kernels.hip"
.globl _Z44__device_stub__generic_CUDA_function__kernelPfm # -- Begin function _Z44__device_stub__generic_CUDA_function__kernelPfm
.p2align 4, 0x90
.type _Z44__device_stub__generic_CUDA_function__kernelPfm,@function
_Z44__device_stub__generic_CUDA_function__kernelPfm: # @_Z44__device_stub__generic_CUDA_function__kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29generic_CUDA_function__kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z44__device_stub__generic_CUDA_function__kernelPfm, .Lfunc_end0-_Z44__device_stub__generic_CUDA_function__kernelPfm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21generic_CUDA_functionPfm
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z21generic_CUDA_functionPfm
.p2align 4, 0x90
.type _Z21generic_CUDA_functionPfm,@function
_Z21generic_CUDA_functionPfm: # @_Z21generic_CUDA_functionPfm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
testq %rsi, %rsi
js .LBB1_1
# %bb.2:
cvtsi2ss %rbx, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rbx, %rax
shrq %rax
movl %ebx, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29generic_CUDA_function__kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21generic_CUDA_functionPfm, .Lfunc_end1-_Z21generic_CUDA_functionPfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29generic_CUDA_function__kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29generic_CUDA_function__kernelPfm,@object # @_Z29generic_CUDA_function__kernelPfm
.section .rodata,"a",@progbits
.globl _Z29generic_CUDA_function__kernelPfm
.p2align 3, 0x0
_Z29generic_CUDA_function__kernelPfm:
.quad _Z44__device_stub__generic_CUDA_function__kernelPfm
.size _Z29generic_CUDA_function__kernelPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29generic_CUDA_function__kernelPfm"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__generic_CUDA_function__kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29generic_CUDA_function__kernelPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29generic_CUDA_function__kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29generic_CUDA_function__kernelPfm
.globl _Z29generic_CUDA_function__kernelPfm
.p2align 8
.type _Z29generic_CUDA_function__kernelPfm,@function
_Z29generic_CUDA_function__kernelPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29generic_CUDA_function__kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29generic_CUDA_function__kernelPfm, .Lfunc_end0-_Z29generic_CUDA_function__kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29generic_CUDA_function__kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29generic_CUDA_function__kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001af559_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
.type _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm, @function
_Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z29generic_CUDA_function__kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm, .-_Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
.globl _Z29generic_CUDA_function__kernelPfm
.type _Z29generic_CUDA_function__kernelPfm, @function
_Z29generic_CUDA_function__kernelPfm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z29generic_CUDA_function__kernelPfm, .-_Z29generic_CUDA_function__kernelPfm
.globl _Z21generic_CUDA_functionPfm
.type _Z21generic_CUDA_functionPfm, @function
_Z21generic_CUDA_functionPfm:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 12(%rsp)
movl $1, 16(%rsp)
testq %rsi, %rsi
js .L12
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
.L13:
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L14
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L14:
cvttss2siq %xmm3, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rsi, %rax
shrq %rax
movq %rsi, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L13
.L17:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z50__device_stub__Z29generic_CUDA_function__kernelPfmPfm
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z21generic_CUDA_functionPfm, .-_Z21generic_CUDA_functionPfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z29generic_CUDA_function__kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z29generic_CUDA_function__kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1031798784
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z44__device_stub__generic_CUDA_function__kernelPfm # -- Begin function _Z44__device_stub__generic_CUDA_function__kernelPfm
.p2align 4, 0x90
.type _Z44__device_stub__generic_CUDA_function__kernelPfm,@function
_Z44__device_stub__generic_CUDA_function__kernelPfm: # @_Z44__device_stub__generic_CUDA_function__kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29generic_CUDA_function__kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z44__device_stub__generic_CUDA_function__kernelPfm, .Lfunc_end0-_Z44__device_stub__generic_CUDA_function__kernelPfm
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z21generic_CUDA_functionPfm
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z21generic_CUDA_functionPfm
.p2align 4, 0x90
.type _Z21generic_CUDA_functionPfm,@function
_Z21generic_CUDA_functionPfm: # @_Z21generic_CUDA_functionPfm
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
testq %rsi, %rsi
js .LBB1_1
# %bb.2:
cvtsi2ss %rbx, %xmm0
jmp .LBB1_3
.LBB1_1:
movq %rbx, %rax
shrq %rax
movl %ebx, %ecx
andl $1, %ecx
orq %rax, %rcx
cvtsi2ss %rcx, %xmm0
addss %xmm0, %xmm0
.LBB1_3:
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z29generic_CUDA_function__kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21generic_CUDA_functionPfm, .Lfunc_end1-_Z21generic_CUDA_functionPfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29generic_CUDA_function__kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29generic_CUDA_function__kernelPfm,@object # @_Z29generic_CUDA_function__kernelPfm
.section .rodata,"a",@progbits
.globl _Z29generic_CUDA_function__kernelPfm
.p2align 3, 0x0
_Z29generic_CUDA_function__kernelPfm:
.quad _Z44__device_stub__generic_CUDA_function__kernelPfm
.size _Z29generic_CUDA_function__kernelPfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29generic_CUDA_function__kernelPfm"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__generic_CUDA_function__kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29generic_CUDA_function__kernelPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
cudaDeviceReset();
cudaMalloc((void**) &d_vetA, h_Size * sizeof(int));
cudaMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), cudaMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
cudaMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), cudaMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
cudaDeviceSynchronize();
cudaFree(d_vetA);
return 0;
} | code for sm_80
Function : _Z13somaMatrizGPUPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x168] ; /* 0x00005a0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0070*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f46270 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fe40007ffe0ff */
/*0090*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R0, R7, R3, R0 ; /* 0x0000000307007224 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 IADD3 R0, R0, -R7, RZ ; /* 0x8000000700008210 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0150*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0160*/ @!P1 IMAD.IADD R0, R0, 0x1, -R7 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a07 */
/*0170*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0180*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff008a12 */
/* 0x000fc800078e33ff */
/*0190*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R2, R4, c[0x0][0x16c], RZ ; /* 0x00005b0004027a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*01f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0200*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*0230*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
cudaDeviceReset();
cudaMalloc((void**) &d_vetA, h_Size * sizeof(int));
cudaMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), cudaMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
cudaMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), cudaMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
cudaDeviceSynchronize();
cudaFree(d_vetA);
return 0;
} | .file "tmpxft_00053840_00000000-6_aula3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
.type _Z35__device_stub__Z13somaMatrizGPUPiiiPiii, @function
_Z35__device_stub__Z13somaMatrizGPUPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13somaMatrizGPUPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z13somaMatrizGPUPiiiPiii, .-_Z35__device_stub__Z13somaMatrizGPUPiiiPiii
.globl _Z13somaMatrizGPUPiii
.type _Z13somaMatrizGPUPiii, @function
_Z13somaMatrizGPUPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13somaMatrizGPUPiii, .-_Z13somaMatrizGPUPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d, "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $6, 68(%rsp)
movl $7, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $10, 84(%rsp)
movl $11, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $14, 100(%rsp)
movl $15, 104(%rsp)
movl $16, 108(%rsp)
call cudaDeviceReset@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq 48(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r15
jmp .L14
.L12:
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 112(%rsp), %rbp
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $4, %r13d
je .L19
.L14:
movl %r13d, %ebx
addl $1, %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, (%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
cvttsd2sil (%rsp), %edx
cvttsd2sil 8(%rsp), %esi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
jmp .L12
.L19:
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z13somaMatrizGPUPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13somaMatrizGPUPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
cudaDeviceReset();
cudaMalloc((void**) &d_vetA, h_Size * sizeof(int));
cudaMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), cudaMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
cudaMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), cudaMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
cudaDeviceSynchronize();
cudaFree(d_vetA);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
hipDeviceReset();
hipMalloc((void**) &d_vetA, h_Size * sizeof(int));
hipMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), hipMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
hipMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), hipMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
hipDeviceSynchronize();
hipFree(d_vetA);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
hipDeviceReset();
hipMalloc((void**) &d_vetA, h_Size * sizeof(int));
hipMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), hipMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
hipMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), hipMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
hipDeviceSynchronize();
hipFree(d_vetA);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13somaMatrizGPUPiii
.globl _Z13somaMatrizGPUPiii
.p2align 8
.type _Z13somaMatrizGPUPiii,@function
_Z13somaMatrizGPUPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s4
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_mov_b32 s2, exec_lo
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13somaMatrizGPUPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13somaMatrizGPUPiii, .Lfunc_end0-_Z13somaMatrizGPUPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13somaMatrizGPUPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13somaMatrizGPUPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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