system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
__global__ void somaMatrizGPU(int *d_vetA, int indice, int passo){
int id = blockDim.x * blockIdx.x + threadIdx.x;
if((id % indice) == 0)
d_vetA[id] += d_vetA[id+passo];
}
int main(){
int h_Size = 16;
int j, i = 0;
int h_vetA[16]={1,2,3,4,5,6,7,8,9,10, 11, 12, 13, 14, 15, 16};
int *d_vetA;
int passo, indice;
int block = h_Size;
hipDeviceReset();
hipMalloc((void**) &d_vetA, h_Size * sizeof(int));
hipMemcpy(d_vetA, h_vetA, h_Size * sizeof(int), hipMemcpyHostToDevice);
for(i = 0; i < 4; i++){
indice = pow(2, i+1);
passo = pow(2, i);
somaMatrizGPU<<<8, 2>>>(d_vetA, indice, passo);
hipMemcpy(h_vetA, d_vetA, h_Size * sizeof(int), hipMemcpyDeviceToHost);
for(j=0; j < h_Size; j++){
printf("%d, ", h_vetA[j]);
}
printf("\n");
}
hipDeviceSynchronize();
hipFree(d_vetA);
return 0;
} | .text
.file "aula3.hip"
.globl _Z28__device_stub__somaMatrizGPUPiii # -- Begin function _Z28__device_stub__somaMatrizGPUPiii
.p2align 4, 0x90
.type _Z28__device_stub__somaMatrizGPUPiii,@function
_Z28__device_stub__somaMatrizGPUPiii: # @_Z28__device_stub__somaMatrizGPUPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13somaMatrizGPUPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__somaMatrizGPUPiii, .Lfunc_end0-_Z28__device_stub__somaMatrizGPUPiii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 5 # 0x5
.long 6 # 0x6
.long 7 # 0x7
.long 8 # 0x8
.LCPI1_2:
.long 9 # 0x9
.long 10 # 0xa
.long 11 # 0xb
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 14 # 0xe
.long 15 # 0xf
.long 16 # 0x10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,6,7,8]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9,10,11,12]
movaps %xmm0, 160(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,14,15,16]
movaps %xmm0, 176(%rsp)
callq hipDeviceReset
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %r14
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 6(%rbx), %r15
leaq 96(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl %ebp, %r12d
leal 1(%r12), %ebp
movsd .LCPI1_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd .LCPI1_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r12d, %edi
callq ldexp@PLT
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cvttsd2si 24(%rsp), %eax # 8-byte Folded Reload
cvttsd2si 32(%rsp), %ecx # 8-byte Folded Reload
movq 8(%rsp), %rdx
movq %rdx, 88(%rsp)
movl %ecx, 20(%rsp)
movl %eax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z13somaMatrizGPUPiii, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $64, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 128(%rsp,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
cmpl $4, %ebp
jne .LBB1_1
# %bb.6:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13somaMatrizGPUPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13somaMatrizGPUPiii,@object # @_Z13somaMatrizGPUPiii
.section .rodata,"a",@progbits
.globl _Z13somaMatrizGPUPiii
.p2align 3, 0x0
_Z13somaMatrizGPUPiii:
.quad _Z28__device_stub__somaMatrizGPUPiii
.size _Z13somaMatrizGPUPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13somaMatrizGPUPiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__somaMatrizGPUPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13somaMatrizGPUPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13somaMatrizGPUPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x168] ; /* 0x00005a0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0070*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f46270 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fe40007ffe0ff */
/*0090*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R0, R7, R3, R0 ; /* 0x0000000307007224 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 IADD3 R0, R0, -R7, RZ ; /* 0x8000000700008210 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0150*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0160*/ @!P1 IMAD.IADD R0, R0, 0x1, -R7 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a07 */
/*0170*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0180*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff008a12 */
/* 0x000fc800078e33ff */
/*0190*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R2, R4, c[0x0][0x16c], RZ ; /* 0x00005b0004027a10 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*01f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0200*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IADD3 R7, R0, R3, RZ ; /* 0x0000000300077210 */
/* 0x004fca0007ffe0ff */
/*0230*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13somaMatrizGPUPiii
.globl _Z13somaMatrizGPUPiii
.p2align 8
.type _Z13somaMatrizGPUPiii,@function
_Z13somaMatrizGPUPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s4
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
s_mov_b32 s2, exec_lo
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13somaMatrizGPUPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13somaMatrizGPUPiii, .Lfunc_end0-_Z13somaMatrizGPUPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13somaMatrizGPUPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13somaMatrizGPUPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053840_00000000-6_aula3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
.type _Z35__device_stub__Z13somaMatrizGPUPiiiPiii, @function
_Z35__device_stub__Z13somaMatrizGPUPiiiPiii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13somaMatrizGPUPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z13somaMatrizGPUPiiiPiii, .-_Z35__device_stub__Z13somaMatrizGPUPiiiPiii
.globl _Z13somaMatrizGPUPiii
.type _Z13somaMatrizGPUPiii, @function
_Z13somaMatrizGPUPiii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13somaMatrizGPUPiii, .-_Z13somaMatrizGPUPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d, "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $6, 68(%rsp)
movl $7, 72(%rsp)
movl $8, 76(%rsp)
movl $9, 80(%rsp)
movl $10, 84(%rsp)
movl $11, 88(%rsp)
movl $12, 92(%rsp)
movl $13, 96(%rsp)
movl $14, 100(%rsp)
movl $15, 104(%rsp)
movl $16, 108(%rsp)
call cudaDeviceReset@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %r13d
leaq 48(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r15
jmp .L14
.L12:
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq %r14, %rbx
leaq 112(%rsp), %rbp
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $4, %r13d
je .L19
.L14:
movl %r13d, %ebx
addl $1, %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, (%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
cvttsd2sil (%rsp), %edx
cvttsd2sil 8(%rsp), %esi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z13somaMatrizGPUPiiiPiii
jmp .L12
.L19:
call cudaDeviceSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z13somaMatrizGPUPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13somaMatrizGPUPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aula3.hip"
.globl _Z28__device_stub__somaMatrizGPUPiii # -- Begin function _Z28__device_stub__somaMatrizGPUPiii
.p2align 4, 0x90
.type _Z28__device_stub__somaMatrizGPUPiii,@function
_Z28__device_stub__somaMatrizGPUPiii: # @_Z28__device_stub__somaMatrizGPUPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13somaMatrizGPUPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__somaMatrizGPUPiii, .Lfunc_end0-_Z28__device_stub__somaMatrizGPUPiii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 5 # 0x5
.long 6 # 0x6
.long 7 # 0x7
.long 8 # 0x8
.LCPI1_2:
.long 9 # 0x9
.long 10 # 0xa
.long 11 # 0xb
.long 12 # 0xc
.LCPI1_3:
.long 13 # 0xd
.long 14 # 0xe
.long 15 # 0xf
.long 16 # 0x10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 128(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5,6,7,8]
movaps %xmm0, 144(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9,10,11,12]
movaps %xmm0, 160(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [13,14,15,16]
movaps %xmm0, 176(%rsp)
callq hipDeviceReset
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 128(%rsp), %r14
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 6(%rbx), %r15
leaq 96(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movl %ebp, %r12d
leal 1(%r12), %ebp
movsd .LCPI1_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
movsd %xmm0, 32(%rsp) # 8-byte Spill
movsd .LCPI1_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r12d, %edi
callq ldexp@PLT
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cvttsd2si 24(%rsp), %eax # 8-byte Folded Reload
cvttsd2si 32(%rsp), %ecx # 8-byte Folded Reload
movq 8(%rsp), %rdx
movq %rdx, 88(%rsp)
movl %ecx, 20(%rsp)
movl %eax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z13somaMatrizGPUPiii, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rsi
movl $64, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 128(%rsp,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $16, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
cmpl $4, %ebp
jne .LBB1_1
# %bb.6:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13somaMatrizGPUPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13somaMatrizGPUPiii,@object # @_Z13somaMatrizGPUPiii
.section .rodata,"a",@progbits
.globl _Z13somaMatrizGPUPiii
.p2align 3, 0x0
_Z13somaMatrizGPUPiii:
.quad _Z28__device_stub__somaMatrizGPUPiii
.size _Z13somaMatrizGPUPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13somaMatrizGPUPiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__somaMatrizGPUPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13somaMatrizGPUPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __shared__ float sha[512];
__shared__ float shb[512];
__global__ void subDiffKernel(const float * a, const float * b, float * res, const int numFloats)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
sha[threadIdx.x] = a[index];
shb[threadIdx.x] = b[index];
__syncthreads();
float temp1 = 0.0f, temp2 = 0.0f;
for (int i = -8; i <= 8; ++i)
{
const int index2 = (threadIdx.x + i + numFloats) % numFloats;
temp1 += sha[index2] * sha[index2];
temp2 += shb[index2] * shb[index2];
}
res[index] = (temp2 - temp1) / 9.0f;
}
void subdiff_runSub(const int gs, const int bs, float * p0, float * p1, float * p2, int p3)
{
subDiffKernel<<<gs, bs>>>(p0, p1, p2, p3);
} | .file "tmpxft_001b0d7c_00000000-6_cuda_Stream_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13subDiffKernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
.globl _Z13subDiffKernelPKfS0_Pfi
.type _Z13subDiffKernelPKfS0_Pfi, @function
_Z13subDiffKernelPKfS0_Pfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13subDiffKernelPKfS0_Pfi, .-_Z13subDiffKernelPKfS0_Pfi
.globl _Z14subdiff_runSubiiPfS_S_i
.type _Z14subdiff_runSubiiPfS_S_i, @function
_Z14subdiff_runSubiiPfS_S_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z14subdiff_runSubiiPfS_S_i, .-_Z14subdiff_runSubiiPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13subDiffKernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13subDiffKernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __shared__ float sha[512];
__shared__ float shb[512];
__global__ void subDiffKernel(const float * a, const float * b, float * res, const int numFloats)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
sha[threadIdx.x] = a[index];
shb[threadIdx.x] = b[index];
__syncthreads();
float temp1 = 0.0f, temp2 = 0.0f;
for (int i = -8; i <= 8; ++i)
{
const int index2 = (threadIdx.x + i + numFloats) % numFloats;
temp1 += sha[index2] * sha[index2];
temp2 += shb[index2] * shb[index2];
}
res[index] = (temp2 - temp1) / 9.0f;
}
void subdiff_runSub(const int gs, const int bs, float * p0, float * p1, float * p2, int p3)
{
subDiffKernel<<<gs, bs>>>(p0, p1, p2, p3);
} | #include <hip/hip_runtime.h>
__shared__ float sha[512];
__shared__ float shb[512];
__global__ void subDiffKernel(const float * a, const float * b, float * res, const int numFloats)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
sha[threadIdx.x] = a[index];
shb[threadIdx.x] = b[index];
__syncthreads();
float temp1 = 0.0f, temp2 = 0.0f;
for (int i = -8; i <= 8; ++i)
{
const int index2 = (threadIdx.x + i + numFloats) % numFloats;
temp1 += sha[index2] * sha[index2];
temp2 += shb[index2] * shb[index2];
}
res[index] = (temp2 - temp1) / 9.0f;
}
void subdiff_runSub(const int gs, const int bs, float * p0, float * p1, float * p2, int p3)
{
subDiffKernel<<<gs, bs>>>(p0, p1, p2, p3);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__shared__ float sha[512];
__shared__ float shb[512];
__global__ void subDiffKernel(const float * a, const float * b, float * res, const int numFloats)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
sha[threadIdx.x] = a[index];
shb[threadIdx.x] = b[index];
__syncthreads();
float temp1 = 0.0f, temp2 = 0.0f;
for (int i = -8; i <= 8; ++i)
{
const int index2 = (threadIdx.x + i + numFloats) % numFloats;
temp1 += sha[index2] * sha[index2];
temp2 += shb[index2] * shb[index2];
}
res[index] = (temp2 - temp1) / 9.0f;
}
void subdiff_runSub(const int gs, const int bs, float * p0, float * p1, float * p2, int p3)
{
subDiffKernel<<<gs, bs>>>(p0, p1, p2, p3);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13subDiffKernelPKfS0_Pfi
.globl _Z13subDiffKernelPKfS0_Pfi
.p2align 8
.type _Z13subDiffKernelPKfS0_Pfi,@function
_Z13subDiffKernelPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v10, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v[3:4], off
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v3, s2
s_sub_i32 s3, 0, s2
s_mov_b32 s4, -8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s3, v6
v_mul_hi_u32 v9, v6, v3
v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v3, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, -8, v3
v_add_nc_u32_e32 v6, v6, v9
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v10, v7, v8 offset1:8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v10, v5, v6
v_add_nc_u32_e32 v7, s4, v3
s_add_i32 s4, s4, 1
s_cmp_eq_u32 s4, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, s3, v10, v[7:8]
v_not_b32_e32 v11, v10
v_mad_u64_u32 v[9:10], null, s2, v11, v[7:8]
v_cmp_le_u32_e32 vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_subrev_nc_u32_e32 v8, s2, v7
v_cmp_le_u32_e32 vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_lshlrev_b32_e32 v7, 2, v7
ds_load_2addr_stride64_b32 v[7:8], v7 offset1:8
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v0, v7, v7 :: v_dual_add_nc_u32 v5, 1, v5
v_fmac_f32_e32 v4, v8, v8
s_cbranch_scc0 .LBB0_1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v4, v0
s_load_b64 s[0:1], s[0:1], 0x10
v_div_scale_f32 v0, null, 0x41100000, 0x41100000, v3
v_div_scale_f32 v6, vcc_lo, v3, 0x41100000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v0, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v0, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v0, -v0, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v0, v4, v5
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_div_fixup_f32 v2, v4, 0x41100000, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13subDiffKernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13subDiffKernelPKfS0_Pfi, .Lfunc_end0-_Z13subDiffKernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
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.size: 2
.value_kind: hidden_remainder_y
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.size: 2
.value_kind: hidden_remainder_z
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.size: 8
.value_kind: hidden_global_offset_x
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.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13subDiffKernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13subDiffKernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__shared__ float sha[512];
__shared__ float shb[512];
__global__ void subDiffKernel(const float * a, const float * b, float * res, const int numFloats)
{
const int index = blockIdx.x * blockDim.x + threadIdx.x;
sha[threadIdx.x] = a[index];
shb[threadIdx.x] = b[index];
__syncthreads();
float temp1 = 0.0f, temp2 = 0.0f;
for (int i = -8; i <= 8; ++i)
{
const int index2 = (threadIdx.x + i + numFloats) % numFloats;
temp1 += sha[index2] * sha[index2];
temp2 += shb[index2] * shb[index2];
}
res[index] = (temp2 - temp1) / 9.0f;
}
void subdiff_runSub(const int gs, const int bs, float * p0, float * p1, float * p2, int p3)
{
subDiffKernel<<<gs, bs>>>(p0, p1, p2, p3);
} | .text
.file "cuda_Stream_test.hip"
.globl _Z28__device_stub__subDiffKernelPKfS0_Pfi # -- Begin function _Z28__device_stub__subDiffKernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__subDiffKernelPKfS0_Pfi,@function
_Z28__device_stub__subDiffKernelPKfS0_Pfi: # @_Z28__device_stub__subDiffKernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13subDiffKernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__subDiffKernelPKfS0_Pfi, .Lfunc_end0-_Z28__device_stub__subDiffKernelPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z14subdiff_runSubiiPfS_S_i # -- Begin function _Z14subdiff_runSubiiPfS_S_i
.p2align 4, 0x90
.type _Z14subdiff_runSubiiPfS_S_i,@function
_Z14subdiff_runSubiiPfS_S_i: # @_Z14subdiff_runSubiiPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %r9d, %ebx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13subDiffKernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14subdiff_runSubiiPfS_S_i, .Lfunc_end1-_Z14subdiff_runSubiiPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13subDiffKernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13subDiffKernelPKfS0_Pfi,@object # @_Z13subDiffKernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13subDiffKernelPKfS0_Pfi
.p2align 3, 0x0
_Z13subDiffKernelPKfS0_Pfi:
.quad _Z28__device_stub__subDiffKernelPKfS0_Pfi
.size _Z13subDiffKernelPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13subDiffKernelPKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__subDiffKernelPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13subDiffKernelPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0d7c_00000000-6_cuda_Stream_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13subDiffKernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
.globl _Z13subDiffKernelPKfS0_Pfi
.type _Z13subDiffKernelPKfS0_Pfi, @function
_Z13subDiffKernelPKfS0_Pfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13subDiffKernelPKfS0_Pfi, .-_Z13subDiffKernelPKfS0_Pfi
.globl _Z14subdiff_runSubiiPfS_S_i
.type _Z14subdiff_runSubiiPfS_S_i, @function
_Z14subdiff_runSubiiPfS_S_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %r13d
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z40__device_stub__Z13subDiffKernelPKfS0_PfiPKfS0_Pfi
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z14subdiff_runSubiiPfS_S_i, .-_Z14subdiff_runSubiiPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13subDiffKernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13subDiffKernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_Stream_test.hip"
.globl _Z28__device_stub__subDiffKernelPKfS0_Pfi # -- Begin function _Z28__device_stub__subDiffKernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__subDiffKernelPKfS0_Pfi,@function
_Z28__device_stub__subDiffKernelPKfS0_Pfi: # @_Z28__device_stub__subDiffKernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13subDiffKernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__subDiffKernelPKfS0_Pfi, .Lfunc_end0-_Z28__device_stub__subDiffKernelPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z14subdiff_runSubiiPfS_S_i # -- Begin function _Z14subdiff_runSubiiPfS_S_i
.p2align 4, 0x90
.type _Z14subdiff_runSubiiPfS_S_i,@function
_Z14subdiff_runSubiiPfS_S_i: # @_Z14subdiff_runSubiiPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %r9d, %ebx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13subDiffKernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14subdiff_runSubiiPfS_S_i, .Lfunc_end1-_Z14subdiff_runSubiiPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13subDiffKernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13subDiffKernelPKfS0_Pfi,@object # @_Z13subDiffKernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13subDiffKernelPKfS0_Pfi
.p2align 3, 0x0
_Z13subDiffKernelPKfS0_Pfi:
.quad _Z28__device_stub__subDiffKernelPKfS0_Pfi
.size _Z13subDiffKernelPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13subDiffKernelPKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__subDiffKernelPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13subDiffKernelPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
cudaSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
cudaMalloc((void**)&d_a, memSize );
cudaMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
cudaMemcpy(d_b, d_a, memSize, cudaMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("cudaMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
cudaFree( d_a);
cudaFree( d_b);
// Check for any CUDA errors
checkCUDAError("cudaFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << cudaGetErrorString(err) << std::endl;
exit(-1);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
cudaSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
cudaMalloc((void**)&d_a, memSize );
cudaMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
cudaMemcpy(d_b, d_a, memSize, cudaMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("cudaMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
cudaFree( d_a);
cudaFree( d_b);
// Check for any CUDA errors
checkCUDAError("cudaFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << cudaGetErrorString(err) << std::endl;
exit(-1);
}
} | .file "tmpxft_0005ee6d_00000000-6_cuda_mem_model.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: "
.LC1:
.string " "
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC3:
.string "cudaMemcpy calls"
.LC4:
.string "cudaFree"
.LC5:
.string "Correct!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $32, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L8:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $8, %rax
jne .L8
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 32(%rbx), %rdx
.L9:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq %rbx, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
cudaSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
cudaMalloc((void**)&d_a, memSize );
cudaMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
cudaMemcpy(d_b, d_a, memSize, cudaMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
cudaMemcpy(h_a, d_b, memSize, cudaMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("cudaMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
cudaFree( d_a);
cudaFree( d_b);
// Check for any CUDA errors
checkCUDAError("cudaFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << cudaGetErrorString(err) << std::endl;
exit(-1);
}
} | // includes, system
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
hipSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
hipMalloc((void**)&d_a, memSize );
hipMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
hipMemcpy(d_b, d_a, memSize, hipMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("hipMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
hipFree( d_a);
hipFree( d_b);
// Check for any CUDA errors
checkCUDAError("hipFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << hipGetErrorString(err) << std::endl;
exit(-1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
hipSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
hipMalloc((void**)&d_a, memSize );
hipMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
hipMemcpy(d_b, d_a, memSize, hipMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("hipMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
hipFree( d_a);
hipFree( d_b);
// Check for any CUDA errors
checkCUDAError("hipFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << hipGetErrorString(err) << std::endl;
exit(-1);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <hip/hip_runtime.h>
#include <iostream>
#include <assert.h>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 0
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg);
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main()
{
hipSetDevice(MYDEVICE);
// pointer and dimension for host memory
int dimA = 8;
float *h_a;
// pointers for device memory
float *d_a, *d_b;
// allocate and initialize host memory
// Bonus: try using cudaMallocHost in place of malloc
// it has the same syntax as cudaMalloc, but it enables asynchronous copies
h_a = (float *) malloc(dimA*sizeof(float));
for (int i = 0; i<dimA; ++i)
{
h_a[i] = i;
}
// Part 1 of 5: allocate device memory
size_t memSize = dimA*sizeof(float);
hipMalloc((void**)&d_a, memSize );
hipMalloc((void**)&d_b, memSize );
// Part 2 of 5: host to device memory copy
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice );
// Part 3 of 5: device to device memory copy
hipMemcpy(d_b, d_a, memSize, hipMemcpyDeviceToDevice );
// clear host memory
for (int i=0; i<dimA; ++i )
{
h_a[i] = 0.f;
}
// Part 4 of 5: device to host copy
hipMemcpy(h_a, d_b, memSize, hipMemcpyDeviceToHost );
// Check for any CUDA errors
checkCUDAError("hipMemcpy calls");
// verify the data on the host is correct
for (int i=0; i<dimA; ++i)
{
assert(h_a[i] == (float) i);
}
// Part 5 of 5: free device memory pointers d_a and d_b
hipFree( d_a);
hipFree( d_b);
// Check for any CUDA errors
checkCUDAError("hipFree");
// free host memory pointer h_a
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
std::cout << "Correct!" << std::endl;
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
std::cerr << "Cuda error: " << msg << " " << hipGetErrorString(err) << std::endl;
exit(-1);
}
} | .text
.file "cuda_mem_model.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $32, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $8, %r14
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $32, %edx
movl $3, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 16(%rbx)
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
callq _Z14checkCUDAErrorPKc
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
callq _Z14checkCUDAErrorPKc
movq %rbx, %rdi
callq free
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl %eax, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCUDAErrorPKc, .Lfunc_end1-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMemcpy calls"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipFree"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Correct!"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005ee6d_00000000-6_cuda_mem_model.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: "
.LC1:
.string " "
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC3:
.string "cudaMemcpy calls"
.LC4:
.string "cudaFree"
.LC5:
.string "Correct!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $32, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L8:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $8, %rax
jne .L8
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 32(%rbx), %rdx
.L9:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L9
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq %rbx, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_mem_model.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $32, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $8, %r14
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movl $32, %edx
movl $3, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movups %xmm0, 16(%rbx)
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
callq _Z14checkCUDAErrorPKc
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
callq _Z14checkCUDAErrorPKc
movq %rbx, %rdi
callq free
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_7:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl %eax, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl %ebp, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z14checkCUDAErrorPKc, .Lfunc_end1-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMemcpy calls"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipFree"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Correct!"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error: "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Authors
- Dibyadarshan Hota 16CO154
- Omkar Prabhu 16CO233
*/
#include <iostream>
#include <stdio.h>
#include <sstream>
#include <string.h>
#include <cuda.h>
#define ll long long
using namespace std;
/**
* Kernel for computing Betweenness Centrality
* res: Stored in global memory variable bc
*/
__global__
void betweenness_centrality_kernel (int nodes, int *C, int *R, int *d, int *sigma, float *delta, float *bc, int *reverse_stack, int *finish_limit) {
// ================================== VARIABLES INIT ============================================
// initial variables
__shared__ int position;
__shared__ int s;
__shared__ int finish_limit_position;
// source variable initially 0
int idx = threadIdx.x;
if (idx == 0) {
s = 0;
}
__syncthreads();
// move through all nodes
while (s < nodes) {
__syncthreads();
// ============================== distance, delta and sigma INIT ============================================
for(int v=idx; v<nodes; v+=blockDim.x) {
if(v == s) {
d[v] = 0;
sigma[v] = 1;
}
else {
d[v] = INT_MAX;
sigma[v] = 0;
}
delta[v] = 0;
}
__syncthreads();
__shared__ int current_depth;
__shared__ bool done;
if(idx == 0) {
done = false;
current_depth = 0;
position = 0;
finish_limit_position = 1;
finish_limit[0] = 0;
}
__syncthreads();
// ============================== Shortest Path Calculation using curr source ======================
// ============================== Using Vertex Parallel ============================================
while(!done)
{ // wait
__syncthreads();
done = true;
__syncthreads();
// move through modes
for(int v=idx; v<nodes; v+=blockDim.x) {
if(d[v] == current_depth) {
// add to reverse_stack
int t = atomicAdd(&position,1);
reverse_stack[t] = v;
// move through neighbours
for(int r=R[v]; r<R[v+1]; r++) {
int w = C[r];
// if not visited
if(d[w] == INT_MAX) {
d[w] = d[v] + 1;
done = false;
}
// add number of paths
if(d[w] == (d[v] + 1)) {
atomicAdd(&sigma[w],sigma[v]);
}
}
}
}
__syncthreads();
// increment variables
if(idx == 0){
current_depth++;
finish_limit[finish_limit_position] = position;
++finish_limit_position;
}
}
// ============================== BC calculation using Brande's Algorithm ============================================
// Parallel Vertex Parallel implementation
// __syncthreads();
if(idx == 0){
finish_limit_position-=2;
// printf("%d %d %d<--", finish_limit_position, finish_limit[finish_limit_position], finish_limit[finish_limit_position+1]);
// for(int a1=0;a1<=finish_limit_position+1;++a1) printf("%d-", finish_limit[a1]);
// printf("\n");
// for(int a1=0;a1<nodes;++a1) printf("%d<", reverse_stack[a1]);
// cout<<"\n";
// printf("\n");
}
__syncthreads();
//atomicSub(&finish_limit_position,2);
for(int itr1 = finish_limit_position; itr1 >= 0; --itr1){
// __syncthreads();
for(int itr2 = finish_limit[itr1] + idx; itr2 < finish_limit[itr1+1]; itr2+=blockDim.x){
// reverse_stack[itr2] is one node
for(int itr3 = R[reverse_stack[itr2]]; itr3 < R[reverse_stack[itr2] + 1]; ++itr3){
int consider = C[itr3];
// C[itr3] other node
if(d[consider] == d[reverse_stack[itr2]]+1){
//atomicAdd(&delta[consider], ( ((float)sigma[consider]/sigma[reverse_stack[itr2]]) * ((float)1 + delta[reverse_stack[itr2]]) ));
delta[reverse_stack[itr2]] += ( ((float)sigma[reverse_stack[itr2]]/sigma[consider]) * ((float)1 + delta[consider]) );
}
}
if(reverse_stack[itr2] != s){
bc[reverse_stack[itr2]] += delta[reverse_stack[itr2]];
}
}
__syncthreads();
}
// Serialized Vertex Parallel implementation
// if(idx == 0){
// for(int itr1 = nodes - 1; itr1 >= 0; --itr1){
// for(int itr2 = R[reverse_stack[itr1]]; itr2 < R[reverse_stack[itr1] + 1]; ++itr2){
// int consider = C[itr2];
// if(d[consider] == d[reverse_stack[itr1]]-1){
// delta[consider] += ( ((float)sigma[consider]/sigma[reverse_stack[itr1]]) * ((float)1 + delta[reverse_stack[itr1]]) );
// }
// }
// if(reverse_stack[itr1] != s){
// bc[reverse_stack[itr1]] += delta[reverse_stack[itr1]];
// }
// }
// }
// increment
__syncthreads();
if (idx == 0) {
s += 1;
}
}
}
/**
* Main function
*/
int main () {
// ================================ READ INPUT AND MAKE Compressed Adjancency List ====================================
// freopen("graph", "r", stdin);
// nodes and edges
int nodes, edges;
cin>>nodes>>edges;
// compressed adjancency list
int * V = new int[nodes + 1];
int * E = new int[2 * edges];
// read graph data in CSR format
string line;
int node = 0;
int counter = 0;
getline(cin, line);
for (int i = 0; i < nodes; ++i) {
getline(cin, line);
V[node] = counter;
istringstream is(line);
int tmp;
while (is >> tmp) {
E[counter] = tmp;
counter += 1;
}
++node;
}
V[node] = counter;
// cout<<"\n";
// for (int i = 0; i <= nodes; i++) {
// cout<<V[i]<<" ";
// }
// cout<<"\n";
// for (int i = 0; i < 2 * edges; ++i) {
// cout<<E[i]<<" ";
// }
// cout<<"\n";
// ================================ DECLARE AND INIT VARIABLES ====================================
int *d = new int[nodes];
int *sigma = new int[nodes];
float *delta = new float[nodes];
float *bc = new float[nodes];
memset(bc,0,sizeof(bc));
int *d_d, *d_sigma, *d_V, *d_E, *d_reverse_stack, *d_end_point;
float *d_delta, *d_bc;
cudaMalloc((void**)&d_d, sizeof(int) * nodes);
cudaMalloc((void**)&d_end_point, sizeof(int) * (nodes + 1));
cudaMalloc((void**)&d_sigma, sizeof(int) * nodes);
cudaMalloc((void**)&d_reverse_stack, sizeof(int) * nodes);
cudaMalloc((void**)&d_V, sizeof(int) * (nodes + 1));
cudaMalloc((void**)&d_E, sizeof(int) * (2*edges));
cudaMalloc((void**)&d_delta, sizeof(float) * nodes);
cudaMalloc((void**)&d_bc, sizeof(float) * nodes);
cudaMemcpy(d_V, V, sizeof(int) * (nodes+1), cudaMemcpyHostToDevice);
cudaMemcpy(d_E, E, sizeof(int) * (2*edges), cudaMemcpyHostToDevice);
cudaMemcpy(d_bc, bc, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// cudaMemcpy(d_delta, delta, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// ================================ KERNEL PARAMS AND CALL ====================================
float elapsed_time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// kernel call
betweenness_centrality_kernel <<<1, 1024>>> (nodes, d_E, d_V, d_d, d_sigma, d_delta, d_bc, d_reverse_stack, d_end_point);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
// ================================ RESULT ====================================
// cudaMemcpy(d, d_d, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(sigma, d_sigma, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cudaMemcpy(bc, d_bc, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(delta, d_delta, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cout<<"Result: \n";
// for (int i = 0; i < nodes; i++) {
// cout<<"Node: "<<i<<" BC: "<<fixed<<setprecision(6)<<bc[i]/2.0<<"\n";
// }
cout<<"\n";
// Print the time for execution
cout<<"Execution time: "<<elapsed_time/1000.0<<endl;
// Maximum BC value
float max_bc = 0.0;
for (int i = 0; i < nodes; ++i) {
max_bc = (bc[i] > max_bc) ? bc[i] : max_bc;
}
cout<<"Max BC value: "<<max_bc/2.0<<endl;
// ================================ MEMORY RELEASE ====================================
cudaFree(d_sigma);
cudaFree(d_d);
cudaFree(d_V);
cudaFree(d_E);
cudaFree(d_delta);
cudaFree(d_bc);
cudaFree(d_reverse_stack);
cudaFree(d_end_point);
free(E);
free(V);
free(d);
free(sigma);
free(delta);
free(bc);
return 0;
} | .file "tmpxft_0006c258_00000000-6_main_vertex_parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3731:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3731:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_
.type _Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_, @function
_Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_:
.LFB3753:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3753:
.size _Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_, .-_Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_
.globl _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.type _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, @function
_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_:
.LFB3754:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3754:
.size _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, .-_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3756:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3756:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Result: \n"
.LC4:
.string "\n"
.LC5:
.string "Execution time: "
.LC7:
.string "Max BC value: "
.text
.globl main
.type main, @function
main:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $600, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -600(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
.LEHB0:
call _ZNSirsERi@PLT
movq %rax, %rdi
leaq -596(%rbp), %rsi
call _ZNSirsERi@PLT
movl -600(%rbp), %eax
addl $1, %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L14
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, -640(%rbp)
movl -596(%rbp), %eax
addl %eax, %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L67
leaq 0(,%rax,4), %rdi
call _Znam@PLT
.LEHE0:
movq %rax, %r12
leaq -480(%rbp), %rsi
leaq -464(%rbp), %rax
movq %rax, -480(%rbp)
movq $0, -472(%rbp)
movb $0, -464(%rbp)
leaq _ZSt3cin(%rip), %rdi
.LEHB1:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE1:
jmp .L68
.L14:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
.LEHB2:
call __cxa_throw_bad_array_new_length@PLT
.LEHE2:
.L68:
movl -600(%rbp), %eax
movq -640(%rbp), %rcx
movq %rcx, -624(%rbp)
movl $0, -616(%rbp)
movl $0, %r14d
leaq _ZSt3cin(%rip), %r15
testl %eax, %eax
jg .L42
.L19:
movslq %r14d, %r14
movq -640(%rbp), %rcx
movl -616(%rbp), %esi
movl %esi, (%rcx,%r14,4)
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L69
leaq 0(,%rax,4), %rbx
movq %rbx, %rdi
.LEHB3:
call _Znam@PLT
.LEHE3:
jmp .L70
.L67:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
.LEHB4:
call __cxa_throw_bad_array_new_length@PLT
.LEHE4:
.L78:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L71
.LEHB5:
call _ZSt16__throw_bad_castv@PLT
.L54:
endbr64
movq %rax, %rbx
jmp .L39
.L71:
call __stack_chk_fail@PLT
.L23:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE5:
movl %eax, %edx
jmp .L24
.L79:
movq -624(%rbp), %rax
movl -616(%rbp), %ecx
movl %ecx, (%rax)
leaq -448(%rbp), %rbx
leaq -328(%rbp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -328(%rbp)
movq $0, -112(%rbp)
movb $0, -104(%rbp)
movb $0, -103(%rbp)
movq $0, -96(%rbp)
movq $0, -88(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq 8+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %r13
movq %r13, -448(%rbp)
movq -24(%r13), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -448(%rbp,%rax)
movq $0, -440(%rbp)
movq -448(%rbp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
leaq 24+_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -448(%rbp)
leaq 40(%rax), %rax
movq %rax, -328(%rbp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -432(%rbp)
movq $0, -424(%rbp)
movq $0, -416(%rbp)
movq $0, -408(%rbp)
movq $0, -400(%rbp)
movq $0, -392(%rbp)
movq $0, -384(%rbp)
leaq -376(%rbp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -432(%rbp)
movl $0, -368(%rbp)
movq -472(%rbp), %rbx
movq -480(%rbp), %rax
movq %rax, %rcx
movq %rax, -632(%rbp)
leaq -344(%rbp), %rax
movq %rax, -360(%rbp)
testq %rcx, %rcx
jne .L25
testq %rbx, %rbx
jne .L72
.L25:
movq %rbx, -496(%rbp)
cmpq $15, %rbx
ja .L73
cmpq $1, %rbx
jne .L29
movq -632(%rbp), %rax
movzbl (%rax), %eax
movb %al, -344(%rbp)
.L30:
movq -496(%rbp), %rax
movq %rax, -352(%rbp)
movq -360(%rbp), %rdx
movb $0, (%rdx,%rax)
movl $8, -368(%rbp)
leaq -432(%rbp), %rdi
movl $0, %ecx
movl $0, %edx
movq -360(%rbp), %rsi
.LEHB7:
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
.LEHE7:
jmp .L74
.L72:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L75
leaq .LC2(%rip), %rdi
.LEHB8:
call _ZSt19__throw_logic_errorPKc@PLT
.L58:
endbr64
movq %rax, %rbx
jmp .L33
.L75:
call __stack_chk_fail@PLT
.L73:
leaq -496(%rbp), %rsi
leaq -360(%rbp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE8:
movq %rax, %rdi
movq %rax, -360(%rbp)
movq -496(%rbp), %rax
movq %rax, -344(%rbp)
.L28:
movq %rbx, %rdx
movq -632(%rbp), %rsi
call memcpy@PLT
jmp .L30
.L29:
testq %rbx, %rbx
je .L30
leaq -344(%rbp), %rdi
jmp .L28
.L59:
endbr64
movq %rax, %rbx
leaq -360(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L33:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -432(%rbp)
leaq -376(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
.L34:
movq %r13, -448(%rbp)
movq -24(%r13), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -448(%rbp,%rax)
movq $0, -440(%rbp)
.L38:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -328(%rbp)
leaq -328(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L39:
leaq -480(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L74:
leaq -432(%rbp), %rsi
leaq -328(%rbp), %rdi
.LEHB9:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE9:
movslq -616(%rbp), %rbx
leaq -496(%rbp), %rax
movq %rax, -616(%rbp)
jmp .L35
.L57:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -432(%rbp)
movq -360(%rbp), %rdi
leaq -344(%rbp), %rax
cmpq %rax, %rdi
je .L37
movq -344(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L37:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -432(%rbp)
leaq -376(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
jmp .L34
.L56:
endbr64
movq %rax, %rbx
jmp .L38
.L77:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L76
movl -496(%rbp), %eax
movl %eax, (%r12,%rbx,4)
addq $1, %rbx
.L35:
leaq -448(%rbp), %rdi
movq -616(%rbp), %rsi
.LEHB10:
call _ZNSirsERi@PLT
.LEHE10:
jmp .L77
.L76:
addl $1, %r14d
leaq 24+_ZTVNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -448(%rbp)
leaq 40(%rax), %rax
movq %rax, -328(%rbp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, -432(%rbp)
movq -360(%rbp), %rdi
leaq -344(%rbp), %rax
cmpq %rax, %rdi
je .L41
movq -344(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L41:
movl %ebx, -616(%rbp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -432(%rbp)
leaq -376(%rbp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r13, -448(%rbp)
movq -24(%r13), %rax
movq 16+_ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, -448(%rbp,%rax)
movq $0, -440(%rbp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, -328(%rbp)
leaq -328(%rbp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movl -600(%rbp), %eax
addq $4, -624(%rbp)
cmpl %r14d, %eax
jle .L19
.L42:
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rbx
testq %rbx, %rbx
je .L78
cmpb $0, 56(%rbx)
je .L23
movzbl 67(%rbx), %edx
.L24:
movsbl %dl, %edx
leaq -480(%rbp), %rsi
movq %r15, %rdi
.LEHB11:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L79
.L69:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L44:
call __cxa_throw_bad_array_new_length@PLT
.L70:
movq %rax, %r14
movq %rbx, %rcx
movl $8, %edx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
movslq -600(%rbp), %rsi
salq $2, %rsi
leaq -592(%rbp), %rdi
call cudaMalloc@PLT
movl -600(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -552(%rbp), %rdi
call cudaMalloc@PLT
movslq -600(%rbp), %rsi
salq $2, %rsi
leaq -584(%rbp), %rdi
call cudaMalloc@PLT
movslq -600(%rbp), %rsi
salq $2, %rsi
leaq -560(%rbp), %rdi
call cudaMalloc@PLT
movl -600(%rbp), %eax
leal 1(%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -576(%rbp), %rdi
call cudaMalloc@PLT
movl -596(%rbp), %eax
leal (%rax,%rax), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -568(%rbp), %rdi
call cudaMalloc@PLT
movslq -600(%rbp), %rsi
salq $2, %rsi
leaq -544(%rbp), %rdi
call cudaMalloc@PLT
movslq -600(%rbp), %rsi
salq $2, %rsi
leaq -536(%rbp), %rdi
call cudaMalloc@PLT
movl -600(%rbp), %eax
leal 1(%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq -640(%rbp), %rsi
movq -576(%rbp), %rdi
call cudaMemcpy@PLT
movl -596(%rbp), %eax
leal (%rax,%rax), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq -568(%rbp), %rdi
call cudaMemcpy@PLT
movslq -600(%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -536(%rbp), %rdi
call cudaMemcpy@PLT
leaq -528(%rbp), %rdi
call cudaEventCreate@PLT
leaq -520(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -528(%rbp), %rdi
call cudaEventRecord@PLT
movl $1024, -496(%rbp)
movl $1, -492(%rbp)
movl $1, -488(%rbp)
movl $1, -508(%rbp)
movl $1, -504(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -496(%rbp), %rdx
movl $1, %ecx
movq -508(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L45
subq $8, %rsp
pushq -552(%rbp)
pushq -560(%rbp)
pushq -536(%rbp)
movq -544(%rbp), %r9
movq -584(%rbp), %r8
movq -592(%rbp), %rcx
movq -576(%rbp), %rdx
movq -568(%rbp), %rsi
movl -600(%rbp), %edi
.cfi_escape 0x2e,0x20
call _Z65__device_stub__Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_iPiS_S_S_PfS0_S_S_
addq $32, %rsp
.L45:
movl $0, %esi
movq -520(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaEventRecord@PLT
movq -520(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -496(%rbp), %rdi
movq -520(%rbp), %rdx
movq -528(%rbp), %rsi
call cudaEventElapsedTime@PLT
movslq -600(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -536(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -496(%rbp), %xmm0
divsd .LC6(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -600(%rbp), %edx
testl %edx, %edx
jle .L52
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rdx
movl $0x00000000, -616(%rbp)
movq %r14, %rdi
.L48:
movss (%rax), %xmm0
maxss -616(%rbp), %xmm0
movss %xmm0, -616(%rbp)
addq $4, %rax
cmpq %rdx, %rax
jne .L48
movq %rdi, %r14
.L46:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L80
.L52:
movl $0x00000000, -616(%rbp)
jmp .L46
.L80:
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -616(%rbp), %xmm0
mulsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -584(%rbp), %rdi
call cudaFree@PLT
movq -592(%rbp), %rdi
call cudaFree@PLT
movq -576(%rbp), %rdi
call cudaFree@PLT
movq -568(%rbp), %rdi
call cudaFree@PLT
movq -544(%rbp), %rdi
call cudaFree@PLT
movq -536(%rbp), %rdi
call cudaFree@PLT
movq -560(%rbp), %rdi
call cudaFree@PLT
movq -552(%rbp), %rdi
call cudaFree@PLT
.LEHE11:
movq %r12, %rdi
call free@PLT
movq -640(%rbp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
leaq -480(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L81
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -448(%rbp), %rdi
call _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L39
.L50:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.LEHE12:
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L54-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 .L54-.LFB3727
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3727
.uleb128 .LEHE5-.LEHB5
.uleb128 .L54-.LFB3727
.uleb128 0
.uleb128 .LEHB6-.LFB3727
.uleb128 .LEHE6-.LEHB6
.uleb128 .L56-.LFB3727
.uleb128 0
.uleb128 .LEHB7-.LFB3727
.uleb128 .LEHE7-.LEHB7
.uleb128 .L59-.LFB3727
.uleb128 0
.uleb128 .LEHB8-.LFB3727
.uleb128 .LEHE8-.LEHB8
.uleb128 .L58-.LFB3727
.uleb128 0
.uleb128 .LEHB9-.LFB3727
.uleb128 .LEHE9-.LEHB9
.uleb128 .L57-.LFB3727
.uleb128 0
.uleb128 .LEHB10-.LFB3727
.uleb128 .LEHE10-.LEHB10
.uleb128 .L55-.LFB3727
.uleb128 0
.uleb128 .LEHB11-.LFB3727
.uleb128 .LEHE11-.LEHB11
.uleb128 .L54-.LFB3727
.uleb128 0
.uleb128 .LEHB12-.LFB3727
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1083129856
.align 8
.LC8:
.long 0
.long 1071644672
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Authors
- Dibyadarshan Hota 16CO154
- Omkar Prabhu 16CO233
*/
#include <iostream>
#include <stdio.h>
#include <sstream>
#include <string.h>
#include <cuda.h>
#define ll long long
using namespace std;
/**
* Kernel for computing Betweenness Centrality
* res: Stored in global memory variable bc
*/
__global__
void betweenness_centrality_kernel (int nodes, int *C, int *R, int *d, int *sigma, float *delta, float *bc, int *reverse_stack, int *finish_limit) {
// ================================== VARIABLES INIT ============================================
// initial variables
__shared__ int position;
__shared__ int s;
__shared__ int finish_limit_position;
// source variable initially 0
int idx = threadIdx.x;
if (idx == 0) {
s = 0;
}
__syncthreads();
// move through all nodes
while (s < nodes) {
__syncthreads();
// ============================== distance, delta and sigma INIT ============================================
for(int v=idx; v<nodes; v+=blockDim.x) {
if(v == s) {
d[v] = 0;
sigma[v] = 1;
}
else {
d[v] = INT_MAX;
sigma[v] = 0;
}
delta[v] = 0;
}
__syncthreads();
__shared__ int current_depth;
__shared__ bool done;
if(idx == 0) {
done = false;
current_depth = 0;
position = 0;
finish_limit_position = 1;
finish_limit[0] = 0;
}
__syncthreads();
// ============================== Shortest Path Calculation using curr source ======================
// ============================== Using Vertex Parallel ============================================
while(!done)
{ // wait
__syncthreads();
done = true;
__syncthreads();
// move through modes
for(int v=idx; v<nodes; v+=blockDim.x) {
if(d[v] == current_depth) {
// add to reverse_stack
int t = atomicAdd(&position,1);
reverse_stack[t] = v;
// move through neighbours
for(int r=R[v]; r<R[v+1]; r++) {
int w = C[r];
// if not visited
if(d[w] == INT_MAX) {
d[w] = d[v] + 1;
done = false;
}
// add number of paths
if(d[w] == (d[v] + 1)) {
atomicAdd(&sigma[w],sigma[v]);
}
}
}
}
__syncthreads();
// increment variables
if(idx == 0){
current_depth++;
finish_limit[finish_limit_position] = position;
++finish_limit_position;
}
}
// ============================== BC calculation using Brande's Algorithm ============================================
// Parallel Vertex Parallel implementation
// __syncthreads();
if(idx == 0){
finish_limit_position-=2;
// printf("%d %d %d<--", finish_limit_position, finish_limit[finish_limit_position], finish_limit[finish_limit_position+1]);
// for(int a1=0;a1<=finish_limit_position+1;++a1) printf("%d-", finish_limit[a1]);
// printf("\n");
// for(int a1=0;a1<nodes;++a1) printf("%d<", reverse_stack[a1]);
// cout<<"\n";
// printf("\n");
}
__syncthreads();
//atomicSub(&finish_limit_position,2);
for(int itr1 = finish_limit_position; itr1 >= 0; --itr1){
// __syncthreads();
for(int itr2 = finish_limit[itr1] + idx; itr2 < finish_limit[itr1+1]; itr2+=blockDim.x){
// reverse_stack[itr2] is one node
for(int itr3 = R[reverse_stack[itr2]]; itr3 < R[reverse_stack[itr2] + 1]; ++itr3){
int consider = C[itr3];
// C[itr3] other node
if(d[consider] == d[reverse_stack[itr2]]+1){
//atomicAdd(&delta[consider], ( ((float)sigma[consider]/sigma[reverse_stack[itr2]]) * ((float)1 + delta[reverse_stack[itr2]]) ));
delta[reverse_stack[itr2]] += ( ((float)sigma[reverse_stack[itr2]]/sigma[consider]) * ((float)1 + delta[consider]) );
}
}
if(reverse_stack[itr2] != s){
bc[reverse_stack[itr2]] += delta[reverse_stack[itr2]];
}
}
__syncthreads();
}
// Serialized Vertex Parallel implementation
// if(idx == 0){
// for(int itr1 = nodes - 1; itr1 >= 0; --itr1){
// for(int itr2 = R[reverse_stack[itr1]]; itr2 < R[reverse_stack[itr1] + 1]; ++itr2){
// int consider = C[itr2];
// if(d[consider] == d[reverse_stack[itr1]]-1){
// delta[consider] += ( ((float)sigma[consider]/sigma[reverse_stack[itr1]]) * ((float)1 + delta[reverse_stack[itr1]]) );
// }
// }
// if(reverse_stack[itr1] != s){
// bc[reverse_stack[itr1]] += delta[reverse_stack[itr1]];
// }
// }
// }
// increment
__syncthreads();
if (idx == 0) {
s += 1;
}
}
}
/**
* Main function
*/
int main () {
// ================================ READ INPUT AND MAKE Compressed Adjancency List ====================================
// freopen("graph", "r", stdin);
// nodes and edges
int nodes, edges;
cin>>nodes>>edges;
// compressed adjancency list
int * V = new int[nodes + 1];
int * E = new int[2 * edges];
// read graph data in CSR format
string line;
int node = 0;
int counter = 0;
getline(cin, line);
for (int i = 0; i < nodes; ++i) {
getline(cin, line);
V[node] = counter;
istringstream is(line);
int tmp;
while (is >> tmp) {
E[counter] = tmp;
counter += 1;
}
++node;
}
V[node] = counter;
// cout<<"\n";
// for (int i = 0; i <= nodes; i++) {
// cout<<V[i]<<" ";
// }
// cout<<"\n";
// for (int i = 0; i < 2 * edges; ++i) {
// cout<<E[i]<<" ";
// }
// cout<<"\n";
// ================================ DECLARE AND INIT VARIABLES ====================================
int *d = new int[nodes];
int *sigma = new int[nodes];
float *delta = new float[nodes];
float *bc = new float[nodes];
memset(bc,0,sizeof(bc));
int *d_d, *d_sigma, *d_V, *d_E, *d_reverse_stack, *d_end_point;
float *d_delta, *d_bc;
cudaMalloc((void**)&d_d, sizeof(int) * nodes);
cudaMalloc((void**)&d_end_point, sizeof(int) * (nodes + 1));
cudaMalloc((void**)&d_sigma, sizeof(int) * nodes);
cudaMalloc((void**)&d_reverse_stack, sizeof(int) * nodes);
cudaMalloc((void**)&d_V, sizeof(int) * (nodes + 1));
cudaMalloc((void**)&d_E, sizeof(int) * (2*edges));
cudaMalloc((void**)&d_delta, sizeof(float) * nodes);
cudaMalloc((void**)&d_bc, sizeof(float) * nodes);
cudaMemcpy(d_V, V, sizeof(int) * (nodes+1), cudaMemcpyHostToDevice);
cudaMemcpy(d_E, E, sizeof(int) * (2*edges), cudaMemcpyHostToDevice);
cudaMemcpy(d_bc, bc, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// cudaMemcpy(d_delta, delta, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// ================================ KERNEL PARAMS AND CALL ====================================
float elapsed_time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// kernel call
betweenness_centrality_kernel <<<1, 1024>>> (nodes, d_E, d_V, d_d, d_sigma, d_delta, d_bc, d_reverse_stack, d_end_point);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed_time, start, stop);
// ================================ RESULT ====================================
// cudaMemcpy(d, d_d, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(sigma, d_sigma, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cudaMemcpy(bc, d_bc, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(delta, d_delta, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cout<<"Result: \n";
// for (int i = 0; i < nodes; i++) {
// cout<<"Node: "<<i<<" BC: "<<fixed<<setprecision(6)<<bc[i]/2.0<<"\n";
// }
cout<<"\n";
// Print the time for execution
cout<<"Execution time: "<<elapsed_time/1000.0<<endl;
// Maximum BC value
float max_bc = 0.0;
for (int i = 0; i < nodes; ++i) {
max_bc = (bc[i] > max_bc) ? bc[i] : max_bc;
}
cout<<"Max BC value: "<<max_bc/2.0<<endl;
// ================================ MEMORY RELEASE ====================================
cudaFree(d_sigma);
cudaFree(d_d);
cudaFree(d_V);
cudaFree(d_E);
cudaFree(d_delta);
cudaFree(d_bc);
cudaFree(d_reverse_stack);
cudaFree(d_end_point);
free(E);
free(V);
free(d);
free(sigma);
free(delta);
free(bc);
return 0;
} | /*
Authors
- Dibyadarshan Hota 16CO154
- Omkar Prabhu 16CO233
*/
#include <iostream>
#include <stdio.h>
#include <sstream>
#include <string.h>
#include <hip/hip_runtime.h>
#define ll long long
using namespace std;
/**
* Kernel for computing Betweenness Centrality
* res: Stored in global memory variable bc
*/
__global__
void betweenness_centrality_kernel (int nodes, int *C, int *R, int *d, int *sigma, float *delta, float *bc, int *reverse_stack, int *finish_limit) {
// ================================== VARIABLES INIT ============================================
// initial variables
__shared__ int position;
__shared__ int s;
__shared__ int finish_limit_position;
// source variable initially 0
int idx = threadIdx.x;
if (idx == 0) {
s = 0;
}
__syncthreads();
// move through all nodes
while (s < nodes) {
__syncthreads();
// ============================== distance, delta and sigma INIT ============================================
for(int v=idx; v<nodes; v+=blockDim.x) {
if(v == s) {
d[v] = 0;
sigma[v] = 1;
}
else {
d[v] = INT_MAX;
sigma[v] = 0;
}
delta[v] = 0;
}
__syncthreads();
__shared__ int current_depth;
__shared__ bool done;
if(idx == 0) {
done = false;
current_depth = 0;
position = 0;
finish_limit_position = 1;
finish_limit[0] = 0;
}
__syncthreads();
// ============================== Shortest Path Calculation using curr source ======================
// ============================== Using Vertex Parallel ============================================
while(!done)
{ // wait
__syncthreads();
done = true;
__syncthreads();
// move through modes
for(int v=idx; v<nodes; v+=blockDim.x) {
if(d[v] == current_depth) {
// add to reverse_stack
int t = atomicAdd(&position,1);
reverse_stack[t] = v;
// move through neighbours
for(int r=R[v]; r<R[v+1]; r++) {
int w = C[r];
// if not visited
if(d[w] == INT_MAX) {
d[w] = d[v] + 1;
done = false;
}
// add number of paths
if(d[w] == (d[v] + 1)) {
atomicAdd(&sigma[w],sigma[v]);
}
}
}
}
__syncthreads();
// increment variables
if(idx == 0){
current_depth++;
finish_limit[finish_limit_position] = position;
++finish_limit_position;
}
}
// ============================== BC calculation using Brande's Algorithm ============================================
// Parallel Vertex Parallel implementation
// __syncthreads();
if(idx == 0){
finish_limit_position-=2;
// printf("%d %d %d<--", finish_limit_position, finish_limit[finish_limit_position], finish_limit[finish_limit_position+1]);
// for(int a1=0;a1<=finish_limit_position+1;++a1) printf("%d-", finish_limit[a1]);
// printf("\n");
// for(int a1=0;a1<nodes;++a1) printf("%d<", reverse_stack[a1]);
// cout<<"\n";
// printf("\n");
}
__syncthreads();
//atomicSub(&finish_limit_position,2);
for(int itr1 = finish_limit_position; itr1 >= 0; --itr1){
// __syncthreads();
for(int itr2 = finish_limit[itr1] + idx; itr2 < finish_limit[itr1+1]; itr2+=blockDim.x){
// reverse_stack[itr2] is one node
for(int itr3 = R[reverse_stack[itr2]]; itr3 < R[reverse_stack[itr2] + 1]; ++itr3){
int consider = C[itr3];
// C[itr3] other node
if(d[consider] == d[reverse_stack[itr2]]+1){
//atomicAdd(&delta[consider], ( ((float)sigma[consider]/sigma[reverse_stack[itr2]]) * ((float)1 + delta[reverse_stack[itr2]]) ));
delta[reverse_stack[itr2]] += ( ((float)sigma[reverse_stack[itr2]]/sigma[consider]) * ((float)1 + delta[consider]) );
}
}
if(reverse_stack[itr2] != s){
bc[reverse_stack[itr2]] += delta[reverse_stack[itr2]];
}
}
__syncthreads();
}
// Serialized Vertex Parallel implementation
// if(idx == 0){
// for(int itr1 = nodes - 1; itr1 >= 0; --itr1){
// for(int itr2 = R[reverse_stack[itr1]]; itr2 < R[reverse_stack[itr1] + 1]; ++itr2){
// int consider = C[itr2];
// if(d[consider] == d[reverse_stack[itr1]]-1){
// delta[consider] += ( ((float)sigma[consider]/sigma[reverse_stack[itr1]]) * ((float)1 + delta[reverse_stack[itr1]]) );
// }
// }
// if(reverse_stack[itr1] != s){
// bc[reverse_stack[itr1]] += delta[reverse_stack[itr1]];
// }
// }
// }
// increment
__syncthreads();
if (idx == 0) {
s += 1;
}
}
}
/**
* Main function
*/
int main () {
// ================================ READ INPUT AND MAKE Compressed Adjancency List ====================================
// freopen("graph", "r", stdin);
// nodes and edges
int nodes, edges;
cin>>nodes>>edges;
// compressed adjancency list
int * V = new int[nodes + 1];
int * E = new int[2 * edges];
// read graph data in CSR format
string line;
int node = 0;
int counter = 0;
getline(cin, line);
for (int i = 0; i < nodes; ++i) {
getline(cin, line);
V[node] = counter;
istringstream is(line);
int tmp;
while (is >> tmp) {
E[counter] = tmp;
counter += 1;
}
++node;
}
V[node] = counter;
// cout<<"\n";
// for (int i = 0; i <= nodes; i++) {
// cout<<V[i]<<" ";
// }
// cout<<"\n";
// for (int i = 0; i < 2 * edges; ++i) {
// cout<<E[i]<<" ";
// }
// cout<<"\n";
// ================================ DECLARE AND INIT VARIABLES ====================================
int *d = new int[nodes];
int *sigma = new int[nodes];
float *delta = new float[nodes];
float *bc = new float[nodes];
memset(bc,0,sizeof(bc));
int *d_d, *d_sigma, *d_V, *d_E, *d_reverse_stack, *d_end_point;
float *d_delta, *d_bc;
hipMalloc((void**)&d_d, sizeof(int) * nodes);
hipMalloc((void**)&d_end_point, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_sigma, sizeof(int) * nodes);
hipMalloc((void**)&d_reverse_stack, sizeof(int) * nodes);
hipMalloc((void**)&d_V, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_E, sizeof(int) * (2*edges));
hipMalloc((void**)&d_delta, sizeof(float) * nodes);
hipMalloc((void**)&d_bc, sizeof(float) * nodes);
hipMemcpy(d_V, V, sizeof(int) * (nodes+1), hipMemcpyHostToDevice);
hipMemcpy(d_E, E, sizeof(int) * (2*edges), hipMemcpyHostToDevice);
hipMemcpy(d_bc, bc, sizeof(float) * (nodes), hipMemcpyHostToDevice);
// cudaMemcpy(d_delta, delta, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// ================================ KERNEL PARAMS AND CALL ====================================
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// kernel call
betweenness_centrality_kernel <<<1, 1024>>> (nodes, d_E, d_V, d_d, d_sigma, d_delta, d_bc, d_reverse_stack, d_end_point);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// ================================ RESULT ====================================
// cudaMemcpy(d, d_d, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(sigma, d_sigma, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
hipMemcpy(bc, d_bc, sizeof(float) * nodes, hipMemcpyDeviceToHost);
// cudaMemcpy(delta, d_delta, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cout<<"Result: \n";
// for (int i = 0; i < nodes; i++) {
// cout<<"Node: "<<i<<" BC: "<<fixed<<setprecision(6)<<bc[i]/2.0<<"\n";
// }
cout<<"\n";
// Print the time for execution
cout<<"Execution time: "<<elapsed_time/1000.0<<endl;
// Maximum BC value
float max_bc = 0.0;
for (int i = 0; i < nodes; ++i) {
max_bc = (bc[i] > max_bc) ? bc[i] : max_bc;
}
cout<<"Max BC value: "<<max_bc/2.0<<endl;
// ================================ MEMORY RELEASE ====================================
hipFree(d_sigma);
hipFree(d_d);
hipFree(d_V);
hipFree(d_E);
hipFree(d_delta);
hipFree(d_bc);
hipFree(d_reverse_stack);
hipFree(d_end_point);
free(E);
free(V);
free(d);
free(sigma);
free(delta);
free(bc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Authors
- Dibyadarshan Hota 16CO154
- Omkar Prabhu 16CO233
*/
#include <iostream>
#include <stdio.h>
#include <sstream>
#include <string.h>
#include <hip/hip_runtime.h>
#define ll long long
using namespace std;
/**
* Kernel for computing Betweenness Centrality
* res: Stored in global memory variable bc
*/
__global__
void betweenness_centrality_kernel (int nodes, int *C, int *R, int *d, int *sigma, float *delta, float *bc, int *reverse_stack, int *finish_limit) {
// ================================== VARIABLES INIT ============================================
// initial variables
__shared__ int position;
__shared__ int s;
__shared__ int finish_limit_position;
// source variable initially 0
int idx = threadIdx.x;
if (idx == 0) {
s = 0;
}
__syncthreads();
// move through all nodes
while (s < nodes) {
__syncthreads();
// ============================== distance, delta and sigma INIT ============================================
for(int v=idx; v<nodes; v+=blockDim.x) {
if(v == s) {
d[v] = 0;
sigma[v] = 1;
}
else {
d[v] = INT_MAX;
sigma[v] = 0;
}
delta[v] = 0;
}
__syncthreads();
__shared__ int current_depth;
__shared__ bool done;
if(idx == 0) {
done = false;
current_depth = 0;
position = 0;
finish_limit_position = 1;
finish_limit[0] = 0;
}
__syncthreads();
// ============================== Shortest Path Calculation using curr source ======================
// ============================== Using Vertex Parallel ============================================
while(!done)
{ // wait
__syncthreads();
done = true;
__syncthreads();
// move through modes
for(int v=idx; v<nodes; v+=blockDim.x) {
if(d[v] == current_depth) {
// add to reverse_stack
int t = atomicAdd(&position,1);
reverse_stack[t] = v;
// move through neighbours
for(int r=R[v]; r<R[v+1]; r++) {
int w = C[r];
// if not visited
if(d[w] == INT_MAX) {
d[w] = d[v] + 1;
done = false;
}
// add number of paths
if(d[w] == (d[v] + 1)) {
atomicAdd(&sigma[w],sigma[v]);
}
}
}
}
__syncthreads();
// increment variables
if(idx == 0){
current_depth++;
finish_limit[finish_limit_position] = position;
++finish_limit_position;
}
}
// ============================== BC calculation using Brande's Algorithm ============================================
// Parallel Vertex Parallel implementation
// __syncthreads();
if(idx == 0){
finish_limit_position-=2;
// printf("%d %d %d<--", finish_limit_position, finish_limit[finish_limit_position], finish_limit[finish_limit_position+1]);
// for(int a1=0;a1<=finish_limit_position+1;++a1) printf("%d-", finish_limit[a1]);
// printf("\n");
// for(int a1=0;a1<nodes;++a1) printf("%d<", reverse_stack[a1]);
// cout<<"\n";
// printf("\n");
}
__syncthreads();
//atomicSub(&finish_limit_position,2);
for(int itr1 = finish_limit_position; itr1 >= 0; --itr1){
// __syncthreads();
for(int itr2 = finish_limit[itr1] + idx; itr2 < finish_limit[itr1+1]; itr2+=blockDim.x){
// reverse_stack[itr2] is one node
for(int itr3 = R[reverse_stack[itr2]]; itr3 < R[reverse_stack[itr2] + 1]; ++itr3){
int consider = C[itr3];
// C[itr3] other node
if(d[consider] == d[reverse_stack[itr2]]+1){
//atomicAdd(&delta[consider], ( ((float)sigma[consider]/sigma[reverse_stack[itr2]]) * ((float)1 + delta[reverse_stack[itr2]]) ));
delta[reverse_stack[itr2]] += ( ((float)sigma[reverse_stack[itr2]]/sigma[consider]) * ((float)1 + delta[consider]) );
}
}
if(reverse_stack[itr2] != s){
bc[reverse_stack[itr2]] += delta[reverse_stack[itr2]];
}
}
__syncthreads();
}
// Serialized Vertex Parallel implementation
// if(idx == 0){
// for(int itr1 = nodes - 1; itr1 >= 0; --itr1){
// for(int itr2 = R[reverse_stack[itr1]]; itr2 < R[reverse_stack[itr1] + 1]; ++itr2){
// int consider = C[itr2];
// if(d[consider] == d[reverse_stack[itr1]]-1){
// delta[consider] += ( ((float)sigma[consider]/sigma[reverse_stack[itr1]]) * ((float)1 + delta[reverse_stack[itr1]]) );
// }
// }
// if(reverse_stack[itr1] != s){
// bc[reverse_stack[itr1]] += delta[reverse_stack[itr1]];
// }
// }
// }
// increment
__syncthreads();
if (idx == 0) {
s += 1;
}
}
}
/**
* Main function
*/
int main () {
// ================================ READ INPUT AND MAKE Compressed Adjancency List ====================================
// freopen("graph", "r", stdin);
// nodes and edges
int nodes, edges;
cin>>nodes>>edges;
// compressed adjancency list
int * V = new int[nodes + 1];
int * E = new int[2 * edges];
// read graph data in CSR format
string line;
int node = 0;
int counter = 0;
getline(cin, line);
for (int i = 0; i < nodes; ++i) {
getline(cin, line);
V[node] = counter;
istringstream is(line);
int tmp;
while (is >> tmp) {
E[counter] = tmp;
counter += 1;
}
++node;
}
V[node] = counter;
// cout<<"\n";
// for (int i = 0; i <= nodes; i++) {
// cout<<V[i]<<" ";
// }
// cout<<"\n";
// for (int i = 0; i < 2 * edges; ++i) {
// cout<<E[i]<<" ";
// }
// cout<<"\n";
// ================================ DECLARE AND INIT VARIABLES ====================================
int *d = new int[nodes];
int *sigma = new int[nodes];
float *delta = new float[nodes];
float *bc = new float[nodes];
memset(bc,0,sizeof(bc));
int *d_d, *d_sigma, *d_V, *d_E, *d_reverse_stack, *d_end_point;
float *d_delta, *d_bc;
hipMalloc((void**)&d_d, sizeof(int) * nodes);
hipMalloc((void**)&d_end_point, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_sigma, sizeof(int) * nodes);
hipMalloc((void**)&d_reverse_stack, sizeof(int) * nodes);
hipMalloc((void**)&d_V, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_E, sizeof(int) * (2*edges));
hipMalloc((void**)&d_delta, sizeof(float) * nodes);
hipMalloc((void**)&d_bc, sizeof(float) * nodes);
hipMemcpy(d_V, V, sizeof(int) * (nodes+1), hipMemcpyHostToDevice);
hipMemcpy(d_E, E, sizeof(int) * (2*edges), hipMemcpyHostToDevice);
hipMemcpy(d_bc, bc, sizeof(float) * (nodes), hipMemcpyHostToDevice);
// cudaMemcpy(d_delta, delta, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// ================================ KERNEL PARAMS AND CALL ====================================
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// kernel call
betweenness_centrality_kernel <<<1, 1024>>> (nodes, d_E, d_V, d_d, d_sigma, d_delta, d_bc, d_reverse_stack, d_end_point);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// ================================ RESULT ====================================
// cudaMemcpy(d, d_d, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(sigma, d_sigma, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
hipMemcpy(bc, d_bc, sizeof(float) * nodes, hipMemcpyDeviceToHost);
// cudaMemcpy(delta, d_delta, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cout<<"Result: \n";
// for (int i = 0; i < nodes; i++) {
// cout<<"Node: "<<i<<" BC: "<<fixed<<setprecision(6)<<bc[i]/2.0<<"\n";
// }
cout<<"\n";
// Print the time for execution
cout<<"Execution time: "<<elapsed_time/1000.0<<endl;
// Maximum BC value
float max_bc = 0.0;
for (int i = 0; i < nodes; ++i) {
max_bc = (bc[i] > max_bc) ? bc[i] : max_bc;
}
cout<<"Max BC value: "<<max_bc/2.0<<endl;
// ================================ MEMORY RELEASE ====================================
hipFree(d_sigma);
hipFree(d_d);
hipFree(d_V);
hipFree(d_E);
hipFree(d_delta);
hipFree(d_bc);
hipFree(d_reverse_stack);
hipFree(d_end_point);
free(E);
free(V);
free(d);
free(sigma);
free(delta);
free(bc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.globl _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.p2align 8
.type _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_,@function
_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_:
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1 offset:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v17, 0
s_load_b32 s24, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v17 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s24, v1
s_cbranch_vccnz .LBB0_43
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b256 s[12:19], s[0:1], 0x28
v_cmp_gt_i32_e64 s3, s24, v0
s_add_u32 s20, s0, 0x48
s_addc_u32 s21, s1, 0
s_mov_b32 s23, 0
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
ds_load_b32 v1, v17 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s24, v1
s_cbranch_vccz .LBB0_43
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_8
s_load_b32 s0, s[20:21], 0xc
ds_load_b32 v3, v17 offset:4
v_mov_b32_e32 v1, v0
s_mov_b32 s25, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s22, s0, 0xffff
.p2align 6
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u32_e32 vcc_lo, v3, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s22, v1
v_cndmask_b32_e64 v10, 0x7fffffff, 0, vcc_lo
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s24, v1
v_add_co_u32 v6, s0, s8, v4
v_add_co_ci_u32_e64 v7, s0, s9, v5, s0
v_add_co_u32 v8, s0, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s11, v5, s0
v_add_co_u32 v4, s0, s12, v4
v_add_co_ci_u32_e64 v5, s0, s13, v5, s0
s_or_b32 s25, vcc_lo, s25
global_store_b32 v[6:7], v10, off
global_store_b32 v[8:9], v2, off
global_store_b32 v[4:5], v17, off
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 1
ds_store_b32 v17, v17
ds_store_b64 v17, v[1:2] offset:8
ds_store_b8 v17, v2 offset:16
global_store_b32 v17, v17, s[18:19]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_u8 v1, v17 offset:16
s_waitcnt lgkmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_28
.LBB0_11:
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_13
ds_load_b32 v1, v17 offset:8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, -2, v1
ds_store_b32 v17, v1 offset:8
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v17 offset:8
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 0, v1
v_readfirstlane_b32 s22, v1
s_cbranch_vccz .LBB0_17
.LBB0_14:
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_4
ds_load_b32 v1, v17 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v17, v1 offset:4
s_branch .LBB0_4
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s0, s22, -1
s_cmp_lt_i32 s22, 1
s_mov_b32 s22, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_17:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[22:23], 2
s_add_u32 s0, s18, s0
s_addc_u32 s1, s19, s1
global_load_b64 v[1:2], v17, s[0:1]
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v3, v2
s_cbranch_execz .LBB0_16
s_load_b32 s0, s[20:21], 0xc
ds_load_b32 v1, v17 offset:4
s_mov_b32 s26, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s25, s0, 0xffff
s_branch .LBB0_20
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, s25, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v2
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_16
.LBB0_20:
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s27, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s16, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
global_load_b32 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v5, vcc_lo
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v7, v8
s_cbranch_execz .LBB0_25
v_add_co_u32 v9, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v5, vcc_lo
v_ashrrev_i32_e32 v12, 31, v7
s_mov_b32 s28, 0
global_load_b32 v15, v[9:10], off
v_mov_b32_e32 v11, v7
v_add_co_u32 v9, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v18, 1, v15
v_lshlrev_b64 v[13:14], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_branch .LBB0_23
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v7, 1, v7
v_add_co_u32 v13, s0, v13, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v14, s0, 0, v14, s0
v_cmp_ge_i32_e32 vcc_lo, v7, v8
s_or_b32 s28, vcc_lo, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execz .LBB0_25
.LBB0_23:
global_load_b32 v15, v[13:14], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v19, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v16, vcc_lo
global_load_b32 v19, v[19:20], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v19, v18
s_cbranch_execz .LBB0_22
v_add_co_u32 v19, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v20, vcc_lo, s11, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s12, v15
s_clause 0x1
global_load_b32 v21, v[9:10], off
global_load_b32 v19, v[19:20], off
v_add_co_ci_u32_e32 v16, vcc_lo, s13, v16, vcc_lo
s_clause 0x1
global_load_b32 v15, v[15:16], off
global_load_b32 v16, v[11:12], off
s_waitcnt vmcnt(3)
v_cvt_f32_i32_e32 v20, v21
s_waitcnt vmcnt(2)
v_cvt_f32_i32_e32 v19, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_scale_f32 v21, null, v19, v19, v20
v_div_scale_f32 v24, vcc_lo, v20, v19, v20
s_waitcnt vmcnt(1)
v_add_f32_e32 v15, 1.0, v15
v_rcp_f32_e32 v22, v21
s_waitcnt_depctr 0xfff
v_fma_f32 v23, -v21, v22, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v22, v23, v22
v_mul_f32_e32 v23, v24, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v25, -v21, v23, v24
v_fmac_f32_e32 v23, v25, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v21, -v21, v23, v24
v_div_fmas_f32 v21, v21, v22, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v19, v21, v19, v20
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v16, v19, v15
global_store_b32 v[11:12], v16, off
s_branch .LBB0_22
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e64 v6, v1
s_cbranch_execz .LBB0_19
v_add_co_u32 v6, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s14, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
s_branch .LBB0_19
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s0
ds_load_u8 v1, v17 offset:16
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_11
.LBB0_28:
v_mov_b32_e32 v1, 1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_store_b8 v17, v1 offset:16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_41
s_load_b32 s0, s[20:21], 0xc
ds_load_b32 v15, v17
v_mov_b32_e32 v1, v0
s_mov_b32 s25, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s22, s0, 0xffff
s_branch .LBB0_31
.LBB0_30:
s_or_b32 exec_lo, exec_lo, s26
v_add_nc_u32_e32 v1, s22, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s24, v1
s_or_b32 s25, vcc_lo, s25
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execz .LBB0_41
.LBB0_31:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s26, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v9, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v4, v15
s_cbranch_execz .LBB0_30
s_mov_b32 s27, exec_lo
s_mov_b32 s0, exec_lo
v_mbcnt_lo_u32_b32 v4, s27, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_34
s_bcnt1_i32_b32 s27, s27
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s27
ds_add_rtn_u32 v5, v17, v5 offset:12
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s0, v4
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s16, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s17, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo
global_store_b32 v[6:7], v1, off
global_load_b64 v[6:7], v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v6, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_30
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s27, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v9, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v11, vcc_lo
s_branch .LBB0_37
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v11, v[4:5], off offset:4
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v9, s0, v9, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v6, v11
s_or_b32 s27, vcc_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_30
.LBB0_37:
global_load_b32 v11, v[9:10], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s8, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v12, vcc_lo
global_load_b32 v16, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0x7fffffff, v16
s_cbranch_execz .LBB0_39
global_load_b32 v16, v[2:3], off
v_mov_b32_e32 v18, 0
ds_store_b8 v17, v18 offset:16
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v16, 1, v16
global_store_b32 v[13:14], v16, off
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_load_b32 v16, v[2:3], off
global_load_b32 v13, v[13:14], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v14, 1, v16
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 v13, v14
s_cbranch_execz .LBB0_36
global_load_b32 v13, v[7:8], off
v_add_co_u32 v11, vcc_lo, s10, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
s_waitcnt vmcnt(0)
global_atomic_add_u32 v[11:12], v13, off
s_branch .LBB0_36
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_27
ds_load_2addr_b32 v[1:2], v17 offset1:2
ds_load_b32 v5, v17 offset:12
s_waitcnt lgkmcnt(1)
v_ashrrev_i32_e32 v4, 31, v2
v_dual_mov_b32 v3, v2 :: v_dual_add_nc_u32 v2, 1, v2
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
ds_store_2addr_b32 v17, v1, v2 offset1:2
v_add_co_u32 v3, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
s_waitcnt lgkmcnt(1)
global_store_b32 v[3:4], v5, off
s_branch .LBB0_27
.LBB0_43:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.amdhsa_group_segment_fixed_size 20
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 29
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, .Lfunc_end0-_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 31
.sgpr_spill_count: 0
.symbol: _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Authors
- Dibyadarshan Hota 16CO154
- Omkar Prabhu 16CO233
*/
#include <iostream>
#include <stdio.h>
#include <sstream>
#include <string.h>
#include <hip/hip_runtime.h>
#define ll long long
using namespace std;
/**
* Kernel for computing Betweenness Centrality
* res: Stored in global memory variable bc
*/
__global__
void betweenness_centrality_kernel (int nodes, int *C, int *R, int *d, int *sigma, float *delta, float *bc, int *reverse_stack, int *finish_limit) {
// ================================== VARIABLES INIT ============================================
// initial variables
__shared__ int position;
__shared__ int s;
__shared__ int finish_limit_position;
// source variable initially 0
int idx = threadIdx.x;
if (idx == 0) {
s = 0;
}
__syncthreads();
// move through all nodes
while (s < nodes) {
__syncthreads();
// ============================== distance, delta and sigma INIT ============================================
for(int v=idx; v<nodes; v+=blockDim.x) {
if(v == s) {
d[v] = 0;
sigma[v] = 1;
}
else {
d[v] = INT_MAX;
sigma[v] = 0;
}
delta[v] = 0;
}
__syncthreads();
__shared__ int current_depth;
__shared__ bool done;
if(idx == 0) {
done = false;
current_depth = 0;
position = 0;
finish_limit_position = 1;
finish_limit[0] = 0;
}
__syncthreads();
// ============================== Shortest Path Calculation using curr source ======================
// ============================== Using Vertex Parallel ============================================
while(!done)
{ // wait
__syncthreads();
done = true;
__syncthreads();
// move through modes
for(int v=idx; v<nodes; v+=blockDim.x) {
if(d[v] == current_depth) {
// add to reverse_stack
int t = atomicAdd(&position,1);
reverse_stack[t] = v;
// move through neighbours
for(int r=R[v]; r<R[v+1]; r++) {
int w = C[r];
// if not visited
if(d[w] == INT_MAX) {
d[w] = d[v] + 1;
done = false;
}
// add number of paths
if(d[w] == (d[v] + 1)) {
atomicAdd(&sigma[w],sigma[v]);
}
}
}
}
__syncthreads();
// increment variables
if(idx == 0){
current_depth++;
finish_limit[finish_limit_position] = position;
++finish_limit_position;
}
}
// ============================== BC calculation using Brande's Algorithm ============================================
// Parallel Vertex Parallel implementation
// __syncthreads();
if(idx == 0){
finish_limit_position-=2;
// printf("%d %d %d<--", finish_limit_position, finish_limit[finish_limit_position], finish_limit[finish_limit_position+1]);
// for(int a1=0;a1<=finish_limit_position+1;++a1) printf("%d-", finish_limit[a1]);
// printf("\n");
// for(int a1=0;a1<nodes;++a1) printf("%d<", reverse_stack[a1]);
// cout<<"\n";
// printf("\n");
}
__syncthreads();
//atomicSub(&finish_limit_position,2);
for(int itr1 = finish_limit_position; itr1 >= 0; --itr1){
// __syncthreads();
for(int itr2 = finish_limit[itr1] + idx; itr2 < finish_limit[itr1+1]; itr2+=blockDim.x){
// reverse_stack[itr2] is one node
for(int itr3 = R[reverse_stack[itr2]]; itr3 < R[reverse_stack[itr2] + 1]; ++itr3){
int consider = C[itr3];
// C[itr3] other node
if(d[consider] == d[reverse_stack[itr2]]+1){
//atomicAdd(&delta[consider], ( ((float)sigma[consider]/sigma[reverse_stack[itr2]]) * ((float)1 + delta[reverse_stack[itr2]]) ));
delta[reverse_stack[itr2]] += ( ((float)sigma[reverse_stack[itr2]]/sigma[consider]) * ((float)1 + delta[consider]) );
}
}
if(reverse_stack[itr2] != s){
bc[reverse_stack[itr2]] += delta[reverse_stack[itr2]];
}
}
__syncthreads();
}
// Serialized Vertex Parallel implementation
// if(idx == 0){
// for(int itr1 = nodes - 1; itr1 >= 0; --itr1){
// for(int itr2 = R[reverse_stack[itr1]]; itr2 < R[reverse_stack[itr1] + 1]; ++itr2){
// int consider = C[itr2];
// if(d[consider] == d[reverse_stack[itr1]]-1){
// delta[consider] += ( ((float)sigma[consider]/sigma[reverse_stack[itr1]]) * ((float)1 + delta[reverse_stack[itr1]]) );
// }
// }
// if(reverse_stack[itr1] != s){
// bc[reverse_stack[itr1]] += delta[reverse_stack[itr1]];
// }
// }
// }
// increment
__syncthreads();
if (idx == 0) {
s += 1;
}
}
}
/**
* Main function
*/
int main () {
// ================================ READ INPUT AND MAKE Compressed Adjancency List ====================================
// freopen("graph", "r", stdin);
// nodes and edges
int nodes, edges;
cin>>nodes>>edges;
// compressed adjancency list
int * V = new int[nodes + 1];
int * E = new int[2 * edges];
// read graph data in CSR format
string line;
int node = 0;
int counter = 0;
getline(cin, line);
for (int i = 0; i < nodes; ++i) {
getline(cin, line);
V[node] = counter;
istringstream is(line);
int tmp;
while (is >> tmp) {
E[counter] = tmp;
counter += 1;
}
++node;
}
V[node] = counter;
// cout<<"\n";
// for (int i = 0; i <= nodes; i++) {
// cout<<V[i]<<" ";
// }
// cout<<"\n";
// for (int i = 0; i < 2 * edges; ++i) {
// cout<<E[i]<<" ";
// }
// cout<<"\n";
// ================================ DECLARE AND INIT VARIABLES ====================================
int *d = new int[nodes];
int *sigma = new int[nodes];
float *delta = new float[nodes];
float *bc = new float[nodes];
memset(bc,0,sizeof(bc));
int *d_d, *d_sigma, *d_V, *d_E, *d_reverse_stack, *d_end_point;
float *d_delta, *d_bc;
hipMalloc((void**)&d_d, sizeof(int) * nodes);
hipMalloc((void**)&d_end_point, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_sigma, sizeof(int) * nodes);
hipMalloc((void**)&d_reverse_stack, sizeof(int) * nodes);
hipMalloc((void**)&d_V, sizeof(int) * (nodes + 1));
hipMalloc((void**)&d_E, sizeof(int) * (2*edges));
hipMalloc((void**)&d_delta, sizeof(float) * nodes);
hipMalloc((void**)&d_bc, sizeof(float) * nodes);
hipMemcpy(d_V, V, sizeof(int) * (nodes+1), hipMemcpyHostToDevice);
hipMemcpy(d_E, E, sizeof(int) * (2*edges), hipMemcpyHostToDevice);
hipMemcpy(d_bc, bc, sizeof(float) * (nodes), hipMemcpyHostToDevice);
// cudaMemcpy(d_delta, delta, sizeof(float) * (nodes), cudaMemcpyHostToDevice);
// ================================ KERNEL PARAMS AND CALL ====================================
float elapsed_time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// kernel call
betweenness_centrality_kernel <<<1, 1024>>> (nodes, d_E, d_V, d_d, d_sigma, d_delta, d_bc, d_reverse_stack, d_end_point);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed_time, start, stop);
// ================================ RESULT ====================================
// cudaMemcpy(d, d_d, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
// cudaMemcpy(sigma, d_sigma, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
hipMemcpy(bc, d_bc, sizeof(float) * nodes, hipMemcpyDeviceToHost);
// cudaMemcpy(delta, d_delta, sizeof(float) * nodes, cudaMemcpyDeviceToHost);
cout<<"Result: \n";
// for (int i = 0; i < nodes; i++) {
// cout<<"Node: "<<i<<" BC: "<<fixed<<setprecision(6)<<bc[i]/2.0<<"\n";
// }
cout<<"\n";
// Print the time for execution
cout<<"Execution time: "<<elapsed_time/1000.0<<endl;
// Maximum BC value
float max_bc = 0.0;
for (int i = 0; i < nodes; ++i) {
max_bc = (bc[i] > max_bc) ? bc[i] : max_bc;
}
cout<<"Max BC value: "<<max_bc/2.0<<endl;
// ================================ MEMORY RELEASE ====================================
hipFree(d_sigma);
hipFree(d_d);
hipFree(d_V);
hipFree(d_E);
hipFree(d_delta);
hipFree(d_bc);
hipFree(d_reverse_stack);
hipFree(d_end_point);
free(E);
free(V);
free(d);
free(sigma);
free(delta);
free(bc);
return 0;
} | .text
.file "main_vertex_parallel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_ # -- Begin function _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.p2align 4, 0x90
.type _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_,@function
_Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_: # @_Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, .Lfunc_end0-_Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.LCPI1_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 720
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rsi
movq %rax, %rdi
callq _ZNSirsERi
movslq 8(%rsp), %rax
cmpq $-1, %rax
leaq 4(,%rax,4), %rdi
movq $-1, %rbx
cmovlq %rbx, %rdi
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, 16(%rsp) # 8-byte Spill
movslq 12(%rsp), %rax
leaq (,%rax,8), %rdi
testq %rax, %rax
cmovsq %rbx, %rdi
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, 32(%rsp) # 8-byte Spill
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq _ZSt3cin+240(%rax), %r14
testq %r14, %r14
je .LBB1_1
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB1_7
.LBB1_5:
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp1:
# %bb.6: # %.noexc62
movq (%r14), %rax
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp3:
.LBB1_7: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp4:
.cfi_escape 0x2e, 0x00
movsbl %al, %edx
leaq 144(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp5:
# %bb.8: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit.preheader
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_9
# %bb.43: # %.lr.ph
xorl %r15d, %r15d
leaq 144(%rsp), %r13
leaq 272(%rsp), %rbp
leaq 72(%rsp), %r14
xorl %r12d, %r12d
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_63: # %_ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
# in Loop: Header=BB1_44 Depth=1
incq %r15
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 288(%rsp)
.cfi_escape 0x2e, 0x00
leaq 344(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+8(%rip), %rax
movq %rax, 272(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rcx
movq %rcx, 272(%rsp,%rax)
movq $0, 280(%rsp)
.cfi_escape 0x2e, 0x00
leaq 392(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movl 8(%rsp), %eax
cmpl %r15d, %eax
jle .LBB1_10
.LBB1_44: # =>This Loop Header: Depth=1
# Child Loop BB1_54 Depth 2
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq _ZSt3cin+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_45
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
# in Loop: Header=BB1_44 Depth=1
cmpb $0, 56(%rbx)
je .LBB1_49
# %bb.48: # in Loop: Header=BB1_44 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB1_51
.p2align 4, 0x90
.LBB1_49: # in Loop: Header=BB1_44 Depth=1
.Ltmp6:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.50: # %.noexc71
# in Loop: Header=BB1_44 Depth=1
movq (%rbx), %rax
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp9:
.LBB1_51: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i68
# in Loop: Header=BB1_44 Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movsbl %al, %edx
movl $_ZSt3cin, %edi
movq %r13, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp11:
# %bb.52: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit74
# in Loop: Header=BB1_44 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl %r12d, (%rax,%r15,4)
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %r13, %rsi
movl $8, %edx
callq _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEC1ERKNS_12basic_stringIcS2_S3_EESt13_Ios_Openmode
.Ltmp14:
# %bb.53: # in Loop: Header=BB1_44 Depth=1
movslq %r12d, %rax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
.p2align 4, 0x90
.LBB1_54: # Parent Loop BB1_44 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movq %r14, %rsi
callq _ZNSirsERi
.Ltmp17:
# %bb.55: # in Loop: Header=BB1_54 Depth=2
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB1_61
# %bb.56: # in Loop: Header=BB1_54 Depth=2
movl 72(%rsp), %eax
movl %eax, (%rbx)
incl %r12d
addq $4, %rbx
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_61: # in Loop: Header=BB1_44 Depth=1
movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 272(%rsp)
movq -24(%rax), %rax
movq _ZTTNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq %rcx, 272(%rsp,%rax)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 288(%rsp)
movq 360(%rsp), %rdi
leaq 376(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_63
# %bb.62: # %.critedge.i.i.i.i.i
# in Loop: Header=BB1_44 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_63
.LBB1_9:
xorl %r12d, %r12d
xorl %r15d, %r15d
.LBB1_10: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit._crit_edge
movl %r15d, %ecx
movq 16(%rsp), %rdx # 8-byte Reload
movl %r12d, (%rdx,%rcx,4)
cltq
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %rbp
cmovnsq %r14, %rbp
.Ltmp19:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _Znam
.Ltmp20:
# %bb.11:
.Ltmp22:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _Znam
.Ltmp23:
# %bb.12:
.Ltmp25:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _Znam
.Ltmp26:
# %bb.13:
.Ltmp28:
movq %rax, %r13
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _Znam
.Ltmp29:
# %bb.14:
movq %rax, %rbp
movq $0, (%rax)
.Ltmp31:
.cfi_escape 0x2e, 0x00
leaq 136(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp32:
# %bb.15:
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
callq hipMalloc
.Ltmp34:
# %bb.16:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
callq hipMalloc
.Ltmp36:
# %bb.17:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
callq hipMalloc
.Ltmp38:
# %bb.18:
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rsi
.Ltmp39:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipMalloc
.Ltmp40:
# %bb.19:
movslq 12(%rsp), %rsi
shlq $3, %rsi
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipMalloc
.Ltmp42:
# %bb.20:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp43:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
callq hipMalloc
.Ltmp44:
# %bb.21:
movslq 8(%rsp), %rsi
shlq $2, %rsi
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipMalloc
.Ltmp46:
# %bb.22:
movq 56(%rsp), %rdi
movslq 8(%rsp), %rax
leaq 4(,%rax,4), %rdx
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp48:
# %bb.23:
movq 48(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $3, %rdx
.Ltmp49:
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
.Ltmp50:
# %bb.24:
movq 24(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
.Ltmp51:
.cfi_escape 0x2e, 0x00
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp52:
# %bb.25:
.Ltmp54:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq hipEventCreate
.Ltmp55:
# %bb.26:
.Ltmp56:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.Ltmp57:
# %bb.27:
movq 96(%rsp), %rdi
.Ltmp58:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp59:
# %bb.28:
.Ltmp60:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp61:
# %bb.29:
testl %eax, %eax
jne .LBB1_32
# %bb.30:
movl 8(%rsp), %eax
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movq 136(%rsp), %rsi
movq 128(%rsp), %rdi
movq 104(%rsp), %r8
movq 24(%rsp), %r9
movq 120(%rsp), %r10
movq 112(%rsp), %r11
movl %eax, 68(%rsp)
movq %rcx, 264(%rsp)
movq %rdx, 256(%rsp)
movq %rsi, 248(%rsp)
movq %rdi, 240(%rsp)
movq %r8, 232(%rsp)
movq %r9, 224(%rsp)
movq %r10, 216(%rsp)
movq %r11, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 272(%rsp)
leaq 264(%rsp), %rax
movq %rax, 280(%rsp)
leaq 256(%rsp), %rax
movq %rax, 288(%rsp)
leaq 248(%rsp), %rax
movq %rax, 296(%rsp)
leaq 240(%rsp), %rax
movq %rax, 304(%rsp)
leaq 232(%rsp), %rax
movq %rax, 312(%rsp)
leaq 224(%rsp), %rax
movq %rax, 320(%rsp)
leaq 216(%rsp), %rax
movq %rax, 328(%rsp)
leaq 208(%rsp), %rax
movq %rax, 336(%rsp)
.Ltmp62:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp63:
# %bb.31: # %.noexc75
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
.Ltmp64:
.cfi_escape 0x2e, 0x10
leaq 272(%rsp), %r9
movl $_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp65:
.LBB1_32:
movq 40(%rsp), %rdi
.Ltmp66:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp67:
# %bb.33:
movq 40(%rsp), %rdi
.Ltmp68:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp69:
# %bb.34:
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
.Ltmp70:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp71:
# %bb.35:
movq 24(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
.Ltmp72:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp73:
# %bb.36:
.Ltmp74:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp75:
# %bb.37: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp76:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp77:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit79
.Ltmp78:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp79:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit81
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
.Ltmp80:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp81:
# %bb.40: # %_ZNSolsEd.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .LBB1_41
# %bb.71: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%rbx)
je .LBB1_73
# %bb.72:
movzbl 67(%rbx), %eax
jmp .LBB1_75
.LBB1_73:
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp83:
# %bb.74: # %.noexc99
movq (%rbx), %rax
.Ltmp84:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp85:
.LBB1_75: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i96
.Ltmp86:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp87:
# %bb.76: # %.noexc101
.Ltmp88:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp89:
# %bb.77: # %_ZNSolsEPFRSoS_E.exit.preheader
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_78
# %bb.84: # %_ZNSolsEPFRSoS_E.exit.preheader139
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_85: # %_ZNSolsEPFRSoS_E.exit
# =>This Inner Loop Header: Depth=1
movapd %xmm0, %xmm1
movss (%rbp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
maxss %xmm1, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB1_85
# %bb.79: # %_ZNSolsEPFRSoS_E.exit._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
jmp .LBB1_80
.LBB1_78:
xorpd %xmm0, %xmm0
.LBB1_80: # %_ZNSolsEPFRSoS_E.exit._crit_edge
movsd %xmm0, 88(%rsp) # 8-byte Spill
.Ltmp90:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp91:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit85
.Ltmp92:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp93:
# %bb.82: # %_ZNSolsEd.exit87
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .LBB1_83
# %bb.87: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%rbx)
je .LBB1_89
# %bb.88:
movzbl 67(%rbx), %eax
jmp .LBB1_91
.LBB1_89:
.Ltmp94:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp95:
# %bb.90: # %.noexc109
movq (%rbx), %rax
.Ltmp96:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp97:
.LBB1_91: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i106
.Ltmp98:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp99:
# %bb.92: # %.noexc111
.Ltmp100:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp101:
# %bb.93: # %_ZNSolsEPFRSoS_E.exit89
movq 128(%rsp), %rdi
.Ltmp102:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp103:
# %bb.94:
movq 136(%rsp), %rdi
.Ltmp104:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp105:
# %bb.95:
movq 56(%rsp), %rdi
.Ltmp106:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp107:
# %bb.96:
movq 48(%rsp), %rdi
.Ltmp108:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp109:
# %bb.97:
movq 104(%rsp), %rdi
.Ltmp110:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp111:
# %bb.98:
movq 24(%rsp), %rdi
.Ltmp112:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp113:
# %bb.99:
movq 120(%rsp), %rdi
.Ltmp114:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp115:
# %bb.100:
movq 112(%rsp), %rdi
.Ltmp116:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp117:
# %bb.101:
.cfi_escape 0x2e, 0x00
movq 32(%rsp), %rdi # 8-byte Reload
callq free
.cfi_escape 0x2e, 0x00
movq 16(%rsp), %rdi # 8-byte Reload
callq free
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq free
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq free
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_103
# %bb.102: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_103: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $664, %rsp # imm = 0x298
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_45:
.cfi_def_cfa_offset 720
.Ltmp124:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp125:
# %bb.46: # %.noexc70
.LBB1_1:
.Ltmp127:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp128:
# %bb.2: # %.noexc
.LBB1_41:
.Ltmp121:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp122:
# %bb.70: # %.noexc98
.LBB1_83:
.Ltmp118:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp119:
# %bb.86: # %.noexc108
.LBB1_67:
.Ltmp30:
jmp .LBB1_105
.LBB1_66:
.Ltmp27:
jmp .LBB1_105
.LBB1_65:
.Ltmp24:
jmp .LBB1_105
.LBB1_64:
.Ltmp21:
jmp .LBB1_105
.LBB1_42:
.Ltmp129:
jmp .LBB1_105
.LBB1_68:
.Ltmp53:
jmp .LBB1_105
.LBB1_104:
.Ltmp120:
jmp .LBB1_105
.LBB1_69:
.Ltmp123:
jmp .LBB1_105
.LBB1_59:
.Ltmp15:
jmp .LBB1_105
.LBB1_58: # %.loopexit.split-lp
.Ltmp126:
jmp .LBB1_105
.LBB1_57: # %.loopexit
.Ltmp12:
.LBB1_105:
movq %rax, %rbx
jmp .LBB1_106
.LBB1_60:
.Ltmp18:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 272(%rsp), %rdi
callq _ZNSt7__cxx1119basic_istringstreamIcSt11char_traitsIcESaIcEED1Ev
.LBB1_106:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_108
# %bb.107: # %.critedge.i.i90
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_108: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit92
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp129-.Lfunc_begin0 # jumps to .Ltmp129
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp11-.Ltmp6 # Call between .Ltmp6 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp26-.Ltmp25 # Call between .Ltmp25 and .Ltmp26
.uleb128 .Ltmp27-.Lfunc_begin0 # jumps to .Ltmp27
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp52-.Ltmp31 # Call between .Ltmp31 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp89-.Ltmp54 # Call between .Ltmp54 and .Ltmp89
.uleb128 .Ltmp123-.Lfunc_begin0 # jumps to .Ltmp123
.byte 0 # On action: cleanup
.uleb128 .Ltmp90-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp117-.Ltmp90 # Call between .Ltmp90 and .Ltmp117
.uleb128 .Ltmp120-.Lfunc_begin0 # jumps to .Ltmp120
.byte 0 # On action: cleanup
.uleb128 .Ltmp124-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp125-.Ltmp124 # Call between .Ltmp124 and .Ltmp125
.uleb128 .Ltmp126-.Lfunc_begin0 # jumps to .Ltmp126
.byte 0 # On action: cleanup
.uleb128 .Ltmp127-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp128-.Ltmp127 # Call between .Ltmp127 and .Ltmp128
.uleb128 .Ltmp129-.Lfunc_begin0 # jumps to .Ltmp129
.byte 0 # On action: cleanup
.uleb128 .Ltmp121-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp122-.Ltmp121 # Call between .Ltmp121 and .Ltmp122
.uleb128 .Ltmp123-.Lfunc_begin0 # jumps to .Ltmp123
.byte 0 # On action: cleanup
.uleb128 .Ltmp118-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp119-.Ltmp118 # Call between .Ltmp118 and .Ltmp119
.uleb128 .Ltmp120-.Lfunc_begin0 # jumps to .Ltmp120
.byte 0 # On action: cleanup
.uleb128 .Ltmp119-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Lfunc_end1-.Ltmp119 # Call between .Ltmp119 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_,@object # @_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.section .rodata,"a",@progbits
.globl _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.p2align 3, 0x0
_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_:
.quad _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.size _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: \n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Execution time: "
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max BC value: "
.size .L.str.3, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z29betweenness_centrality_kerneliPiS_S_S_PfS0_S_S_
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
cudaMalloc(&rowArr, sizeOfMatrix*sizeof(int));
cudaMalloc(&colArr, numOfNumbers*sizeof(int));
cudaMalloc(&valueArr, numOfNumbers*sizeof(double));
cudaMalloc(&xArr, sizeOfMatrix*sizeof(double));
cudaMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(valueArr, values, numOfNumbers*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(xArr, x, sizeOfMatrix*sizeof(double), cudaMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
cudaThreadSynchronize();
}
cudaMemcpy(x, xArr, sizeOfMatrix*sizeof(double), cudaMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
cudaFree(rowArr);
cudaFree(colArr);
cudaFree(valueArr);
cudaFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} | code for sm_80
Function : _Z10calculateXPiS_PdS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R0, c[0x0][0x0] ; /* 0x0000000000007b06 */
/* 0x000e220000209000 */
/*0020*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0030*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ BSSY B0, 0x4d0 ; /* 0x0000047000007945 */
/* 0x000fe80003800000 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00a0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x004fc800078e0a03 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.HI.U32 R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a27 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R0, R4, R5, c[0x0][0x180] ; /* 0x0000600004007624 */
/* 0x000fca00078e0205 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R7, R3, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R5, R0, c[0x0][0x180] ; /* 0x0000600005007624 */
/* 0x000fe200078e0200 */
/*01a0*/ IADD3 R5, R8, -0x1, RZ ; /* 0xffffffff08057810 */
/* 0x002fc80007ffe0ff */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R0.reuse, R8, PT ; /* 0x000000080000720c */
/* 0x040fe40003f04070 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fd60003f24070 */
/*01d0*/ @!P0 IMAD.MOV R7, RZ, RZ, R3 ; /* 0x000000ffff078224 */
/* 0x000fca00078e0203 */
/*01e0*/ ISETP.GE.AND P0, PT, R7.reuse, 0x1, PT ; /* 0x000000010700780c */
/* 0x040fe40003f06270 */
/*01f0*/ SEL R3, R7, R3, P1 ; /* 0x0000000307037207 */
/* 0x000fca0000800000 */
/*0200*/ IMAD R8, R3, R8, RZ ; /* 0x0000000803087224 */
/* 0x000fe400078e02ff */
/*0210*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fc6000001ff00 */
/*0220*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe20000011408 */
/*0230*/ @!P0 BRA 0x4c0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0240*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fc8000001ff00 */
/*0260*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fe400078e0200 */
/*0270*/ LEA R4, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc800078010ff */
/*0280*/ LEA.HI.X R5, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008057a11 */
/* 0x000fca00000f1409 */
/*0290*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*02b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*02d0*/ BSSY B1, 0x490 ; /* 0x000001b000017945 */
/* 0x000fe40003800000 */
/*02e0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06270 */
/*02f0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x170] ; /* 0x00005c00060a7625 */
/* 0x004fc800078e020b */
/*0300*/ IMAD.WIDE R8, R6, R9, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fe200078e0209 */
/*0310*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fc60000000f00 */
/*0320*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000b */
/*0350*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f26270 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x001fd800078e00ff */
/*0370*/ @!P1 LDG.E R9, [R4.64+0x4] ; /* 0x0000040404099981 */
/* 0x000ea4000c1e1900 */
/*0380*/ ISETP.GE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f26270 */
/*0390*/ @P1 BRA 0x480 ; /* 0x000000e000001947 */
/* 0x002fea0003800000 */
/*03a0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fe20000000f00 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fcc00078e000e */
/*03e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x004fcc00078e020b */
/*0400*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*0420*/ IADD3 R14, P2, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007f5e0ff */
/*0430*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*0450*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0460*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x0080620000000002 */
/*0470*/ BRA 0x350 ; /* 0xfffffed000007947 */
/* 0x000fea000383ffff */
/*0480*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0490*/ SHF.R.S32.HI R9, RZ, 0x1f, R0.reuse ; /* 0x0000001fff097819 */
/* 0x100fe20000011400 */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*04b0*/ @!P0 BRA 0x270 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ LEA R4, P0, R8, c[0x0][0x178], 0x3 ; /* 0x00005e0008047a11 */
/* 0x000fc800078018ff */
/*04e0*/ LEA.HI.X R5, R8, c[0x0][0x17c], R9, 0x3, P0 ; /* 0x00005f0008057a11 */
/* 0x000fca00000f1c09 */
/*04f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
cudaMalloc(&rowArr, sizeOfMatrix*sizeof(int));
cudaMalloc(&colArr, numOfNumbers*sizeof(int));
cudaMalloc(&valueArr, numOfNumbers*sizeof(double));
cudaMalloc(&xArr, sizeOfMatrix*sizeof(double));
cudaMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(valueArr, values, numOfNumbers*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(xArr, x, sizeOfMatrix*sizeof(double), cudaMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
cudaThreadSynchronize();
}
cudaMemcpy(x, xArr, sizeOfMatrix*sizeof(double), cudaMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
cudaFree(rowArr);
cudaFree(colArr);
cudaFree(valueArr);
cudaFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} | .file "tmpxft_0003563b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
.type _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii, @function
_Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10calculateXPiS_PdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii, .-_Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
.globl _Z10calculateXPiS_PdS0_ii
.type _Z10calculateXPiS_PdS0_ii, @function
_Z10calculateXPiS_PdS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10calculateXPiS_PdS0_ii, .-_Z10calculateXPiS_PdS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC3:
.string "%lf"
.LC5:
.string "ROW"
.LC6:
.string "%d "
.LC7:
.string "\n"
.LC8:
.string "COL"
.LC9:
.string "VALUES"
.LC10:
.string "%lf "
.LC11:
.string "X ARRAY"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 80(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 64(%rsp)
movl %eax, 76(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
movq 32(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r12
leaq 100(%rsp), %rbp
movq %rbp, %rdx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %r14d
movl %r14d, 72(%rsp)
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
movl %eax, 8(%rsp)
testl %r14d, %r14d
jle .L12
movslq %r14d, %rcx
leaq _ZZ4mainE6matrix(%rip), %rax
leaq (%rax,%rcx,8), %rdx
imulq $120008, %rcx, %rsi
addq %rax, %rsi
negq %rcx
salq $3, %rcx
.L13:
leaq (%rdx,%rcx), %rax
.L14:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L14
addq $120000, %rdx
cmpq %rsi, %rdx
jne .L13
.L12:
leaq 100(%rsp), %r14
leaq .LC1(%rip), %r13
leaq _ZZ4mainE6matrix(%rip), %r15
jmp .L15
.L16:
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
leal -1(%rax), %ebx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
leal -1(%rax), %ebp
leaq 104(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %ebp, %rbp
movslq %ebx, %rbx
imulq $15000, %rbx, %rbx
addq %rbp, %rbx
movsd 104(%rsp), %xmm0
movsd %xmm0, (%r15,%rbx,8)
.L15:
movq %r12, %rdi
call feof@PLT
testl %eax, %eax
je .L16
movl 72(%rsp), %ebx
movslq %ebx, %r12
leaq 0(,%r12,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L17
leaq (%r15,%rax), %rdx
movsd .LC4(%rip), %xmm0
.L18:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L18
leaq 0(,%r12,4), %r13
movq %r13, 32(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movslq 8(%rsp), %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 0(,%rbx,8), %rax
movq %rax, 48(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rax
leaq _ZZ4mainE6matrix(%rip), %r8
movq %r14, %r10
addq %r14, %r13
movl $0, %esi
movl $0, %r14d
pxor %xmm1, %xmm1
movl $1, %r9d
movl $1, %r11d
movq %r15, 88(%rsp)
jmp .L19
.L58:
movl %esi, (%r10)
movslq %esi, %rcx
movl %edx, 0(%rbp,%rcx,4)
movsd %xmm0, (%rbx,%rcx,8)
addl $1, %esi
movl %r11d, %edi
.L21:
addq $1, %rdx
cmpq %rdx, %r12
je .L57
.L22:
movl %edx, %r15d
movsd (%r8,%rdx,8), %xmm0
ucomisd %xmm1, %xmm0
setp %cl
cmovne %r9d, %ecx
testl %edi, %edi
jne .L20
testb %cl, %cl
jne .L58
.L20:
testl %edi, %edi
je .L21
testb %cl, %cl
je .L21
movslq %esi, %rcx
movl %r15d, 0(%rbp,%rcx,4)
movsd %xmm0, (%rbx,%rcx,8)
addl $1, %esi
jmp .L21
.L57:
testl %edi, %edi
jne .L23
movl $-1, (%r10)
.L23:
addq $4, %r10
addq $120000, %r8
cmpq %r13, %r10
je .L41
.L19:
movl $0, %edx
movl %r14d, %edi
jmp .L22
.L41:
movq 88(%rsp), %r15
movl $0, %ecx
movl 72(%rsp), %r8d
jmp .L24
.L27:
movl %esi, (%rdi)
.L25:
addl $1, %ecx
addq $4, %rax
cmpl %ecx, %r8d
je .L39
.L24:
movq %rax, %rdi
cmpl $-1, (%rax)
jne .L25
movl 4(%rax), %esi
movq %rax, %rdx
cmpl $-1, %esi
jne .L27
.L26:
addq $4, %rdx
movl 4(%rdx), %esi
cmpl $-1, %esi
je .L26
jmp .L27
.L29:
call cudaThreadSynchronize@PLT
addl $1, %r13d
cmpl %r12d, %r13d
je .L59
.L30:
movl %r14d, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 8(%rsp), %r9d
movl 72(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
jmp .L29
.L59:
movq 32(%rsp), %r12
.L28:
movl $2, %ecx
movq %r15, %rdx
movq 136(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 56(%rsp)
je .L60
.L31:
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 72(%rsp)
jle .L32
movq 24(%rsp), %rax
movq %rax, %r13
leaq (%rax,%r12,4), %r14
leaq .LC6(%rip), %r12
.L33:
movl 0(%r13), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r14, %r13
jne .L33
.L32:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
testl %eax, %eax
jle .L34
movq %rbp, %r12
cltq
movq %rax, 8(%rsp)
leaq 0(%rbp,%rax,4), %r14
leaq .LC6(%rip), %r13
.L35:
movl (%r12), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r14, %r12
jne .L35
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %r12
movq 8(%rsp), %rax
leaq (%rbx,%rax,8), %r14
leaq .LC10(%rip), %r13
.L36:
movsd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r12
cmpq %r12, %r14
jne .L36
.L38:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 72(%rsp)
jle .L31
movq 16(%rsp), %rax
movq %rax, %r12
addq %rax, %r15
leaq .LC10(%rip), %r13
.L37:
movsd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r12
cmpq %r15, %r12
jne .L37
jmp .L31
.L34:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L38
.L17:
leaq 0(,%r12,4), %rax
movq %rax, 32(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movslq 8(%rsp), %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 0(,%rbx,8), %rax
movq %rax, 48(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
.L39:
leaq 112(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq 40(%rsp), %r13
movq %r13, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq 48(%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 64(%rsp)
jle .L28
movl $0, %r13d
movq %r12, 32(%rsp)
movl 76(%rsp), %r12d
movq 80(%rsp), %r14
jmp .L30
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z10calculateXPiS_PdS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calculateXPiS_PdS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE6matrix
.comm _ZZ4mainE6matrix,1800000000,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
cudaMalloc(&rowArr, sizeOfMatrix*sizeof(int));
cudaMalloc(&colArr, numOfNumbers*sizeof(int));
cudaMalloc(&valueArr, numOfNumbers*sizeof(double));
cudaMalloc(&xArr, sizeOfMatrix*sizeof(double));
cudaMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(valueArr, values, numOfNumbers*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(xArr, x, sizeOfMatrix*sizeof(double), cudaMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
cudaThreadSynchronize();
}
cudaMemcpy(x, xArr, sizeOfMatrix*sizeof(double), cudaMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
cudaFree(rowArr);
cudaFree(colArr);
cudaFree(valueArr);
cudaFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
hipMalloc(&rowArr, sizeOfMatrix*sizeof(int));
hipMalloc(&colArr, numOfNumbers*sizeof(int));
hipMalloc(&valueArr, numOfNumbers*sizeof(double));
hipMalloc(&xArr, sizeOfMatrix*sizeof(double));
hipMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(valueArr, values, numOfNumbers*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(xArr, x, sizeOfMatrix*sizeof(double), hipMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
hipDeviceSynchronize();
}
hipMemcpy(x, xArr, sizeOfMatrix*sizeof(double), hipMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
hipFree(rowArr);
hipFree(colArr);
hipFree(valueArr);
hipFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
hipMalloc(&rowArr, sizeOfMatrix*sizeof(int));
hipMalloc(&colArr, numOfNumbers*sizeof(int));
hipMalloc(&valueArr, numOfNumbers*sizeof(double));
hipMalloc(&xArr, sizeOfMatrix*sizeof(double));
hipMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(valueArr, values, numOfNumbers*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(xArr, x, sizeOfMatrix*sizeof(double), hipMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
hipDeviceSynchronize();
}
hipMemcpy(x, xArr, sizeOfMatrix*sizeof(double), hipMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
hipFree(rowArr);
hipFree(colArr);
hipFree(valueArr);
hipFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10calculateXPiS_PdS0_ii
.globl _Z10calculateXPiS_PdS0_ii
.p2align 8
.type _Z10calculateXPiS_PdS0_ii,@function
_Z10calculateXPiS_PdS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x20
s_mov_b32 s12, 0
s_mov_b32 s11, exec_lo
v_add_nc_u32_e32 v2, -1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s4, 0, s2
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s3
s_mul_hi_u32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_mul_hi_u32 s3, s10, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s3, s2
s_add_i32 s5, s3, 1
s_sub_i32 s4, s10, s4
s_sub_i32 s6, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s3, s5, s3
s_cselect_b32 s4, s6, s4
s_add_i32 s5, s3, 1
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_load_b64 s[2:3], s[0:1], 0x18
s_sub_i32 s5, s10, s5
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_add_co_ci_u32_e64 v1, null, s4, 0, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, s4, v1, vcc_lo
v_mul_lo_u32 v0, v2, v0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x24
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v14, v0, v1
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
v_cmp_ge_i32_e32 vcc_lo, v0, v14
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_9
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v12, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s10, v0
global_load_b32 v4, v[4:5], off
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_lshlrev_b64 v[10:11], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s8, v8
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s6, v10
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s15
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_2
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v12 :: v_dual_mov_b32 v3, v13
v_mov_b32_e32 v1, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v1, v[6:7], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s15, -1
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v1
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB0_4
global_load_b32 v12, v[10:11], off
v_add_nc_u32_e32 v4, 1, v4
s_xor_b32 s15, exec_lo, -1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_u32 v12, s0, s2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s3, v13, s0
global_load_b64 v[15:16], v[8:9], off
global_load_b64 v[12:13], v[12:13], off
v_add_co_u32 v8, s0, v8, 8
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
v_add_co_u32 v10, s0, v10, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
s_waitcnt vmcnt(0)
v_fma_f64 v[12:13], v[15:16], v[12:13], v[2:3]
s_branch .LBB0_4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
s_or_b32 exec_lo, exec_lo, s11
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calculateXPiS_PdS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10calculateXPiS_PdS0_ii, .Lfunc_end0-_Z10calculateXPiS_PdS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calculateXPiS_PdS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10calculateXPiS_PdS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void calculateX(int *rowArr, int *colArr, double *valueArr,double *xArr,int n, int m)
{
int dist = n/blockDim.x;
if(n%blockDim.x > threadIdx.x)
dist = dist + 1;
int s = ((n%blockDim.x>(threadIdx.x-1))? dist : n/blockDim.x)*threadIdx.x;
int i;
double sum = 0;
for(i = s; i< s + dist; i++)
for(int j = rowArr[i]; j < ((i+1 < n)? rowArr[i+1] : m); j++)
sum = sum + valueArr[j] * xArr[colArr[j]];
xArr[i] = sum;
sum = 0;
}
int main(int argc, char *argv[])
{
int threads = atoi(argv[1]);
int iterations = atoi(argv[2]);
int answer = atoi(argv[3]);
FILE *file = fopen(argv[4], "r");
int num;
double num2;
int row;
int col;
fscanf(file, "%d", &num);
int sizeOfMatrix = num;
fscanf (file, "%d", &num);
fscanf(file, "%d", &num);
int numOfNumbers = num;
static double matrix[15000][15000];
for(row = 0; row < sizeOfMatrix; row++)
for(col = 0; col < sizeOfMatrix; col++)
matrix[row][col] = 0;
while(!feof (file))
{
fscanf(file, "%d", &num);
row = num-1;
fscanf(file, "%d", &num);
col = num-1;
fscanf(file, "%lf", &num2);
matrix[row][col] = num2;
}
double *x = (double *)malloc(sizeOfMatrix*sizeof(double));
for(row = 0; row < sizeOfMatrix; row++)
x[row] = 1;
int *row_ptr = (int *)malloc(sizeOfMatrix*sizeof(int));
int *col_ind = (int *)malloc(numOfNumbers*sizeof(int));
double *values = (double *)malloc(numOfNumbers*sizeof(double));
int count = 0;
int first = 0;
for(row = 0; row < sizeOfMatrix; row++)
{
for(col = 0; col < sizeOfMatrix; col++)
{
if(matrix[row][col] != 0 && first == 0)
{
row_ptr[row] = count;
col_ind[count] = col;
values [count] = matrix[row][col];
count ++;
first = 1;
}
else if(matrix[row][col] != 0 && first == 1)
{
col_ind [count] = col;
values [count] = matrix[row][col];
count++;
}
}
if(first == 0)
row_ptr[row] = -1;
first = 0;
}
int i = 1;
for(row = 0; row < sizeOfMatrix; row++)
if(row_ptr[row] == -1)
{
while(1)
{
if(row_ptr[row + i] != -1)
{
row_ptr[row] = row_ptr[row+i];
break;
}
i++;
}
i = 1;
}
int *rowArr, *colArr;
double *valueArr, *xArr;
hipMalloc(&rowArr, sizeOfMatrix*sizeof(int));
hipMalloc(&colArr, numOfNumbers*sizeof(int));
hipMalloc(&valueArr, numOfNumbers*sizeof(double));
hipMalloc(&xArr, sizeOfMatrix*sizeof(double));
hipMemcpy(rowArr, row_ptr, sizeOfMatrix*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(colArr, col_ind, numOfNumbers*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(valueArr, values, numOfNumbers*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(xArr, x, sizeOfMatrix*sizeof(double), hipMemcpyHostToDevice);
for(row = 0; row < iterations; row++)
{
calculateX<<<1, threads>>>(rowArr, colArr, valueArr, xArr, sizeOfMatrix, numOfNumbers);
hipDeviceSynchronize();
}
hipMemcpy(x, xArr, sizeOfMatrix*sizeof(double), hipMemcpyDeviceToHost);
if(answer == 1)
{
printf("ROW");
for(row = 0; row < sizeOfMatrix; row++)
printf("%d ",row_ptr[row]);
printf("\n");
printf("COL");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%d ",col_ind[row]);
printf("\n");
printf("VALUES");
printf("\n");
for(row = 0; row < numOfNumbers; row++)
printf("%lf ",values[row]);
printf("\n");
printf("X ARRAY");
printf("\n");
for(row = 0; row < sizeOfMatrix; row++)
printf("%lf ",x[row]);
}
hipFree(rowArr);
hipFree(colArr);
hipFree(valueArr);
hipFree(xArr);
free(row_ptr);
free(col_ind);
free(values);
free(x);
} | .text
.file "main.hip"
.globl _Z25__device_stub__calculateXPiS_PdS0_ii # -- Begin function _Z25__device_stub__calculateXPiS_PdS0_ii
.p2align 4, 0x90
.type _Z25__device_stub__calculateXPiS_PdS0_ii,@function
_Z25__device_stub__calculateXPiS_PdS0_ii: # @_Z25__device_stub__calculateXPiS_PdS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10calculateXPiS_PdS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__calculateXPiS_PdS0_ii, .Lfunc_end0-_Z25__device_stub__calculateXPiS_PdS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 88(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 96(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
leaq 4(%rsp), %r14
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %r12
movl %r12d, %r15d
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl %r12d, (%rsp) # 4-byte Spill
movl %r12d, %r13d
movl 4(%rsp), %eax
movq %rax, 40(%rsp) # 8-byte Spill
movq %r12, 8(%rsp) # 8-byte Spill
testq %r12, %r12
jle .LBB1_3
# %bb.1: # %.preheader156.lr.ph
leaq (,%r13,8), %r14
imulq $120000, %r13, %r15 # imm = 0x1D4C0
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader156
# =>This Inner Loop Header: Depth=1
leaq _ZZ4mainE6matrix(%r12), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
addq $120000, %r12 # imm = 0x1D4C0
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %.preheader155
movq %rbx, %rdi
callq feof
testl %eax, %eax
jne .LBB1_6
# %bb.4: # %.lr.ph160.preheader
leaq 4(%rsp), %r14
.p2align 4, 0x90
.LBB1_5: # %.lr.ph160
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %rax
imulq $120000, %rax, %r12 # imm = 0x1D4C0
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %r15
movl $.L.str.2, %esi
movq %rbx, %rdi
leaq 104(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movsd 104(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, _ZZ4mainE6matrix-120008(%r12,%r15,8)
movq %rbx, %rdi
callq feof
testl %eax, %eax
je .LBB1_5
.LBB1_6: # %._crit_edge161
movslq 40(%rsp), %r12 # 4-byte Folded Reload
movq 8(%rsp), %rbx # 8-byte Reload
leaq (,%rbx,8), %rdi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_9
# %bb.7: # %.lr.ph164.preheader
xorl %edx, %edx
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
.p2align 4, 0x90
.LBB1_8: # %.lr.ph164
# =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rdx,8)
incq %rdx
cmpq %rdx, %r13
jne .LBB1_8
.LBB1_9: # %._crit_edge165
movq %rax, 24(%rsp) # 8-byte Spill
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq (,%r12,4), %rdi
movq %rdi, 80(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r15
shlq $3, %r12
movq %r12, 8(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_15
# %bb.10: # %.preheader154.lr.ph
xorl %eax, %eax
movl $_ZZ4mainE6matrix, %ecx
xorpd %xmm0, %xmm0
xorl %edx, %edx
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_45: # %._crit_edge170
# in Loop: Header=BB1_11 Depth=1
testl %edi, %edi
je .LBB1_46
.LBB1_47: # in Loop: Header=BB1_11 Depth=1
incq %rax
addq $120000, %rcx # imm = 0x1D4C0
cmpq %r13, %rax
je .LBB1_15
.LBB1_11: # %.preheader154
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=2
movl %edx, (%r14,%rax,4)
.LBB1_43: # %.sink.split
# in Loop: Header=BB1_12 Depth=2
movslq %edx, %rdi
movl %esi, (%r15,%rdi,4)
movsd %xmm1, (%r12,%rdi,8)
incl %edx
movl $1, %edi
.LBB1_44: # in Loop: Header=BB1_12 Depth=2
incq %rsi
cmpq %rsi, %r13
je .LBB1_45
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jne .LBB1_13
jnp .LBB1_41
.LBB1_13: # in Loop: Header=BB1_12 Depth=2
testl %edi, %edi
je .LBB1_14
.LBB1_41: # in Loop: Header=BB1_12 Depth=2
ucomisd %xmm0, %xmm1
jne .LBB1_42
jnp .LBB1_44
.LBB1_42: # in Loop: Header=BB1_12 Depth=2
cmpl $1, %edi
je .LBB1_43
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_46: # in Loop: Header=BB1_11 Depth=1
movl $-1, (%r14,%rax,4)
jmp .LBB1_47
.LBB1_15: # %.preheader153
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_22
# %bb.16: # %.lr.ph175.preheader
movq %r14, %rax
addq $4, %rax
xorl %ecx, %ecx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_17 Depth=1
incq %rcx
addq $4, %rax
cmpq %r13, %rcx
je .LBB1_22
.LBB1_17: # %.lr.ph175
# =>This Loop Header: Depth=1
# Child Loop BB1_19 Depth 2
cmpl $-1, (%r14,%rcx,4)
jne .LBB1_21
# %bb.18: # %.preheader.preheader
# in Loop: Header=BB1_17 Depth=1
movq %rax, %rdx
.p2align 4, 0x90
.LBB1_19: # %.preheader
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx), %esi
addq $4, %rdx
cmpl $-1, %esi
je .LBB1_19
# %bb.20: # in Loop: Header=BB1_17 Depth=1
movl %esi, (%r14,%rcx,4)
jmp .LBB1_21
.LBB1_22: # %._crit_edge176
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 48(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 16(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r15, %rsi
movq 80(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r12, %rsi
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq 32(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB1_27
# %bb.23: # %.lr.ph179
movabsq $4294967296, %rbx # imm = 0x100000000
movl 88(%rsp), %eax # 4-byte Reload
orq %rbx, %rax
movq %rax, 8(%rsp) # 8-byte Spill
incq %rbx
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_24 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB1_27
.LBB1_24: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_26
# %bb.25: # in Loop: Header=BB1_24 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 76(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 72(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 160(%rsp), %rax
movq %rax, 216(%rsp)
leaq 76(%rsp), %rax
movq %rax, 224(%rsp)
leaq 72(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z10calculateXPiS_PdS0_ii, %edi
leaq 192(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_26
.LBB1_27: # %._crit_edge180
movq 16(%rsp), %rsi
movq 24(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $1, 96(%rsp) # 4-byte Folded Reload
jne .LBB1_40
# %bb.28:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_31
# %bb.29: # %.lr.ph183.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_30: # %.lr.ph183
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_30
.LBB1_31: # %._crit_edge184
movl $10, %edi
callq putchar@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rbp # 8-byte Reload
testl %ebp, %ebp
jle .LBB1_34
# %bb.32: # %.lr.ph187.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_33: # %.lr.ph187
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_33
.LBB1_34: # %._crit_edge188
movl $10, %edi
callq putchar@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_37
# %bb.35: # %.lr.ph191.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_36: # %.lr.ph191
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_36
.LBB1_37: # %._crit_edge192
movl $10, %edi
callq putchar@PLT
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, (%rsp) # 4-byte Folded Reload
movq 24(%rsp), %rbp # 8-byte Reload
jle .LBB1_40
# %bb.38: # %.lr.ph195.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph195
# =>This Inner Loop Header: Depth=1
movsd (%rbp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_39
.LBB1_40: # %.loopexit
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calculateXPiS_PdS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10calculateXPiS_PdS0_ii,@object # @_Z10calculateXPiS_PdS0_ii
.section .rodata,"a",@progbits
.globl _Z10calculateXPiS_PdS0_ii
.p2align 3, 0x0
_Z10calculateXPiS_PdS0_ii:
.quad _Z25__device_stub__calculateXPiS_PdS0_ii
.size _Z10calculateXPiS_PdS0_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type _ZZ4mainE6matrix,@object # @_ZZ4mainE6matrix
.local _ZZ4mainE6matrix
.comm _ZZ4mainE6matrix,1800000000,16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lf"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ROW"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d "
.size .L.str.4, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "COL"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "VALUES"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%lf "
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "X ARRAY"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calculateXPiS_PdS0_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calculateXPiS_PdS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10calculateXPiS_PdS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10calculateXPiS_PdS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R0, c[0x0][0x0] ; /* 0x0000000000007b06 */
/* 0x000e220000209000 */
/*0020*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0030*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ BSSY B0, 0x4d0 ; /* 0x0000047000007945 */
/* 0x000fe80003800000 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00a0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x004fc800078e0a03 */
/*00b0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.HI.U32 R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a27 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R0, R4, R5, c[0x0][0x180] ; /* 0x0000600004007624 */
/* 0x000fca00078e0205 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R7, R3, 0x1, RZ ; /* 0x0000000103077810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R5, R0, c[0x0][0x180] ; /* 0x0000600005007624 */
/* 0x000fe200078e0200 */
/*01a0*/ IADD3 R5, R8, -0x1, RZ ; /* 0xffffffff08057810 */
/* 0x002fc80007ffe0ff */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R0.reuse, R8, PT ; /* 0x000000080000720c */
/* 0x040fe40003f04070 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fd60003f24070 */
/*01d0*/ @!P0 IMAD.MOV R7, RZ, RZ, R3 ; /* 0x000000ffff078224 */
/* 0x000fca00078e0203 */
/*01e0*/ ISETP.GE.AND P0, PT, R7.reuse, 0x1, PT ; /* 0x000000010700780c */
/* 0x040fe40003f06270 */
/*01f0*/ SEL R3, R7, R3, P1 ; /* 0x0000000307037207 */
/* 0x000fca0000800000 */
/*0200*/ IMAD R8, R3, R8, RZ ; /* 0x0000000803087224 */
/* 0x000fe400078e02ff */
/*0210*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fc6000001ff00 */
/*0220*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe20000011408 */
/*0230*/ @!P0 BRA 0x4c0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0240*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fc8000001ff00 */
/*0260*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fe400078e0200 */
/*0270*/ LEA R4, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc800078010ff */
/*0280*/ LEA.HI.X R5, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008057a11 */
/* 0x000fca00000f1409 */
/*0290*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*02b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*02d0*/ BSSY B1, 0x490 ; /* 0x000001b000017945 */
/* 0x000fe40003800000 */
/*02e0*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06270 */
/*02f0*/ IMAD.WIDE R10, R6, R11, c[0x0][0x170] ; /* 0x00005c00060a7625 */
/* 0x004fc800078e020b */
/*0300*/ IMAD.WIDE R8, R6, R9, c[0x0][0x168] ; /* 0x00005a0006087625 */
/* 0x000fe200078e0209 */
/*0310*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fc60000000f00 */
/*0320*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0330*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000b */
/*0350*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f26270 */
/*0360*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x001fd800078e00ff */
/*0370*/ @!P1 LDG.E R9, [R4.64+0x4] ; /* 0x0000040404099981 */
/* 0x000ea4000c1e1900 */
/*0380*/ ISETP.GE.AND P1, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x004fda0003f26270 */
/*0390*/ @P1 BRA 0x480 ; /* 0x000000e000001947 */
/* 0x002fea0003800000 */
/*03a0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fe20000000f00 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fcc00078e000e */
/*03e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x004fcc00078e020b */
/*0400*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007f3e0ff */
/*0420*/ IADD3 R14, P2, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007f5e0ff */
/*0430*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe20007ffe0ff */
/*0440*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e060d */
/*0450*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0460*/ DFMA R2, R8, R10, R2 ; /* 0x0000000a0802722b */
/* 0x0080620000000002 */
/*0470*/ BRA 0x350 ; /* 0xfffffed000007947 */
/* 0x000fea000383ffff */
/*0480*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0490*/ SHF.R.S32.HI R9, RZ, 0x1f, R0.reuse ; /* 0x0000001fff097819 */
/* 0x100fe20000011400 */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*04b0*/ @!P0 BRA 0x270 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ LEA R4, P0, R8, c[0x0][0x178], 0x3 ; /* 0x00005e0008047a11 */
/* 0x000fc800078018ff */
/*04e0*/ LEA.HI.X R5, R8, c[0x0][0x17c], R9, 0x3, P0 ; /* 0x00005f0008057a11 */
/* 0x000fca00000f1c09 */
/*04f0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10calculateXPiS_PdS0_ii
.globl _Z10calculateXPiS_PdS0_ii
.p2align 8
.type _Z10calculateXPiS_PdS0_ii,@function
_Z10calculateXPiS_PdS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x20
s_mov_b32 s12, 0
s_mov_b32 s11, exec_lo
v_add_nc_u32_e32 v2, -1, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s4, 0, s2
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s3
s_mul_hi_u32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_mul_hi_u32 s3, s10, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s3, s2
s_add_i32 s5, s3, 1
s_sub_i32 s4, s10, s4
s_sub_i32 s6, s4, s2
s_cmp_ge_u32 s4, s2
s_cselect_b32 s3, s5, s3
s_cselect_b32 s4, s6, s4
s_add_i32 s5, s3, 1
s_cmp_ge_u32 s4, s2
s_cselect_b32 s4, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s4, s2
s_load_b64 s[2:3], s[0:1], 0x18
s_sub_i32 s5, s10, s5
v_cmp_gt_u32_e32 vcc_lo, s5, v0
v_add_co_ci_u32_e64 v1, null, s4, 0, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, s4, v1, vcc_lo
v_mul_lo_u32 v0, v2, v0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x24
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v14, v0, v1
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
v_cmp_ge_i32_e32 vcc_lo, v0, v14
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_9
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v12, v2
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s10, v0
global_load_b32 v4, v[4:5], off
v_add_co_u32 v6, s0, s4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_lshlrev_b64 v[10:11], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s8, v8
v_add_co_ci_u32_e64 v9, s0, s9, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s6, v10
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s15
s_or_b32 s13, s0, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_2
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v12 :: v_dual_mov_b32 v3, v13
v_mov_b32_e32 v1, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v1, v[6:7], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s15, -1
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v1
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB0_4
global_load_b32 v12, v[10:11], off
v_add_nc_u32_e32 v4, 1, v4
s_xor_b32 s15, exec_lo, -1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 3, v[12:13]
v_add_co_u32 v12, s0, s2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s0, s3, v13, s0
global_load_b64 v[15:16], v[8:9], off
global_load_b64 v[12:13], v[12:13], off
v_add_co_u32 v8, s0, v8, 8
v_add_co_ci_u32_e64 v9, s0, 0, v9, s0
v_add_co_u32 v10, s0, v10, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, 0, v11, s0
s_waitcnt vmcnt(0)
v_fma_f64 v[12:13], v[15:16], v[12:13], v[2:3]
s_branch .LBB0_4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
s_or_b32 exec_lo, exec_lo, s11
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calculateXPiS_PdS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10calculateXPiS_PdS0_ii, .Lfunc_end0-_Z10calculateXPiS_PdS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calculateXPiS_PdS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10calculateXPiS_PdS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003563b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
.type _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii, @function
_Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10calculateXPiS_PdS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii, .-_Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
.globl _Z10calculateXPiS_PdS0_ii
.type _Z10calculateXPiS_PdS0_ii, @function
_Z10calculateXPiS_PdS0_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10calculateXPiS_PdS0_ii, .-_Z10calculateXPiS_PdS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC3:
.string "%lf"
.LC5:
.string "ROW"
.LC6:
.string "%d "
.LC7:
.string "\n"
.LC8:
.string "COL"
.LC9:
.string "VALUES"
.LC10:
.string "%lf "
.LC11:
.string "X ARRAY"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 80(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 64(%rsp)
movl %eax, 76(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
movq 32(%rbx), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r12
leaq 100(%rsp), %rbp
movq %rbp, %rdx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %r14d
movl %r14d, 72(%rsp)
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
movl %eax, 8(%rsp)
testl %r14d, %r14d
jle .L12
movslq %r14d, %rcx
leaq _ZZ4mainE6matrix(%rip), %rax
leaq (%rax,%rcx,8), %rdx
imulq $120008, %rcx, %rsi
addq %rax, %rsi
negq %rcx
salq $3, %rcx
.L13:
leaq (%rdx,%rcx), %rax
.L14:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L14
addq $120000, %rdx
cmpq %rsi, %rdx
jne .L13
.L12:
leaq 100(%rsp), %r14
leaq .LC1(%rip), %r13
leaq _ZZ4mainE6matrix(%rip), %r15
jmp .L15
.L16:
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
leal -1(%rax), %ebx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %eax
leal -1(%rax), %ebp
leaq 104(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %ebp, %rbp
movslq %ebx, %rbx
imulq $15000, %rbx, %rbx
addq %rbp, %rbx
movsd 104(%rsp), %xmm0
movsd %xmm0, (%r15,%rbx,8)
.L15:
movq %r12, %rdi
call feof@PLT
testl %eax, %eax
je .L16
movl 72(%rsp), %ebx
movslq %ebx, %r12
leaq 0(,%r12,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %ebx, %ebx
jle .L17
leaq (%r15,%rax), %rdx
movsd .LC4(%rip), %xmm0
.L18:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L18
leaq 0(,%r12,4), %r13
movq %r13, 32(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movslq 8(%rsp), %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 0(,%rbx,8), %rax
movq %rax, 48(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rax
leaq _ZZ4mainE6matrix(%rip), %r8
movq %r14, %r10
addq %r14, %r13
movl $0, %esi
movl $0, %r14d
pxor %xmm1, %xmm1
movl $1, %r9d
movl $1, %r11d
movq %r15, 88(%rsp)
jmp .L19
.L58:
movl %esi, (%r10)
movslq %esi, %rcx
movl %edx, 0(%rbp,%rcx,4)
movsd %xmm0, (%rbx,%rcx,8)
addl $1, %esi
movl %r11d, %edi
.L21:
addq $1, %rdx
cmpq %rdx, %r12
je .L57
.L22:
movl %edx, %r15d
movsd (%r8,%rdx,8), %xmm0
ucomisd %xmm1, %xmm0
setp %cl
cmovne %r9d, %ecx
testl %edi, %edi
jne .L20
testb %cl, %cl
jne .L58
.L20:
testl %edi, %edi
je .L21
testb %cl, %cl
je .L21
movslq %esi, %rcx
movl %r15d, 0(%rbp,%rcx,4)
movsd %xmm0, (%rbx,%rcx,8)
addl $1, %esi
jmp .L21
.L57:
testl %edi, %edi
jne .L23
movl $-1, (%r10)
.L23:
addq $4, %r10
addq $120000, %r8
cmpq %r13, %r10
je .L41
.L19:
movl $0, %edx
movl %r14d, %edi
jmp .L22
.L41:
movq 88(%rsp), %r15
movl $0, %ecx
movl 72(%rsp), %r8d
jmp .L24
.L27:
movl %esi, (%rdi)
.L25:
addl $1, %ecx
addq $4, %rax
cmpl %ecx, %r8d
je .L39
.L24:
movq %rax, %rdi
cmpl $-1, (%rax)
jne .L25
movl 4(%rax), %esi
movq %rax, %rdx
cmpl $-1, %esi
jne .L27
.L26:
addq $4, %rdx
movl 4(%rdx), %esi
cmpl $-1, %esi
je .L26
jmp .L27
.L29:
call cudaThreadSynchronize@PLT
addl $1, %r13d
cmpl %r12d, %r13d
je .L59
.L30:
movl %r14d, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl 8(%rsp), %r9d
movl 72(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z39__device_stub__Z10calculateXPiS_PdS0_iiPiS_PdS0_ii
jmp .L29
.L59:
movq 32(%rsp), %r12
.L28:
movl $2, %ecx
movq %r15, %rdx
movq 136(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 56(%rsp)
je .L60
.L31:
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 72(%rsp)
jle .L32
movq 24(%rsp), %rax
movq %rax, %r13
leaq (%rax,%r12,4), %r14
leaq .LC6(%rip), %r12
.L33:
movl 0(%r13), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
cmpq %r14, %r13
jne .L33
.L32:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
testl %eax, %eax
jle .L34
movq %rbp, %r12
cltq
movq %rax, 8(%rsp)
leaq 0(%rbp,%rax,4), %r14
leaq .LC6(%rip), %r13
.L35:
movl (%r12), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r14, %r12
jne .L35
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %r12
movq 8(%rsp), %rax
leaq (%rbx,%rax,8), %r14
leaq .LC10(%rip), %r13
.L36:
movsd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r12
cmpq %r12, %r14
jne .L36
.L38:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 72(%rsp)
jle .L31
movq 16(%rsp), %rax
movq %rax, %r12
addq %rax, %r15
leaq .LC10(%rip), %r13
.L37:
movsd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %r12
cmpq %r15, %r12
jne .L37
jmp .L31
.L34:
leaq .LC7(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L38
.L17:
leaq 0(,%r12,4), %rax
movq %rax, 32(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movslq 8(%rsp), %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 0(,%rbx,8), %rax
movq %rax, 48(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
.L39:
leaq 112(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq 40(%rsp), %r13
movq %r13, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq 48(%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq 16(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $0, 64(%rsp)
jle .L28
movl $0, %r13d
movq %r12, 32(%rsp)
movl 76(%rsp), %r12d
movq 80(%rsp), %r14
jmp .L30
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z10calculateXPiS_PdS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calculateXPiS_PdS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ4mainE6matrix
.comm _ZZ4mainE6matrix,1800000000,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z25__device_stub__calculateXPiS_PdS0_ii # -- Begin function _Z25__device_stub__calculateXPiS_PdS0_ii
.p2align 4, 0x90
.type _Z25__device_stub__calculateXPiS_PdS0_ii,@function
_Z25__device_stub__calculateXPiS_PdS0_ii: # @_Z25__device_stub__calculateXPiS_PdS0_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10calculateXPiS_PdS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__calculateXPiS_PdS0_ii, .Lfunc_end0-_Z25__device_stub__calculateXPiS_PdS0_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 88(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 96(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
leaq 4(%rsp), %r14
movl $.L.str.1, %esi
movq %rax, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %r12
movl %r12d, %r15d
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl %r12d, (%rsp) # 4-byte Spill
movl %r12d, %r13d
movl 4(%rsp), %eax
movq %rax, 40(%rsp) # 8-byte Spill
movq %r12, 8(%rsp) # 8-byte Spill
testq %r12, %r12
jle .LBB1_3
# %bb.1: # %.preheader156.lr.ph
leaq (,%r13,8), %r14
imulq $120000, %r13, %r15 # imm = 0x1D4C0
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader156
# =>This Inner Loop Header: Depth=1
leaq _ZZ4mainE6matrix(%r12), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
addq $120000, %r12 # imm = 0x1D4C0
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %.preheader155
movq %rbx, %rdi
callq feof
testl %eax, %eax
jne .LBB1_6
# %bb.4: # %.lr.ph160.preheader
leaq 4(%rsp), %r14
.p2align 4, 0x90
.LBB1_5: # %.lr.ph160
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %rax
imulq $120000, %rax, %r12 # imm = 0x1D4C0
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 4(%rsp), %r15
movl $.L.str.2, %esi
movq %rbx, %rdi
leaq 104(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movsd 104(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, _ZZ4mainE6matrix-120008(%r12,%r15,8)
movq %rbx, %rdi
callq feof
testl %eax, %eax
je .LBB1_5
.LBB1_6: # %._crit_edge161
movslq 40(%rsp), %r12 # 4-byte Folded Reload
movq 8(%rsp), %rbx # 8-byte Reload
leaq (,%rbx,8), %rdi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_9
# %bb.7: # %.lr.ph164.preheader
xorl %edx, %edx
movabsq $4607182418800017408, %rcx # imm = 0x3FF0000000000000
.p2align 4, 0x90
.LBB1_8: # %.lr.ph164
# =>This Inner Loop Header: Depth=1
movq %rcx, (%rax,%rdx,8)
incq %rdx
cmpq %rdx, %r13
jne .LBB1_8
.LBB1_9: # %._crit_edge165
movq %rax, 24(%rsp) # 8-byte Spill
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq (,%r12,4), %rdi
movq %rdi, 80(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r15
shlq $3, %r12
movq %r12, 8(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_15
# %bb.10: # %.preheader154.lr.ph
xorl %eax, %eax
movl $_ZZ4mainE6matrix, %ecx
xorpd %xmm0, %xmm0
xorl %edx, %edx
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_45: # %._crit_edge170
# in Loop: Header=BB1_11 Depth=1
testl %edi, %edi
je .LBB1_46
.LBB1_47: # in Loop: Header=BB1_11 Depth=1
incq %rax
addq $120000, %rcx # imm = 0x1D4C0
cmpq %r13, %rax
je .LBB1_15
.LBB1_11: # %.preheader154
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=2
movl %edx, (%r14,%rax,4)
.LBB1_43: # %.sink.split
# in Loop: Header=BB1_12 Depth=2
movslq %edx, %rdi
movl %esi, (%r15,%rdi,4)
movsd %xmm1, (%r12,%rdi,8)
incl %edx
movl $1, %edi
.LBB1_44: # in Loop: Header=BB1_12 Depth=2
incq %rsi
cmpq %rsi, %r13
je .LBB1_45
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rcx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jne .LBB1_13
jnp .LBB1_41
.LBB1_13: # in Loop: Header=BB1_12 Depth=2
testl %edi, %edi
je .LBB1_14
.LBB1_41: # in Loop: Header=BB1_12 Depth=2
ucomisd %xmm0, %xmm1
jne .LBB1_42
jnp .LBB1_44
.LBB1_42: # in Loop: Header=BB1_12 Depth=2
cmpl $1, %edi
je .LBB1_43
jmp .LBB1_44
.p2align 4, 0x90
.LBB1_46: # in Loop: Header=BB1_11 Depth=1
movl $-1, (%r14,%rax,4)
jmp .LBB1_47
.LBB1_15: # %.preheader153
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_22
# %bb.16: # %.lr.ph175.preheader
movq %r14, %rax
addq $4, %rax
xorl %ecx, %ecx
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_17 Depth=1
incq %rcx
addq $4, %rax
cmpq %r13, %rcx
je .LBB1_22
.LBB1_17: # %.lr.ph175
# =>This Loop Header: Depth=1
# Child Loop BB1_19 Depth 2
cmpl $-1, (%r14,%rcx,4)
jne .LBB1_21
# %bb.18: # %.preheader.preheader
# in Loop: Header=BB1_17 Depth=1
movq %rax, %rdx
.p2align 4, 0x90
.LBB1_19: # %.preheader
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx), %esi
addq $4, %rdx
cmpl $-1, %esi
je .LBB1_19
# %bb.20: # in Loop: Header=BB1_17 Depth=1
movl %esi, (%r14,%rcx,4)
jmp .LBB1_21
.LBB1_22: # %._crit_edge176
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 48(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 16(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 64(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %r15, %rsi
movq 80(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %r12, %rsi
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq 32(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %ebp, %ebp
jle .LBB1_27
# %bb.23: # %.lr.ph179
movabsq $4294967296, %rbx # imm = 0x100000000
movl 88(%rsp), %eax # 4-byte Reload
orq %rbx, %rax
movq %rax, 8(%rsp) # 8-byte Spill
incq %rbx
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_24 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB1_27
.LBB1_24: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq 8(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_26
# %bb.25: # in Loop: Header=BB1_24 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movq %rsi, 160(%rsp)
movl (%rsp), %eax # 4-byte Reload
movl %eax, 76(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 72(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 160(%rsp), %rax
movq %rax, 216(%rsp)
leaq 76(%rsp), %rax
movq %rax, 224(%rsp)
leaq 72(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movl $_Z10calculateXPiS_PdS0_ii, %edi
leaq 192(%rsp), %r9
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_26
.LBB1_27: # %._crit_edge180
movq 16(%rsp), %rsi
movq 24(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq 32(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $1, 96(%rsp) # 4-byte Folded Reload
jne .LBB1_40
# %bb.28:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpl $0, (%rsp) # 4-byte Folded Reload
jle .LBB1_31
# %bb.29: # %.lr.ph183.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_30: # %.lr.ph183
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_30
.LBB1_31: # %._crit_edge184
movl $10, %edi
callq putchar@PLT
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
movq 40(%rsp), %rbp # 8-byte Reload
testl %ebp, %ebp
jle .LBB1_34
# %bb.32: # %.lr.ph187.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_33: # %.lr.ph187
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_33
.LBB1_34: # %._crit_edge188
movl $10, %edi
callq putchar@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_37
# %bb.35: # %.lr.ph191.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_36: # %.lr.ph191
# =>This Inner Loop Header: Depth=1
movsd (%r12,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_36
.LBB1_37: # %._crit_edge192
movl $10, %edi
callq putchar@PLT
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
cmpl $0, (%rsp) # 4-byte Folded Reload
movq 24(%rsp), %rbp # 8-byte Reload
jle .LBB1_40
# %bb.38: # %.lr.ph195.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph195
# =>This Inner Loop Header: Depth=1
movsd (%rbp,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.8, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB1_39
.LBB1_40: # %.loopexit
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calculateXPiS_PdS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10calculateXPiS_PdS0_ii,@object # @_Z10calculateXPiS_PdS0_ii
.section .rodata,"a",@progbits
.globl _Z10calculateXPiS_PdS0_ii
.p2align 3, 0x0
_Z10calculateXPiS_PdS0_ii:
.quad _Z25__device_stub__calculateXPiS_PdS0_ii
.size _Z10calculateXPiS_PdS0_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type _ZZ4mainE6matrix,@object # @_ZZ4mainE6matrix
.local _ZZ4mainE6matrix
.comm _ZZ4mainE6matrix,1800000000,16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lf"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ROW"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d "
.size .L.str.4, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "COL"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "VALUES"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%lf "
.size .L.str.8, 5
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "X ARRAY"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calculateXPiS_PdS0_ii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calculateXPiS_PdS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10calculateXPiS_PdS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} | code for sm_80
Function : _Z15ReduceRowMajor2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0050*/ STS [R9.X4], RZ ; /* 0x000000ff09007388 */
/* 0x0011e20000004800 */
/*0060*/ IMAD R2, R8, c[0x0][0x0], R9 ; /* 0x0000000008027a24 */
/* 0x002fca00078e0209 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0xd0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0041e40000004800 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0x270 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R0, 0x4 ; /* 0x0000000400007802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.SHL.U32 R10, R0, 0x2, RZ ; /* 0x00000002000a7824 */
/* 0x000fe200078e00ff */
/*0140*/ BSSY B0, 0x230 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0150*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x001fca00078e02ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x0], PT ; /* 0x000000000b007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 BRA 0x220 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fe20007ffe0ff */
/*0190*/ LDS.128 R4, [R11.X4] ; /* 0x000000000b047984 */
/* 0x000fe80000004c00 */
/*01a0*/ LDS.64 R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004a00 */
/*01b0*/ IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103037824 */
/* 0x001fe200078e0205 */
/*01c0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fca0007ffe0ff */
/*01d0*/ STS.64 [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x000fe80000004a00 */
/*01e0*/ LDS.64 R4, [R0.X4+0x8] ; /* 0x0000080000047984 */
/* 0x000e240000004a00 */
/*01f0*/ IMAD.IADD R5, R7, 0x1, R5 ; /* 0x0000000107057824 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R4, R6, R4, RZ ; /* 0x0000000406047210 */
/* 0x000fca0007ffe0ff */
/*0210*/ STS.64 [R11.X4+0x8], R4 ; /* 0x000008040b007388 */
/* 0x0001e40000004a00 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fe20003f06070 */
/*0250*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fd800078e000a */
/*0260*/ @!P0 BRA 0x130 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000c00 */
/*02a0*/ SHF.L.U32 R2, R8, 0x2, RZ ; /* 0x0000000208027819 */
/* 0x000fe200000006ff */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*02d0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101904 */
/*02e0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} | .file "tmpxft_001a9b18_00000000-6_ReduceRowMajor2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
.type _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i, @function
_Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15ReduceRowMajor2PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i, .-_Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
.globl _Z15ReduceRowMajor2PiS_i
.type _Z15ReduceRowMajor2PiS_i, @function
_Z15ReduceRowMajor2PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15ReduceRowMajor2PiS_i, .-_Z15ReduceRowMajor2PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15ReduceRowMajor2PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15ReduceRowMajor2PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15ReduceRowMajor2PiS_i
.globl _Z15ReduceRowMajor2PiS_i
.p2align 8
.type _Z15ReduceRowMajor2PiS_i,@function
_Z15ReduceRowMajor2PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_lshl_add_u32 v3, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lt_u32 s2, 5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_ge_u32 s3, s2
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s3, s5, 1
s_mov_b32 s4, exec_lo
v_mul_lo_u32 v1, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, s5, v1
v_lshl_add_u32 v6, v1, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v5, v2, 2, 0
ds_load_b32 v7, v5
ds_load_2addr_b32 v[1:2], v6 offset1:1
ds_load_2addr_b32 v[3:4], v6 offset0:2 offset1:3
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v1, v1, v7
ds_store_b32 v6, v1
ds_load_b32 v1, v5 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v6, v1 offset:4
ds_load_b32 v1, v5 offset:8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v3, v1
ds_store_b32 v6, v1 offset:8
ds_load_b32 v1, v5 offset:12
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v4, v1
ds_store_b32 v6, v1 offset:12
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_lshl_b32 s2, s15, 2
s_mov_b32 s7, s3
ds_load_2addr_b32 v[0:1], v2 offset1:1
ds_load_2addr_b32 v[2:3], v2 offset0:2 offset1:3
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s9, s3
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_or_b32 s6, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_or_b32 s8, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_or_b32 s2, s2, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x3
global_store_b32 v4, v0, s[4:5]
global_store_b32 v4, v1, s[6:7]
global_store_b32 v4, v2, s[8:9]
global_store_b32 v4, v3, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15ReduceRowMajor2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15ReduceRowMajor2PiS_i, .Lfunc_end0-_Z15ReduceRowMajor2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15ReduceRowMajor2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15ReduceRowMajor2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ReduceRowMajor2(int *g_idata, int *g_odata, int size) {
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int tid = threadIdx.x;
extern __shared__ int sdata[];
sdata[tid] = 0;
if(i < size)
sdata[tid] = g_idata[i];
__syncthreads();
for(unsigned int s = 4; s < blockDim.x; s*=2) {
int index = 2*s*tid;
if(index < blockDim.x) {
sdata[index] += sdata[index+s];
sdata[index+1] += sdata[index+s+1];
sdata[index+2] += sdata[index+s+2];
sdata[index+3] += sdata[index+s+3];
}
__syncthreads();
}
if(tid == 0) {
g_odata[blockIdx.x*4] = sdata[0];
g_odata[blockIdx.x*4+1] = sdata[1];
g_odata[blockIdx.x*4+2] = sdata[2];
g_odata[blockIdx.x*4+3] = sdata[3];
}
} | .text
.file "ReduceRowMajor2.hip"
.globl _Z30__device_stub__ReduceRowMajor2PiS_i # -- Begin function _Z30__device_stub__ReduceRowMajor2PiS_i
.p2align 4, 0x90
.type _Z30__device_stub__ReduceRowMajor2PiS_i,@function
_Z30__device_stub__ReduceRowMajor2PiS_i: # @_Z30__device_stub__ReduceRowMajor2PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15ReduceRowMajor2PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__ReduceRowMajor2PiS_i, .Lfunc_end0-_Z30__device_stub__ReduceRowMajor2PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ReduceRowMajor2PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ReduceRowMajor2PiS_i,@object # @_Z15ReduceRowMajor2PiS_i
.section .rodata,"a",@progbits
.globl _Z15ReduceRowMajor2PiS_i
.p2align 3, 0x0
_Z15ReduceRowMajor2PiS_i:
.quad _Z30__device_stub__ReduceRowMajor2PiS_i
.size _Z15ReduceRowMajor2PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ReduceRowMajor2PiS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ReduceRowMajor2PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ReduceRowMajor2PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15ReduceRowMajor2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0050*/ STS [R9.X4], RZ ; /* 0x000000ff09007388 */
/* 0x0011e20000004800 */
/*0060*/ IMAD R2, R8, c[0x0][0x0], R9 ; /* 0x0000000008027a24 */
/* 0x002fca00078e0209 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0xd0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0041e40000004800 */
/*00d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x000fda0003f06070 */
/*0110*/ @!P0 BRA 0x270 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R0, 0x4 ; /* 0x0000000400007802 */
/* 0x000fca0000000f00 */
/*0130*/ IMAD.SHL.U32 R10, R0, 0x2, RZ ; /* 0x00000002000a7824 */
/* 0x000fe200078e00ff */
/*0140*/ BSSY B0, 0x230 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0150*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x001fca00078e02ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x0], PT ; /* 0x000000000b007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 BRA 0x220 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fe20007ffe0ff */
/*0190*/ LDS.128 R4, [R11.X4] ; /* 0x000000000b047984 */
/* 0x000fe80000004c00 */
/*01a0*/ LDS.64 R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e240000004a00 */
/*01b0*/ IMAD.IADD R3, R3, 0x1, R5 ; /* 0x0000000103037824 */
/* 0x001fe200078e0205 */
/*01c0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fca0007ffe0ff */
/*01d0*/ STS.64 [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x000fe80000004a00 */
/*01e0*/ LDS.64 R4, [R0.X4+0x8] ; /* 0x0000080000047984 */
/* 0x000e240000004a00 */
/*01f0*/ IMAD.IADD R5, R7, 0x1, R5 ; /* 0x0000000107057824 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R4, R6, R4, RZ ; /* 0x0000000406047210 */
/* 0x000fca0007ffe0ff */
/*0210*/ STS.64 [R11.X4+0x8], R4 ; /* 0x000008040b007388 */
/* 0x0001e40000004a00 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fe20003f06070 */
/*0250*/ IMAD.MOV.U32 R0, RZ, RZ, R10 ; /* 0x000000ffff007224 */
/* 0x000fd800078e000a */
/*0260*/ @!P0 BRA 0x130 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e220000000c00 */
/*02a0*/ SHF.L.U32 R2, R8, 0x2, RZ ; /* 0x0000000208027819 */
/* 0x000fe200000006ff */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*02d0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101904 */
/*02e0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15ReduceRowMajor2PiS_i
.globl _Z15ReduceRowMajor2PiS_i
.p2align 8
.type _Z15ReduceRowMajor2PiS_i,@function
_Z15ReduceRowMajor2PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_lshl_add_u32 v3, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
ds_store_b32 v3, v2
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lt_u32 s2, 5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_ge_u32 s3, s2
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s3, s5, 1
s_mov_b32 s4, exec_lo
v_mul_lo_u32 v1, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v2, s5, v1
v_lshl_add_u32 v6, v1, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v5, v2, 2, 0
ds_load_b32 v7, v5
ds_load_2addr_b32 v[1:2], v6 offset1:1
ds_load_2addr_b32 v[3:4], v6 offset0:2 offset1:3
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v1, v1, v7
ds_store_b32 v6, v1
ds_load_b32 v1, v5 offset:4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v6, v1 offset:4
ds_load_b32 v1, v5 offset:8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v3, v1
ds_store_b32 v6, v1 offset:8
ds_load_b32 v1, v5 offset:12
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v4, v1
ds_store_b32 v6, v1 offset:12
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_lshl_b32 s2, s15, 2
s_mov_b32 s7, s3
ds_load_2addr_b32 v[0:1], v2 offset1:1
ds_load_2addr_b32 v[2:3], v2 offset0:2 offset1:3
s_lshl_b64 s[4:5], s[2:3], 2
s_mov_b32 s9, s3
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_or_b32 s6, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_or_b32 s8, s2, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_or_b32 s2, s2, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x3
global_store_b32 v4, v0, s[4:5]
global_store_b32 v4, v1, s[6:7]
global_store_b32 v4, v2, s[8:9]
global_store_b32 v4, v3, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15ReduceRowMajor2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15ReduceRowMajor2PiS_i, .Lfunc_end0-_Z15ReduceRowMajor2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15ReduceRowMajor2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15ReduceRowMajor2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a9b18_00000000-6_ReduceRowMajor2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
.type _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i, @function
_Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15ReduceRowMajor2PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i, .-_Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
.globl _Z15ReduceRowMajor2PiS_i
.type _Z15ReduceRowMajor2PiS_i, @function
_Z15ReduceRowMajor2PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15ReduceRowMajor2PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15ReduceRowMajor2PiS_i, .-_Z15ReduceRowMajor2PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15ReduceRowMajor2PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15ReduceRowMajor2PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ReduceRowMajor2.hip"
.globl _Z30__device_stub__ReduceRowMajor2PiS_i # -- Begin function _Z30__device_stub__ReduceRowMajor2PiS_i
.p2align 4, 0x90
.type _Z30__device_stub__ReduceRowMajor2PiS_i,@function
_Z30__device_stub__ReduceRowMajor2PiS_i: # @_Z30__device_stub__ReduceRowMajor2PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15ReduceRowMajor2PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__ReduceRowMajor2PiS_i, .Lfunc_end0-_Z30__device_stub__ReduceRowMajor2PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15ReduceRowMajor2PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15ReduceRowMajor2PiS_i,@object # @_Z15ReduceRowMajor2PiS_i
.section .rodata,"a",@progbits
.globl _Z15ReduceRowMajor2PiS_i
.p2align 3, 0x0
_Z15ReduceRowMajor2PiS_i:
.quad _Z30__device_stub__ReduceRowMajor2PiS_i
.size _Z15ReduceRowMajor2PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15ReduceRowMajor2PiS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__ReduceRowMajor2PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15ReduceRowMajor2PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
cudaMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
cudaDeviceSynchronize();
// Store result from device to host.
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
cudaFree(d_out);
} | code for sm_80
Function : _Z12mandelKernelPiffffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fca0000000f00 */
/*00e0*/ FFMA R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027623 */
/* 0x001fe20000000005 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0100*/ FFMA R4, R4, R7, c[0x0][0x16c] ; /* 0x00005b0004047623 */
/* 0x002fc80000000007 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R7, R7 ; /* 0x0000000707097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R7, R6, R7, R4 ; /* 0x0000000706077223 */
/* 0x000fe40000000004 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
cudaMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
cudaDeviceSynchronize();
// Store result from device to host.
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
cudaFree(d_out);
} | .file "tmpxft_00184aaf_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
.type _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii, @function
_Z38__device_stub__Z12mandelKernelPiffffiiPiffffii:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mandelKernelPiffffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii, .-_Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
.globl _Z12mandelKernelPiffffii
.type _Z12mandelKernelPiffffii, @function
_Z12mandelKernelPiffffii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mandelKernelPiffffii, .-_Z12mandelKernelPiffffii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r14
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movq %r13, %rsi
movq %r14, %rdi
call memcpy@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 4(%rsp), %xmm3
movss 12(%rsp), %xmm4
subss %xmm4, %xmm3
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
movss (%rsp), %xmm2
movss 8(%rsp), %xmm5
subss %xmm5, %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
movl %r15d, %edx
movl %ebp, %esi
divss %xmm1, %xmm3
divss %xmm0, %xmm2
movaps %xmm4, %xmm1
movaps %xmm5, %xmm0
movq 24(%rsp), %rdi
call _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelPiffffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelPiffffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
cudaMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
cudaDeviceSynchronize();
// Store result from device to host.
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
cudaFree(d_out);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
hipMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
hipDeviceSynchronize();
// Store result from device to host.
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
hipFree(d_out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
hipMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
hipDeviceSynchronize();
// Store result from device to host.
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
hipFree(d_out);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelPiffffii
.globl _Z12mandelKernelPiffffii
.p2align 8
.type _Z12mandelKernelPiffffii,@function
_Z12mandelKernelPiffffii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s6, s4
v_fma_f32 v3, v3, s7, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mul_f32 v5, v4, v4 :: v_dual_add_f32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v5
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v5, s2
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelPiffffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelPiffffii, .Lfunc_end0-_Z12mandelKernelPiffffii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelPiffffii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelPiffffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
__global__ void mandelKernel(
int *d_out,
float lowerX, float lowerY,
float stepX, float stepY,
int resX, int maxIters
) {
// To avoid error caused by the floating number, use the following pseudo code
//
// float x = lowerX + thisX * stepX;
// float y = lowerY + thisY * stepY;
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*resX + i;
float c_re = lowerX + i*stepX;
float c_im = lowerY + j*stepY;
float z_re = c_re;
float z_im = c_im;
int iter;
for (iter = 0; iter < maxIters; ++iter) {
if (z_re*z_re + z_im*z_im > 4.f)
break;
float new_re = z_re*z_re - z_im*z_im;
float new_im = 2.f*z_re*z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
d_out[index] = iter;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *h_out, *d_out; // Mandelbort result on host & device
int size = resX * resY * sizeof(int);
// Allocate memory on host & device.
h_out = (int *)malloc(size);
hipMalloc((void **)&d_out, size);
// CUDA kernel function.
dim3 block_size(BLOCK_SIZE, BLOCK_SIZE);
dim3 num_block(resX / BLOCK_SIZE, resY / BLOCK_SIZE);
mandelKernel<<<num_block, block_size>>>(d_out,
lowerX, lowerY,
stepX, stepY,
resX, maxIterations);
// Wait for all CUDA threads to finish.
hipDeviceSynchronize();
// Store result from device to host.
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
memcpy(img, h_out, size);
// Free memory.
free(h_out);
hipFree(d_out);
} | .text
.file "kernel1.hip"
.globl _Z27__device_stub__mandelKernelPiffffii # -- Begin function _Z27__device_stub__mandelKernelPiffffii
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelPiffffii,@function
_Z27__device_stub__mandelKernelPiffffii: # @_Z27__device_stub__mandelKernelPiffffii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mandelKernelPiffffii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelPiffffii, .Lfunc_end0-_Z27__device_stub__mandelKernelPiffffii
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r13d
movl %esi, %r12d
movq %rdi, %rbx
movss %xmm3, 28(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 24(%rsp) # 4-byte Spill
movss %xmm0, 16(%rsp) # 4-byte Spill
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
sarl $4, %eax
leal 15(%r13), %edi
testl %r13d, %r13d
cmovnsl %r13d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movss 28(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
divss %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm3, %xmm4
divss %xmm0, %xmm4
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movss %xmm3, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm4, 44(%rsp)
movss %xmm2, 40(%rsp)
movl %r12d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 52(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12mandelKernelPiffffii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelPiffffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelPiffffii,@object # @_Z12mandelKernelPiffffii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelPiffffii
.p2align 3, 0x0
_Z12mandelKernelPiffffii:
.quad _Z27__device_stub__mandelKernelPiffffii
.size _Z12mandelKernelPiffffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelPiffffii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelPiffffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelPiffffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mandelKernelPiffffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R3, R4, c[0x0][0x4], R5 ; /* 0x0000010004037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R5, c[0x0][0x170] ; /* 0x00005c0000057a02 */
/* 0x000fca0000000f00 */
/*00e0*/ FFMA R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027623 */
/* 0x001fe20000000005 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0100*/ FFMA R4, R4, R7, c[0x0][0x16c] ; /* 0x00005b0004047623 */
/* 0x002fc80000000007 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R7, R7 ; /* 0x0000000707097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R7, R6, R7, R4 ; /* 0x0000000706077223 */
/* 0x000fe40000000004 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0260*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelPiffffii
.globl _Z12mandelKernelPiffffii
.p2align 8
.type _Z12mandelKernelPiffffii,@function
_Z12mandelKernelPiffffii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s6, s4
v_fma_f32 v3, v3, s7, s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v2
v_mov_b32_e32 v4, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v5, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mul_f32 v5, v4, v4 :: v_dual_add_f32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v5
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v5, s2
v_fma_f32 v4, v4, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v5, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelPiffffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelPiffffii, .Lfunc_end0-_Z12mandelKernelPiffffii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelPiffffii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelPiffffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00184aaf_00000000-6_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
.type _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii, @function
_Z38__device_stub__Z12mandelKernelPiffffiiPiffffii:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mandelKernelPiffffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii, .-_Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
.globl _Z12mandelKernelPiffffii
.type _Z12mandelKernelPiffffii, @function
_Z12mandelKernelPiffffii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mandelKernelPiffffii, .-_Z12mandelKernelPiffffii
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rdi, %r14
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r15d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $16, 32(%rsp)
movl $16, 36(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
movl %eax, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movq %r13, %rsi
movq %r14, %rdi
call memcpy@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 4(%rsp), %xmm3
movss 12(%rsp), %xmm4
subss %xmm4, %xmm3
pxor %xmm1, %xmm1
cvtsi2ssl %r12d, %xmm1
movss (%rsp), %xmm2
movss 8(%rsp), %xmm5
subss %xmm5, %xmm2
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
movl %r15d, %edx
movl %ebp, %esi
divss %xmm1, %xmm3
divss %xmm0, %xmm2
movaps %xmm4, %xmm1
movaps %xmm5, %xmm0
movq 24(%rsp), %rdi
call _Z38__device_stub__Z12mandelKernelPiffffiiPiffffii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelPiffffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelPiffffii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel1.hip"
.globl _Z27__device_stub__mandelKernelPiffffii # -- Begin function _Z27__device_stub__mandelKernelPiffffii
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelPiffffii,@function
_Z27__device_stub__mandelKernelPiffffii: # @_Z27__device_stub__mandelKernelPiffffii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mandelKernelPiffffii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelPiffffii, .Lfunc_end0-_Z27__device_stub__mandelKernelPiffffii
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r13d
movl %esi, %r12d
movq %rdi, %rbx
movss %xmm3, 28(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 24(%rsp) # 4-byte Spill
movss %xmm0, 16(%rsp) # 4-byte Spill
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
sarl $4, %eax
leal 15(%r13), %edi
testl %r13d, %r13d
cmovnsl %r13d, %edi
sarl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movss 28(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
divss %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm3, %xmm4
divss %xmm0, %xmm4
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movss %xmm3, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm4, 44(%rsp)
movss %xmm2, 40(%rsp)
movl %r12d, 36(%rsp)
movl %ebp, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 52(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12mandelKernelPiffffii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelPiffffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelPiffffii,@object # @_Z12mandelKernelPiffffii
.section .rodata,"a",@progbits
.globl _Z12mandelKernelPiffffii
.p2align 3, 0x0
_Z12mandelKernelPiffffii:
.quad _Z27__device_stub__mandelKernelPiffffii
.size _Z12mandelKernelPiffffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelPiffffii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelPiffffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelPiffffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} | .file "tmpxft_00126c67_00000000-6_my_first_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hellow world from cpu"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main(void)
{
printf("Hellow world from cpu");
} | .text
.file "my_first_cuda.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hellow world from cpu"
.size .L.str, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00126c67_00000000-6_my_first_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hellow world from cpu"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "my_first_cuda.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hellow world from cpu"
.size .L.str, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} | code for sm_80
Function : stanh_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R8, -RZ, RZ, 1.125, -9232 ; /* 0x3c80f082ff087435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*00c0*/ FMUL R4, |R2|.reuse, 2.8853900432586669922 ; /* 0x4038aa3b02047820 */
/* 0x044fe20000400200 */
/*00d0*/ FSETP.GE.AND P1, PT, |R2|.reuse, 0.60000002384185791016, PT ; /* 0x3f19999a0200780b */
/* 0x040fe20003f26200 */
/*00e0*/ FMUL R7, R2.reuse, R2 ; /* 0x0000000202077220 */
/* 0x040fe20000400000 */
/*00f0*/ FSETP.GE.AND P0, PT, |R2|, 9.010913848876953125, PT ; /* 0x41102cb40200780b */
/* 0x000fc60003f06200 */
/*0100*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*0110*/ FFMA R8, R7, R8, -0.052303962409496307373 ; /* 0xbd563cae07087423 */
/* 0x000fc80000000008 */
/*0120*/ FFMA R8, R7, R8, 0.1331529766321182251 ; /* 0x3e08594107087423 */
/* 0x000fc80000000008 */
/*0130*/ FFMA R8, R7, R8, -0.33332768082618713379 ; /* 0xbeaaa9ed07087423 */
/* 0x000fc80000000008 */
/*0140*/ FFMA R7, R7, R8, RZ ; /* 0x0000000807077223 */
/* 0x000fe400000000ff */
/*0150*/ FADD R5, R4, 1 ; /* 0x3f80000004057421 */
/* 0x001fcc0000000000 */
/*0160*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000001000 */
/*0170*/ FFMA R6, R5, -2, R6 ; /* 0xc000000005067823 */
/* 0x001fca0000000006 */
/*0180*/ FSEL R3, R6, 1, !P0 ; /* 0x3f80000006037808 */
/* 0x000fc80004000000 */
/*0190*/ LOP3.LUT R4, R3, 0x80000000, R2.reuse, 0xf8, !PT ; /* 0x8000000003047812 */
/* 0x100fe200078ef802 */
/*01a0*/ @!P1 FFMA R4, R2, R7, R2 ; /* 0x0000000702049223 */
/* 0x000fe40000000002 */
/*01b0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0209 */
/*01c0*/ FMUL R5, R4, c[0x0][0x164] ; /* 0x0000590004057a20 */
/* 0x000fca0000400000 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} | .file "tmpxft_00010315_00000000-6_stanh_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
.type _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf, @function
_Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq stanh_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf, .-_Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
.globl stanh_32
.type stanh_32, @function
stanh_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size stanh_32, .-stanh_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "stanh_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq stanh_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected stanh_32
.globl stanh_32
.p2align 8
.type stanh_32,@function
stanh_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s2, 0x3f200000, |v0|
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_3
v_add_f32_e64 v3, |v0|, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v3, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v3, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v3, v3, -2.0, 1.0
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
v_mul_f32_e32 v3, v0, v0
s_mov_b32 s3, 0xbbbac73d
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v4, s3, v3, 0x3ca908c9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbd5c1c4e
v_fmaak_f32 v4, v3, v4, 0x3e088382
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbeaaaa99
v_mul_f32_e64 v4, |v0|, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, v3, v4, |v0|
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x10
v_bfi_b32 v3, 0x7fffffff, v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, s2, v3
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel stanh_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size stanh_32, .Lfunc_end0-stanh_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: stanh_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: stanh_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void stanh_32(const int lengthA, const float alpha, const float *a, float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthA)
{
b[i] = alpha*tanh(a[i]);
}
}
} | .text
.file "stanh_32.hip"
.globl __device_stub__stanh_32 # -- Begin function __device_stub__stanh_32
.p2align 4, 0x90
.type __device_stub__stanh_32,@function
__device_stub__stanh_32: # @__device_stub__stanh_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $stanh_32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__stanh_32, .Lfunc_end0-__device_stub__stanh_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $stanh_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type stanh_32,@object # @stanh_32
.section .rodata,"a",@progbits
.globl stanh_32
.p2align 3, 0x0
stanh_32:
.quad __device_stub__stanh_32
.size stanh_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "stanh_32"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__stanh_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym stanh_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : stanh_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R8, -RZ, RZ, 1.125, -9232 ; /* 0x3c80f082ff087435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R6, 0x3f800000 ; /* 0x3f80000000067802 */
/* 0x000fe20000000f00 */
/*00c0*/ FMUL R4, |R2|.reuse, 2.8853900432586669922 ; /* 0x4038aa3b02047820 */
/* 0x044fe20000400200 */
/*00d0*/ FSETP.GE.AND P1, PT, |R2|.reuse, 0.60000002384185791016, PT ; /* 0x3f19999a0200780b */
/* 0x040fe20003f26200 */
/*00e0*/ FMUL R7, R2.reuse, R2 ; /* 0x0000000202077220 */
/* 0x040fe20000400000 */
/*00f0*/ FSETP.GE.AND P0, PT, |R2|, 9.010913848876953125, PT ; /* 0x41102cb40200780b */
/* 0x000fc60003f06200 */
/*0100*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*0110*/ FFMA R8, R7, R8, -0.052303962409496307373 ; /* 0xbd563cae07087423 */
/* 0x000fc80000000008 */
/*0120*/ FFMA R8, R7, R8, 0.1331529766321182251 ; /* 0x3e08594107087423 */
/* 0x000fc80000000008 */
/*0130*/ FFMA R8, R7, R8, -0.33332768082618713379 ; /* 0xbeaaa9ed07087423 */
/* 0x000fc80000000008 */
/*0140*/ FFMA R7, R7, R8, RZ ; /* 0x0000000807077223 */
/* 0x000fe400000000ff */
/*0150*/ FADD R5, R4, 1 ; /* 0x3f80000004057421 */
/* 0x001fcc0000000000 */
/*0160*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000001000 */
/*0170*/ FFMA R6, R5, -2, R6 ; /* 0xc000000005067823 */
/* 0x001fca0000000006 */
/*0180*/ FSEL R3, R6, 1, !P0 ; /* 0x3f80000006037808 */
/* 0x000fc80004000000 */
/*0190*/ LOP3.LUT R4, R3, 0x80000000, R2.reuse, 0xf8, !PT ; /* 0x8000000003047812 */
/* 0x100fe200078ef802 */
/*01a0*/ @!P1 FFMA R4, R2, R7, R2 ; /* 0x0000000702049223 */
/* 0x000fe40000000002 */
/*01b0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0209 */
/*01c0*/ FMUL R5, R4, c[0x0][0x164] ; /* 0x0000590004057a20 */
/* 0x000fca0000400000 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected stanh_32
.globl stanh_32
.p2align 8
.type stanh_32,@function
stanh_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e64 s2, 0x3f200000, |v0|
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_3
v_add_f32_e64 v3, |v0|, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_rndne_f32_e32 v5, v4
v_fma_f32 v6, v3, 0x3fb8aa3b, -v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v5
v_fmamk_f32 v6, v3, 0x32a5705f, v6
v_cvt_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v3
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v3, v3, -2.0, 1.0
.LBB0_3:
s_and_not1_saveexec_b32 s2, s2
v_mul_f32_e32 v3, v0, v0
s_mov_b32 s3, 0xbbbac73d
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v4, s3, v3, 0x3ca908c9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbd5c1c4e
v_fmaak_f32 v4, v3, v4, 0x3e088382
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v4, v3, v4, 0xbeaaaa99
v_mul_f32_e64 v4, |v0|, v4
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, v3, v4, |v0|
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b64 s[0:1], s[0:1], 0x10
v_bfi_b32 v3, 0x7fffffff, v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, s2, v3
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel stanh_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size stanh_32, .Lfunc_end0-stanh_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: stanh_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: stanh_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00010315_00000000-6_stanh_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
.type _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf, @function
_Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq stanh_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf, .-_Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
.globl stanh_32
.type stanh_32, @function
stanh_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8stanh_32ifPKfPfifPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size stanh_32, .-stanh_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "stanh_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq stanh_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stanh_32.hip"
.globl __device_stub__stanh_32 # -- Begin function __device_stub__stanh_32
.p2align 4, 0x90
.type __device_stub__stanh_32,@function
__device_stub__stanh_32: # @__device_stub__stanh_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $stanh_32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__stanh_32, .Lfunc_end0-__device_stub__stanh_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $stanh_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type stanh_32,@object # @stanh_32
.section .rodata,"a",@progbits
.globl stanh_32
.p2align 3, 0x0
stanh_32:
.quad __device_stub__stanh_32
.size stanh_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "stanh_32"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__stanh_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym stanh_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} | code for sm_80
Function : _Z7maxPolydPKddiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R18, R18, c[0x0][0x0], R3 ; /* 0x0000000012127a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R19, RZ, 0x1f, R18 ; /* 0x0000001fff137819 */
/* 0x000fca0000011412 */
/*00a0*/ DADD R2, R2, 1 ; /* 0x3ff0000002027429 */
/* 0x000e0c0000000000 */
/*00b0*/ DSETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c000200762a */
/* 0x0010640003f04000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd400078e00ff */
/*00e0*/ @!P0 BRA 0x320 ; /* 0x0000023000008947 */
/* 0x002fea0003800000 */
/*00f0*/ LEA R2, P0, R18, c[0x0][0x168], 0x3 ; /* 0x00005a0012027a11 */
/* 0x000fc800078018ff */
/*0100*/ LEA.HI.X R3, R18, c[0x0][0x16c], R19, 0x3, P0 ; /* 0x00005b0012037a11 */
/* 0x000fca00000f1c13 */
/*0110*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ BSSY B0, 0x320 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0150*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x004e0c0000000010 */
/*0160*/ MUFU.RCP64H R3, R17 ; /* 0x0000001100037308 */
/* 0x001e220000001800 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0180*/ DFMA R10, R16.reuse, R6, c[0x2][0x0] ; /* 0x00800000100a762b */
/* 0x042e620000000006 */
/*0190*/ BSSY B1, 0x2b0 ; /* 0x0000011000017945 */
/* 0x000ff20003800000 */
/*01a0*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x002fe20003f2e200 */
/*01b0*/ DFMA R4, -R16, R2, 1 ; /* 0x3ff000001004742b */
/* 0x001e0c0000000102 */
/*01c0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*01d0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*01e0*/ DFMA R2, -R16, R4, 1 ; /* 0x3ff000001002742b */
/* 0x001e0c0000000104 */
/*01f0*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0200*/ DMUL R4, R10, R2 ; /* 0x000000020a047228 */
/* 0x001e0c0000000000 */
/*0210*/ DFMA R8, -R16, R4, R10 ; /* 0x000000041008722b */
/* 0x001e0c000000010a */
/*0220*/ DFMA R2, R2, R8, R4 ; /* 0x000000080202722b */
/* 0x001e140000000004 */
/*0230*/ FFMA R0, RZ, R17, R3 ; /* 0x00000011ff007223 */
/* 0x001fca0000000003 */
/*0240*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0250*/ @P0 BRA P1, 0x2a0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0260*/ MOV R0, 0x280 ; /* 0x0000028000007802 */
/* 0x000fe40000000f00 */
/*0270*/ CALL.REL.NOINC 0x360 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*02a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02b0*/ DADD R2, -R2, R6 ; /* 0x0000000002027229 */
/* 0x000e0c0000000106 */
/*02c0*/ DADD R4, R2, -R6 ; /* 0x0000000002047229 */
/* 0x0010880000000806 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*02e0*/ DSETP.GT.AND P0, PT, |R4|, c[0x0][0x170], PT ; /* 0x00005c000400762a */
/* 0x004e220003f04200 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fda00078e0003 */
/*0300*/ @P0 BRA 0x160 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ LEA R4, P0, R18, c[0x0][0x180], 0x3 ; /* 0x0000600012047a11 */
/* 0x000fc800078018ff */
/*0330*/ LEA.HI.X R5, R18, c[0x0][0x184], R19, 0x3, P0 ; /* 0x0000610012057a11 */
/* 0x000fca00000f1c13 */
/*0340*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x040fe20003f0e200 */
/*0370*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*0380*/ LOP3.LUT R8, R17, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff11087812 */
/* 0x000fe200078ec0ff */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*03a0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*03c0*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*03e0*/ LOP3.LUT R20, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b147812 */
/* 0x000fe200078ec0ff */
/*03f0*/ BSSY B2, 0x8f0 ; /* 0x000004f000027945 */
/* 0x000fe20003800000 */
/*0400*/ LOP3.LUT R23, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011177812 */
/* 0x000fc600078ec0ff */
/*0410*/ @!P0 DMUL R8, R16, 8.98846567431157953865e+307 ; /* 0x7fe0000010088828 */
/* 0x000e220000000000 */
/*0420*/ ISETP.GE.U32.AND P1, PT, R20.reuse, R23, PT ; /* 0x000000171400720c */
/* 0x040fe20003f26070 */
/*0430*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0014 */
/*0440*/ @!P2 LOP3.LUT R3, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001103a812 */
/* 0x000fe200078ec0ff */
/*0450*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e00ff */
/*0460*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x001e240000001800 */
/*0470*/ @!P2 ISETP.GE.U32.AND P3, PT, R20, R3, PT ; /* 0x000000031400a20c */
/* 0x000fe40003f66070 */
/*0480*/ SEL R3, R21, 0x63400000, !P1 ; /* 0x6340000015037807 */
/* 0x000fc40004800000 */
/*0490*/ @!P2 SEL R15, R21, 0x63400000, !P3 ; /* 0x63400000150fa807 */
/* 0x000fe40005800000 */
/*04a0*/ LOP3.LUT R3, R3, 0x800fffff, R11.reuse, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x100fe400078ef80b */
/*04b0*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fe400078ef80b */
/*04c0*/ @!P0 LOP3.LUT R23, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009178812 */
/* 0x000fe400078ec0ff */
/*04d0*/ @!P2 LOP3.LUT R15, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f0fa812 */
/* 0x000fe200078efcff */
/*04e0*/ DFMA R12, R4, -R8, 1 ; /* 0x3ff00000040c742b */
/* 0x001e220000000808 */
/*04f0*/ IADD3 R24, R23, -0x1, RZ ; /* 0xffffffff17187810 */
/* 0x000fc80007ffe0ff */
/*0500*/ @!P2 DFMA R2, R2, 2, -R14 ; /* 0x400000000202a82b */
/* 0x000fc8000000080e */
/*0510*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0520*/ DFMA R12, R4, R12, R4 ; /* 0x0000000c040c722b */
/* 0x001e220000000004 */
/*0530*/ @!P2 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000316a812 */
/* 0x000fc800078ec0ff */
/*0540*/ IADD3 R14, R22, -0x1, RZ ; /* 0xffffffff160e7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ DFMA R4, R12, -R8, 1 ; /* 0x3ff000000c04742b */
/* 0x001e060000000808 */
/*0560*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc60003f04070 */
/*0570*/ DFMA R12, R12, R4, R12 ; /* 0x000000040c0c722b */
/* 0x001e22000000000c */
/*0580*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*0590*/ DMUL R4, R12, R2 ; /* 0x000000020c047228 */
/* 0x001e0c0000000000 */
/*05a0*/ DFMA R14, R4, -R8, R2 ; /* 0x80000008040e722b */
/* 0x001e0c0000000002 */
/*05b0*/ DFMA R14, R12, R14, R4 ; /* 0x0000000e0c0e722b */
/* 0x0010620000000004 */
/*05c0*/ @P0 BRA 0x790 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT R5, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011057812 */
/* 0x001fe200078ec0ff */
/*05e0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R20.reuse, R5, PT ; /* 0x000000051400720c */
/* 0x040fe20003f06070 */
/*0600*/ IMAD.IADD R4, R20, 0x1, -R5 ; /* 0x0000000114047824 */
/* 0x000fc600078e0a05 */
/*0610*/ SEL R21, R21, 0x63400000, !P0 ; /* 0x6340000015157807 */
/* 0x000fe40004000000 */
/*0620*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0630*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0640*/ IMAD.IADD R10, R4, 0x1, -R21 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a15 */
/*0650*/ IADD3 R13, R10, 0x7fe00000, RZ ; /* 0x7fe000000a0d7810 */
/* 0x000fcc0007ffe0ff */
/*0660*/ DMUL R4, R14, R12 ; /* 0x0000000c0e047228 */
/* 0x002e140000000000 */
/*0670*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0680*/ @P0 BRA 0x8e0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0690*/ DFMA R2, R14, -R8, R2 ; /* 0x800000080e02722b */
/* 0x000e220000000002 */
/*06a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd200078e00ff */
/*06b0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*06c0*/ LOP3.LUT R9, R3, 0x80000000, R17, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4811 */
/*06d0*/ LOP3.LUT R13, R9, R13, RZ, 0xfc, !PT ; /* 0x0000000d090d7212 */
/* 0x000fce00078efcff */
/*06e0*/ @!P0 BRA 0x8e0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD.MOV R3, RZ, RZ, -R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0a */
/*0700*/ DMUL.RP R12, R14, R12 ; /* 0x0000000c0e0c7228 */
/* 0x000e220000008000 */
/*0710*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0720*/ DFMA R2, R4, -R2, R14 ; /* 0x800000020402722b */
/* 0x000e46000000000e */
/*0730*/ LOP3.LUT R9, R13, R9, RZ, 0x3c, !PT ; /* 0x000000090d097212 */
/* 0x001fc600078e3cff */
/*0740*/ IADD3 R2, -R10, -0x43300000, RZ ; /* 0xbcd000000a027810 */
/* 0x002fc80007ffe1ff */
/*0750*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0760*/ FSEL R4, R12, R4, !P0 ; /* 0x000000040c047208 */
/* 0x000fe40004000000 */
/*0770*/ FSEL R5, R9, R5, !P0 ; /* 0x0000000509057208 */
/* 0x000fe20004000000 */
/*0780*/ BRA 0x8e0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0790*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*07a0*/ @P0 BRA 0x8c0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*07b0*/ DSETP.NAN.AND P0, PT, R16, R16, PT ; /* 0x000000101000722a */
/* 0x000e9c0003f08000 */
/*07c0*/ @P0 BRA 0x890 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R22, R23, PT ; /* 0x000000171600720c */
/* 0x000fe20003f05270 */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0800*/ @!P0 BRA 0x8e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0820*/ LOP3.LUT R5, R11, 0x80000000, R17, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fe400078e4811 */
/*0830*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fda0004702670 */
/*0840*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*0850*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0860*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0870*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*0880*/ BRA 0x8e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT R5, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011057812 */
/* 0x001fe200078efcff */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0010 */
/*08b0*/ BRA 0x8e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R5, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b057812 */
/* 0x001fe200078efcff */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*08e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0910*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff6e002007950 */
/* 0x000fea0003c3ffff */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} | .file "tmpxft_0018c1b9_00000000-6_maxPoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
.type _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd, @function
_Z32__device_stub__Z7maxPolydPKddiPddPKddiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movsd %xmm0, 40(%rsp)
movq %rdi, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7maxPolydPKddiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd, .-_Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
.globl _Z7maxPolydPKddiPd
.type _Z7maxPolydPKddiPd, @function
_Z7maxPolydPKddiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7maxPolydPKddiPd, .-_Z7maxPolydPKddiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7maxPolydPKddiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7maxPolydPKddiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} | #include <hip/hip_runtime.h>
#include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7maxPolydPKddiPd
.globl _Z7maxPolydPKddiPd
.p2align 8
.type _Z7maxPolydPKddiPd,@function
_Z7maxPolydPKddiPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], s[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[2:3]
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_vccnz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s6, 0
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[3:4], v[3:4]
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
s_mov_b32 s5, 0x40026666
s_mov_b32 s4, 0x66666666
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
v_fma_f64 v[3:4], v[7:8], v[5:6], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[9:10], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[15:16], vcc_lo, v[3:4], v[5:6], v[3:4]
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_mul_f64 v[13:14], v[15:16], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[9:10], v[5:6], v[3:4]
v_add_f64 v[3:4], v[7:8], -v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[3:4], -v[7:8]
v_cmp_ngt_f64_e64 s7, |v[7:8]|, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s7, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7maxPolydPKddiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7maxPolydPKddiPd, .Lfunc_end0-_Z7maxPolydPKddiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7maxPolydPKddiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7maxPolydPKddiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
__global__ void maxPoly(const double x0, const double* coef,
const double tol, const int nParam, double* argMax){
// Thread ID
int i = blockIdx.x*blockDim.x + threadIdx.x;
// The Kernel should only execute if i < nParam
if(i >= nParam){
return;
} else {
// Iterate to convergence
double x = x0;
double diff = tol+1;
double firstDeriv, secondDeriv, xNew;
while(diff > tol){
// Compute the first derivative
firstDeriv = 2*coef[i]*x + 2.3;
// Compute the second derivative
secondDeriv = 2*coef[i];
// Newton step
xNew = x - firstDeriv/secondDeriv;
// Compute difference for convergence check and update
diff = fabs(xNew - x);
x = xNew;
}
// Function outpout
argMax[i] = x;
}
} | .text
.file "maxPoly.hip"
.globl _Z22__device_stub__maxPolydPKddiPd # -- Begin function _Z22__device_stub__maxPolydPKddiPd
.p2align 4, 0x90
.type _Z22__device_stub__maxPolydPKddiPd,@function
_Z22__device_stub__maxPolydPKddiPd: # @_Z22__device_stub__maxPolydPKddiPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 88(%rsp)
movq %rdi, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7maxPolydPKddiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z22__device_stub__maxPolydPKddiPd, .Lfunc_end0-_Z22__device_stub__maxPolydPKddiPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7maxPolydPKddiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7maxPolydPKddiPd,@object # @_Z7maxPolydPKddiPd
.section .rodata,"a",@progbits
.globl _Z7maxPolydPKddiPd
.p2align 3, 0x0
_Z7maxPolydPKddiPd:
.quad _Z22__device_stub__maxPolydPKddiPd
.size _Z7maxPolydPKddiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7maxPolydPKddiPd"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__maxPolydPKddiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7maxPolydPKddiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7maxPolydPKddiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R18, SR_CTAID.X ; /* 0x0000000000127919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R18, R18, c[0x0][0x0], R3 ; /* 0x0000000012127a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R19, RZ, 0x1f, R18 ; /* 0x0000001fff137819 */
/* 0x000fca0000011412 */
/*00a0*/ DADD R2, R2, 1 ; /* 0x3ff0000002027429 */
/* 0x000e0c0000000000 */
/*00b0*/ DSETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c000200762a */
/* 0x0010640003f04000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd400078e00ff */
/*00e0*/ @!P0 BRA 0x320 ; /* 0x0000023000008947 */
/* 0x002fea0003800000 */
/*00f0*/ LEA R2, P0, R18, c[0x0][0x168], 0x3 ; /* 0x00005a0012027a11 */
/* 0x000fc800078018ff */
/*0100*/ LEA.HI.X R3, R18, c[0x0][0x16c], R19, 0x3, P0 ; /* 0x00005b0012037a11 */
/* 0x000fca00000f1c13 */
/*0110*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ BSSY B0, 0x320 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0150*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x004e0c0000000010 */
/*0160*/ MUFU.RCP64H R3, R17 ; /* 0x0000001100037308 */
/* 0x001e220000001800 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0180*/ DFMA R10, R16.reuse, R6, c[0x2][0x0] ; /* 0x00800000100a762b */
/* 0x042e620000000006 */
/*0190*/ BSSY B1, 0x2b0 ; /* 0x0000011000017945 */
/* 0x000ff20003800000 */
/*01a0*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x002fe20003f2e200 */
/*01b0*/ DFMA R4, -R16, R2, 1 ; /* 0x3ff000001004742b */
/* 0x001e0c0000000102 */
/*01c0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*01d0*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*01e0*/ DFMA R2, -R16, R4, 1 ; /* 0x3ff000001002742b */
/* 0x001e0c0000000104 */
/*01f0*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0200*/ DMUL R4, R10, R2 ; /* 0x000000020a047228 */
/* 0x001e0c0000000000 */
/*0210*/ DFMA R8, -R16, R4, R10 ; /* 0x000000041008722b */
/* 0x001e0c000000010a */
/*0220*/ DFMA R2, R2, R8, R4 ; /* 0x000000080202722b */
/* 0x001e140000000004 */
/*0230*/ FFMA R0, RZ, R17, R3 ; /* 0x00000011ff007223 */
/* 0x001fca0000000003 */
/*0240*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0250*/ @P0 BRA P1, 0x2a0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0260*/ MOV R0, 0x280 ; /* 0x0000028000007802 */
/* 0x000fe40000000f00 */
/*0270*/ CALL.REL.NOINC 0x360 ; /* 0x000000e000007944 */
/* 0x000fea0003c00000 */
/*0280*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0005 */
/*02a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02b0*/ DADD R2, -R2, R6 ; /* 0x0000000002027229 */
/* 0x000e0c0000000106 */
/*02c0*/ DADD R4, R2, -R6 ; /* 0x0000000002047229 */
/* 0x0010880000000806 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*02e0*/ DSETP.GT.AND P0, PT, |R4|, c[0x0][0x170], PT ; /* 0x00005c000400762a */
/* 0x004e220003f04200 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fda00078e0003 */
/*0300*/ @P0 BRA 0x160 ; /* 0xfffffe5000000947 */
/* 0x001fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ LEA R4, P0, R18, c[0x0][0x180], 0x3 ; /* 0x0000600012047a11 */
/* 0x000fc800078018ff */
/*0330*/ LEA.HI.X R5, R18, c[0x0][0x184], R19, 0x3, P0 ; /* 0x0000610012057a11 */
/* 0x000fca00000f1c13 */
/*0340*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x040fe20003f0e200 */
/*0370*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*0380*/ LOP3.LUT R8, R17, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff11087812 */
/* 0x000fe200078ec0ff */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*03a0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*03c0*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*03e0*/ LOP3.LUT R20, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b147812 */
/* 0x000fe200078ec0ff */
/*03f0*/ BSSY B2, 0x8f0 ; /* 0x000004f000027945 */
/* 0x000fe20003800000 */
/*0400*/ LOP3.LUT R23, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011177812 */
/* 0x000fc600078ec0ff */
/*0410*/ @!P0 DMUL R8, R16, 8.98846567431157953865e+307 ; /* 0x7fe0000010088828 */
/* 0x000e220000000000 */
/*0420*/ ISETP.GE.U32.AND P1, PT, R20.reuse, R23, PT ; /* 0x000000171400720c */
/* 0x040fe20003f26070 */
/*0430*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0014 */
/*0440*/ @!P2 LOP3.LUT R3, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001103a812 */
/* 0x000fe200078ec0ff */
/*0450*/ @!P2 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e00ff */
/*0460*/ MUFU.RCP64H R5, R9 ; /* 0x0000000900057308 */
/* 0x001e240000001800 */
/*0470*/ @!P2 ISETP.GE.U32.AND P3, PT, R20, R3, PT ; /* 0x000000031400a20c */
/* 0x000fe40003f66070 */
/*0480*/ SEL R3, R21, 0x63400000, !P1 ; /* 0x6340000015037807 */
/* 0x000fc40004800000 */
/*0490*/ @!P2 SEL R15, R21, 0x63400000, !P3 ; /* 0x63400000150fa807 */
/* 0x000fe40005800000 */
/*04a0*/ LOP3.LUT R3, R3, 0x800fffff, R11.reuse, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x100fe400078ef80b */
/*04b0*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fe400078ef80b */
/*04c0*/ @!P0 LOP3.LUT R23, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009178812 */
/* 0x000fe400078ec0ff */
/*04d0*/ @!P2 LOP3.LUT R15, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f0fa812 */
/* 0x000fe200078efcff */
/*04e0*/ DFMA R12, R4, -R8, 1 ; /* 0x3ff00000040c742b */
/* 0x001e220000000808 */
/*04f0*/ IADD3 R24, R23, -0x1, RZ ; /* 0xffffffff17187810 */
/* 0x000fc80007ffe0ff */
/*0500*/ @!P2 DFMA R2, R2, 2, -R14 ; /* 0x400000000202a82b */
/* 0x000fc8000000080e */
/*0510*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0520*/ DFMA R12, R4, R12, R4 ; /* 0x0000000c040c722b */
/* 0x001e220000000004 */
/*0530*/ @!P2 LOP3.LUT R22, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000316a812 */
/* 0x000fc800078ec0ff */
/*0540*/ IADD3 R14, R22, -0x1, RZ ; /* 0xffffffff160e7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ DFMA R4, R12, -R8, 1 ; /* 0x3ff000000c04742b */
/* 0x001e060000000808 */
/*0560*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc60003f04070 */
/*0570*/ DFMA R12, R12, R4, R12 ; /* 0x000000040c0c722b */
/* 0x001e22000000000c */
/*0580*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fca0000704470 */
/*0590*/ DMUL R4, R12, R2 ; /* 0x000000020c047228 */
/* 0x001e0c0000000000 */
/*05a0*/ DFMA R14, R4, -R8, R2 ; /* 0x80000008040e722b */
/* 0x001e0c0000000002 */
/*05b0*/ DFMA R14, R12, R14, R4 ; /* 0x0000000e0c0e722b */
/* 0x0010620000000004 */
/*05c0*/ @P0 BRA 0x790 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT R5, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011057812 */
/* 0x001fe200078ec0ff */
/*05e0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R20.reuse, R5, PT ; /* 0x000000051400720c */
/* 0x040fe20003f06070 */
/*0600*/ IMAD.IADD R4, R20, 0x1, -R5 ; /* 0x0000000114047824 */
/* 0x000fc600078e0a05 */
/*0610*/ SEL R21, R21, 0x63400000, !P0 ; /* 0x6340000015157807 */
/* 0x000fe40004000000 */
/*0620*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0630*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0640*/ IMAD.IADD R10, R4, 0x1, -R21 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a15 */
/*0650*/ IADD3 R13, R10, 0x7fe00000, RZ ; /* 0x7fe000000a0d7810 */
/* 0x000fcc0007ffe0ff */
/*0660*/ DMUL R4, R14, R12 ; /* 0x0000000c0e047228 */
/* 0x002e140000000000 */
/*0670*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0680*/ @P0 BRA 0x8e0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0690*/ DFMA R2, R14, -R8, R2 ; /* 0x800000080e02722b */
/* 0x000e220000000002 */
/*06a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd200078e00ff */
/*06b0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*06c0*/ LOP3.LUT R9, R3, 0x80000000, R17, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4811 */
/*06d0*/ LOP3.LUT R13, R9, R13, RZ, 0xfc, !PT ; /* 0x0000000d090d7212 */
/* 0x000fce00078efcff */
/*06e0*/ @!P0 BRA 0x8e0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD.MOV R3, RZ, RZ, -R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0a */
/*0700*/ DMUL.RP R12, R14, R12 ; /* 0x0000000c0e0c7228 */
/* 0x000e220000008000 */
/*0710*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0720*/ DFMA R2, R4, -R2, R14 ; /* 0x800000020402722b */
/* 0x000e46000000000e */
/*0730*/ LOP3.LUT R9, R13, R9, RZ, 0x3c, !PT ; /* 0x000000090d097212 */
/* 0x001fc600078e3cff */
/*0740*/ IADD3 R2, -R10, -0x43300000, RZ ; /* 0xbcd000000a027810 */
/* 0x002fc80007ffe1ff */
/*0750*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0760*/ FSEL R4, R12, R4, !P0 ; /* 0x000000040c047208 */
/* 0x000fe40004000000 */
/*0770*/ FSEL R5, R9, R5, !P0 ; /* 0x0000000509057208 */
/* 0x000fe20004000000 */
/*0780*/ BRA 0x8e0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0790*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e9c0003f08000 */
/*07a0*/ @P0 BRA 0x8c0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*07b0*/ DSETP.NAN.AND P0, PT, R16, R16, PT ; /* 0x000000101000722a */
/* 0x000e9c0003f08000 */
/*07c0*/ @P0 BRA 0x890 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R22, R23, PT ; /* 0x000000171600720c */
/* 0x000fe20003f05270 */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x001fe400078e00ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0800*/ @!P0 BRA 0x8e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0820*/ LOP3.LUT R5, R11, 0x80000000, R17, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fe400078e4811 */
/*0830*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fda0004702670 */
/*0840*/ @P0 LOP3.LUT R2, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005020812 */
/* 0x000fe200078efcff */
/*0850*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0860*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0870*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0002 */
/*0880*/ BRA 0x8e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT R5, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011057812 */
/* 0x001fe200078efcff */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0010 */
/*08b0*/ BRA 0x8e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*08c0*/ LOP3.LUT R5, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b057812 */
/* 0x001fe200078efcff */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*08e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0910*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff6e002007950 */
/* 0x000fea0003c3ffff */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7maxPolydPKddiPd
.globl _Z7maxPolydPKddiPd
.p2align 8
.type _Z7maxPolydPKddiPd,@function
_Z7maxPolydPKddiPd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], s[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, s[2:3], v[2:3]
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_vccnz .LBB0_5
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_mov_b32 s6, 0
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[3:4], v[3:4]
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
s_mov_b32 s5, 0x40026666
s_mov_b32 s4, 0x66666666
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
v_fma_f64 v[3:4], v[7:8], v[5:6], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[9:10], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[15:16], vcc_lo, v[3:4], v[5:6], v[3:4]
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
v_mul_f64 v[13:14], v[15:16], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[9:10], v[5:6], v[3:4]
v_add_f64 v[3:4], v[7:8], -v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[3:4], -v[7:8]
v_cmp_ngt_f64_e64 s7, |v[7:8]|, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s6, s7, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7maxPolydPKddiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7maxPolydPKddiPd, .Lfunc_end0-_Z7maxPolydPKddiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7maxPolydPKddiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7maxPolydPKddiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018c1b9_00000000-6_maxPoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
.type _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd, @function
_Z32__device_stub__Z7maxPolydPKddiPddPKddiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movsd %xmm0, 40(%rsp)
movq %rdi, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7maxPolydPKddiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd, .-_Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
.globl _Z7maxPolydPKddiPd
.type _Z7maxPolydPKddiPd, @function
_Z7maxPolydPKddiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7maxPolydPKddiPddPKddiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7maxPolydPKddiPd, .-_Z7maxPolydPKddiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7maxPolydPKddiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7maxPolydPKddiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxPoly.hip"
.globl _Z22__device_stub__maxPolydPKddiPd # -- Begin function _Z22__device_stub__maxPolydPKddiPd
.p2align 4, 0x90
.type _Z22__device_stub__maxPolydPKddiPd,@function
_Z22__device_stub__maxPolydPKddiPd: # @_Z22__device_stub__maxPolydPKddiPd
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 88(%rsp)
movq %rdi, 80(%rsp)
movsd %xmm1, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7maxPolydPKddiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z22__device_stub__maxPolydPKddiPd, .Lfunc_end0-_Z22__device_stub__maxPolydPKddiPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7maxPolydPKddiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7maxPolydPKddiPd,@object # @_Z7maxPolydPKddiPd
.section .rodata,"a",@progbits
.globl _Z7maxPolydPKddiPd
.p2align 3, 0x0
_Z7maxPolydPKddiPd:
.quad _Z22__device_stub__maxPolydPKddiPd
.size _Z7maxPolydPKddiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7maxPolydPKddiPd"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__maxPolydPKddiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7maxPolydPKddiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* sgemm.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
enum {
BLOCK_SIZE = 32,
N = 1024
};
__global__ void sgemm_naive(const float *a, const float *b, float *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < n && col < n) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[row * n + k] * b[k * n + col];
c[row * n + col] = s;
}
}
__global__ void sgemm_tailed(const float *a, const float *b, float *c, int n)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
int tail_size = blockDim.x;
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
// Result for c[i, j]
float sum = 0.0;
// Index of first tail (sub-matrix) in A
int Astart = by * n * tail_size;
int Aend = Astart + n - 1;
int Astep = tail_size;
// Index of first tail (sub-matrix) in B
int Bstart = bx * tail_size;
int Bstep = n * tail_size;
int ai = Astart;
int bi = Bstart;
while (ai <= Aend) {
// Load tail to shared memory - each thread load one item
as[ty][tx] = a[ai + ty * n + tx];
bs[ty][tx] = b[bi + ty * n + tx];
// Wait all threads
__syncthreads();
// Compute partial result
for (int k = 0; k < tail_size; k++)
sum += as[ty][k] * bs[k][tx];
// Wait for all threads before overwriting of as and bs
__syncthreads();
ai += Astep;
bi += Bstep;
}
int Cstart = by * n * tail_size + bx * tail_size;
c[Cstart + ty * n + tx] = sum;
}
void sgemm_host(float *a, float *b, float *c, int n)
{
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[i * n + k] * b[k * n + j];
c[i * n + j] = s;
}
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu, tgpu, tmem;
cudaError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N * N;
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
h_A[i * N + j] = 2.0;
h_B[i * N + j] = 3.0;
}
}
tcpu = -wtime();
sgemm_host(h_A, h_B, h_C, N);
tcpu += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "CPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (cudaMalloc((void **)&d_A, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_B, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_C, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
tmem = -wtime();
if (cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
/* Launch the kernel */
int threadsPerBlockDim = BLOCK_SIZE;
dim3 blockDim(threadsPerBlockDim, threadsPerBlockDim, 1);
int blocksPerGridDimX = ceilf(N / (float)threadsPerBlockDim);
int blocksPerGridDimY = ceilf(N / (float)threadsPerBlockDim);
dim3 gridDim(blocksPerGridDimX, blocksPerGridDimY, 1);
printf("CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n",
blocksPerGridDimX * blocksPerGridDimY, blocksPerGridDimX, blocksPerGridDimY,
threadsPerBlockDim * threadsPerBlockDim, threadsPerBlockDim, threadsPerBlockDim);
tgpu = -wtime();
//sgemm_naive<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
sgemm_tailed<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
cudaDeviceSynchronize();
tgpu += wtime();
if ( (err = cudaGetLastError()) != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "GPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Memory bw. (MiB/sec.): %.2f\n", ((3 * size) >> 20) / tmem);
printf("CPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tcpu);
printf("GPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tgpu);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000000b3_00000000-6_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10sgemm_hostPfS_S_i
.type _Z10sgemm_hostPfS_S_i, @function
_Z10sgemm_hostPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L5:
movq %rbx, %r8
movl $0, %edi
.L8:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L6
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %r11, %rdi
jne .L8
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z10sgemm_hostPfS_S_i, .-_Z10sgemm_hostPfS_S_i
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
.type _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi, @function
_Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sgemm_naivePKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi, .-_Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
.globl _Z11sgemm_naivePKfS0_Pfi
.type _Z11sgemm_naivePKfS0_Pfi, @function
_Z11sgemm_naivePKfS0_Pfi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11sgemm_naivePKfS0_Pfi, .-_Z11sgemm_naivePKfS0_Pfi
.globl _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
.type _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi, @function
_Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sgemm_tailedPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi, .-_Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
.globl _Z12sgemm_tailedPKfS0_Pfi
.type _Z12sgemm_tailedPKfS0_Pfi, @function
_Z12sgemm_tailedPKfS0_Pfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12sgemm_tailedPKfS0_Pfi, .-_Z12sgemm_tailedPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocation error.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "CPU results verification failed at element %d %d!\n"
.section .rodata.str1.1
.LC9:
.string "Allocation error\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Host to device copying failed\n"
.align 8
.LC11:
.string "CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n"
.align 8
.LC12:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC13:
.string "Device to host copying failed\n"
.align 8
.LC14:
.string "GPU results verification failed at element %d %d!\n"
.section .rodata.str1.1
.LC15:
.string "CPU version (sec.): %.6f\n"
.LC16:
.string "GPU version (sec.): %.6f\n"
.LC17:
.string "Memory ops. (sec.): %.6f\n"
.LC19:
.string "Memory bw. (MiB/sec.): %.2f\n"
.LC21:
.string "CPU GFLOPS: %.2f\n"
.LC22:
.string "GPU GFLOPS: %.2f\n"
.LC23:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC24:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L59
testq %r12, %r12
je .L59
movl $4096, %edx
movss .LC3(%rip), %xmm1
movss .LC4(%rip), %xmm0
.L35:
leaq -4096(%rdx), %rax
.L37:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L37
addq $4096, %rdx
cmpq $4198400, %rdx
jne .L35
call _Z5wtimev
movsd %xmm0, 8(%rsp)
movl $1024, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10sgemm_hostPfS_S_i
call _Z5wtimev
movsd %xmm0, 32(%rsp)
movq %r12, %r13
movq %r12, %rax
movl $0, %ecx
movsd .LC5(%rip), %xmm4
movq .LC6(%rip), %xmm3
movsd .LC7(%rip), %xmm2
jmp .L39
.L59:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L68:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
addl $1, %ecx
addq $4096, %rax
cmpl $1024, %ecx
je .L43
.L39:
movl $0, %r8d
.L42:
pxor %xmm1, %xmm1
cvtss2sd (%rax,%r8,4), %xmm1
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
andpd %xmm3, %xmm0
comisd %xmm2, %xmm0
ja .L68
addq $1, %r8
cmpq $1024, %r8
jne .L42
jmp .L69
.L43:
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L70
leaq 80(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L71
leaq 88(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L72
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L73
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L74
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movl $32, 96(%rsp)
movl $32, 100(%rsp)
movl $1, 104(%rsp)
movl $32, 108(%rsp)
movl $32, 112(%rsp)
movl $1, 116(%rsp)
pushq $32
.cfi_def_cfa_offset 184
pushq $32
.cfi_def_cfa_offset 192
movl $1024, %r9d
movl $32, %r8d
movl $32, %ecx
movl $1024, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z5wtimev
movsd %xmm0, 40(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L49:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
movsd %xmm0, 48(%rsp)
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
call _Z5wtimev
movsd %xmm0, 56(%rsp)
movl $2, %ecx
movl $4194304, %edx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L77
call _Z5wtimev
movapd %xmm0, %xmm5
movl $0, %ecx
movsd .LC5(%rip), %xmm4
movq .LC6(%rip), %xmm3
movsd .LC7(%rip), %xmm2
jmp .L52
.L70:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl $1024, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
jmp .L49
.L76:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L79:
addl $1, %ecx
addq $4096, %r13
cmpl $1024, %ecx
je .L56
.L52:
movl $0, %r8d
.L55:
pxor %xmm1, %xmm1
cvtss2sd 0(%r13,%r8,4), %xmm1
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
andpd %xmm3, %xmm0
comisd %xmm2, %xmm0
ja .L78
addq $1, %r8
cmpq $1024, %r8
jne .L55
jmp .L79
.L56:
movsd 32(%rsp), %xmm6
subsd 8(%rsp), %xmm6
movsd 48(%rsp), %xmm7
subsd 24(%rsp), %xmm7
movsd %xmm7, 8(%rsp)
movsd 40(%rsp), %xmm0
subsd 16(%rsp), %xmm0
subsd 56(%rsp), %xmm0
addsd %xmm5, %xmm0
movsd %xmm0, 24(%rsp)
movsd %xmm6, 16(%rsp)
movapd %xmm6, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC18(%rip), %xmm0
divsd 24(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC20(%rip), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC20(%rip), %xmm3
divsd 8(%rsp), %xmm3
movapd %xmm3, %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm7
addsd 24(%rsp), %xmm7
movsd 16(%rsp), %xmm6
divsd %xmm7, %xmm6
movapd %xmm6, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z12sgemm_tailedPKfS0_Pfi"
.LC26:
.string "_Z11sgemm_naivePKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_tailedPKfS0_Pfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sgemm_naivePKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1085800448
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC7:
.long -1998362383
.long 1055193269
.align 8
.LC18:
.long 0
.long 1076363264
.align 8
.LC20:
.long -536870912
.long 1073819147
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* sgemm.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
enum {
BLOCK_SIZE = 32,
N = 1024
};
__global__ void sgemm_naive(const float *a, const float *b, float *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < n && col < n) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[row * n + k] * b[k * n + col];
c[row * n + col] = s;
}
}
__global__ void sgemm_tailed(const float *a, const float *b, float *c, int n)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
int tail_size = blockDim.x;
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
// Result for c[i, j]
float sum = 0.0;
// Index of first tail (sub-matrix) in A
int Astart = by * n * tail_size;
int Aend = Astart + n - 1;
int Astep = tail_size;
// Index of first tail (sub-matrix) in B
int Bstart = bx * tail_size;
int Bstep = n * tail_size;
int ai = Astart;
int bi = Bstart;
while (ai <= Aend) {
// Load tail to shared memory - each thread load one item
as[ty][tx] = a[ai + ty * n + tx];
bs[ty][tx] = b[bi + ty * n + tx];
// Wait all threads
__syncthreads();
// Compute partial result
for (int k = 0; k < tail_size; k++)
sum += as[ty][k] * bs[k][tx];
// Wait for all threads before overwriting of as and bs
__syncthreads();
ai += Astep;
bi += Bstep;
}
int Cstart = by * n * tail_size + bx * tail_size;
c[Cstart + ty * n + tx] = sum;
}
void sgemm_host(float *a, float *b, float *c, int n)
{
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[i * n + k] * b[k * n + j];
c[i * n + j] = s;
}
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu, tgpu, tmem;
cudaError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N * N;
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
h_A[i * N + j] = 2.0;
h_B[i * N + j] = 3.0;
}
}
tcpu = -wtime();
sgemm_host(h_A, h_B, h_C, N);
tcpu += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "CPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (cudaMalloc((void **)&d_A, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_B, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_C, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
tmem = -wtime();
if (cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
/* Launch the kernel */
int threadsPerBlockDim = BLOCK_SIZE;
dim3 blockDim(threadsPerBlockDim, threadsPerBlockDim, 1);
int blocksPerGridDimX = ceilf(N / (float)threadsPerBlockDim);
int blocksPerGridDimY = ceilf(N / (float)threadsPerBlockDim);
dim3 gridDim(blocksPerGridDimX, blocksPerGridDimY, 1);
printf("CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n",
blocksPerGridDimX * blocksPerGridDimY, blocksPerGridDimX, blocksPerGridDimY,
threadsPerBlockDim * threadsPerBlockDim, threadsPerBlockDim, threadsPerBlockDim);
tgpu = -wtime();
//sgemm_naive<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
sgemm_tailed<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
cudaDeviceSynchronize();
tgpu += wtime();
if ( (err = cudaGetLastError()) != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "GPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Memory bw. (MiB/sec.): %.2f\n", ((3 * size) >> 20) / tmem);
printf("CPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tcpu);
printf("GPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tgpu);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
cudaDeviceReset();
return 0;
} | /*
* sgemm.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
BLOCK_SIZE = 32,
N = 1024
};
__global__ void sgemm_naive(const float *a, const float *b, float *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < n && col < n) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[row * n + k] * b[k * n + col];
c[row * n + col] = s;
}
}
__global__ void sgemm_tailed(const float *a, const float *b, float *c, int n)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
int tail_size = blockDim.x;
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
// Result for c[i, j]
float sum = 0.0;
// Index of first tail (sub-matrix) in A
int Astart = by * n * tail_size;
int Aend = Astart + n - 1;
int Astep = tail_size;
// Index of first tail (sub-matrix) in B
int Bstart = bx * tail_size;
int Bstep = n * tail_size;
int ai = Astart;
int bi = Bstart;
while (ai <= Aend) {
// Load tail to shared memory - each thread load one item
as[ty][tx] = a[ai + ty * n + tx];
bs[ty][tx] = b[bi + ty * n + tx];
// Wait all threads
__syncthreads();
// Compute partial result
for (int k = 0; k < tail_size; k++)
sum += as[ty][k] * bs[k][tx];
// Wait for all threads before overwriting of as and bs
__syncthreads();
ai += Astep;
bi += Bstep;
}
int Cstart = by * n * tail_size + bx * tail_size;
c[Cstart + ty * n + tx] = sum;
}
void sgemm_host(float *a, float *b, float *c, int n)
{
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[i * n + k] * b[k * n + j];
c[i * n + j] = s;
}
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu, tgpu, tmem;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N * N;
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
h_A[i * N + j] = 2.0;
h_B[i * N + j] = 3.0;
}
}
tcpu = -wtime();
sgemm_host(h_A, h_B, h_C, N);
tcpu += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "CPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
tmem = -wtime();
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
/* Launch the kernel */
int threadsPerBlockDim = BLOCK_SIZE;
dim3 blockDim(threadsPerBlockDim, threadsPerBlockDim, 1);
int blocksPerGridDimX = ceilf(N / (float)threadsPerBlockDim);
int blocksPerGridDimY = ceilf(N / (float)threadsPerBlockDim);
dim3 gridDim(blocksPerGridDimX, blocksPerGridDimY, 1);
printf("CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n",
blocksPerGridDimX * blocksPerGridDimY, blocksPerGridDimX, blocksPerGridDimY,
threadsPerBlockDim * threadsPerBlockDim, threadsPerBlockDim, threadsPerBlockDim);
tgpu = -wtime();
//sgemm_naive<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
sgemm_tailed<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "GPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Memory bw. (MiB/sec.): %.2f\n", ((3 * size) >> 20) / tmem);
printf("CPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tcpu);
printf("GPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tgpu);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* sgemm.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
BLOCK_SIZE = 32,
N = 1024
};
__global__ void sgemm_naive(const float *a, const float *b, float *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < n && col < n) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[row * n + k] * b[k * n + col];
c[row * n + col] = s;
}
}
__global__ void sgemm_tailed(const float *a, const float *b, float *c, int n)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
int tail_size = blockDim.x;
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
// Result for c[i, j]
float sum = 0.0;
// Index of first tail (sub-matrix) in A
int Astart = by * n * tail_size;
int Aend = Astart + n - 1;
int Astep = tail_size;
// Index of first tail (sub-matrix) in B
int Bstart = bx * tail_size;
int Bstep = n * tail_size;
int ai = Astart;
int bi = Bstart;
while (ai <= Aend) {
// Load tail to shared memory - each thread load one item
as[ty][tx] = a[ai + ty * n + tx];
bs[ty][tx] = b[bi + ty * n + tx];
// Wait all threads
__syncthreads();
// Compute partial result
for (int k = 0; k < tail_size; k++)
sum += as[ty][k] * bs[k][tx];
// Wait for all threads before overwriting of as and bs
__syncthreads();
ai += Astep;
bi += Bstep;
}
int Cstart = by * n * tail_size + bx * tail_size;
c[Cstart + ty * n + tx] = sum;
}
void sgemm_host(float *a, float *b, float *c, int n)
{
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[i * n + k] * b[k * n + j];
c[i * n + j] = s;
}
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu, tgpu, tmem;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N * N;
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
h_A[i * N + j] = 2.0;
h_B[i * N + j] = 3.0;
}
}
tcpu = -wtime();
sgemm_host(h_A, h_B, h_C, N);
tcpu += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "CPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
tmem = -wtime();
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
/* Launch the kernel */
int threadsPerBlockDim = BLOCK_SIZE;
dim3 blockDim(threadsPerBlockDim, threadsPerBlockDim, 1);
int blocksPerGridDimX = ceilf(N / (float)threadsPerBlockDim);
int blocksPerGridDimY = ceilf(N / (float)threadsPerBlockDim);
dim3 gridDim(blocksPerGridDimX, blocksPerGridDimY, 1);
printf("CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n",
blocksPerGridDimX * blocksPerGridDimY, blocksPerGridDimX, blocksPerGridDimY,
threadsPerBlockDim * threadsPerBlockDim, threadsPerBlockDim, threadsPerBlockDim);
tgpu = -wtime();
//sgemm_naive<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
sgemm_tailed<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "GPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Memory bw. (MiB/sec.): %.2f\n", ((3 * size) >> 20) / tmem);
printf("CPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tcpu);
printf("GPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tgpu);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sgemm_naivePKfS0_Pfi
.globl _Z11sgemm_naivePKfS0_Pfi
.p2align 8
.type _Z11sgemm_naivePKfS0_Pfi,@function
_Z11sgemm_naivePKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sgemm_naivePKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sgemm_naivePKfS0_Pfi, .Lfunc_end0-_Z11sgemm_naivePKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12sgemm_tailedPKfS0_Pfi
.globl _Z12sgemm_tailedPKfS0_Pfi
.p2align 8
.type _Z12sgemm_tailedPKfS0_Pfi,@function
_Z12sgemm_tailedPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_cmp_lt_i32 s3, 1
s_mul_i32 s11, s10, s3
s_mul_i32 s9, s14, s10
s_mul_i32 s8, s11, s15
s_cbranch_scc1 .LBB1_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 2, v1
s_add_i32 s12, s8, s3
s_cmp_lg_u32 s10, 0
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_mov_b32_e32 v3, 0
s_cselect_b32 s2, -1, 0
v_lshlrev_b32_e32 v4, 7, v0
v_or_b32_e32 v5, 0x1000, v6
v_cndmask_b32_e64 v8, 0, 1, s2
s_mov_b32 s13, s9
s_mov_b32 s14, s8
v_add_nc_u32_e32 v6, v4, v6
v_add_nc_u32_e32 v7, v5, v4
v_cmp_ne_u32_e64 s2, 1, v8
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_add_i32 s14, s14, s10
s_add_i32 s13, s13, s11
s_cmp_ge_i32 s14, s12
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_6
.LBB1_3:
v_add_nc_u32_e32 v8, s14, v2
v_add_nc_u32_e32 v10, s13, v2
s_mov_b32 s15, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_and_b32 vcc_lo, exec_lo, s2
global_load_b32 v12, v[8:9], off
global_load_b32 v10, v[10:11], off
v_dual_mov_b32 v9, v4 :: v_dual_mov_b32 v8, v5
s_waitcnt vmcnt(1)
ds_store_b32 v6, v12
s_waitcnt vmcnt(0)
ds_store_b32 v7, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_2
.LBB1_4:
ds_load_b32 v10, v9
ds_load_b32 v11, v8
v_add_nc_u32_e32 v9, 4, v9
v_add_nc_u32_e32 v8, 0x80, v8
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v10, v11
s_cbranch_scc0 .LBB1_4
s_branch .LBB1_2
.LBB1_5:
v_mov_b32_e32 v3, 0
.LBB1_6:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[4:5], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s9, s8, v4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sgemm_tailedPKfS0_Pfi
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12sgemm_tailedPKfS0_Pfi, .Lfunc_end1-_Z12sgemm_tailedPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sgemm_naivePKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sgemm_naivePKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sgemm_tailedPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sgemm_tailedPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* sgemm.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
BLOCK_SIZE = 32,
N = 1024
};
__global__ void sgemm_naive(const float *a, const float *b, float *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if (row < n && col < n) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[row * n + k] * b[k * n + col];
c[row * n + col] = s;
}
}
__global__ void sgemm_tailed(const float *a, const float *b, float *c, int n)
{
__shared__ float as[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float bs[BLOCK_SIZE][BLOCK_SIZE];
int tail_size = blockDim.x;
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
// Result for c[i, j]
float sum = 0.0;
// Index of first tail (sub-matrix) in A
int Astart = by * n * tail_size;
int Aend = Astart + n - 1;
int Astep = tail_size;
// Index of first tail (sub-matrix) in B
int Bstart = bx * tail_size;
int Bstep = n * tail_size;
int ai = Astart;
int bi = Bstart;
while (ai <= Aend) {
// Load tail to shared memory - each thread load one item
as[ty][tx] = a[ai + ty * n + tx];
bs[ty][tx] = b[bi + ty * n + tx];
// Wait all threads
__syncthreads();
// Compute partial result
for (int k = 0; k < tail_size; k++)
sum += as[ty][k] * bs[k][tx];
// Wait for all threads before overwriting of as and bs
__syncthreads();
ai += Astep;
bi += Bstep;
}
int Cstart = by * n * tail_size + bx * tail_size;
c[Cstart + ty * n + tx] = sum;
}
void sgemm_host(float *a, float *b, float *c, int n)
{
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
float s = 0.0;
for (int k = 0; k < n; k++)
s += a[i * n + k] * b[k * n + j];
c[i * n + j] = s;
}
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu, tgpu, tmem;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N * N;
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
h_A[i * N + j] = 2.0;
h_B[i * N + j] = 3.0;
}
}
tcpu = -wtime();
sgemm_host(h_A, h_B, h_C, N);
tcpu += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "CPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
tmem = -wtime();
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
/* Launch the kernel */
int threadsPerBlockDim = BLOCK_SIZE;
dim3 blockDim(threadsPerBlockDim, threadsPerBlockDim, 1);
int blocksPerGridDimX = ceilf(N / (float)threadsPerBlockDim);
int blocksPerGridDimY = ceilf(N / (float)threadsPerBlockDim);
dim3 gridDim(blocksPerGridDimX, blocksPerGridDimY, 1);
printf("CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n",
blocksPerGridDimX * blocksPerGridDimY, blocksPerGridDimX, blocksPerGridDimY,
threadsPerBlockDim * threadsPerBlockDim, threadsPerBlockDim, threadsPerBlockDim);
tgpu = -wtime();
//sgemm_naive<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
sgemm_tailed<<<gridDim, blockDim>>>(d_A, d_B, d_C, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
if (fabs(6.0 * N - h_C[i * N + j]) > 1e-5) {
fprintf(stderr, "GPU results verification failed at element %d %d!\n", i, j);
exit(EXIT_FAILURE);
}
}
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Memory bw. (MiB/sec.): %.2f\n", ((3 * size) >> 20) / tmem);
printf("CPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tcpu);
printf("GPU GFLOPS: %.2f\n", 2.0 * N * N * N * 1.0E-9F / tgpu);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} | .text
.file "sgemm.hip"
.globl _Z26__device_stub__sgemm_naivePKfS0_Pfi # -- Begin function _Z26__device_stub__sgemm_naivePKfS0_Pfi
.p2align 4, 0x90
.type _Z26__device_stub__sgemm_naivePKfS0_Pfi,@function
_Z26__device_stub__sgemm_naivePKfS0_Pfi: # @_Z26__device_stub__sgemm_naivePKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sgemm_naivePKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sgemm_naivePKfS0_Pfi, .Lfunc_end0-_Z26__device_stub__sgemm_naivePKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sgemm_tailedPKfS0_Pfi # -- Begin function _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_tailedPKfS0_Pfi,@function
_Z27__device_stub__sgemm_tailedPKfS0_Pfi: # @_Z27__device_stub__sgemm_tailedPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sgemm_tailedPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__sgemm_tailedPKfS0_Pfi, .Lfunc_end1-_Z27__device_stub__sgemm_tailedPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z10sgemm_hostPfS_S_i # -- Begin function _Z10sgemm_hostPfS_S_i
.p2align 4, 0x90
.type _Z10sgemm_hostPfS_S_i,@function
_Z10sgemm_hostPfS_S_i: # @_Z10sgemm_hostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
xorps %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB2_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB2_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge32
retq
.Lfunc_end2:
.size _Z10sgemm_hostPfS_S_i, .Lfunc_end2-_Z10sgemm_hostPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z5wtimev, .Lfunc_end3-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x40b8000000000000 # double 6144
.LCPI4_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.LCPI4_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI4_4:
.quad 0x4028000000000000 # double 12
.LCPI4_5:
.quad 0x40012e0be0000000 # double 2.1474835872650146
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
testq %r13, %r13
je .LBB4_41
# %bb.1:
testq %r14, %r14
je .LBB4_41
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB4_41
# %bb.3: # %.preheader109.preheader
xorl %eax, %eax
movq %r13, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB4_4: # %.preheader109
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_5: # Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rsi,4) # imm = 0x40000000
movl $1077936128, (%rdx,%rsi,4) # imm = 0x40400000
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_5
# %bb.6: # in Loop: Header=BB4_4 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_4
# %bb.7:
xorl %ebx, %ebx
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbp
movq 24(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq %r13, %rax
.p2align 4, 0x90
.LBB4_8: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
# Child Loop BB4_10 Depth 3
movq %rbx, %rcx
shlq $12, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_9: # %.preheader.i
# Parent Loop BB4_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_10 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_8 Depth=1
# Parent Loop BB4_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_10
# %bb.11: # %._crit_edge.i
# in Loop: Header=BB4_9 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_9
# %bb.12: # %._crit_edge30.i
# in Loop: Header=BB4_8 Depth=1
incq %rbx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_8
# %bb.13: # %_Z10sgemm_hostPfS_S_i.exit
xorl %r12d, %r12d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbx
movq 24(%rsp), %rdx
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
movq %r15, %rax
.p2align 4, 0x90
.LBB4_14: # %.preheader108
# =>This Loop Header: Depth=1
# Child Loop BB4_15 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movapd %xmm2, %xmm1
subsd %xmm0, %xmm1
andpd .LCPI4_1(%rip), %xmm1
ucomisd .LCPI4_2(%rip), %xmm1
ja .LBB4_16
# %bb.18: # in Loop: Header=BB4_15 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB4_15
# %bb.19: # in Loop: Header=BB4_14 Depth=1
incq %r12
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_14
# %bb.20:
movq %rdx, 8(%rsp) # 8-byte Spill
movq $0, 88(%rsp)
movq $0, 80(%rsp)
movq $0, 72(%rsp)
leaq 88(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.22:
leaq 80(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.23:
leaq 72(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.24:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r12
movq 24(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_25
# %bb.28:
movq 80(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_25
# %bb.29:
movq %r13, 168(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 144(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 136(%rsp) # 8-byte Spill
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
movl $32, %edx
movl $32, %ecx
movl $1024, %r8d # imm = 0x400
movl $32, %r9d
xorl %eax, %eax
pushq $32
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_31
# %bb.30:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl $1024, 100(%rsp) # imm = 0x400
leaq 240(%rsp), %rax
movq %rax, 16(%rsp)
leaq 232(%rsp), %rax
movq %rax, 24(%rsp)
leaq 224(%rsp), %rax
movq %rax, 32(%rsp)
leaq 100(%rsp), %rax
movq %rax, 40(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12sgemm_tailedPKfS0_Pfi, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31:
movq %rbx, 152(%rsp) # 8-byte Spill
movq %rbp, 160(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movq 24(%rsp), %r13
callq hipGetLastError
testl %eax, %eax
jne .LBB4_42
# %bb.32:
movq %r12, 104(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbp
movq 24(%rsp), %rbx
movq 72(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_33
# %bb.34:
xorl %r12d, %r12d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
movq %r15, %rsi
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI4_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI4_2(%rip), %xmm4 # xmm4 = mem[0],zero
.p2align 4, 0x90
.LBB4_35: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_36 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_36: # Parent Loop BB4_35 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movapd %xmm2, %xmm1
subsd %xmm0, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
ja .LBB4_37
# %bb.38: # in Loop: Header=BB4_36 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB4_36
# %bb.39: # in Loop: Header=BB4_35 Depth=1
incq %r12
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_35
# %bb.40:
xorps %xmm2, %xmm2
cvtsi2sd %rdx, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm3, %xmm3
cvtsi2sd %rbx, %xmm3
xorps %xmm1, %xmm1
cvtsi2sd %rbp, %xmm1
xorps %xmm4, %xmm4
cvtsi2sd %r13, %xmm4
cvtsi2sdq 112(%rsp), %xmm14 # 8-byte Folded Reload
cvtsi2sdq 120(%rsp), %xmm5 # 8-byte Folded Reload
cvtsi2sdq 128(%rsp), %xmm6 # 8-byte Folded Reload
cvtsi2sdq 136(%rsp), %xmm7 # 8-byte Folded Reload
cvtsi2sdq 144(%rsp), %xmm15 # 8-byte Folded Reload
cvtsi2sdq 64(%rsp), %xmm8 # 8-byte Folded Reload
cvtsi2sdq 104(%rsp), %xmm9 # 8-byte Folded Reload
cvtsi2sdq 8(%rsp), %xmm10 # 8-byte Folded Reload
cvtsi2sdq 152(%rsp), %xmm11 # 8-byte Folded Reload
movsd %xmm11, 8(%rsp) # 8-byte Spill
xorps %xmm11, %xmm11
cvtsi2sdq 56(%rsp), %xmm11 # 8-byte Folded Reload
movsd .LCPI4_3(%rip), %xmm12 # xmm12 = mem[0],zero
mulsd %xmm12, %xmm2
cvtsi2sdq 160(%rsp), %xmm13 # 8-byte Folded Reload
addsd %xmm2, %xmm0
mulsd %xmm12, %xmm3
addsd %xmm3, %xmm1
mulsd %xmm12, %xmm4
addsd %xmm4, %xmm14
mulsd %xmm12, %xmm5
addsd %xmm5, %xmm6
subsd %xmm6, %xmm14
movsd %xmm14, 56(%rsp) # 8-byte Spill
mulsd %xmm12, %xmm7
addsd %xmm7, %xmm15
mulsd %xmm12, %xmm8
addsd %xmm8, %xmm9
subsd %xmm9, %xmm15
subsd %xmm1, %xmm15
addsd %xmm0, %xmm15
movsd %xmm15, 64(%rsp) # 8-byte Spill
mulsd %xmm12, %xmm10
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm10, %xmm0
mulsd %xmm12, %xmm11
addsd %xmm11, %xmm13
subsd %xmm13, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.L.str.9, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.10, %edi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 64(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.11, %edi
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.12, %edi
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.14, %edi
movb $1, %al
callq printf
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 56(%rsp), %xmm1 # 8-byte Folded Reload
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_16:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
jmp .LBB4_17
.LBB4_37:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
.LBB4_17:
movl %r12d, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_21:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
jmp .LBB4_27
.LBB4_25:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
jmp .LBB4_26
.LBB4_41:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB4_27
.LBB4_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_33:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
.LBB4_26:
movl $30, %esi
.LBB4_27:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sgemm_naivePKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_tailedPKfS0_Pfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sgemm_naivePKfS0_Pfi,@object # @_Z11sgemm_naivePKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z11sgemm_naivePKfS0_Pfi
.p2align 3, 0x0
_Z11sgemm_naivePKfS0_Pfi:
.quad _Z26__device_stub__sgemm_naivePKfS0_Pfi
.size _Z11sgemm_naivePKfS0_Pfi, 8
.type _Z12sgemm_tailedPKfS0_Pfi,@object # @_Z12sgemm_tailedPKfS0_Pfi
.globl _Z12sgemm_tailedPKfS0_Pfi
.p2align 3, 0x0
_Z12sgemm_tailedPKfS0_Pfi:
.quad _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.size _Z12sgemm_tailedPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU results verification failed at element %d %d!\n"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Allocation error\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Host to device copying failed\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n"
.size .L.str.4, 65
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Device to host copying failed\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU results verification failed at element %d %d!\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Memory ops. (sec.): %.6f\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Memory bw. (MiB/sec.): %.2f\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "CPU GFLOPS: %.2f\n"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "GPU GFLOPS: %.2f\n"
.size .L.str.13, 18
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Speedup: %.2f\n"
.size .L.str.14, 15
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.15, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11sgemm_naivePKfS0_Pfi"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12sgemm_tailedPKfS0_Pfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sgemm_naivePKfS0_Pfi
.addrsig_sym _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sgemm_naivePKfS0_Pfi
.addrsig_sym _Z12sgemm_tailedPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000000b3_00000000-6_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10sgemm_hostPfS_S_i
.type _Z10sgemm_hostPfS_S_i, @function
_Z10sgemm_hostPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L5:
movq %rbx, %r8
movl $0, %edi
.L8:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L6
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %r11, %rdi
jne .L8
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z10sgemm_hostPfS_S_i, .-_Z10sgemm_hostPfS_S_i
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
.type _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi, @function
_Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sgemm_naivePKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi, .-_Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
.globl _Z11sgemm_naivePKfS0_Pfi
.type _Z11sgemm_naivePKfS0_Pfi, @function
_Z11sgemm_naivePKfS0_Pfi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11sgemm_naivePKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11sgemm_naivePKfS0_Pfi, .-_Z11sgemm_naivePKfS0_Pfi
.globl _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
.type _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi, @function
_Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sgemm_tailedPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi, .-_Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
.globl _Z12sgemm_tailedPKfS0_Pfi
.type _Z12sgemm_tailedPKfS0_Pfi, @function
_Z12sgemm_tailedPKfS0_Pfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12sgemm_tailedPKfS0_Pfi, .-_Z12sgemm_tailedPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocation error.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "CPU results verification failed at element %d %d!\n"
.section .rodata.str1.1
.LC9:
.string "Allocation error\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Host to device copying failed\n"
.align 8
.LC11:
.string "CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n"
.align 8
.LC12:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC13:
.string "Device to host copying failed\n"
.align 8
.LC14:
.string "GPU results verification failed at element %d %d!\n"
.section .rodata.str1.1
.LC15:
.string "CPU version (sec.): %.6f\n"
.LC16:
.string "GPU version (sec.): %.6f\n"
.LC17:
.string "Memory ops. (sec.): %.6f\n"
.LC19:
.string "Memory bw. (MiB/sec.): %.2f\n"
.LC21:
.string "CPU GFLOPS: %.2f\n"
.LC22:
.string "GPU GFLOPS: %.2f\n"
.LC23:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC24:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L59
testq %r12, %r12
je .L59
movl $4096, %edx
movss .LC3(%rip), %xmm1
movss .LC4(%rip), %xmm0
.L35:
leaq -4096(%rdx), %rax
.L37:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L37
addq $4096, %rdx
cmpq $4198400, %rdx
jne .L35
call _Z5wtimev
movsd %xmm0, 8(%rsp)
movl $1024, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10sgemm_hostPfS_S_i
call _Z5wtimev
movsd %xmm0, 32(%rsp)
movq %r12, %r13
movq %r12, %rax
movl $0, %ecx
movsd .LC5(%rip), %xmm4
movq .LC6(%rip), %xmm3
movsd .LC7(%rip), %xmm2
jmp .L39
.L59:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L68:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
addl $1, %ecx
addq $4096, %rax
cmpl $1024, %ecx
je .L43
.L39:
movl $0, %r8d
.L42:
pxor %xmm1, %xmm1
cvtss2sd (%rax,%r8,4), %xmm1
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
andpd %xmm3, %xmm0
comisd %xmm2, %xmm0
ja .L68
addq $1, %r8
cmpq $1024, %r8
jne .L42
jmp .L69
.L43:
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L70
leaq 80(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L71
leaq 88(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L72
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L73
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L74
call _Z5wtimev
movsd %xmm0, 40(%rsp)
movl $32, 96(%rsp)
movl $32, 100(%rsp)
movl $1, 104(%rsp)
movl $32, 108(%rsp)
movl $32, 112(%rsp)
movl $1, 116(%rsp)
pushq $32
.cfi_def_cfa_offset 184
pushq $32
.cfi_def_cfa_offset 192
movl $1024, %r9d
movl $32, %r8d
movl $32, %ecx
movl $1024, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z5wtimev
movsd %xmm0, 40(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L49:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
movsd %xmm0, 48(%rsp)
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
call _Z5wtimev
movsd %xmm0, 56(%rsp)
movl $2, %ecx
movl $4194304, %edx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L77
call _Z5wtimev
movapd %xmm0, %xmm5
movl $0, %ecx
movsd .LC5(%rip), %xmm4
movq .LC6(%rip), %xmm3
movsd .LC7(%rip), %xmm2
jmp .L52
.L70:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl $1024, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z12sgemm_tailedPKfS0_PfiPKfS0_Pfi
jmp .L49
.L76:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L79:
addl $1, %ecx
addq $4096, %r13
cmpl $1024, %ecx
je .L56
.L52:
movl $0, %r8d
.L55:
pxor %xmm1, %xmm1
cvtss2sd 0(%r13,%r8,4), %xmm1
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
andpd %xmm3, %xmm0
comisd %xmm2, %xmm0
ja .L78
addq $1, %r8
cmpq $1024, %r8
jne .L55
jmp .L79
.L56:
movsd 32(%rsp), %xmm6
subsd 8(%rsp), %xmm6
movsd 48(%rsp), %xmm7
subsd 24(%rsp), %xmm7
movsd %xmm7, 8(%rsp)
movsd 40(%rsp), %xmm0
subsd 16(%rsp), %xmm0
subsd 56(%rsp), %xmm0
addsd %xmm5, %xmm0
movsd %xmm0, 24(%rsp)
movsd %xmm6, 16(%rsp)
movapd %xmm6, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC18(%rip), %xmm0
divsd 24(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC20(%rip), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC20(%rip), %xmm3
divsd 8(%rsp), %xmm3
movapd %xmm3, %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm7
addsd 24(%rsp), %xmm7
movsd 16(%rsp), %xmm6
divsd %xmm7, %xmm6
movapd %xmm6, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC25:
.string "_Z12sgemm_tailedPKfS0_Pfi"
.LC26:
.string "_Z11sgemm_naivePKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sgemm_tailedPKfS0_Pfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sgemm_naivePKfS0_Pfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst8
.align 8
.LC5:
.long 0
.long 1085800448
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC7:
.long -1998362383
.long 1055193269
.align 8
.LC18:
.long 0
.long 1076363264
.align 8
.LC20:
.long -536870912
.long 1073819147
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemm.hip"
.globl _Z26__device_stub__sgemm_naivePKfS0_Pfi # -- Begin function _Z26__device_stub__sgemm_naivePKfS0_Pfi
.p2align 4, 0x90
.type _Z26__device_stub__sgemm_naivePKfS0_Pfi,@function
_Z26__device_stub__sgemm_naivePKfS0_Pfi: # @_Z26__device_stub__sgemm_naivePKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sgemm_naivePKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__sgemm_naivePKfS0_Pfi, .Lfunc_end0-_Z26__device_stub__sgemm_naivePKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sgemm_tailedPKfS0_Pfi # -- Begin function _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.p2align 4, 0x90
.type _Z27__device_stub__sgemm_tailedPKfS0_Pfi,@function
_Z27__device_stub__sgemm_tailedPKfS0_Pfi: # @_Z27__device_stub__sgemm_tailedPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sgemm_tailedPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__sgemm_tailedPKfS0_Pfi, .Lfunc_end1-_Z27__device_stub__sgemm_tailedPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z10sgemm_hostPfS_S_i # -- Begin function _Z10sgemm_hostPfS_S_i
.p2align 4, 0x90
.type _Z10sgemm_hostPfS_S_i,@function
_Z10sgemm_hostPfS_S_i: # @_Z10sgemm_hostPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_8
# %bb.1: # %.preheader26.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %eax
leaq (,%rax,4), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
movl %r9d, %r11d
leaq (%rdi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
leaq (%rdx,%rbx,4), %rbx
movq %rsi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
xorps %xmm0, %xmm0
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB2_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB2_3 Depth=2
movss %xmm0, (%rbx,%r15,4)
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB2_3
# %bb.6: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
cmpq %rax, %r10
jne .LBB2_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_8: # %._crit_edge32
retq
.Lfunc_end2:
.size _Z10sgemm_hostPfS_S_i, .Lfunc_end2-_Z10sgemm_hostPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z5wtimev, .Lfunc_end3-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x40b8000000000000 # double 6144
.LCPI4_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.LCPI4_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI4_4:
.quad 0x4028000000000000 # double 12
.LCPI4_5:
.quad 0x40012e0be0000000 # double 2.1474835872650146
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI4_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
testq %r13, %r13
je .LBB4_41
# %bb.1:
testq %r14, %r14
je .LBB4_41
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB4_41
# %bb.3: # %.preheader109.preheader
xorl %eax, %eax
movq %r13, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB4_4: # %.preheader109
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_5: # Parent Loop BB4_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rsi,4) # imm = 0x40000000
movl $1077936128, (%rdx,%rsi,4) # imm = 0x40400000
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_5
# %bb.6: # in Loop: Header=BB4_4 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB4_4
# %bb.7:
xorl %ebx, %ebx
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbp
movq 24(%rsp), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq %r13, %rax
.p2align 4, 0x90
.LBB4_8: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
# Child Loop BB4_10 Depth 3
movq %rbx, %rcx
shlq $12, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_9: # %.preheader.i
# Parent Loop BB4_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_10 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_8 Depth=1
# Parent Loop BB4_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $4096, %rdi # imm = 0x1000
cmpq $1024, %r8 # imm = 0x400
jne .LBB4_10
# %bb.11: # %._crit_edge.i
# in Loop: Header=BB4_9 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $1024, %rsi # imm = 0x400
jne .LBB4_9
# %bb.12: # %._crit_edge30.i
# in Loop: Header=BB4_8 Depth=1
incq %rbx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_8
# %bb.13: # %_Z10sgemm_hostPfS_S_i.exit
xorl %r12d, %r12d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbx
movq 24(%rsp), %rdx
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
movq %r15, %rax
.p2align 4, 0x90
.LBB4_14: # %.preheader108
# =>This Loop Header: Depth=1
# Child Loop BB4_15 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movapd %xmm2, %xmm1
subsd %xmm0, %xmm1
andpd .LCPI4_1(%rip), %xmm1
ucomisd .LCPI4_2(%rip), %xmm1
ja .LBB4_16
# %bb.18: # in Loop: Header=BB4_15 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB4_15
# %bb.19: # in Loop: Header=BB4_14 Depth=1
incq %r12
addq $4096, %rax # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_14
# %bb.20:
movq %rdx, 8(%rsp) # 8-byte Spill
movq $0, 88(%rsp)
movq $0, 80(%rsp)
movq $0, 72(%rsp)
leaq 88(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.22:
leaq 80(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.23:
leaq 72(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.24:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r12
movq 24(%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_25
# %bb.28:
movq 80(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_25
# %bb.29:
movq %r13, 168(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 144(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 136(%rsp) # 8-byte Spill
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
movl $32, %edx
movl $32, %ecx
movl $1024, %r8d # imm = 0x400
movl $32, %r9d
xorl %eax, %eax
pushq $32
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_31
# %bb.30:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl $1024, 100(%rsp) # imm = 0x400
leaq 240(%rsp), %rax
movq %rax, 16(%rsp)
leaq 232(%rsp), %rax
movq %rax, 24(%rsp)
leaq 224(%rsp), %rax
movq %rax, 32(%rsp)
leaq 100(%rsp), %rax
movq %rax, 40(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12sgemm_tailedPKfS0_Pfi, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31:
movq %rbx, 152(%rsp) # 8-byte Spill
movq %rbp, 160(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movq 24(%rsp), %r13
callq hipGetLastError
testl %eax, %eax
jne .LBB4_42
# %bb.32:
movq %r12, 104(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rbp
movq 24(%rsp), %rbx
movq 72(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_33
# %bb.34:
xorl %r12d, %r12d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
movq %r15, %rsi
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
movapd .LCPI4_1(%rip), %xmm3 # xmm3 = [NaN,NaN]
movsd .LCPI4_2(%rip), %xmm4 # xmm4 = mem[0],zero
.p2align 4, 0x90
.LBB4_35: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_36 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_36: # Parent Loop BB4_35 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movapd %xmm2, %xmm1
subsd %xmm0, %xmm1
andpd %xmm3, %xmm1
ucomisd %xmm4, %xmm1
ja .LBB4_37
# %bb.38: # in Loop: Header=BB4_36 Depth=2
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB4_36
# %bb.39: # in Loop: Header=BB4_35 Depth=1
incq %r12
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB4_35
# %bb.40:
xorps %xmm2, %xmm2
cvtsi2sd %rdx, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm3, %xmm3
cvtsi2sd %rbx, %xmm3
xorps %xmm1, %xmm1
cvtsi2sd %rbp, %xmm1
xorps %xmm4, %xmm4
cvtsi2sd %r13, %xmm4
cvtsi2sdq 112(%rsp), %xmm14 # 8-byte Folded Reload
cvtsi2sdq 120(%rsp), %xmm5 # 8-byte Folded Reload
cvtsi2sdq 128(%rsp), %xmm6 # 8-byte Folded Reload
cvtsi2sdq 136(%rsp), %xmm7 # 8-byte Folded Reload
cvtsi2sdq 144(%rsp), %xmm15 # 8-byte Folded Reload
cvtsi2sdq 64(%rsp), %xmm8 # 8-byte Folded Reload
cvtsi2sdq 104(%rsp), %xmm9 # 8-byte Folded Reload
cvtsi2sdq 8(%rsp), %xmm10 # 8-byte Folded Reload
cvtsi2sdq 152(%rsp), %xmm11 # 8-byte Folded Reload
movsd %xmm11, 8(%rsp) # 8-byte Spill
xorps %xmm11, %xmm11
cvtsi2sdq 56(%rsp), %xmm11 # 8-byte Folded Reload
movsd .LCPI4_3(%rip), %xmm12 # xmm12 = mem[0],zero
mulsd %xmm12, %xmm2
cvtsi2sdq 160(%rsp), %xmm13 # 8-byte Folded Reload
addsd %xmm2, %xmm0
mulsd %xmm12, %xmm3
addsd %xmm3, %xmm1
mulsd %xmm12, %xmm4
addsd %xmm4, %xmm14
mulsd %xmm12, %xmm5
addsd %xmm5, %xmm6
subsd %xmm6, %xmm14
movsd %xmm14, 56(%rsp) # 8-byte Spill
mulsd %xmm12, %xmm7
addsd %xmm7, %xmm15
mulsd %xmm12, %xmm8
addsd %xmm8, %xmm9
subsd %xmm9, %xmm15
subsd %xmm1, %xmm15
addsd %xmm0, %xmm15
movsd %xmm15, 64(%rsp) # 8-byte Spill
mulsd %xmm12, %xmm10
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm10, %xmm0
mulsd %xmm12, %xmm11
addsd %xmm11, %xmm13
subsd %xmm13, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.L.str.9, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.10, %edi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 64(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.11, %edi
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.12, %edi
movb $1, %al
callq printf
movsd .LCPI4_5(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.14, %edi
movb $1, %al
callq printf
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 56(%rsp), %xmm1 # 8-byte Folded Reload
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_16:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
jmp .LBB4_17
.LBB4_37:
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
.LBB4_17:
movl %r12d, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_21:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
jmp .LBB4_27
.LBB4_25:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
jmp .LBB4_26
.LBB4_41:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB4_27
.LBB4_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_33:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
.LBB4_26:
movl $30, %esi
.LBB4_27:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sgemm_naivePKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sgemm_tailedPKfS0_Pfi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sgemm_naivePKfS0_Pfi,@object # @_Z11sgemm_naivePKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z11sgemm_naivePKfS0_Pfi
.p2align 3, 0x0
_Z11sgemm_naivePKfS0_Pfi:
.quad _Z26__device_stub__sgemm_naivePKfS0_Pfi
.size _Z11sgemm_naivePKfS0_Pfi, 8
.type _Z12sgemm_tailedPKfS0_Pfi,@object # @_Z12sgemm_tailedPKfS0_Pfi
.globl _Z12sgemm_tailedPKfS0_Pfi
.p2align 3, 0x0
_Z12sgemm_tailedPKfS0_Pfi:
.quad _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.size _Z12sgemm_tailedPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU results verification failed at element %d %d!\n"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Allocation error\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Host to device copying failed\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA kernel launch with %d (%d %d) blocks of %d (%d %d) threads\n"
.size .L.str.4, 65
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.5, 42
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Device to host copying failed\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU results verification failed at element %d %d!\n"
.size .L.str.7, 51
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Memory ops. (sec.): %.6f\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Memory bw. (MiB/sec.): %.2f\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "CPU GFLOPS: %.2f\n"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "GPU GFLOPS: %.2f\n"
.size .L.str.13, 18
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Speedup: %.2f\n"
.size .L.str.14, 15
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.15, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11sgemm_naivePKfS0_Pfi"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12sgemm_tailedPKfS0_Pfi"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sgemm_naivePKfS0_Pfi
.addrsig_sym _Z27__device_stub__sgemm_tailedPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sgemm_naivePKfS0_Pfi
.addrsig_sym _Z12sgemm_tailedPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 512
#define BLOCK_DIM 512
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
cudaMalloc((void**)&dev_a, size);
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} | code for sm_80
Function : _Z9matrixAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x1ff, P0 ; /* 0x000001ff0000780c */
/* 0x000fe40000704670 */
/*0090*/ LEA R0, R3, R0, 0x9 ; /* 0x0000000003007211 */
/* 0x000fd600078e48ff */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 512
#define BLOCK_DIM 512
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
cudaMalloc((void**)&dev_a, size);
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} | .file "tmpxft_000e11ed_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.type _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, @function
_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, .-_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.globl _Z9matrixAddPiS_S_
.type _Z9matrixAddPiS_S_, @function
_Z9matrixAddPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9matrixAddPiS_S_, .-_Z9matrixAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -3145728(%rsp), %r11
.cfi_def_cfa 11, 3145760
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 3145840
movq %fs:40, %rax
movq %rax, 3145800(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdx
leaq 1048640(%rsp), %rcx
movq %rcx, %rsi
.L12:
movl $0, %eax
.L13:
movl $1, (%rdx,%rax)
movl $1, (%rcx,%rax)
addq $4, %rax
cmpq $2048, %rax
jne .L13
addq $2048, %rdx
addq $2048, %rcx
cmpq %rsi, %rdx
jne .L12
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1048640(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $512, 40(%rsp)
movl $512, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 2097216(%rsp), %rdi
movl $2, %ecx
movl $1048576, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2099264(%rsp), %rbp
leaq 3147840(%rsp), %r12
movl $0x00000000, 12(%rsp)
.L16:
leaq -2048(%rbp), %rbx
.L17:
movl (%rbx), %eax
subl $2, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
andpd .LC1(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call fmax@PLT
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $2048, %rbp
cmpq %r12, %rbp
jne .L16
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 1048640(%rsp), %rdi
call cudaFree@PLT
leaq 2097216(%rsp), %rdi
call cudaFree@PLT
movq 3145800(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $3145808, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9matrixAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 512
#define BLOCK_DIM 512
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
cudaMalloc((void**)&dev_a, size);
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, size);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(a);
cudaFree(b);
cudaFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} | #define N 512
#define BLOCK_DIM 512
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(a);
hipFree(b);
hipFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define N 512
#define BLOCK_DIM 512
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(a);
hipFree(b);
hipFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPiS_S_
.globl _Z9matrixAddPiS_S_
.p2align 8
.type _Z9matrixAddPiS_S_,@function
_Z9matrixAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x200, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 9, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPiS_S_, .Lfunc_end0-_Z9matrixAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define N 512
#define BLOCK_DIM 512
#include <hip/hip_runtime.h>
#include <iostream>
__global__ void matrixAdd (int *a, int *b, int *c);
int main() {
int a[N][N], b[N][N], c[N][N];
int *dev_a, *dev_b, *dev_c;
int size = N * N * sizeof(int);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i][j] = 1;
b[i][j] = 1;
}
}
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, size);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
dim3 dimBlock(BLOCK_DIM, BLOCK_DIM);
dim3 dimGrid((int)ceil(N/dimBlock.x),(int)ceil(N/dimBlock.y));
matrixAdd<<<dimGrid,dimBlock>>>(dev_a,dev_b,dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(c[i][j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(a);
hipFree(b);
hipFree(c);
}
__global__ void matrixAdd (int *a, int *b, int *c) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int index = col + row * N;
if (col < N && row < N) {
c[index] = a[index] + b[index];
}
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $3145848, %rsp # imm = 0x300078
.cfi_def_cfa_offset 3145872
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 2097264(%rsp), %rax
leaq 1048688(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_1: # %.preheader34
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rsi,4)
movl $1, (%rcx,%rsi,4)
incq %rsi
cmpq $512, %rsi # imm = 0x200
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $2048, %rax # imm = 0x800
addq $2048, %rcx # imm = 0x800
cmpq $512, %rdx # imm = 0x200
jne .LBB0_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 2097264(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 1048688(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $2199023256064, %rdx # imm = 0x20000000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI0_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
.p2align 4, 0x90
.LBB0_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_7 Depth=1
# => This Inner Loop Header: Depth=2
cvtss2sd %xmm1, %xmm1
movl (%rbx,%rcx,4), %edx
addl $-2, %edx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
andpd %xmm0, %xmm2
maxsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
incq %rcx
cmpq $512, %rcx # imm = 0x200
jne .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
incq %rax
addq $2048, %rbx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB0_7
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB0_14
.LBB0_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 2097264(%rsp), %rdi
callq hipFree
leaq 1048688(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $3145848, %rsp # imm = 0x300078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 3145872
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixAddPiS_S_ # -- Begin function _Z24__device_stub__matrixAddPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPiS_S_,@function
_Z24__device_stub__matrixAddPiS_S_: # @_Z24__device_stub__matrixAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__matrixAddPiS_S_, .Lfunc_end1-_Z24__device_stub__matrixAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPiS_S_,@object # @_Z9matrixAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPiS_S_
.p2align 3, 0x0
_Z9matrixAddPiS_S_:
.quad _Z24__device_stub__matrixAddPiS_S_
.size _Z9matrixAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: "
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0x1ff, PT ; /* 0x000001ff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x1ff, P0 ; /* 0x000001ff0000780c */
/* 0x000fe40000704670 */
/*0090*/ LEA R0, R3, R0, 0x9 ; /* 0x0000000003007211 */
/* 0x000fd600078e48ff */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPiS_S_
.globl _Z9matrixAddPiS_S_
.p2align 8
.type _Z9matrixAddPiS_S_,@function
_Z9matrixAddPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x200, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 9, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPiS_S_, .Lfunc_end0-_Z9matrixAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e11ed_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.type _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, @function
_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, .-_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.globl _Z9matrixAddPiS_S_
.type _Z9matrixAddPiS_S_, @function
_Z9matrixAddPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9matrixAddPiS_S_, .-_Z9matrixAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -3145728(%rsp), %r11
.cfi_def_cfa 11, 3145760
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 3145840
movq %fs:40, %rax
movq %rax, 3145800(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdx
leaq 1048640(%rsp), %rcx
movq %rcx, %rsi
.L12:
movl $0, %eax
.L13:
movl $1, (%rdx,%rax)
movl $1, (%rcx,%rax)
addq $4, %rax
cmpq $2048, %rax
jne .L13
addq $2048, %rdx
addq $2048, %rcx
cmpq %rsi, %rdx
jne .L12
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 1048640(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $512, 40(%rsp)
movl $512, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 2097216(%rsp), %rdi
movl $2, %ecx
movl $1048576, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2099264(%rsp), %rbp
leaq 3147840(%rsp), %r12
movl $0x00000000, 12(%rsp)
.L16:
leaq -2048(%rbp), %rbx
.L17:
movl (%rbx), %eax
subl $2, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
andpd .LC1(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call fmax@PLT
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $2048, %rbp
cmpq %r12, %rbp
jne .L16
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 64(%rsp), %rdi
call cudaFree@PLT
leaq 1048640(%rsp), %rdi
call cudaFree@PLT
leaq 2097216(%rsp), %rdi
call cudaFree@PLT
movq 3145800(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $3145808, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9matrixAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC1:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $3145848, %rsp # imm = 0x300078
.cfi_def_cfa_offset 3145872
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 2097264(%rsp), %rax
leaq 1048688(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_1: # %.preheader34
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rsi,4)
movl $1, (%rcx,%rsi,4)
incq %rsi
cmpq $512, %rsi # imm = 0x200
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
addq $2048, %rax # imm = 0x800
addq $2048, %rcx # imm = 0x800
cmpq $512, %rdx # imm = 0x200
jne .LBB0_1
# %bb.4:
leaq 32(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
movq 32(%rsp), %rdi
leaq 2097264(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 1048688(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $2199023256064, %rdx # imm = 0x20000000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 16(%rsp), %rsi
leaq 112(%rsp), %rbx
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
xorl %eax, %eax
movapd .LCPI0_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
.p2align 4, 0x90
.LBB0_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_8: # Parent Loop BB0_7 Depth=1
# => This Inner Loop Header: Depth=2
cvtss2sd %xmm1, %xmm1
movl (%rbx,%rcx,4), %edx
addl $-2, %edx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
andpd %xmm0, %xmm2
maxsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
incq %rcx
cmpq $512, %rcx # imm = 0x200
jne .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
incq %rax
addq $2048, %rbx # imm = 0x800
cmpq $512, %rax # imm = 0x200
jne .LBB0_7
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
movss %xmm1, 12(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB0_14
.LBB0_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 2097264(%rsp), %rdi
callq hipFree
leaq 1048688(%rsp), %rdi
callq hipFree
leaq 112(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $3145848, %rsp # imm = 0x300078
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 3145872
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixAddPiS_S_ # -- Begin function _Z24__device_stub__matrixAddPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPiS_S_,@function
_Z24__device_stub__matrixAddPiS_S_: # @_Z24__device_stub__matrixAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__matrixAddPiS_S_, .Lfunc_end1-_Z24__device_stub__matrixAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPiS_S_,@object # @_Z9matrixAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPiS_S_
.p2align 3, 0x0
_Z9matrixAddPiS_S_:
.quad _Z24__device_stub__matrixAddPiS_S_
.size _Z9matrixAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: "
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
cudaMalloc((void**)&darray2D, n*n*sizeof(float));
cudaMemcpy(darray2D, array2D, n*n*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
cudaMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} | code for sm_80
Function : _Z19transpose_device_v3PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ LEA R11, R0, R5, 0x4 ; /* 0x00000005000b7211 */
/* 0x000fe400078e20ff */
/*0100*/ LEA R7, R9.reuse, R4, 0x4 ; /* 0x0000000409077211 */
/* 0x040fe200078e20ff */
/*0110*/ IMAD R4, R9, c[0x0][0x174], R4 ; /* 0x00005d0009047a24 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e020d */
/*0130*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
cudaMalloc((void**)&darray2D, n*n*sizeof(float));
cudaMemcpy(darray2D, array2D, n*n*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
cudaMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} | .file "tmpxft_000aaa1a_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15getMicroSecondsv
.type _Z15getMicroSecondsv, @function
_Z15getMicroSecondsv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZL3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZL3tv0(%rip), %rax
addq 8+_ZL3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15getMicroSecondsv, .-_Z15getMicroSecondsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "/dev/urandom"
.text
.globl _Z9init_seedv
.type _Z9init_seedv, @function
_Z9init_seedv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $1, 4(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 4(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl 4(%rsp), %edi
call srand@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9init_seedv, .-_Z9init_seedv
.globl _Z10init2DrandPPfi
.type _Z10init2DrandPPfi, @function
_Z10init2DrandPPfi:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r13
leaq 0(,%rsi,4), %r12
.L11:
movl $0, %ebx
.L12:
call rand@PLT
movq 0(%rbp), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC3(%rip), %xmm0
subsd .LC3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdx,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
addq $8, %rbp
cmpq %r13, %rbp
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2059:
.size _Z10init2DrandPPfi, .-_Z10init2DrandPPfi
.section .rodata.str1.1
.LC4:
.string "ERROR in memory allocation\n"
.text
.globl _Z11getmemory1Di
.type _Z11getmemory1Di, @function
_Z11getmemory1Di:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movslq %edi, %r12
leaq 0(,%r12,8), %rdi
call malloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L19
leaq (%rax,%r12,4), %rdx
testl %ebp, %ebp
jle .L18
.L22:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
.L18:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z11getmemory1Di, .-_Z11getmemory1Di
.globl _Z11getmemory2Dii
.type _Z11getmemory2Dii, @function
_Z11getmemory2Dii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r13d
movl %esi, %ebx
movslq %edi, %rsi
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L42
movl %r13d, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 0(%rbp)
testq %rax, %rax
je .L29
cmpl $1, %r13d
jle .L43
movslq %ebx, %rcx
salq $2, %rcx
movq %rbp, %rax
leal -1(%r13), %edx
leaq 0(%rbp,%rdx,8), %rsi
.L32:
movq %rcx, %rdx
addq (%rax), %rdx
movq %rdx, 8(%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L32
.L33:
movq %rbp, %rcx
leaq (%r12,%rbp), %rsi
movslq %ebx, %rdi
salq $2, %rdi
jmp .L34
.L42:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L29:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rbp
jmp .L26
.L43:
testl %r13d, %r13d
jg .L33
.L26:
movq %rbp, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq (%rcx), %rax
leaq (%rdi,%rax), %rdx
.L35:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L35
.L37:
addq $8, %rcx
cmpq %rsi, %rcx
je .L26
.L34:
testl %ebx, %ebx
jg .L36
jmp .L37
.cfi_endproc
.LFE2061:
.size _Z11getmemory2Dii, .-_Z11getmemory2Dii
.globl _Z11transpose2DPPfS0_i
.type _Z11transpose2DPPfS0_i, @function
_Z11transpose2DPPfS0_i:
.LFB2062:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L44
movslq %edx, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %ecx
.L46:
movl $0, %eax
.L47:
movq (%rdi,%rax,2), %rdx
movss (%rdx,%rcx), %xmm0
movq (%rsi), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L47
addq $4, %rcx
addq $8, %rsi
cmpq %r8, %rcx
jne .L46
.L44:
ret
.cfi_endproc
.LFE2062:
.size _Z11transpose2DPPfS0_i, .-_Z11transpose2DPPfS0_i
.globl _Z11transpose1DPfS_i
.type _Z11transpose1DPfS_i, @function
_Z11transpose1DPfS_i:
.LFB2063:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L49
movslq %edx, %r10
leaq 0(,%r10,4), %r8
addq %r8, %rsi
negq %r10
salq $2, %r10
movl $0, %r9d
.L51:
leaq (%rsi,%r10), %rax
movq %rdi, %rcx
.L52:
movss (%rcx), %xmm0
movss %xmm0, (%rax)
addq %r8, %rcx
addq $4, %rax
cmpq %rsi, %rax
jne .L52
addl $1, %r9d
addq $4, %rdi
addq %r8, %rsi
cmpl %r9d, %edx
jne .L51
.L49:
ret
.cfi_endproc
.LFE2063:
.size _Z11transpose1DPfS_i, .-_Z11transpose1DPfS_i
.globl _Z5checkPfPS_i
.type _Z5checkPfPS_i, @function
_Z5checkPfPS_i:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L59
movq %rsi, %r8
movslq %edx, %rdx
leaq 0(,%rdx,4), %rcx
leaq (%rsi,%rdx,8), %rsi
.L56:
movq (%r8), %rdx
movl $0, %eax
.L58:
movss (%rdi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L60
jne .L60
addq $4, %rax
cmpq %rcx, %rax
jne .L58
addq $8, %r8
addq %rcx, %rdi
cmpq %rsi, %r8
jne .L56
movl $0, %eax
ret
.L59:
movl $0, %eax
ret
.L60:
movl $1, %eax
ret
.cfi_endproc
.LFE2064:
.size _Z5checkPfPS_i, .-_Z5checkPfPS_i
.section .rodata.str1.1
.LC6:
.string "%4.1f "
.LC7:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L64
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC6(%rip), %r12
jmp .L66
.L68:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L67:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L67
.L69:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L64
.L66:
testl %r15d, %r15d
jg .L68
jmp .L69
.L64:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.globl _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
.type _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii, @function
_Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19transpose_device_v3PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L72
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii, .-_Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
.globl _Z19transpose_device_v3PfS_ii
.type _Z19transpose_device_v3PfS_ii, @function
_Z19transpose_device_v3PfS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z19transpose_device_v3PfS_ii, .-_Z19transpose_device_v3PfS_ii
.section .rodata.str1.1
.LC8:
.string "./exec n (by default n=%i)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Transpose version 2D: %f MB/s\n"
.align 8
.LC16:
.string "Transpose kernel version: %f MB/s\n"
.section .rodata.str1.1
.LC17:
.string "Matriz GPU:\n"
.LC18:
.string "Matriz CPU\n"
.LC19:
.string "Transpose CPU-GPU differs!!\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L94
movl $4096, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %ebx
.L82:
call _Z9init_seedv
movl %ebx, %esi
movl %ebx, %edi
call _Z11getmemory2Dii
movq %rax, %r13
movl %ebx, %esi
movl %ebx, %edi
call _Z11getmemory2Dii
movq %rax, %r15
movq %rax, (%rsp)
movl %ebx, %esi
movq %r13, %rdi
call _Z10init2DrandPPfi
call _Z15getMicroSecondsv
movsd %xmm0, 16(%rsp)
movl %ebx, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z11transpose2DPPfS0_i
movl %ebx, %eax
imull %ebx, %eax
movl %eax, 12(%rsp)
movslq %eax, %r12
salq $2, %r12
js .L83
pxor %xmm7, %xmm7
cvtsi2sdq %r12, %xmm7
movq %xmm7, %rbp
.L84:
call _Z15getMicroSecondsv
movapd %xmm0, %xmm1
subsd 16(%rsp), %xmm1
divsd .LC9(%rip), %xmm1
movq %rbp, %xmm0
divsd %xmm1, %xmm0
movsd .LC10(%rip), %xmm1
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC12(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC20(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC13(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L85
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC15(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L85:
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
call _Z15getMicroSecondsv
movsd %xmm0, 16(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L86:
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call _Z15getMicroSecondsv
movapd %xmm0, %xmm1
subsd 16(%rsp), %xmm1
divsd .LC9(%rip), %xmm1
movq %rbp, %xmm0
divsd %xmm1, %xmm0
movsd .LC10(%rip), %xmm1
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r14, %rdi
call _Z12print_matrixPfii
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L87
movq (%rsp), %rax
movq %rax, %rbp
movslq %ebx, %rbx
leaq (%rax,%rbx,8), %r15
leaq 0(,%rbx,4), %r12
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
.L88:
movl $0, %ebx
.L89:
movq 0(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L89
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r15, %rbp
jne .L88
.L87:
movl 12(%rsp), %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call _Z5checkPfPS_i
testl %eax, %eax
jne .L96
.L90:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L97
movl $1, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L82
.L83:
movq %r12, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %rbp
jmp .L84
.L95:
movl %ebx, %ecx
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
jmp .L86
.L96:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L90
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z19transpose_device_v3PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z19transpose_device_v3PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3tv0
.comm _ZL3tv0,16,16
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1082081280
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1062207488
.section .rodata.cst4
.align 4
.LC12:
.long 1031798784
.align 4
.LC13:
.long 1258291200
.align 4
.LC15:
.long 1065353216
.align 4
.LC20:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
cudaMalloc((void**)&darray2D, n*n*sizeof(float));
cudaMemcpy(darray2D, array2D, n*n*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
cudaMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
hipMalloc((void**)&darray2D, n*n*sizeof(float));
hipMemcpy(darray2D, array2D, n*n*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
hipMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
hipMalloc((void**)&darray2D, n*n*sizeof(float));
hipMemcpy(darray2D, array2D, n*n*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
hipMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19transpose_device_v3PfS_ii
.globl _Z19transpose_device_v3PfS_ii
.p2align 8
.type _Z19transpose_device_v3PfS_ii,@function
_Z19transpose_device_v3PfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s3, v[2:3]
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v2, 6, v3
v_ashrrev_i32_e32 v5, 31, v4
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v1, 6, v5
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19transpose_device_v3PfS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19transpose_device_v3PfS_ii, .Lfunc_end0-_Z19transpose_device_v3PfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19transpose_device_v3PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19transpose_device_v3PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/* Time */
#include <sys/time.h>
#include <sys/resource.h>
static struct timeval tv0;
double getMicroSeconds()
{
double t;
gettimeofday(&tv0, (struct timezone*)0);
t = ((tv0.tv_usec) + (tv0.tv_sec)*1000000);
return (t);
}
void init_seed()
{
int seedi=1;
FILE *fd;
/* Generated random values between 0.00 - 1.00 */
fd = fopen("/dev/urandom", "r");
fread( &seedi, sizeof(int), 1, fd);
fclose (fd);
srand( seedi );
}
void init2Drand(float **buffer, int n)
{
int i, j;
for (i=0; i<n; i++)
for(j=0; j<n; j++)
buffer[i][j] = 500.0*(float(rand())/RAND_MAX)-500.0; /* [-500 500]*/
}
float *getmemory1D( int nx )
{
int i;
float *buffer;
if( (buffer=(float *)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
for( i=0; i<nx; i++ )
buffer[i] = 0.0;
return( buffer );
}
float **getmemory2D(int nx, int ny)
{
int i,j;
float **buffer;
if( (buffer=(float **)malloc(nx*sizeof(float *)))== NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
return( NULL );
}
if( (buffer[0]=(float *)malloc(nx*ny*sizeof(float)))==NULL )
{
fprintf( stderr, "ERROR in memory allocation\n" );
free( buffer );
return( NULL );
}
for( i=1; i<nx; i++ )
{
buffer[i] = buffer[i-1] + ny;
}
for( i=0; i<nx; i++ )
for( j=0; j<ny; j++ )
{
buffer[i][j] = 0.0;
}
return( buffer );
}
/********************************************************************************/
/********************************************************************************/
/*
* Traspose 2D version
*/
void transpose2D(float **in, float **out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j][i] = in[i][j];
}
/*
* Traspose 1D version
*/
void transpose1D(float *in, float *out, int n)
{
int i, j;
for(j=0; j < n; j++)
for(i=0; i < n; i++)
out[j*n+i] = in[i*n+j];
}
/*
* Traspose CUDA version
*/
#define TILE_DIM 16
__global__ void transpose_device_v3(float *in, float *out, int rows, int cols)
{
int i,j;
__shared__ float tile[TILE_DIM][TILE_DIM];
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if(i < rows && j<cols){
tile[i][j] = in[j * cols + i];
__syncthreads();
i = threadIdx.x;
j = threadIdx.y;
out [ i * cols + j ] = tile [i][j];
}
}
int check(float *GPU, float **CPU, int n)
{
int i,j;
for (i=0; i<n; i++)
for(j = 0; j < n; j++)
if(GPU[i * n + j]!=CPU[i][j])
return(1);
return(0);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int main(int argc, char **argv)
{
int n;
float **array2D, **array2D_trans;
float *array2D_trans_GPU;
double t0;
float size_block = 16;
if (argc==2)
n = atoi(argv[1]);
else {
n = 4096;
printf("./exec n (by default n=%i)\n", n);
}
/* Initizalization */
init_seed();
array2D = getmemory2D(n,n);
array2D_trans = getmemory2D(n,n);
init2Drand(array2D, n);
/* Transpose 2D version */
t0 = getMicroSeconds();
transpose2D(array2D, array2D_trans, n);
printf("Transpose version 2D: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
/* CUDA version */
float *darray2D, *darray2D_trans;
hipMalloc((void**)&darray2D, n*n*sizeof(float));
hipMemcpy(darray2D, array2D, n*n*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&darray2D_trans, n*n*sizeof(float));
dim3 dimBlock(size_block,size_block);
int blocks = ceil(n/size_block);
dim3 dimGrid(blocks);
t0 = getMicroSeconds();
transpose_device_v3<<<dimGrid,dimBlock>>>(darray2D, darray2D_trans, n, n);
array2D_trans_GPU = (float *)malloc(n*n * sizeof(float));
hipMemcpy(array2D_trans_GPU, darray2D_trans, n*n*sizeof(float), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("Transpose kernel version: %f MB/s\n", n*n*sizeof(float)/((getMicroSeconds()-t0)/1000000)/1024/1024);
printf("Matriz GPU:\n");
print_matrix(array2D_trans_GPU,n,n);
printf("Matriz CPU\n");
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
printf("%4.1f ",array2D_trans[i][j]);
}
printf("\n");
}
if (check(array2D_trans_GPU, array2D_trans, n*n))
printf("Transpose CPU-GPU differs!!\n");
return(1);
} | .text
.file "transpose.hip"
.globl _Z15getMicroSecondsv # -- Begin function _Z15getMicroSecondsv
.p2align 4, 0x90
.type _Z15getMicroSecondsv,@function
_Z15getMicroSecondsv: # @_Z15getMicroSecondsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15getMicroSecondsv, .Lfunc_end0-_Z15getMicroSecondsv
.cfi_endproc
# -- End function
.globl _Z9init_seedv # -- Begin function _Z9init_seedv
.p2align 4, 0x90
.type _Z9init_seedv,@function
_Z9init_seedv: # @_Z9init_seedv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $1, 12(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movl 12(%rsp), %edi
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp srand # TAILCALL
.Lfunc_end1:
.size _Z9init_seedv, .Lfunc_end1-_Z9init_seedv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10init2DrandPPfi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x407f400000000000 # double 500
.LCPI2_2:
.quad 0xc07f400000000000 # double -500
.text
.globl _Z10init2DrandPPfi
.p2align 4, 0x90
.type _Z10init2DrandPPfi,@function
_Z10init2DrandPPfi: # @_Z10init2DrandPPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtss2sd %xmm0, %xmm0
mulsd %xmm1, %xmm0
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq (%rbx,%r15,8), %rax
movss %xmm0, (%rax,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
cmpq %r14, %r15
jne .LBB2_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_6: # %._crit_edge12
retq
.Lfunc_end2:
.size _Z10init2DrandPPfi, .Lfunc_end2-_Z10init2DrandPPfi
.cfi_endproc
# -- End function
.globl _Z11getmemory1Di # -- Begin function _Z11getmemory1Di
.p2align 4, 0x90
.type _Z11getmemory1Di,@function
_Z11getmemory1Di: # @_Z11getmemory1Di
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movslq %edi, %rdi
shlq $3, %rdi
callq malloc
testq %rax, %rax
je .LBB3_3
# %bb.1: # %.preheader
testl %ebx, %ebx
jle .LBB3_4
# %bb.2: # %.lr.ph.preheader
movl %ebx, %edx
shlq $2, %rdx
movq %rax, %rdi
xorl %esi, %esi
movq %rax, %rbx
callq memset@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
.LBB3_4: # %.loopexit
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11getmemory1Di, .Lfunc_end3-_Z11getmemory1Di
.cfi_endproc
# -- End function
.globl _Z11getmemory2Dii # -- Begin function _Z11getmemory2Dii
.p2align 4, 0x90
.type _Z11getmemory2Dii,@function
_Z11getmemory2Dii: # @_Z11getmemory2Dii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %edi, %rdi
shlq $3, %rdi
callq malloc
testq %rax, %rax
je .LBB4_10
# %bb.1:
movq %rax, %rbx
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, (%rbx)
testq %rax, %rax
je .LBB4_11
# %bb.2: # %.preheader28
movl %r14d, %r15d
cmpl $2, %r14d
jl .LBB4_5
# %bb.3: # %.lr.ph
movslq %ebp, %rax
shlq $2, %rax
movq (%rbx), %rcx
addq %rax, %rcx
movl $1, %edx
.p2align 4, 0x90
.LBB4_4: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rdx,8)
incq %rdx
addq %rax, %rcx
cmpq %rdx, %r15
jne .LBB4_4
.LBB4_5: # %.preheader27
testl %r14d, %r14d
jle .LBB4_13
# %bb.6: # %.preheader.lr.ph
movl %ebp, %r14d
shlq $2, %r14
xorl %r12d, %r12d
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_8 Depth=1
incq %r12
cmpq %r12, %r15
je .LBB4_13
.LBB4_8: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
jle .LBB4_7
# %bb.9: # %.lr.ph31
# in Loop: Header=BB4_8 Depth=1
movq (%rbx,%r12,8), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
jmp .LBB4_7
.LBB4_10:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_12
.LBB4_11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
movq %rbx, %rdi
callq free
.LBB4_12: # %.loopexit
xorl %ebx, %ebx
.LBB4_13: # %.loopexit
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11getmemory2Dii, .Lfunc_end4-_Z11getmemory2Dii
.cfi_endproc
# -- End function
.globl _Z11transpose2DPPfS0_i # -- Begin function _Z11transpose2DPPfS0_i
.p2align 4, 0x90
.type _Z11transpose2DPPfS0_i,@function
_Z11transpose2DPPfS0_i: # @_Z11transpose2DPPfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movq (%rsi,%rcx,8), %rdx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rdi,%r8,8), %r9
movss (%r9,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdx,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %rcx
cmpq %rax, %rcx
jne .LBB5_2
.LBB5_5: # %._crit_edge15
retq
.Lfunc_end5:
.size _Z11transpose2DPPfS0_i, .Lfunc_end5-_Z11transpose2DPPfS0_i
.cfi_endproc
# -- End function
.globl _Z11transpose1DPfS_i # -- Begin function _Z11transpose1DPfS_i
.p2align 4, 0x90
.type _Z11transpose1DPfS_i,@function
_Z11transpose1DPfS_i: # @_Z11transpose1DPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB6_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
movl %r8d, %r10d
leaq (%rsi,%r10,4), %r10
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r10,%rbx,4)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB6_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %r9
addl %edx, %r8d
addq $4, %rdi
cmpq %rax, %r9
jne .LBB6_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB6_6: # %._crit_edge17
retq
.Lfunc_end6:
.size _Z11transpose1DPfS_i, .Lfunc_end6-_Z11transpose1DPfS_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__transpose_device_v3PfS_ii # -- Begin function _Z34__device_stub__transpose_device_v3PfS_ii
.p2align 4, 0x90
.type _Z34__device_stub__transpose_device_v3PfS_ii,@function
_Z34__device_stub__transpose_device_v3PfS_ii: # @_Z34__device_stub__transpose_device_v3PfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19transpose_device_v3PfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z34__device_stub__transpose_device_v3PfS_ii, .Lfunc_end7-_Z34__device_stub__transpose_device_v3PfS_ii
.cfi_endproc
# -- End function
.globl _Z5checkPfPS_i # -- Begin function _Z5checkPfPS_i
.p2align 4, 0x90
.type _Z5checkPfPS_i,@function
_Z5checkPfPS_i: # @_Z5checkPfPS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB8_1
# %bb.3: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
xorl %r8d, %r8d
.LBB8_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
movl %ecx, %r9d
leaq (%rdi,%r9,4), %r9
movq (%rsi,%r8,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_6: # Parent Loop BB8_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r11,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r10,%r11,4), %xmm0
jne .LBB8_7
jp .LBB8_7
# %bb.5: # in Loop: Header=BB8_6 Depth=2
incq %r11
cmpq %r11, %rax
jne .LBB8_6
# %bb.8: # %._crit_edge
# in Loop: Header=BB8_4 Depth=1
incq %r8
addl %edx, %ecx
cmpq %rax, %r8
jne .LBB8_4
.LBB8_1:
xorl %eax, %eax
retq
.LBB8_7:
movl $1, %eax
retq
.Lfunc_end8:
.size _Z5checkPfPS_i, .Lfunc_end8-_Z5checkPfPS_i
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB9_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB9_2
.p2align 4, 0x90
.LBB9_5: # %._crit_edge
# in Loop: Header=BB9_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB9_6
.LBB9_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
testl %ebx, %ebx
jle .LBB9_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB9_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB9_4: # Parent Loop BB9_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB9_4
jmp .LBB9_5
.LBB9_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z12print_matrixPfii, .Lfunc_end9-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI10_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI10_5:
.long 0x3d800000 # float 0.0625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI10_1:
.quad 0x407f400000000000 # double 500
.LCPI10_2:
.quad 0xc07f400000000000 # double -500
.LCPI10_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI10_4:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB10_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB10_3
.LBB10_2:
movl $4096, %ebx # imm = 0x1000
movl $.L.str.5, %edi
movl $4096, %esi # imm = 0x1000
xorl %eax, %eax
callq printf
.LBB10_3:
movl $1, 48(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movq %r14, %rdi
callq fclose
movl 48(%rsp), %edi
callq srand
movl %ebx, %edi
movl %ebx, %esi
callq _Z11getmemory2Dii
movq %rax, %r15
movl %ebx, %edi
movl %ebx, %esi
callq _Z11getmemory2Dii
movq %rax, 24(%rsp) # 8-byte Spill
movl %ebx, %r13d
testl %ebx, %ebx
movq %rbx, %r14
jle .LBB10_8
# %bb.4: # %.preheader.lr.ph.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB10_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_6: # Parent Loop BB10_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI10_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movsd .LCPI10_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtss2sd %xmm0, %xmm0
mulsd %xmm1, %xmm0
movsd .LCPI10_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq (%r15,%r12,8), %rax
movss %xmm0, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB10_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB10_5 Depth=1
incq %r12
cmpq %r13, %r12
jne .LBB10_5
.LBB10_8: # %_Z10init2DrandPPfi.exit
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB10_13
# %bb.9: # %.preheader.lr.ph.i64
xorl %eax, %eax
.p2align 4, 0x90
.LBB10_10: # %.preheader.i65
# =>This Loop Header: Depth=1
# Child Loop BB10_11 Depth 2
movq 24(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rax,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB10_11: # Parent Loop BB10_10 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15,%rdx,8), %rsi
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %r13
jne .LBB10_11
# %bb.12: # %._crit_edge.i70
# in Loop: Header=BB10_10 Depth=1
incq %rax
cmpq %r13, %rax
jne .LBB10_10
.LBB10_13: # %_Z11transpose2DPPfS0_i.exit
movl %r14d, %eax
imull %eax, %eax
movq %rax, 96(%rsp) # 8-byte Spill
leaq (,%rax,4), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI10_3(%rip), %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI10_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
mulss .LCPI10_5(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_15
# %bb.14:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %r14d, 12(%rsp)
movl %r14d, 8(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19transpose_device_v3PfS_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_15:
movq %r12, %rdi
callq malloc
movq 32(%rsp), %rsi
movq %rax, (%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %r12d, %r12d
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 88(%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI10_3(%rip), %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI10_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
testl %r14d, %r14d
jle .LBB10_20
# %bb.16: # %.preheader.lr.ph.i71
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_17: # %.preheader.i72
# =>This Loop Header: Depth=1
# Child Loop BB10_18 Depth 2
movq %r14, %r15
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB10_18: # Parent Loop BB10_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r13
jne .LBB10_18
# %bb.19: # %._crit_edge.i73
# in Loop: Header=BB10_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
movq %r15, %r14
addl %r14d, %r12d
cmpq %r13, %rbp
jne .LBB10_17
.LBB10_20: # %_Z12print_matrixPfii.exit
movl $.Lstr.1, %edi
callq puts@PLT
testl %r14d, %r14d
movq 24(%rsp), %r15 # 8-byte Reload
jle .LBB10_25
# %bb.21: # %.preheader.lr.ph
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_22: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB10_23 Depth 2
movq (%r15,%r12,8), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB10_23: # Parent Loop BB10_22 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB10_23
# %bb.24: # %._crit_edge
# in Loop: Header=BB10_22 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
cmpq %r13, %r12
jne .LBB10_22
.LBB10_25: # %._crit_edge90
testl %r14d, %r14d
movq 96(%rsp), %r8 # 8-byte Reload
je .LBB10_32
# %bb.26: # %.preheader.i79.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.LBB10_27: # %.preheader.i79
# =>This Loop Header: Depth=1
# Child Loop BB10_29 Depth 2
movl %eax, %edx
movq (%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %rdx
movq (%r15,%rcx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB10_29: # Parent Loop BB10_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%rdi,4), %xmm0
jne .LBB10_30
jp .LBB10_30
# %bb.28: # in Loop: Header=BB10_29 Depth=2
incq %rdi
cmpq %rdi, %r8
jne .LBB10_29
# %bb.31: # %._crit_edge.i84
# in Loop: Header=BB10_27 Depth=1
incq %rcx
addl %r8d, %eax
cmpq %r8, %rcx
jne .LBB10_27
jmp .LBB10_32
.LBB10_30: # %_Z5checkPfPS_i.exit
movl $.Lstr.2, %edi
callq puts@PLT
.LBB10_32: # %.critedge
movl $1, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19transpose_device_v3PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL3tv0,@object # @_ZL3tv0
.local _ZL3tv0
.comm _ZL3tv0,16,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/dev/urandom"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR in memory allocation\n"
.size .L.str.2, 28
.type _Z19transpose_device_v3PfS_ii,@object # @_Z19transpose_device_v3PfS_ii
.section .rodata,"a",@progbits
.globl _Z19transpose_device_v3PfS_ii
.p2align 3, 0x0
_Z19transpose_device_v3PfS_ii:
.quad _Z34__device_stub__transpose_device_v3PfS_ii
.size _Z19transpose_device_v3PfS_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%4.1f "
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "./exec n (by default n=%i)\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Transpose version 2D: %f MB/s\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Transpose kernel version: %f MB/s\n"
.size .L.str.7, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19transpose_device_v3PfS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz GPU:"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matriz CPU"
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Transpose CPU-GPU differs!!"
.size .Lstr.2, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__transpose_device_v3PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL3tv0
.addrsig_sym _Z19transpose_device_v3PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19transpose_device_v3PfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ LEA R11, R0, R5, 0x4 ; /* 0x00000005000b7211 */
/* 0x000fe400078e20ff */
/*0100*/ LEA R7, R9.reuse, R4, 0x4 ; /* 0x0000000409077211 */
/* 0x040fe200078e20ff */
/*0110*/ IMAD R4, R9, c[0x0][0x174], R4 ; /* 0x00005d0009047a24 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e020d */
/*0130*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x004fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*0160*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19transpose_device_v3PfS_ii
.globl _Z19transpose_device_v3PfS_ii
.p2align 8
.type _Z19transpose_device_v3PfS_ii,@function
_Z19transpose_device_v3PfS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s3, v[2:3]
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v6, v2, 6, v3
v_ashrrev_i32_e32 v5, 31, v4
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v1, 6, v5
s_waitcnt vmcnt(0)
ds_store_b32 v6, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19transpose_device_v3PfS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19transpose_device_v3PfS_ii, .Lfunc_end0-_Z19transpose_device_v3PfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19transpose_device_v3PfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19transpose_device_v3PfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aaa1a_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15getMicroSecondsv
.type _Z15getMicroSecondsv, @function
_Z15getMicroSecondsv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZL3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZL3tv0(%rip), %rax
addq 8+_ZL3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15getMicroSecondsv, .-_Z15getMicroSecondsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "/dev/urandom"
.text
.globl _Z9init_seedv
.type _Z9init_seedv, @function
_Z9init_seedv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $1, 4(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 4(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl 4(%rsp), %edi
call srand@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9init_seedv, .-_Z9init_seedv
.globl _Z10init2DrandPPfi
.type _Z10init2DrandPPfi, @function
_Z10init2DrandPPfi:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r13
leaq 0(,%rsi,4), %r12
.L11:
movl $0, %ebx
.L12:
call rand@PLT
movq 0(%rbp), %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC3(%rip), %xmm0
subsd .LC3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdx,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
addq $8, %rbp
cmpq %r13, %rbp
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2059:
.size _Z10init2DrandPPfi, .-_Z10init2DrandPPfi
.section .rodata.str1.1
.LC4:
.string "ERROR in memory allocation\n"
.text
.globl _Z11getmemory1Di
.type _Z11getmemory1Di, @function
_Z11getmemory1Di:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movslq %edi, %r12
leaq 0(,%r12,8), %rdi
call malloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L19
leaq (%rax,%r12,4), %rdx
testl %ebp, %ebp
jle .L18
.L22:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
.L18:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z11getmemory1Di, .-_Z11getmemory1Di
.globl _Z11getmemory2Dii
.type _Z11getmemory2Dii, @function
_Z11getmemory2Dii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %r13d
movl %esi, %ebx
movslq %edi, %rsi
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L42
movl %r13d, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 0(%rbp)
testq %rax, %rax
je .L29
cmpl $1, %r13d
jle .L43
movslq %ebx, %rcx
salq $2, %rcx
movq %rbp, %rax
leal -1(%r13), %edx
leaq 0(%rbp,%rdx,8), %rsi
.L32:
movq %rcx, %rdx
addq (%rax), %rdx
movq %rdx, 8(%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L32
.L33:
movq %rbp, %rcx
leaq (%r12,%rbp), %rsi
movslq %ebx, %rdi
salq $2, %rdi
jmp .L34
.L42:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L26
.L29:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r14, %rbp
jmp .L26
.L43:
testl %r13d, %r13d
jg .L33
.L26:
movq %rbp, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq (%rcx), %rax
leaq (%rdi,%rax), %rdx
.L35:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L35
.L37:
addq $8, %rcx
cmpq %rsi, %rcx
je .L26
.L34:
testl %ebx, %ebx
jg .L36
jmp .L37
.cfi_endproc
.LFE2061:
.size _Z11getmemory2Dii, .-_Z11getmemory2Dii
.globl _Z11transpose2DPPfS0_i
.type _Z11transpose2DPPfS0_i, @function
_Z11transpose2DPPfS0_i:
.LFB2062:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L44
movslq %edx, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %ecx
.L46:
movl $0, %eax
.L47:
movq (%rdi,%rax,2), %rdx
movss (%rdx,%rcx), %xmm0
movq (%rsi), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L47
addq $4, %rcx
addq $8, %rsi
cmpq %r8, %rcx
jne .L46
.L44:
ret
.cfi_endproc
.LFE2062:
.size _Z11transpose2DPPfS0_i, .-_Z11transpose2DPPfS0_i
.globl _Z11transpose1DPfS_i
.type _Z11transpose1DPfS_i, @function
_Z11transpose1DPfS_i:
.LFB2063:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L49
movslq %edx, %r10
leaq 0(,%r10,4), %r8
addq %r8, %rsi
negq %r10
salq $2, %r10
movl $0, %r9d
.L51:
leaq (%rsi,%r10), %rax
movq %rdi, %rcx
.L52:
movss (%rcx), %xmm0
movss %xmm0, (%rax)
addq %r8, %rcx
addq $4, %rax
cmpq %rsi, %rax
jne .L52
addl $1, %r9d
addq $4, %rdi
addq %r8, %rsi
cmpl %r9d, %edx
jne .L51
.L49:
ret
.cfi_endproc
.LFE2063:
.size _Z11transpose1DPfS_i, .-_Z11transpose1DPfS_i
.globl _Z5checkPfPS_i
.type _Z5checkPfPS_i, @function
_Z5checkPfPS_i:
.LFB2064:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L59
movq %rsi, %r8
movslq %edx, %rdx
leaq 0(,%rdx,4), %rcx
leaq (%rsi,%rdx,8), %rsi
.L56:
movq (%r8), %rdx
movl $0, %eax
.L58:
movss (%rdi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L60
jne .L60
addq $4, %rax
cmpq %rcx, %rax
jne .L58
addq $8, %r8
addq %rcx, %rdi
cmpq %rsi, %r8
jne .L56
movl $0, %eax
ret
.L59:
movl $0, %eax
ret
.L60:
movl $1, %eax
ret
.cfi_endproc
.LFE2064:
.size _Z5checkPfPS_i, .-_Z5checkPfPS_i
.section .rodata.str1.1
.LC6:
.string "%4.1f "
.LC7:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L64
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC6(%rip), %r12
jmp .L66
.L68:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L67:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L67
.L69:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L64
.L66:
testl %r15d, %r15d
jg .L68
jmp .L69
.L64:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.globl _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
.type _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii, @function
_Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19transpose_device_v3PfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L72
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii, .-_Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
.globl _Z19transpose_device_v3PfS_ii
.type _Z19transpose_device_v3PfS_ii, @function
_Z19transpose_device_v3PfS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z19transpose_device_v3PfS_ii, .-_Z19transpose_device_v3PfS_ii
.section .rodata.str1.1
.LC8:
.string "./exec n (by default n=%i)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "Transpose version 2D: %f MB/s\n"
.align 8
.LC16:
.string "Transpose kernel version: %f MB/s\n"
.section .rodata.str1.1
.LC17:
.string "Matriz GPU:\n"
.LC18:
.string "Matriz CPU\n"
.LC19:
.string "Transpose CPU-GPU differs!!\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L94
movl $4096, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4096, %ebx
.L82:
call _Z9init_seedv
movl %ebx, %esi
movl %ebx, %edi
call _Z11getmemory2Dii
movq %rax, %r13
movl %ebx, %esi
movl %ebx, %edi
call _Z11getmemory2Dii
movq %rax, %r15
movq %rax, (%rsp)
movl %ebx, %esi
movq %r13, %rdi
call _Z10init2DrandPPfi
call _Z15getMicroSecondsv
movsd %xmm0, 16(%rsp)
movl %ebx, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z11transpose2DPPfS0_i
movl %ebx, %eax
imull %ebx, %eax
movl %eax, 12(%rsp)
movslq %eax, %r12
salq $2, %r12
js .L83
pxor %xmm7, %xmm7
cvtsi2sdq %r12, %xmm7
movq %xmm7, %rbp
.L84:
call _Z15getMicroSecondsv
movapd %xmm0, %xmm1
subsd 16(%rsp), %xmm1
divsd .LC9(%rip), %xmm1
movq %rbp, %xmm0
divsd %xmm1, %xmm0
movsd .LC10(%rip), %xmm1
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC12(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC20(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC13(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L85
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC15(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L85:
cvttss2sil %xmm3, %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
call _Z15getMicroSecondsv
movsd %xmm0, 16(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L86:
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
call _Z15getMicroSecondsv
movapd %xmm0, %xmm1
subsd 16(%rsp), %xmm1
divsd .LC9(%rip), %xmm1
movq %rbp, %xmm0
divsd %xmm1, %xmm0
movsd .LC10(%rip), %xmm1
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r14, %rdi
call _Z12print_matrixPfii
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L87
movq (%rsp), %rax
movq %rax, %rbp
movslq %ebx, %rbx
leaq (%rax,%rbx,8), %r15
leaq 0(,%rbx,4), %r12
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
.L88:
movl $0, %ebx
.L89:
movq 0(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L89
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r15, %rbp
jne .L88
.L87:
movl 12(%rsp), %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call _Z5checkPfPS_i
testl %eax, %eax
jne .L96
.L90:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L97
movl $1, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L82
.L83:
movq %r12, %rax
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %rbp
jmp .L84
.L95:
movl %ebx, %ecx
movl %ebx, %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z43__device_stub__Z19transpose_device_v3PfS_iiPfS_ii
jmp .L86
.L96:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L90
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z19transpose_device_v3PfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z19transpose_device_v3PfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3tv0
.comm _ZL3tv0,16,16
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1082081280
.align 8
.LC9:
.long 0
.long 1093567616
.align 8
.LC10:
.long 0
.long 1062207488
.section .rodata.cst4
.align 4
.LC12:
.long 1031798784
.align 4
.LC13:
.long 1258291200
.align 4
.LC15:
.long 1065353216
.align 4
.LC20:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
.globl _Z15getMicroSecondsv # -- Begin function _Z15getMicroSecondsv
.p2align 4, 0x90
.type _Z15getMicroSecondsv,@function
_Z15getMicroSecondsv: # @_Z15getMicroSecondsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15getMicroSecondsv, .Lfunc_end0-_Z15getMicroSecondsv
.cfi_endproc
# -- End function
.globl _Z9init_seedv # -- Begin function _Z9init_seedv
.p2align 4, 0x90
.type _Z9init_seedv,@function
_Z9init_seedv: # @_Z9init_seedv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl $1, 12(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movl 12(%rsp), %edi
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp srand # TAILCALL
.Lfunc_end1:
.size _Z9init_seedv, .Lfunc_end1-_Z9init_seedv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10init2DrandPPfi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x407f400000000000 # double 500
.LCPI2_2:
.quad 0xc07f400000000000 # double -500
.text
.globl _Z10init2DrandPPfi
.p2align 4, 0x90
.type _Z10init2DrandPPfi,@function
_Z10init2DrandPPfi: # @_Z10init2DrandPPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtss2sd %xmm0, %xmm0
mulsd %xmm1, %xmm0
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq (%rbx,%r15,8), %rax
movss %xmm0, (%rax,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
cmpq %r14, %r15
jne .LBB2_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_6: # %._crit_edge12
retq
.Lfunc_end2:
.size _Z10init2DrandPPfi, .Lfunc_end2-_Z10init2DrandPPfi
.cfi_endproc
# -- End function
.globl _Z11getmemory1Di # -- Begin function _Z11getmemory1Di
.p2align 4, 0x90
.type _Z11getmemory1Di,@function
_Z11getmemory1Di: # @_Z11getmemory1Di
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
movslq %edi, %rdi
shlq $3, %rdi
callq malloc
testq %rax, %rax
je .LBB3_3
# %bb.1: # %.preheader
testl %ebx, %ebx
jle .LBB3_4
# %bb.2: # %.lr.ph.preheader
movl %ebx, %edx
shlq $2, %rdx
movq %rax, %rdi
xorl %esi, %esi
movq %rax, %rbx
callq memset@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
.LBB3_4: # %.loopexit
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11getmemory1Di, .Lfunc_end3-_Z11getmemory1Di
.cfi_endproc
# -- End function
.globl _Z11getmemory2Dii # -- Begin function _Z11getmemory2Dii
.p2align 4, 0x90
.type _Z11getmemory2Dii,@function
_Z11getmemory2Dii: # @_Z11getmemory2Dii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %edi, %rdi
shlq $3, %rdi
callq malloc
testq %rax, %rax
je .LBB4_10
# %bb.1:
movq %rax, %rbx
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, (%rbx)
testq %rax, %rax
je .LBB4_11
# %bb.2: # %.preheader28
movl %r14d, %r15d
cmpl $2, %r14d
jl .LBB4_5
# %bb.3: # %.lr.ph
movslq %ebp, %rax
shlq $2, %rax
movq (%rbx), %rcx
addq %rax, %rcx
movl $1, %edx
.p2align 4, 0x90
.LBB4_4: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rdx,8)
incq %rdx
addq %rax, %rcx
cmpq %rdx, %r15
jne .LBB4_4
.LBB4_5: # %.preheader27
testl %r14d, %r14d
jle .LBB4_13
# %bb.6: # %.preheader.lr.ph
movl %ebp, %r14d
shlq $2, %r14
xorl %r12d, %r12d
jmp .LBB4_8
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_8 Depth=1
incq %r12
cmpq %r12, %r15
je .LBB4_13
.LBB4_8: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
jle .LBB4_7
# %bb.9: # %.lr.ph31
# in Loop: Header=BB4_8 Depth=1
movq (%rbx,%r12,8), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
jmp .LBB4_7
.LBB4_10:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB4_12
.LBB4_11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $27, %esi
movl $1, %edx
callq fwrite@PLT
movq %rbx, %rdi
callq free
.LBB4_12: # %.loopexit
xorl %ebx, %ebx
.LBB4_13: # %.loopexit
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11getmemory2Dii, .Lfunc_end4-_Z11getmemory2Dii
.cfi_endproc
# -- End function
.globl _Z11transpose2DPPfS0_i # -- Begin function _Z11transpose2DPPfS0_i
.p2align 4, 0x90
.type _Z11transpose2DPPfS0_i,@function
_Z11transpose2DPPfS0_i: # @_Z11transpose2DPPfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_5
# %bb.1: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movq (%rsi,%rcx,8), %rdx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rdi,%r8,8), %r9
movss (%r9,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdx,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %rcx
cmpq %rax, %rcx
jne .LBB5_2
.LBB5_5: # %._crit_edge15
retq
.Lfunc_end5:
.size _Z11transpose2DPPfS0_i, .Lfunc_end5-_Z11transpose2DPPfS0_i
.cfi_endproc
# -- End function
.globl _Z11transpose1DPfS_i # -- Begin function _Z11transpose1DPfS_i
.p2align 4, 0x90
.type _Z11transpose1DPfS_i,@function
_Z11transpose1DPfS_i: # @_Z11transpose1DPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB6_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
movl %r8d, %r10d
leaq (%rsi,%r10,4), %r10
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r10,%rbx,4)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB6_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %r9
addl %edx, %r8d
addq $4, %rdi
cmpq %rax, %r9
jne .LBB6_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB6_6: # %._crit_edge17
retq
.Lfunc_end6:
.size _Z11transpose1DPfS_i, .Lfunc_end6-_Z11transpose1DPfS_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__transpose_device_v3PfS_ii # -- Begin function _Z34__device_stub__transpose_device_v3PfS_ii
.p2align 4, 0x90
.type _Z34__device_stub__transpose_device_v3PfS_ii,@function
_Z34__device_stub__transpose_device_v3PfS_ii: # @_Z34__device_stub__transpose_device_v3PfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19transpose_device_v3PfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z34__device_stub__transpose_device_v3PfS_ii, .Lfunc_end7-_Z34__device_stub__transpose_device_v3PfS_ii
.cfi_endproc
# -- End function
.globl _Z5checkPfPS_i # -- Begin function _Z5checkPfPS_i
.p2align 4, 0x90
.type _Z5checkPfPS_i,@function
_Z5checkPfPS_i: # @_Z5checkPfPS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB8_1
# %bb.3: # %.preheader.lr.ph
movl %edx, %eax
xorl %ecx, %ecx
xorl %r8d, %r8d
.LBB8_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_6 Depth 2
movl %ecx, %r9d
leaq (%rdi,%r9,4), %r9
movq (%rsi,%r8,8), %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_6: # Parent Loop BB8_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r11,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r10,%r11,4), %xmm0
jne .LBB8_7
jp .LBB8_7
# %bb.5: # in Loop: Header=BB8_6 Depth=2
incq %r11
cmpq %r11, %rax
jne .LBB8_6
# %bb.8: # %._crit_edge
# in Loop: Header=BB8_4 Depth=1
incq %r8
addl %edx, %ecx
cmpq %rax, %r8
jne .LBB8_4
.LBB8_1:
xorl %eax, %eax
retq
.LBB8_7:
movl $1, %eax
retq
.Lfunc_end8:
.size _Z5checkPfPS_i, .Lfunc_end8-_Z5checkPfPS_i
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB9_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB9_2
.p2align 4, 0x90
.LBB9_5: # %._crit_edge
# in Loop: Header=BB9_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB9_6
.LBB9_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
testl %ebx, %ebx
jle .LBB9_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB9_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB9_4: # Parent Loop BB9_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB9_4
jmp .LBB9_5
.LBB9_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z12print_matrixPfii, .Lfunc_end9-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI10_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI10_5:
.long 0x3d800000 # float 0.0625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI10_1:
.quad 0x407f400000000000 # double 500
.LCPI10_2:
.quad 0xc07f400000000000 # double -500
.LCPI10_3:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI10_4:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB10_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB10_3
.LBB10_2:
movl $4096, %ebx # imm = 0x1000
movl $.L.str.5, %edi
movl $4096, %esi # imm = 0x1000
xorl %eax, %eax
callq printf
.LBB10_3:
movl $1, 48(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movq %r14, %rdi
callq fclose
movl 48(%rsp), %edi
callq srand
movl %ebx, %edi
movl %ebx, %esi
callq _Z11getmemory2Dii
movq %rax, %r15
movl %ebx, %edi
movl %ebx, %esi
callq _Z11getmemory2Dii
movq %rax, 24(%rsp) # 8-byte Spill
movl %ebx, %r13d
testl %ebx, %ebx
movq %rbx, %r14
jle .LBB10_8
# %bb.4: # %.preheader.lr.ph.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB10_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_6: # Parent Loop BB10_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI10_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movsd .LCPI10_1(%rip), %xmm1 # xmm1 = mem[0],zero
cvtss2sd %xmm0, %xmm0
mulsd %xmm1, %xmm0
movsd .LCPI10_2(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq (%r15,%r12,8), %rax
movss %xmm0, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB10_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB10_5 Depth=1
incq %r12
cmpq %r13, %r12
jne .LBB10_5
.LBB10_8: # %_Z10init2DrandPPfi.exit
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB10_13
# %bb.9: # %.preheader.lr.ph.i64
xorl %eax, %eax
.p2align 4, 0x90
.LBB10_10: # %.preheader.i65
# =>This Loop Header: Depth=1
# Child Loop BB10_11 Depth 2
movq 24(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rax,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB10_11: # Parent Loop BB10_10 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15,%rdx,8), %rsi
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%rdx,4)
incq %rdx
cmpq %rdx, %r13
jne .LBB10_11
# %bb.12: # %._crit_edge.i70
# in Loop: Header=BB10_10 Depth=1
incq %rax
cmpq %r13, %rax
jne .LBB10_10
.LBB10_13: # %_Z11transpose2DPPfS0_i.exit
movl %r14d, %eax
imull %eax, %eax
movq %rax, 96(%rsp) # 8-byte Spill
leaq (,%rax,4), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI10_3(%rip), %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI10_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
mulss .LCPI10_5(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movabsq $4294967296, %r15 # imm = 0x100000000
orq %rax, %r15
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_15
# %bb.14:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %r14d, 12(%rsp)
movl %r14d, 8(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19transpose_device_v3PfS_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_15:
movq %r12, %rdi
callq malloc
movq 32(%rsp), %rsi
movq %rax, (%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %r12d, %r12d
movl $_ZL3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZL3tv0(%rip), %rax # imm = 0xF4240
addq _ZL3tv0+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 88(%rsp), %xmm1 # 8-byte Folded Reload
divsd .LCPI10_3(%rip), %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd .LCPI10_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
testl %r14d, %r14d
jle .LBB10_20
# %bb.16: # %.preheader.lr.ph.i71
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_17: # %.preheader.i72
# =>This Loop Header: Depth=1
# Child Loop BB10_18 Depth 2
movq %r14, %r15
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB10_18: # Parent Loop BB10_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r13
jne .LBB10_18
# %bb.19: # %._crit_edge.i73
# in Loop: Header=BB10_17 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
movq %r15, %r14
addl %r14d, %r12d
cmpq %r13, %rbp
jne .LBB10_17
.LBB10_20: # %_Z12print_matrixPfii.exit
movl $.Lstr.1, %edi
callq puts@PLT
testl %r14d, %r14d
movq 24(%rsp), %r15 # 8-byte Reload
jle .LBB10_25
# %bb.21: # %.preheader.lr.ph
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB10_22: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB10_23 Depth 2
movq (%r15,%r12,8), %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB10_23: # Parent Loop BB10_22 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB10_23
# %bb.24: # %._crit_edge
# in Loop: Header=BB10_22 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
cmpq %r13, %r12
jne .LBB10_22
.LBB10_25: # %._crit_edge90
testl %r14d, %r14d
movq 96(%rsp), %r8 # 8-byte Reload
je .LBB10_32
# %bb.26: # %.preheader.i79.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.LBB10_27: # %.preheader.i79
# =>This Loop Header: Depth=1
# Child Loop BB10_29 Depth 2
movl %eax, %edx
movq (%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %rdx
movq (%r15,%rcx,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB10_29: # Parent Loop BB10_27 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%rdi,4), %xmm0
jne .LBB10_30
jp .LBB10_30
# %bb.28: # in Loop: Header=BB10_29 Depth=2
incq %rdi
cmpq %rdi, %r8
jne .LBB10_29
# %bb.31: # %._crit_edge.i84
# in Loop: Header=BB10_27 Depth=1
incq %rcx
addl %r8d, %eax
cmpq %r8, %rcx
jne .LBB10_27
jmp .LBB10_32
.LBB10_30: # %_Z5checkPfPS_i.exit
movl $.Lstr.2, %edi
callq puts@PLT
.LBB10_32: # %.critedge
movl $1, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size main, .Lfunc_end10-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19transpose_device_v3PfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZL3tv0,@object # @_ZL3tv0
.local _ZL3tv0
.comm _ZL3tv0,16,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/dev/urandom"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR in memory allocation\n"
.size .L.str.2, 28
.type _Z19transpose_device_v3PfS_ii,@object # @_Z19transpose_device_v3PfS_ii
.section .rodata,"a",@progbits
.globl _Z19transpose_device_v3PfS_ii
.p2align 3, 0x0
_Z19transpose_device_v3PfS_ii:
.quad _Z34__device_stub__transpose_device_v3PfS_ii
.size _Z19transpose_device_v3PfS_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%4.1f "
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "./exec n (by default n=%i)\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Transpose version 2D: %f MB/s\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Transpose kernel version: %f MB/s\n"
.size .L.str.7, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19transpose_device_v3PfS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matriz GPU:"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Matriz CPU"
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Transpose CPU-GPU differs!!"
.size .Lstr.2, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__transpose_device_v3PfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL3tv0
.addrsig_sym _Z19transpose_device_v3PfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // everything is done in the .cu file
int ass; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // everything is done in the .cu file
int ass; | .file "tmpxft_000440f2_00000000-6_monkey_even_odd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl ass
.bss
.align 4
.type ass, @object
.size ass, 4
ass:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // everything is done in the .cu file
int ass; | #include <hip/hip_runtime.h>
// everything is done in the .cu file
int ass; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// everything is done in the .cu file
int ass; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// everything is done in the .cu file
int ass; | .text
.file "monkey_even_odd.hip"
.type ass,@object # @ass
.bss
.globl ass
.p2align 2, 0x0
ass:
.long 0 # 0x0
.size ass, 4
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000440f2_00000000-6_monkey_even_odd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl ass
.bss
.align 4
.type ass, @object
.size ass, 4
ass:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "monkey_even_odd.hip"
.type ass,@object # @ass
.bss
.globl ass
.p2align 2, 0x0
ass:
.long 0 # 0x0
.size ass, 4
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
cudaMalloc( (void**)&dev_f, N * sizeof(float) );
cudaMalloc( (void**)&dev_f_old, N * sizeof(float) );
cudaMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
cudaMemcpy( dev_f, f, N*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dev_f_old, f_old, N*sizeof(float), cudaMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
cudaDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
cudaMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
cudaMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
cudaFree( dev_f );
cudaFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} | code for sm_80
Function : _Z3addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x63, PT ; /* 0x000000630200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9reductionPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fd800000001ff */
/*0070*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff028424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007028625 */
/* 0x000fca00078e0202 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1f0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26270 */
/*0140*/ @!P1 IMAD R2, R3.reuse, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x040fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0180*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0190*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*01d0*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*01e0*/ @P1 BRA 0x130 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0200*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0210*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0220*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
cudaMalloc( (void**)&dev_f, N * sizeof(float) );
cudaMalloc( (void**)&dev_f_old, N * sizeof(float) );
cudaMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
cudaMemcpy( dev_f, f, N*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dev_f_old, f_old, N*sizeof(float), cudaMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
cudaDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
cudaMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
cudaMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
cudaFree( dev_f );
cudaFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} | .file "tmpxft_00014d00_00000000-6_reducao.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_iPfS_i
.type _Z31__device_stub__Z9reductionPfS_iPfS_i, @function
_Z31__device_stub__Z9reductionPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9reductionPfS_iPfS_i, .-_Z31__device_stub__Z9reductionPfS_iPfS_i
.globl _Z9reductionPfS_i
.type _Z9reductionPfS_i, @function
_Z9reductionPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9reductionPfS_i, .-_Z9reductionPfS_i
.globl _Z24__device_stub__Z3addPfS_PfS_
.type _Z24__device_stub__Z3addPfS_PfS_, @function
_Z24__device_stub__Z3addPfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z3addPfS_PfS_, .-_Z24__device_stub__Z3addPfS_PfS_
.globl _Z3addPfS_
.type _Z3addPfS_, @function
_Z3addPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPfS_, .-_Z3addPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "entrada.txt"
.LC4:
.string "\nErro ao abrir aqv\n"
.LC5:
.string "%f"
.LC7:
.string "%lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\ncom double SERIAL - Valor da soma = %f\n"
.align 8
.LC11:
.string "\ncom double SERIAL - Valor da media = %f\n"
.align 8
.LC12:
.string "\ncom float SERIAL - Valor da soma = %f\n"
.align 8
.LC14:
.string "\ncom float SERIAL - Valor da media = %f\n\n\n"
.align 8
.LC15:
.string "\n com double CUDA - Valor da soma = %f\n"
.align 8
.LC16:
.string "\n com double CUDA - Valor da media = %f\n"
.section .rodata.str1.1
.LC17:
.string "\n CUDA - Valor da soma = %f\n"
.LC18:
.string "\n CUDA - Valor da media = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L33
.L20:
movl $8, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r14
movl $8, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r15
movl $4, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r13
movl $0, %ebx
.L21:
leaq 0(%rbp,%rbx), %rdx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $0x3f800000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L21
movl $0, %eax
movl $0x00000000, 12(%rsp)
.L22:
movss 0(%rbp,%rax), %xmm0
addss 0(%r13,%rax), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq $400, %rax
jne .L22
movl $0, %edx
movl $0, %esi
movq %r12, %rdi
call fseek@PLT
movl $0, %ebx
.L23:
leaq (%r14,%rbx), %rdx
leaq .LC7(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq .LC8(%rip), %rax
movq %rax, (%r15,%rbx)
addq $8, %rbx
cmpq $800, %rbx
jne .L23
movl $0, %eax
movq $0x000000000, (%rsp)
.L24:
movsd (%r14,%rax), %xmm0
addsd (%r15,%rax), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rax
cmpq $800, %rax
jne .L24
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
call cudaDeviceSynchronize@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $100, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9reductionPfS_iPfS_i
.L26:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movss (%r12), %xmm0
pxor %xmm1, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rsp)
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
addsd %xmm1, %xmm0
movq %xmm0, %rbx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%rsp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L34:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z24__device_stub__Z3addPfS_PfS_
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z3addPfS_"
.LC20:
.string "_Z9reductionPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC10:
.long 0
.long 1079574528
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
cudaMalloc( (void**)&dev_f, N * sizeof(float) );
cudaMalloc( (void**)&dev_f_old, N * sizeof(float) );
cudaMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
cudaMemcpy( dev_f, f, N*sizeof(float), cudaMemcpyHostToDevice );
cudaMemcpy( dev_f_old, f_old, N*sizeof(float), cudaMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
cudaDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
cudaMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
cudaMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
cudaFree( dev_f );
cudaFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
hipMalloc( (void**)&dev_f, N * sizeof(float) );
hipMalloc( (void**)&dev_f_old, N * sizeof(float) );
hipMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
hipMemcpy( dev_f, f, N*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( dev_f_old, f_old, N*sizeof(float), hipMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
hipDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
hipMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
hipMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
hipFree( dev_f );
hipFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
hipMalloc( (void**)&dev_f, N * sizeof(float) );
hipMalloc( (void**)&dev_f_old, N * sizeof(float) );
hipMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
hipMemcpy( dev_f, f, N*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( dev_f_old, f_old, N*sizeof(float), hipMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
hipDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
hipMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
hipMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
hipFree( dev_f );
hipFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_i
.globl _Z9reductionPfS_i
.p2align 8
.type _Z9reductionPfS_i,@function
_Z9reductionPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[6:7]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_i, .Lfunc_end0-_Z9reductionPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPfS_
.globl _Z3addPfS_
.p2align 8
.type _Z3addPfS_,@function
_Z3addPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x64, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPfS_, .Lfunc_end1-_Z3addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#define imin(a,b) (a<b?a:b)
// const int N = 33 * 1024;
const int N = 100;
const int threadsPerBlock = 256;
const int blocksPerGrid = imin( 32, (N+threadsPerBlock-1) / threadsPerBlock );
__global__ void reduction( float *in, float *out, int n ) {
__shared__ float cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
cache[cacheIndex] = (tid < n)? in[cacheIndex] : 0;
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
out[blockIdx.x] = cache[0];
}
__global__ void add( float *a, float *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < N)
a[tid] = a[tid] + b[tid];
}
int main (void){
FILE *aqv = NULL;
aqv = fopen("entrada.txt", "r");
if(aqv == NULL)
printf("\nErro ao abrir aqv\n");
double *d = (double *) calloc(N, sizeof(double));
double *d_old = (double *) calloc(N, sizeof(double));
float *f = (float *) calloc(N, sizeof(float));
float *f_old = (float *) calloc(N, sizeof(float));
/**
*
* inicia valores
*
*/
int i;
for(i = 0; i < N; i++){
fscanf (aqv, "%f", &f[i]);
f_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
float soma = 0.0;
float temp = 0.0;
for(i = 0; i < N; i++){
temp = f[i] + f_old[i];
soma += temp;
}
/**
*
* Pula o ponteiro de leitura do arquivo
* devolta para o inicio do aqv
*
*/
fseek ( aqv, 0, SEEK_SET);
/**
*
* inicia valores para o tipo DOUBLE
*/
for(i = 0; i < N; i++){
fscanf (aqv, "%lf", &d[i]);
d_old[i] = 1.0;
}
/**
*
* calcula a soma dos vetores
* Efetua a soma da matriz f
*/
double somad = 0.0;
double tempd = 0.0;
for(i = 0; i < N; i++){
tempd = d[i] + d_old[i];
somad += tempd;
}
printf("\ncom double SERIAL - Valor da soma = %f\n", somad);
printf("\ncom double SERIAL - Valor da media = %f\n", somad/N);
printf("\ncom float SERIAL - Valor da soma = %f\n", soma);
printf("\ncom float SERIAL - Valor da media = %f\n\n\n", soma/N);
float *partial_c = NULL;
float *dev_f = NULL, *dev_f_old = NULL, *dev_partial_c = NULL;
partial_c = (float*) calloc( blocksPerGrid, sizeof(float) );
hipMalloc( (void**)&dev_f, N * sizeof(float) );
hipMalloc( (void**)&dev_f_old, N * sizeof(float) );
hipMalloc( (void**)&dev_partial_c, blocksPerGrid * sizeof(float) );
hipMemcpy( dev_f, f, N*sizeof(float), hipMemcpyHostToDevice );
hipMemcpy( dev_f_old, f_old, N*sizeof(float), hipMemcpyHostToDevice );
add<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_f_old );
hipDeviceSynchronize();
reduction<<<blocksPerGrid,threadsPerBlock>>>( dev_f, dev_partial_c, 100 );
hipMemcpy( partial_c, dev_partial_c,
blocksPerGrid*sizeof(float),
hipMemcpyDeviceToHost );
soma = 0.0;
double teste = 0.0;
for ( i=0; i<blocksPerGrid; i++) {
soma += partial_c[i];
teste += partial_c[i];
}
printf("\n com double CUDA - Valor da soma = %f\n", teste);
printf("\n com double CUDA - Valor da media = %f\n", teste/N);
printf("\n CUDA - Valor da soma = %f\n", soma);
printf("\n CUDA - Valor da media = %f\n", soma/N);
hipFree( dev_f );
hipFree( dev_partial_c );
free(f);
free(partial_c);
return 0;
} | .text
.file "reducao.hip"
.globl _Z24__device_stub__reductionPfS_i # -- Begin function _Z24__device_stub__reductionPfS_i
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_i,@function
_Z24__device_stub__reductionPfS_i: # @_Z24__device_stub__reductionPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_i, .Lfunc_end0-_Z24__device_stub__reductionPfS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPfS_ # -- Begin function _Z18__device_stub__addPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_,@function
_Z18__device_stub__addPfS_: # @_Z18__device_stub__addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addPfS_, .Lfunc_end1-_Z18__device_stub__addPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4059000000000000 # double 100
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB2_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_2:
movl $100, %edi
movl $8, %esi
callq calloc
movq %rax, %r14
movl $100, %edi
movl $8, %esi
callq calloc
movq %rax, %r13
movl $100, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $100, %edi
movl $4, %esi
callq calloc
movq %rax, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%rbp), %rdx
movl $.L.str.3, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $1065353216, (%r15,%rbp) # imm = 0x3F800000
addq $4, %rbp
cmpq $400, %rbp # imm = 0x190
jne .LBB2_3
# %bb.4: # %.preheader78.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.preheader78
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r15,%rax,4), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $100, %rax
jne .LBB2_5
# %bb.6:
movss %xmm1, 4(%rsp) # 4-byte Spill
movq %rbx, 144(%rsp) # 8-byte Spill
movq %r12, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movabsq $4607182418800017408, %rbp # imm = 0x3FF0000000000000
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
leaq (%r14,%rbx), %rdx
movl $.L.str.4, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbp, (%r13,%rbx)
addq $8, %rbx
cmpq $800, %rbx # imm = 0x320
jne .LBB2_7
# %bb.8: # %.preheader.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero
addsd (%r13,%rax,8), %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB2_9
# %bb.10:
movabsq $4294967297, %r12 # imm = 0x100000001
movl $.L.str.5, %edi
movb $1, %al
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq $0, 8(%rsp)
movq $0, 32(%rsp)
movq $0, 16(%rsp)
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq 144(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 255(%r12), %r15
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $100, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 108(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9reductionPfS_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 16(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
xorps %xmm2, %xmm2
addss %xmm0, %xmm2
movss %xmm2, 4(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str.9, %edi
movb $1, %al
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_i,@object # @_Z9reductionPfS_i
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_i
.p2align 3, 0x0
_Z9reductionPfS_i:
.quad _Z24__device_stub__reductionPfS_i
.size _Z9reductionPfS_i, 8
.type _Z3addPfS_,@object # @_Z3addPfS_
.globl _Z3addPfS_
.p2align 3, 0x0
_Z3addPfS_:
.quad _Z18__device_stub__addPfS_
.size _Z3addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "entrada.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lf"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\ncom double SERIAL - Valor da soma = %f\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\ncom double SERIAL - Valor da media = %f\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\ncom float SERIAL - Valor da soma = %f\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\ncom float SERIAL - Valor da media = %f\n\n\n"
.size .L.str.8, 43
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\n com double CUDA - Valor da soma = %f\n"
.size .L.str.9, 40
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n com double CUDA - Valor da media = %f\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n CUDA - Valor da soma = %f\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\n CUDA - Valor da media = %f\n"
.size .L.str.12, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPfS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPfS_"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nErro ao abrir aqv"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_i
.addrsig_sym _Z18__device_stub__addPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_i
.addrsig_sym _Z3addPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x63, PT ; /* 0x000000630200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R4, R7 ; /* 0x0000000704077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9reductionPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fd800000001ff */
/*0070*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff028424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007028625 */
/* 0x000fca00078e0202 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1f0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26270 */
/*0140*/ @!P1 IMAD R2, R3.reuse, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x040fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe80000004800 */
/*0160*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0170*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0180*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0190*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*01d0*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*01e0*/ @P1 BRA 0x130 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0200*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0210*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0220*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_i
.globl _Z9reductionPfS_i
.p2align 8
.type _Z9reductionPfS_i,@function
_Z9reductionPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[6:7]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_i
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_i, .Lfunc_end0-_Z9reductionPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addPfS_
.globl _Z3addPfS_
.p2align 8
.type _Z3addPfS_,@function
_Z3addPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x64, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addPfS_, .Lfunc_end1-_Z3addPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014d00_00000000-6_reducao.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_iPfS_i
.type _Z31__device_stub__Z9reductionPfS_iPfS_i, @function
_Z31__device_stub__Z9reductionPfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z9reductionPfS_iPfS_i, .-_Z31__device_stub__Z9reductionPfS_iPfS_i
.globl _Z9reductionPfS_i
.type _Z9reductionPfS_i, @function
_Z9reductionPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9reductionPfS_i, .-_Z9reductionPfS_i
.globl _Z24__device_stub__Z3addPfS_PfS_
.type _Z24__device_stub__Z3addPfS_PfS_, @function
_Z24__device_stub__Z3addPfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z3addPfS_PfS_, .-_Z24__device_stub__Z3addPfS_PfS_
.globl _Z3addPfS_
.type _Z3addPfS_, @function
_Z3addPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPfS_, .-_Z3addPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "r"
.LC3:
.string "entrada.txt"
.LC4:
.string "\nErro ao abrir aqv\n"
.LC5:
.string "%f"
.LC7:
.string "%lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\ncom double SERIAL - Valor da soma = %f\n"
.align 8
.LC11:
.string "\ncom double SERIAL - Valor da media = %f\n"
.align 8
.LC12:
.string "\ncom float SERIAL - Valor da soma = %f\n"
.align 8
.LC14:
.string "\ncom float SERIAL - Valor da media = %f\n\n\n"
.align 8
.LC15:
.string "\n com double CUDA - Valor da soma = %f\n"
.align 8
.LC16:
.string "\n com double CUDA - Valor da media = %f\n"
.section .rodata.str1.1
.LC17:
.string "\n CUDA - Valor da soma = %f\n"
.LC18:
.string "\n CUDA - Valor da media = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L33
.L20:
movl $8, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r14
movl $8, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r15
movl $4, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movl $100, %edi
call calloc@PLT
movq %rax, %r13
movl $0, %ebx
.L21:
leaq 0(%rbp,%rbx), %rdx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $0x3f800000, 0(%r13,%rbx)
addq $4, %rbx
cmpq $400, %rbx
jne .L21
movl $0, %eax
movl $0x00000000, 12(%rsp)
.L22:
movss 0(%rbp,%rax), %xmm0
addss 0(%r13,%rax), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq $400, %rax
jne .L22
movl $0, %edx
movl $0, %esi
movq %r12, %rdi
call fseek@PLT
movl $0, %ebx
.L23:
leaq (%r14,%rbx), %rdx
leaq .LC7(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq .LC8(%rip), %rax
movq %rax, (%r15,%rbx)
addq $8, %rbx
cmpq $800, %rbx
jne .L23
movl $0, %eax
movq $0x000000000, (%rsp)
.L24:
movsd (%r14,%rax), %xmm0
addsd (%r15,%rax), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rax
cmpq $800, %rax
jne .L24
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl $4, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L25:
call cudaDeviceSynchronize@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
movl $100, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9reductionPfS_iPfS_i
.L26:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movss (%r12), %xmm0
pxor %xmm1, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rsp)
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
addsd %xmm1, %xmm0
movq %xmm0, %rbx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss (%rsp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L34:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z24__device_stub__Z3addPfS_PfS_
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z3addPfS_"
.LC20:
.string "_Z9reductionPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC10:
.long 0
.long 1079574528
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reducao.hip"
.globl _Z24__device_stub__reductionPfS_i # -- Begin function _Z24__device_stub__reductionPfS_i
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_i,@function
_Z24__device_stub__reductionPfS_i: # @_Z24__device_stub__reductionPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_i, .Lfunc_end0-_Z24__device_stub__reductionPfS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPfS_ # -- Begin function _Z18__device_stub__addPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_,@function
_Z18__device_stub__addPfS_: # @_Z18__device_stub__addPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__addPfS_, .Lfunc_end1-_Z18__device_stub__addPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4059000000000000 # double 100
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB2_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_2:
movl $100, %edi
movl $8, %esi
callq calloc
movq %rax, %r14
movl $100, %edi
movl $8, %esi
callq calloc
movq %rax, %r13
movl $100, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $100, %edi
movl $4, %esi
callq calloc
movq %rax, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%rbp), %rdx
movl $.L.str.3, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $1065353216, (%r15,%rbp) # imm = 0x3F800000
addq $4, %rbp
cmpq $400, %rbp # imm = 0x190
jne .LBB2_3
# %bb.4: # %.preheader78.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.preheader78
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r15,%rax,4), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $100, %rax
jne .LBB2_5
# %bb.6:
movss %xmm1, 4(%rsp) # 4-byte Spill
movq %rbx, 144(%rsp) # 8-byte Spill
movq %r12, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movabsq $4607182418800017408, %rbp # imm = 0x3FF0000000000000
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
leaq (%r14,%rbx), %rdx
movl $.L.str.4, %esi
movq %r12, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbp, (%r13,%rbx)
addq $8, %rbx
cmpq $800, %rbx # imm = 0x320
jne .LBB2_7
# %bb.8: # %.preheader.preheader
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movsd (%r14,%rax,8), %xmm1 # xmm1 = mem[0],zero
addsd (%r13,%rax,8), %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $100, %rax
jne .LBB2_9
# %bb.10:
movabsq $4294967297, %r12 # imm = 0x100000001
movl $.L.str.5, %edi
movb $1, %al
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq $0, 8(%rsp)
movq $0, 32(%rsp)
movq $0, 16(%rsp)
movl $1, %edi
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq 144(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 255(%r12), %r15
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $100, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 108(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9reductionPfS_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 16(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
xorps %xmm2, %xmm2
addss %xmm0, %xmm2
movss %xmm2, 4(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $.L.str.9, %edi
movb $1, %al
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_i,@object # @_Z9reductionPfS_i
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_i
.p2align 3, 0x0
_Z9reductionPfS_i:
.quad _Z24__device_stub__reductionPfS_i
.size _Z9reductionPfS_i, 8
.type _Z3addPfS_,@object # @_Z3addPfS_
.globl _Z3addPfS_
.p2align 3, 0x0
_Z3addPfS_:
.quad _Z18__device_stub__addPfS_
.size _Z3addPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "entrada.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%lf"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\ncom double SERIAL - Valor da soma = %f\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\ncom double SERIAL - Valor da media = %f\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\ncom float SERIAL - Valor da soma = %f\n"
.size .L.str.7, 40
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\ncom float SERIAL - Valor da media = %f\n\n\n"
.size .L.str.8, 43
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\n com double CUDA - Valor da soma = %f\n"
.size .L.str.9, 40
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n com double CUDA - Valor da media = %f\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n CUDA - Valor da soma = %f\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\n CUDA - Valor da media = %f\n"
.size .L.str.12, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9reductionPfS_i"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addPfS_"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nErro ao abrir aqv"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_i
.addrsig_sym _Z18__device_stub__addPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_i
.addrsig_sym _Z3addPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<time.h>
__global__ void threennKernel(int b, int n, int m, int t, const float * __restrict__ xyz1, const float * __restrict__ xyz2, float * __restrict__ dist, int * __restrict__ idx) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
float best1=1e20, best2=1e20, best3=1e20;
int besti1=0, besti2 = 0, besti3 = 0;
for(int u=0;u<m;u++){
float t_dist = 0;
for(int v=0;v<t;v++){
int tmp_idx1 = i*n*t*3 + j*t*3 + v*3;
int tmp_idx2 = i*m*t*3 + u*t*3 + v*3;
float x1 = xyz1[tmp_idx1+0];
float y1 = xyz1[tmp_idx1+1];
float z1 = xyz1[tmp_idx1+2];
float x2 = xyz2[tmp_idx2+0];
float y2 = xyz2[tmp_idx2+1];
float z2 = xyz2[tmp_idx2+2];
t_dist += max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
}
t_dist /= t;
if (t_dist<best1) {
best3=best2;
besti3=besti2;
best2=best1;
besti2=besti1;
best1=t_dist;
besti1=u;
} else if (t_dist<best2) {
best3=best2;
besti3=besti2;
best2=t_dist;
besti2=u;
} else if (t_dist<best3) {
best3=t_dist;
besti3=u;
}
}
int tmp_idx = i*n*3+j*3;
dist[tmp_idx+0]=best1;
idx[tmp_idx+0]=besti1;
dist[tmp_idx+1]=best2;
idx[tmp_idx+1]=besti2;
dist[tmp_idx+2]=best3;
idx[tmp_idx+2]=besti3;
}
}
}
void threennLauncher(int b,int n,int m,int t,const float *xyz1, const float *xyz2, float *dist, int *idx){
//clock_t start,finish;
//double totaltime;
//start=clock();
threennKernel<<<32,512>>>(b,n,m,t,xyz1,xyz2,dist,idx);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threennKernel:%f \n",totaltime);
}
__global__ void threeinterpolateKernel(int b, int n, int m, int t,int c, const float * __restrict__ points, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ out) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
out[tmp_idx1] = points[tmp_idx2]*w1 + points[tmp_idx3]*w2 + points[tmp_idx4]*w3;
}
}
}
}
}
void threeinterpolateLauncher(int b, int n, int m, int t, int c,const float *points, const int *idx, const float *weight, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolateKernel<<<32,512>>>(b,n,m,t,c,points,idx,weight,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolateKernel:%f \n",totaltime);
}
// input: grad_out (b,n,c), idx (b,n,3), weight (b,n,3)
// output: grad_points (b,m,c)
__global__ void threeinterpolategradKernel(int b, int n, int m, int t, int c, const float * __restrict__ grad_out, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ grad_points) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
atomicAdd(&grad_points[tmp_idx2],grad_out[tmp_idx1]*w1);
atomicAdd(&grad_points[tmp_idx3],grad_out[tmp_idx1]*w2);
atomicAdd(&grad_points[tmp_idx4],grad_out[tmp_idx1]*w3);
}
}
}
}
}
void threeinterpolategradLauncher(int b, int n, int m, int t, int c, const float *grad_out, const int *idx, const float *weight, float *grad_points){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolategradKernel<<<32,128>>>(b,n,m,t,c,grad_out,idx,weight,grad_points);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolategradKernel:%f \n",totaltime);
} | .file "tmpxft_0014d959_00000000-6_interpolation_trajectory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
.type _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi, @function
_Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 208(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 216(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13threennKerneliiiiPKfS0_PfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi, .-_Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
.globl _Z13threennKerneliiiiPKfS0_PfPi
.type _Z13threennKerneliiiiPKfS0_PfPi, @function
_Z13threennKerneliiiiPKfS0_PfPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13threennKerneliiiiPKfS0_PfPi, .-_Z13threennKerneliiiiPKfS0_PfPi
.globl _Z15threennLauncheriiiiPKfS0_PfPi
.type _Z15threennLauncheriiiiPKfS0_PfPi, @function
_Z15threennLauncheriiiiPKfS0_PfPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z15threennLauncheriiiiPKfS0_PfPi, .-_Z15threennLauncheriiiiPKfS0_PfPi
.globl _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.type _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, @function
_Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 224(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq 232(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, .-_Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.globl _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.type _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, @function
_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, .-_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.globl _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.type _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, @function
_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, .-_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.globl _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.type _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, @function
_Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf:
.LFB2088:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 224(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq 232(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, .-_Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.globl _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.type _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, @function
_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, .-_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.globl _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.type _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, @function
_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2059:
.size _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, .-_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf"
.align 8
.LC1:
.string "_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf"
.align 8
.LC2:
.string "_Z13threennKerneliiiiPKfS0_PfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13threennKerneliiiiPKfS0_PfPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<time.h>
__global__ void threennKernel(int b, int n, int m, int t, const float * __restrict__ xyz1, const float * __restrict__ xyz2, float * __restrict__ dist, int * __restrict__ idx) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
float best1=1e20, best2=1e20, best3=1e20;
int besti1=0, besti2 = 0, besti3 = 0;
for(int u=0;u<m;u++){
float t_dist = 0;
for(int v=0;v<t;v++){
int tmp_idx1 = i*n*t*3 + j*t*3 + v*3;
int tmp_idx2 = i*m*t*3 + u*t*3 + v*3;
float x1 = xyz1[tmp_idx1+0];
float y1 = xyz1[tmp_idx1+1];
float z1 = xyz1[tmp_idx1+2];
float x2 = xyz2[tmp_idx2+0];
float y2 = xyz2[tmp_idx2+1];
float z2 = xyz2[tmp_idx2+2];
t_dist += max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
}
t_dist /= t;
if (t_dist<best1) {
best3=best2;
besti3=besti2;
best2=best1;
besti2=besti1;
best1=t_dist;
besti1=u;
} else if (t_dist<best2) {
best3=best2;
besti3=besti2;
best2=t_dist;
besti2=u;
} else if (t_dist<best3) {
best3=t_dist;
besti3=u;
}
}
int tmp_idx = i*n*3+j*3;
dist[tmp_idx+0]=best1;
idx[tmp_idx+0]=besti1;
dist[tmp_idx+1]=best2;
idx[tmp_idx+1]=besti2;
dist[tmp_idx+2]=best3;
idx[tmp_idx+2]=besti3;
}
}
}
void threennLauncher(int b,int n,int m,int t,const float *xyz1, const float *xyz2, float *dist, int *idx){
//clock_t start,finish;
//double totaltime;
//start=clock();
threennKernel<<<32,512>>>(b,n,m,t,xyz1,xyz2,dist,idx);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threennKernel:%f \n",totaltime);
}
__global__ void threeinterpolateKernel(int b, int n, int m, int t,int c, const float * __restrict__ points, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ out) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
out[tmp_idx1] = points[tmp_idx2]*w1 + points[tmp_idx3]*w2 + points[tmp_idx4]*w3;
}
}
}
}
}
void threeinterpolateLauncher(int b, int n, int m, int t, int c,const float *points, const int *idx, const float *weight, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolateKernel<<<32,512>>>(b,n,m,t,c,points,idx,weight,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolateKernel:%f \n",totaltime);
}
// input: grad_out (b,n,c), idx (b,n,3), weight (b,n,3)
// output: grad_points (b,m,c)
__global__ void threeinterpolategradKernel(int b, int n, int m, int t, int c, const float * __restrict__ grad_out, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ grad_points) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
atomicAdd(&grad_points[tmp_idx2],grad_out[tmp_idx1]*w1);
atomicAdd(&grad_points[tmp_idx3],grad_out[tmp_idx1]*w2);
atomicAdd(&grad_points[tmp_idx4],grad_out[tmp_idx1]*w3);
}
}
}
}
}
void threeinterpolategradLauncher(int b, int n, int m, int t, int c, const float *grad_out, const int *idx, const float *weight, float *grad_points){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolategradKernel<<<32,128>>>(b,n,m,t,c,grad_out,idx,weight,grad_points);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolategradKernel:%f \n",totaltime);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void threennKernel(int b, int n, int m, int t, const float * __restrict__ xyz1, const float * __restrict__ xyz2, float * __restrict__ dist, int * __restrict__ idx) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
float best1=1e20, best2=1e20, best3=1e20;
int besti1=0, besti2 = 0, besti3 = 0;
for(int u=0;u<m;u++){
float t_dist = 0;
for(int v=0;v<t;v++){
int tmp_idx1 = i*n*t*3 + j*t*3 + v*3;
int tmp_idx2 = i*m*t*3 + u*t*3 + v*3;
float x1 = xyz1[tmp_idx1+0];
float y1 = xyz1[tmp_idx1+1];
float z1 = xyz1[tmp_idx1+2];
float x2 = xyz2[tmp_idx2+0];
float y2 = xyz2[tmp_idx2+1];
float z2 = xyz2[tmp_idx2+2];
t_dist += max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
}
t_dist /= t;
if (t_dist<best1) {
best3=best2;
besti3=besti2;
best2=best1;
besti2=besti1;
best1=t_dist;
besti1=u;
} else if (t_dist<best2) {
best3=best2;
besti3=besti2;
best2=t_dist;
besti2=u;
} else if (t_dist<best3) {
best3=t_dist;
besti3=u;
}
}
int tmp_idx = i*n*3+j*3;
dist[tmp_idx+0]=best1;
idx[tmp_idx+0]=besti1;
dist[tmp_idx+1]=best2;
idx[tmp_idx+1]=besti2;
dist[tmp_idx+2]=best3;
idx[tmp_idx+2]=besti3;
}
}
}
void threennLauncher(int b,int n,int m,int t,const float *xyz1, const float *xyz2, float *dist, int *idx){
//clock_t start,finish;
//double totaltime;
//start=clock();
threennKernel<<<32,512>>>(b,n,m,t,xyz1,xyz2,dist,idx);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threennKernel:%f \n",totaltime);
}
__global__ void threeinterpolateKernel(int b, int n, int m, int t,int c, const float * __restrict__ points, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ out) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
out[tmp_idx1] = points[tmp_idx2]*w1 + points[tmp_idx3]*w2 + points[tmp_idx4]*w3;
}
}
}
}
}
void threeinterpolateLauncher(int b, int n, int m, int t, int c,const float *points, const int *idx, const float *weight, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolateKernel<<<32,512>>>(b,n,m,t,c,points,idx,weight,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolateKernel:%f \n",totaltime);
}
// input: grad_out (b,n,c), idx (b,n,3), weight (b,n,3)
// output: grad_points (b,m,c)
__global__ void threeinterpolategradKernel(int b, int n, int m, int t, int c, const float * __restrict__ grad_out, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ grad_points) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
atomicAdd(&grad_points[tmp_idx2],grad_out[tmp_idx1]*w1);
atomicAdd(&grad_points[tmp_idx3],grad_out[tmp_idx1]*w2);
atomicAdd(&grad_points[tmp_idx4],grad_out[tmp_idx1]*w3);
}
}
}
}
}
void threeinterpolategradLauncher(int b, int n, int m, int t, int c, const float *grad_out, const int *idx, const float *weight, float *grad_points){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolategradKernel<<<32,128>>>(b,n,m,t,c,grad_out,idx,weight,grad_points);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolategradKernel:%f \n",totaltime);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void threennKernel(int b, int n, int m, int t, const float * __restrict__ xyz1, const float * __restrict__ xyz2, float * __restrict__ dist, int * __restrict__ idx) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
float best1=1e20, best2=1e20, best3=1e20;
int besti1=0, besti2 = 0, besti3 = 0;
for(int u=0;u<m;u++){
float t_dist = 0;
for(int v=0;v<t;v++){
int tmp_idx1 = i*n*t*3 + j*t*3 + v*3;
int tmp_idx2 = i*m*t*3 + u*t*3 + v*3;
float x1 = xyz1[tmp_idx1+0];
float y1 = xyz1[tmp_idx1+1];
float z1 = xyz1[tmp_idx1+2];
float x2 = xyz2[tmp_idx2+0];
float y2 = xyz2[tmp_idx2+1];
float z2 = xyz2[tmp_idx2+2];
t_dist += max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
}
t_dist /= t;
if (t_dist<best1) {
best3=best2;
besti3=besti2;
best2=best1;
besti2=besti1;
best1=t_dist;
besti1=u;
} else if (t_dist<best2) {
best3=best2;
besti3=besti2;
best2=t_dist;
besti2=u;
} else if (t_dist<best3) {
best3=t_dist;
besti3=u;
}
}
int tmp_idx = i*n*3+j*3;
dist[tmp_idx+0]=best1;
idx[tmp_idx+0]=besti1;
dist[tmp_idx+1]=best2;
idx[tmp_idx+1]=besti2;
dist[tmp_idx+2]=best3;
idx[tmp_idx+2]=besti3;
}
}
}
void threennLauncher(int b,int n,int m,int t,const float *xyz1, const float *xyz2, float *dist, int *idx){
//clock_t start,finish;
//double totaltime;
//start=clock();
threennKernel<<<32,512>>>(b,n,m,t,xyz1,xyz2,dist,idx);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threennKernel:%f \n",totaltime);
}
__global__ void threeinterpolateKernel(int b, int n, int m, int t,int c, const float * __restrict__ points, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ out) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
out[tmp_idx1] = points[tmp_idx2]*w1 + points[tmp_idx3]*w2 + points[tmp_idx4]*w3;
}
}
}
}
}
void threeinterpolateLauncher(int b, int n, int m, int t, int c,const float *points, const int *idx, const float *weight, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolateKernel<<<32,512>>>(b,n,m,t,c,points,idx,weight,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolateKernel:%f \n",totaltime);
}
// input: grad_out (b,n,c), idx (b,n,3), weight (b,n,3)
// output: grad_points (b,m,c)
__global__ void threeinterpolategradKernel(int b, int n, int m, int t, int c, const float * __restrict__ grad_out, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ grad_points) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
atomicAdd(&grad_points[tmp_idx2],grad_out[tmp_idx1]*w1);
atomicAdd(&grad_points[tmp_idx3],grad_out[tmp_idx1]*w2);
atomicAdd(&grad_points[tmp_idx4],grad_out[tmp_idx1]*w3);
}
}
}
}
}
void threeinterpolategradLauncher(int b, int n, int m, int t, int c, const float *grad_out, const int *idx, const float *weight, float *grad_points){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolategradKernel<<<32,128>>>(b,n,m,t,c,grad_out,idx,weight,grad_points);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolategradKernel:%f \n",totaltime);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13threennKerneliiiiPKfS0_PfPi
.globl _Z13threennKerneliiiiPKfS0_PfPi
.p2align 8
.type _Z13threennKerneliiiiPKfS0_PfPi,@function
_Z13threennKerneliiiiPKfS0_PfPi:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_19
s_clause 0x3
s_load_b64 s[12:13], s[0:1], 0x4
s_load_b32 s14, s[0:1], 0xc
s_load_b32 s20, s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_mul_i32 s21, s14, 3
s_cmp_gt_i32 s13, 0
s_mul_i32 s18, s20, s14
s_mul_i32 s19, s15, s14
s_cselect_b32 s22, -1, 0
s_cmp_gt_i32 s14, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v4, s21, v1
v_cmp_gt_i32_e64 s2, s12, v0
v_cvt_f32_i32_e32 v3, s14
s_mul_i32 s24, s18, s12
s_cselect_b32 s23, -1, 0
s_add_u32 s16, s0, 48
s_mul_i32 s0, s19, s13
s_mul_i32 s25, s18, s13
s_addc_u32 s17, s1, 0
s_mul_i32 s1, s24, 3
s_mul_i32 s24, s0, 3
s_mul_i32 s25, s25, 3
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s26
v_add_nc_u32_e32 v4, s1, v4
s_add_i32 s15, s20, s15
s_add_i32 s24, s24, s25
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_19
.LBB0_3:
s_and_saveexec_b32 s26, s2
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[16:17], 0xc
v_mov_b32_e32 v5, v4
v_mov_b32_e32 v6, v0
s_mul_i32 s28, s15, s12
s_mov_b32 s30, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s27, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s29, s21, s27
s_branch .LBB0_6
.LBB0_5:
v_add_nc_u32_e32 v7, s28, v6
v_add_nc_u32_e32 v6, s27, v6
v_add_nc_u32_e32 v5, s29, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 1, v7
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v9, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v17, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v19, vcc_lo, v7, 8
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s8, v17
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v18, vcc_lo
global_store_b32 v[9:10], v1, off
global_store_b32 v[11:12], v15, off
v_add_co_u32 v9, vcc_lo, s10, v17
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v18, vcc_lo
global_store_b32 v[7:8], v16, off
v_add_co_u32 v7, vcc_lo, s8, v19
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v20, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s12, v6
v_add_co_u32 v11, s0, s10, v19
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v12, s0, s11, v20, s0
s_or_b32 s30, vcc_lo, s30
global_store_b32 v[9:10], v2, off
global_store_b32 v[7:8], v14, off
global_store_b32 v[11:12], v13, off
s_and_not1_b32 exec_lo, exec_lo, s30
s_cbranch_execz .LBB0_2
.LBB0_6:
v_dual_mov_b32 v1, 0x60ad78ec :: v_dual_mov_b32 v16, 0x60ad78ec
v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, 0x60ad78ec
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v13, 0
s_and_not1_b32 vcc_lo, exec_lo, s22
s_mov_b32 s31, 0
s_cbranch_vccnz .LBB0_5
v_dual_mov_b32 v7, 0x60ad78ec :: v_dual_mov_b32 v8, 0
v_dual_mov_b32 v9, 0x60ad78ec :: v_dual_mov_b32 v10, 0
v_dual_mov_b32 v11, 0x60ad78ec :: v_dual_mov_b32 v12, 0
s_mov_b32 s33, s24
.LBB0_8:
v_mov_b32_e32 v13, 0
s_and_not1_b32 vcc_lo, exec_lo, s23
s_cbranch_vccnz .LBB0_11
v_mov_b32_e32 v1, v5
s_mov_b32 s18, s33
s_mov_b32 s34, s14
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[36:37], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_u32 s36, s6, s36
v_lshlrev_b64 v[14:15], 2, v[1:2]
s_addc_u32 s37, s7, s37
s_add_i32 s34, s34, -1
s_add_i32 s18, s18, 3
s_cmp_eq_u32 s34, 0
v_add_nc_u32_e32 v1, 3, v1
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b96 v[14:16], v[14:15], off
s_clause 0x1
s_load_b64 s[38:39], s[36:37], 0x0
s_load_b32 s0, s[36:37], 0x8
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_sub_f32 v2, s39, v15 :: v_dual_sub_f32 v15, s0, v16
v_sub_f32_e32 v14, s38, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_fmac_f32_e32 v2, v14, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v15, v15
v_mul_f32_e32 v14, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v14, vcc_lo
v_sqrt_f32_e32 v14, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v15, -1, v14
v_add_nc_u32_e32 v16, 1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, -v15, v14, v2
v_fma_f32 v18, -v16, v14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v17
v_cndmask_b32_e64 v14, v14, v15, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v18
v_cndmask_b32_e64 v14, v14, v16, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, 0x37800000, v14
v_cndmask_b32_e32 v14, v14, v15, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v14, v2, vcc_lo
v_max_f32_e32 v2, 0x1e3ce508, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v13, v13, v2
s_cbranch_scc0 .LBB0_10
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v3, v3, v13
v_div_scale_f32 v15, vcc_lo, v13, v3, v13
s_mov_b32 s0, exec_lo
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v14, v2
v_mul_f32_e32 v14, v15, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v1, v14, v15
v_fmac_f32_e32 v14, v16, v2
v_mov_b32_e32 v16, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v1, -v1, v14, v15
v_mov_b32_e32 v15, s31
v_div_fmas_f32 v1, v1, v2, v14
v_mov_b32_e32 v2, v8
v_mov_b32_e32 v14, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v1, v3, v13
v_mov_b32_e32 v13, v10
v_cmpx_nlt_f32_e32 v1, v7
s_cbranch_execz .LBB0_17
v_mov_b32_e32 v2, s31
s_mov_b32 s18, exec_lo
v_cmpx_nlt_f32_e32 v1, v9
s_cbranch_execz .LBB0_16
s_mov_b32 s19, exec_lo
v_cmpx_lt_f32_e32 v1, v11
v_dual_mov_b32 v12, s31 :: v_dual_mov_b32 v11, v1
s_or_b32 exec_lo, exec_lo, s19
v_dual_mov_b32 v1, v9 :: v_dual_mov_b32 v2, v10
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v13, v10 :: v_dual_mov_b32 v14, v9
v_dual_mov_b32 v15, v8 :: v_dual_mov_b32 v16, v1
v_mov_b32_e32 v1, v7
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s31, s31, 1
s_add_i32 s33, s33, s21
s_cmp_eq_u32 s31, s13
s_cbranch_scc1 .LBB0_5
v_dual_mov_b32 v7, v1 :: v_dual_mov_b32 v8, v15
v_dual_mov_b32 v9, v16 :: v_dual_mov_b32 v10, v2
v_dual_mov_b32 v11, v14 :: v_dual_mov_b32 v12, v13
s_branch .LBB0_8
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13threennKerneliiiiPKfS0_PfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 40
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13threennKerneliiiiPKfS0_PfPi, .Lfunc_end0-_Z13threennKerneliiiiPKfS0_PfPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.globl _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.p2align 8
.type _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf,@function
_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_12
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x4
s_load_b32 s12, s[0:1], 0x38
s_load_b256 s[4:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
s_mul_i32 s20, s19, s18
s_cmp_gt_i32 s18, 0
v_cmp_gt_i32_e64 s2, s16, v0
s_cselect_b32 s13, -1, 0
s_cmp_gt_i32 s19, 0
s_mul_i32 s22, s20, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v17, s20, v1
s_cselect_b32 s14, -1, 0
s_add_u32 s0, s0, 56
s_addc_u32 s1, s1, 0
s_mul_i32 s21, s15, s17
s_mul_i32 s17, s12, s17
s_mul_i32 s22, s22, s16
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s23
v_add_nc_u32_e32 v17, s22, v17
s_add_i32 s15, s12, s15
s_add_i32 s21, s21, s17
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_12
.LBB1_3:
s_and_saveexec_b32 s23, s2
s_cbranch_execz .LBB1_2
s_load_b32 s24, s[0:1], 0xc
v_dual_mov_b32 v18, v17 :: v_dual_mov_b32 v19, v0
s_mul_i32 s25, s15, s16
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s24, s24, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s26, s20, s24
s_branch .LBB1_6
.LBB1_5:
v_add_nc_u32_e32 v19, s24, v19
v_add_nc_u32_e32 v18, s26, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s16, v19
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB1_2
.LBB1_6:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_5
v_add_nc_u32_e32 v1, s25, v19
s_mov_b32 s28, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v9, vcc_lo, v1, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v11, vcc_lo, v1, 8
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
s_clause 0x2
global_load_b32 v13, v[5:6], off
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[3:4], off
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v12, vcc_lo
s_clause 0x2
global_load_b32 v20, v[1:2], off
global_load_b32 v21, v[3:4], off
global_load_b32 v22, v[5:6], off
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v1, s21, v13
s_waitcnt vmcnt(4)
v_dual_mov_b32 v7, v18 :: v_dual_add_nc_u32 v2, s21, v7
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v4, s21, v8
v_mul_lo_u32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, s20, v2
v_mul_lo_u32 v5, s20, v4
s_branch .LBB1_9
.LBB1_8:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, s19, v1
v_add_nc_u32_e32 v3, s19, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s19, v5
v_add_nc_u32_e32 v7, s19, v7
s_add_i32 s28, s28, 1
s_cmp_eq_u32 s28, s18
s_cbranch_scc1 .LBB1_5
.LBB1_9:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB1_8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_mov_b32 s29, s19
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_lshlrev_b64 v[15:16], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v15, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
.p2align 6
.LBB1_11:
global_load_b32 v2, v[11:12], off
global_load_b32 v4, v[13:14], off
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
s_add_i32 s29, s29, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s29, 0
s_waitcnt vmcnt(2)
v_mul_f32_e32 v2, v21, v2
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v2, v20, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v22, v6
global_store_b32 v[15:16], v2, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
s_cbranch_scc0 .LBB1_11
s_branch .LBB1_8
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, .Lfunc_end1-_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.globl _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.p2align 8
.type _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf,@function
_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB2_18
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x4
s_load_b256 s[4:11], s[0:1], 0x18
s_load_b32 s12, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s18, 0
v_cmp_gt_i32_e64 s2, s16, v0
s_cselect_b32 s13, -1, 0
s_cmp_gt_i32 s19, 0
s_cselect_b32 s14, -1, 0
s_add_u32 s0, s0, 56
s_addc_u32 s1, s1, 0
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s20
s_add_i32 s15, s12, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB2_18
.LBB2_3:
s_and_saveexec_b32 s20, s2
s_cbranch_execz .LBB2_2
s_load_b32 s23, s[0:1], 0xc
v_mov_b32_e32 v5, v0
s_mul_i32 s21, s15, s16
s_mul_i32 s22, s15, s17
s_mov_b32 s24, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s23, s23, 0xffff
s_branch .LBB2_6
.LBB2_5:
v_add_nc_u32_e32 v5, s23, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s16, v5
s_or_b32 s24, vcc_lo, s24
s_and_not1_b32 exec_lo, exec_lo, s24
s_cbranch_execz .LBB2_2
.LBB2_6:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB2_5
v_add_nc_u32_e32 v10, s21, v5
s_mov_b32 s25, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v10, 1, v10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v11, vcc_lo, v1, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v13, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v12, vcc_lo
s_waitcnt vmcnt(2)
v_add_co_u32 v6, vcc_lo, s6, v13
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v14, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v2, vcc_lo
s_clause 0x2
global_load_b32 v15, v[3:4], off
global_load_b32 v16, v[6:7], off
global_load_b32 v17, v[8:9], off
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v13
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v14, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v12, vcc_lo
s_clause 0x2
global_load_b32 v6, v[1:2], off
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[8:9], off
v_mul_lo_u32 v9, v10, s18
s_waitcnt vmcnt(5)
v_add_nc_u32_e32 v3, s22, v15
s_waitcnt vmcnt(4)
v_add_nc_u32_e32 v2, s22, v16
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v1, s22, v17
v_mul_lo_u32 v12, v3, s18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v11, v2, s18
v_mul_lo_u32 v10, v1, s18
s_branch .LBB2_9
.LBB2_8:
s_add_i32 s25, s25, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s25, s18
s_cbranch_scc1 .LBB2_5
.LBB2_9:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB2_8
v_add_nc_u32_e32 v1, s25, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, s25, v10
v_add_nc_u32_e32 v3, s25, v11
v_add_nc_u32_e32 v4, s25, v12
s_mov_b32 s26, 0
v_mul_lo_u32 v13, v1, s19
v_mul_lo_u32 v14, v2, s19
v_mul_lo_u32 v15, v3, s19
v_mul_lo_u32 v16, v4, s19
.LBB2_11:
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v1, s26, v13
v_add_nc_u32_e32 v3, s26, v14
s_mov_b32 s27, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v4, vcc_lo
global_load_b32 v17, v[17:18], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v18, v6, v17
.LBB2_12:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v4, v18
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s27, vcc_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB2_12
s_or_b32 exec_lo, exec_lo, s27
v_dual_mul_f32 v18, v7, v17 :: v_dual_add_nc_u32 v1, s26, v15
s_mov_b32 s27, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB2_14:
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v4, v18
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s27, vcc_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB2_14
s_or_b32 exec_lo, exec_lo, s27
v_add_nc_u32_e32 v1, s26, v16
v_mul_f32_e32 v17, v8, v17
s_mov_b32 s27, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b32 v4, v[1:2], off
.LBB2_16:
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v4, v17
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s27, vcc_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execnz .LBB2_16
s_or_b32 exec_lo, exec_lo, s27
s_add_i32 s26, s26, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s26, s19
s_cbranch_scc0 .LBB2_11
s_branch .LBB2_8
.LBB2_18:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, .Lfunc_end2-_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13threennKerneliiiiPKfS0_PfPi
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z13threennKerneliiiiPKfS0_PfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void threennKernel(int b, int n, int m, int t, const float * __restrict__ xyz1, const float * __restrict__ xyz2, float * __restrict__ dist, int * __restrict__ idx) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
float best1=1e20, best2=1e20, best3=1e20;
int besti1=0, besti2 = 0, besti3 = 0;
for(int u=0;u<m;u++){
float t_dist = 0;
for(int v=0;v<t;v++){
int tmp_idx1 = i*n*t*3 + j*t*3 + v*3;
int tmp_idx2 = i*m*t*3 + u*t*3 + v*3;
float x1 = xyz1[tmp_idx1+0];
float y1 = xyz1[tmp_idx1+1];
float z1 = xyz1[tmp_idx1+2];
float x2 = xyz2[tmp_idx2+0];
float y2 = xyz2[tmp_idx2+1];
float z2 = xyz2[tmp_idx2+2];
t_dist += max(sqrtf((x2-x1)*(x2-x1)+(y2-y1)*(y2-y1)+(z2-z1)*(z2-z1)),1e-20f);
}
t_dist /= t;
if (t_dist<best1) {
best3=best2;
besti3=besti2;
best2=best1;
besti2=besti1;
best1=t_dist;
besti1=u;
} else if (t_dist<best2) {
best3=best2;
besti3=besti2;
best2=t_dist;
besti2=u;
} else if (t_dist<best3) {
best3=t_dist;
besti3=u;
}
}
int tmp_idx = i*n*3+j*3;
dist[tmp_idx+0]=best1;
idx[tmp_idx+0]=besti1;
dist[tmp_idx+1]=best2;
idx[tmp_idx+1]=besti2;
dist[tmp_idx+2]=best3;
idx[tmp_idx+2]=besti3;
}
}
}
void threennLauncher(int b,int n,int m,int t,const float *xyz1, const float *xyz2, float *dist, int *idx){
//clock_t start,finish;
//double totaltime;
//start=clock();
threennKernel<<<32,512>>>(b,n,m,t,xyz1,xyz2,dist,idx);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threennKernel:%f \n",totaltime);
}
__global__ void threeinterpolateKernel(int b, int n, int m, int t,int c, const float * __restrict__ points, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ out) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
out[tmp_idx1] = points[tmp_idx2]*w1 + points[tmp_idx3]*w2 + points[tmp_idx4]*w3;
}
}
}
}
}
void threeinterpolateLauncher(int b, int n, int m, int t, int c,const float *points, const int *idx, const float *weight, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolateKernel<<<32,512>>>(b,n,m,t,c,points,idx,weight,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolateKernel:%f \n",totaltime);
}
// input: grad_out (b,n,c), idx (b,n,3), weight (b,n,3)
// output: grad_points (b,m,c)
__global__ void threeinterpolategradKernel(int b, int n, int m, int t, int c, const float * __restrict__ grad_out, const int * __restrict__ idx, const float * __restrict__ weight, float * __restrict__ grad_points) {
for(int i=blockIdx.x;i<b;i+=gridDim.x){
for(int j=threadIdx.x;j<n;j+=blockDim.x){
int tmp_idx = i*n*3+j*3;
float w1=weight[tmp_idx+0];
float w2=weight[tmp_idx+1];
float w3=weight[tmp_idx+2];
int i1=idx[tmp_idx+0];
int i2=idx[tmp_idx+1];
int i3=idx[tmp_idx+2];
for(int u=0;u<t;u++){
for(int v=0;v<c;v++){
int tmp_idx1 = i*n*t*c + j*t*c + u*c + v;
int tmp_idx2 = i*m*t*c + i1*t*c + u*c + v;
int tmp_idx3 = i*m*t*c + i2*t*c + u*c + v;
int tmp_idx4 = i*m*t*c + i3*t*c + u*c + v;
atomicAdd(&grad_points[tmp_idx2],grad_out[tmp_idx1]*w1);
atomicAdd(&grad_points[tmp_idx3],grad_out[tmp_idx1]*w2);
atomicAdd(&grad_points[tmp_idx4],grad_out[tmp_idx1]*w3);
}
}
}
}
}
void threeinterpolategradLauncher(int b, int n, int m, int t, int c, const float *grad_out, const int *idx, const float *weight, float *grad_points){
//clock_t start,finish;
//double totaltime;
//start=clock();
threeinterpolategradKernel<<<32,128>>>(b,n,m,t,c,grad_out,idx,weight,grad_points);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("threeinterpolategradKernel:%f \n",totaltime);
} | .text
.file "interpolation_trajectory.hip"
.globl _Z28__device_stub__threennKerneliiiiPKfS0_PfPi # -- Begin function _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.p2align 4, 0x90
.type _Z28__device_stub__threennKerneliiiiPKfS0_PfPi,@function
_Z28__device_stub__threennKerneliiiiPKfS0_PfPi: # @_Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13threennKerneliiiiPKfS0_PfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__threennKerneliiiiPKfS0_PfPi, .Lfunc_end0-_Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.cfi_endproc
# -- End function
.globl _Z15threennLauncheriiiiPKfS0_PfPi # -- Begin function _Z15threennLauncheriiiiPKfS0_PfPi
.p2align 4, 0x90
.type _Z15threennLauncheriiiiPKfS0_PfPi,@function
_Z15threennLauncheriiiiPKfS0_PfPi: # @_Z15threennLauncheriiiiPKfS0_PfPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 12(%rsp)
movl %r12d, 8(%rsp)
movl %r15d, 4(%rsp)
movl %ebp, (%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13threennKerneliiiiPKfS0_PfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15threennLauncheriiiiPKfS0_PfPi, .Lfunc_end1-_Z15threennLauncheriiiiPKfS0_PfPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf # -- Begin function _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf,@function
_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf: # @_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf, .Lfunc_end2-_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf # -- Begin function _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf,@function
_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf: # @_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, .Lfunc_end3-_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf # -- Begin function _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf,@function
_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf: # @_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf, .Lfunc_end4-_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf # -- Begin function _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf,@function
_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf: # @_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 96(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, .Lfunc_end5-_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13threennKerneliiiiPKfS0_PfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13threennKerneliiiiPKfS0_PfPi,@object # @_Z13threennKerneliiiiPKfS0_PfPi
.section .rodata,"a",@progbits
.globl _Z13threennKerneliiiiPKfS0_PfPi
.p2align 3, 0x0
_Z13threennKerneliiiiPKfS0_PfPi:
.quad _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.size _Z13threennKerneliiiiPKfS0_PfPi, 8
.type _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf,@object # @_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.globl _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.p2align 3, 0x0
_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf:
.quad _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.size _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, 8
.type _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf,@object # @_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.globl _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.p2align 3, 0x0
_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf:
.quad _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.size _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13threennKerneliiiiPKfS0_PfPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf"
.size .L__unnamed_3, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.addrsig_sym _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.addrsig_sym _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13threennKerneliiiiPKfS0_PfPi
.addrsig_sym _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.addrsig_sym _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d959_00000000-6_interpolation_trajectory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
.type _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi, @function
_Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 208(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
movq 216(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13threennKerneliiiiPKfS0_PfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi, .-_Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
.globl _Z13threennKerneliiiiPKfS0_PfPi
.type _Z13threennKerneliiiiPKfS0_PfPi, @function
_Z13threennKerneliiiiPKfS0_PfPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13threennKerneliiiiPKfS0_PfPi, .-_Z13threennKerneliiiiPKfS0_PfPi
.globl _Z15threennLauncheriiiiPKfS0_PfPi
.type _Z15threennLauncheriiiiPKfS0_PfPi, @function
_Z15threennLauncheriiiiPKfS0_PfPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z45__device_stub__Z13threennKerneliiiiPKfS0_PfPiiiiiPKfS0_PfPi
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z15threennLauncheriiiiPKfS0_PfPi, .-_Z15threennLauncheriiiiPKfS0_PfPi
.globl _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.type _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, @function
_Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 224(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq 232(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, .-_Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.globl _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.type _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, @function
_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, .-_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.globl _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.type _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, @function
_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z56__device_stub__Z22threeinterpolateKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, .-_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.globl _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.type _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, @function
_Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf:
.LFB2088:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
movq 224(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
movq 232(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf, .-_Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
.globl _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.type _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, @function
_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, .-_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.globl _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.type _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, @function
_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movq %r9, %r15
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movl %r14d, %r8d
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z60__device_stub__Z26threeinterpolategradKerneliiiiiPKfPKiS0_PfiiiiiPKfPKiS0_Pf
addq $32, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2059:
.size _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, .-_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf"
.align 8
.LC1:
.string "_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf"
.align 8
.LC2:
.string "_Z13threennKerneliiiiPKfS0_PfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13threennKerneliiiiPKfS0_PfPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "interpolation_trajectory.hip"
.globl _Z28__device_stub__threennKerneliiiiPKfS0_PfPi # -- Begin function _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.p2align 4, 0x90
.type _Z28__device_stub__threennKerneliiiiPKfS0_PfPi,@function
_Z28__device_stub__threennKerneliiiiPKfS0_PfPi: # @_Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13threennKerneliiiiPKfS0_PfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__threennKerneliiiiPKfS0_PfPi, .Lfunc_end0-_Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.cfi_endproc
# -- End function
.globl _Z15threennLauncheriiiiPKfS0_PfPi # -- Begin function _Z15threennLauncheriiiiPKfS0_PfPi
.p2align 4, 0x90
.type _Z15threennLauncheriiiiPKfS0_PfPi,@function
_Z15threennLauncheriiiiPKfS0_PfPi: # @_Z15threennLauncheriiiiPKfS0_PfPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl %r13d, 12(%rsp)
movl %r12d, 8(%rsp)
movl %r15d, 4(%rsp)
movl %ebp, (%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13threennKerneliiiiPKfS0_PfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15threennLauncheriiiiPKfS0_PfPi, .Lfunc_end1-_Z15threennLauncheriiiiPKfS0_PfPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf # -- Begin function _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf,@function
_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf: # @_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf, .Lfunc_end2-_Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf # -- Begin function _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf,@function
_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf: # @_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf, .Lfunc_end3-_Z24threeinterpolateLauncheriiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf # -- Begin function _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf,@function
_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf: # @_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf, .Lfunc_end4-_Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.globl _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf # -- Begin function _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.p2align 4, 0x90
.type _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf,@function
_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf: # @_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 96(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 256(%rsp), %rax
movq 248(%rsp), %rcx
movq 240(%rsp), %rdx
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rax, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf, .Lfunc_end5-_Z28threeinterpolategradLauncheriiiiiPKfPKiS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13threennKerneliiiiPKfS0_PfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13threennKerneliiiiPKfS0_PfPi,@object # @_Z13threennKerneliiiiPKfS0_PfPi
.section .rodata,"a",@progbits
.globl _Z13threennKerneliiiiPKfS0_PfPi
.p2align 3, 0x0
_Z13threennKerneliiiiPKfS0_PfPi:
.quad _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.size _Z13threennKerneliiiiPKfS0_PfPi, 8
.type _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf,@object # @_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.globl _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.p2align 3, 0x0
_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf:
.quad _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.size _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf, 8
.type _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf,@object # @_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.globl _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.p2align 3, 0x0
_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf:
.quad _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.size _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13threennKerneliiiiPKfS0_PfPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf"
.size .L__unnamed_3, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__threennKerneliiiiPKfS0_PfPi
.addrsig_sym _Z37__device_stub__threeinterpolateKerneliiiiiPKfPKiS0_Pf
.addrsig_sym _Z41__device_stub__threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13threennKerneliiiiPKfS0_PfPi
.addrsig_sym _Z22threeinterpolateKerneliiiiiPKfPKiS0_Pf
.addrsig_sym _Z26threeinterpolategradKerneliiiiiPKfPKiS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* This file is copied from https://github.com/jzbonter/mc-cnn */
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void copy_fill(float *in, float *out, int size, int in_size2, int in_size3, int out_size2, int out_size3)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
int out_x = id % out_size3;
int out_y = id / out_size3;
int in_x = out_x - (out_size3 - in_size3) / 2;
int in_y = out_y - (out_size2 - in_size2) / 2;
int x = min(in_size3 - 1, max(0, in_x));
int y = min(in_size2 - 1, max(0, in_y));
out[id] = in[y * in_size3 + x];
}
} | code for sm_80
Function : _Z9copy_fillPfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IABS R5, c[0x0][0x180] ; /* 0x0000600000057a13 */
/* 0x000fe20000000000 */
/*0070*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe20000000800 */
/*0090*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00a0*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ UIADD3 UR4, UR4, -UR8, URZ ; /* 0x8000000804047290 */
/* 0x000fe4000fffe03f */
/*00c0*/ UIADD3 UR5, UR9, -UR6, URZ ; /* 0x8000000609057290 */
/* 0x000fe4000fffe03f */
/*00d0*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc4000f8f083f */
/*00e0*/ ULEA.HI UR5, UR5, UR5, URZ, 0x1 ; /* 0x0000000505057291 */
/* 0x000fe4000f8f083f */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011404 */
/*0100*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0110*/ UMOV UR7, 0x1 ; /* 0x0000000100077882 */
/* 0x000fe20000000000 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0130*/ UIADD3 UR6, -UR7, UR6, URZ ; /* 0x0000000607067290 */
/* 0x000fe2000fffe13f */
/*0140*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0180*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*01a0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*01b0*/ LOP3.LUT R2, R0, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600000027a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01d0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01f0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0200*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0210*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0220*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0260*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0270*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff03aa12 */
/* 0x000fca00078e33ff */
/*0280*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0290*/ IADD3 R3, R3, -UR5, RZ ; /* 0x8000000503037c10 */
/* 0x000fc6000fffe0ff */
/*02a0*/ IMAD R2, R5, c[0x0][0x180], R0 ; /* 0x0000600005027a24 */
/* 0x000fe200078e0200 */
/*02b0*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe20007800200 */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*02d0*/ IADD3 R2, R2, -UR4, RZ ; /* 0x8000000402027c10 */
/* 0x000fe2000fffe0ff */
/*02e0*/ UIADD3 UR4, -UR7, UR8, URZ ; /* 0x0000000807047290 */
/* 0x000fe2000fffe13f */
/*02f0*/ IMNMX R3, R3, UR6, PT ; /* 0x0000000603037c17 */
/* 0x000fe4000b800200 */
/*0300*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0310*/ IMNMX R2, R2, UR4, PT ; /* 0x0000000402027c17 */
/* 0x000fe2000b800200 */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0330*/ IMAD R2, R3, c[0x0][0x178], R2 ; /* 0x00005e0003027a24 */
/* 0x000fc800078e0202 */
/*0340*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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