system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// VectorAdd.cu
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// VectorAdd.cu
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// VectorAdd.cu
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// VectorAdd.cu
#define N 10 // size of vectors
#define B 1 // blocks in the grid
#define T 10 // threads in a block
__global__ void add (int *a,int *b, int *c) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N) {
c[tid] = a[tid]+b[tid];
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a9806_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
// deallocate memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
// deallocate memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} | .file "tmpxft_0019f7aa_00000000-6_add_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Addition on CPU: %d + %d = %d\n"
.align 8
.LC1:
.string "\n Addition on GPU: %d + %d = %d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $5, (%rsp)
movl $7, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl (%rsp), %edx
movl 4(%rsp), %ecx
leal (%rdx,%rcx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
cudaMemcpy(d_a, &h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b, size, cudaMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
cudaMemcpy(&h_c, d_c, size, cudaMemcpyDeviceToHost);
// deallocate memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include <hip/hip_runtime.h>
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
// deallocate memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include <hip/hip_runtime.h>
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
// deallocate memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // SDSC Summer Institute 2018
// Andreas Goetz (agoetz@sdsc.edu)
// CUDA program to add two integer numbers on the GPU
//
#include <hip/hip_runtime.h>
#include<stdio.h>
//
// CUDA device function that adds two integer numbers
//
__global__ void add(int *a, int *b, int *c){
*c = *a + *b;
}
//
// main program
//
int main(void) {
int h_a, h_b, h_c; // host copies
int *d_a, *d_b, *d_c; // device copies
int size = sizeof(int);
// allocate device memory
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
// setup input data
h_a = 5;
h_b = 7;
// copy input data to device
hipMemcpy(d_a, &h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b, size, hipMemcpyHostToDevice);
// launch kernel
add<<<1,1>>>(d_a, d_b, d_c);
// copy results back to host
hipMemcpy(&h_c, d_c, size, hipMemcpyDeviceToHost);
// deallocate memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// print results
printf("\n Addition on CPU: %d + %d = %d\n", h_a, h_b, h_a + h_b);
printf("\n Addition on GPU: %d + %d = %d\n\n",h_a, h_b, h_c);
return 0;
} | .text
.file "add_gpu.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $5, 4(%rsp)
movl $7, (%rsp)
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl 4(%rsp), %esi
movl (%rsp), %edx
leal (%rdx,%rsi), %ecx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Addition on CPU: %d + %d = %d\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n Addition on GPU: %d + %d = %d\n\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019f7aa_00000000-6_add_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Addition on CPU: %d + %d = %d\n"
.align 8
.LC1:
.string "\n Addition on GPU: %d + %d = %d\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $5, (%rsp)
movl $7, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl (%rsp), %edx
movl 4(%rsp), %ecx
leal (%rdx,%rcx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_gpu.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $5, 4(%rsp)
movl $7, (%rsp)
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl 4(%rsp), %esi
movl (%rsp), %edx
leal (%rdx,%rsi), %ecx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Addition on CPU: %d + %d = %d\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n Addition on GPU: %d + %d = %d\n\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <memory>
#include <fstream>
#include <queue>
class Graph{
public:
Graph(const int verticeNum){
this->verticeNum = verticeNum;
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
}
Graph(std::string fileName){
std::ifstream file;
file.open(fileName);
if(!file){
printf("Unable to open file!\n");
exit(1);
}
file >> verticeNum;
//find vertice number
//skip the second line
int tmp;
file >> tmp;
//init matrix...
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = -1;
}
}
int vA, vB;
while (!file.eof()) {
file >> vA >> vB;
int linkWeight = generateRandomNum(100);
graphMatrix[vA][vB] = linkWeight;
graphMatrix[vB][vA] = linkWeight;
}
file.close();
}
void printGraphMatrix(){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
printf("%d\t", graphMatrix[i][j]);
}
printf("\n");
}
}
void BFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
//printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.empty()){
i = bfsQueue.front();
bfsQueue.pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue.push(j);
}
}
}
}
}
}
void _recursiveBFS(std::queue<int>* bfsQueue, bool visited[]){
while(!bfsQueue->empty()){
int i = bfsQueue->front();
bfsQueue->pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue->push(j);
}
}
_recursiveBFS(bfsQueue, visited);
}
}
void recursiveBFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
if(!visited[i]){
//printf("visit node %d\n", i);
bfsQueue.push(i);
visited[i] = true;
_recursiveBFS(&bfsQueue, visited);
}
}
}
int** graphMatrix;
int verticeNum;
private:
void generateRandomMatrix(int verticeNum){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = generateRandomNum(100);
}
}
}
int generateRandomNum(int max){
return rand() % 100;
}
};
struct Node{
int data;
Node* next;
Node* prev;
Node(int data){
this->data = data;
}
Node(){}
}Node;
struct List{
struct Node* head, *tail;
int listSize;
List(int vNum){
head = (struct Node*)malloc(sizeof(Node) * vNum);
tail = head + 1;
head->next = tail;
tail->prev = head;
listSize = 0;
}
~List(){
delete []head;
}
void push(int data){
struct Node* node = new struct Node(data);
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
int pop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
void cudaPush(int data){
struct Node* node = (struct Node*)malloc(sizeof(struct Node));
node->data = data;
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
__device__
int cudaPop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
int cudaGetSize(){
return listSize;
}
__device__
bool cudaIsEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
int getSize(){
return listSize;
}
bool isEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
void printList(){
struct Node* node = head->next;
while(node != tail){
//printf("value %d\n", node->data);
node = node->next;
}
}
};
__global__
void cudaComputeBFS(bool* visited, int** graphMatrix, List* bfsQueue, int* i){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if(graphMatrix[*i][x] != -1 && !visited[x]){
visited[x] = true;
//printf("inner visit node %d\n", x);
bfsQueue->cudaPush(x);
}
}
void cudaBFS(Graph g){
const int vNum = g.verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
struct List bfsQueue(vNum);
for(int i = 0; i < vNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.isEmpty()){
i = bfsQueue.pop();
//cuda optimization...
const int BLOCK_SIZE = 64;
dim3 dimBlock((vNum + BLOCK_SIZE - 1) / BLOCK_SIZE, 1, 1);
dim3 dimGrid(BLOCK_SIZE, 1, 1);
bool* cudaVisited;
int** cudaGraphMatrix;
List* cudaBfsQueue;
int* cudaI;
int* cudaSize;
int* size;
cudaMalloc(&cudaVisited, sizeof(bool) * vNum);
cudaMalloc(&cudaBfsQueue->head, sizeof(Node) * vNum + 2);
cudaMalloc(&cudaGraphMatrix, sizeof(int *) * vNum);
cudaMalloc(&cudaI, sizeof(int*));
cudaMalloc(&cudaSize, sizeof(int*));
for(int k = 0; k < vNum; k++){
cudaMalloc(&cudaGraphMatrix[k], sizeof(int) * vNum);
}
//copy data to device
cudaMemcpy(cudaVisited, visited, sizeof(bool) * vNum, cudaMemcpyHostToDevice);
int count = 0;
while(!bfsQueue.isEmpty()){
cudaMemcpy(&cudaBfsQueue->head + count++, &bfsQueue.head + count++, sizeof(Node), cudaMemcpyHostToDevice);
}
for(int k = 0; k < vNum; k++){
cudaMemcpy(cudaGraphMatrix, g.graphMatrix, sizeof(int) * vNum, cudaMemcpyHostToDevice);
}
cudaMemcpy(cudaI, &i, sizeof(int), cudaMemcpyHostToDevice);
cudaComputeBFS<<<dimGrid, dimBlock>>>(cudaVisited, cudaGraphMatrix, cudaBfsQueue, cudaI);
//update visited & queue...
cudaMemcpy(visited, cudaVisited, sizeof(bool) * vNum, cudaMemcpyDeviceToHost);
cudaMemcpy(&bfsQueue.head, &cudaBfsQueue->head, sizeof(Node) * vNum, cudaMemcpyDeviceToHost);
cudaFree(cudaVisited);
cudaFree (cudaGraphMatrix);
cudaFree(cudaI);
cudaFree(cudaBfsQueue);
}
}
}
}
int main(){
struct timeval tpstart, tpend;
long timeuse;
Graph graph("./largeG.txt");
gettimeofday( &tpstart, NULL );
//graph.BFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU looped version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//graph.recursiveBFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU recursive version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//cudaBFS(graph);
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("GPU version is finished in time %ld ms\n", timeuse);
return 0;
} | code for sm_80
Function : _Z14cudaComputeBFSPbPPiP4ListS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e280000002500 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0080*/ IMAD.WIDE R4, R2, R5, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fcc00078e0205 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000002404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD R17, R17, c[0x0][0x0], R0 ; /* 0x0000000011117a24 */
/* 0x001fc800078e0200 */
/*00b0*/ IMAD.WIDE R6, R17, 0x4, R4 ; /* 0x0000000411067825 */
/* 0x004fcc00078e0204 */
/*00c0*/ LD.E R6, [R6.64] ; /* 0x0000002406067980 */
/* 0x000ea4000c101900 */
/*00d0*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x004fda0003f05270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, P0, R17, c[0x0][0x160], RZ ; /* 0x0000580011027a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ LEA.HI.X.SX32 R3, R17, c[0x0][0x164], 0x1, P0 ; /* 0x0000590011037a11 */
/* 0x000fca00000f0eff */
/*0110*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000002402007981 */
/* 0x000ea4000c1e1100 */
/*0120*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, 0x18 ; /* 0x00000018ff047424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0180*/ LDC.64 R6, c[0x4][R0] ; /* 0x0100000000067b82 */
/* 0x0000620000000a00 */
/*0190*/ STG.E.U8 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001ea000c101124 */
/*01a0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*01b0*/ MOV R9, 0x220 ; /* 0x0000022000097802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R20, 0x1a0 ; /* 0x000001a000147802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*01e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01f0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0200*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0210*/ CALL.ABS.NOINC R6 ; /* 0x0000000006007343 */
/* 0x002fea0003c00000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0230*/ ST.E [R4.64], R17 ; /* 0x0000001104007985 */
/* 0x0001e2000c101924 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0250*/ LDG.E.64 R6, [R2.64] ; /* 0x0000002402067981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000082402087981 */
/* 0x000ee8000c1e1b00 */
/*0270*/ LD.E.64 R10, [R6.64+0x8] ; /* 0x00000824060a7980 */
/* 0x004ee4000c101b00 */
/*0280*/ ISETP.NE.U32.AND P0, PT, R10, R8, PT ; /* 0x000000080a00720c */
/* 0x008fc80003f05070 */
/*0290*/ ISETP.NE.AND.EX P0, PT, R11, R9, PT, P0 ; /* 0x000000090b00720c */
/* 0x000fda0003f05300 */
/*02a0*/ @P0 LD.E.64 R8, [R8.64+0x10] ; /* 0x0000102408080980 */
/* 0x000ea8000c101b00 */
/*02b0*/ @P0 ST.E.64 [R4.64+0x10], R8 ; /* 0x0000100804000985 */
/* 0x004fe8000c101b24 */
/*02c0*/ @P0 LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000824020a0981 */
/* 0x000ea8000c1e1b00 */
/*02d0*/ @P0 ST.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04000985 */
/* 0x004fe8000c101b24 */
/*02e0*/ @P0 LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000824020c0981 */
/* 0x000ea8000c1e1b00 */
/*02f0*/ @P0 LD.E.64 R12, [R12.64+0x10] ; /* 0x000010240c0c0980 */
/* 0x004ea8000c101b00 */
/*0300*/ @P0 ST.E.64 [R12.64+0x8], R4 ; /* 0x000008040c000985 */
/* 0x0043e8000c101b24 */
/*0310*/ @P0 LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000824020e0981 */
/* 0x000ea8000c1e1b00 */
/*0320*/ @P0 ST.E.64 [R14.64+0x10], R4 ; /* 0x000010040e000985 */
/* 0x004fe8000c101b24 */
/*0330*/ @!P0 ST.E.64 [R6.64+0x8], R4 ; /* 0x0000080406008985 */
/* 0x000fe8000c101b24 */
/*0340*/ @!P0 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000082402108981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ @!P0 ST.E.64 [R16.64+0x10], R4 ; /* 0x0000100410008985 */
/* 0x004fe8000c101b24 */
/*0360*/ @!P0 LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000082402088981 */
/* 0x000ea8000c1e1b00 */
/*0370*/ @!P0 ST.E.64 [R4.64+0x8], R8 ; /* 0x0000080804008985 */
/* 0x004fe8000c101b24 */
/*0380*/ @!P0 LDG.E.64 R10, [R2.64] ; /* 0x00000024020a8981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ @!P0 ST.E.64 [R4.64+0x10], R10 ; /* 0x0000100a04008985 */
/* 0x004fe8000c101b24 */
/*03a0*/ LDG.E R0, [R2.64+0x10] ; /* 0x0000102402007981 */
/* 0x000e64000c1e1900 */
/*03b0*/ IADD3 R13, R0, 0x1, RZ ; /* 0x00000001000d7810 */
/* 0x002fca0007ffe0ff */
/*03c0*/ STG.E [R2.64+0x10], R13 ; /* 0x0000100d02007986 */
/* 0x000fe2000c101924 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <memory>
#include <fstream>
#include <queue>
class Graph{
public:
Graph(const int verticeNum){
this->verticeNum = verticeNum;
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
}
Graph(std::string fileName){
std::ifstream file;
file.open(fileName);
if(!file){
printf("Unable to open file!\n");
exit(1);
}
file >> verticeNum;
//find vertice number
//skip the second line
int tmp;
file >> tmp;
//init matrix...
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = -1;
}
}
int vA, vB;
while (!file.eof()) {
file >> vA >> vB;
int linkWeight = generateRandomNum(100);
graphMatrix[vA][vB] = linkWeight;
graphMatrix[vB][vA] = linkWeight;
}
file.close();
}
void printGraphMatrix(){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
printf("%d\t", graphMatrix[i][j]);
}
printf("\n");
}
}
void BFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
//printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.empty()){
i = bfsQueue.front();
bfsQueue.pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue.push(j);
}
}
}
}
}
}
void _recursiveBFS(std::queue<int>* bfsQueue, bool visited[]){
while(!bfsQueue->empty()){
int i = bfsQueue->front();
bfsQueue->pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue->push(j);
}
}
_recursiveBFS(bfsQueue, visited);
}
}
void recursiveBFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
if(!visited[i]){
//printf("visit node %d\n", i);
bfsQueue.push(i);
visited[i] = true;
_recursiveBFS(&bfsQueue, visited);
}
}
}
int** graphMatrix;
int verticeNum;
private:
void generateRandomMatrix(int verticeNum){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = generateRandomNum(100);
}
}
}
int generateRandomNum(int max){
return rand() % 100;
}
};
struct Node{
int data;
Node* next;
Node* prev;
Node(int data){
this->data = data;
}
Node(){}
}Node;
struct List{
struct Node* head, *tail;
int listSize;
List(int vNum){
head = (struct Node*)malloc(sizeof(Node) * vNum);
tail = head + 1;
head->next = tail;
tail->prev = head;
listSize = 0;
}
~List(){
delete []head;
}
void push(int data){
struct Node* node = new struct Node(data);
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
int pop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
void cudaPush(int data){
struct Node* node = (struct Node*)malloc(sizeof(struct Node));
node->data = data;
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
__device__
int cudaPop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
int cudaGetSize(){
return listSize;
}
__device__
bool cudaIsEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
int getSize(){
return listSize;
}
bool isEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
void printList(){
struct Node* node = head->next;
while(node != tail){
//printf("value %d\n", node->data);
node = node->next;
}
}
};
__global__
void cudaComputeBFS(bool* visited, int** graphMatrix, List* bfsQueue, int* i){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if(graphMatrix[*i][x] != -1 && !visited[x]){
visited[x] = true;
//printf("inner visit node %d\n", x);
bfsQueue->cudaPush(x);
}
}
void cudaBFS(Graph g){
const int vNum = g.verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
struct List bfsQueue(vNum);
for(int i = 0; i < vNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.isEmpty()){
i = bfsQueue.pop();
//cuda optimization...
const int BLOCK_SIZE = 64;
dim3 dimBlock((vNum + BLOCK_SIZE - 1) / BLOCK_SIZE, 1, 1);
dim3 dimGrid(BLOCK_SIZE, 1, 1);
bool* cudaVisited;
int** cudaGraphMatrix;
List* cudaBfsQueue;
int* cudaI;
int* cudaSize;
int* size;
cudaMalloc(&cudaVisited, sizeof(bool) * vNum);
cudaMalloc(&cudaBfsQueue->head, sizeof(Node) * vNum + 2);
cudaMalloc(&cudaGraphMatrix, sizeof(int *) * vNum);
cudaMalloc(&cudaI, sizeof(int*));
cudaMalloc(&cudaSize, sizeof(int*));
for(int k = 0; k < vNum; k++){
cudaMalloc(&cudaGraphMatrix[k], sizeof(int) * vNum);
}
//copy data to device
cudaMemcpy(cudaVisited, visited, sizeof(bool) * vNum, cudaMemcpyHostToDevice);
int count = 0;
while(!bfsQueue.isEmpty()){
cudaMemcpy(&cudaBfsQueue->head + count++, &bfsQueue.head + count++, sizeof(Node), cudaMemcpyHostToDevice);
}
for(int k = 0; k < vNum; k++){
cudaMemcpy(cudaGraphMatrix, g.graphMatrix, sizeof(int) * vNum, cudaMemcpyHostToDevice);
}
cudaMemcpy(cudaI, &i, sizeof(int), cudaMemcpyHostToDevice);
cudaComputeBFS<<<dimGrid, dimBlock>>>(cudaVisited, cudaGraphMatrix, cudaBfsQueue, cudaI);
//update visited & queue...
cudaMemcpy(visited, cudaVisited, sizeof(bool) * vNum, cudaMemcpyDeviceToHost);
cudaMemcpy(&bfsQueue.head, &cudaBfsQueue->head, sizeof(Node) * vNum, cudaMemcpyDeviceToHost);
cudaFree(cudaVisited);
cudaFree (cudaGraphMatrix);
cudaFree(cudaI);
cudaFree(cudaBfsQueue);
}
}
}
}
int main(){
struct timeval tpstart, tpend;
long timeuse;
Graph graph("./largeG.txt");
gettimeofday( &tpstart, NULL );
//graph.BFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU looped version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//graph.recursiveBFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU recursive version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//cudaBFS(graph);
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("GPU version is finished in time %ld ms\n", timeuse);
return 0;
} | .file "tmpxft_0012f96e_00000000-6_bfs.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_
.type _Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_, @function
_Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_:
.LFB5076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14cudaComputeBFSPbPPiP4ListS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5076:
.size _Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_, .-_Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_
.globl _Z14cudaComputeBFSPbPPiP4ListS0_
.type _Z14cudaComputeBFSPbPPiP4ListS0_, @function
_Z14cudaComputeBFSPbPPiP4ListS0_:
.LFB5077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5077:
.size _Z14cudaComputeBFSPbPPiP4ListS0_, .-_Z14cudaComputeBFSPbPPiP4ListS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "visit node %d\n"
.text
.globl _Z7cudaBFS5Graph
.type _Z7cudaBFS5Graph, @function
_Z7cudaBFS5Graph:
.LFB5050:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5050
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -152(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl %esi, %r12d
movslq %esi, %rax
movq %rax, -168(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
movq %rbx, -160(%rbp)
testl %esi, %esi
jle .L15
movq %rbx, %rax
movq -168(%rbp), %rcx
leaq (%rcx,%rbx), %rdx
.L16:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L16
movq -168(%rbp), %rax
leaq (%rax,%rax,2), %rax
salq $3, %rax
movq %rax, -176(%rbp)
movq %rax, %rdi
call malloc@PLT
movq %rax, -80(%rbp)
leaq 24(%rax), %rdx
movq %rdx, -72(%rbp)
movq %rdx, 8(%rax)
movq %rax, 40(%rax)
movl $0, -64(%rbp)
movl $0, -140(%rbp)
movl $0, %edx
jmp .L28
.L50:
movl -140(%rbp), %ebx
movl $24, %edi
.LEHB0:
call _Znwm@PLT
movl %ebx, (%rax)
movq -80(%rbp), %rcx
movq -72(%rbp), %rdx
cmpq %rdx, 8(%rcx)
je .L42
movq 16(%rdx), %rsi
movq %rsi, 16(%rax)
movq %rdx, 8(%rax)
movq 16(%rdx), %rdx
movq %rax, 8(%rdx)
movq -72(%rbp), %rdx
movq %rax, 16(%rdx)
.L19:
addl $1, -64(%rbp)
movq 8(%rcx), %rdi
cmpq -72(%rbp), %rdi
je .L17
leal 126(%r12), %eax
movl %r12d, %edx
addl $63, %edx
cmovns %edx, %eax
sarl $6, %eax
movl %eax, -188(%rbp)
movq -168(%rbp), %rax
leaq 0(,%rax,8), %r13
leaq 0(,%rax,4), %rbx
leaq -136(%rbp), %rax
movq %rax, -200(%rbp)
jmp .L20
.L42:
movq %rax, 8(%rcx)
movq -72(%rbp), %rdx
movq %rax, 16(%rdx)
movq %rdx, 8(%rax)
movq %rcx, 16(%rax)
jmp .L19
.L49:
movl $0, %edi
movq %rdi, -184(%rbp)
movq -176(%rbp), %rax
leaq 2(%rax), %rsi
call cudaMalloc@PLT
leaq -128(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -120(%rbp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $0, %r14d
jmp .L21
.L44:
addq $8, %r14
cmpq %r14, %r13
je .L43
.L21:
movq %r14, %rdi
addq -128(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
jmp .L44
.L43:
movl $1, %ecx
movq -168(%rbp), %rdx
movq -160(%rbp), %rsi
movq -136(%rbp), %rdi
call cudaMemcpy@PLT
movl $8, %r14d
leaq -80(%rbp), %r15
jmp .L22
.L46:
addq $16, %r14
addq $16, %r15
.L22:
movq -80(%rbp), %rax
movq -72(%rbp), %rcx
cmpq %rcx, 8(%rax)
je .L45
movl $1, %ecx
movl $24, %edx
movq %r15, %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
jmp .L46
.L45:
movl $0, %r14d
jmp .L24
.L48:
addl $1, %r14d
cmpl %r14d, %r12d
je .L47
.L24:
movl $1, %ecx
movq %rbx, %rdx
movq -152(%rbp), %rsi
movq -128(%rbp), %rdi
call cudaMemcpy@PLT
jmp .L48
.L47:
leaq -140(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl -96(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -104(%rbp), %rdx
movq -92(%rbp), %rdi
movl -84(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movq -120(%rbp), %rcx
movl $0, %edi
movq %rdi, %rdx
movq -128(%rbp), %rsi
movq -136(%rbp), %rdi
call _Z46__device_stub__Z14cudaComputeBFSPbPPiP4ListS0_PbPPiP4ListS0_
.L25:
movl $2, %ecx
movq -168(%rbp), %rdx
movq -136(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
leaq -80(%rbp), %rdi
movl $2, %ecx
movq -176(%rbp), %rdx
movq -184(%rbp), %rsi
call cudaMemcpy@PLT
movq -136(%rbp), %rdi
call cudaFree@PLT
movq -128(%rbp), %rdi
call cudaFree@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq -80(%rbp), %rax
movq 8(%rax), %rdi
cmpq -72(%rbp), %rdi
je .L17
.L20:
movq 16(%rdi), %rdx
movq 8(%rdi), %rax
movq %rax, 8(%rdx)
movq 16(%rdi), %rdx
movq %rdx, 16(%rax)
movl (%rdi), %r14d
testq %rdi, %rdi
je .L26
movl $24, %esi
call _ZdlPvm@PLT
.L26:
subl $1, -64(%rbp)
movl %r14d, -140(%rbp)
movl -188(%rbp), %eax
movl %eax, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $64, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movq -168(%rbp), %rsi
movq -200(%rbp), %rdi
call cudaMalloc@PLT
jmp .L49
.L17:
movl -140(%rbp), %eax
leal 1(%rax), %edx
movl %edx, -140(%rbp)
cmpl %r12d, %edx
jge .L33
.L28:
movslq %edx, %rax
movq -160(%rbp), %rbx
cmpb $0, (%rbx,%rax)
jne .L17
movb $1, (%rbx,%rax)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE0:
jmp .L50
.L35:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L31
call _ZdaPv@PLT
.L31:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L15:
movq -168(%rbp), %rax
leaq (%rax,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, -80(%rbp)
leaq 24(%rax), %rdx
movq %rdx, -72(%rbp)
movq %rdx, 8(%rax)
movq %rax, 40(%rax)
movl $0, -64(%rbp)
.L33:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L11
call _ZdaPv@PLT
.L11:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L51
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L51:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5050:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA5050:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5050-.LLSDACSB5050
.LLSDACSB5050:
.uleb128 .LEHB0-.LFB5050
.uleb128 .LEHE0-.LEHB0
.uleb128 .L35-.LFB5050
.uleb128 0
.uleb128 .LEHB1-.LFB5050
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE5050:
.text
.size _Z7cudaBFS5Graph, .-_Z7cudaBFS5Graph
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z14cudaComputeBFSPbPPiP4ListS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14cudaComputeBFSPbPPiP4ListS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5079:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE.str1.1,"aMS",@progbits,1
.LC2:
.string "Unable to open file!\n"
.section .text._ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN5GraphC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.align 2
.weak _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB5017:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5017
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $552, %rsp
.cfi_def_cfa_offset 608
movq %rdi, %rbx
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %r14
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
movq $0, 488(%rsp)
movb $0, 496(%rsp)
movb $0, 497(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rbp
movq %rbp, 16(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq -24(%rbp), %rax
movq %r12, 16(%rsp,%rax)
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movq %r14, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rdi
.LEHB3:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE3:
leaq 32(%rsp), %rsi
leaq 272(%rsp), %rdi
.LEHB4:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE4:
jmp .L98
.L87:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L57:
movq %rbp, 16(%rsp)
movq -24(%rbp), %rax
movq %r12, 16(%rsp,%rax)
movq $0, 24(%rsp)
.L58:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L86:
endbr64
movq %rax, %rbx
jmp .L57
.L85:
endbr64
movq %rax, %rbx
jmp .L58
.L59:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L98:
movq 0(%r13), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
.LEHB6:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L99
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L61
.L99:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L61:
testb $5, 304(%rsp)
jne .L100
leaq 8(%rbx), %rsi
leaq 16(%rsp), %rdi
call _ZNSirsERi@PLT
jmp .L101
.L100:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L101:
leaq 4(%rsp), %rsi
leaq 16(%rsp), %rdi
call _ZNSirsERi@PLT
movslq 8(%rbx), %rax
movq %rax, %rsi
shrq $60, %rsi
jne .L63
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, (%rbx)
movl 8(%rbx), %edi
movl $0, %r13d
movabsq $2305843009213693950, %r14
testl %edi, %edi
jg .L70
.L66:
testb $2, 304(%rsp)
jne .L75
leaq 8(%rsp), %r13
jmp .L76
.L63:
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L65:
call __cxa_throw_bad_array_new_length@PLT
.L84:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L81
call __stack_chk_fail@PLT
.L103:
movq %rax, (%r15)
movl 8(%rbx), %edi
addq $1, %r13
cmpl %r13d, %edi
jle .L102
.L70:
movslq %edi, %rdi
cmpq %rdi, %r14
jb .L67
movq (%rbx), %rax
leaq (%rax,%r13,8), %r15
salq $2, %rdi
call _Znam@PLT
jmp .L103
.L67:
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L69
call __stack_chk_fail@PLT
.L69:
call __cxa_throw_bad_array_new_length@PLT
.L102:
testl %edi, %edi
jle .L66
movl $0, %esi
jmp .L71
.L72:
movq (%rbx), %rdx
movq (%rdx,%rcx), %rdx
movl $-1, (%rdx,%rax,4)
addq $1, %rax
cmpl %eax, 8(%rbx)
jg .L72
.L74:
addq $1, %rsi
cmpl %esi, 8(%rbx)
jle .L66
.L71:
leaq 0(,%rsi,8), %rcx
movl $0, %eax
cmpl $0, 8(%rbx)
jg .L72
jmp .L74
.L104:
movq %rax, %rdi
leaq 12(%rsp), %rsi
call _ZNSirsERi@PLT
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
movslq 8(%rsp), %rsi
movq (%rbx), %rax
movslq 12(%rsp), %rcx
movq (%rax,%rsi,8), %rax
movl %edx, (%rax,%rcx,4)
movslq 12(%rsp), %rsi
movq (%rbx), %rax
movslq 8(%rsp), %rcx
movq (%rax,%rsi,8), %rax
movl %edx, (%rax,%rcx,4)
testb $2, 304(%rsp)
jne .L75
.L76:
leaq 16(%rsp), %rdi
movq %r13, %rsi
call _ZNSirsERi@PLT
jmp .L104
.L75:
leaq 32(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE6:
testq %rax, %rax
je .L105
.L77:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rdi
.LEHB7:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE7:
jmp .L79
.L105:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB8:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE8:
jmp .L77
.L88:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L79:
leaq 136(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %rbp, 16(%rsp)
movq -24(%rbp), %rax
movq %r12, 16(%rsp,%rax)
movq $0, 24(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L106
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L106:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5017:
.section .gcc_except_table
.align 4
.LLSDA5017:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT5017-.LLSDATTD5017
.LLSDATTD5017:
.byte 0x1
.uleb128 .LLSDACSE5017-.LLSDACSB5017
.LLSDACSB5017:
.uleb128 .LEHB2-.LFB5017
.uleb128 .LEHE2-.LEHB2
.uleb128 .L85-.LFB5017
.uleb128 0
.uleb128 .LEHB3-.LFB5017
.uleb128 .LEHE3-.LEHB3
.uleb128 .L86-.LFB5017
.uleb128 0
.uleb128 .LEHB4-.LFB5017
.uleb128 .LEHE4-.LEHB4
.uleb128 .L87-.LFB5017
.uleb128 0
.uleb128 .LEHB5-.LFB5017
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.uleb128 .LEHB6-.LFB5017
.uleb128 .LEHE6-.LEHB6
.uleb128 .L84-.LFB5017
.uleb128 0
.uleb128 .LEHB7-.LFB5017
.uleb128 .LEHE7-.LEHB7
.uleb128 .L88-.LFB5017
.uleb128 0x1
.uleb128 .LEHB8-.LFB5017
.uleb128 .LEHE8-.LEHB8
.uleb128 .L84-.LFB5017
.uleb128 0
.uleb128 .LEHB9-.LFB5017
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.LLSDACSE5017:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT5017:
.section .text._ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN5GraphC5ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.size _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.weak _ZN5GraphC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.set _ZN5GraphC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.8
.align 8
.LC3:
.string "CPU looped version is finished in time %ld ms\n"
.align 8
.LC4:
.string "CPU recursive version is finished in time %ld ms\n"
.align 8
.LC5:
.string "GPU version is finished in time %ld ms\n"
.text
.globl main
.type main, @function
main:
.LFB5051:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5051
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
movabsq $5144631890299072302, %rax
movq %rax, 64(%rsp)
movl $1954051118, 72(%rsp)
movq $12, 56(%rsp)
movb $0, 76(%rsp)
leaq 32(%rsp), %rdi
.LEHB10:
call _ZN5GraphC1ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE10:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq %rsp, %r12
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
leaq 16(%rsp), %rbp
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
movq 16(%rsp), %rcx
subq (%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 24(%rsp), %rsi
subq 8(%rsp), %rsi
movabsq $2361183241434822607, %rbx
movq %rsi, %rax
imulq %rbx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addq %rcx, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB11:
call __printf_chk@PLT
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
movq 16(%rsp), %rcx
subq (%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 24(%rsp), %rsi
subq 8(%rsp), %rsi
movq %rsi, %rax
imulq %rbx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addq %rcx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq %r12, %rdi
call gettimeofday@PLT
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
movq 16(%rsp), %rcx
subq (%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 24(%rsp), %rsi
subq 8(%rsp), %rsi
movq %rsi, %rax
imulq %rbx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
addq %rcx, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L114
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L111:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L109
call __stack_chk_fail@PLT
.L109:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE11:
.L114:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5051:
.section .gcc_except_table
.LLSDA5051:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5051-.LLSDACSB5051
.LLSDACSB5051:
.uleb128 .LEHB10-.LFB5051
.uleb128 .LEHE10-.LEHB10
.uleb128 .L111-.LFB5051
.uleb128 0
.uleb128 .LEHB11-.LFB5051
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE5051:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl Node
.bss
.align 16
.type Node, @object
.size Node, 24
Node:
.zero 24
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <memory>
#include <fstream>
#include <queue>
class Graph{
public:
Graph(const int verticeNum){
this->verticeNum = verticeNum;
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
}
Graph(std::string fileName){
std::ifstream file;
file.open(fileName);
if(!file){
printf("Unable to open file!\n");
exit(1);
}
file >> verticeNum;
//find vertice number
//skip the second line
int tmp;
file >> tmp;
//init matrix...
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = -1;
}
}
int vA, vB;
while (!file.eof()) {
file >> vA >> vB;
int linkWeight = generateRandomNum(100);
graphMatrix[vA][vB] = linkWeight;
graphMatrix[vB][vA] = linkWeight;
}
file.close();
}
void printGraphMatrix(){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
printf("%d\t", graphMatrix[i][j]);
}
printf("\n");
}
}
void BFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
//printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.empty()){
i = bfsQueue.front();
bfsQueue.pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue.push(j);
}
}
}
}
}
}
void _recursiveBFS(std::queue<int>* bfsQueue, bool visited[]){
while(!bfsQueue->empty()){
int i = bfsQueue->front();
bfsQueue->pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue->push(j);
}
}
_recursiveBFS(bfsQueue, visited);
}
}
void recursiveBFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
if(!visited[i]){
//printf("visit node %d\n", i);
bfsQueue.push(i);
visited[i] = true;
_recursiveBFS(&bfsQueue, visited);
}
}
}
int** graphMatrix;
int verticeNum;
private:
void generateRandomMatrix(int verticeNum){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = generateRandomNum(100);
}
}
}
int generateRandomNum(int max){
return rand() % 100;
}
};
struct Node{
int data;
Node* next;
Node* prev;
Node(int data){
this->data = data;
}
Node(){}
}Node;
struct List{
struct Node* head, *tail;
int listSize;
List(int vNum){
head = (struct Node*)malloc(sizeof(Node) * vNum);
tail = head + 1;
head->next = tail;
tail->prev = head;
listSize = 0;
}
~List(){
delete []head;
}
void push(int data){
struct Node* node = new struct Node(data);
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
int pop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
void cudaPush(int data){
struct Node* node = (struct Node*)malloc(sizeof(struct Node));
node->data = data;
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
__device__
int cudaPop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
int cudaGetSize(){
return listSize;
}
__device__
bool cudaIsEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
int getSize(){
return listSize;
}
bool isEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
void printList(){
struct Node* node = head->next;
while(node != tail){
//printf("value %d\n", node->data);
node = node->next;
}
}
};
__global__
void cudaComputeBFS(bool* visited, int** graphMatrix, List* bfsQueue, int* i){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if(graphMatrix[*i][x] != -1 && !visited[x]){
visited[x] = true;
//printf("inner visit node %d\n", x);
bfsQueue->cudaPush(x);
}
}
void cudaBFS(Graph g){
const int vNum = g.verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
struct List bfsQueue(vNum);
for(int i = 0; i < vNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.isEmpty()){
i = bfsQueue.pop();
//cuda optimization...
const int BLOCK_SIZE = 64;
dim3 dimBlock((vNum + BLOCK_SIZE - 1) / BLOCK_SIZE, 1, 1);
dim3 dimGrid(BLOCK_SIZE, 1, 1);
bool* cudaVisited;
int** cudaGraphMatrix;
List* cudaBfsQueue;
int* cudaI;
int* cudaSize;
int* size;
cudaMalloc(&cudaVisited, sizeof(bool) * vNum);
cudaMalloc(&cudaBfsQueue->head, sizeof(Node) * vNum + 2);
cudaMalloc(&cudaGraphMatrix, sizeof(int *) * vNum);
cudaMalloc(&cudaI, sizeof(int*));
cudaMalloc(&cudaSize, sizeof(int*));
for(int k = 0; k < vNum; k++){
cudaMalloc(&cudaGraphMatrix[k], sizeof(int) * vNum);
}
//copy data to device
cudaMemcpy(cudaVisited, visited, sizeof(bool) * vNum, cudaMemcpyHostToDevice);
int count = 0;
while(!bfsQueue.isEmpty()){
cudaMemcpy(&cudaBfsQueue->head + count++, &bfsQueue.head + count++, sizeof(Node), cudaMemcpyHostToDevice);
}
for(int k = 0; k < vNum; k++){
cudaMemcpy(cudaGraphMatrix, g.graphMatrix, sizeof(int) * vNum, cudaMemcpyHostToDevice);
}
cudaMemcpy(cudaI, &i, sizeof(int), cudaMemcpyHostToDevice);
cudaComputeBFS<<<dimGrid, dimBlock>>>(cudaVisited, cudaGraphMatrix, cudaBfsQueue, cudaI);
//update visited & queue...
cudaMemcpy(visited, cudaVisited, sizeof(bool) * vNum, cudaMemcpyDeviceToHost);
cudaMemcpy(&bfsQueue.head, &cudaBfsQueue->head, sizeof(Node) * vNum, cudaMemcpyDeviceToHost);
cudaFree(cudaVisited);
cudaFree (cudaGraphMatrix);
cudaFree(cudaI);
cudaFree(cudaBfsQueue);
}
}
}
}
int main(){
struct timeval tpstart, tpend;
long timeuse;
Graph graph("./largeG.txt");
gettimeofday( &tpstart, NULL );
//graph.BFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU looped version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//graph.recursiveBFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU recursive version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//cudaBFS(graph);
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("GPU version is finished in time %ld ms\n", timeuse);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <memory>
#include <fstream>
#include <queue>
class Graph{
public:
Graph(const int verticeNum){
this->verticeNum = verticeNum;
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
}
Graph(std::string fileName){
std::ifstream file;
file.open(fileName);
if(!file){
printf("Unable to open file!\n");
exit(1);
}
file >> verticeNum;
//find vertice number
//skip the second line
int tmp;
file >> tmp;
//init matrix...
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = -1;
}
}
int vA, vB;
while (!file.eof()) {
file >> vA >> vB;
int linkWeight = generateRandomNum(100);
graphMatrix[vA][vB] = linkWeight;
graphMatrix[vB][vA] = linkWeight;
}
file.close();
}
void printGraphMatrix(){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
printf("%d\t", graphMatrix[i][j]);
}
printf("\n");
}
}
void BFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
//printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.empty()){
i = bfsQueue.front();
bfsQueue.pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue.push(j);
}
}
}
}
}
}
void _recursiveBFS(std::queue<int>* bfsQueue, bool visited[]){
while(!bfsQueue->empty()){
int i = bfsQueue->front();
bfsQueue->pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue->push(j);
}
}
_recursiveBFS(bfsQueue, visited);
}
}
void recursiveBFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
if(!visited[i]){
//printf("visit node %d\n", i);
bfsQueue.push(i);
visited[i] = true;
_recursiveBFS(&bfsQueue, visited);
}
}
}
int** graphMatrix;
int verticeNum;
private:
void generateRandomMatrix(int verticeNum){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = generateRandomNum(100);
}
}
}
int generateRandomNum(int max){
return rand() % 100;
}
};
struct Node{
int data;
Node* next;
Node* prev;
Node(int data){
this->data = data;
}
Node(){}
}Node;
struct List{
struct Node* head, *tail;
int listSize;
List(int vNum){
head = (struct Node*)malloc(sizeof(Node) * vNum);
tail = head + 1;
head->next = tail;
tail->prev = head;
listSize = 0;
}
~List(){
delete []head;
}
void push(int data){
struct Node* node = new struct Node(data);
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
int pop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
void cudaPush(int data){
struct Node* node = (struct Node*)malloc(sizeof(struct Node));
node->data = data;
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
__device__
int cudaPop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
int cudaGetSize(){
return listSize;
}
__device__
bool cudaIsEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
int getSize(){
return listSize;
}
bool isEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
void printList(){
struct Node* node = head->next;
while(node != tail){
//printf("value %d\n", node->data);
node = node->next;
}
}
};
__global__
void cudaComputeBFS(bool* visited, int** graphMatrix, List* bfsQueue, int* i){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if(graphMatrix[*i][x] != -1 && !visited[x]){
visited[x] = true;
//printf("inner visit node %d\n", x);
bfsQueue->cudaPush(x);
}
}
void cudaBFS(Graph g){
const int vNum = g.verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
struct List bfsQueue(vNum);
for(int i = 0; i < vNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.isEmpty()){
i = bfsQueue.pop();
//cuda optimization...
const int BLOCK_SIZE = 64;
dim3 dimBlock((vNum + BLOCK_SIZE - 1) / BLOCK_SIZE, 1, 1);
dim3 dimGrid(BLOCK_SIZE, 1, 1);
bool* cudaVisited;
int** cudaGraphMatrix;
List* cudaBfsQueue;
int* cudaI;
int* cudaSize;
int* size;
hipMalloc(&cudaVisited, sizeof(bool) * vNum);
hipMalloc(&cudaBfsQueue->head, sizeof(Node) * vNum + 2);
hipMalloc(&cudaGraphMatrix, sizeof(int *) * vNum);
hipMalloc(&cudaI, sizeof(int*));
hipMalloc(&cudaSize, sizeof(int*));
for(int k = 0; k < vNum; k++){
hipMalloc(&cudaGraphMatrix[k], sizeof(int) * vNum);
}
//copy data to device
hipMemcpy(cudaVisited, visited, sizeof(bool) * vNum, hipMemcpyHostToDevice);
int count = 0;
while(!bfsQueue.isEmpty()){
hipMemcpy(&cudaBfsQueue->head + count++, &bfsQueue.head + count++, sizeof(Node), hipMemcpyHostToDevice);
}
for(int k = 0; k < vNum; k++){
hipMemcpy(cudaGraphMatrix, g.graphMatrix, sizeof(int) * vNum, hipMemcpyHostToDevice);
}
hipMemcpy(cudaI, &i, sizeof(int), hipMemcpyHostToDevice);
cudaComputeBFS<<<dimGrid, dimBlock>>>(cudaVisited, cudaGraphMatrix, cudaBfsQueue, cudaI);
//update visited & queue...
hipMemcpy(visited, cudaVisited, sizeof(bool) * vNum, hipMemcpyDeviceToHost);
hipMemcpy(&bfsQueue.head, &cudaBfsQueue->head, sizeof(Node) * vNum, hipMemcpyDeviceToHost);
hipFree(cudaVisited);
hipFree (cudaGraphMatrix);
hipFree(cudaI);
hipFree(cudaBfsQueue);
}
}
}
}
int main(){
struct timeval tpstart, tpend;
long timeuse;
Graph graph("./largeG.txt");
gettimeofday( &tpstart, NULL );
//graph.BFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU looped version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//graph.recursiveBFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU recursive version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//cudaBFS(graph);
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("GPU version is finished in time %ld ms\n", timeuse);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <memory>
#include <fstream>
#include <queue>
class Graph{
public:
Graph(const int verticeNum){
this->verticeNum = verticeNum;
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
}
Graph(std::string fileName){
std::ifstream file;
file.open(fileName);
if(!file){
printf("Unable to open file!\n");
exit(1);
}
file >> verticeNum;
//find vertice number
//skip the second line
int tmp;
file >> tmp;
//init matrix...
graphMatrix = new int*[verticeNum];
for(int i = 0; i < verticeNum; i++){
graphMatrix[i] = new int [verticeNum];
}
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = -1;
}
}
int vA, vB;
while (!file.eof()) {
file >> vA >> vB;
int linkWeight = generateRandomNum(100);
graphMatrix[vA][vB] = linkWeight;
graphMatrix[vB][vA] = linkWeight;
}
file.close();
}
void printGraphMatrix(){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
printf("%d\t", graphMatrix[i][j]);
}
printf("\n");
}
}
void BFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
//printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.empty()){
i = bfsQueue.front();
bfsQueue.pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue.push(j);
}
}
}
}
}
}
void _recursiveBFS(std::queue<int>* bfsQueue, bool visited[]){
while(!bfsQueue->empty()){
int i = bfsQueue->front();
bfsQueue->pop();
for(int j = 0; j < verticeNum; j++){
if(graphMatrix[i][j] != -1 && !visited[j]){
visited[j] = true;
//printf("inner visit node %d\n", j);
bfsQueue->push(j);
}
}
_recursiveBFS(bfsQueue, visited);
}
}
void recursiveBFS(){
const int vNum = verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
std::queue<int> bfsQueue;
for(int i = 0; i < verticeNum; i++){
if(!visited[i]){
//printf("visit node %d\n", i);
bfsQueue.push(i);
visited[i] = true;
_recursiveBFS(&bfsQueue, visited);
}
}
}
int** graphMatrix;
int verticeNum;
private:
void generateRandomMatrix(int verticeNum){
for(int i = 0 ; i < verticeNum; i++){
for(int j =0 ; j < verticeNum; j++){
graphMatrix[i][j] = generateRandomNum(100);
}
}
}
int generateRandomNum(int max){
return rand() % 100;
}
};
struct Node{
int data;
Node* next;
Node* prev;
Node(int data){
this->data = data;
}
Node(){}
}Node;
struct List{
struct Node* head, *tail;
int listSize;
List(int vNum){
head = (struct Node*)malloc(sizeof(Node) * vNum);
tail = head + 1;
head->next = tail;
tail->prev = head;
listSize = 0;
}
~List(){
delete []head;
}
void push(int data){
struct Node* node = new struct Node(data);
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
int pop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
void cudaPush(int data){
struct Node* node = (struct Node*)malloc(sizeof(struct Node));
node->data = data;
if(head->next == tail){
head->next = node;
tail->prev = node;
node->next = tail;
node->prev = head;
}else{
node->prev = tail->prev;
node->next = tail;
tail->prev->next = node;
tail->prev = node;
}
listSize++;
}
__device__
int cudaPop(){
assert(!isEmpty());
struct Node * tmp = head->next;
tmp->prev->next = tmp->next;
tmp->next->prev = tmp->prev;
int n = tmp->data;
delete tmp;
listSize--;
return n;
}
__device__
int cudaGetSize(){
return listSize;
}
__device__
bool cudaIsEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
int getSize(){
return listSize;
}
bool isEmpty(){
if(head->next == tail){
return true;
}else{
return false;
}
}
void printList(){
struct Node* node = head->next;
while(node != tail){
//printf("value %d\n", node->data);
node = node->next;
}
}
};
__global__
void cudaComputeBFS(bool* visited, int** graphMatrix, List* bfsQueue, int* i){
int x = blockIdx.x * blockDim.x + threadIdx.x;
if(graphMatrix[*i][x] != -1 && !visited[x]){
visited[x] = true;
//printf("inner visit node %d\n", x);
bfsQueue->cudaPush(x);
}
}
void cudaBFS(Graph g){
const int vNum = g.verticeNum;
bool visited[vNum];
for(int i = 0; i < vNum; i++){
visited[i] = false;
}
struct List bfsQueue(vNum);
for(int i = 0; i < vNum; i++){
//if not visited, we do processing..
if(!visited[i]){
//mark the node as visited
visited[i] = true;
printf("visit node %d\n", i);
bfsQueue.push(i);
while(!bfsQueue.isEmpty()){
i = bfsQueue.pop();
//cuda optimization...
const int BLOCK_SIZE = 64;
dim3 dimBlock((vNum + BLOCK_SIZE - 1) / BLOCK_SIZE, 1, 1);
dim3 dimGrid(BLOCK_SIZE, 1, 1);
bool* cudaVisited;
int** cudaGraphMatrix;
List* cudaBfsQueue;
int* cudaI;
int* cudaSize;
int* size;
hipMalloc(&cudaVisited, sizeof(bool) * vNum);
hipMalloc(&cudaBfsQueue->head, sizeof(Node) * vNum + 2);
hipMalloc(&cudaGraphMatrix, sizeof(int *) * vNum);
hipMalloc(&cudaI, sizeof(int*));
hipMalloc(&cudaSize, sizeof(int*));
for(int k = 0; k < vNum; k++){
hipMalloc(&cudaGraphMatrix[k], sizeof(int) * vNum);
}
//copy data to device
hipMemcpy(cudaVisited, visited, sizeof(bool) * vNum, hipMemcpyHostToDevice);
int count = 0;
while(!bfsQueue.isEmpty()){
hipMemcpy(&cudaBfsQueue->head + count++, &bfsQueue.head + count++, sizeof(Node), hipMemcpyHostToDevice);
}
for(int k = 0; k < vNum; k++){
hipMemcpy(cudaGraphMatrix, g.graphMatrix, sizeof(int) * vNum, hipMemcpyHostToDevice);
}
hipMemcpy(cudaI, &i, sizeof(int), hipMemcpyHostToDevice);
cudaComputeBFS<<<dimGrid, dimBlock>>>(cudaVisited, cudaGraphMatrix, cudaBfsQueue, cudaI);
//update visited & queue...
hipMemcpy(visited, cudaVisited, sizeof(bool) * vNum, hipMemcpyDeviceToHost);
hipMemcpy(&bfsQueue.head, &cudaBfsQueue->head, sizeof(Node) * vNum, hipMemcpyDeviceToHost);
hipFree(cudaVisited);
hipFree (cudaGraphMatrix);
hipFree(cudaI);
hipFree(cudaBfsQueue);
}
}
}
}
int main(){
struct timeval tpstart, tpend;
long timeuse;
Graph graph("./largeG.txt");
gettimeofday( &tpstart, NULL );
//graph.BFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU looped version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//graph.recursiveBFS();
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("CPU recursive version is finished in time %ld ms\n", timeuse);
gettimeofday( &tpstart, NULL );
//cudaBFS(graph);
gettimeofday (&tpend, NULL);
timeuse = 1000 * (tpend.tv_sec - tpstart.tv_sec) + (tpend.tv_usec - tpstart.tv_usec) / 1000;
printf("GPU version is finished in time %ld ms\n", timeuse);
return 0;
} | .text
.file "bfs.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_ # -- Begin function _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_
.p2align 4, 0x90
.type _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_,@function
_Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_: # @_Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14cudaComputeBFSPbPPiP4ListS0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_, .Lfunc_end0-_Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_
.cfi_endproc
# -- End function
.globl _Z7cudaBFS5Graph # -- Begin function _Z7cudaBFS5Graph
.p2align 4, 0x90
.type _Z7cudaBFS5Graph,@function
_Z7cudaBFS5Graph: # @_Z7cudaBFS5Graph
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $232, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $esi killed $esi def $rsi
movq %rdi, %r14
movl %esi, %r15d
.cfi_escape 0x2e, 0x00
movq %rsp, %r12
leaq 15(%r15), %rax
andq $-16, %rax
subq %rax, %r12
movq %r12, %rsp
movq %rsi, -80(%rbp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_2
# %bb.1: # %.lr.ph.preheader
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.LBB1_2: # %._crit_edge
movq -80(%rbp), %rbx # 8-byte Reload
movslq %ebx, %r13
leaq (,%r13,8), %rax
movq %rax, -144(%rbp) # 8-byte Spill
leaq (%rax,%rax,2), %rdi
.cfi_escape 0x2e, 0x00
movq %rdi, -120(%rbp) # 8-byte Spill
callq malloc
movq %rax, -72(%rbp)
leaq 24(%rax), %rcx
movq %rcx, -64(%rbp)
movq %rcx, 8(%rax)
movq %rax, 40(%rax)
movl $0, -56(%rbp)
movl $0, -44(%rbp)
testl %ebx, %ebx
jle .LBB1_9
# %bb.3: # %.lr.ph91
movq -80(%rbp), %rax # 8-byte Reload
addl $63, %eax
shrl $6, %eax
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rax, %rcx
movq %rcx, -128(%rbp) # 8-byte Spill
movq -120(%rbp), %rax # 8-byte Reload
orq $2, %rax
movq %rax, -136(%rbp) # 8-byte Spill
leaq (,%r13,4), %rbx
shlq $3, %r15
xorl %eax, %eax
movq %r12, -88(%rbp) # 8-byte Spill
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_8: # %.loopexit68
# in Loop: Header=BB1_4 Depth=1
movl -44(%rbp), %eax
incl %eax
movl %eax, -44(%rbp)
cmpl -80(%rbp), %eax # 4-byte Folded Reload
jge .LBB1_9
.LBB1_4: # =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
# Child Loop BB1_21 Depth 3
# Child Loop BB1_25 Depth 3
# Child Loop BB1_27 Depth 3
movslq %eax, %rsi
cmpb $0, (%r12,%rsi)
jne .LBB1_8
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movb $1, (%r12,%rsi)
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl -44(%rbp), %r12d
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $24, %edi
callq _Znwm
.Ltmp1:
# %bb.6: # %.noexc
# in Loop: Header=BB1_4 Depth=1
movl %r12d, (%rax)
movq -72(%rbp), %rdx
movq -64(%rbp), %rcx
cmpq %rcx, 8(%rdx)
je .LBB1_7
# %bb.12: # in Loop: Header=BB1_4 Depth=1
movq 16(%rcx), %rdx
movq %rdx, 16(%rax)
movq %rcx, 8(%rax)
movq 16(%rcx), %rdx
movq %rax, 8(%rdx)
movq %rax, 16(%rcx)
jmp .LBB1_13
.LBB1_7: # in Loop: Header=BB1_4 Depth=1
movq %rax, 8(%rdx)
movq %rax, 16(%rcx)
movq %rcx, 8(%rax)
movq %rdx, 16(%rax)
.LBB1_13: # %_ZN4List4pushEi.exit
# in Loop: Header=BB1_4 Depth=1
movq -88(%rbp), %r12 # 8-byte Reload
incl -56(%rbp)
.p2align 4, 0x90
.LBB1_14: # %_ZN4List4pushEi.exit
# Parent Loop BB1_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_21 Depth 3
# Child Loop BB1_25 Depth 3
# Child Loop BB1_27 Depth 3
movq -72(%rbp), %rax
movq 8(%rax), %rdi
cmpq -64(%rbp), %rdi
je .LBB1_8
# %bb.15: # %.lr.ph85
# in Loop: Header=BB1_14 Depth=2
movq 8(%rdi), %rax
movq 16(%rdi), %rcx
movq %rax, 8(%rcx)
movq 8(%rdi), %rax
movq %rcx, 16(%rax)
movl (%rdi), %r12d
.cfi_escape 0x2e, 0x00
callq _ZdlPv
decl -56(%rbp)
movl %r12d, -44(%rbp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq -104(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
.Ltmp4:
# %bb.16: # %_ZL9hipMallocIbE10hipError_tPPT_m.exit
# in Loop: Header=BB1_14 Depth=2
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq -136(%rbp), %rsi # 8-byte Reload
callq hipMalloc
.Ltmp6:
# %bb.17: # %_ZL9hipMallocI4NodeE10hipError_tPPT_m.exit
# in Loop: Header=BB1_14 Depth=2
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq -96(%rbp), %rdi
movq -144(%rbp), %rsi # 8-byte Reload
callq hipMalloc
.Ltmp8:
# %bb.18: # %_ZL9hipMallocIPiE10hipError_tPPT_m.exit
# in Loop: Header=BB1_14 Depth=2
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $8, %esi
leaq -112(%rbp), %rdi
callq hipMalloc
.Ltmp10:
# %bb.19: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
# in Loop: Header=BB1_14 Depth=2
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $8, %esi
leaq -264(%rbp), %rdi
callq hipMalloc
.Ltmp12:
# %bb.20: # %.lr.ph81.preheader
# in Loop: Header=BB1_14 Depth=2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_21: # %.lr.ph81
# Parent Loop BB1_4 Depth=1
# Parent Loop BB1_14 Depth=2
# => This Inner Loop Header: Depth=3
movq -96(%rbp), %rdi
addq %r12, %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
callq hipMalloc
.Ltmp14:
# %bb.22: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit61
# in Loop: Header=BB1_21 Depth=3
addq $8, %r12
cmpq %r12, %r15
jne .LBB1_21
# %bb.23: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit59._crit_edge
# in Loop: Header=BB1_14 Depth=2
movq -104(%rbp), %rdi
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq -88(%rbp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp17:
# %bb.24: # %.preheader67.preheader
# in Loop: Header=BB1_14 Depth=2
leaq -64(%rbp), %rsi
.p2align 4, 0x90
.LBB1_25: # %.preheader67
# Parent Loop BB1_4 Depth=1
# Parent Loop BB1_14 Depth=2
# => This Inner Loop Header: Depth=3
movq -72(%rbp), %rax
movq 8(%rax), %rax
cmpq -64(%rbp), %rax
je .LBB1_26
# %bb.42: # in Loop: Header=BB1_25 Depth=3
leaq 16(%rsi), %r12
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
.Ltmp20:
movq %r12, %rsi
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_26: # in Loop: Header=BB1_14 Depth=2
movq -80(%rbp), %rax # 8-byte Reload
movl %eax, %r12d
.p2align 4, 0x90
.LBB1_27: # %.lr.ph83
# Parent Loop BB1_4 Depth=1
# Parent Loop BB1_14 Depth=2
# => This Inner Loop Header: Depth=3
movq -96(%rbp), %rdi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.28: # in Loop: Header=BB1_27 Depth=3
decl %r12d
jne .LBB1_27
# %bb.29: # %._crit_edge84
# in Loop: Header=BB1_14 Depth=2
movq -112(%rbp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
movl $4, %edx
leaq -44(%rbp), %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp26:
movq -88(%rbp), %r12 # 8-byte Reload
# %bb.30: # in Loop: Header=BB1_14 Depth=2
.Ltmp27:
.cfi_escape 0x2e, 0x00
movabsq $4294967360, %rdi # imm = 0x100000040
movl $1, %esi
movq -128(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp28:
# %bb.31: # in Loop: Header=BB1_14 Depth=2
testl %eax, %eax
jne .LBB1_34
# %bb.32: # in Loop: Header=BB1_14 Depth=2
movq -104(%rbp), %rax
movq -96(%rbp), %rcx
movq -112(%rbp), %rdx
movq %rax, -216(%rbp)
movq %rcx, -208(%rbp)
movq %rdx, -200(%rbp)
leaq -216(%rbp), %rax
movq %rax, -256(%rbp)
leaq -208(%rbp), %rax
movq %rax, -248(%rbp)
leaq -272(%rbp), %rax
movq %rax, -240(%rbp)
leaq -200(%rbp), %rax
movq %rax, -232(%rbp)
.Ltmp29:
.cfi_escape 0x2e, 0x00
leaq -192(%rbp), %rdi
leaq -176(%rbp), %rsi
leaq -160(%rbp), %rdx
leaq -152(%rbp), %rcx
callq __hipPopCallConfiguration
.Ltmp30:
# %bb.33: # %.noexc62
# in Loop: Header=BB1_14 Depth=2
movq -192(%rbp), %rsi
movl -184(%rbp), %edx
movq -176(%rbp), %rcx
movl -168(%rbp), %r8d
.Ltmp31:
.cfi_escape 0x2e, 0x10
movl $_Z14cudaComputeBFSPbPPiP4ListS0_, %edi
leaq -256(%rbp), %r9
pushq -152(%rbp)
pushq -160(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.Ltmp32:
.LBB1_34: # in Loop: Header=BB1_14 Depth=2
movq -104(%rbp), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp34:
# %bb.35: # in Loop: Header=BB1_14 Depth=2
.Ltmp35:
.cfi_escape 0x2e, 0x00
leaq -72(%rbp), %rdi
movq -120(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.36: # in Loop: Header=BB1_14 Depth=2
movq -104(%rbp), %rdi
.Ltmp37:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp38:
# %bb.37: # in Loop: Header=BB1_14 Depth=2
movq -96(%rbp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp40:
# %bb.38: # in Loop: Header=BB1_14 Depth=2
movq -112(%rbp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp42:
# %bb.39: # in Loop: Header=BB1_14 Depth=2
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
jmp .LBB1_14
.LBB1_9: # %._crit_edge92
movq -72(%rbp), %rdi
testq %rdi, %rdi
je .LBB1_11
# %bb.10:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_11: # %_ZN4ListD2Ev.exit
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_46:
.cfi_def_cfa %rbp, 16
.Ltmp2:
jmp .LBB1_47
.LBB1_40:
.Ltmp18:
jmp .LBB1_47
.LBB1_44: # %.loopexit.split-lp
.Ltmp45:
jmp .LBB1_47
.LBB1_43: # %.loopexit
.Ltmp21:
jmp .LBB1_47
.LBB1_45:
.Ltmp24:
jmp .LBB1_47
.LBB1_41:
.Ltmp15:
.LBB1_47:
movq %rax, %rbx
movq -72(%rbp), %rdi
testq %rdi, %rdi
je .LBB1_49
# %bb.48:
.cfi_escape 0x2e, 0x00
callq _ZdaPv
.LBB1_49: # %_ZN4ListD2Ev.exit64
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z7cudaBFS5Graph, .Lfunc_end1-_Z7cudaBFS5Graph
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp23-.Ltmp22 # Call between .Ltmp22 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp44-.Ltmp25 # Call between .Ltmp25 and .Ltmp44
.uleb128 .Ltmp45-.Lfunc_begin0 # jumps to .Ltmp45
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp44 # Call between .Ltmp44 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %r14
movq %r14, 32(%rsp)
movabsq $5144631890299072302, %rax # imm = 0x47656772616C2F2E
movq %rax, 48(%rsp)
movl $1954051118, 56(%rsp) # imm = 0x7478742E
movq $12, 40(%rsp)
movb $0, 60(%rsp)
.Ltmp46:
leaq 64(%rsp), %rdi
leaq 32(%rsp), %rsi
callq _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp47:
# %bb.1:
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_3
# %bb.2: # %.critedge.i.i
callq _ZdlPv
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq %rsp, %r14
movq %r14, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rcx
movq 8(%rsp), %rax
subq 16(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 24(%rsp), %rax
movabsq $2361183241434822607, %r15 # imm = 0x20C49BA5E353F7CF
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rcx
movq 8(%rsp), %rax
subq 16(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 24(%rsp), %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rcx
movq 8(%rsp), %rax
subq 16(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 24(%rsp), %rax
imulq %r15
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 112
.Ltmp48:
movq %rax, %rbx
movq 32(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_6
# %bb.5: # %.critedge.i.i8
callq _ZdlPv
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit10
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp46-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin1 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Lfunc_end2-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 592
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq %rdi, %rbx
leaq 16(%rsp), %r15
movq %r15, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 32(%rsp), %r14
movq (%r12), %rsi
.Ltmp49:
movq %r14, %rdi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp50:
# %bb.1: # %.noexc
movq 16(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB3_3
# %bb.2:
movl 32(%r15), %esi
orl $4, %esi
.LBB3_3: # %.invoke
.Ltmp51:
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp52:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode.exit
movq 16(%rsp), %rax
movq -24(%rax), %rax
testb $5, 48(%rsp,%rax)
jne .LBB3_5
# %bb.7:
leaq 8(%rbx), %r15
.Ltmp53:
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp54:
# %bb.8:
.Ltmp56:
leaq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
callq _ZNSirsERi
.Ltmp57:
# %bb.9:
movslq (%r15), %r13
leaq (,%r13,8), %rax
testq %r13, %r13
movq $-1, %rdi
cmovnsq %rax, %rdi
.Ltmp58:
callq _Znam
.Ltmp59:
# %bb.10:
movq %rax, (%rbx)
testl %r13d, %r13d
jle .LBB3_14
# %bb.11: # %.lr.ph
leaq (,%r13,4), %r12
movl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_12: # =>This Inner Loop Header: Depth=1
.Ltmp61:
movq %r12, %rdi
callq _Znam
.Ltmp62:
# %bb.13: # in Loop: Header=BB3_12 Depth=1
movq (%rbx), %rcx
movq %rax, (%rcx,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB3_12
.LBB3_14: # %.preheader27
cmpl $0, (%r15)
jle .LBB3_20
# %bb.15: # %.preheader.lr.ph
movq (%rbx), %rax
xorl %ecx, %ecx
jmp .LBB3_16
.p2align 4, 0x90
.LBB3_19: # %._crit_edge
# in Loop: Header=BB3_16 Depth=1
incq %rcx
movslq (%r15), %rdx
cmpq %rdx, %rcx
jge .LBB3_20
.LBB3_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
cmpl $0, (%r15)
jle .LBB3_19
# %bb.17: # %.lr.ph30
# in Loop: Header=BB3_16 Depth=1
movq (%rax,%rcx,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_18: # Parent Loop BB3_16 Depth=1
# => This Inner Loop Header: Depth=2
movl $-1, (%rdx,%rsi,4)
incq %rsi
movslq (%r15), %rdi
cmpq %rdi, %rsi
jl .LBB3_18
jmp .LBB3_19
.LBB3_20: # %._crit_edge32
movq 16(%rsp), %rax
movq -24(%rax), %rax
testb $2, 48(%rsp,%rax)
jne .LBB3_25
# %bb.21:
leaq 16(%rsp), %r15
leaq 8(%rsp), %r12
leaq 4(%rsp), %r13
.p2align 4, 0x90
.LBB3_22: # %.lr.ph36
# =>This Inner Loop Header: Depth=1
.Ltmp64:
movq %r15, %rdi
movq %r12, %rsi
callq _ZNSirsERi
.Ltmp65:
# %bb.23: # in Loop: Header=BB3_22 Depth=1
.Ltmp66:
movq %rax, %rdi
movq %r13, %rsi
callq _ZNSirsERi
.Ltmp67:
# %bb.24: # in Loop: Header=BB3_22 Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movq (%rbx), %rcx
movslq 8(%rsp), %rdx
movq (%rcx,%rdx,8), %rdx
movslq 4(%rsp), %rsi
movl %eax, (%rdx,%rsi,4)
movslq 4(%rsp), %rdx
movq (%rcx,%rdx,8), %rcx
movslq 8(%rsp), %rdx
movl %eax, (%rcx,%rdx,4)
movq 16(%rsp), %rax
movq -24(%rax), %rax
testb $2, 48(%rsp,%rax)
je .LBB3_22
.LBB3_25: # %._crit_edge37
.Ltmp69:
movq %r14, %rdi
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp70:
# %bb.26: # %.noexc24
testq %rax, %rax
jne .LBB3_28
# %bb.27:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $16, %rdi
movl 48(%rsp,%rax), %esi
orl $4, %esi
.Ltmp71:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp72:
.LBB3_28: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 16(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 272(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 592
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_30: # %.loopexit.split-lp
.Ltmp73:
jmp .LBB3_32
.LBB3_31:
.Ltmp60:
jmp .LBB3_32
.LBB3_6:
.Ltmp55:
jmp .LBB3_32
.LBB3_33:
.Ltmp63:
jmp .LBB3_32
.LBB3_29: # %.loopexit
.Ltmp68:
.LBB3_32:
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 272(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end3-_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table._ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"aG",@progbits,_ZN5GraphC2ENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp49-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp49
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp54-.Ltmp49 # Call between .Ltmp49 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin2 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp56-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp59-.Ltmp56 # Call between .Ltmp56 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin2 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp62-.Ltmp61 # Call between .Ltmp61 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin2 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp67-.Ltmp64 # Call between .Ltmp64 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin2 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Ltmp72-.Ltmp69 # Call between .Ltmp69 and .Ltmp72
.uleb128 .Ltmp73-.Lfunc_begin2 # jumps to .Ltmp73
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin2 # >> Call Site 7 <<
.uleb128 .Lfunc_end3-.Ltmp72 # Call between .Ltmp72 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14cudaComputeBFSPbPPiP4ListS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type Node,@object # @Node
.bss
.globl Node
.p2align 3, 0x0
Node:
.zero 24
.size Node, 24
.type _Z14cudaComputeBFSPbPPiP4ListS0_,@object # @_Z14cudaComputeBFSPbPPiP4ListS0_
.section .rodata,"a",@progbits
.globl _Z14cudaComputeBFSPbPPiP4ListS0_
.p2align 3, 0x0
_Z14cudaComputeBFSPbPPiP4ListS0_:
.quad _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_
.size _Z14cudaComputeBFSPbPPiP4ListS0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "visit node %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "./largeG.txt"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU looped version is finished in time %ld ms\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU recursive version is finished in time %ld ms\n"
.size .L.str.3, 50
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU version is finished in time %ld ms\n"
.size .L.str.4, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14cudaComputeBFSPbPPiP4ListS0_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Unable to open file!"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__cudaComputeBFSPbPPiP4ListS0_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z14cudaComputeBFSPbPPiP4ListS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} | code for sm_80
Function : _Z13fupdate_dummyPfS_S_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x188], PT ; /* 0x0000620009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x184], P0 ; /* 0x0000610000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R8, R9, c[0x0][0x184], R0 ; /* 0x0000610009087a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fcc00078e020b */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R8, R11, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R6, R8, R11, c[0x0][0x178] ; /* 0x00005e0008067625 */
/* 0x000fe400078e020b */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f22000c1e1900 */
/*0130*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe40000000800 */
/*0140*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*0150*/ ULDC UR4, c[0x0][0x184] ; /* 0x0000610000047ab9 */
/* 0x000fc40000000800 */
/*0160*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0170*/ ISETP.NE.AND P1, PT, R9, UR5, PT ; /* 0x0000000509007c0c */
/* 0x000fc8000bf25270 */
/*0180*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*0190*/ FADD R9, RZ, R2 ; /* 0x00000002ff097221 */
/* 0x004fe40000000000 */
/*01a0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc600078e020b */
/*01b0*/ FSEL R9, R9, RZ, P0 ; /* 0x000000ff09097208 */
/* 0x000fca0000000000 */
/*01c0*/ @P1 FADD R9, R9, R4 ; /* 0x0000000409091221 */
/* 0x008fc80000000000 */
/*01d0*/ FFMA R9, -R6, c[0x0][0x180], R9 ; /* 0x0000600006097a23 */
/* 0x010fca0000000109 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} | .file "tmpxft_00046a7b_00000000-6_fupdate_dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
.type _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii, @function
_Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13fupdate_dummyPfS_S_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii, .-_Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
.globl _Z13fupdate_dummyPfS_S_S_fii
.type _Z13fupdate_dummyPfS_S_S_fii, @function
_Z13fupdate_dummyPfS_S_S_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13fupdate_dummyPfS_S_S_fii, .-_Z13fupdate_dummyPfS_S_S_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13fupdate_dummyPfS_S_S_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13fupdate_dummyPfS_S_S_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13fupdate_dummyPfS_S_S_fii
.globl _Z13fupdate_dummyPfS_S_S_fii
.p2align 8
.type _Z13fupdate_dummyPfS_S_S_fii,@function
_Z13fupdate_dummyPfS_S_S_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v0, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v3
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, 0, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
s_add_i32 s2, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v0
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cndmask_b32_e32 v0, 0x80000000, v4, vcc_lo
v_add_f32_e32 v0, v0, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, -v5, s4, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13fupdate_dummyPfS_S_S_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13fupdate_dummyPfS_S_S_fii, .Lfunc_end0-_Z13fupdate_dummyPfS_S_S_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13fupdate_dummyPfS_S_S_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13fupdate_dummyPfS_S_S_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fupdate_dummy(float *f, float *z1, float *z2, float *g, float invlambda, int nx, int ny)
{
int px = blockIdx.x * blockDim.x + threadIdx.x;
int py = blockIdx.y * blockDim.y + threadIdx.y;
int idx = px + py*nx;
float DIVZ;
if (px<nx && py<ny)
{
// compute the divergence
DIVZ = 0;
float Z1c = z1[(idx)];
float Z2c = z2[(idx)];
// float Z1l=z1[(idx-1 )];
// float Z2d=z2[(idx-nx)];
if (!(px == (nx - 1))) DIVZ += Z1c;
// if (!(px==0)) DIVZ -= Z1l;
if (!(py == (ny - 1))) DIVZ += Z2c;
// if (!(py==0)) DIVZ -= Z2d;
// update f
f[idx] = DIVZ - g[idx] * invlambda;
}
} | .text
.file "fupdate_dummy.hip"
.globl _Z28__device_stub__fupdate_dummyPfS_S_S_fii # -- Begin function _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.p2align 4, 0x90
.type _Z28__device_stub__fupdate_dummyPfS_S_S_fii,@function
_Z28__device_stub__fupdate_dummyPfS_S_S_fii: # @_Z28__device_stub__fupdate_dummyPfS_S_S_fii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13fupdate_dummyPfS_S_S_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__fupdate_dummyPfS_S_S_fii, .Lfunc_end0-_Z28__device_stub__fupdate_dummyPfS_S_S_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13fupdate_dummyPfS_S_S_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13fupdate_dummyPfS_S_S_fii,@object # @_Z13fupdate_dummyPfS_S_S_fii
.section .rodata,"a",@progbits
.globl _Z13fupdate_dummyPfS_S_S_fii
.p2align 3, 0x0
_Z13fupdate_dummyPfS_S_S_fii:
.quad _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.size _Z13fupdate_dummyPfS_S_S_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13fupdate_dummyPfS_S_S_fii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13fupdate_dummyPfS_S_S_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13fupdate_dummyPfS_S_S_fii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x188], PT ; /* 0x0000620009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x184], P0 ; /* 0x0000610000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R8, R9, c[0x0][0x184], R0 ; /* 0x0000610009087a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fcc00078e020b */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R4, R8, R11, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R6, R8, R11, c[0x0][0x178] ; /* 0x00005e0008067625 */
/* 0x000fe400078e020b */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000f22000c1e1900 */
/*0130*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe40000000800 */
/*0140*/ UIADD3 UR5, UR5, -0x1, URZ ; /* 0xffffffff05057890 */
/* 0x000fe4000fffe03f */
/*0150*/ ULDC UR4, c[0x0][0x184] ; /* 0x0000610000047ab9 */
/* 0x000fc40000000800 */
/*0160*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0170*/ ISETP.NE.AND P1, PT, R9, UR5, PT ; /* 0x0000000509007c0c */
/* 0x000fc8000bf25270 */
/*0180*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*0190*/ FADD R9, RZ, R2 ; /* 0x00000002ff097221 */
/* 0x004fe40000000000 */
/*01a0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc600078e020b */
/*01b0*/ FSEL R9, R9, RZ, P0 ; /* 0x000000ff09097208 */
/* 0x000fca0000000000 */
/*01c0*/ @P1 FADD R9, R9, R4 ; /* 0x0000000409091221 */
/* 0x008fc80000000000 */
/*01d0*/ FFMA R9, -R6, c[0x0][0x180], R9 ; /* 0x0000600006097a23 */
/* 0x010fca0000000109 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13fupdate_dummyPfS_S_S_fii
.globl _Z13fupdate_dummyPfS_S_S_fii
.p2align 8
.type _Z13fupdate_dummyPfS_S_S_fii,@function
_Z13fupdate_dummyPfS_S_S_fii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v0, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v3
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, 0, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v2, vcc_lo
s_add_i32 s2, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v0
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
v_cndmask_b32_e32 v0, 0x80000000, v4, vcc_lo
v_add_f32_e32 v0, v0, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v3, -v5, s4, v0
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13fupdate_dummyPfS_S_S_fii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13fupdate_dummyPfS_S_S_fii, .Lfunc_end0-_Z13fupdate_dummyPfS_S_S_fii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13fupdate_dummyPfS_S_S_fii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13fupdate_dummyPfS_S_S_fii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00046a7b_00000000-6_fupdate_dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
.type _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii, @function
_Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13fupdate_dummyPfS_S_S_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii, .-_Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
.globl _Z13fupdate_dummyPfS_S_S_fii
.type _Z13fupdate_dummyPfS_S_S_fii, @function
_Z13fupdate_dummyPfS_S_S_fii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z13fupdate_dummyPfS_S_S_fiiPfS_S_S_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13fupdate_dummyPfS_S_S_fii, .-_Z13fupdate_dummyPfS_S_S_fii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13fupdate_dummyPfS_S_S_fii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13fupdate_dummyPfS_S_S_fii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fupdate_dummy.hip"
.globl _Z28__device_stub__fupdate_dummyPfS_S_S_fii # -- Begin function _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.p2align 4, 0x90
.type _Z28__device_stub__fupdate_dummyPfS_S_S_fii,@function
_Z28__device_stub__fupdate_dummyPfS_S_S_fii: # @_Z28__device_stub__fupdate_dummyPfS_S_S_fii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13fupdate_dummyPfS_S_S_fii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__fupdate_dummyPfS_S_S_fii, .Lfunc_end0-_Z28__device_stub__fupdate_dummyPfS_S_S_fii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13fupdate_dummyPfS_S_S_fii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13fupdate_dummyPfS_S_S_fii,@object # @_Z13fupdate_dummyPfS_S_S_fii
.section .rodata,"a",@progbits
.globl _Z13fupdate_dummyPfS_S_S_fii
.p2align 3, 0x0
_Z13fupdate_dummyPfS_S_S_fii:
.quad _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.size _Z13fupdate_dummyPfS_S_S_fii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13fupdate_dummyPfS_S_S_fii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__fupdate_dummyPfS_S_S_fii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13fupdate_dummyPfS_S_S_fii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const cudaDeviceProp &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
cudaDeviceProp prop;
int status;
status = cudaGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == cudaSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
cudaSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
cudaMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
cudaMalloc((void**)&cuda_e, sizeof(int));
cudaMalloc((void**)&time, sizeof(clock_t) * n * 2);
cudaMemcpy(cuda_a, a, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b, b, sizeof(float) * n * n, cudaMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
cudaMemcpy(c, cuda_c, sizeof(float) * n * n, cudaMemcpyDeviceToHost);
cudaMemcpy(e, cuda_e, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, cudaMemcpyDeviceToHost);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} | code for sm_80
Function : _Z11matMultCUDAPKfS0_PfiPlPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P2, PT, R7.reuse, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x041fe40003f46270 */
/*0060*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f25270 */
/*0070*/ @!P1 MOV R11, c[0x0][0x0] ; /* 0x00000000000b9a02 */
/* 0x000fe40000000f00 */
/*0080*/ @!P1 MOV R4, c[0x0][0x188] ; /* 0x0000620000049a02 */
/* 0x000fe40000000f00 */
/*0090*/ @!P1 MOV R5, c[0x0][0x18c] ; /* 0x0000630000059a02 */
/* 0x000fe20000000f00 */
/*00a0*/ @P2 BRA 0x140 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x002fc80000000f00 */
/*00c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R2, R0, c[0x0][0x178], R9 ; /* 0x00005e0000027a24 */
/* 0x000fd200078e0209 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0100*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0041e40000004800 */
/*0110*/ IADD3 R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a10 */
/* 0x001fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fda0003f06270 */
/*0130*/ @!P0 BRA 0xc0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P1 STG.E [R4.64], R11 ; /* 0x0000000b04009986 */
/* 0x0001e4000c101904 */
/*0170*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fe40000015000 */
/*0180*/ MOV R17, 0x8 ; /* 0x0000000800117802 */
/* 0x000fe20000000f00 */
/*0190*/ BSSY B0, 0x1300 ; /* 0x0000116000007945 */
/* 0x000fe80003800000 */
/*01a0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x180] ; /* 0x0000600000107625 */
/* 0x000fca00078e0211 */
/*01b0*/ STG.E.64 [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x0003e2000c101b04 */
/*01c0*/ @P2 BRA 0x12f0 ; /* 0x0000112000002947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fda0003f01270 */
/*01e0*/ @P0 BRA 0x270 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*01f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fcc00000001ff */
/*0200*/ IMAD R2, R0, c[0x0][0x178], R7 ; /* 0x00005e0000027a24 */
/* 0x003fe200078e0207 */
/*0210*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x000fc60007ffe0ff */
/*0220*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0205 */
/*0230*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*0240*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101904 */
/*0250*/ @!P0 BRA 0x200 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0260*/ BRA 0x12f0 ; /* 0x0000108000007947 */
/* 0x000fea0003800000 */
/*0270*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x002fc80000000f00 */
/*0280*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*0290*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*02a0*/ ISETP.GE.U32.AND P2, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f46070 */
/*02b0*/ IADD3 R3, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002037a10 */
/* 0x000fd00007ffe1ff */
/*02c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*02d0*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*02e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*02f0*/ @!P2 BRA 0x10b0 ; /* 0x00000db00000a947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f04270 */
/*0310*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fc40000000f00 */
/*0320*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe40000000f00 */
/*0330*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fce0000000f00 */
/*0340*/ @!P0 BRA 0xea0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.GT.AND P3, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f64270 */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0370*/ @!P3 BRA 0xab0 ; /* 0x000007300000b947 */
/* 0x000fea0003800000 */
/*0380*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0390*/ HFMA2.MMA R20, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff147435 */
/* 0x000fe200000001ff */
/*03a0*/ IMAD R9, R4, c[0x0][0x178], R7 ; /* 0x00005e0004097a24 */
/* 0x000fd200078e0207 */
/*03b0*/ IMAD.WIDE R8, R9, R20, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fca00078e0214 */
/*03c0*/ LDG.E R27, [R8.64] ; /* 0x00000004081b7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ MOV R14, c[0x0][0x178] ; /* 0x00005e00000e7a02 */
/* 0x000fca0000000f00 */
/*03e0*/ IMAD.WIDE R10, R14, 0x4, R8 ; /* 0x000000040e0a7825 */
/* 0x000fca00078e0208 */
/*03f0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x0000e2000c1e1900 */
/*0400*/ IMAD.WIDE R28, R14, 0x4, R10 ; /* 0x000000040e1c7825 */
/* 0x000fca00078e020a */
/*0410*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000322000c1e1900 */
/*0420*/ IMAD.WIDE R24, R14, 0x4, R28 ; /* 0x000000040e187825 */
/* 0x000fca00078e021c */
/*0430*/ LDG.E R26, [R24.64] ; /* 0x00000004181a7981 */
/* 0x000b22000c1e1900 */
/*0440*/ IADD3 R12, R4, 0x4, RZ ; /* 0x00000004040c7810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD R15, R12, c[0x0][0x178], R7 ; /* 0x00005e000c0f7a24 */
/* 0x000fc800078e0207 */
/*0460*/ IMAD.WIDE R24, R15, R20, c[0x0][0x168] ; /* 0x00005a000f187625 */
/* 0x020fca00078e0214 */
/*0470*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x000b22000c1e1900 */
/*0480*/ IMAD.WIDE R28, R14, 0x4, R24 ; /* 0x000000040e1c7825 */
/* 0x002fca00078e0218 */
/*0490*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x000322000c1e1900 */
/*04a0*/ SHF.L.U32 R18, R4, 0x2, RZ ; /* 0x0000000204127819 */
/* 0x000fca00000006ff */
/*04b0*/ LDS.128 R8, [R18] ; /* 0x0000000012087984 */
/* 0x001ea20000000c00 */
/*04c0*/ IMAD.WIDE R28, R14, 0x4, R28 ; /* 0x000000040e1c7825 */
/* 0x002fca00078e021c */
/*04d0*/ LDG.E R15, [R28.64] ; /* 0x000000041c0f7981 */
/* 0x000122000c1e1900 */
/*04e0*/ IMAD.WIDE R24, R14, 0x4, R28 ; /* 0x000000040e187825 */
/* 0x020fca00078e021c */
/*04f0*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000362000c1e1900 */
/*0500*/ FFMA R27, -R8, R27, R13 ; /* 0x0000001b081b7223 */
/* 0x004fc8000000010d */
/*0510*/ FADD R8, -R27, R6 ; /* 0x000000061b087221 */
/* 0x000fc80000000100 */
/*0520*/ FADD R6, R8, -R6 ; /* 0x8000000608067221 */
/* 0x000fc80000000000 */
/*0530*/ FADD R6, R27, R6 ; /* 0x000000061b067221 */
/* 0x000fc80000000000 */
/*0540*/ FFMA R23, -R9, R23, R6 ; /* 0x0000001709177223 */
/* 0x008fe20000000106 */
/*0550*/ IADD3 R6, R4, 0x8, RZ ; /* 0x0000000804067810 */
/* 0x000fc60007ffe0ff */
/*0560*/ FADD R9, R8, -R23 ; /* 0x8000001708097221 */
/* 0x000fe40000000000 */
/*0570*/ IMAD R13, R6, c[0x0][0x178], R7 ; /* 0x00005e00060d7a24 */
/* 0x000fe400078e0207 */
/*0580*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x000fe40000000100 */
/*0590*/ IMAD.WIDE R28, R13, R20, c[0x0][0x168] ; /* 0x00005a000d1c7625 */
/* 0x001fc800078e0214 */
/*05a0*/ FADD R8, R23, R8 ; /* 0x0000000817087221 */
/* 0x000fe20000000000 */
/*05b0*/ LDG.E R13, [R28.64] ; /* 0x000000041c0d7981 */
/* 0x0000a6000c1e1900 */
/*05c0*/ FFMA R8, -R10, R19, R8 ; /* 0x000000130a087223 */
/* 0x010fc80000000108 */
/*05d0*/ FADD R6, R9, -R8 ; /* 0x8000000809067221 */
/* 0x000fe40000000000 */
/*05e0*/ IMAD.WIDE R28, R14, 0x4, R28 ; /* 0x000000040e1c7825 */
/* 0x001fc800078e021c */
/*05f0*/ FADD R9, -R9, R6 ; /* 0x0000000609097221 */
/* 0x000fe20000000100 */
/*0600*/ LDG.E R24, [R28.64] ; /* 0x000000041c187981 */
/* 0x0020e6000c1e1900 */
/*0610*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*0620*/ FFMA R25, -R11, R26, R9 ; /* 0x0000001a0b197223 */
/* 0x000fe40000000109 */
/*0630*/ LDS.128 R8, [R18+0x10] ; /* 0x0000100012087984 */
/* 0x000e620000000c00 */
/*0640*/ IMAD.WIDE R26, R14, 0x4, R28 ; /* 0x000000040e1a7825 */
/* 0x000fca00078e021c */
/*0650*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0008e2000c1e1900 */
/*0660*/ FADD R23, R6, -R25 ; /* 0x8000001906177221 */
/* 0x000fc80000000000 */
/*0670*/ FADD R6, -R6, R23 ; /* 0x0000001706067221 */
/* 0x000fe40000000100 */
/*0680*/ IMAD.WIDE R26, R14, 0x4, R26 ; /* 0x000000040e1a7825 */
/* 0x010fe200078e021a */
/*0690*/ IADD3 R28, R4, 0xc, RZ ; /* 0x0000000c041c7810 */
/* 0x001fc60007ffe0ff */
/*06a0*/ FADD R25, R25, R6 ; /* 0x0000000619197221 */
/* 0x000fe40000000000 */
/*06b0*/ LDG.E R6, [R26.64] ; /* 0x000000041a067981 */
/* 0x000122000c1e1900 */
/*06c0*/ IMAD R29, R28, c[0x0][0x178], R7 ; /* 0x00005e001c1d7a24 */
/* 0x000fc800078e0207 */
/*06d0*/ IMAD.WIDE R28, R29, R20, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fc800078e0214 */
/*06e0*/ FFMA R20, -R8, R21, R25 ; /* 0x0000001508147223 */
/* 0x002fe40000000119 */
/*06f0*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x000324000c1e1900 */
/*0700*/ FADD R8, R23, -R20 ; /* 0x8000001417087221 */
/* 0x000fc80000000000 */
/*0710*/ FADD R23, -R23, R8 ; /* 0x0000000817177221 */
/* 0x000fe40000000100 */
/*0720*/ IMAD.WIDE R28, R14, 0x4, R28 ; /* 0x000000040e1c7825 */
/* 0x002fc800078e021c */
/*0730*/ FADD R23, R20, R23 ; /* 0x0000001714177221 */
/* 0x000fe40000000000 */
/*0740*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000f22000c1e1900 */
/*0750*/ IMAD.WIDE R26, R14, 0x4, R28 ; /* 0x000000040e1a7825 */
/* 0x001fc800078e021c */
/*0760*/ FFMA R9, -R9, R22, R23 ; /* 0x0000001609097223 */
/* 0x000fe40000000117 */
/*0770*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x000124000c1e1900 */
/*0780*/ IMAD.WIDE R26, R14, 0x4, R26 ; /* 0x000000040e1a7825 */
/* 0x001fca00078e021a */
/*0790*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x000f22000c1e1900 */
/*07a0*/ FADD R25, R8, -R9 ; /* 0x8000000908197221 */
/* 0x000fc80000000000 */
/*07b0*/ FADD R8, -R8, R25 ; /* 0x0000001908087221 */
/* 0x000fc80000000100 */
/*07c0*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x000fc80000000000 */
/*07d0*/ FFMA R8, -R10, R15, R8 ; /* 0x0000000f0a087223 */
/* 0x000fc80000000108 */
/*07e0*/ FADD R14, R25, -R8 ; /* 0x80000008190e7221 */
/* 0x000fc80000000000 */
/*07f0*/ FADD R25, -R25, R14 ; /* 0x0000000e19197221 */
/* 0x000fc80000000100 */
/*0800*/ FADD R25, R8, R25 ; /* 0x0000001908197221 */
/* 0x000fc80000000000 */
/*0810*/ FFMA R25, -R11, R12, R25 ; /* 0x0000000c0b197223 */
/* 0x020fe40000000119 */
/*0820*/ LDS.128 R8, [R18+0x20] ; /* 0x0000200012087984 */
/* 0x000ea40000000c00 */
/*0830*/ FADD R15, R14, -R25 ; /* 0x800000190e0f7221 */
/* 0x000fc80000000000 */
/*0840*/ FADD R14, -R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x000fc80000000100 */
/*0850*/ FADD R14, R25, R14 ; /* 0x0000000e190e7221 */
/* 0x000fe20000000000 */
/*0860*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0870*/ ISETP.GT.AND P3, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f64270 */
/*0880*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0890*/ FFMA R14, -R8, R13, R14 ; /* 0x0000000d080e7223 */
/* 0x004fc8000000010e */
/*08a0*/ FADD R8, R15, -R14 ; /* 0x8000000e0f087221 */
/* 0x000fc80000000000 */
/*08b0*/ FADD R15, -R15, R8 ; /* 0x000000080f0f7221 */
/* 0x000fc80000000100 */
/*08c0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*08d0*/ FFMA R9, -R9, R24, R15 ; /* 0x0000001809097223 */
/* 0x008fe4000000010f */
/*08e0*/ LDS.128 R12, [R18+0x30] ; /* 0x00003000120c7984 */
/* 0x000e240000000c00 */
/*08f0*/ FADD R25, R8, -R9 ; /* 0x8000000908197221 */
/* 0x000fc80000000000 */
/*0900*/ FADD R8, -R8, R25 ; /* 0x0000001908087221 */
/* 0x000fc80000000100 */
/*0910*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x000fc80000000000 */
/*0920*/ FFMA R8, -R10, R19, R8 ; /* 0x000000130a087223 */
/* 0x000fc80000000108 */
/*0930*/ FADD R10, R25, -R8 ; /* 0x80000008190a7221 */
/* 0x000fc80000000000 */
/*0940*/ FADD R25, -R25, R10 ; /* 0x0000000a19197221 */
/* 0x000fc80000000100 */
/*0950*/ FADD R25, R8, R25 ; /* 0x0000001908197221 */
/* 0x000fc80000000000 */
/*0960*/ FFMA R11, -R11, R6, R25 ; /* 0x000000060b0b7223 */
/* 0x010fc80000000119 */
/*0970*/ FADD R9, R10, -R11 ; /* 0x8000000b0a097221 */
/* 0x000fc80000000000 */
/*0980*/ FADD R10, -R10, R9 ; /* 0x000000090a0a7221 */
/* 0x000fc80000000100 */
/*0990*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x000fc80000000000 */
/*09a0*/ FFMA R10, -R12, R21, R10 ; /* 0x000000150c0a7223 */
/* 0x001fc8000000010a */
/*09b0*/ FADD R6, R9, -R10 ; /* 0x8000000a09067221 */
/* 0x000fc80000000000 */
/*09c0*/ FADD R9, -R9, R6 ; /* 0x0000000609097221 */
/* 0x000fc80000000100 */
/*09d0*/ FADD R9, R10, R9 ; /* 0x000000090a097221 */
/* 0x000fc80000000000 */
/*09e0*/ FFMA R9, -R13, R20, R9 ; /* 0x000000140d097223 */
/* 0x000fc80000000109 */
/*09f0*/ FADD R11, R6, -R9 ; /* 0x80000009060b7221 */
/* 0x000fc80000000000 */
/*0a00*/ FADD R6, -R6, R11 ; /* 0x0000000b06067221 */
/* 0x000fc80000000100 */
/*0a10*/ FADD R6, R9, R6 ; /* 0x0000000609067221 */
/* 0x000fc80000000000 */
/*0a20*/ FFMA R6, -R14, R23, R6 ; /* 0x000000170e067223 */
/* 0x000fc80000000106 */
/*0a30*/ FADD R8, R11, -R6 ; /* 0x800000060b087221 */
/* 0x000fc80000000000 */
/*0a40*/ FADD R11, -R11, R8 ; /* 0x000000080b0b7221 */
/* 0x000fc80000000100 */
/*0a50*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x000fc80000000000 */
/*0a60*/ FFMA R11, -R15, R22, R11 ; /* 0x000000160f0b7223 */
/* 0x000fc8000000010b */
/*0a70*/ FADD R6, R8, -R11 ; /* 0x8000000b08067221 */
/* 0x000fc80000000000 */
/*0a80*/ FADD R8, -R8, R6 ; /* 0x0000000608087221 */
/* 0x000fc80000000100 */
/*0a90*/ FADD R13, R11, R8 ; /* 0x000000080b0d7221 */
/* 0x000fe20000000000 */
/*0aa0*/ @P3 BRA 0x390 ; /* 0xfffff8e000003947 */
/* 0x000fea000383ffff */
/*0ab0*/ ISETP.GT.AND P3, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f64270 */
/*0ac0*/ @!P3 BRA 0xe80 ; /* 0x000003b00000b947 */
/* 0x000fea0003800000 */
/*0ad0*/ HFMA2.MMA R27, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1b7435 */
/* 0x000fe200000001ff */
/*0ae0*/ IMAD R14, R4, c[0x0][0x178], R7 ; /* 0x00005e00040e7a24 */
/* 0x000fd200078e0207 */
/*0af0*/ IMAD.WIDE R14, R14, R27, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fca00078e021b */
/*0b00*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x0000a2000c1e1900 */
/*0b10*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fca0000000f00 */
/*0b20*/ IMAD.WIDE R22, R25, 0x4, R14 ; /* 0x0000000419167825 */
/* 0x000fca00078e020e */
/*0b30*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0002e2000c1e1900 */
/*0b40*/ IMAD.WIDE R8, R25, 0x4, R22 ; /* 0x0000000419087825 */
/* 0x000fca00078e0216 */
/*0b50*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000962000c1e1900 */
/*0b60*/ IMAD.WIDE R10, R25, 0x4, R8 ; /* 0x00000004190a7825 */
/* 0x000fe200078e0208 */
/*0b70*/ IADD3 R20, R4, 0x4, RZ ; /* 0x0000000404147810 */
/* 0x000fc80007ffe0ff */
/*0b80*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000962000c1e1900 */
/*0b90*/ IMAD R20, R20, c[0x0][0x178], R7 ; /* 0x00005e0014147a24 */
/* 0x000fc800078e0207 */
/*0ba0*/ IMAD.WIDE R26, R20, R27, c[0x0][0x168] ; /* 0x00005a00141a7625 */
/* 0x000fca00078e021b */
/*0bb0*/ LDG.E R21, [R26.64] ; /* 0x000000041a157981 */
/* 0x000562000c1e1900 */
/*0bc0*/ IMAD.WIDE R14, R25, 0x4, R26 ; /* 0x00000004190e7825 */
/* 0x001fca00078e021a */
/*0bd0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000162000c1e1900 */
/*0be0*/ IMAD.WIDE R22, R25, 0x4, R14 ; /* 0x0000000419167825 */
/* 0x002fca00078e020e */
/*0bf0*/ LDG.E R29, [R22.64] ; /* 0x00000004161d7981 */
/* 0x000362000c1e1900 */
/*0c00*/ IMAD.WIDE R24, R25, 0x4, R22 ; /* 0x0000000419187825 */
/* 0x000fcc00078e0216 */
/*0c10*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f62000c1e1900 */
/*0c20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0c30*/ SHF.L.U32 R22, R4.reuse, 0x2, RZ ; /* 0x0000000204167819 */
/* 0x042fe400000006ff */
/*0c40*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe40007ffe0ff */
/*0c50*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ LDS.128 R8, [R22] ; /* 0x0000000016087984 */
/* 0x010ea40000000c00 */
/*0c70*/ FFMA R13, -R8, R12, R13 ; /* 0x0000000c080d7223 */
/* 0x004fc8000000010d */
/*0c80*/ FADD R8, R6, -R13 ; /* 0x8000000d06087221 */
/* 0x000fc80000000000 */
/*0c90*/ FADD R6, -R6, R8 ; /* 0x0000000806067221 */
/* 0x000fc80000000100 */
/*0ca0*/ FADD R6, R13, R6 ; /* 0x000000060d067221 */
/* 0x000fe40000000000 */
/*0cb0*/ LDS.128 R12, [R22+0x10] ; /* 0x00001000160c7984 */
/* 0x001e240000000c00 */
/*0cc0*/ FFMA R9, -R9, R28, R6 ; /* 0x0000001c09097223 */
/* 0x008fc80000000106 */
/*0cd0*/ FADD R27, R8, -R9 ; /* 0x80000009081b7221 */
/* 0x000fc80000000000 */
/*0ce0*/ FADD R8, -R8, R27 ; /* 0x0000001b08087221 */
/* 0x000fc80000000100 */
/*0cf0*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x000fc80000000000 */
/*0d00*/ FFMA R8, -R10, R19, R8 ; /* 0x000000130a087223 */
/* 0x020fc80000000108 */
/*0d10*/ FADD R6, R27, -R8 ; /* 0x800000081b067221 */
/* 0x000fc80000000000 */
/*0d20*/ FADD R27, -R27, R6 ; /* 0x000000061b1b7221 */
/* 0x000fc80000000100 */
/*0d30*/ FADD R27, R8, R27 ; /* 0x0000001b081b7221 */
/* 0x000fc80000000000 */
/*0d40*/ FFMA R11, -R11, R18, R27 ; /* 0x000000120b0b7223 */
/* 0x000fc8000000011b */
/*0d50*/ FADD R9, R6, -R11 ; /* 0x8000000b06097221 */
/* 0x000fc80000000000 */
/*0d60*/ FADD R6, -R6, R9 ; /* 0x0000000906067221 */
/* 0x000fc80000000100 */
/*0d70*/ FADD R6, R11, R6 ; /* 0x000000060b067221 */
/* 0x000fc80000000000 */
/*0d80*/ FFMA R6, -R12, R21, R6 ; /* 0x000000150c067223 */
/* 0x001fc80000000106 */
/*0d90*/ FADD R8, R9, -R6 ; /* 0x8000000609087221 */
/* 0x000fc80000000000 */
/*0da0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fc80000000100 */
/*0db0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x000fc80000000000 */
/*0dc0*/ FFMA R9, -R13, R20, R9 ; /* 0x000000140d097223 */
/* 0x000fc80000000109 */
/*0dd0*/ FADD R11, R8, -R9 ; /* 0x80000009080b7221 */
/* 0x000fc80000000000 */
/*0de0*/ FADD R8, -R8, R11 ; /* 0x0000000b08087221 */
/* 0x000fc80000000100 */
/*0df0*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x000fc80000000000 */
/*0e00*/ FFMA R8, -R14, R29, R8 ; /* 0x0000001d0e087223 */
/* 0x000fc80000000108 */
/*0e10*/ FADD R9, R11, -R8 ; /* 0x800000080b097221 */
/* 0x000fc80000000000 */
/*0e20*/ FADD R11, -R11, R9 ; /* 0x000000090b0b7221 */
/* 0x000fc80000000100 */
/*0e30*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x000fc80000000000 */
/*0e40*/ FFMA R24, -R15, R24, R11 ; /* 0x000000180f187223 */
/* 0x000fc8000000010b */
/*0e50*/ FADD R6, R9, -R24 ; /* 0x8000001809067221 */
/* 0x000fc80000000000 */
/*0e60*/ FADD R9, -R9, R6 ; /* 0x0000000609097221 */
/* 0x000fc80000000100 */
/*0e70*/ FADD R13, R24, R9 ; /* 0x00000009180d7221 */
/* 0x000fe40000000000 */
/*0e80*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0e90*/ @!P0 BRA 0x10b0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*0eb0*/ IMAD R18, R4, c[0x0][0x178], R7 ; /* 0x00005e0004127a24 */
/* 0x000fd200078e0207 */
/*0ec0*/ IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0213 */
/*0ed0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ea2000c1e1900 */
/*0ee0*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fca0000000f00 */
/*0ef0*/ IMAD.WIDE R20, R25, 0x4, R18 ; /* 0x0000000419147825 */
/* 0x000fca00078e0212 */
/*0f00*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ee2000c1e1900 */
/*0f10*/ IMAD.WIDE R22, R25, 0x4, R20 ; /* 0x0000000419167825 */
/* 0x000fca00078e0214 */
/*0f20*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000f22000c1e1900 */
/*0f30*/ IMAD.WIDE R24, R25, 0x4, R22 ; /* 0x0000000419187825 */
/* 0x000fca00078e0216 */
/*0f40*/ LDG.E R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000f62000c1e1900 */
/*0f50*/ SHF.L.U32 R10, R4.reuse, 0x2, RZ ; /* 0x00000002040a7819 */
/* 0x040fe400000006ff */
/*0f60*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe40007ffe0ff */
/*0f70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe40007ffe0ff */
/*0f80*/ LDS.128 R8, [R10] ; /* 0x000000000a087984 */
/* 0x000ea20000000c00 */
/*0f90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0fa0*/ FFMA R13, -R8, R26, R13 ; /* 0x0000001a080d7223 */
/* 0x004fc8000000010d */
/*0fb0*/ FADD R19, -R13, R6 ; /* 0x000000060d137221 */
/* 0x000fc80000000100 */
/*0fc0*/ FADD R6, R19, -R6 ; /* 0x8000000613067221 */
/* 0x000fc80000000000 */
/*0fd0*/ FADD R6, R13, R6 ; /* 0x000000060d067221 */
/* 0x000fc80000000000 */
/*0fe0*/ FFMA R6, -R9, R14, R6 ; /* 0x0000000e09067223 */
/* 0x008fc80000000106 */
/*0ff0*/ FADD R8, R19, -R6 ; /* 0x8000000613087221 */
/* 0x000fc80000000000 */
/*1000*/ FADD R19, -R19, R8 ; /* 0x0000000813137221 */
/* 0x000fc80000000100 */
/*1010*/ FADD R19, R6, R19 ; /* 0x0000001306137221 */
/* 0x000fc80000000000 */
/*1020*/ FFMA R15, -R10, R15, R19 ; /* 0x0000000f0a0f7223 */
/* 0x010fc80000000113 */
/*1030*/ FADD R9, R8, -R15 ; /* 0x8000000f08097221 */
/* 0x000fc80000000000 */
/*1040*/ FADD R8, -R8, R9 ; /* 0x0000000908087221 */
/* 0x000fc80000000100 */
/*1050*/ FADD R8, R15, R8 ; /* 0x000000080f087221 */
/* 0x000fc80000000000 */
/*1060*/ FFMA R8, -R11, R12, R8 ; /* 0x0000000c0b087223 */
/* 0x020fc80000000108 */
/*1070*/ FADD R6, R9, -R8 ; /* 0x8000000809067221 */
/* 0x000fc80000000000 */
/*1080*/ FADD R9, -R9, R6 ; /* 0x0000000609097221 */
/* 0x000fc80000000100 */
/*1090*/ FADD R13, R8, R9 ; /* 0x00000009080d7221 */
/* 0x000fe20000000000 */
/*10a0*/ @P0 BRA 0xea0 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*10b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*10c0*/ @!P0 BRA 0x1270 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*10d0*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*10e0*/ IMAD R5, R4, c[0x0][0x178], R7 ; /* 0x00005e0004057a24 */
/* 0x000fd200078e0207 */
/*10f0*/ IMAD.WIDE R14, R5, R19, c[0x0][0x168] ; /* 0x00005a00050e7625 */
/* 0x000fcc00078e0213 */
/*1100*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*1110*/ SHF.L.U32 R8, R4, 0x2, RZ ; /* 0x0000000204087819 */
/* 0x000fe400000006ff */
/*1120*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05270 */
/*1130*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000ea40000000c00 */
/*1140*/ FFMA R13, R14, -R8, R13 ; /* 0x800000080e0d7223 */
/* 0x004fc8000000000d */
/*1150*/ FADD R11, R6, -R13 ; /* 0x8000000d060b7221 */
/* 0x000fc80000000000 */
/*1160*/ FADD R4, -R6, R11 ; /* 0x0000000b06047221 */
/* 0x000fe20000000100 */
/*1170*/ MOV R6, R11 ; /* 0x0000000b00067202 */
/* 0x000fc60000000f00 */
/*1180*/ FADD R18, R13, R4 ; /* 0x000000040d127221 */
/* 0x000fe20000000000 */
/*1190*/ @!P0 BRA 0x1270 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*11a0*/ IADD3 R12, R5, c[0x0][0x178], RZ ; /* 0x00005e00050c7a10 */
/* 0x000fe40007ffe0ff */
/*11b0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fc60003f05270 */
/*11c0*/ IMAD.WIDE R4, R12, R19, c[0x0][0x168] ; /* 0x00005a000c047625 */
/* 0x000fcc00078e0213 */
/*11d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*11e0*/ @P0 IADD3 R12, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c0a10 */
/* 0x000fca0007ffe0ff */
/*11f0*/ @P0 IMAD.WIDE R12, R12, R19, c[0x0][0x168] ; /* 0x00005a000c0c0625 */
/* 0x000fcc00078e0213 */
/*1200*/ @P0 LDG.E R13, [R12.64] ; /* 0x000000040c0d0981 */
/* 0x000ee2000c1e1900 */
/*1210*/ FFMA R9, R4, -R9, R18 ; /* 0x8000000904097223 */
/* 0x004fc80000000012 */
/*1220*/ FADD R6, R11, -R9 ; /* 0x800000090b067221 */
/* 0x000fc80000000000 */
/*1230*/ FADD R8, -R11, R6 ; /* 0x000000060b087221 */
/* 0x000fc80000000100 */
/*1240*/ FADD R9, R9, R8 ; /* 0x0000000809097221 */
/* 0x000fc80000000000 */
/*1250*/ @P0 FFMA R9, R13, -R10, R9 ; /* 0x8000000a0d090223 */
/* 0x008fc80000000009 */
/*1260*/ @P0 FADD R6, R6, -R9 ; /* 0x8000000906060221 */
/* 0x000fe40000000000 */
/*1270*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*1280*/ IMAD R4, R0, c[0x0][0x178], R7 ; /* 0x00005e0000047a24 */
/* 0x000fe200078e0207 */
/*1290*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x000fc60007ffe0ff */
/*12a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*12b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*12c0*/ STG.E [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001f2000c101904 */
/*12d0*/ @P0 CALL.REL.NOINC 0x12f0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*12e0*/ BRA 0x2c0 ; /* 0xffffefd000007947 */
/* 0x000fea000383ffff */
/*12f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1300*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*1310*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x003fca0000015000 */
/*1320*/ STG.E.64 [R16.64+0x10], R2 ; /* 0x0000100210007986 */
/* 0x000fe2000c101b04 */
/*1330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1340*/ BRA 0x1340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const cudaDeviceProp &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
cudaDeviceProp prop;
int status;
status = cudaGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == cudaSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
cudaSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
cudaMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
cudaMalloc((void**)&cuda_e, sizeof(int));
cudaMalloc((void**)&time, sizeof(clock_t) * n * 2);
cudaMemcpy(cuda_a, a, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b, b, sizeof(float) * n * n, cudaMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
cudaMemcpy(c, cuda_c, sizeof(float) * n * n, cudaMemcpyDeviceToHost);
cudaMemcpy(e, cuda_e, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, cudaMemcpyDeviceToHost);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} | .file "tmpxft_000d347e_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL11matMultCUDAPKfS0_PfiPlPi, @function
_ZL11matMultCUDAPKfS0_PfiPlPi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL11matMultCUDAPKfS0_PfiPlPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL11matMultCUDAPKfS0_PfiPlPi, .-_ZL11matMultCUDAPKfS0_PfiPlPi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Name : %s.\n"
.LC1:
.string "totalFlbalMem : %d.\n"
.LC2:
.string "sharedMemPerBlock : %d.\n"
.LC3:
.string "regsPerBlock : %d.\n"
.LC4:
.string "warpSize : %d.\n"
.LC5:
.string "memPitch : %d.\n"
.LC6:
.string "maxThreadsPerBlock : %d.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "maxThreadsDim[0 - 2] : %d %d %d.\n"
.align 8
.LC8:
.string "maxGridSize[0 - 2] : %d %d %d.\n"
.section .rodata.str1.1
.LC9:
.string "totalConstMem : %d.\n"
.LC10:
.string "major.minor : %d.%d.\n"
.LC11:
.string "clockRate : %d.\n"
.LC12:
.string "textureAlignment : %d.\n"
.LC13:
.string "deviceOverlap : %d.\n"
.LC14:
.string "multiProcessorCount : %d.\n"
.text
.globl _Z15printDevicePropRK14cudaDeviceProp
.type _Z15printDevicePropRK14cudaDeviceProp, @function
_Z15printDevicePropRK14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rbx), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rbx), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rbx), %ecx
movl 336(%rbx), %edx
movl 344(%rbx), %r8d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rbx), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rbx), %ecx
movl 360(%rbx), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rbx), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rbx), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 384(%rbx), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 388(%rbx), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15printDevicePropRK14cudaDeviceProp, .-_Z15printDevicePropRK14cudaDeviceProp
.section .rodata.str1.1
.LC15:
.string "There is no device.\n"
.LC16:
.string "Total %d GPU\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "There is no device supporting cuda 1.x.\n"
.text
.globl _Z8InitCUDAv
.type _Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L24
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L16
jmp .L17
.L24:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %eax
jmp .L11
.L14:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L17
.L16:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L14
cmpl $0, 376(%rsp)
jle .L14
.L17:
movl 12(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, 12(%rsp)
je .L25
leal 1(%rbx), %edi
call cudaSetDevice@PLT
movl $1, %eax
.L11:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L11
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8InitCUDAv, .-_Z8InitCUDAv
.globl _Z6matgenPfi
.type _Z6matgenPfi, @function
_Z6matgenPfi:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L29:
leaq 0(%rbp,%r13), %rbx
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC18(%rip), %xmm0
movss %xmm0, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L29
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2059:
.size _Z6matgenPfi, .-_Z6matgenPfi
.section .rodata.str1.1
.LC21:
.string "sizeof(c)= %d\n"
.LC22:
.string "blockDim.x = %d\n"
.LC23:
.string "%f "
.section .rodata.str1.8
.align 8
.LC26:
.string "Max error: %g Average error: %g\n"
.section .rodata.str1.1
.LC27:
.string "gputime: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
call _Z8InitCUDAv
testb %al, %al
jne .L58
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call srand@PLT
movl $1000, %esi
movq %r12, %rdi
call _Z6matgenPfi
movl $1000, %esi
movq %r13, %rdi
call _Z6matgenPfi
leaq 48(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 64(%rsp), %rsi
leaq 24(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 84(%rsp)
movl $1, 88(%rsp)
movl $1000, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $4000, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L38:
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $8, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%r14), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r14
leaq 40(%rbp), %r15
.L39:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L39
movq 120(%rsp), %rax
movq 112(%rsp), %rdx
cmpq %rdx, %rax
cmovge %rax, %rdx
movq %rdx, %r14
movq 96(%rsp), %rax
movq 104(%rsp), %rdx
cmpq %rdx, %rax
cmovg %rdx, %rax
subq %rax, %r14
movl $0, %r9d
jmp .L40
.L60:
movq 32(%rsp), %r9
movq 40(%rsp), %r8
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL11matMultCUDAPKfS0_PfiPlPi
jmp .L38
.L61:
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $1000, %rsi
je .L42
.L44:
leaq -4000000(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L41:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $4, %rdx
addq $4000, %rax
cmpq %rcx, %rax
jne .L41
jmp .L61
.L42:
addq $1, %r9
cmpq $1000, %r9
je .L51
.L40:
leaq 4000000(%r13), %rcx
imulq $4000, %r9, %rdi
leaq (%r12,%rdi), %r8
addq %rbx, %rdi
movl $0, %esi
jmp .L44
.L53:
movss 0(%rbp,%rax), %xmm0
subss %xmm1, %xmm0
divss %xmm1, %xmm0
andps %xmm5, %xmm0
movaps %xmm0, %xmm6
maxss %xmm3, %xmm6
movaps %xmm6, %xmm3
addss %xmm0, %xmm4
.L45:
addq $4, %rax
cmpq %rax, %rdx
je .L62
.L48:
movss (%rbx,%rax), %xmm1
ucomiss %xmm2, %xmm1
jp .L53
je .L45
jmp .L53
.L62:
addq $4000, %rdx
cmpq $4004000, %rdx
je .L63
.L43:
leaq -4000(%rdx), %rax
jmp .L48
.L51:
movl $4000, %edx
pxor %xmm4, %xmm4
movaps %xmm4, %xmm3
movaps %xmm4, %xmm2
movss .LC24(%rip), %xmm5
jmp .L43
.L63:
divss .LC25(%rip), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm4, %xmm1
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %r14, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L37
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z11matMultCUDAPKfS0_PfiPlPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfS0_PfiPlPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 805306368
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC24:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC25:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const cudaDeviceProp &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
cudaDeviceProp prop;
int status;
status = cudaGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == cudaSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
cudaSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
cudaMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
cudaMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
cudaMalloc((void**)&cuda_e, sizeof(int));
cudaMalloc((void**)&time, sizeof(clock_t) * n * 2);
cudaMemcpy(cuda_a, a, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(cuda_b, b, sizeof(float) * n * n, cudaMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
cudaMemcpy(c, cuda_c, sizeof(float) * n * n, cudaMemcpyDeviceToHost);
cudaMemcpy(e, cuda_e, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, cudaMemcpyDeviceToHost);
cudaFree(cuda_a);
cudaFree(cuda_b);
cudaFree(cuda_c);
cudaFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const hipDeviceProp_t &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
hipDeviceProp_t prop;
int status;
status = hipGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == hipSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
hipSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
hipMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
hipMalloc((void**)&cuda_e, sizeof(int));
hipMalloc((void**)&time, sizeof(clock_t) * n * 2);
hipMemcpy(cuda_a, a, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_b, b, sizeof(float) * n * n, hipMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
hipMemcpy(c, cuda_c, sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(e, cuda_e, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, hipMemcpyDeviceToHost);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const hipDeviceProp_t &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
hipDeviceProp_t prop;
int status;
status = hipGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == hipSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
hipSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
hipMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
hipMalloc((void**)&cuda_e, sizeof(int));
hipMalloc((void**)&time, sizeof(clock_t) * n * 2);
hipMemcpy(cuda_a, a, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_b, b, sizeof(float) * n * n, hipMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
hipMemcpy(c, cuda_c, sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(e, cuda_e, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, hipMemcpyDeviceToHost);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11matMultCUDAPKfS0_PfiPlPi,"axG",@progbits,_ZL11matMultCUDAPKfS0_PfiPlPi,comdat
.globl _ZL11matMultCUDAPKfS0_PfiPlPi
.p2align 8
.type _ZL11matMultCUDAPKfS0_PfiPlPi,@function
_ZL11matMultCUDAPKfS0_PfiPlPi:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s12, s15
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s6, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_add_u32 v1, v0, 2, 0
v_mov_b32_e32 v2, v0
s_mul_i32 s5, s12, s8
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s9, s6, 2
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v3, s5, v2
v_add_nc_u32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v2
global_load_b32 v3, v[3:4], off
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
v_add_nc_u32_e32 v1, s9, v1
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_eq_u32_e64 s2, 0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s6, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
global_store_b32 v1, v2, s[4:5]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[4:5], s[0:1], 0x20
s_getreg_b32 s3, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_ashr_i32 s13, s12, 31
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, 0
s_lshl_b64 s[6:7], s[12:13], 3
v_mov_b32_e32 v3, 0
s_mov_b32 s3, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s4, s6
s_addc_u32 s11, s5, s7
global_store_b64 v3, v[1:2], s[10:11]
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_12
s_clause 0x1
s_load_b32 s13, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x8
s_cmp_gt_i32 s8, 0
s_mul_i32 s1, s12, s8
s_cselect_b32 s15, -1, 0
s_ashr_i32 s9, s8, 31
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s13, 0xffff
s_lshl_b64 s[12:13], s[8:9], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_7:
v_mov_b32_e32 v3, 0
.LBB0_8:
v_add_nc_u32_e32 v1, s1, v0
v_add_nc_u32_e32 v0, s16, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_le_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_or_b32 s3, vcc_lo, s3
v_add_co_u32 v1, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_12
.LBB0_9:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
s_mov_b32 s0, 0
s_mov_b32 s9, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_11:
global_load_b32 v5, v[1:2], off
v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, v3
v_add_co_u32 v1, vcc_lo, v1, s12
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
ds_load_b32 v6, v6
s_add_i32 s9, s9, -1
s_add_i32 s0, s0, 4
s_cmp_lg_u32 s9, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v4, -v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v7, v4
v_sub_f32_e32 v5, v3, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v4, v5
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_14
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[10:11] offset:16
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11matMultCUDAPKfS0_PfiPlPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11matMultCUDAPKfS0_PfiPlPi,"axG",@progbits,_ZL11matMultCUDAPKfS0_PfiPlPi,comdat
.Lfunc_end0:
.size _ZL11matMultCUDAPKfS0_PfiPlPi, .Lfunc_end0-_ZL11matMultCUDAPKfS0_PfiPlPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11matMultCUDAPKfS0_PfiPlPi
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _ZL11matMultCUDAPKfS0_PfiPlPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define THREAD_NUM 512
#define MATRIX_SIZE 1000
const int blocks_num = (MATRIX_SIZE + THREAD_NUM - 1) / THREAD_NUM;
void printDeviceProp(const hipDeviceProp_t &prop)
{
printf("Device Name : %s.\n", prop.name);
printf("totalFlbalMem : %d.\n", prop.totalGlobalMem);
printf("sharedMemPerBlock : %d.\n", prop.regsPerBlock);
printf("regsPerBlock : %d.\n", prop.regsPerBlock);
printf("warpSize : %d.\n", prop.warpSize);
printf("memPitch : %d.\n", prop.memPitch);
printf("maxThreadsPerBlock : %d.\n", prop.maxThreadsPerBlock);
printf("maxThreadsDim[0 - 2] : %d %d %d.\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf("maxGridSize[0 - 2] : %d %d %d.\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
printf("totalConstMem : %d.\n", prop.totalConstMem);
printf("major.minor : %d.%d.\n", prop.major, prop.minor);
printf("clockRate : %d.\n", prop.clockRate);
printf("textureAlignment : %d.\n", prop.textureAlignment);
printf("deviceOverlap : %d.\n", prop.deviceOverlap);
printf("multiProcessorCount : %d.\n", prop.multiProcessorCount);
}
bool InitCUDA()
{
int count;
hipGetDeviceCount(&count);
if(count == 0){
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for(i = 0; i < count; i++)
{
hipDeviceProp_t prop;
int status;
status = hipGetDeviceProperties(&prop, i);
//printDeviceProp(prop);
if(status == hipSuccess){
if(prop.major >= 1){
break;
}
}
}
printf("Total %d GPU\n", count);
if(i == count){
fprintf(stderr, "There is no device supporting cuda 1.x.\n");
return false;
}
hipSetDevice(i+1);
return true;
}
void matgen(float* a, int n)
{
int i, j;
for(i = 0; i < n; i++){
for(j = 0; j < n; j++){
a[i * n + j] = (float)rand() / RAND_MAX + (float)rand() / (RAND_MAX * RAND_MAX);
}
}
}
__global__ static void matMultCUDA(const float* a, const float* b, float* c, int n, clock_t* time, int *e)
{
extern __shared__ float data[];
const int tid = threadIdx.x;
const int row = blockIdx.x;
int i, j;
//for(i = tid; i < n; i += THREAD_NUM){
for(i = tid; i < n; i += blockDim.x){
data[i] = a[row * n + i];
}
__syncthreads();
clock_t start;
if(tid == 0)
*e = blockDim.x;
time[row] = clock();
//for(j = tid; j < n; j += THREAD_NUM){
for(j = tid; j < n; j += blockDim.x){
float t = 0;
float y = 0;
for(i = 0; i < n; i++){
float r ;
y -= data[i] * b[i * n + j];
r = t - y;
y = (r - t) + y;
t = r;
}
c[row * n + j] = t;
}
if(tid == 0){
time[row + blocks_num] = clock();
}
}
int main()
{
if(!InitCUDA())
return 0;
float *a, *b, *c, *d;
int *e;
int n = MATRIX_SIZE;
a = (float*)malloc(sizeof(float) * n * n);
b = (float*)malloc(sizeof(float) *n * n);
c = (float*)malloc(sizeof(float) * n * n);
d = (float*)malloc(sizeof(float) * n * n);
e = (int*)malloc(sizeof(int) * n * n);
srand(0);
matgen(a, n);
matgen(b, n);
float *cuda_a, *cuda_b, *cuda_c;
int *cuda_e;
clock_t* time;
size_t pitch_a, pitch_b, pitch_c;
hipMallocPitch((void**) &cuda_a, &pitch_a, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_b, &pitch_b, sizeof(float) * n, n);
hipMallocPitch((void**)&cuda_c, &pitch_c, sizeof(float) * n, n);
/*
cudaMalloc((void**)&cuda_a, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_b, sizeof(float) * n * n);
cudaMalloc((void**)&cuda_c, sizeof(float) * n * n);
*/
hipMalloc((void**)&cuda_e, sizeof(int));
hipMalloc((void**)&time, sizeof(clock_t) * n * 2);
hipMemcpy(cuda_a, a, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(cuda_b, b, sizeof(float) * n * n, hipMemcpyHostToDevice);
//matMultCUDA<<<blocks_num, THREAD_NUM, 0>>>(cuda_a, cuda_b, cuda_c, n, time);
matMultCUDA<<<n, THREAD_NUM, sizeof(float) * n >>> (cuda_a, cuda_b, cuda_c, n, time, cuda_e);
clock_t time_use[blocks_num * 2];
hipMemcpy(c, cuda_c, sizeof(float) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(e, cuda_e, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(&time_use, time, sizeof(clock_t) * 2 * blocks_num, hipMemcpyDeviceToHost);
hipFree(cuda_a);
hipFree(cuda_b);
hipFree(cuda_c);
hipFree(time);
printf("sizeof(c)= %d\n",sizeof(c));
printf("blockDim.x = %d\n", *e);
for(int i = 0; i < 10; i++)
printf("%f ", c[i]);
clock_t min_start, max_end;
min_start = time_use[0];
max_end = time_use[blocks_num];
for(int i = 1; i < blocks_num; i++){
if(min_start > time_use[i])
min_start = time_use[i];
if(max_end < time_use[i + blocks_num])
max_end = time_use[i + blocks_num];
}
clock_t final_time = max_end - min_start;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
double t = 0;
for(int k = 0; k < n; k++){
t += a[i * n + k] * b[k * n + j];
}
d[i * n + j] = t;
}
}
float max_err = 0;
float average_err = 0;
for(int i = 0; i < n; i++){
for(int j = 0; j < n; j++){
if(d[i * n + j] != 0){
float err = fabs((c[i * n + j] - d[i * n + j]) / d[i * n + j]);
if(max_err < err)
max_err = err;
average_err += err;
}
}
}
printf("Max error: %g Average error: %g\n", max_err, average_err / (n*n));
printf("gputime: %d\n", final_time);
return 0;
} | .text
.file "copy.hip"
.globl _Z15printDevicePropRK20hipDeviceProp_tR0600 # -- Begin function _Z15printDevicePropRK20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z15printDevicePropRK20hipDeviceProp_tR0600,@function
_Z15printDevicePropRK20hipDeviceProp_tR0600: # @_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 288(%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 308(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 312(%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rbx), %esi
movl 340(%rbx), %edx
movl 344(%rbx), %ecx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 360(%rbx), %esi
movl 364(%rbx), %edx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 384(%rbx), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z15printDevicePropRK20hipDeviceProp_tR0600, .Lfunc_end0-_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv
.p2align 4, 0x90
.type _Z8InitCUDAv,@function
_Z8InitCUDAv: # @_Z8InitCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB1_3
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_2
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_9
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
cmpl $0, 368(%rsp)
jle .LBB1_8
jmp .LBB1_9
.LBB1_2:
xorl %ebx, %ebx
.LBB1_9: # %._crit_edge
movl 4(%rsp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
cmpl 4(%rsp), %ebx
je .LBB1_10
# %bb.11:
incl %ebx
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB1_12:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $20, %esi
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rcx
movl $.L.str.17, %edi
movl $40, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
jmp .LBB1_12
.Lfunc_end1:
.size _Z8InitCUDAv, .Lfunc_end1-_Z8InitCUDAv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6matgenPfi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z6matgenPfi
.p2align 4, 0x90
.type _Z6matgenPfi,@function
_Z6matgenPfi: # @_Z6matgenPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6matgenPfi, .Lfunc_end2-_Z6matgenPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z8InitCUDAv
testb %al, %al
je .LBB3_26
# %bb.1:
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %edi, %edi
callq srand
movq %r15, %r13
.p2align 4, 0x90
.LBB3_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %rbp
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %rbp # imm = 0x3E8
jne .LBB3_2
# %bb.5: # %.preheader.i125.preheader
xorl %ebp, %ebp
movq 48(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB3_6: # %.preheader.i125
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_7
# %bb.8: # %._crit_edge.i130
# in Loop: Header=BB3_6 Depth=1
incq %rbp
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %rbp # imm = 0x3E8
jne .LBB3_6
# %bb.9: # %_Z6matgenPfi.exit133
leaq 32(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 24(%rsp), %rdi
leaq 216(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 16(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 56(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16000, %esi # imm = 0x3E80
callq hipMalloc
movq 32(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $4000, %r8d # imm = 0xFA0
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl $1000, 44(%rsp) # imm = 0x3E8
movq %rsi, 176(%rsp)
movq %rdi, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 64(%rsp)
leaq 192(%rsp), %rax
movq %rax, 72(%rsp)
leaq 184(%rsp), %rax
movq %rax, 80(%rsp)
leaq 44(%rsp), %rax
movq %rax, 88(%rsp)
leaq 176(%rsp), %rax
movq %rax, 96(%rsp)
leaq 168(%rsp), %rax
movq %rax, 104(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movl $4, %edx
movq 112(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r13d, %r13d
movl $.L.str.18, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl (%rbp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB3_12: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB3_12
# %bb.13:
movq 64(%rsp), %rcx
movq 72(%rsp), %rax
movq 80(%rsp), %rdx
movq 88(%rsp), %r13
cmpq %r13, %rdx
cmovgq %rdx, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_14: # %.preheader139
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
# Child Loop BB3_16 Depth 3
imulq $4000, %rdx, %rsi # imm = 0xFA0
addq %r14, %rsi
movq %r12, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_15: # %.preheader138
# Parent Loop BB3_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_16 Depth 3
xorps %xmm0, %xmm0
movq %rdi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_14 Depth=1
# Parent Loop BB3_15 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r9), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r10
addq $4000, %r9 # imm = 0xFA0
cmpq $1000, %r10 # imm = 0x3E8
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_15 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsi,%r8,4)
incq %r8
addq $4, %rdi
cmpq $1000, %r8 # imm = 0x3E8
jne .LBB3_15
# %bb.18: # in Loop: Header=BB3_14 Depth=1
incq %rdx
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB3_14
# %bb.19: # %.preheader.preheader
cmpq %rax, %rcx
cmovlq %rcx, %rax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
xorps %xmm1, %xmm1
xorps %xmm3, %xmm3
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_24: # in Loop: Header=BB3_20 Depth=1
incq %rcx
addq $4000, %rbx # imm = 0xFA0
addq $4000, %r14 # imm = 0xFA0
cmpq $1000, %rcx # imm = 0x3E8
je .LBB3_25
.LBB3_20: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
xorl %edx, %edx
jmp .LBB3_21
.p2align 4, 0x90
.LBB3_23: # in Loop: Header=BB3_21 Depth=2
incq %rdx
cmpq $1000, %rdx # imm = 0x3E8
je .LBB3_24
.LBB3_21: # Parent Loop BB3_20 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB3_22
jnp .LBB3_23
.LBB3_22: # in Loop: Header=BB3_21 Depth=2
movss (%rbx,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm2, %xmm5
addss %xmm5, %xmm1
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB3_23
.LBB3_25:
subq %rax, %r13
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
divss .LCPI3_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.21, %edi
movb $2, %al
callq printf
movl $.L.str.22, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
.LBB3_26:
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.type _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi,@function
_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi: # @_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi, .Lfunc_end4-_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Name : %s.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "totalFlbalMem : %d.\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sharedMemPerBlock : %d.\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "regsPerBlock : %d.\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "warpSize : %d.\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "memPitch : %d.\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "maxThreadsPerBlock : %d.\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "maxThreadsDim[0 - 2] : %d %d %d.\n"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "maxGridSize[0 - 2] : %d %d %d.\n"
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "totalConstMem : %d.\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "major.minor : %d.%d.\n"
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "clockRate : %d.\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "textureAlignment : %d.\n"
.size .L.str.12, 24
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "deviceOverlap : %d.\n"
.size .L.str.13, 21
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "multiProcessorCount : %d.\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "There is no device.\n"
.size .L.str.15, 21
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Total %d GPU\n"
.size .L.str.16, 14
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "There is no device supporting cuda 1.x.\n"
.size .L.str.17, 41
.type _ZL11matMultCUDAPKfS0_PfiPlPi,@object # @_ZL11matMultCUDAPKfS0_PfiPlPi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11matMultCUDAPKfS0_PfiPlPi:
.quad _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.size _ZL11matMultCUDAPKfS0_PfiPlPi, 8
.type .L.str.18,@object # @.str.18
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.18:
.asciz "sizeof(c)= %d\n"
.size .L.str.18, 15
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "blockDim.x = %d\n"
.size .L.str.19, 17
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%f "
.size .L.str.20, 4
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Max error: %g Average error: %g\n"
.size .L.str.21, 33
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "gputime: %d\n"
.size .L.str.22, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL11matMultCUDAPKfS0_PfiPlPi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL11matMultCUDAPKfS0_PfiPlPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d347e_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL11matMultCUDAPKfS0_PfiPlPi, @function
_ZL11matMultCUDAPKfS0_PfiPlPi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL11matMultCUDAPKfS0_PfiPlPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL11matMultCUDAPKfS0_PfiPlPi, .-_ZL11matMultCUDAPKfS0_PfiPlPi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device Name : %s.\n"
.LC1:
.string "totalFlbalMem : %d.\n"
.LC2:
.string "sharedMemPerBlock : %d.\n"
.LC3:
.string "regsPerBlock : %d.\n"
.LC4:
.string "warpSize : %d.\n"
.LC5:
.string "memPitch : %d.\n"
.LC6:
.string "maxThreadsPerBlock : %d.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "maxThreadsDim[0 - 2] : %d %d %d.\n"
.align 8
.LC8:
.string "maxGridSize[0 - 2] : %d %d %d.\n"
.section .rodata.str1.1
.LC9:
.string "totalConstMem : %d.\n"
.LC10:
.string "major.minor : %d.%d.\n"
.LC11:
.string "clockRate : %d.\n"
.LC12:
.string "textureAlignment : %d.\n"
.LC13:
.string "deviceOverlap : %d.\n"
.LC14:
.string "multiProcessorCount : %d.\n"
.text
.globl _Z15printDevicePropRK14cudaDeviceProp
.type _Z15printDevicePropRK14cudaDeviceProp, @function
_Z15printDevicePropRK14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rdi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 288(%rbx), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 304(%rbx), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 308(%rbx), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rbx), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rbx), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 328(%rbx), %ecx
movl 324(%rbx), %edx
movl 332(%rbx), %r8d
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rbx), %ecx
movl 336(%rbx), %edx
movl 344(%rbx), %r8d
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 352(%rbx), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rbx), %ecx
movl 360(%rbx), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rbx), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rbx), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 384(%rbx), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 388(%rbx), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15printDevicePropRK14cudaDeviceProp, .-_Z15printDevicePropRK14cudaDeviceProp
.section .rodata.str1.1
.LC15:
.string "There is no device.\n"
.LC16:
.string "Total %d GPU\n"
.section .rodata.str1.8
.align 8
.LC17:
.string "There is no device supporting cuda 1.x.\n"
.text
.globl _Z8InitCUDAv
.type _Z8InitCUDAv, @function
_Z8InitCUDAv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %eax
testl %eax, %eax
je .L24
movl $0, %ebx
leaq 16(%rsp), %rbp
jg .L16
jmp .L17
.L24:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %eax
jmp .L11
.L14:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L17
.L16:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L14
cmpl $0, 376(%rsp)
jle .L14
.L17:
movl 12(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, 12(%rsp)
je .L25
leal 1(%rbx), %edi
call cudaSetDevice@PLT
movl $1, %eax
.L11:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L26
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L11
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8InitCUDAv, .-_Z8InitCUDAv
.globl _Z6matgenPfi
.type _Z6matgenPfi, @function
_Z6matgenPfi:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L29:
leaq 0(%rbp,%r13), %rbx
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC18(%rip), %xmm0
movss %xmm0, 12(%rsp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L29
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2059:
.size _Z6matgenPfi, .-_Z6matgenPfi
.section .rodata.str1.1
.LC21:
.string "sizeof(c)= %d\n"
.LC22:
.string "blockDim.x = %d\n"
.LC23:
.string "%f "
.section .rodata.str1.8
.align 8
.LC26:
.string "Max error: %g Average error: %g\n"
.section .rodata.str1.1
.LC27:
.string "gputime: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
call _Z8InitCUDAv
testb %al, %al
jne .L58
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %edi
call srand@PLT
movl $1000, %esi
movq %r12, %rdi
call _Z6matgenPfi
movl $1000, %esi
movq %r13, %rdi
call _Z6matgenPfi
leaq 48(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 64(%rsp), %rsi
leaq 24(%rsp), %rdi
movl $1000, %ecx
movl $4000, %edx
call cudaMallocPitch@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 84(%rsp)
movl $1, 88(%rsp)
movl $1000, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $4000, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L38:
movl $2, %ecx
movl $4000000, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $8, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%r14), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %r14
leaq 40(%rbp), %r15
.L39:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r14
cmpq %r15, %r14
jne .L39
movq 120(%rsp), %rax
movq 112(%rsp), %rdx
cmpq %rdx, %rax
cmovge %rax, %rdx
movq %rdx, %r14
movq 96(%rsp), %rax
movq 104(%rsp), %rdx
cmpq %rdx, %rax
cmovg %rdx, %rax
subq %rax, %r14
movl $0, %r9d
jmp .L40
.L60:
movq 32(%rsp), %r9
movq 40(%rsp), %r8
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _ZL11matMultCUDAPKfS0_PfiPlPi
jmp .L38
.L61:
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $1000, %rsi
je .L42
.L44:
leaq -4000000(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L41:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
addq $4, %rdx
addq $4000, %rax
cmpq %rcx, %rax
jne .L41
jmp .L61
.L42:
addq $1, %r9
cmpq $1000, %r9
je .L51
.L40:
leaq 4000000(%r13), %rcx
imulq $4000, %r9, %rdi
leaq (%r12,%rdi), %r8
addq %rbx, %rdi
movl $0, %esi
jmp .L44
.L53:
movss 0(%rbp,%rax), %xmm0
subss %xmm1, %xmm0
divss %xmm1, %xmm0
andps %xmm5, %xmm0
movaps %xmm0, %xmm6
maxss %xmm3, %xmm6
movaps %xmm6, %xmm3
addss %xmm0, %xmm4
.L45:
addq $4, %rax
cmpq %rax, %rdx
je .L62
.L48:
movss (%rbx,%rax), %xmm1
ucomiss %xmm2, %xmm1
jp .L53
je .L45
jmp .L53
.L62:
addq $4000, %rdx
cmpq $4004000, %rdx
je .L63
.L43:
leaq -4000(%rdx), %rax
jmp .L48
.L51:
movl $4000, %edx
pxor %xmm4, %xmm4
movaps %xmm4, %xmm3
movaps %xmm4, %xmm2
movss .LC24(%rip), %xmm5
jmp .L43
.L63:
divss .LC25(%rip), %xmm4
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm4, %xmm1
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %r14, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L37
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z11matMultCUDAPKfS0_PfiPlPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11matMultCUDAPKfS0_PfiPlPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC18:
.long 805306368
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC24:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC25:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy.hip"
.globl _Z15printDevicePropRK20hipDeviceProp_tR0600 # -- Begin function _Z15printDevicePropRK20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z15printDevicePropRK20hipDeviceProp_tR0600,@function
_Z15printDevicePropRK20hipDeviceProp_tR0600: # @_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 288(%rbx), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 304(%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 308(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 312(%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 320(%rbx), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 324(%rbx), %esi
movl 328(%rbx), %edx
movl 332(%rbx), %ecx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 336(%rbx), %esi
movl 340(%rbx), %edx
movl 344(%rbx), %ecx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 360(%rbx), %esi
movl 364(%rbx), %edx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 384(%rbx), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z15printDevicePropRK20hipDeviceProp_tR0600, .Lfunc_end0-_Z15printDevicePropRK20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl _Z8InitCUDAv # -- Begin function _Z8InitCUDAv
.p2align 4, 0x90
.type _Z8InitCUDAv,@function
_Z8InitCUDAv: # @_Z8InitCUDAv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
je .LBB1_3
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB1_2
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_9
.LBB1_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
cmpl $0, 368(%rsp)
jle .LBB1_8
jmp .LBB1_9
.LBB1_2:
xorl %ebx, %ebx
.LBB1_9: # %._crit_edge
movl 4(%rsp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
cmpl 4(%rsp), %ebx
je .LBB1_10
# %bb.11:
incl %ebx
movl %ebx, %edi
callq hipSetDevice
movb $1, %al
.LBB1_12:
# kill: def $al killed $al killed $eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $20, %esi
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rcx
movl $.L.str.17, %edi
movl $40, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
xorl %eax, %eax
jmp .LBB1_12
.Lfunc_end1:
.size _Z8InitCUDAv, .Lfunc_end1-_Z8InitCUDAv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6matgenPfi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z6matgenPfi
.p2align 4, 0x90
.type _Z6matgenPfi,@function
_Z6matgenPfi: # @_Z6matgenPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB2_2
.LBB2_5: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6matgenPfi, .Lfunc_end2-_Z6matgenPfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z8InitCUDAv
testb %al, %al
je .LBB3_26
# %bb.1:
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r15
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %edi, %edi
callq srand
movq %r15, %r13
.p2align 4, 0x90
.LBB3_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
incq %rbp
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %rbp # imm = 0x3E8
jne .LBB3_2
# %bb.5: # %.preheader.i125.preheader
xorl %ebp, %ebp
movq 48(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB3_6: # %.preheader.i125
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss 4(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_7
# %bb.8: # %._crit_edge.i130
# in Loop: Header=BB3_6 Depth=1
incq %rbp
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %rbp # imm = 0x3E8
jne .LBB3_6
# %bb.9: # %_Z6matgenPfi.exit133
leaq 32(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 24(%rsp), %rdi
leaq 216(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 16(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1000, %ecx # imm = 0x3E8
callq hipMallocPitch
leaq 56(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16000, %esi # imm = 0x3E80
callq hipMalloc
movq 32(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 488(%rdx), %rdi
movl $4000, %r8d # imm = 0xFA0
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl $1000, 44(%rsp) # imm = 0x3E8
movq %rsi, 176(%rsp)
movq %rdi, 168(%rsp)
leaq 200(%rsp), %rax
movq %rax, 64(%rsp)
leaq 192(%rsp), %rax
movq %rax, 72(%rsp)
leaq 184(%rsp), %rax
movq %rax, 80(%rsp)
leaq 44(%rsp), %rax
movq %rax, 88(%rsp)
leaq 176(%rsp), %rax
movq %rax, 96(%rsp)
leaq 168(%rsp), %rax
movq %rax, 104(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movq 16(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movl $4, %edx
movq 112(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %r13d, %r13d
movl $.L.str.18, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl (%rbp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB3_12: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %edi
movb $1, %al
callq printf
incq %r13
cmpq $10, %r13
jne .LBB3_12
# %bb.13:
movq 64(%rsp), %rcx
movq 72(%rsp), %rax
movq 80(%rsp), %rdx
movq 88(%rsp), %r13
cmpq %r13, %rdx
cmovgq %rdx, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_14: # %.preheader139
# =>This Loop Header: Depth=1
# Child Loop BB3_15 Depth 2
# Child Loop BB3_16 Depth 3
imulq $4000, %rdx, %rsi # imm = 0xFA0
addq %r14, %rsi
movq %r12, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_15: # %.preheader138
# Parent Loop BB3_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_16 Depth 3
xorps %xmm0, %xmm0
movq %rdi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_14 Depth=1
# Parent Loop BB3_15 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r9), %xmm1
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r10
addq $4000, %r9 # imm = 0xFA0
cmpq $1000, %r10 # imm = 0x3E8
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_15 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsi,%r8,4)
incq %r8
addq $4, %rdi
cmpq $1000, %r8 # imm = 0x3E8
jne .LBB3_15
# %bb.18: # in Loop: Header=BB3_14 Depth=1
incq %rdx
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB3_14
# %bb.19: # %.preheader.preheader
cmpq %rax, %rcx
cmovlq %rcx, %rax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
xorps %xmm1, %xmm1
xorps %xmm3, %xmm3
jmp .LBB3_20
.p2align 4, 0x90
.LBB3_24: # in Loop: Header=BB3_20 Depth=1
incq %rcx
addq $4000, %rbx # imm = 0xFA0
addq $4000, %r14 # imm = 0xFA0
cmpq $1000, %rcx # imm = 0x3E8
je .LBB3_25
.LBB3_20: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
xorl %edx, %edx
jmp .LBB3_21
.p2align 4, 0x90
.LBB3_23: # in Loop: Header=BB3_21 Depth=2
incq %rdx
cmpq $1000, %rdx # imm = 0x3E8
je .LBB3_24
.LBB3_21: # Parent Loop BB3_20 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rdx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm4
jne .LBB3_22
jnp .LBB3_23
.LBB3_22: # in Loop: Header=BB3_21 Depth=2
movss (%rbx,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
subss %xmm4, %xmm5
divss %xmm4, %xmm5
andps %xmm2, %xmm5
addss %xmm5, %xmm1
maxss %xmm3, %xmm5
movaps %xmm5, %xmm3
jmp .LBB3_23
.LBB3_25:
subq %rax, %r13
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
divss .LCPI3_2(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.21, %edi
movb $2, %al
callq printf
movl $.L.str.22, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
.LBB3_26:
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.type _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi,@function
_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi: # @_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi, .Lfunc_end4-_ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11matMultCUDAPKfS0_PfiPlPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Name : %s.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "totalFlbalMem : %d.\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sharedMemPerBlock : %d.\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "regsPerBlock : %d.\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "warpSize : %d.\n"
.size .L.str.4, 16
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "memPitch : %d.\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "maxThreadsPerBlock : %d.\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "maxThreadsDim[0 - 2] : %d %d %d.\n"
.size .L.str.7, 34
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "maxGridSize[0 - 2] : %d %d %d.\n"
.size .L.str.8, 32
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "totalConstMem : %d.\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "major.minor : %d.%d.\n"
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "clockRate : %d.\n"
.size .L.str.11, 17
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "textureAlignment : %d.\n"
.size .L.str.12, 24
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "deviceOverlap : %d.\n"
.size .L.str.13, 21
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "multiProcessorCount : %d.\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "There is no device.\n"
.size .L.str.15, 21
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Total %d GPU\n"
.size .L.str.16, 14
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "There is no device supporting cuda 1.x.\n"
.size .L.str.17, 41
.type _ZL11matMultCUDAPKfS0_PfiPlPi,@object # @_ZL11matMultCUDAPKfS0_PfiPlPi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11matMultCUDAPKfS0_PfiPlPi:
.quad _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.size _ZL11matMultCUDAPKfS0_PfiPlPi, 8
.type .L.str.18,@object # @.str.18
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.18:
.asciz "sizeof(c)= %d\n"
.size .L.str.18, 15
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "blockDim.x = %d\n"
.size .L.str.19, 17
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%f "
.size .L.str.20, 4
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Max error: %g Average error: %g\n"
.size .L.str.21, 33
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "gputime: %d\n"
.size .L.str.22, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL11matMultCUDAPKfS0_PfiPlPi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL26__device_stub__matMultCUDAPKfS0_PfiPlPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL11matMultCUDAPKfS0_PfiPlPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <cstring>
#include <fstream>
#include <stdlib.h>
#include <locale>
#include <string>
#include <limits>
#include <time.h>
#include <stdio.h>
#include <iomanip>
#include <sys/time.h>
using namespace std;
//------------ Kernel de Processamento
__global__ void Classif(int* d_dados, int* d_class, long dsize, int colsIn, int colsOut)
{
int i=(threadIdx.x * colsIn) + (blockIdx.x * blockDim.x * colsIn);
int o=(threadIdx.x * colsOut) + (blockIdx.x * blockDim.x * colsOut);
int VlOpen,VlHigh,VlLow,VlClose,classe;
if (i<=dsize) {
VlOpen = d_dados[i+1];
VlHigh = d_dados[i+2];
VlLow = d_dados[i+3];
VlClose = d_dados[i+4];
classe=(VlOpen==VlClose ? 512: VlOpen>VlClose ? 256:1024)+(VlLow<VlOpen ? 1:4)+(VlLow<VlClose ? 2:8)+(VlHigh>VlOpen ? 16:64)+(VlHigh>VlClose ? 32:128);
d_class[o]=d_dados[i];
d_class[o+1]=classe;
}
}
//--------------------- Funcoes de tempo --------------------------------
std::string DataHora()
{
time_t rawtime;
struct tm * timeinfo;
char buffer [20];
time ( &rawtime );
timeinfo = localtime ( &rawtime );
strftime (buffer,20,"%F %H-%M-%S",timeinfo);
return buffer;
}
/* funcao de tempo */
double calcula_tempo(const unsigned long int ini, const unsigned long int fim)
{
double r;
if(fim >= ini)
r = ((double)(fim - ini)) / CLOCKS_PER_SEC;
else
r = ((double)( (fim + (unsigned long int)-1) - ini)) / CLOCKS_PER_SEC;
return r;
}
//------- Classif_paralela:: / std::string ---------------------------
void Classif_GPU(const char * nome, long plins, int nthd, const char * sthd){
char arq[256];
//char arqo[256];
//std::ifstream fin;
int colsIn=5, colsOut=2;
long lins,i, c, dsize, csize;
//int classe,VlOpen,VlHigh,VlLow,VlClose;
int v_blocos,v_threads;
std::string sIndice,sVlOpen,sVlHigh,sVlLow,sVlClose;
unsigned long int t_ini;
unsigned long int t_fin;
unsigned long int t_tmp;
std::string dateStr,fn,fnl,s_threads;
/*--- define variaveis de tempo -------------*/
timeval start, end;
double delta;
dateStr=DataHora();
std::cout<<" <DataHora > = "<<dateStr<<std::endl;
/* tempo inicial */
t_ini = (unsigned long int) clock;
gettimeofday(&start, NULL); //marcador de início do processamento
/* -- define as dimensões dos vetores que serão criados em logar de matrizes */
/* -- dsize define o tamanho do vetor de dados em função do numero de linhas e colunas*/
dsize=plins*colsIn;
/* -- csize define o tamanho do vetor de classificacao em função do numero de linhas e colunas*/
csize=plins*colsOut;
/* -- Cria os vetores que conterão os dados lidos do arquivo e a classificação */
int *h_dados;
int *h_class;
//std::cout<<"dsize= "<< dsize <<" csize= "<< csize<<std::endl;
size_t d_nbytes=dsize * sizeof(int);
size_t c_nbytes=csize * sizeof(int);
cudaMallocManaged ((void**)&h_dados, d_nbytes);
cudaMallocManaged ((void**)&h_class, c_nbytes);
//h_dados[0]=0;
//h_dados[1]=1;
//std::cout<<"h_dados[0]= "<< h_dados[0] <<" h_dados[1]= "<< h_dados[1]<<std::endl;
lins=plins-0;
std::cout<<" <inicializou lns> = "<<lins<<std::endl;
/* ----- Abre o arquivo csv e inicia a carga dos vetores ------------------- */
strcpy(arq,nome);
ifstream fin(arq);
if (fin.is_open())
{
t_tmp=(unsigned long int) clock();
/*--- carrega o arquivo no vetor host h_dados e inicializa h_class, transformando valores float em int*/
i=0;
c=0;
while (fin.good())
{
getline(fin,sIndice,',');
getline(fin,sVlOpen,',');
getline(fin,sVlHigh,',');
getline(fin,sVlLow,',');
getline(fin,sVlClose,'\n');
//std::cout<<"sIndice= "<< sIndice <<"sVlOpen= "<< sVlOpen<<"sVlHigh= "<< sVlHigh<<"sVlLow= "<< sVlLow<<"sVlClose= "<< sVlClose<<std::endl;
//h_dados[i]=std::stoi(sIndice);
h_dados[i]=std::atoi(sIndice.c_str());
//h_dados[i+1]=static_cast<int>(std::stof(sVlOpen,NULL)*100);
h_dados[i+1]=static_cast<int>(std::atof(sVlOpen.c_str())*100);
h_dados[i+2]=static_cast<int>(std::atof(sVlHigh.c_str())*100);
h_dados[i+3]=static_cast<int>(std::atof(sVlLow.c_str())*100);
h_dados[i+4]=static_cast<int>(std::atof(sVlClose.c_str())*100);
h_class[c]=0;
h_class[c+1]=0;
i+=colsIn;
c+=colsOut;
}
//std::cout<<" <Carregou h_dados com "<< i <<" posições e h_class com "<< c << " posicoes"<<std::endl;
/*--- Calcula o número de blocos e threads em função do número de registros
i = número de posições geradas para o vetor vezes o número de colunas de entrada (colsIn)
Fixei as threads em 256
Para processar todas as linhas do arquivo de entrada, plins, uso i/colsIN que tem o mesmo valor de plins
assim, para 17.000.000 de registros a classificar tremos:
v_blocos=ceil((85.000.000/5)/256)=66406,26 ==> 66407 blocos
---*/
v_threads=nthd;
s_threads=std::string(sthd);
//s_threads = "64";
//v_blocos=ceil((i/colsIn)/v_threads);
v_blocos=(int)ceil((float)lins/v_threads);
//std::cout<<" <Calculou v_blocos com "<< v_blocos <<" threads com "<< v_threads <<std::endl;
/*--- invoca o kernel de classificação ---*/
Classif<<<v_blocos,v_threads>>>(h_dados, h_class, dsize, colsIn, colsOut);
/*--- copia de volta o vetor de classicação --*/
cudaDeviceSynchronize();
//std::cout<<" <Sincronizou -------------------"<<std::endl;
fnl="log/Classif_KernelT"+ s_threads +dateStr+".log.txt";
//arqo=fnl.c_str();
std::ofstream mylog (fnl.c_str());
//std::ofstream mylog (arqo);
mylog<<"Processado em "<< dateStr <<std::endl;
mylog<<"Processado em "<< v_blocos <<" blocos com "<< v_threads <<" threads"<<std::endl;
mylog<<"Tempo total de classificaçao (ler CSV e classificar via kernel)= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/*---- fecha o arquivo de entrada de registros a classificar*/
fin.close();
//mylog<<"Tempo decorrido até o final da classificaçao= "<< calcula_tempo(t_ini, (unsigned long int) clock()) <<std::endl;
/*--- cria o nome do arquivo csv de saída com as classificações ----*/
//fn="/home/UFF/GPU/Trabalho/Dados/Classif_Kernel"+dateStr+".csv";
fn="csv/Classif_KernelT"+ s_threads +dateStr+".csv";
//std::cout<<std::endl<<fn <<std::endl;
t_tmp=(unsigned long int) clock();
/*--- abre o csv de saída ---*/
std::ofstream myfile (fn.c_str());
myfile<<"Indice,IdClasse"<<std::endl;
/*--- exporta o conteúdo do vetor h_class ---*/
for (i=0; i<csize; i+=colsOut)
{
myfile<<h_class[i]<<','<<h_class[i+1]<<"\n";
}
myfile.close();
mylog<<"Tempo para exportar classificaçao para CSV= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
// desaloca a matriz << no Thtrust a desalocação dos vetores é transparente ---------------
//mylog<<"Tempo para free matriz = "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/* tempo final */
t_fin = (unsigned long int) clock();
mylog<<"Total de registros classificados= "<< lins <<std::endl;
mylog<<"Tempo total de processamento= "<< setprecision(6) << calcula_tempo(t_ini, t_fin) <<std::endl;
gettimeofday(&end, NULL);
delta = ((end.tv_sec - start.tv_sec) * 1000000u + end.tv_usec - start.tv_usec) / 1.e6;
mylog<<"Tempo total de processamento 2 = "<< delta <<std::endl;
mylog.close();
std::cout<<std::endl<<"Tempo total de processamento= "<< calcula_tempo(t_ini, t_fin) <<std::endl;
std::cout<<"Tempo total de processamento 2 = "<< delta <<std::endl;
}
else
{
std::cout<<std::endl<<"Erro na abertura do arquivo "<< nome <<std::endl;
}
}
//---------------------------------------------------------------------------
int main(int argc, char * argv[])
{
long nlin=0;
int nthd=0;
if (argc < 4){
std::cout<<"Digite o nome do arquivo de entrada e a quantidade de registros e quantas threads"<<std::endl;
abort();
}
// File
std::cout<<" <Arquivo de entrada> = "<<argv[1]<<std::endl;
//nlin=std::stol(argv[2]);
nlin=std::atol(argv[2]);
nthd=std::atoi(argv[3]);
/* processa a classificaçao */
std::cout<<" <Qtd Registros> = "<<nlin<<std::endl;
Classif_GPU(argv[1],nlin,nthd,argv[3]);
} | code for sm_80
Function : _Z7ClassifPiS_lii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f04070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0070*/ ISETP.GT.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f04300 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IMAD.WIDE R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0208 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x10 ; /* 0x00000010ff0b7424 */
/* 0x000fc400078e00ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, 0x100 ; /* 0x00000100ff0a7424 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P3, PT, R6.reuse, R5.reuse, PT ; /* 0x000000050600720c */
/* 0x0c4fe40003f66270 */
/*0140*/ ISETP.GE.AND P4, PT, R6, R4.reuse, PT ; /* 0x000000040600720c */
/* 0x088fe20003f86270 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GT.AND P1, PT, R5, R4.reuse, PT ; /* 0x000000040500720c */
/* 0x080fe40003f24270 */
/*0170*/ ISETP.GT.AND P2, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x010fe40003f44270 */
/*0180*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe40003f05270 */
/*0190*/ SEL R3, R11, 0x40, P2 ; /* 0x000000400b037807 */
/* 0x001fc40001000000 */
/*01a0*/ SEL R6, R6, 0x8, !P4 ; /* 0x0000000806067807 */
/* 0x000fe40006000000 */
/*01b0*/ SEL R5, R8, 0x1, P3 ; /* 0x0000000108057807 */
/* 0x000fe40001800000 */
/*01c0*/ ISETP.GT.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe20003f44270 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x20 ; /* 0x00000020ff047424 */
/* 0x000fe200078e00ff */
/*01e0*/ SEL R2, R10, 0x400, P1 ; /* 0x000004000a027807 */
/* 0x000fe40000800000 */
/*01f0*/ IADD3 R6, R6, R5, R3 ; /* 0x0000000506067210 */
/* 0x000fe20007ffe003 */
/*0200*/ IMAD R3, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000037a24 */
/* 0x000fe200078e02ff */
/*0210*/ SEL R5, R4, 0x80, P2 ; /* 0x0000008004057807 */
/* 0x000fc40001000000 */
/*0220*/ SEL R0, R2, 0x200, P0 ; /* 0x0000020002007807 */
/* 0x000fe20000000000 */
/*0230*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc600078e0208 */
/*0240*/ IADD3 R5, R0, R6, R5 ; /* 0x0000000600057210 */
/* 0x000fe40007ffe005 */
/*0250*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe8000c101904 */
/*0260*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cstring>
#include <fstream>
#include <stdlib.h>
#include <locale>
#include <string>
#include <limits>
#include <time.h>
#include <stdio.h>
#include <iomanip>
#include <sys/time.h>
using namespace std;
//------------ Kernel de Processamento
__global__ void Classif(int* d_dados, int* d_class, long dsize, int colsIn, int colsOut)
{
int i=(threadIdx.x * colsIn) + (blockIdx.x * blockDim.x * colsIn);
int o=(threadIdx.x * colsOut) + (blockIdx.x * blockDim.x * colsOut);
int VlOpen,VlHigh,VlLow,VlClose,classe;
if (i<=dsize) {
VlOpen = d_dados[i+1];
VlHigh = d_dados[i+2];
VlLow = d_dados[i+3];
VlClose = d_dados[i+4];
classe=(VlOpen==VlClose ? 512: VlOpen>VlClose ? 256:1024)+(VlLow<VlOpen ? 1:4)+(VlLow<VlClose ? 2:8)+(VlHigh>VlOpen ? 16:64)+(VlHigh>VlClose ? 32:128);
d_class[o]=d_dados[i];
d_class[o+1]=classe;
}
}
//--------------------- Funcoes de tempo --------------------------------
std::string DataHora()
{
time_t rawtime;
struct tm * timeinfo;
char buffer [20];
time ( &rawtime );
timeinfo = localtime ( &rawtime );
strftime (buffer,20,"%F %H-%M-%S",timeinfo);
return buffer;
}
/* funcao de tempo */
double calcula_tempo(const unsigned long int ini, const unsigned long int fim)
{
double r;
if(fim >= ini)
r = ((double)(fim - ini)) / CLOCKS_PER_SEC;
else
r = ((double)( (fim + (unsigned long int)-1) - ini)) / CLOCKS_PER_SEC;
return r;
}
//------- Classif_paralela:: / std::string ---------------------------
void Classif_GPU(const char * nome, long plins, int nthd, const char * sthd){
char arq[256];
//char arqo[256];
//std::ifstream fin;
int colsIn=5, colsOut=2;
long lins,i, c, dsize, csize;
//int classe,VlOpen,VlHigh,VlLow,VlClose;
int v_blocos,v_threads;
std::string sIndice,sVlOpen,sVlHigh,sVlLow,sVlClose;
unsigned long int t_ini;
unsigned long int t_fin;
unsigned long int t_tmp;
std::string dateStr,fn,fnl,s_threads;
/*--- define variaveis de tempo -------------*/
timeval start, end;
double delta;
dateStr=DataHora();
std::cout<<" <DataHora > = "<<dateStr<<std::endl;
/* tempo inicial */
t_ini = (unsigned long int) clock;
gettimeofday(&start, NULL); //marcador de início do processamento
/* -- define as dimensões dos vetores que serão criados em logar de matrizes */
/* -- dsize define o tamanho do vetor de dados em função do numero de linhas e colunas*/
dsize=plins*colsIn;
/* -- csize define o tamanho do vetor de classificacao em função do numero de linhas e colunas*/
csize=plins*colsOut;
/* -- Cria os vetores que conterão os dados lidos do arquivo e a classificação */
int *h_dados;
int *h_class;
//std::cout<<"dsize= "<< dsize <<" csize= "<< csize<<std::endl;
size_t d_nbytes=dsize * sizeof(int);
size_t c_nbytes=csize * sizeof(int);
cudaMallocManaged ((void**)&h_dados, d_nbytes);
cudaMallocManaged ((void**)&h_class, c_nbytes);
//h_dados[0]=0;
//h_dados[1]=1;
//std::cout<<"h_dados[0]= "<< h_dados[0] <<" h_dados[1]= "<< h_dados[1]<<std::endl;
lins=plins-0;
std::cout<<" <inicializou lns> = "<<lins<<std::endl;
/* ----- Abre o arquivo csv e inicia a carga dos vetores ------------------- */
strcpy(arq,nome);
ifstream fin(arq);
if (fin.is_open())
{
t_tmp=(unsigned long int) clock();
/*--- carrega o arquivo no vetor host h_dados e inicializa h_class, transformando valores float em int*/
i=0;
c=0;
while (fin.good())
{
getline(fin,sIndice,',');
getline(fin,sVlOpen,',');
getline(fin,sVlHigh,',');
getline(fin,sVlLow,',');
getline(fin,sVlClose,'\n');
//std::cout<<"sIndice= "<< sIndice <<"sVlOpen= "<< sVlOpen<<"sVlHigh= "<< sVlHigh<<"sVlLow= "<< sVlLow<<"sVlClose= "<< sVlClose<<std::endl;
//h_dados[i]=std::stoi(sIndice);
h_dados[i]=std::atoi(sIndice.c_str());
//h_dados[i+1]=static_cast<int>(std::stof(sVlOpen,NULL)*100);
h_dados[i+1]=static_cast<int>(std::atof(sVlOpen.c_str())*100);
h_dados[i+2]=static_cast<int>(std::atof(sVlHigh.c_str())*100);
h_dados[i+3]=static_cast<int>(std::atof(sVlLow.c_str())*100);
h_dados[i+4]=static_cast<int>(std::atof(sVlClose.c_str())*100);
h_class[c]=0;
h_class[c+1]=0;
i+=colsIn;
c+=colsOut;
}
//std::cout<<" <Carregou h_dados com "<< i <<" posições e h_class com "<< c << " posicoes"<<std::endl;
/*--- Calcula o número de blocos e threads em função do número de registros
i = número de posições geradas para o vetor vezes o número de colunas de entrada (colsIn)
Fixei as threads em 256
Para processar todas as linhas do arquivo de entrada, plins, uso i/colsIN que tem o mesmo valor de plins
assim, para 17.000.000 de registros a classificar tremos:
v_blocos=ceil((85.000.000/5)/256)=66406,26 ==> 66407 blocos
---*/
v_threads=nthd;
s_threads=std::string(sthd);
//s_threads = "64";
//v_blocos=ceil((i/colsIn)/v_threads);
v_blocos=(int)ceil((float)lins/v_threads);
//std::cout<<" <Calculou v_blocos com "<< v_blocos <<" threads com "<< v_threads <<std::endl;
/*--- invoca o kernel de classificação ---*/
Classif<<<v_blocos,v_threads>>>(h_dados, h_class, dsize, colsIn, colsOut);
/*--- copia de volta o vetor de classicação --*/
cudaDeviceSynchronize();
//std::cout<<" <Sincronizou -------------------"<<std::endl;
fnl="log/Classif_KernelT"+ s_threads +dateStr+".log.txt";
//arqo=fnl.c_str();
std::ofstream mylog (fnl.c_str());
//std::ofstream mylog (arqo);
mylog<<"Processado em "<< dateStr <<std::endl;
mylog<<"Processado em "<< v_blocos <<" blocos com "<< v_threads <<" threads"<<std::endl;
mylog<<"Tempo total de classificaçao (ler CSV e classificar via kernel)= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/*---- fecha o arquivo de entrada de registros a classificar*/
fin.close();
//mylog<<"Tempo decorrido até o final da classificaçao= "<< calcula_tempo(t_ini, (unsigned long int) clock()) <<std::endl;
/*--- cria o nome do arquivo csv de saída com as classificações ----*/
//fn="/home/UFF/GPU/Trabalho/Dados/Classif_Kernel"+dateStr+".csv";
fn="csv/Classif_KernelT"+ s_threads +dateStr+".csv";
//std::cout<<std::endl<<fn <<std::endl;
t_tmp=(unsigned long int) clock();
/*--- abre o csv de saída ---*/
std::ofstream myfile (fn.c_str());
myfile<<"Indice,IdClasse"<<std::endl;
/*--- exporta o conteúdo do vetor h_class ---*/
for (i=0; i<csize; i+=colsOut)
{
myfile<<h_class[i]<<','<<h_class[i+1]<<"\n";
}
myfile.close();
mylog<<"Tempo para exportar classificaçao para CSV= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
// desaloca a matriz << no Thtrust a desalocação dos vetores é transparente ---------------
//mylog<<"Tempo para free matriz = "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/* tempo final */
t_fin = (unsigned long int) clock();
mylog<<"Total de registros classificados= "<< lins <<std::endl;
mylog<<"Tempo total de processamento= "<< setprecision(6) << calcula_tempo(t_ini, t_fin) <<std::endl;
gettimeofday(&end, NULL);
delta = ((end.tv_sec - start.tv_sec) * 1000000u + end.tv_usec - start.tv_usec) / 1.e6;
mylog<<"Tempo total de processamento 2 = "<< delta <<std::endl;
mylog.close();
std::cout<<std::endl<<"Tempo total de processamento= "<< calcula_tempo(t_ini, t_fin) <<std::endl;
std::cout<<"Tempo total de processamento 2 = "<< delta <<std::endl;
}
else
{
std::cout<<std::endl<<"Erro na abertura do arquivo "<< nome <<std::endl;
}
}
//---------------------------------------------------------------------------
int main(int argc, char * argv[])
{
long nlin=0;
int nthd=0;
if (argc < 4){
std::cout<<"Digite o nome do arquivo de entrada e a quantidade de registros e quantas threads"<<std::endl;
abort();
}
// File
std::cout<<" <Arquivo de entrada> = "<<argv[1]<<std::endl;
//nlin=std::stol(argv[2]);
nlin=std::atol(argv[2]);
nthd=std::atoi(argv[3]);
/* processa a classificaçao */
std::cout<<" <Qtd Registros> = "<<nlin<<std::endl;
Classif_GPU(argv[1],nlin,nthd,argv[3]);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstring>
#include <fstream>
#include <stdlib.h>
#include <locale>
#include <string>
#include <limits>
#include <time.h>
#include <stdio.h>
#include <iomanip>
#include <sys/time.h>
using namespace std;
//------------ Kernel de Processamento
__global__ void Classif(int* d_dados, int* d_class, long dsize, int colsIn, int colsOut)
{
int i=(threadIdx.x * colsIn) + (blockIdx.x * blockDim.x * colsIn);
int o=(threadIdx.x * colsOut) + (blockIdx.x * blockDim.x * colsOut);
int VlOpen,VlHigh,VlLow,VlClose,classe;
if (i<=dsize) {
VlOpen = d_dados[i+1];
VlHigh = d_dados[i+2];
VlLow = d_dados[i+3];
VlClose = d_dados[i+4];
classe=(VlOpen==VlClose ? 512: VlOpen>VlClose ? 256:1024)+(VlLow<VlOpen ? 1:4)+(VlLow<VlClose ? 2:8)+(VlHigh>VlOpen ? 16:64)+(VlHigh>VlClose ? 32:128);
d_class[o]=d_dados[i];
d_class[o+1]=classe;
}
}
//--------------------- Funcoes de tempo --------------------------------
std::string DataHora()
{
time_t rawtime;
struct tm * timeinfo;
char buffer [20];
time ( &rawtime );
timeinfo = localtime ( &rawtime );
strftime (buffer,20,"%F %H-%M-%S",timeinfo);
return buffer;
}
/* funcao de tempo */
double calcula_tempo(const unsigned long int ini, const unsigned long int fim)
{
double r;
if(fim >= ini)
r = ((double)(fim - ini)) / CLOCKS_PER_SEC;
else
r = ((double)( (fim + (unsigned long int)-1) - ini)) / CLOCKS_PER_SEC;
return r;
}
//------- Classif_paralela:: / std::string ---------------------------
void Classif_GPU(const char * nome, long plins, int nthd, const char * sthd){
char arq[256];
//char arqo[256];
//std::ifstream fin;
int colsIn=5, colsOut=2;
long lins,i, c, dsize, csize;
//int classe,VlOpen,VlHigh,VlLow,VlClose;
int v_blocos,v_threads;
std::string sIndice,sVlOpen,sVlHigh,sVlLow,sVlClose;
unsigned long int t_ini;
unsigned long int t_fin;
unsigned long int t_tmp;
std::string dateStr,fn,fnl,s_threads;
/*--- define variaveis de tempo -------------*/
timeval start, end;
double delta;
dateStr=DataHora();
std::cout<<" <DataHora > = "<<dateStr<<std::endl;
/* tempo inicial */
t_ini = (unsigned long int) clock;
gettimeofday(&start, NULL); //marcador de início do processamento
/* -- define as dimensões dos vetores que serão criados em logar de matrizes */
/* -- dsize define o tamanho do vetor de dados em função do numero de linhas e colunas*/
dsize=plins*colsIn;
/* -- csize define o tamanho do vetor de classificacao em função do numero de linhas e colunas*/
csize=plins*colsOut;
/* -- Cria os vetores que conterão os dados lidos do arquivo e a classificação */
int *h_dados;
int *h_class;
//std::cout<<"dsize= "<< dsize <<" csize= "<< csize<<std::endl;
size_t d_nbytes=dsize * sizeof(int);
size_t c_nbytes=csize * sizeof(int);
hipMallocManaged ((void**)&h_dados, d_nbytes);
hipMallocManaged ((void**)&h_class, c_nbytes);
//h_dados[0]=0;
//h_dados[1]=1;
//std::cout<<"h_dados[0]= "<< h_dados[0] <<" h_dados[1]= "<< h_dados[1]<<std::endl;
lins=plins-0;
std::cout<<" <inicializou lns> = "<<lins<<std::endl;
/* ----- Abre o arquivo csv e inicia a carga dos vetores ------------------- */
strcpy(arq,nome);
ifstream fin(arq);
if (fin.is_open())
{
t_tmp=(unsigned long int) clock();
/*--- carrega o arquivo no vetor host h_dados e inicializa h_class, transformando valores float em int*/
i=0;
c=0;
while (fin.good())
{
getline(fin,sIndice,',');
getline(fin,sVlOpen,',');
getline(fin,sVlHigh,',');
getline(fin,sVlLow,',');
getline(fin,sVlClose,'\n');
//std::cout<<"sIndice= "<< sIndice <<"sVlOpen= "<< sVlOpen<<"sVlHigh= "<< sVlHigh<<"sVlLow= "<< sVlLow<<"sVlClose= "<< sVlClose<<std::endl;
//h_dados[i]=std::stoi(sIndice);
h_dados[i]=std::atoi(sIndice.c_str());
//h_dados[i+1]=static_cast<int>(std::stof(sVlOpen,NULL)*100);
h_dados[i+1]=static_cast<int>(std::atof(sVlOpen.c_str())*100);
h_dados[i+2]=static_cast<int>(std::atof(sVlHigh.c_str())*100);
h_dados[i+3]=static_cast<int>(std::atof(sVlLow.c_str())*100);
h_dados[i+4]=static_cast<int>(std::atof(sVlClose.c_str())*100);
h_class[c]=0;
h_class[c+1]=0;
i+=colsIn;
c+=colsOut;
}
//std::cout<<" <Carregou h_dados com "<< i <<" posições e h_class com "<< c << " posicoes"<<std::endl;
/*--- Calcula o número de blocos e threads em função do número de registros
i = número de posições geradas para o vetor vezes o número de colunas de entrada (colsIn)
Fixei as threads em 256
Para processar todas as linhas do arquivo de entrada, plins, uso i/colsIN que tem o mesmo valor de plins
assim, para 17.000.000 de registros a classificar tremos:
v_blocos=ceil((85.000.000/5)/256)=66406,26 ==> 66407 blocos
---*/
v_threads=nthd;
s_threads=std::string(sthd);
//s_threads = "64";
//v_blocos=ceil((i/colsIn)/v_threads);
v_blocos=(int)ceil((float)lins/v_threads);
//std::cout<<" <Calculou v_blocos com "<< v_blocos <<" threads com "<< v_threads <<std::endl;
/*--- invoca o kernel de classificação ---*/
Classif<<<v_blocos,v_threads>>>(h_dados, h_class, dsize, colsIn, colsOut);
/*--- copia de volta o vetor de classicação --*/
hipDeviceSynchronize();
//std::cout<<" <Sincronizou -------------------"<<std::endl;
fnl="log/Classif_KernelT"+ s_threads +dateStr+".log.txt";
//arqo=fnl.c_str();
std::ofstream mylog (fnl.c_str());
//std::ofstream mylog (arqo);
mylog<<"Processado em "<< dateStr <<std::endl;
mylog<<"Processado em "<< v_blocos <<" blocos com "<< v_threads <<" threads"<<std::endl;
mylog<<"Tempo total de classificaçao (ler CSV e classificar via kernel)= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/*---- fecha o arquivo de entrada de registros a classificar*/
fin.close();
//mylog<<"Tempo decorrido até o final da classificaçao= "<< calcula_tempo(t_ini, (unsigned long int) clock()) <<std::endl;
/*--- cria o nome do arquivo csv de saída com as classificações ----*/
//fn="/home/UFF/GPU/Trabalho/Dados/Classif_Kernel"+dateStr+".csv";
fn="csv/Classif_KernelT"+ s_threads +dateStr+".csv";
//std::cout<<std::endl<<fn <<std::endl;
t_tmp=(unsigned long int) clock();
/*--- abre o csv de saída ---*/
std::ofstream myfile (fn.c_str());
myfile<<"Indice,IdClasse"<<std::endl;
/*--- exporta o conteúdo do vetor h_class ---*/
for (i=0; i<csize; i+=colsOut)
{
myfile<<h_class[i]<<','<<h_class[i+1]<<"\n";
}
myfile.close();
mylog<<"Tempo para exportar classificaçao para CSV= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
// desaloca a matriz << no Thtrust a desalocação dos vetores é transparente ---------------
//mylog<<"Tempo para free matriz = "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/* tempo final */
t_fin = (unsigned long int) clock();
mylog<<"Total de registros classificados= "<< lins <<std::endl;
mylog<<"Tempo total de processamento= "<< setprecision(6) << calcula_tempo(t_ini, t_fin) <<std::endl;
gettimeofday(&end, NULL);
delta = ((end.tv_sec - start.tv_sec) * 1000000u + end.tv_usec - start.tv_usec) / 1.e6;
mylog<<"Tempo total de processamento 2 = "<< delta <<std::endl;
mylog.close();
std::cout<<std::endl<<"Tempo total de processamento= "<< calcula_tempo(t_ini, t_fin) <<std::endl;
std::cout<<"Tempo total de processamento 2 = "<< delta <<std::endl;
}
else
{
std::cout<<std::endl<<"Erro na abertura do arquivo "<< nome <<std::endl;
}
}
//---------------------------------------------------------------------------
int main(int argc, char * argv[])
{
long nlin=0;
int nthd=0;
if (argc < 4){
std::cout<<"Digite o nome do arquivo de entrada e a quantidade de registros e quantas threads"<<std::endl;
abort();
}
// File
std::cout<<" <Arquivo de entrada> = "<<argv[1]<<std::endl;
//nlin=std::stol(argv[2]);
nlin=std::atol(argv[2]);
nthd=std::atoi(argv[3]);
/* processa a classificaçao */
std::cout<<" <Qtd Registros> = "<<nlin<<std::endl;
Classif_GPU(argv[1],nlin,nthd,argv[3]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstring>
#include <fstream>
#include <stdlib.h>
#include <locale>
#include <string>
#include <limits>
#include <time.h>
#include <stdio.h>
#include <iomanip>
#include <sys/time.h>
using namespace std;
//------------ Kernel de Processamento
__global__ void Classif(int* d_dados, int* d_class, long dsize, int colsIn, int colsOut)
{
int i=(threadIdx.x * colsIn) + (blockIdx.x * blockDim.x * colsIn);
int o=(threadIdx.x * colsOut) + (blockIdx.x * blockDim.x * colsOut);
int VlOpen,VlHigh,VlLow,VlClose,classe;
if (i<=dsize) {
VlOpen = d_dados[i+1];
VlHigh = d_dados[i+2];
VlLow = d_dados[i+3];
VlClose = d_dados[i+4];
classe=(VlOpen==VlClose ? 512: VlOpen>VlClose ? 256:1024)+(VlLow<VlOpen ? 1:4)+(VlLow<VlClose ? 2:8)+(VlHigh>VlOpen ? 16:64)+(VlHigh>VlClose ? 32:128);
d_class[o]=d_dados[i];
d_class[o+1]=classe;
}
}
//--------------------- Funcoes de tempo --------------------------------
std::string DataHora()
{
time_t rawtime;
struct tm * timeinfo;
char buffer [20];
time ( &rawtime );
timeinfo = localtime ( &rawtime );
strftime (buffer,20,"%F %H-%M-%S",timeinfo);
return buffer;
}
/* funcao de tempo */
double calcula_tempo(const unsigned long int ini, const unsigned long int fim)
{
double r;
if(fim >= ini)
r = ((double)(fim - ini)) / CLOCKS_PER_SEC;
else
r = ((double)( (fim + (unsigned long int)-1) - ini)) / CLOCKS_PER_SEC;
return r;
}
//------- Classif_paralela:: / std::string ---------------------------
void Classif_GPU(const char * nome, long plins, int nthd, const char * sthd){
char arq[256];
//char arqo[256];
//std::ifstream fin;
int colsIn=5, colsOut=2;
long lins,i, c, dsize, csize;
//int classe,VlOpen,VlHigh,VlLow,VlClose;
int v_blocos,v_threads;
std::string sIndice,sVlOpen,sVlHigh,sVlLow,sVlClose;
unsigned long int t_ini;
unsigned long int t_fin;
unsigned long int t_tmp;
std::string dateStr,fn,fnl,s_threads;
/*--- define variaveis de tempo -------------*/
timeval start, end;
double delta;
dateStr=DataHora();
std::cout<<" <DataHora > = "<<dateStr<<std::endl;
/* tempo inicial */
t_ini = (unsigned long int) clock;
gettimeofday(&start, NULL); //marcador de início do processamento
/* -- define as dimensões dos vetores que serão criados em logar de matrizes */
/* -- dsize define o tamanho do vetor de dados em função do numero de linhas e colunas*/
dsize=plins*colsIn;
/* -- csize define o tamanho do vetor de classificacao em função do numero de linhas e colunas*/
csize=plins*colsOut;
/* -- Cria os vetores que conterão os dados lidos do arquivo e a classificação */
int *h_dados;
int *h_class;
//std::cout<<"dsize= "<< dsize <<" csize= "<< csize<<std::endl;
size_t d_nbytes=dsize * sizeof(int);
size_t c_nbytes=csize * sizeof(int);
hipMallocManaged ((void**)&h_dados, d_nbytes);
hipMallocManaged ((void**)&h_class, c_nbytes);
//h_dados[0]=0;
//h_dados[1]=1;
//std::cout<<"h_dados[0]= "<< h_dados[0] <<" h_dados[1]= "<< h_dados[1]<<std::endl;
lins=plins-0;
std::cout<<" <inicializou lns> = "<<lins<<std::endl;
/* ----- Abre o arquivo csv e inicia a carga dos vetores ------------------- */
strcpy(arq,nome);
ifstream fin(arq);
if (fin.is_open())
{
t_tmp=(unsigned long int) clock();
/*--- carrega o arquivo no vetor host h_dados e inicializa h_class, transformando valores float em int*/
i=0;
c=0;
while (fin.good())
{
getline(fin,sIndice,',');
getline(fin,sVlOpen,',');
getline(fin,sVlHigh,',');
getline(fin,sVlLow,',');
getline(fin,sVlClose,'\n');
//std::cout<<"sIndice= "<< sIndice <<"sVlOpen= "<< sVlOpen<<"sVlHigh= "<< sVlHigh<<"sVlLow= "<< sVlLow<<"sVlClose= "<< sVlClose<<std::endl;
//h_dados[i]=std::stoi(sIndice);
h_dados[i]=std::atoi(sIndice.c_str());
//h_dados[i+1]=static_cast<int>(std::stof(sVlOpen,NULL)*100);
h_dados[i+1]=static_cast<int>(std::atof(sVlOpen.c_str())*100);
h_dados[i+2]=static_cast<int>(std::atof(sVlHigh.c_str())*100);
h_dados[i+3]=static_cast<int>(std::atof(sVlLow.c_str())*100);
h_dados[i+4]=static_cast<int>(std::atof(sVlClose.c_str())*100);
h_class[c]=0;
h_class[c+1]=0;
i+=colsIn;
c+=colsOut;
}
//std::cout<<" <Carregou h_dados com "<< i <<" posições e h_class com "<< c << " posicoes"<<std::endl;
/*--- Calcula o número de blocos e threads em função do número de registros
i = número de posições geradas para o vetor vezes o número de colunas de entrada (colsIn)
Fixei as threads em 256
Para processar todas as linhas do arquivo de entrada, plins, uso i/colsIN que tem o mesmo valor de plins
assim, para 17.000.000 de registros a classificar tremos:
v_blocos=ceil((85.000.000/5)/256)=66406,26 ==> 66407 blocos
---*/
v_threads=nthd;
s_threads=std::string(sthd);
//s_threads = "64";
//v_blocos=ceil((i/colsIn)/v_threads);
v_blocos=(int)ceil((float)lins/v_threads);
//std::cout<<" <Calculou v_blocos com "<< v_blocos <<" threads com "<< v_threads <<std::endl;
/*--- invoca o kernel de classificação ---*/
Classif<<<v_blocos,v_threads>>>(h_dados, h_class, dsize, colsIn, colsOut);
/*--- copia de volta o vetor de classicação --*/
hipDeviceSynchronize();
//std::cout<<" <Sincronizou -------------------"<<std::endl;
fnl="log/Classif_KernelT"+ s_threads +dateStr+".log.txt";
//arqo=fnl.c_str();
std::ofstream mylog (fnl.c_str());
//std::ofstream mylog (arqo);
mylog<<"Processado em "<< dateStr <<std::endl;
mylog<<"Processado em "<< v_blocos <<" blocos com "<< v_threads <<" threads"<<std::endl;
mylog<<"Tempo total de classificaçao (ler CSV e classificar via kernel)= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/*---- fecha o arquivo de entrada de registros a classificar*/
fin.close();
//mylog<<"Tempo decorrido até o final da classificaçao= "<< calcula_tempo(t_ini, (unsigned long int) clock()) <<std::endl;
/*--- cria o nome do arquivo csv de saída com as classificações ----*/
//fn="/home/UFF/GPU/Trabalho/Dados/Classif_Kernel"+dateStr+".csv";
fn="csv/Classif_KernelT"+ s_threads +dateStr+".csv";
//std::cout<<std::endl<<fn <<std::endl;
t_tmp=(unsigned long int) clock();
/*--- abre o csv de saída ---*/
std::ofstream myfile (fn.c_str());
myfile<<"Indice,IdClasse"<<std::endl;
/*--- exporta o conteúdo do vetor h_class ---*/
for (i=0; i<csize; i+=colsOut)
{
myfile<<h_class[i]<<','<<h_class[i+1]<<"\n";
}
myfile.close();
mylog<<"Tempo para exportar classificaçao para CSV= "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
// desaloca a matriz << no Thtrust a desalocação dos vetores é transparente ---------------
//mylog<<"Tempo para free matriz = "<< calcula_tempo(t_tmp, (unsigned long int) clock()) <<std::endl;
/* tempo final */
t_fin = (unsigned long int) clock();
mylog<<"Total de registros classificados= "<< lins <<std::endl;
mylog<<"Tempo total de processamento= "<< setprecision(6) << calcula_tempo(t_ini, t_fin) <<std::endl;
gettimeofday(&end, NULL);
delta = ((end.tv_sec - start.tv_sec) * 1000000u + end.tv_usec - start.tv_usec) / 1.e6;
mylog<<"Tempo total de processamento 2 = "<< delta <<std::endl;
mylog.close();
std::cout<<std::endl<<"Tempo total de processamento= "<< calcula_tempo(t_ini, t_fin) <<std::endl;
std::cout<<"Tempo total de processamento 2 = "<< delta <<std::endl;
}
else
{
std::cout<<std::endl<<"Erro na abertura do arquivo "<< nome <<std::endl;
}
}
//---------------------------------------------------------------------------
int main(int argc, char * argv[])
{
long nlin=0;
int nthd=0;
if (argc < 4){
std::cout<<"Digite o nome do arquivo de entrada e a quantidade de registros e quantas threads"<<std::endl;
abort();
}
// File
std::cout<<" <Arquivo de entrada> = "<<argv[1]<<std::endl;
//nlin=std::stol(argv[2]);
nlin=std::atol(argv[2]);
nthd=std::atoi(argv[3]);
/* processa a classificaçao */
std::cout<<" <Qtd Registros> = "<<nlin<<std::endl;
Classif_GPU(argv[1],nlin,nthd,argv[3]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7ClassifPiS_lii
.globl _Z7ClassifPiS_lii
.p2align 8
.type _Z7ClassifPiS_lii,@function
_Z7ClassifPiS_lii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_lo_u32 v2, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_load_b32 s0, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_mul_lo_u32 v0, v1, s0
s_clause 0x1
global_load_b128 v[2:5], v[6:7], off
global_load_b32 v6, v[6:7], off offset:16
v_mov_b32_e32 v7, 0x100
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v3, v6
v_cndmask_b32_e32 v7, 0x400, v7, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, v5, v3
v_cndmask_b32_e64 v8, 4, 1, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, v5, v6
v_cndmask_b32_e64 v5, 8, 2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, v4, v3
v_cndmask_b32_e64 v9, 64, 16, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, v4, v6
s_delay_alu instid0(VALU_DEP_2)
v_or3_b32 v5, v8, v9, v5
v_cndmask_b32_e64 v4, 0x80, 32, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, v3, v6
v_cndmask_b32_e32 v3, 0x200, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_or3_b32 v3, v5, v4, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7ClassifPiS_lii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7ClassifPiS_lii, .Lfunc_end0-_Z7ClassifPiS_lii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7ClassifPiS_lii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7ClassifPiS_lii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7ClassifPiS_lii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GT.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f04070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0070*/ ISETP.GT.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f04300 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IMAD.WIDE R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0208 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R2.64+0xc] ; /* 0x00000c0402067981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000f28000c1e1900 */
/*0100*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000162000c1e1900 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x10 ; /* 0x00000010ff0b7424 */
/* 0x000fc400078e00ff */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, 0x100 ; /* 0x00000100ff0a7424 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P3, PT, R6.reuse, R5.reuse, PT ; /* 0x000000050600720c */
/* 0x0c4fe40003f66270 */
/*0140*/ ISETP.GE.AND P4, PT, R6, R4.reuse, PT ; /* 0x000000040600720c */
/* 0x088fe20003f86270 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fe200078e00ff */
/*0160*/ ISETP.GT.AND P1, PT, R5, R4.reuse, PT ; /* 0x000000040500720c */
/* 0x080fe40003f24270 */
/*0170*/ ISETP.GT.AND P2, PT, R7, R5, PT ; /* 0x000000050700720c */
/* 0x010fe40003f44270 */
/*0180*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe40003f05270 */
/*0190*/ SEL R3, R11, 0x40, P2 ; /* 0x000000400b037807 */
/* 0x001fc40001000000 */
/*01a0*/ SEL R6, R6, 0x8, !P4 ; /* 0x0000000806067807 */
/* 0x000fe40006000000 */
/*01b0*/ SEL R5, R8, 0x1, P3 ; /* 0x0000000108057807 */
/* 0x000fe40001800000 */
/*01c0*/ ISETP.GT.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe20003f44270 */
/*01d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x20 ; /* 0x00000020ff047424 */
/* 0x000fe200078e00ff */
/*01e0*/ SEL R2, R10, 0x400, P1 ; /* 0x000004000a027807 */
/* 0x000fe40000800000 */
/*01f0*/ IADD3 R6, R6, R5, R3 ; /* 0x0000000506067210 */
/* 0x000fe20007ffe003 */
/*0200*/ IMAD R3, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000037a24 */
/* 0x000fe200078e02ff */
/*0210*/ SEL R5, R4, 0x80, P2 ; /* 0x0000008004057807 */
/* 0x000fc40001000000 */
/*0220*/ SEL R0, R2, 0x200, P0 ; /* 0x0000020002007807 */
/* 0x000fe20000000000 */
/*0230*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc600078e0208 */
/*0240*/ IADD3 R5, R0, R6, R5 ; /* 0x0000000600057210 */
/* 0x000fe40007ffe005 */
/*0250*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe8000c101904 */
/*0260*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7ClassifPiS_lii
.globl _Z7ClassifPiS_lii
.p2align 8
.type _Z7ClassifPiS_lii,@function
_Z7ClassifPiS_lii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_lo_u32 v2, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_load_b32 s0, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_mul_lo_u32 v0, v1, s0
s_clause 0x1
global_load_b128 v[2:5], v[6:7], off
global_load_b32 v6, v[6:7], off offset:16
v_mov_b32_e32 v7, 0x100
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v3, v6
v_cndmask_b32_e32 v7, 0x400, v7, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, v5, v3
v_cndmask_b32_e64 v8, 4, 1, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, v5, v6
v_cndmask_b32_e64 v5, 8, 2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, v4, v3
v_cndmask_b32_e64 v9, 64, 16, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, v4, v6
s_delay_alu instid0(VALU_DEP_2)
v_or3_b32 v5, v8, v9, v5
v_cndmask_b32_e64 v4, 0x80, 32, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, v3, v6
v_cndmask_b32_e32 v3, 0x200, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_or3_b32 v3, v5, v4, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7ClassifPiS_lii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7ClassifPiS_lii, .Lfunc_end0-_Z7ClassifPiS_lii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7ClassifPiS_lii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7ClassifPiS_lii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} | code for sm_80
Function : _Z19FillAdjacencyMatrixPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x174] ; /* 0x00005d0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fe40000000000 */
/*00a0*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*00b0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00c0*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe4000fffe13f */
/*00d0*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe40000000800 */
/*00e0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc6000fffe13f */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0170*/ LOP3.LUT R2, R0, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0000027a12 */
/* 0x000fc800078e3cff */
/*0180*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0190*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01b0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01e0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*0200*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fd60003f45270 */
/*0210*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0230*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff03aa12 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, -R3.reuse, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x040fe40007ffe1ff */
/*0250*/ ISETP.GE.AND P0, PT, R3, UR5, PT ; /* 0x0000000503007c0c */
/* 0x000fc6000bf06270 */
/*0260*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fca00078e0200 */
/*0270*/ ISETP.GE.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc80008706670 */
/*0280*/ ISETP.LT.OR P0, PT, R3, 0x2, P0 ; /* 0x000000020300780c */
/* 0x000fc80000701670 */
/*0290*/ ISETP.LT.OR P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000701670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ IMAD.WIDE R2, R0, R10, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e020a */
/*02e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee2000c1e1900 */
/*0300*/ F2I.TRUNC.NTZ R6, R4 ; /* 0x0000000400067305 */
/* 0x004e30000020f100 */
/*0310*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001ee40000201400 */
/*0320*/ FSETP.NEU.AND P0, PT, R8, R5, PT ; /* 0x000000050800720b */
/* 0x008fda0003f0d000 */
/*0330*/ @P0 BRA 0x440 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R2, R0, -c[0x0][0x174], RZ ; /* 0x80005d0000027a10 */
/* 0x000fca0007ffe0ff */
/*0350*/ IMAD.WIDE R2, R2, R10, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e020a */
/*0360*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FSETP.NEU.AND P0, PT, R0, R5, PT ; /* 0x000000050000720b */
/* 0x004fda0003f0d000 */
/*0380*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0390*/ F2I.TRUNC.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x000e22000020f100 */
/*03a0*/ HFMA2.MMA R9, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff097435 */
/* 0x000fe200000001ff */
/*03b0*/ IMAD R5, R6, c[0x0][0x17c], R5 ; /* 0x00005f0006057a24 */
/* 0x001fc800078e0205 */
/*03c0*/ IMAD.WIDE R4, R5, R10, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e020a */
/*03d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ F2I.TRUNC.NTZ R7, R2 ; /* 0x0000000200077305 */
/* 0x004e24000020f100 */
/*0400*/ IMAD R7, R7, c[0x0][0x17c], R6 ; /* 0x00005f0007077a24 */
/* 0x001fc800078e0206 */
/*0410*/ IMAD.WIDE R6, R7, R10, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e020a */
/*0420*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ F2I.TRUNC.NTZ R5, R8 ; /* 0x0000000800057305 */
/* 0x000e22000020f100 */
/*0450*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R5, R6, c[0x0][0x17c], R5 ; /* 0x00005f0006057a24 */
/* 0x001fc800078e0205 */
/*0470*/ IMAD.WIDE R4, R5, R10, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e020a */
/*0480*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0490*/ LDG.E R2, [R2.64+0x4] ; /* 0x0000040402027981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ F2I.TRUNC.NTZ R7, R2 ; /* 0x0000000200077305 */
/* 0x004e24000020f100 */
/*04b0*/ IMAD R7, R7, c[0x0][0x17c], R6 ; /* 0x00005f0007077a24 */
/* 0x001fc800078e0206 */
/*04c0*/ IMAD.WIDE R6, R7, R10, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e020a */
/*04d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} | .file "tmpxft_00011b1e_00000000-6_FillAdjacencyMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
.type _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii, @function
_Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19FillAdjacencyMatrixPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii, .-_Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
.globl _Z19FillAdjacencyMatrixPfS_iiii
.type _Z19FillAdjacencyMatrixPfS_iiii, @function
_Z19FillAdjacencyMatrixPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19FillAdjacencyMatrixPfS_iiii, .-_Z19FillAdjacencyMatrixPfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19FillAdjacencyMatrixPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19FillAdjacencyMatrixPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19FillAdjacencyMatrixPfS_iiii
.globl _Z19FillAdjacencyMatrixPfS_iiii
.p2align 8
.type _Z19FillAdjacencyMatrixPfS_iiii,@function
_Z19FillAdjacencyMatrixPfS_iiii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_mul_i32 s4, s4, s15
s_add_i32 s7, s3, s6
s_and_b32 s5, s5, 0xffff
s_xor_b32 s7, s7, s6
s_add_i32 s4, s4, s14
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_add_i32 s4, s3, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s7
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_gt_i32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
v_min_i32_e32 v2, v0, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v6, 4
global_load_b64 v[3:4], v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v0
v_cmp_neq_f32_e64 s2, v4, v5
v_cmpx_eq_f32_e32 v4, v5
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, v4, v5
s_and_b32 s3, vcc_lo, exec_lo
s_or_b32 s2, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
v_cvt_i32_f32_e32 v1, v4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v6, 1.0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b32 v[4:5], v6, off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19FillAdjacencyMatrixPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19FillAdjacencyMatrixPfS_iiii, .Lfunc_end0-_Z19FillAdjacencyMatrixPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19FillAdjacencyMatrixPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19FillAdjacencyMatrixPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void FillAdjacencyMatrix(float* adj_mat , float* maskBuffer , int size , int cols , int rows ,int Nsegs){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % cols;
int irow = idx / cols;
int seg_id1=-1;
if (idx<size){
if (icol<cols-2 && irow<rows-2 && irow>1 && icol>1){
seg_id1 = maskBuffer[idx];
if (seg_id1!=maskBuffer[idx+1]){
adj_mat[ (int)maskBuffer[idx+1] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx+1] ]=1; /// it can happen that a->b, but b->a wont appear...
}
else if (seg_id1!=maskBuffer[idx-cols]){
adj_mat[ (int)maskBuffer[idx-cols] + seg_id1*Nsegs ]=1;
adj_mat[ seg_id1 + Nsegs*(int)maskBuffer[idx-cols] ]=1; /// it can happen that a->b, but b->a wont appear...
}
}
}
} | .text
.file "FillAdjacencyMatrix.hip"
.globl _Z34__device_stub__FillAdjacencyMatrixPfS_iiii # -- Begin function _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.p2align 4, 0x90
.type _Z34__device_stub__FillAdjacencyMatrixPfS_iiii,@function
_Z34__device_stub__FillAdjacencyMatrixPfS_iiii: # @_Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19FillAdjacencyMatrixPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__FillAdjacencyMatrixPfS_iiii, .Lfunc_end0-_Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19FillAdjacencyMatrixPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19FillAdjacencyMatrixPfS_iiii,@object # @_Z19FillAdjacencyMatrixPfS_iiii
.section .rodata,"a",@progbits
.globl _Z19FillAdjacencyMatrixPfS_iiii
.p2align 3, 0x0
_Z19FillAdjacencyMatrixPfS_iiii:
.quad _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.size _Z19FillAdjacencyMatrixPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19FillAdjacencyMatrixPfS_iiii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19FillAdjacencyMatrixPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19FillAdjacencyMatrixPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x174] ; /* 0x00005d0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fe40000000000 */
/*00a0*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*00b0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*00c0*/ UIADD3 UR5, -UR4, UR5, URZ ; /* 0x0000000504057290 */
/* 0x000fe4000fffe13f */
/*00d0*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe40000000800 */
/*00e0*/ UIADD3 UR4, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc6000fffe13f */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0170*/ LOP3.LUT R2, R0, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0000027a12 */
/* 0x000fc800078e3cff */
/*0180*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0190*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01b0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01e0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*0200*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fd60003f45270 */
/*0210*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0230*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff03aa12 */
/* 0x000fc800078e33ff */
/*0240*/ IADD3 R5, -R3.reuse, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x040fe40007ffe1ff */
/*0250*/ ISETP.GE.AND P0, PT, R3, UR5, PT ; /* 0x0000000503007c0c */
/* 0x000fc6000bf06270 */
/*0260*/ IMAD R2, R5, c[0x0][0x174], R0 ; /* 0x00005d0005027a24 */
/* 0x000fca00078e0200 */
/*0270*/ ISETP.GE.OR P0, PT, R2, UR4, P0 ; /* 0x0000000402007c0c */
/* 0x000fc80008706670 */
/*0280*/ ISETP.LT.OR P0, PT, R3, 0x2, P0 ; /* 0x000000020300780c */
/* 0x000fc80000701670 */
/*0290*/ ISETP.LT.OR P0, PT, R2, 0x2, P0 ; /* 0x000000020200780c */
/* 0x000fda0000701670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ IMAD.WIDE R2, R0, R10, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e020a */
/*02e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee2000c1e1900 */
/*0300*/ F2I.TRUNC.NTZ R6, R4 ; /* 0x0000000400067305 */
/* 0x004e30000020f100 */
/*0310*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001ee40000201400 */
/*0320*/ FSETP.NEU.AND P0, PT, R8, R5, PT ; /* 0x000000050800720b */
/* 0x008fda0003f0d000 */
/*0330*/ @P0 BRA 0x440 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R2, R0, -c[0x0][0x174], RZ ; /* 0x80005d0000027a10 */
/* 0x000fca0007ffe0ff */
/*0350*/ IMAD.WIDE R2, R2, R10, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e020a */
/*0360*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FSETP.NEU.AND P0, PT, R0, R5, PT ; /* 0x000000050000720b */
/* 0x004fda0003f0d000 */
/*0380*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0390*/ F2I.TRUNC.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x000e22000020f100 */
/*03a0*/ HFMA2.MMA R9, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff097435 */
/* 0x000fe200000001ff */
/*03b0*/ IMAD R5, R6, c[0x0][0x17c], R5 ; /* 0x00005f0006057a24 */
/* 0x001fc800078e0205 */
/*03c0*/ IMAD.WIDE R4, R5, R10, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e020a */
/*03d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ F2I.TRUNC.NTZ R7, R2 ; /* 0x0000000200077305 */
/* 0x004e24000020f100 */
/*0400*/ IMAD R7, R7, c[0x0][0x17c], R6 ; /* 0x00005f0007077a24 */
/* 0x001fc800078e0206 */
/*0410*/ IMAD.WIDE R6, R7, R10, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e020a */
/*0420*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ F2I.TRUNC.NTZ R5, R8 ; /* 0x0000000800057305 */
/* 0x000e22000020f100 */
/*0450*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R5, R6, c[0x0][0x17c], R5 ; /* 0x00005f0006057a24 */
/* 0x001fc800078e0205 */
/*0470*/ IMAD.WIDE R4, R5, R10, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e020a */
/*0480*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0490*/ LDG.E R2, [R2.64+0x4] ; /* 0x0000040402027981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ F2I.TRUNC.NTZ R7, R2 ; /* 0x0000000200077305 */
/* 0x004e24000020f100 */
/*04b0*/ IMAD R7, R7, c[0x0][0x17c], R6 ; /* 0x00005f0007077a24 */
/* 0x001fc800078e0206 */
/*04c0*/ IMAD.WIDE R6, R7, R10, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e020a */
/*04d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19FillAdjacencyMatrixPfS_iiii
.globl _Z19FillAdjacencyMatrixPfS_iiii
.p2align 8
.type _Z19FillAdjacencyMatrixPfS_iiii,@function
_Z19FillAdjacencyMatrixPfS_iiii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_mul_i32 s4, s4, s15
s_add_i32 s7, s3, s6
s_and_b32 s5, s5, 0xffff
s_xor_b32 s7, s7, s6
s_add_i32 s4, s4, s14
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_add_i32 s4, s3, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s7
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_gt_i32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
v_min_i32_e32 v2, v0, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_lt_i32_e64 s2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v6, 4
global_load_b64 v[3:4], v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v0
v_cmp_neq_f32_e64 s2, v4, v5
v_cmpx_eq_f32_e32 v4, v5
s_cbranch_execz .LBB0_4
v_subrev_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, v4, v5
s_and_b32 s3, vcc_lo, exec_lo
s_or_b32 s2, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
v_cvt_i32_f32_e32 v1, v4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v6, 1.0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b32 v[4:5], v6, off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19FillAdjacencyMatrixPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19FillAdjacencyMatrixPfS_iiii, .Lfunc_end0-_Z19FillAdjacencyMatrixPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19FillAdjacencyMatrixPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19FillAdjacencyMatrixPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00011b1e_00000000-6_FillAdjacencyMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
.type _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii, @function
_Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19FillAdjacencyMatrixPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii, .-_Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
.globl _Z19FillAdjacencyMatrixPfS_iiii
.type _Z19FillAdjacencyMatrixPfS_iiii, @function
_Z19FillAdjacencyMatrixPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19FillAdjacencyMatrixPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19FillAdjacencyMatrixPfS_iiii, .-_Z19FillAdjacencyMatrixPfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19FillAdjacencyMatrixPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19FillAdjacencyMatrixPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FillAdjacencyMatrix.hip"
.globl _Z34__device_stub__FillAdjacencyMatrixPfS_iiii # -- Begin function _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.p2align 4, 0x90
.type _Z34__device_stub__FillAdjacencyMatrixPfS_iiii,@function
_Z34__device_stub__FillAdjacencyMatrixPfS_iiii: # @_Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19FillAdjacencyMatrixPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__FillAdjacencyMatrixPfS_iiii, .Lfunc_end0-_Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19FillAdjacencyMatrixPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19FillAdjacencyMatrixPfS_iiii,@object # @_Z19FillAdjacencyMatrixPfS_iiii
.section .rodata,"a",@progbits
.globl _Z19FillAdjacencyMatrixPfS_iiii
.p2align 3, 0x0
_Z19FillAdjacencyMatrixPfS_iiii:
.quad _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.size _Z19FillAdjacencyMatrixPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19FillAdjacencyMatrixPfS_iiii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__FillAdjacencyMatrixPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19FillAdjacencyMatrixPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define MAX_VALUE 5600
#define MAX_STRING_LENGTH 4096
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
// global variables:
// d_A: the huge string buffer in GPU
// d_B: start position of each line in d_A
// d_C: length of each line in d_A
// d_D: stores the pattern in GPU
char *d_A;
int *d_B;
int *d_C;
char *d_D;
cudaError_t err;
//kernel function: each thread gets its corresponding line and search the pattern in the naive way.
__global__ void grep (char* d_A, int * d_B, int * d_C, char * d_D, int arrayLength,int patternLength ) {
// get the index of the thread.
int threadIndex = blockDim.x * blockIdx.x + threadIdx.x;
// only the thread whose index is less than the 4096 does the search
if (threadIndex < arrayLength) {
int flag = 1;
// match algorithm: naive
// if the length of each substring is less than the size of the pattern, there is certainly no match. Just return
if(d_C[threadIndex] <patternLength ){
flag=0;
return;
}
else {
// use a for loop to search from every possible position.
for(int i = d_B[threadIndex]; i < d_B[threadIndex] + d_C[threadIndex] + 1 - patternLength ; i ++ ){
flag =1;
int k = i ;
for( int j = 0 ; j < patternLength && flag == 1 ; j ++ ) {
if(d_A[k + j ]!= d_D[j])
flag = 0;
}
// if match ,print and return.
if(flag==1) {
printf("%s\n",d_A+d_B[threadIndex]);
return ;
}
}
}
}
}
// allocate GPU memory, only 4 blocks of memory in GPU are required.
void allocDeviceMemory(int totalstringSize ){
err = cudaMalloc((char **) &d_A, sizeof(char)*MAX_STRING_LENGTH*MAX_VALUE);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_B, sizeof(int)*MAX_STRING_LENGTH);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_C, sizeof(int)*MAX_STRING_LENGTH );
CHECK_ERR(err);
err = cudaMalloc((char **) &d_D, sizeof(char)*MAX_STRING_LENGTH );
CHECK_ERR(err);
}
// copy the string buffer, start position array and string length array to GPU.
void copytoDeviceMemory(char * result, int * start, int * stringSize, char * pattern, int totalstringSize){
err = cudaMemcpy(d_A, result, sizeof(char)*totalstringSize, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_B, start, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_C, stringSize, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
}
// before terminates the program, free the GPU memory.
void freeDeviceMemory()
{
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_D);
}
int main(int argc, char *argv[])
{
int lineNumber, n;
FILE *f;
f = fopen(argv[1], "r");
if (f == NULL) {
printf("can't open %s:", argv[1]);
}
// result is the huge string buffer in CPU end
// pattern is the string you are looking for.
// start array stores the start position of each string in the buffer.
// stringSize sotres each string's real length.
// totalstringSize records the total lengths of the current 4096 lines of string.
char * result = (char *)malloc(sizeof(char)*MAX_VALUE * MAX_STRING_LENGTH);
char * pattern = (char *)malloc(sizeof(char)*MAX_VALUE);
int start[MAX_STRING_LENGTH];
int stringSize[MAX_STRING_LENGTH];
int totalstringSize=0;
// line number the line index the current file descriptor is reading.
lineNumber = 0;
n=0;
// initializing...
for(int i = 0; i < MAX_STRING_LENGTH; i ++ ) {
start[i] = 0;
stringSize[i] = 0;
}
totalstringSize = 0;
strcat(pattern,argv[2]);
// allocate memory in GPU.
allocDeviceMemory(totalstringSize);
// pattern only needs to be copied to GPU once. Thus do it first.
err = cudaMemcpy(d_D, pattern, sizeof(char)*strlen(pattern), cudaMemcpyHostToDevice);
CHECK_ERR(err);
// each while loop ,we read 4096 lines of strings to the buffer string.
while (fgets(result+start[lineNumber%MAX_STRING_LENGTH], MAX_VALUE, f) != NULL) {
n = strlen(result+start[lineNumber%MAX_STRING_LENGTH]);
// save the current string to the huge buffer string
if (n > 0 && *(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) == '\n'){
*(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) = '\0';
}
// save the correct start position and string length.
if(lineNumber%MAX_STRING_LENGTH < MAX_STRING_LENGTH-1) {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
start[lineNumber%MAX_STRING_LENGTH + 1] = start[lineNumber%MAX_STRING_LENGTH] + stringSize[lineNumber%MAX_STRING_LENGTH];
}
else {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
}
totalstringSize += n;
lineNumber ++;
// send the 4096 lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH == 0) {
// copy first
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
grep<<<16,256>>>(d_A, d_B, d_C, d_D, MAX_STRING_LENGTH,strlen(pattern));
// reset the buffer and other variables.
memset(result,'\0',sizeof(result));
totalstringSize = 0;
start[0]=0;
}
}
// send the remaining lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH !=0) {
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
// only copy lineNumber%MAX_STRING_LENGTH strings to GPU.
grep<<<16,256>>>(d_A, d_B, d_C, d_D,lineNumber % MAX_STRING_LENGTH,strlen(pattern) );
// free the memory finally
freeDeviceMemory();
}
return 0;
} | code for sm_80
Function : _Z4grepPcPiS0_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R4, [R2.64] ; /* 0x0000002402047981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x184], PT ; /* 0x0000610004007a0c */
/* 0x004fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00e0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f1403 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000002402007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R5, R0, -c[0x0][0x184], R7 ; /* 0x8000610000057a10 */
/* 0x004fca0007ffe007 */
/*0130*/ IMAD.IADD R9, R4, 0x1, R5 ; /* 0x0000000104097824 */
/* 0x000fca00078e0205 */
/*0140*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fda0003f06270 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ ISETP.LE.AND P0, PT, R7, c[0x0][0x184], PT ; /* 0x0000610007007a0c */
/* 0x000fe20003f03270 */
/*0170*/ BSSY B0, 0x300 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0180*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0190*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fcc00008e06ff */
/*01a0*/ @!P0 BRA 0x2f0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*01c0*/ BSSY B1, 0x2a0 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.IADD R5, R11.reuse, 0x1, R8 ; /* 0x000000010b057824 */
/* 0x040fe200078e0208 */
/*01f0*/ IADD3 R2, P1, R11, c[0x0][0x178], RZ ; /* 0x00005e000b027a10 */
/* 0x000fc80007f3e0ff */
/*0200*/ IADD3 R4, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005047a10 */
/* 0x000fe40007f1e0ff */
/*0210*/ LEA.HI.X.SX32 R3, R11, c[0x0][0x17c], 0x1, P1 ; /* 0x00005f000b037a11 */
/* 0x000fe400008f0eff */
/*0220*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P0 ; /* 0x0000590005057a11 */
/* 0x000fc600000f0eff */
/*0230*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea8000c1e1100 */
/*0240*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000002404057981 */
/* 0x000ea2000c1e1100 */
/*0250*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.LT.AND P1, PT, R11, c[0x0][0x184], PT ; /* 0x000061000b007a0c */
/* 0x000fe40003f21270 */
/*0270*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*0280*/ @!P0 BRA P1, 0x1e0 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ @!P0 BRA 0x2f0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fda0003f06270 */
/*02d0*/ @!P0 BRA 0x1c0 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R8, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x040fe20007f1e0ff */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0320*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0340*/ LEA.HI.X.SX32 R9, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000097a11 */
/* 0x000fc800000f0eff */
/*0350*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0360*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e80000100a00 */
/*0370*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe20000000000 */
/*0380*/ MOV R11, 0x3f0 ; /* 0x000003f0000b7802 */
/* 0x000fe40000000f00 */
/*0390*/ MOV R20, 0x370 ; /* 0x0000037000147802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*03d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*03e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ BRA 0x400; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define MAX_VALUE 5600
#define MAX_STRING_LENGTH 4096
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
// global variables:
// d_A: the huge string buffer in GPU
// d_B: start position of each line in d_A
// d_C: length of each line in d_A
// d_D: stores the pattern in GPU
char *d_A;
int *d_B;
int *d_C;
char *d_D;
cudaError_t err;
//kernel function: each thread gets its corresponding line and search the pattern in the naive way.
__global__ void grep (char* d_A, int * d_B, int * d_C, char * d_D, int arrayLength,int patternLength ) {
// get the index of the thread.
int threadIndex = blockDim.x * blockIdx.x + threadIdx.x;
// only the thread whose index is less than the 4096 does the search
if (threadIndex < arrayLength) {
int flag = 1;
// match algorithm: naive
// if the length of each substring is less than the size of the pattern, there is certainly no match. Just return
if(d_C[threadIndex] <patternLength ){
flag=0;
return;
}
else {
// use a for loop to search from every possible position.
for(int i = d_B[threadIndex]; i < d_B[threadIndex] + d_C[threadIndex] + 1 - patternLength ; i ++ ){
flag =1;
int k = i ;
for( int j = 0 ; j < patternLength && flag == 1 ; j ++ ) {
if(d_A[k + j ]!= d_D[j])
flag = 0;
}
// if match ,print and return.
if(flag==1) {
printf("%s\n",d_A+d_B[threadIndex]);
return ;
}
}
}
}
}
// allocate GPU memory, only 4 blocks of memory in GPU are required.
void allocDeviceMemory(int totalstringSize ){
err = cudaMalloc((char **) &d_A, sizeof(char)*MAX_STRING_LENGTH*MAX_VALUE);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_B, sizeof(int)*MAX_STRING_LENGTH);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_C, sizeof(int)*MAX_STRING_LENGTH );
CHECK_ERR(err);
err = cudaMalloc((char **) &d_D, sizeof(char)*MAX_STRING_LENGTH );
CHECK_ERR(err);
}
// copy the string buffer, start position array and string length array to GPU.
void copytoDeviceMemory(char * result, int * start, int * stringSize, char * pattern, int totalstringSize){
err = cudaMemcpy(d_A, result, sizeof(char)*totalstringSize, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_B, start, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_C, stringSize, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
}
// before terminates the program, free the GPU memory.
void freeDeviceMemory()
{
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_D);
}
int main(int argc, char *argv[])
{
int lineNumber, n;
FILE *f;
f = fopen(argv[1], "r");
if (f == NULL) {
printf("can't open %s:", argv[1]);
}
// result is the huge string buffer in CPU end
// pattern is the string you are looking for.
// start array stores the start position of each string in the buffer.
// stringSize sotres each string's real length.
// totalstringSize records the total lengths of the current 4096 lines of string.
char * result = (char *)malloc(sizeof(char)*MAX_VALUE * MAX_STRING_LENGTH);
char * pattern = (char *)malloc(sizeof(char)*MAX_VALUE);
int start[MAX_STRING_LENGTH];
int stringSize[MAX_STRING_LENGTH];
int totalstringSize=0;
// line number the line index the current file descriptor is reading.
lineNumber = 0;
n=0;
// initializing...
for(int i = 0; i < MAX_STRING_LENGTH; i ++ ) {
start[i] = 0;
stringSize[i] = 0;
}
totalstringSize = 0;
strcat(pattern,argv[2]);
// allocate memory in GPU.
allocDeviceMemory(totalstringSize);
// pattern only needs to be copied to GPU once. Thus do it first.
err = cudaMemcpy(d_D, pattern, sizeof(char)*strlen(pattern), cudaMemcpyHostToDevice);
CHECK_ERR(err);
// each while loop ,we read 4096 lines of strings to the buffer string.
while (fgets(result+start[lineNumber%MAX_STRING_LENGTH], MAX_VALUE, f) != NULL) {
n = strlen(result+start[lineNumber%MAX_STRING_LENGTH]);
// save the current string to the huge buffer string
if (n > 0 && *(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) == '\n'){
*(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) = '\0';
}
// save the correct start position and string length.
if(lineNumber%MAX_STRING_LENGTH < MAX_STRING_LENGTH-1) {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
start[lineNumber%MAX_STRING_LENGTH + 1] = start[lineNumber%MAX_STRING_LENGTH] + stringSize[lineNumber%MAX_STRING_LENGTH];
}
else {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
}
totalstringSize += n;
lineNumber ++;
// send the 4096 lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH == 0) {
// copy first
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
grep<<<16,256>>>(d_A, d_B, d_C, d_D, MAX_STRING_LENGTH,strlen(pattern));
// reset the buffer and other variables.
memset(result,'\0',sizeof(result));
totalstringSize = 0;
start[0]=0;
}
}
// send the remaining lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH !=0) {
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
// only copy lineNumber%MAX_STRING_LENGTH strings to GPU.
grep<<<16,256>>>(d_A, d_B, d_C, d_D,lineNumber % MAX_STRING_LENGTH,strlen(pattern) );
// free the memory finally
freeDeviceMemory();
}
return 0;
} | .file "tmpxft_00009f8f_00000000-6_grep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tianyangche/cs550pa4/master/grep.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z17allocDeviceMemoryi
.type _Z17allocDeviceMemoryi, @function
_Z17allocDeviceMemoryi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $22937600, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L9
movl $16384, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L10
movl $16384, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L11
movl $4096, %esi
leaq d_D(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L12
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $63, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L10:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $66, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L11:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $72, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17allocDeviceMemoryi, .-_Z17allocDeviceMemoryi
.globl _Z18copytoDeviceMemoryPcPiS0_S_i
.type _Z18copytoDeviceMemoryPcPiS0_S_i, @function
_Z18copytoDeviceMemoryPcPiS0_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movslq %r8d, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L18
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L19
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq d_C(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L20
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $82, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z18copytoDeviceMemoryPcPiS0_S_i, .-_Z18copytoDeviceMemoryPcPiS0_S_i
.globl _Z16freeDeviceMemoryv
.type _Z16freeDeviceMemoryv, @function
_Z16freeDeviceMemoryv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
movq d_D(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z16freeDeviceMemoryv, .-_Z16freeDeviceMemoryv
.globl _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
.type _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii, @function
_Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4grepPcPiS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii, .-_Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
.globl _Z4grepPcPiS0_S_ii
.type _Z4grepPcPiS0_S_ii, @function
_Z4grepPcPiS0_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z4grepPcPiS0_S_ii, .-_Z4grepPcPiS0_S_ii
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "can't open %s:"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32824
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 32912
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 32840(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L47
.L32:
movl $22937600, %edi
call malloc@PLT
movq %rax, %r12
movl $5600, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $0, %eax
.L33:
movl $0, 64(%rsp,%rax)
movl $0, 16448(%rsp,%rax)
addq $4, %rax
cmpq $16384, %rax
jne .L33
movq 16(%rbx), %rsi
movl $5600, %edx
movq 16(%rsp), %rbx
movq %rbx, %rdi
call __strcat_chk@PLT
movl $0, %edi
call _Z17allocDeviceMemoryi
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq d_D(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L48
movl $0, %r14d
movl $0, %ebp
leaq 16448(%rsp), %rax
movq %rax, 24(%rsp)
jmp .L34
.L47:
movq 8(%rbx), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L32
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $138, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
cmpl $4094, %ebx
jg .L36
movslq %ebx, %rdx
movl %eax, 16448(%rsp,%rdx,4)
addl $1, %ebx
movslq %ebx, %rbx
addl %eax, %r13d
movl %r13d, 64(%rsp,%rbx,4)
.L37:
addl %eax, %r14d
addl $1, %ebp
movl %ebp, %ebx
andl $4095, %ebx
je .L49
.L34:
movl %ebp, %eax
sarl $31, %eax
shrl $20, %eax
leal 0(%rbp,%rax), %ebx
andl $4095, %ebx
subl %eax, %ebx
movslq %ebx, %rax
movslq 64(%rsp,%rax,4), %rdi
movl $22937600, %esi
cmpq %rsi, %rdi
cmovnb %rdi, %rsi
subq %rdi, %rsi
addq %r12, %rdi
movq 8(%rsp), %rcx
movl $5600, %edx
call __fgets_chk@PLT
testq %rax, %rax
je .L50
movslq %ebx, %rax
movl 64(%rsp,%rax,4), %r13d
movslq %r13d, %r15
leaq (%r12,%r15), %rdi
call strlen@PLT
testl %eax, %eax
jle .L35
movslq %eax, %rdx
leaq -1(%r15,%rdx), %rdx
addq %r12, %rdx
cmpb $10, (%rdx)
jne .L35
movb $0, (%rdx)
jmp .L35
.L36:
movl %eax, 32828(%rsp)
jmp .L37
.L49:
leaq 64(%rsp), %rsi
movl %r14d, %r8d
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %r12, %rdi
call _Z18copytoDeviceMemoryPcPiS0_S_i
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
movq $0, (%r12)
movl $0, 64(%rsp)
movl %ebx, %r14d
jmp .L34
.L51:
movq 16(%rsp), %rdi
call strlen@PLT
movl %eax, %r9d
movl $4096, %r8d
movq d_D(%rip), %rcx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
jmp .L39
.L50:
testl $4095, %ebp
jne .L52
.L41:
movq 32840(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $32856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq 16448(%rsp), %rdx
leaq 64(%rsp), %rsi
movl %r14d, %r8d
movq 16(%rsp), %rcx
movq %r12, %rdi
call _Z18copytoDeviceMemoryPcPiS0_S_i
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L42:
call _Z16freeDeviceMemoryv
jmp .L41
.L54:
movq 16(%rsp), %rdi
call strlen@PLT
movl %eax, %r9d
movl %ebx, %r8d
movq d_D(%rip), %rcx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4grepPcPiS0_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4grepPcPiS0_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl err
.bss
.align 4
.type err, @object
.size err, 4
err:
.zero 4
.globl d_D
.align 8
.type d_D, @object
.size d_D, 8
d_D:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define MAX_VALUE 5600
#define MAX_STRING_LENGTH 4096
#define CHECK_ERR(x) \
if (x != cudaSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
cudaGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
// global variables:
// d_A: the huge string buffer in GPU
// d_B: start position of each line in d_A
// d_C: length of each line in d_A
// d_D: stores the pattern in GPU
char *d_A;
int *d_B;
int *d_C;
char *d_D;
cudaError_t err;
//kernel function: each thread gets its corresponding line and search the pattern in the naive way.
__global__ void grep (char* d_A, int * d_B, int * d_C, char * d_D, int arrayLength,int patternLength ) {
// get the index of the thread.
int threadIndex = blockDim.x * blockIdx.x + threadIdx.x;
// only the thread whose index is less than the 4096 does the search
if (threadIndex < arrayLength) {
int flag = 1;
// match algorithm: naive
// if the length of each substring is less than the size of the pattern, there is certainly no match. Just return
if(d_C[threadIndex] <patternLength ){
flag=0;
return;
}
else {
// use a for loop to search from every possible position.
for(int i = d_B[threadIndex]; i < d_B[threadIndex] + d_C[threadIndex] + 1 - patternLength ; i ++ ){
flag =1;
int k = i ;
for( int j = 0 ; j < patternLength && flag == 1 ; j ++ ) {
if(d_A[k + j ]!= d_D[j])
flag = 0;
}
// if match ,print and return.
if(flag==1) {
printf("%s\n",d_A+d_B[threadIndex]);
return ;
}
}
}
}
}
// allocate GPU memory, only 4 blocks of memory in GPU are required.
void allocDeviceMemory(int totalstringSize ){
err = cudaMalloc((char **) &d_A, sizeof(char)*MAX_STRING_LENGTH*MAX_VALUE);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_B, sizeof(int)*MAX_STRING_LENGTH);
CHECK_ERR(err);
err = cudaMalloc((int **) &d_C, sizeof(int)*MAX_STRING_LENGTH );
CHECK_ERR(err);
err = cudaMalloc((char **) &d_D, sizeof(char)*MAX_STRING_LENGTH );
CHECK_ERR(err);
}
// copy the string buffer, start position array and string length array to GPU.
void copytoDeviceMemory(char * result, int * start, int * stringSize, char * pattern, int totalstringSize){
err = cudaMemcpy(d_A, result, sizeof(char)*totalstringSize, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_B, start, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
err = cudaMemcpy(d_C, stringSize, sizeof(int)*MAX_STRING_LENGTH, cudaMemcpyHostToDevice);
CHECK_ERR(err);
}
// before terminates the program, free the GPU memory.
void freeDeviceMemory()
{
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(d_D);
}
int main(int argc, char *argv[])
{
int lineNumber, n;
FILE *f;
f = fopen(argv[1], "r");
if (f == NULL) {
printf("can't open %s:", argv[1]);
}
// result is the huge string buffer in CPU end
// pattern is the string you are looking for.
// start array stores the start position of each string in the buffer.
// stringSize sotres each string's real length.
// totalstringSize records the total lengths of the current 4096 lines of string.
char * result = (char *)malloc(sizeof(char)*MAX_VALUE * MAX_STRING_LENGTH);
char * pattern = (char *)malloc(sizeof(char)*MAX_VALUE);
int start[MAX_STRING_LENGTH];
int stringSize[MAX_STRING_LENGTH];
int totalstringSize=0;
// line number the line index the current file descriptor is reading.
lineNumber = 0;
n=0;
// initializing...
for(int i = 0; i < MAX_STRING_LENGTH; i ++ ) {
start[i] = 0;
stringSize[i] = 0;
}
totalstringSize = 0;
strcat(pattern,argv[2]);
// allocate memory in GPU.
allocDeviceMemory(totalstringSize);
// pattern only needs to be copied to GPU once. Thus do it first.
err = cudaMemcpy(d_D, pattern, sizeof(char)*strlen(pattern), cudaMemcpyHostToDevice);
CHECK_ERR(err);
// each while loop ,we read 4096 lines of strings to the buffer string.
while (fgets(result+start[lineNumber%MAX_STRING_LENGTH], MAX_VALUE, f) != NULL) {
n = strlen(result+start[lineNumber%MAX_STRING_LENGTH]);
// save the current string to the huge buffer string
if (n > 0 && *(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) == '\n'){
*(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) = '\0';
}
// save the correct start position and string length.
if(lineNumber%MAX_STRING_LENGTH < MAX_STRING_LENGTH-1) {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
start[lineNumber%MAX_STRING_LENGTH + 1] = start[lineNumber%MAX_STRING_LENGTH] + stringSize[lineNumber%MAX_STRING_LENGTH];
}
else {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
}
totalstringSize += n;
lineNumber ++;
// send the 4096 lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH == 0) {
// copy first
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
grep<<<16,256>>>(d_A, d_B, d_C, d_D, MAX_STRING_LENGTH,strlen(pattern));
// reset the buffer and other variables.
memset(result,'\0',sizeof(result));
totalstringSize = 0;
start[0]=0;
}
}
// send the remaining lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH !=0) {
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
// only copy lineNumber%MAX_STRING_LENGTH strings to GPU.
grep<<<16,256>>>(d_A, d_B, d_C, d_D,lineNumber % MAX_STRING_LENGTH,strlen(pattern) );
// free the memory finally
freeDeviceMemory();
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define MAX_VALUE 5600
#define MAX_STRING_LENGTH 4096
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
// global variables:
// d_A: the huge string buffer in GPU
// d_B: start position of each line in d_A
// d_C: length of each line in d_A
// d_D: stores the pattern in GPU
char *d_A;
int *d_B;
int *d_C;
char *d_D;
hipError_t err;
//kernel function: each thread gets its corresponding line and search the pattern in the naive way.
__global__ void grep (char* d_A, int * d_B, int * d_C, char * d_D, int arrayLength,int patternLength ) {
// get the index of the thread.
int threadIndex = blockDim.x * blockIdx.x + threadIdx.x;
// only the thread whose index is less than the 4096 does the search
if (threadIndex < arrayLength) {
int flag = 1;
// match algorithm: naive
// if the length of each substring is less than the size of the pattern, there is certainly no match. Just return
if(d_C[threadIndex] <patternLength ){
flag=0;
return;
}
else {
// use a for loop to search from every possible position.
for(int i = d_B[threadIndex]; i < d_B[threadIndex] + d_C[threadIndex] + 1 - patternLength ; i ++ ){
flag =1;
int k = i ;
for( int j = 0 ; j < patternLength && flag == 1 ; j ++ ) {
if(d_A[k + j ]!= d_D[j])
flag = 0;
}
// if match ,print and return.
if(flag==1) {
printf("%s\n",d_A+d_B[threadIndex]);
return ;
}
}
}
}
}
// allocate GPU memory, only 4 blocks of memory in GPU are required.
void allocDeviceMemory(int totalstringSize ){
err = hipMalloc((char **) &d_A, sizeof(char)*MAX_STRING_LENGTH*MAX_VALUE);
CHECK_ERR(err);
err = hipMalloc((int **) &d_B, sizeof(int)*MAX_STRING_LENGTH);
CHECK_ERR(err);
err = hipMalloc((int **) &d_C, sizeof(int)*MAX_STRING_LENGTH );
CHECK_ERR(err);
err = hipMalloc((char **) &d_D, sizeof(char)*MAX_STRING_LENGTH );
CHECK_ERR(err);
}
// copy the string buffer, start position array and string length array to GPU.
void copytoDeviceMemory(char * result, int * start, int * stringSize, char * pattern, int totalstringSize){
err = hipMemcpy(d_A, result, sizeof(char)*totalstringSize, hipMemcpyHostToDevice);
CHECK_ERR(err);
err = hipMemcpy(d_B, start, sizeof(int)*MAX_STRING_LENGTH, hipMemcpyHostToDevice);
CHECK_ERR(err);
err = hipMemcpy(d_C, stringSize, sizeof(int)*MAX_STRING_LENGTH, hipMemcpyHostToDevice);
CHECK_ERR(err);
}
// before terminates the program, free the GPU memory.
void freeDeviceMemory()
{
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(d_D);
}
int main(int argc, char *argv[])
{
int lineNumber, n;
FILE *f;
f = fopen(argv[1], "r");
if (f == NULL) {
printf("can't open %s:", argv[1]);
}
// result is the huge string buffer in CPU end
// pattern is the string you are looking for.
// start array stores the start position of each string in the buffer.
// stringSize sotres each string's real length.
// totalstringSize records the total lengths of the current 4096 lines of string.
char * result = (char *)malloc(sizeof(char)*MAX_VALUE * MAX_STRING_LENGTH);
char * pattern = (char *)malloc(sizeof(char)*MAX_VALUE);
int start[MAX_STRING_LENGTH];
int stringSize[MAX_STRING_LENGTH];
int totalstringSize=0;
// line number the line index the current file descriptor is reading.
lineNumber = 0;
n=0;
// initializing...
for(int i = 0; i < MAX_STRING_LENGTH; i ++ ) {
start[i] = 0;
stringSize[i] = 0;
}
totalstringSize = 0;
strcat(pattern,argv[2]);
// allocate memory in GPU.
allocDeviceMemory(totalstringSize);
// pattern only needs to be copied to GPU once. Thus do it first.
err = hipMemcpy(d_D, pattern, sizeof(char)*strlen(pattern), hipMemcpyHostToDevice);
CHECK_ERR(err);
// each while loop ,we read 4096 lines of strings to the buffer string.
while (fgets(result+start[lineNumber%MAX_STRING_LENGTH], MAX_VALUE, f) != NULL) {
n = strlen(result+start[lineNumber%MAX_STRING_LENGTH]);
// save the current string to the huge buffer string
if (n > 0 && *(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) == '\n'){
*(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) = '\0';
}
// save the correct start position and string length.
if(lineNumber%MAX_STRING_LENGTH < MAX_STRING_LENGTH-1) {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
start[lineNumber%MAX_STRING_LENGTH + 1] = start[lineNumber%MAX_STRING_LENGTH] + stringSize[lineNumber%MAX_STRING_LENGTH];
}
else {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
}
totalstringSize += n;
lineNumber ++;
// send the 4096 lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH == 0) {
// copy first
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
grep<<<16,256>>>(d_A, d_B, d_C, d_D, MAX_STRING_LENGTH,strlen(pattern));
// reset the buffer and other variables.
memset(result,'\0',sizeof(result));
totalstringSize = 0;
start[0]=0;
}
}
// send the remaining lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH !=0) {
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
// only copy lineNumber%MAX_STRING_LENGTH strings to GPU.
grep<<<16,256>>>(d_A, d_B, d_C, d_D,lineNumber % MAX_STRING_LENGTH,strlen(pattern) );
// free the memory finally
freeDeviceMemory();
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#define MAX_VALUE 5600
#define MAX_STRING_LENGTH 4096
#define CHECK_ERR(x) \
if (x != hipSuccess) { \
fprintf(stderr,"%s in %s at line %d\n", \
hipGetErrorString(err),__FILE__,__LINE__); \
exit(-1); \
} \
// global variables:
// d_A: the huge string buffer in GPU
// d_B: start position of each line in d_A
// d_C: length of each line in d_A
// d_D: stores the pattern in GPU
char *d_A;
int *d_B;
int *d_C;
char *d_D;
hipError_t err;
//kernel function: each thread gets its corresponding line and search the pattern in the naive way.
__global__ void grep (char* d_A, int * d_B, int * d_C, char * d_D, int arrayLength,int patternLength ) {
// get the index of the thread.
int threadIndex = blockDim.x * blockIdx.x + threadIdx.x;
// only the thread whose index is less than the 4096 does the search
if (threadIndex < arrayLength) {
int flag = 1;
// match algorithm: naive
// if the length of each substring is less than the size of the pattern, there is certainly no match. Just return
if(d_C[threadIndex] <patternLength ){
flag=0;
return;
}
else {
// use a for loop to search from every possible position.
for(int i = d_B[threadIndex]; i < d_B[threadIndex] + d_C[threadIndex] + 1 - patternLength ; i ++ ){
flag =1;
int k = i ;
for( int j = 0 ; j < patternLength && flag == 1 ; j ++ ) {
if(d_A[k + j ]!= d_D[j])
flag = 0;
}
// if match ,print and return.
if(flag==1) {
printf("%s\n",d_A+d_B[threadIndex]);
return ;
}
}
}
}
}
// allocate GPU memory, only 4 blocks of memory in GPU are required.
void allocDeviceMemory(int totalstringSize ){
err = hipMalloc((char **) &d_A, sizeof(char)*MAX_STRING_LENGTH*MAX_VALUE);
CHECK_ERR(err);
err = hipMalloc((int **) &d_B, sizeof(int)*MAX_STRING_LENGTH);
CHECK_ERR(err);
err = hipMalloc((int **) &d_C, sizeof(int)*MAX_STRING_LENGTH );
CHECK_ERR(err);
err = hipMalloc((char **) &d_D, sizeof(char)*MAX_STRING_LENGTH );
CHECK_ERR(err);
}
// copy the string buffer, start position array and string length array to GPU.
void copytoDeviceMemory(char * result, int * start, int * stringSize, char * pattern, int totalstringSize){
err = hipMemcpy(d_A, result, sizeof(char)*totalstringSize, hipMemcpyHostToDevice);
CHECK_ERR(err);
err = hipMemcpy(d_B, start, sizeof(int)*MAX_STRING_LENGTH, hipMemcpyHostToDevice);
CHECK_ERR(err);
err = hipMemcpy(d_C, stringSize, sizeof(int)*MAX_STRING_LENGTH, hipMemcpyHostToDevice);
CHECK_ERR(err);
}
// before terminates the program, free the GPU memory.
void freeDeviceMemory()
{
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(d_D);
}
int main(int argc, char *argv[])
{
int lineNumber, n;
FILE *f;
f = fopen(argv[1], "r");
if (f == NULL) {
printf("can't open %s:", argv[1]);
}
// result is the huge string buffer in CPU end
// pattern is the string you are looking for.
// start array stores the start position of each string in the buffer.
// stringSize sotres each string's real length.
// totalstringSize records the total lengths of the current 4096 lines of string.
char * result = (char *)malloc(sizeof(char)*MAX_VALUE * MAX_STRING_LENGTH);
char * pattern = (char *)malloc(sizeof(char)*MAX_VALUE);
int start[MAX_STRING_LENGTH];
int stringSize[MAX_STRING_LENGTH];
int totalstringSize=0;
// line number the line index the current file descriptor is reading.
lineNumber = 0;
n=0;
// initializing...
for(int i = 0; i < MAX_STRING_LENGTH; i ++ ) {
start[i] = 0;
stringSize[i] = 0;
}
totalstringSize = 0;
strcat(pattern,argv[2]);
// allocate memory in GPU.
allocDeviceMemory(totalstringSize);
// pattern only needs to be copied to GPU once. Thus do it first.
err = hipMemcpy(d_D, pattern, sizeof(char)*strlen(pattern), hipMemcpyHostToDevice);
CHECK_ERR(err);
// each while loop ,we read 4096 lines of strings to the buffer string.
while (fgets(result+start[lineNumber%MAX_STRING_LENGTH], MAX_VALUE, f) != NULL) {
n = strlen(result+start[lineNumber%MAX_STRING_LENGTH]);
// save the current string to the huge buffer string
if (n > 0 && *(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) == '\n'){
*(result+start[lineNumber%MAX_STRING_LENGTH] + n-1) = '\0';
}
// save the correct start position and string length.
if(lineNumber%MAX_STRING_LENGTH < MAX_STRING_LENGTH-1) {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
start[lineNumber%MAX_STRING_LENGTH + 1] = start[lineNumber%MAX_STRING_LENGTH] + stringSize[lineNumber%MAX_STRING_LENGTH];
}
else {
stringSize[lineNumber%MAX_STRING_LENGTH]=n;
}
totalstringSize += n;
lineNumber ++;
// send the 4096 lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH == 0) {
// copy first
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
grep<<<16,256>>>(d_A, d_B, d_C, d_D, MAX_STRING_LENGTH,strlen(pattern));
// reset the buffer and other variables.
memset(result,'\0',sizeof(result));
totalstringSize = 0;
start[0]=0;
}
}
// send the remaining lines to GPU and do the searching.
if(lineNumber % MAX_STRING_LENGTH !=0) {
copytoDeviceMemory(result, start, stringSize, pattern, totalstringSize);
// only copy lineNumber%MAX_STRING_LENGTH strings to GPU.
grep<<<16,256>>>(d_A, d_B, d_C, d_D,lineNumber % MAX_STRING_LENGTH,strlen(pattern) );
// free the memory finally
freeDeviceMemory();
}
return 0;
} | .text
.file "grep.hip"
.globl _Z19__device_stub__grepPcPiS0_S_ii # -- Begin function _Z19__device_stub__grepPcPiS0_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__grepPcPiS0_S_ii,@function
_Z19__device_stub__grepPcPiS0_S_ii: # @_Z19__device_stub__grepPcPiS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4grepPcPiS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__grepPcPiS0_S_ii, .Lfunc_end0-_Z19__device_stub__grepPcPiS0_S_ii
.cfi_endproc
# -- End function
.globl _Z17allocDeviceMemoryi # -- Begin function _Z17allocDeviceMemoryi
.p2align 4, 0x90
.type _Z17allocDeviceMemoryi,@function
_Z17allocDeviceMemoryi: # @_Z17allocDeviceMemoryi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $d_A, %edi
movl $22937600, %esi # imm = 0x15E0000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $d_B, %edi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $d_C, %edi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $d_D, %edi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_8
# %bb.9:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $65, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $68, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z17allocDeviceMemoryi, .Lfunc_end1-_Z17allocDeviceMemoryi
.cfi_endproc
# -- End function
.globl _Z18copytoDeviceMemoryPcPiS0_S_i # -- Begin function _Z18copytoDeviceMemoryPcPiS0_S_i
.p2align 4, 0x90
.type _Z18copytoDeviceMemoryPcPiS0_S_i,@function
_Z18copytoDeviceMemoryPcPiS0_S_i: # @_Z18copytoDeviceMemoryPcPiS0_S_i
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
movq d_A(%rip), %rdi
movslq %r8d, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq d_B(%rip), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movq d_C(%rip), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_6
# %bb.7:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z18copytoDeviceMemoryPcPiS0_S_i, .Lfunc_end2-_Z18copytoDeviceMemoryPcPiS0_S_i
.cfi_endproc
# -- End function
.globl _Z16freeDeviceMemoryv # -- Begin function _Z16freeDeviceMemoryv
.p2align 4, 0x90
.type _Z16freeDeviceMemoryv,@function
_Z16freeDeviceMemoryv: # @_Z16freeDeviceMemoryv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq d_D(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end3:
.size _Z16freeDeviceMemoryv, .Lfunc_end3-_Z16freeDeviceMemoryv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $32952, %rsp # imm = 0x80B8
.cfi_def_cfa_offset 33008
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, 104(%rsp) # 8-byte Spill
testq %rax, %rax
jne .LBB4_2
# %bb.1:
movq 8(%r12), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB4_2:
movl $22937600, %edi # imm = 0x15E0000
callq malloc
movq %rax, %r15
movl $5600, %edi # imm = 0x15E0
callq malloc
movq %rax, %rbx
leaq 176(%rsp), %rdi
xorl %ebp, %ebp
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
leaq 16560(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
movq 16(%r12), %rsi
movq %rbx, %rdi
callq strcat
callq _Z17allocDeviceMemoryi
movq d_D(%rip), %r12
movq %rbx, %rdi
callq strlen
movq %r12, %rdi
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB4_20
# %bb.3: # %.preheader
movslq 176(%rsp), %rdi
addq %r15, %rdi
movl $5600, %esi # imm = 0x15E0
movq 104(%rsp), %rdx # 8-byte Reload
callq fgets
movl $0, %r13d
testq %rax, %rax
je .LBB4_15
# %bb.4: # %.lr.ph
xorl %r13d, %r13d
movl $1, %ebx
movabsq $4294967312, %rax # imm = 0x100000010
addq $240, %rax
movq %rax, 168(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_5 Depth=1
movq $0, (%r15)
movl $0, 176(%rsp)
xorl %ebp, %ebp
.LBB4_14: # in Loop: Header=BB4_5 Depth=1
movl %ebx, %r13d
andl $4095, %r13d # imm = 0xFFF
movslq 176(%rsp,%r13,4), %rdi
addq %r15, %rdi
movl $5600, %esi # imm = 0x15E0
movq 104(%rsp), %rdx # 8-byte Reload
callq fgets
incl %ebx
testq %rax, %rax
je .LBB4_15
.LBB4_5: # =>This Inner Loop Header: Depth=1
movslq 176(%rsp,%r13,4), %r14
leaq (%r15,%r14), %r12
movq %r12, %rdi
callq strlen
testl %eax, %eax
jle .LBB4_8
# %bb.6: # in Loop: Header=BB4_5 Depth=1
movl %eax, %ecx
cmpb $10, -1(%r12,%rcx)
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_5 Depth=1
movb $0, -1(%r12,%rcx)
.LBB4_8: # in Loop: Header=BB4_5 Depth=1
movl %eax, 16560(%rsp,%r13,4)
cmpl $4095, %r13d # imm = 0xFFF
je .LBB4_10
# %bb.9: # in Loop: Header=BB4_5 Depth=1
addl %eax, %r14d
movl %r13d, %ecx
movl %r14d, 180(%rsp,%rcx,4)
.LBB4_10: # in Loop: Header=BB4_5 Depth=1
addl %eax, %ebp
testl $4095, %ebx # imm = 0xFFF
jne .LBB4_14
# %bb.11: # in Loop: Header=BB4_5 Depth=1
movq %r15, %rdi
leaq 176(%rsp), %rsi
leaq 16560(%rsp), %rdx
movl %ebp, %r8d
callq _Z18copytoDeviceMemoryPcPiS0_S_i
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq 168(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_5 Depth=1
movq d_A(%rip), %r14
movq d_B(%rip), %r12
movq d_C(%rip), %r13
movq d_D(%rip), %rbp
movq 96(%rsp), %rdi # 8-byte Reload
callq strlen
movq %r14, 88(%rsp)
movq %r12, 80(%rsp)
movq %r13, 72(%rsp)
movq %rbp, 64(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4grepPcPiS0_S_ii, %edi
leaq 112(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_13
.LBB4_15: # %._crit_edge
testl %r13d, %r13d
je .LBB4_19
# %bb.16:
leaq 176(%rsp), %rsi
leaq 16560(%rsp), %rdx
movq %r15, %rdi
movl %ebp, %r8d
callq _Z18copytoDeviceMemoryPcPiS0_S_i
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17:
movq d_A(%rip), %rbx
movq d_B(%rip), %r14
movq d_C(%rip), %r15
movq d_D(%rip), %r12
movq 96(%rsp), %rdi # 8-byte Reload
callq strlen
movq %rbx, 88(%rsp)
movq %r14, 80(%rsp)
movq %r15, 72(%rsp)
movq %r12, 64(%rsp)
movl %r13d, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4grepPcPiS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_18:
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq d_D(%rip), %rdi
callq hipFree
.LBB4_19:
xorl %eax, %eax
addq $32952, %rsp # imm = 0x80B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_20:
.cfi_def_cfa_offset 33008
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $140, %r8d
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4grepPcPiS0_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_D,@object # @d_D
.globl d_D
.p2align 3, 0x0
d_D:
.quad 0
.size d_D, 8
.type err,@object # @err
.globl err
.p2align 2, 0x0
err:
.long 0 # 0x0
.size err, 4
.type _Z4grepPcPiS0_S_ii,@object # @_Z4grepPcPiS0_S_ii
.section .rodata,"a",@progbits
.globl _Z4grepPcPiS0_S_ii
.p2align 3, 0x0
_Z4grepPcPiS0_S_ii:
.quad _Z19__device_stub__grepPcPiS0_S_ii
.size _Z4grepPcPiS0_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tianyangche/cs550pa4/master/grep.hip"
.size .L.str.1, 94
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "can't open %s:"
.size .L.str.3, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4grepPcPiS0_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__grepPcPiS0_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym d_B
.addrsig_sym d_C
.addrsig_sym d_D
.addrsig_sym _Z4grepPcPiS0_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00009f8f_00000000-6_grep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tianyangche/cs550pa4/master/grep.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z17allocDeviceMemoryi
.type _Z17allocDeviceMemoryi, @function
_Z17allocDeviceMemoryi:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $22937600, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L9
movl $16384, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L10
movl $16384, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L11
movl $4096, %esi
leaq d_D(%rip), %rdi
call cudaMalloc@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L12
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $63, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L10:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $66, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L11:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $69, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $72, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17allocDeviceMemoryi, .-_Z17allocDeviceMemoryi
.globl _Z18copytoDeviceMemoryPcPiS0_S_i
.type _Z18copytoDeviceMemoryPcPiS0_S_i, @function
_Z18copytoDeviceMemoryPcPiS0_S_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movslq %r8d, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L18
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L19
movl $1, %ecx
movl $16384, %edx
movq %rbx, %rsi
movq d_C(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L20
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $80, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $82, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z18copytoDeviceMemoryPcPiS0_S_i, .-_Z18copytoDeviceMemoryPcPiS0_S_i
.globl _Z16freeDeviceMemoryv
.type _Z16freeDeviceMemoryv, @function
_Z16freeDeviceMemoryv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
movq d_D(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z16freeDeviceMemoryv, .-_Z16freeDeviceMemoryv
.globl _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
.type _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii, @function
_Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4grepPcPiS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii, .-_Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
.globl _Z4grepPcPiS0_S_ii
.type _Z4grepPcPiS0_S_ii, @function
_Z4grepPcPiS0_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z4grepPcPiS0_S_ii, .-_Z4grepPcPiS0_S_ii
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "can't open %s:"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -32768(%rsp), %r11
.cfi_def_cfa 11, 32824
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 32912
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 32840(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L47
.L32:
movl $22937600, %edi
call malloc@PLT
movq %rax, %r12
movl $5600, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $0, %eax
.L33:
movl $0, 64(%rsp,%rax)
movl $0, 16448(%rsp,%rax)
addq $4, %rax
cmpq $16384, %rax
jne .L33
movq 16(%rbx), %rsi
movl $5600, %edx
movq 16(%rsp), %rbx
movq %rbx, %rdi
call __strcat_chk@PLT
movl $0, %edi
call _Z17allocDeviceMemoryi
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq d_D(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, err(%rip)
testl %eax, %eax
jne .L48
movl $0, %r14d
movl $0, %ebp
leaq 16448(%rsp), %rax
movq %rax, 24(%rsp)
jmp .L34
.L47:
movq 8(%rbx), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L32
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $138, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
cmpl $4094, %ebx
jg .L36
movslq %ebx, %rdx
movl %eax, 16448(%rsp,%rdx,4)
addl $1, %ebx
movslq %ebx, %rbx
addl %eax, %r13d
movl %r13d, 64(%rsp,%rbx,4)
.L37:
addl %eax, %r14d
addl $1, %ebp
movl %ebp, %ebx
andl $4095, %ebx
je .L49
.L34:
movl %ebp, %eax
sarl $31, %eax
shrl $20, %eax
leal 0(%rbp,%rax), %ebx
andl $4095, %ebx
subl %eax, %ebx
movslq %ebx, %rax
movslq 64(%rsp,%rax,4), %rdi
movl $22937600, %esi
cmpq %rsi, %rdi
cmovnb %rdi, %rsi
subq %rdi, %rsi
addq %r12, %rdi
movq 8(%rsp), %rcx
movl $5600, %edx
call __fgets_chk@PLT
testq %rax, %rax
je .L50
movslq %ebx, %rax
movl 64(%rsp,%rax,4), %r13d
movslq %r13d, %r15
leaq (%r12,%r15), %rdi
call strlen@PLT
testl %eax, %eax
jle .L35
movslq %eax, %rdx
leaq -1(%r15,%rdx), %rdx
addq %r12, %rdx
cmpb $10, (%rdx)
jne .L35
movb $0, (%rdx)
jmp .L35
.L36:
movl %eax, 32828(%rsp)
jmp .L37
.L49:
leaq 64(%rsp), %rsi
movl %r14d, %r8d
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq %r12, %rdi
call _Z18copytoDeviceMemoryPcPiS0_S_i
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
movq $0, (%r12)
movl $0, 64(%rsp)
movl %ebx, %r14d
jmp .L34
.L51:
movq 16(%rsp), %rdi
call strlen@PLT
movl %eax, %r9d
movl $4096, %r8d
movq d_D(%rip), %rcx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
jmp .L39
.L50:
testl $4095, %ebp
jne .L52
.L41:
movq 32840(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $32856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
leaq 16448(%rsp), %rdx
leaq 64(%rsp), %rsi
movl %r14d, %r8d
movq 16(%rsp), %rcx
movq %r12, %rdi
call _Z18copytoDeviceMemoryPcPiS0_S_i
movl $256, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L42:
call _Z16freeDeviceMemoryv
jmp .L41
.L54:
movq 16(%rsp), %rdi
call strlen@PLT
movl %eax, %r9d
movl %ebx, %r8d
movq d_D(%rip), %rcx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z4grepPcPiS0_S_iiPcPiS0_S_ii
jmp .L42
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z4grepPcPiS0_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4grepPcPiS0_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl err
.bss
.align 4
.type err, @object
.size err, 4
err:
.zero 4
.globl d_D
.align 8
.type d_D, @object
.size d_D, 8
d_D:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grep.hip"
.globl _Z19__device_stub__grepPcPiS0_S_ii # -- Begin function _Z19__device_stub__grepPcPiS0_S_ii
.p2align 4, 0x90
.type _Z19__device_stub__grepPcPiS0_S_ii,@function
_Z19__device_stub__grepPcPiS0_S_ii: # @_Z19__device_stub__grepPcPiS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4grepPcPiS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__grepPcPiS0_S_ii, .Lfunc_end0-_Z19__device_stub__grepPcPiS0_S_ii
.cfi_endproc
# -- End function
.globl _Z17allocDeviceMemoryi # -- Begin function _Z17allocDeviceMemoryi
.p2align 4, 0x90
.type _Z17allocDeviceMemoryi,@function
_Z17allocDeviceMemoryi: # @_Z17allocDeviceMemoryi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $d_A, %edi
movl $22937600, %esi # imm = 0x15E0000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $d_B, %edi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_4
# %bb.5:
movl $d_C, %edi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movl $d_D, %edi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB1_8
# %bb.9:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $65, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $68, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $71, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z17allocDeviceMemoryi, .Lfunc_end1-_Z17allocDeviceMemoryi
.cfi_endproc
# -- End function
.globl _Z18copytoDeviceMemoryPcPiS0_S_i # -- Begin function _Z18copytoDeviceMemoryPcPiS0_S_i
.p2align 4, 0x90
.type _Z18copytoDeviceMemoryPcPiS0_S_i,@function
_Z18copytoDeviceMemoryPcPiS0_S_i: # @_Z18copytoDeviceMemoryPcPiS0_S_i
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
movq d_A(%rip), %rdi
movslq %r8d, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq d_B(%rip), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_4
# %bb.5:
movq d_C(%rip), %rdi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB2_6
# %bb.7:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z18copytoDeviceMemoryPcPiS0_S_i, .Lfunc_end2-_Z18copytoDeviceMemoryPcPiS0_S_i
.cfi_endproc
# -- End function
.globl _Z16freeDeviceMemoryv # -- Begin function _Z16freeDeviceMemoryv
.p2align 4, 0x90
.type _Z16freeDeviceMemoryv,@function
_Z16freeDeviceMemoryv: # @_Z16freeDeviceMemoryv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq d_D(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end3:
.size _Z16freeDeviceMemoryv, .Lfunc_end3-_Z16freeDeviceMemoryv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $32952, %rsp # imm = 0x80B8
.cfi_def_cfa_offset 33008
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, 104(%rsp) # 8-byte Spill
testq %rax, %rax
jne .LBB4_2
# %bb.1:
movq 8(%r12), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB4_2:
movl $22937600, %edi # imm = 0x15E0000
callq malloc
movq %rax, %r15
movl $5600, %edi # imm = 0x15E0
callq malloc
movq %rax, %rbx
leaq 176(%rsp), %rdi
xorl %ebp, %ebp
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
leaq 16560(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
xorl %esi, %esi
callq memset@PLT
movq 16(%r12), %rsi
movq %rbx, %rdi
callq strcat
callq _Z17allocDeviceMemoryi
movq d_D(%rip), %r12
movq %rbx, %rdi
callq strlen
movq %r12, %rdi
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rsi
movq %rax, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, err(%rip)
testl %eax, %eax
jne .LBB4_20
# %bb.3: # %.preheader
movslq 176(%rsp), %rdi
addq %r15, %rdi
movl $5600, %esi # imm = 0x15E0
movq 104(%rsp), %rdx # 8-byte Reload
callq fgets
movl $0, %r13d
testq %rax, %rax
je .LBB4_15
# %bb.4: # %.lr.ph
xorl %r13d, %r13d
movl $1, %ebx
movabsq $4294967312, %rax # imm = 0x100000010
addq $240, %rax
movq %rax, 168(%rsp) # 8-byte Spill
xorl %ebp, %ebp
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_5 Depth=1
movq $0, (%r15)
movl $0, 176(%rsp)
xorl %ebp, %ebp
.LBB4_14: # in Loop: Header=BB4_5 Depth=1
movl %ebx, %r13d
andl $4095, %r13d # imm = 0xFFF
movslq 176(%rsp,%r13,4), %rdi
addq %r15, %rdi
movl $5600, %esi # imm = 0x15E0
movq 104(%rsp), %rdx # 8-byte Reload
callq fgets
incl %ebx
testq %rax, %rax
je .LBB4_15
.LBB4_5: # =>This Inner Loop Header: Depth=1
movslq 176(%rsp,%r13,4), %r14
leaq (%r15,%r14), %r12
movq %r12, %rdi
callq strlen
testl %eax, %eax
jle .LBB4_8
# %bb.6: # in Loop: Header=BB4_5 Depth=1
movl %eax, %ecx
cmpb $10, -1(%r12,%rcx)
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_5 Depth=1
movb $0, -1(%r12,%rcx)
.LBB4_8: # in Loop: Header=BB4_5 Depth=1
movl %eax, 16560(%rsp,%r13,4)
cmpl $4095, %r13d # imm = 0xFFF
je .LBB4_10
# %bb.9: # in Loop: Header=BB4_5 Depth=1
addl %eax, %r14d
movl %r13d, %ecx
movl %r14d, 180(%rsp,%rcx,4)
.LBB4_10: # in Loop: Header=BB4_5 Depth=1
addl %eax, %ebp
testl $4095, %ebx # imm = 0xFFF
jne .LBB4_14
# %bb.11: # in Loop: Header=BB4_5 Depth=1
movq %r15, %rdi
leaq 176(%rsp), %rsi
leaq 16560(%rsp), %rdx
movl %ebp, %r8d
callq _Z18copytoDeviceMemoryPcPiS0_S_i
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq 168(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_5 Depth=1
movq d_A(%rip), %r14
movq d_B(%rip), %r12
movq d_C(%rip), %r13
movq d_D(%rip), %rbp
movq 96(%rsp), %rdi # 8-byte Reload
callq strlen
movq %r14, 88(%rsp)
movq %r12, 80(%rsp)
movq %r13, 72(%rsp)
movq %rbp, 64(%rsp)
movl $4096, 12(%rsp) # imm = 0x1000
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z4grepPcPiS0_S_ii, %edi
leaq 112(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_13
.LBB4_15: # %._crit_edge
testl %r13d, %r13d
je .LBB4_19
# %bb.16:
leaq 176(%rsp), %rsi
leaq 16560(%rsp), %rdx
movq %r15, %rdi
movl %ebp, %r8d
callq _Z18copytoDeviceMemoryPcPiS0_S_i
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 240(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17:
movq d_A(%rip), %rbx
movq d_B(%rip), %r14
movq d_C(%rip), %r15
movq d_D(%rip), %r12
movq 96(%rsp), %rdi # 8-byte Reload
callq strlen
movq %rbx, 88(%rsp)
movq %r14, 80(%rsp)
movq %r15, 72(%rsp)
movq %r12, 64(%rsp)
movl %r13d, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4grepPcPiS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_18:
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq d_D(%rip), %rdi
callq hipFree
.LBB4_19:
xorl %eax, %eax
addq $32952, %rsp # imm = 0x80B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_20:
.cfi_def_cfa_offset 33008
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $140, %r8d
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4grepPcPiS0_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_D,@object # @d_D
.globl d_D
.p2align 3, 0x0
d_D:
.quad 0
.size d_D, 8
.type err,@object # @err
.globl err
.p2align 2, 0x0
err:
.long 0 # 0x0
.size err, 4
.type _Z4grepPcPiS0_S_ii,@object # @_Z4grepPcPiS0_S_ii
.section .rodata,"a",@progbits
.globl _Z4grepPcPiS0_S_ii
.p2align 3, 0x0
_Z4grepPcPiS0_S_ii:
.quad _Z19__device_stub__grepPcPiS0_S_ii
.size _Z4grepPcPiS0_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tianyangche/cs550pa4/master/grep.hip"
.size .L.str.1, 94
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "can't open %s:"
.size .L.str.3, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4grepPcPiS0_S_ii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__grepPcPiS0_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym d_B
.addrsig_sym d_C
.addrsig_sym d_D
.addrsig_sym _Z4grepPcPiS0_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "prefix_sum_cuda.cuh"
__global__ void prefix_sum_cuda(int *a, size_t N) {
int tid = threadIdx.x;
int i = 0;
for (i = 2; i <= N; i *= 2) {
if (((i - tid % i) == 1) && tid != 0) {
a[tid] = a[tid] + a[tid - i / 2];
}
__syncthreads();
}
if (tid == N - 1) {
a[tid] = 0;
}
for (; i > 1; i /= 2) {
if (((i - tid % i) == 1) && tid != 0) {
int temp = a[tid - i / 2];
a[tid - i / 2] = a[tid];
a[tid] = a[tid] + temp;
}
__syncthreads();
}
// a[tid] += d_in[tid];
} | code for sm_80
Function : _Z15prefix_sum_cudaPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fe200078e00ff */
/*0060*/ ISETP.LE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f03070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20003f06100 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R12, RZ, 0x1f, R0 ; /* 0x0000001fff0c7819 */
/* 0x001fc60000011400 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd000078e0203 */
/*00b0*/ @!P0 BRA 0x370 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fe40000000000 */
/*00d0*/ IABS R9, R4.reuse ; /* 0x0000000400097213 */
/* 0x081fe20000000000 */
/*00e0*/ BSSY B0, 0x320 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IABS R13, R4 ; /* 0x00000004000d7213 */
/* 0x000fe40000000000 */
/*0100*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e220000209400 */
/*0110*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0120*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a07 */
/*0180*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fc800078e0006 */
/*01a0*/ IMAD.MOV R7, RZ, RZ, -R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a0d */
/*01b0*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R10, R10, R7, R8 ; /* 0x000000070a0a7224 */
/* 0x000fca00078e0208 */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fe200078e0a09 */
/*01f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f24070 */
/*0210*/ @!P1 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a9824 */
/* 0x000fc800078e0a09 */
/*0220*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0230*/ @!P0 LOP3.LUT R10, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff0a8212 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.IADD R10, R4, 0x1, -R10 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a0a */
/*0250*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*0260*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0270*/ @P0 BRA 0x310 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0280*/ LEA.HI R6, R4, R4, RZ, 0x1 ; /* 0x0000000404067211 */
/* 0x000fe200078f08ff */
/*0290*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000ea6000c1e1900 */
/*02a0*/ SHF.R.S32.HI R7, RZ, 0x1, R6 ; /* 0x00000001ff077819 */
/* 0x000fe20000011406 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*02d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fcc00078e0206 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0300*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101908 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0340*/ ISETP.GT.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fc80003f04070 */
/*0350*/ ISETP.GT.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f04100 */
/*0360*/ @!P0 BRA 0xd0 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0370*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0380*/ ISETP.GE.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f26270 */
/*0390*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*03a0*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000ff1e13f */
/*03b0*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fe400087fe43f */
/*03c0*/ ISETP.NE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf05070 */
/*03d0*/ ISETP.NE.AND.EX P0, PT, R12, UR5, PT, P0 ; /* 0x000000050c007c0c */
/* 0x000fda000bf05300 */
/*03e0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0003e2000c101908 */
/*03f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0400*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fe40000000000 */
/*0410*/ IABS R9, R4.reuse ; /* 0x0000000400097213 */
/* 0x081fe20000000000 */
/*0420*/ BSSY B0, 0x670 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0430*/ IABS R12, R4 ; /* 0x00000004000c7213 */
/* 0x000fe40000000000 */
/*0440*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e220000209400 */
/*0450*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0460*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0470*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0480*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000a4000021f000 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*04b0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a07 */
/*04c0*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fc800078e02ff */
/*04d0*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fc800078e0006 */
/*04e0*/ IMAD.MOV R7, RZ, RZ, -R12 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a0c */
/*04f0*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD R10, R10, R7, R8 ; /* 0x000000070a0a7224 */
/* 0x000fca00078e0208 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*0520*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fe200078e0a09 */
/*0530*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0540*/ ISETP.GT.U32.AND P1, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f24070 */
/*0550*/ @!P1 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a9824 */
/* 0x000fc800078e0a09 */
/*0560*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0570*/ @!P0 LOP3.LUT R10, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff0a8212 */
/* 0x000fca00078e33ff */
/*0580*/ IMAD.IADD R10, R4, 0x1, -R10 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a0a */
/*0590*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*05a0*/ ISETP.NE.AND P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004705270 */
/*05b0*/ @!P0 BRA 0x660 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fe20000011604 */
/*05e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*0600*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0206 */
/*0610*/ LDG.E R8, [R6.64] ; /* 0x0000000806087981 */
/* 0x000ee8000c1e1900 */
/*0620*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e8000c101908 */
/*0630*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.IADD R11, R8, 0x1, R11 ; /* 0x00000001080b7824 */
/* 0x008fca00078e020b */
/*0650*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101908 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0680*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04070 */
/*0690*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fd60000011604 */
/*06a0*/ @P0 BRA 0x410 ; /* 0xfffffd6000000947 */
/* 0x000fea000383ffff */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "prefix_sum_cuda.cuh"
__global__ void prefix_sum_cuda(int *a, size_t N) {
int tid = threadIdx.x;
int i = 0;
for (i = 2; i <= N; i *= 2) {
if (((i - tid % i) == 1) && tid != 0) {
a[tid] = a[tid] + a[tid - i / 2];
}
__syncthreads();
}
if (tid == N - 1) {
a[tid] = 0;
}
for (; i > 1; i /= 2) {
if (((i - tid % i) == 1) && tid != 0) {
int temp = a[tid - i / 2];
a[tid - i / 2] = a[tid];
a[tid] = a[tid] + temp;
}
__syncthreads();
}
// a[tid] += d_in[tid];
} | .file "tmpxft_00057d34_00000000-6_prefix_sum_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15prefix_sum_cudaPimPim
.type _Z36__device_stub__Z15prefix_sum_cudaPimPim, @function
_Z36__device_stub__Z15prefix_sum_cudaPimPim:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15prefix_sum_cudaPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z36__device_stub__Z15prefix_sum_cudaPimPim, .-_Z36__device_stub__Z15prefix_sum_cudaPimPim
.globl _Z15prefix_sum_cudaPim
.type _Z15prefix_sum_cudaPim, @function
_Z15prefix_sum_cudaPim:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15prefix_sum_cudaPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z15prefix_sum_cudaPim, .-_Z15prefix_sum_cudaPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15prefix_sum_cudaPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15prefix_sum_cudaPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "prefix_sum_cuda.cuh"
__global__ void prefix_sum_cuda(int *a, size_t N) {
int tid = threadIdx.x;
int i = 0;
for (i = 2; i <= N; i *= 2) {
if (((i - tid % i) == 1) && tid != 0) {
a[tid] = a[tid] + a[tid - i / 2];
}
__syncthreads();
}
if (tid == N - 1) {
a[tid] = 0;
}
for (; i > 1; i /= 2) {
if (((i - tid % i) == 1) && tid != 0) {
int temp = a[tid - i / 2];
a[tid - i / 2] = a[tid];
a[tid] = a[tid] + temp;
}
__syncthreads();
}
// a[tid] += d_in[tid];
} | #include <hip/hip_runtime.h>
#include <cstdio>
__global__ void prefix_sum_cuda(int *a, size_t N); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
__global__ void prefix_sum_cuda(int *a, size_t N); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
__global__ void prefix_sum_cuda(int *a, size_t N); | .text
.file "prefix_sum_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15prefix_sum_cudaPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, 0x2 ; /* 0x00000002ff047424 */
/* 0x000fe200078e00ff */
/*0060*/ ISETP.LE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fc80003f03070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20003f06100 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R12, RZ, 0x1f, R0 ; /* 0x0000001fff0c7819 */
/* 0x001fc60000011400 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fd000078e0203 */
/*00b0*/ @!P0 BRA 0x370 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fe40000000000 */
/*00d0*/ IABS R9, R4.reuse ; /* 0x0000000400097213 */
/* 0x081fe20000000000 */
/*00e0*/ BSSY B0, 0x320 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IABS R13, R4 ; /* 0x00000004000d7213 */
/* 0x000fe40000000000 */
/*0100*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e220000209400 */
/*0110*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0120*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a07 */
/*0180*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fc800078e0006 */
/*01a0*/ IMAD.MOV R7, RZ, RZ, -R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a0d */
/*01b0*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R10, R10, R7, R8 ; /* 0x000000070a0a7224 */
/* 0x000fca00078e0208 */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fe200078e0a09 */
/*01f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0200*/ ISETP.GT.U32.AND P1, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f24070 */
/*0210*/ @!P1 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a9824 */
/* 0x000fc800078e0a09 */
/*0220*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0230*/ @!P0 LOP3.LUT R10, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff0a8212 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.IADD R10, R4, 0x1, -R10 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a0a */
/*0250*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*0260*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0270*/ @P0 BRA 0x310 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0280*/ LEA.HI R6, R4, R4, RZ, 0x1 ; /* 0x0000000404067211 */
/* 0x000fe200078f08ff */
/*0290*/ LDG.E R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000ea6000c1e1900 */
/*02a0*/ SHF.R.S32.HI R7, RZ, 0x1, R6 ; /* 0x00000001ff077819 */
/* 0x000fe20000011406 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*02d0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fcc00078e0206 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0300*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101908 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204047824 */
/* 0x000fe200078e00ff */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0340*/ ISETP.GT.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fc80003f04070 */
/*0350*/ ISETP.GT.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f04100 */
/*0360*/ @!P0 BRA 0xd0 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0370*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0380*/ ISETP.GE.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f26270 */
/*0390*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*03a0*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000ff1e13f */
/*03b0*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fe400087fe43f */
/*03c0*/ ISETP.NE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf05070 */
/*03d0*/ ISETP.NE.AND.EX P0, PT, R12, UR5, PT, P0 ; /* 0x000000050c007c0c */
/* 0x000fda000bf05300 */
/*03e0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0003e2000c101908 */
/*03f0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0400*/ IABS R5, R0 ; /* 0x0000000000057213 */
/* 0x000fe40000000000 */
/*0410*/ IABS R9, R4.reuse ; /* 0x0000000400097213 */
/* 0x081fe20000000000 */
/*0420*/ BSSY B0, 0x670 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0430*/ IABS R12, R4 ; /* 0x00000004000c7213 */
/* 0x000fe40000000000 */
/*0440*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e220000209400 */
/*0450*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0460*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0470*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fe40007ffe0ff */
/*0480*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000a4000021f000 */
/*04a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*04b0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x004fc800078e0a07 */
/*04c0*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fc800078e02ff */
/*04d0*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fc800078e0006 */
/*04e0*/ IMAD.MOV R7, RZ, RZ, -R12 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a0c */
/*04f0*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD R10, R10, R7, R8 ; /* 0x000000070a0a7224 */
/* 0x000fca00078e0208 */
/*0510*/ ISETP.GT.U32.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f04070 */
/*0520*/ @!P0 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a8824 */
/* 0x000fe200078e0a09 */
/*0530*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f05270 */
/*0540*/ ISETP.GT.U32.AND P1, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x000fda0003f24070 */
/*0550*/ @!P1 IMAD.IADD R10, R10, 0x1, -R9 ; /* 0x000000010a0a9824 */
/* 0x000fc800078e0a09 */
/*0560*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe200078e0a0a */
/*0570*/ @!P0 LOP3.LUT R10, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff0a8212 */
/* 0x000fca00078e33ff */
/*0580*/ IMAD.IADD R10, R4, 0x1, -R10 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0a0a */
/*0590*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*05a0*/ ISETP.NE.AND P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004705270 */
/*05b0*/ @!P0 BRA 0x660 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*05c0*/ LDG.E R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fe20000011604 */
/*05e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*0600*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0206 */
/*0610*/ LDG.E R8, [R6.64] ; /* 0x0000000806087981 */
/* 0x000ee8000c1e1900 */
/*0620*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e8000c101908 */
/*0630*/ LDG.E R11, [R2.64] ; /* 0x00000008020b7981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.IADD R11, R8, 0x1, R11 ; /* 0x00000001080b7824 */
/* 0x008fca00078e020b */
/*0650*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101908 */
/*0660*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0680*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04070 */
/*0690*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fd60000011604 */
/*06a0*/ @P0 BRA 0x410 ; /* 0xfffffd6000000947 */
/* 0x000fea000383ffff */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00057d34_00000000-6_prefix_sum_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15prefix_sum_cudaPimPim
.type _Z36__device_stub__Z15prefix_sum_cudaPimPim, @function
_Z36__device_stub__Z15prefix_sum_cudaPimPim:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15prefix_sum_cudaPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z36__device_stub__Z15prefix_sum_cudaPimPim, .-_Z36__device_stub__Z15prefix_sum_cudaPimPim
.globl _Z15prefix_sum_cudaPim
.type _Z15prefix_sum_cudaPim, @function
_Z15prefix_sum_cudaPim:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15prefix_sum_cudaPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z15prefix_sum_cudaPim, .-_Z15prefix_sum_cudaPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15prefix_sum_cudaPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15prefix_sum_cudaPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefix_sum_cuda.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_profiler_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
cudaProfilerStart();
cuda_hello<<<1,1>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
cudaProfilerStop();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_profiler_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
cudaProfilerStart();
cuda_hello<<<1,1>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
cudaProfilerStop();
return 0;
} | .file "tmpxft_00140901_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
call cudaProfilerStart@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
call cudaProfilerStop@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_profiler_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
cudaProfilerStart();
cuda_hello<<<1,1>>>();
cudaDeviceSynchronize();
cudaDeviceReset();
cudaProfilerStop();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
hipProfilerStart();
cuda_hello<<<1,1>>>();
hipDeviceSynchronize();
hipDeviceReset();
hipProfilerStop();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
hipProfilerStart();
cuda_hello<<<1,1>>>();
hipDeviceSynchronize();
hipDeviceReset();
hipProfilerStop();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main() {
hipProfilerStart();
cuda_hello<<<1,1>>>();
hipDeviceSynchronize();
hipDeviceReset();
hipProfilerStop();
return 0;
} | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
callq hipProfilerStart
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
callq hipProfilerStop
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00140901_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
call cudaProfilerStart@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
call cudaProfilerStop@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
callq hipProfilerStart
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
callq hipDeviceReset
callq hipProfilerStop
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <curand_kernel.h>
/*
* Function : cuda_tauSqInv
* Purpose : calculates the relevant parameters for tau^-2, and
draws one sample from G(a,b) distribution with a large by
implementing the rejection sampler in Cheng (1977) for a set of
parallel threads in one block and taking one of the samples
that wasn't rejected. Note that to work properly,
blockDim.x and size of shared memory should be equal.
* Argument *state : pointer to random number generator
* Argument *tauSqInv : pointer to tauSqInv output and LB input (used in calculating rate)
* Argument *alphaG : pointer to shape parameter
* Argument *xiInv : pointer to xiInv (used in calculating rate)
* Output : mutates tauSqInv and stores result in its place
*/
extern "C"
__global__ void cuda_tauSqInv(curandStatePhilox4_32_10_t *globalState, float *tauSqInv, float *alphaG, float *xiInv) {
extern __shared__ float acc[]; //store accepted proposals in shared memory
__shared__ int success[1]; //store flag value indicating whether proposal was accepted in shared memory
if(threadIdx.x == 0)
success[1] = 0; //initialize success
if(threadIdx.x < blockDim.x && blockIdx.x == 0) {
acc[threadIdx.x] = 0.0f;
//copy parameters to local memory
float alpha = alphaG[0];
float LB = tauSqInv[0];
//copy RNG to local memory, skip to new sequence (avoid overlap with z), and
curandStatePhilox4_32_10_t state = globalState[0]; //copy random number generator state to local memory
skipahead((unsigned long long) (6*threadIdx.x), &state); //give each thread its own pseudorandom subsequence
//compute rate parameter
float beta = xiInv[0] + (0.5 * LB);
//compute constants
float a = rsqrtf(2.0f * alpha - 1.0f);
float b = alpha - 1.3862944f; //log(4) = 1.3862944f
float c = alpha + (1.0f / a);
//perform rejection sampling
while(success[0] == 0) {
//compute uniforms
float u1 = curand_uniform(&state); //one uniform for proposal
float u2 = curand_uniform(&state); //one uniform for accept/reject step
//compute proposal-dependant constants
float v = a * logf(u1 / (1.0f - u1));
float x = alpha * expf(v);
//perform accept/reject
if( (b + (c*v) - x) > logf(u1 * u1 * u2) ) {
acc[threadIdx.x] = x;
}
__syncthreads();
//find accepted value on thread 0
if(threadIdx.x == 0) {
for(int j=0; j < blockDim.x; j++) {
float stdGamma = acc[j];
if(stdGamma > 0.0f) { //thread accepted its proposal
tauSqInv[0] = stdGamma / beta; //write accepted proposal back to global memory
success[0] = 1; //tell other threads to stop
break; //stop checking for accepted proposals
}
}
}
}
__syncthreads();
//last thread: copy curand state back to global memory
if(threadIdx.x == blockDim.x - 1)
globalState[0] = state;
}
} | .file "tmpxft_000ae61e_00000000-6_cuTAU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
.type _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_, @function
_Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_:
.LFB2265:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq cuda_tauSqInv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_, .-_Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
.globl cuda_tauSqInv
.type cuda_tauSqInv, @function
cuda_tauSqInv:
.LFB2266:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size cuda_tauSqInv, .-cuda_tauSqInv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda_tauSqInv"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2268:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cuda_tauSqInv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <curand_kernel.h>
/*
* Function : cuda_tauSqInv
* Purpose : calculates the relevant parameters for tau^-2, and
draws one sample from G(a,b) distribution with a large by
implementing the rejection sampler in Cheng (1977) for a set of
parallel threads in one block and taking one of the samples
that wasn't rejected. Note that to work properly,
blockDim.x and size of shared memory should be equal.
* Argument *state : pointer to random number generator
* Argument *tauSqInv : pointer to tauSqInv output and LB input (used in calculating rate)
* Argument *alphaG : pointer to shape parameter
* Argument *xiInv : pointer to xiInv (used in calculating rate)
* Output : mutates tauSqInv and stores result in its place
*/
extern "C"
__global__ void cuda_tauSqInv(curandStatePhilox4_32_10_t *globalState, float *tauSqInv, float *alphaG, float *xiInv) {
extern __shared__ float acc[]; //store accepted proposals in shared memory
__shared__ int success[1]; //store flag value indicating whether proposal was accepted in shared memory
if(threadIdx.x == 0)
success[1] = 0; //initialize success
if(threadIdx.x < blockDim.x && blockIdx.x == 0) {
acc[threadIdx.x] = 0.0f;
//copy parameters to local memory
float alpha = alphaG[0];
float LB = tauSqInv[0];
//copy RNG to local memory, skip to new sequence (avoid overlap with z), and
curandStatePhilox4_32_10_t state = globalState[0]; //copy random number generator state to local memory
skipahead((unsigned long long) (6*threadIdx.x), &state); //give each thread its own pseudorandom subsequence
//compute rate parameter
float beta = xiInv[0] + (0.5 * LB);
//compute constants
float a = rsqrtf(2.0f * alpha - 1.0f);
float b = alpha - 1.3862944f; //log(4) = 1.3862944f
float c = alpha + (1.0f / a);
//perform rejection sampling
while(success[0] == 0) {
//compute uniforms
float u1 = curand_uniform(&state); //one uniform for proposal
float u2 = curand_uniform(&state); //one uniform for accept/reject step
//compute proposal-dependant constants
float v = a * logf(u1 / (1.0f - u1));
float x = alpha * expf(v);
//perform accept/reject
if( (b + (c*v) - x) > logf(u1 * u1 * u2) ) {
acc[threadIdx.x] = x;
}
__syncthreads();
//find accepted value on thread 0
if(threadIdx.x == 0) {
for(int j=0; j < blockDim.x; j++) {
float stdGamma = acc[j];
if(stdGamma > 0.0f) { //thread accepted its proposal
tauSqInv[0] = stdGamma / beta; //write accepted proposal back to global memory
success[0] = 1; //tell other threads to stop
break; //stop checking for accepted proposals
}
}
}
}
__syncthreads();
//last thread: copy curand state back to global memory
if(threadIdx.x == blockDim.x - 1)
globalState[0] = state;
}
} | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/*
* Function : cuda_tauSqInv
* Purpose : calculates the relevant parameters for tau^-2, and
draws one sample from G(a,b) distribution with a large by
implementing the rejection sampler in Cheng (1977) for a set of
parallel threads in one block and taking one of the samples
that wasn't rejected. Note that to work properly,
blockDim.x and size of shared memory should be equal.
* Argument *state : pointer to random number generator
* Argument *tauSqInv : pointer to tauSqInv output and LB input (used in calculating rate)
* Argument *alphaG : pointer to shape parameter
* Argument *xiInv : pointer to xiInv (used in calculating rate)
* Output : mutates tauSqInv and stores result in its place
*/
extern "C"
__global__ void cuda_tauSqInv(hiprandStatePhilox4_32_10_t *globalState, float *tauSqInv, float *alphaG, float *xiInv) {
extern __shared__ float acc[]; //store accepted proposals in shared memory
__shared__ int success[1]; //store flag value indicating whether proposal was accepted in shared memory
if(threadIdx.x == 0)
success[1] = 0; //initialize success
if(threadIdx.x < blockDim.x && blockIdx.x == 0) {
acc[threadIdx.x] = 0.0f;
//copy parameters to local memory
float alpha = alphaG[0];
float LB = tauSqInv[0];
//copy RNG to local memory, skip to new sequence (avoid overlap with z), and
hiprandStatePhilox4_32_10_t state = globalState[0]; //copy random number generator state to local memory
skipahead((unsigned long long) (6*threadIdx.x), &state); //give each thread its own pseudorandom subsequence
//compute rate parameter
float beta = xiInv[0] + (0.5 * LB);
//compute constants
float a = rsqrtf(2.0f * alpha - 1.0f);
float b = alpha - 1.3862944f; //log(4) = 1.3862944f
float c = alpha + (1.0f / a);
//perform rejection sampling
while(success[0] == 0) {
//compute uniforms
float u1 = hiprand_uniform(&state); //one uniform for proposal
float u2 = hiprand_uniform(&state); //one uniform for accept/reject step
//compute proposal-dependant constants
float v = a * logf(u1 / (1.0f - u1));
float x = alpha * expf(v);
//perform accept/reject
if( (b + (c*v) - x) > logf(u1 * u1 * u2) ) {
acc[threadIdx.x] = x;
}
__syncthreads();
//find accepted value on thread 0
if(threadIdx.x == 0) {
for(int j=0; j < blockDim.x; j++) {
float stdGamma = acc[j];
if(stdGamma > 0.0f) { //thread accepted its proposal
tauSqInv[0] = stdGamma / beta; //write accepted proposal back to global memory
success[0] = 1; //tell other threads to stop
break; //stop checking for accepted proposals
}
}
}
}
__syncthreads();
//last thread: copy curand state back to global memory
if(threadIdx.x == blockDim.x - 1)
globalState[0] = state;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/*
* Function : cuda_tauSqInv
* Purpose : calculates the relevant parameters for tau^-2, and
draws one sample from G(a,b) distribution with a large by
implementing the rejection sampler in Cheng (1977) for a set of
parallel threads in one block and taking one of the samples
that wasn't rejected. Note that to work properly,
blockDim.x and size of shared memory should be equal.
* Argument *state : pointer to random number generator
* Argument *tauSqInv : pointer to tauSqInv output and LB input (used in calculating rate)
* Argument *alphaG : pointer to shape parameter
* Argument *xiInv : pointer to xiInv (used in calculating rate)
* Output : mutates tauSqInv and stores result in its place
*/
extern "C"
__global__ void cuda_tauSqInv(hiprandStatePhilox4_32_10_t *globalState, float *tauSqInv, float *alphaG, float *xiInv) {
extern __shared__ float acc[]; //store accepted proposals in shared memory
__shared__ int success[1]; //store flag value indicating whether proposal was accepted in shared memory
if(threadIdx.x == 0)
success[1] = 0; //initialize success
if(threadIdx.x < blockDim.x && blockIdx.x == 0) {
acc[threadIdx.x] = 0.0f;
//copy parameters to local memory
float alpha = alphaG[0];
float LB = tauSqInv[0];
//copy RNG to local memory, skip to new sequence (avoid overlap with z), and
hiprandStatePhilox4_32_10_t state = globalState[0]; //copy random number generator state to local memory
skipahead((unsigned long long) (6*threadIdx.x), &state); //give each thread its own pseudorandom subsequence
//compute rate parameter
float beta = xiInv[0] + (0.5 * LB);
//compute constants
float a = rsqrtf(2.0f * alpha - 1.0f);
float b = alpha - 1.3862944f; //log(4) = 1.3862944f
float c = alpha + (1.0f / a);
//perform rejection sampling
while(success[0] == 0) {
//compute uniforms
float u1 = hiprand_uniform(&state); //one uniform for proposal
float u2 = hiprand_uniform(&state); //one uniform for accept/reject step
//compute proposal-dependant constants
float v = a * logf(u1 / (1.0f - u1));
float x = alpha * expf(v);
//perform accept/reject
if( (b + (c*v) - x) > logf(u1 * u1 * u2) ) {
acc[threadIdx.x] = x;
}
__syncthreads();
//find accepted value on thread 0
if(threadIdx.x == 0) {
for(int j=0; j < blockDim.x; j++) {
float stdGamma = acc[j];
if(stdGamma > 0.0f) { //thread accepted its proposal
tauSqInv[0] = stdGamma / beta; //write accepted proposal back to global memory
success[0] = 1; //tell other threads to stop
break; //stop checking for accepted proposals
}
}
}
}
__syncthreads();
//last thread: copy curand state back to global memory
if(threadIdx.x == blockDim.x - 1)
globalState[0] = state;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected cuda_tauSqInv
.globl cuda_tauSqInv
.p2align 8
.type cuda_tauSqInv,@function
cuda_tauSqInv:
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1 offset:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_eq_u32 s15, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_7
s_load_b64 s[8:9], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 6, v0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 2, v1
v_mov_b32_e32 v14, 0
v_lshrrev_b32_e32 v1, 2, v1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b128 v[10:13], v14, s[8:9] offset:44
global_load_b32 v22, v14, s[8:9] offset:60
s_clause 0x1
s_load_b32 s10, s[8:9], 0x28
s_load_b128 s[4:7], s[8:9], 0x0
s_add_u32 s12, s8, 44
s_addc_u32 s13, s9, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v21, s10, v2
s_load_b64 s[10:11], s[8:9], 0x20
ds_load_b32 v24, v14
v_cmp_lt_u32_e32 vcc_lo, 3, v21
v_cndmask_b32_e64 v23, 0, -4, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, v23, v21
v_cmp_gt_u32_e32 vcc_lo, s4, v1
v_mad_u64_u32 v[5:6], null, v1, 0xd2511f53, 0
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s14, s10, 0x9e3779b9
s_add_i32 s15, s11, 0xbb67ae85
s_add_i32 s16, s11, 0x76cf5d0a
s_add_i32 s17, s10, 0x3c6ef372
v_add_co_u32 v2, s4, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s4, s6, 0, s4
v_add_co_ci_u32_e64 v4, null, s7, 0, s4
s_add_i32 s18, s10, 0xdaa66d2b
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v3, 0xcd9e8d57, 0
v_xor3_b32 v6, s11, v6, v4
s_add_i32 s19, s11, 0x32370b8f
s_add_i32 s20, s11, 0xed9eba14
s_add_i32 s21, s10, 0x78dde6e4
s_add_i32 s22, s10, 0x1715609d
s_add_i32 s23, s11, 0xa9066899
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor3_b32 v17, s10, v8, v2
v_mad_u64_u32 v[8:9], null, v6, 0xcd9e8d57, 0
s_add_i32 s24, s11, 0x646e171e
s_add_i32 s25, s10, 0xb54cda56
v_mad_u64_u32 v[15:16], null, v17, 0xd2511f53, 0
s_add_i32 s26, s10, 0x5384540f
s_add_i32 s27, s11, 0x1fd5c5a3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor3_b32 v7, v9, v7, s14
s_add_i32 s28, s11, 0xdb3d7428
s_add_i32 s29, s10, 0xf1bbcdc8
s_add_i32 s30, s10, 0x8ff34781
v_xor3_b32 v9, v16, v5, s15
v_mad_u64_u32 v[5:6], null, v7, 0xd2511f53, 0
s_add_i32 s31, s11, 0x96a522ad
v_cmp_ne_u32_e32 vcc_lo, 0, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[16:17], null, v9, 0xcd9e8d57, 0
v_xor3_b32 v9, v6, v15, s16
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v15, v17, v8, s17
v_mad_u64_u32 v[6:7], null, v9, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0xd2511f53, 0
v_xor3_b32 v7, v7, v16, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, v9, v5, s19
v_mad_u64_u32 v[15:16], null, v7, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v5, 0xcd9e8d57, 0
v_xor3_b32 v7, v16, v8, s20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v18, v6, s21
v_mad_u64_u32 v[5:6], null, v7, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v9, 0xd2511f53, 0
v_xor3_b32 v6, v6, v17, s22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v17, v8, v15, s23
v_mad_u64_u32 v[8:9], null, v6, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[15:16], null, v17, 0xcd9e8d57, 0
v_xor3_b32 v7, v9, v7, s24
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v16, v5, s25
v_mad_u64_u32 v[5:6], null, v7, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[16:17], null, v9, 0xd2511f53, 0
v_xor3_b32 v6, v6, v15, s26
v_lshl_add_u32 v15, v0, 2, 4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v7, v17, v8, s27
v_mad_u64_u32 v[17:18], null, v6, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, v7, 0xcd9e8d57, 0
v_xor3_b32 v8, v18, v16, s28
v_mov_b32_e32 v16, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v5, v20, v5, s29
v_mad_u64_u32 v[6:7], null, v8, 0xcd9e8d57, 0
ds_store_b32 v15, v16
s_waitcnt vmcnt(1)
scratch_store_b128 off, v[10:13], off offset:4
s_waitcnt vmcnt(0)
scratch_store_b32 off, v22, off offset:20
v_mad_u64_u32 v[8:9], null, v5, 0xd2511f53, 0
v_xor3_b32 v5, v7, v19, s30
s_delay_alu instid0(VALU_DEP_2)
v_xor3_b32 v7, v9, v17, s31
s_cbranch_vccz .LBB0_8
v_mov_b32_e32 v11, v21
.LBB0_5:
s_add_i32 s3, s3, -1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
v_cmp_eq_u32_e32 vcc_lo, s3, v0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x1
scratch_load_b128 v[12:15], off, off offset:4
scratch_load_b32 v0, off, off offset:20
v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v9, s10
v_mov_b32_e32 v10, s11
s_clause 0x2
global_store_b128 v16, v[1:4], s[8:9]
global_store_b128 v16, v[5:8], s[8:9] offset:16
global_store_b96 v16, v[9:11], s[8:9] offset:32
s_waitcnt vmcnt(1)
global_store_b128 v16, v[12:15], s[12:13]
s_waitcnt vmcnt(0)
global_store_b32 v16, v0, s[12:13] offset:16
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_8:
s_clause 0x1
s_load_b64 s[34:35], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[34:35], 0x0
s_load_b32 s33, s[4:5], 0x0
s_load_b32 s1, s[6:7], 0x0
v_mov_b32_e32 v20, 1
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[9:10], s0
v_cvt_f64_f32_e32 v[11:12], s33
v_fma_f32 v13, s1, 2.0, -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v16, 0x4b800000, v13
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v13
v_cndmask_b32_e32 v13, v13, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rsq_f32_e32 v13, v13
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v16, 0x45800000, v13
v_cndmask_b32_e32 v16, v13, v16, vcc_lo
v_fma_f64 v[9:10], v[11:12], 0.5, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v11, null, v16, v16, 1.0
v_rcp_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v11, v12, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v12
v_div_scale_f32 v13, vcc_lo, 1.0, v16, 1.0
v_mul_f32_e32 v18, v13, v12
v_cvt_f32_f64_e32 v17, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v11, v18, v13
v_fmac_f32_e32 v18, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v11, v18, v13
v_div_fmas_f32 v9, v9, v12, v18
v_add_f32_e64 v18, 0xbfb17218, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v9, v9, v16, 1.0
v_add_f32_e32 v19, s1, v9
.LBB0_9:
v_dual_mov_b32 v22, v5 :: v_dual_mov_b32 v23, v6
v_dual_mov_b32 v24, v7 :: v_dual_mov_b32 v25, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v12, v23 :: v_dual_add_nc_u32 v13, 1, v21
v_dual_mov_b32 v27, v22 :: v_dual_mov_b32 v26, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v10, v25
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 4, v13
s_cbranch_execz .LBB0_12
v_add_co_u32 v1, vcc_lo, v1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_mad_u64_u32 v[7:8], null, v1, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v5, v3
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e32 v9, 0, v5, vcc_lo
v_mad_u64_u32 v[5:6], null, v3, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v9, v4
v_xor3_b32 v6, s10, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v12, s11, v8, v4
v_mad_u64_u32 v[8:9], null, v6, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v12, 0xcd9e8d57, 0
v_xor3_b32 v7, v9, v7, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v11, v5, s14
v_mad_u64_u32 v[5:6], null, v7, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v9, 0xd2511f53, 0
v_xor3_b32 v9, v6, v10, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v12, v8, s16
v_mad_u64_u32 v[6:7], null, v9, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v10, 0xcd9e8d57, 0
v_xor3_b32 v7, v7, v11, s19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, v9, v5, s18
v_mad_u64_u32 v[9:10], null, v7, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v5, 0xd2511f53, 0
v_xor3_b32 v7, v10, v8, s21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v12, v6, s20
v_mad_u64_u32 v[5:6], null, v7, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v10, 0xcd9e8d57, 0
v_xor3_b32 v6, v6, v11, s23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v12, v8, v9, s22
v_mad_u64_u32 v[8:9], null, v6, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v12, 0xd2511f53, 0
v_xor3_b32 v7, v9, v7, s25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v11, v5, s24
v_mad_u64_u32 v[5:6], null, v7, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v9, 0xcd9e8d57, 0
v_xor3_b32 v9, v6, v10, s27
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v12, v8, s26
v_mad_u64_u32 v[6:7], null, v9, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v10, 0xd2511f53, 0
v_xor3_b32 v7, v7, v11, s29
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, v9, v5, s28
v_mad_u64_u32 v[10:11], null, v7, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v5, 0xcd9e8d57, 0
v_xor3_b32 v26, v11, v8, s31
s_delay_alu instid0(VALU_DEP_2)
v_xor3_b32 v27, v13, v6, s30
v_mov_b32_e32 v13, 0
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v6, v12 :: v_dual_add_nc_u32 v11, 1, v13
v_dual_mov_b32 v5, v27 :: v_dual_mov_b32 v8, v10
v_mov_b32_e32 v7, v26
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmpx_eq_u32_e32 4, v11
s_cbranch_execz .LBB0_14
v_add_co_u32 v1, vcc_lo, v1, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_add_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_mad_u64_u32 v[7:8], null, v3, 0xcd9e8d57, 0
v_cndmask_b32_e32 v9, 0, v5, vcc_lo
v_mad_u64_u32 v[5:6], null, v1, 0xd2511f53, 0
v_xor3_b32 v11, s10, v8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v9, v4
v_mad_u64_u32 v[28:29], null, v11, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v6, s11, v6, v4
v_mad_u64_u32 v[8:9], null, v6, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor3_b32 v7, v9, v7, s14
v_xor3_b32 v9, v29, v5, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v7, 0xd2511f53, 0
v_mad_u64_u32 v[29:30], null, v9, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v6, v28, s16
v_xor3_b32 v11, v30, v8, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v9, 0xcd9e8d57, 0
v_mad_u64_u32 v[8:9], null, v11, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v7, v7, v29, s18
v_xor3_b32 v5, v9, v5, s19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[28:29], null, v7, 0xd2511f53, 0
v_mad_u64_u32 v[30:31], null, v5, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v7, v29, v8, s20
v_xor3_b32 v9, v31, v6, s21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v7, 0xcd9e8d57, 0
v_mad_u64_u32 v[7:8], null, v9, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v6, v6, v30, s22
v_xor3_b32 v11, v8, v28, s23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v6, 0xd2511f53, 0
v_mad_u64_u32 v[28:29], null, v11, 0xcd9e8d57, 0
v_mov_b32_e32 v11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v7, v9, v7, s24
v_xor3_b32 v9, v29, v5, s25
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v7, 0xcd9e8d57, 0
v_mad_u64_u32 v[29:30], null, v9, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v6, v6, v28, s26
v_xor3_b32 v7, v30, v8, s27
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[30:31], null, v6, 0xd2511f53, 0
v_mad_u64_u32 v[32:33], null, v7, 0xcd9e8d57, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v8, v31, v29, s28
v_xor3_b32 v5, v33, v5, s29
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v8, 0xcd9e8d57, 0
v_mad_u64_u32 v[8:9], null, v5, 0xd2511f53, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v5, v7, v32, s30
v_xor3_b32 v7, v9, v30, s31
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_eq_u32_e32 vcc_lo, 1, v21
v_cmp_eq_u32_e64 s0, 1, v13
v_cndmask_b32_e32 v9, v22, v23, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v27, v12, s0
v_cmp_eq_u32_e64 s0, 2, v13
v_cndmask_b32_e32 v9, v9, v24, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v26, s0
v_cmp_eq_u32_e64 s0, 3, v13
v_cndmask_b32_e32 v9, v9, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, v12, v10, s0
v_cvt_f32_u32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v10, v10
v_dual_fmaak_f32 v9, 0x2f800000, v9, 0x2f800000 :: v_dual_fmaak_f32 v10, 0x2f800000, v10, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v21, 1.0, v9
v_div_scale_f32 v22, null, v21, v21, v9
v_div_scale_f32 v25, vcc_lo, v9, v21, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v23, v22
s_waitcnt_depctr 0xfff
v_fma_f32 v24, -v22, v23, 1.0
v_fmac_f32_e32 v23, v24, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v24, v25, v23
v_fma_f32 v28, -v22, v24, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v24, v28, v23
v_fma_f32 v22, -v22, v24, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v22, v22, v23, v24
v_div_fixup_f32 v21, v22, v21, v9
v_mul_f32_e32 v9, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v21
v_mul_f32_e32 v9, v9, v10
v_cndmask_b32_e64 v22, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v21, v22
v_log_f32_e32 v21, v21
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v22, 0x3f317217, v21
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v21|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v23, v21, 0x3f317217, -v22
v_fmac_f32_e32 v23, 0x3377d1cf, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v22, v22, v23
v_cndmask_b32_e32 v13, v21, v22, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v13, v12
v_cndmask_b32_e64 v13, 1.0, 0x4f800000, vcc_lo
v_dual_mul_f32 v12, v16, v12 :: v_dual_mul_f32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, 0x3fb8aa3b, v12
v_log_f32_e32 v13, v9
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v21, v12, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v22, v10
v_dual_fmac_f32 v21, 0x32a5705f, v12 :: v_dual_sub_f32 v10, v10, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v10, v21
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, 0x3f317217, v13
v_cvt_i32_f32_e32 v21, v22
v_exp_f32_e32 v9, v9
v_fma_f32 v22, v13, 0x3f317217, -v10
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v22, 0x3377d1cf, v13
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v9, v21
v_cndmask_b32_e64 v21, 0, 0x41b17218, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
v_add_f32_e32 v10, v10, v22
v_fma_f32 v22, v19, v12, v18
v_cndmask_b32_e64 v9, 0, v9, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, 0x7f800000, v9, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v13|
v_fma_f32 v12, -s1, v9, v22
v_cndmask_b32_e32 v10, v13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v10, v21
v_cmpx_gt_f32_e32 v12, v10
s_cbranch_execz .LBB0_16
v_mul_f32_e32 v9, s1, v9
ds_store_b32 v15, v9
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_23
s_mov_b32 s6, 4
s_mov_b32 s7, s3
s_branch .LBB0_19
.LBB0_18:
s_and_not1_b32 vcc_lo, exec_lo, s34
s_cbranch_vccz .LBB0_21
.LBB0_19:
v_mov_b32_e32 v9, s6
s_mov_b32 s33, -1
s_mov_b32 s34, -1
ds_load_b32 v9, v9
s_waitcnt lgkmcnt(0)
v_cmp_nlt_f32_e32 vcc_lo, 0, v9
s_cbranch_vccz .LBB0_18
s_add_i32 s7, s7, -1
s_add_i32 s6, s6, 4
s_cmp_eq_u32 s7, 0
s_mov_b32 s33, 0
s_cselect_b32 s34, -1, 0
s_branch .LBB0_18
.LBB0_21:
s_and_b32 vcc_lo, exec_lo, s33
s_cbranch_vccz .LBB0_23
v_div_scale_f32 v10, null, v17, v17, v9
v_div_scale_f32 v21, vcc_lo, v9, v17, v9
ds_store_b32 v14, v20
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v10, v12, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v12
v_mul_f32_e32 v13, v21, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v22, -v10, v13, v21
v_fmac_f32_e32 v13, v22, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v10, v13, v21
v_div_fmas_f32 v10, v10, v12, v13
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v9, v10, v17, v9
s_waitcnt lgkmcnt(0)
global_store_b32 v14, v9, s[4:5]
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s0
ds_load_b32 v9, v14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_cbranch_vccz .LBB0_5
v_mov_b32_e32 v21, v11
s_branch .LBB0_9
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel cuda_tauSqInv
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 24
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 34
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size cuda_tauSqInv, .Lfunc_end0-cuda_tauSqInv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: cuda_tauSqInv
.private_segment_fixed_size: 24
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: cuda_tauSqInv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 34
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 2016 Alexander Terenin
*
* Licensed under the Apache License, Version 2.0 (the "License")
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* /
*/
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/*
* Function : cuda_tauSqInv
* Purpose : calculates the relevant parameters for tau^-2, and
draws one sample from G(a,b) distribution with a large by
implementing the rejection sampler in Cheng (1977) for a set of
parallel threads in one block and taking one of the samples
that wasn't rejected. Note that to work properly,
blockDim.x and size of shared memory should be equal.
* Argument *state : pointer to random number generator
* Argument *tauSqInv : pointer to tauSqInv output and LB input (used in calculating rate)
* Argument *alphaG : pointer to shape parameter
* Argument *xiInv : pointer to xiInv (used in calculating rate)
* Output : mutates tauSqInv and stores result in its place
*/
extern "C"
__global__ void cuda_tauSqInv(hiprandStatePhilox4_32_10_t *globalState, float *tauSqInv, float *alphaG, float *xiInv) {
extern __shared__ float acc[]; //store accepted proposals in shared memory
__shared__ int success[1]; //store flag value indicating whether proposal was accepted in shared memory
if(threadIdx.x == 0)
success[1] = 0; //initialize success
if(threadIdx.x < blockDim.x && blockIdx.x == 0) {
acc[threadIdx.x] = 0.0f;
//copy parameters to local memory
float alpha = alphaG[0];
float LB = tauSqInv[0];
//copy RNG to local memory, skip to new sequence (avoid overlap with z), and
hiprandStatePhilox4_32_10_t state = globalState[0]; //copy random number generator state to local memory
skipahead((unsigned long long) (6*threadIdx.x), &state); //give each thread its own pseudorandom subsequence
//compute rate parameter
float beta = xiInv[0] + (0.5 * LB);
//compute constants
float a = rsqrtf(2.0f * alpha - 1.0f);
float b = alpha - 1.3862944f; //log(4) = 1.3862944f
float c = alpha + (1.0f / a);
//perform rejection sampling
while(success[0] == 0) {
//compute uniforms
float u1 = hiprand_uniform(&state); //one uniform for proposal
float u2 = hiprand_uniform(&state); //one uniform for accept/reject step
//compute proposal-dependant constants
float v = a * logf(u1 / (1.0f - u1));
float x = alpha * expf(v);
//perform accept/reject
if( (b + (c*v) - x) > logf(u1 * u1 * u2) ) {
acc[threadIdx.x] = x;
}
__syncthreads();
//find accepted value on thread 0
if(threadIdx.x == 0) {
for(int j=0; j < blockDim.x; j++) {
float stdGamma = acc[j];
if(stdGamma > 0.0f) { //thread accepted its proposal
tauSqInv[0] = stdGamma / beta; //write accepted proposal back to global memory
success[0] = 1; //tell other threads to stop
break; //stop checking for accepted proposals
}
}
}
}
__syncthreads();
//last thread: copy curand state back to global memory
if(threadIdx.x == blockDim.x - 1)
globalState[0] = state;
}
} | .text
.file "cuTAU.hip"
.globl __device_stub__cuda_tauSqInv # -- Begin function __device_stub__cuda_tauSqInv
.p2align 4, 0x90
.type __device_stub__cuda_tauSqInv,@function
__device_stub__cuda_tauSqInv: # @__device_stub__cuda_tauSqInv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $cuda_tauSqInv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__cuda_tauSqInv, .Lfunc_end0-__device_stub__cuda_tauSqInv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cuda_tauSqInv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cuda_tauSqInv,@object # @cuda_tauSqInv
.section .rodata,"a",@progbits
.globl cuda_tauSqInv
.p2align 3, 0x0
cuda_tauSqInv:
.quad __device_stub__cuda_tauSqInv
.size cuda_tauSqInv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cuda_tauSqInv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cuda_tauSqInv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cuda_tauSqInv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae61e_00000000-6_cuTAU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
.type _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_, @function
_Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_:
.LFB2265:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq cuda_tauSqInv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_, .-_Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
.globl cuda_tauSqInv
.type cuda_tauSqInv, @function
cuda_tauSqInv:
.LFB2266:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z13cuda_tauSqInvP24curandStatePhilox4_32_10PfS1_S1_P24curandStatePhilox4_32_10PfS1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size cuda_tauSqInv, .-cuda_tauSqInv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cuda_tauSqInv"
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2268:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cuda_tauSqInv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuTAU.hip"
.globl __device_stub__cuda_tauSqInv # -- Begin function __device_stub__cuda_tauSqInv
.p2align 4, 0x90
.type __device_stub__cuda_tauSqInv,@function
__device_stub__cuda_tauSqInv: # @__device_stub__cuda_tauSqInv
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $cuda_tauSqInv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__cuda_tauSqInv, .Lfunc_end0-__device_stub__cuda_tauSqInv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cuda_tauSqInv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cuda_tauSqInv,@object # @cuda_tauSqInv
.section .rodata,"a",@progbits
.globl cuda_tauSqInv
.p2align 3, 0x0
cuda_tauSqInv:
.quad __device_stub__cuda_tauSqInv
.size cuda_tauSqInv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cuda_tauSqInv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cuda_tauSqInv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cuda_tauSqInv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <vector>
#include <iostream>
#include <cmath>
#include <cstdlib>
#include <chrono>
using namespace std;
const int nx = 41;
const int ny = 41;
//const int nt = 10;
const int nit = 50;
//const int c = 1;
__global__ void build_up_b(float *b, int rho, float dt, float dx, float dy, float *u , float *v){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
b[m] = 0;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
b[m] = (rho*(1/dt* ((u[m+1]-u[m-1])/(2*dx)
+ (v[m+nx] - v[m-nx])/(2*dy))
- pow((u[m+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx] - u[m-nx])/(2*dy)*
(v[m+1]-v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @x = 2
b[m] = (rho*(1/dt*((u[m-nx+1] - u[m-1])/(2*dx)
+(v[m+nx] - v[m-nx])/(2*dy))
-pow((u[m-nx+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m-nx+1] - v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @x = 0
b[m] = (rho*(1/dt*((u[m+1] - u[m+nx-1])/(2*dx)
+(v[m+nx] - v[m-nx]) /(2*dy))
- pow((u[m+1] - u[m+nx-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m+1] - v[m+nx-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}
}
__global__ void pressure_poisson_periodic(float *p, float *pn, float *b, float dx, float dy){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
for(int q=0; q<nit; q++){
__syncthreads();
pn[m] = p[m];
__syncthreads();
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
p[m]=(((pn[m+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @ x = 2
p[m]=(((pn[m-nx+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @ x = 0
p[m]=(((pn[m+1]+pn[m+nx-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId == 0){
p[m] = p[m+nx];
}else if(bId == (ny-1)){
p[m] = p[m-nx];
}
}
}
__global__ void updated_u_v(float *u, float *v, float *un, float *vn, float *p, float dx, float dy, float dt, float rho, float nu, float F){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC u @ x = 2 u[j][nx-1]
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m-nx+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m-nx+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 2
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m-nx+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId !=0 && bId != (ny-1) && tId == 0){
//Periodic BC u @ x = 0
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m+nx-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m+nx-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m+nx-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 0
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m+nx-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m+nx-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId == 0 || bId == (ny-1)){
//Wall BC: u,v = 0 @ y = 0,2
u[m] = 0;
v[m] = 0;
}
}
int main() {
//Variable Declarations
float dx = 2/(nx - 1.0);
float dy = 2/(ny - 1.0);
int m;
//Physical Variables
const float rho = 1.0;
const float nu = .1;
const float F = 1.0;
const float dt = .01;
//Initial Conditions
float udiff = 1.0;
int stepcount = 0;
float sumu = 0.0;
float sumun = 0.0;
float *b;
float *p;
float *u;
float *v;
float *un;
float *vn;
float *pn;
cudaMallocManaged(&b,ny*nx*sizeof(float));
cudaMallocManaged(&p,ny*nx*sizeof(float));
cudaMallocManaged(&u,ny*nx*sizeof(float));
cudaMallocManaged(&v,ny*nx*sizeof(float));
cudaMallocManaged(&un,ny*nx*sizeof(float));
cudaMallocManaged(&vn,ny*nx*sizeof(float));
cudaMallocManaged(&pn,ny*nx*sizeof(float));
for(int i=0; i<ny*nx; i++) {
u[i]=0.0;
v[i]=0.0;
un[i]=0.0;
vn[i]=0.0;
pn[i]=1.0;
}
auto tic = chrono::steady_clock::now();
while(udiff>.001){
for(int i=0; i<nx; i++){
for(int j=0; j<ny; j++){
un[j*nx+i] = u[j*nx+i];
vn[j*nx+i] = v[j*nx+i];
}
}
build_up_b<<<ny,nx>>>(b,rho,dt,dx,dy,u,v);
cudaDeviceSynchronize();
//b = build_up_b(rho, dt, dx, dy, u, v);
pressure_poisson_periodic<<<ny,nx>>>(p,pn,b, dx, dy);
cudaDeviceSynchronize();
//p = pressure_poisson_periodic(p, b, dx, dy);
updated_u_v<<<ny,nx>>>(u,v,un,vn,p,dx,dy,dt,rho,nu,F);
cudaDeviceSynchronize();
sumu = 0.0;
sumun = 0.0;
for(int i=0;i<nx;i++){
for(int j=0; j<ny;j++){
m = j*nx+i;
sumu += u[m];
sumun += un[m];
}
}
udiff = (sumu - sumun)/ sumu ;
if(stepcount % 50 ==0){
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
}
stepcount += 1;
}
auto toc = chrono::steady_clock::now();
double time = chrono::duration<double>(toc - tic).count();
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
std::cout<<"Step Count = " << stepcount <<std::endl;
std::cout<<"Time = " << time <<std::endl;
} | .file "tmpxft_00094d0f_00000000-6_Final_Report_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4137:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4137:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
.type _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_, @function
_Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_:
.LFB4159:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10build_up_bPfifffS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_, .-_Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
.globl _Z10build_up_bPfifffS_S_
.type _Z10build_up_bPfifffS_S_, @function
_Z10build_up_bPfifffS_S_:
.LFB4160:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4160:
.size _Z10build_up_bPfifffS_S_, .-_Z10build_up_bPfifffS_S_
.globl _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
.type _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff, @function
_Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff:
.LFB4161:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25pressure_poisson_periodicPfS_S_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4161:
.size _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff, .-_Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
.globl _Z25pressure_poisson_periodicPfS_S_ff
.type _Z25pressure_poisson_periodicPfS_S_ff, @function
_Z25pressure_poisson_periodicPfS_S_ff:
.LFB4162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4162:
.size _Z25pressure_poisson_periodicPfS_S_ff, .-_Z25pressure_poisson_periodicPfS_S_ff
.globl _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
.type _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff, @function
_Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff:
.LFB4163:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11updated_u_vPfS_S_S_S_ffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff, .-_Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
.globl _Z11updated_u_vPfS_S_S_S_ffffff
.type _Z11updated_u_vPfS_S_S_S_ffffff, @function
_Z11updated_u_vPfS_S_S_S_ffffff:
.LFB4164:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _Z11updated_u_vPfS_S_S_S_ffffff, .-_Z11updated_u_vPfS_S_S_S_ffffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Step: "
.LC6:
.string ": udiff = "
.LC9:
.string "Step Count = "
.LC10:
.string "Time = "
.text
.globl main
.type main, @function
main:
.LFB4131:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 64(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 72(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
movss .LC1(%rip), %xmm0
.L28:
movq 40(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 48(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 56(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 64(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 72(%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq $6724, %rbx
jne .L28
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r14
movl $0, %ebp
jmp .L29
.L52:
addl $1, %esi
addq $4, %rcx
cmpl $41, %esi
je .L31
.L45:
leaq -6724(%rcx), %rax
.L30:
movq 40(%rsp), %rdx
movss (%rdx,%rax), %xmm0
movq 56(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 48(%rsp), %rdx
movss (%rdx,%rax), %xmm0
movq 64(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $164, %rax
cmpq %rax, %rcx
jne .L30
jmp .L52
.L31:
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L32:
call cudaDeviceSynchronize@PLT
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L33:
call cudaDeviceSynchronize@PLT
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L34:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rsi
movq 56(%rsp), %rcx
movq %rbx, %rdx
movl $0, %edi
pxor %xmm1, %xmm1
movaps %xmm1, %xmm0
.L35:
leaq -6724(%rdx), %rax
.L36:
addss (%rsi,%rax), %xmm0
addss (%rcx,%rax), %xmm1
addq $164, %rax
cmpq %rdx, %rax
jne .L36
addl $1, %edi
addq $4, %rdx
cmpl $41, %edi
jne .L35
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
movslq %ebp, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %ebp, %edx
sarl $31, %edx
subl %edx, %eax
imull $50, %eax, %eax
cmpl %eax, %ebp
je .L56
.L38:
addl $1, %ebp
pxor %xmm6, %xmm6
cvtss2sd 12(%rsp), %xmm6
movq %xmm6, %r12
comisd .LC7(%rip), %xmm6
jbe .L50
.L29:
movq %rbx, %rcx
movl $0, %esi
jmp .L45
.L53:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movss .LC2(%rip), %xmm2
movaps %xmm2, %xmm1
movss .LC3(%rip), %xmm0
movl $1, %esi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
jmp .L32
.L54:
movss .LC2(%rip), %xmm1
movaps %xmm1, %xmm0
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
jmp .L33
.L55:
movss .LC1(%rip), %xmm5
movss .LC4(%rip), %xmm4
movaps %xmm5, %xmm3
movss .LC3(%rip), %xmm2
movss .LC2(%rip), %xmm1
movaps %xmm1, %xmm0
movq 32(%rsp), %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
jmp .L34
.L56:
movl $6, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $10, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L57
cmpb $0, 56(%r13)
je .L41
movzbl 67(%r13), %eax
.L42:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L38
.L57:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L41:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L42
.L50:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4131:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z11updated_u_vPfS_S_S_S_ffffff"
.align 8
.LC12:
.string "_Z25pressure_poisson_periodicPfS_S_ff"
.section .rodata.str1.1
.LC13:
.string "_Z10build_up_bPfifffS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4166:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11updated_u_vPfS_S_S_S_ffffff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z25pressure_poisson_periodicPfS_S_ff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z10build_up_bPfifffS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1028443341
.align 4
.LC3:
.long 1008981770
.align 4
.LC4:
.long 1036831949
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -755914244
.long 1062232653
.align 8
.LC8:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <vector>
#include <iostream>
#include <cmath>
#include <cstdlib>
#include <chrono>
using namespace std;
const int nx = 41;
const int ny = 41;
//const int nt = 10;
const int nit = 50;
//const int c = 1;
__global__ void build_up_b(float *b, int rho, float dt, float dx, float dy, float *u , float *v){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
b[m] = 0;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
b[m] = (rho*(1/dt* ((u[m+1]-u[m-1])/(2*dx)
+ (v[m+nx] - v[m-nx])/(2*dy))
- pow((u[m+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx] - u[m-nx])/(2*dy)*
(v[m+1]-v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @x = 2
b[m] = (rho*(1/dt*((u[m-nx+1] - u[m-1])/(2*dx)
+(v[m+nx] - v[m-nx])/(2*dy))
-pow((u[m-nx+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m-nx+1] - v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @x = 0
b[m] = (rho*(1/dt*((u[m+1] - u[m+nx-1])/(2*dx)
+(v[m+nx] - v[m-nx]) /(2*dy))
- pow((u[m+1] - u[m+nx-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m+1] - v[m+nx-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}
}
__global__ void pressure_poisson_periodic(float *p, float *pn, float *b, float dx, float dy){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
for(int q=0; q<nit; q++){
__syncthreads();
pn[m] = p[m];
__syncthreads();
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
p[m]=(((pn[m+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @ x = 2
p[m]=(((pn[m-nx+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @ x = 0
p[m]=(((pn[m+1]+pn[m+nx-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId == 0){
p[m] = p[m+nx];
}else if(bId == (ny-1)){
p[m] = p[m-nx];
}
}
}
__global__ void updated_u_v(float *u, float *v, float *un, float *vn, float *p, float dx, float dy, float dt, float rho, float nu, float F){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC u @ x = 2 u[j][nx-1]
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m-nx+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m-nx+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 2
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m-nx+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId !=0 && bId != (ny-1) && tId == 0){
//Periodic BC u @ x = 0
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m+nx-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m+nx-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m+nx-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 0
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m+nx-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m+nx-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId == 0 || bId == (ny-1)){
//Wall BC: u,v = 0 @ y = 0,2
u[m] = 0;
v[m] = 0;
}
}
int main() {
//Variable Declarations
float dx = 2/(nx - 1.0);
float dy = 2/(ny - 1.0);
int m;
//Physical Variables
const float rho = 1.0;
const float nu = .1;
const float F = 1.0;
const float dt = .01;
//Initial Conditions
float udiff = 1.0;
int stepcount = 0;
float sumu = 0.0;
float sumun = 0.0;
float *b;
float *p;
float *u;
float *v;
float *un;
float *vn;
float *pn;
cudaMallocManaged(&b,ny*nx*sizeof(float));
cudaMallocManaged(&p,ny*nx*sizeof(float));
cudaMallocManaged(&u,ny*nx*sizeof(float));
cudaMallocManaged(&v,ny*nx*sizeof(float));
cudaMallocManaged(&un,ny*nx*sizeof(float));
cudaMallocManaged(&vn,ny*nx*sizeof(float));
cudaMallocManaged(&pn,ny*nx*sizeof(float));
for(int i=0; i<ny*nx; i++) {
u[i]=0.0;
v[i]=0.0;
un[i]=0.0;
vn[i]=0.0;
pn[i]=1.0;
}
auto tic = chrono::steady_clock::now();
while(udiff>.001){
for(int i=0; i<nx; i++){
for(int j=0; j<ny; j++){
un[j*nx+i] = u[j*nx+i];
vn[j*nx+i] = v[j*nx+i];
}
}
build_up_b<<<ny,nx>>>(b,rho,dt,dx,dy,u,v);
cudaDeviceSynchronize();
//b = build_up_b(rho, dt, dx, dy, u, v);
pressure_poisson_periodic<<<ny,nx>>>(p,pn,b, dx, dy);
cudaDeviceSynchronize();
//p = pressure_poisson_periodic(p, b, dx, dy);
updated_u_v<<<ny,nx>>>(u,v,un,vn,p,dx,dy,dt,rho,nu,F);
cudaDeviceSynchronize();
sumu = 0.0;
sumun = 0.0;
for(int i=0;i<nx;i++){
for(int j=0; j<ny;j++){
m = j*nx+i;
sumu += u[m];
sumun += un[m];
}
}
udiff = (sumu - sumun)/ sumu ;
if(stepcount % 50 ==0){
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
}
stepcount += 1;
}
auto toc = chrono::steady_clock::now();
double time = chrono::duration<double>(toc - tic).count();
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
std::cout<<"Step Count = " << stepcount <<std::endl;
std::cout<<"Time = " << time <<std::endl;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <vector>
#include <iostream>
#include <cmath>
#include <cstdlib>
#include <chrono>
using namespace std;
const int nx = 41;
const int ny = 41;
//const int nt = 10;
const int nit = 50;
//const int c = 1;
__global__ void build_up_b(float *b, int rho, float dt, float dx, float dy, float *u , float *v){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
b[m] = 0;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
b[m] = (rho*(1/dt* ((u[m+1]-u[m-1])/(2*dx)
+ (v[m+nx] - v[m-nx])/(2*dy))
- pow((u[m+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx] - u[m-nx])/(2*dy)*
(v[m+1]-v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @x = 2
b[m] = (rho*(1/dt*((u[m-nx+1] - u[m-1])/(2*dx)
+(v[m+nx] - v[m-nx])/(2*dy))
-pow((u[m-nx+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m-nx+1] - v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @x = 0
b[m] = (rho*(1/dt*((u[m+1] - u[m+nx-1])/(2*dx)
+(v[m+nx] - v[m-nx]) /(2*dy))
- pow((u[m+1] - u[m+nx-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m+1] - v[m+nx-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}
}
__global__ void pressure_poisson_periodic(float *p, float *pn, float *b, float dx, float dy){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
for(int q=0; q<nit; q++){
__syncthreads();
pn[m] = p[m];
__syncthreads();
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
p[m]=(((pn[m+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @ x = 2
p[m]=(((pn[m-nx+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @ x = 0
p[m]=(((pn[m+1]+pn[m+nx-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId == 0){
p[m] = p[m+nx];
}else if(bId == (ny-1)){
p[m] = p[m-nx];
}
}
}
__global__ void updated_u_v(float *u, float *v, float *un, float *vn, float *p, float dx, float dy, float dt, float rho, float nu, float F){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC u @ x = 2 u[j][nx-1]
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m-nx+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m-nx+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 2
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m-nx+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId !=0 && bId != (ny-1) && tId == 0){
//Periodic BC u @ x = 0
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m+nx-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m+nx-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m+nx-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 0
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m+nx-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m+nx-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId == 0 || bId == (ny-1)){
//Wall BC: u,v = 0 @ y = 0,2
u[m] = 0;
v[m] = 0;
}
}
int main() {
//Variable Declarations
float dx = 2/(nx - 1.0);
float dy = 2/(ny - 1.0);
int m;
//Physical Variables
const float rho = 1.0;
const float nu = .1;
const float F = 1.0;
const float dt = .01;
//Initial Conditions
float udiff = 1.0;
int stepcount = 0;
float sumu = 0.0;
float sumun = 0.0;
float *b;
float *p;
float *u;
float *v;
float *un;
float *vn;
float *pn;
hipMallocManaged(&b,ny*nx*sizeof(float));
hipMallocManaged(&p,ny*nx*sizeof(float));
hipMallocManaged(&u,ny*nx*sizeof(float));
hipMallocManaged(&v,ny*nx*sizeof(float));
hipMallocManaged(&un,ny*nx*sizeof(float));
hipMallocManaged(&vn,ny*nx*sizeof(float));
hipMallocManaged(&pn,ny*nx*sizeof(float));
for(int i=0; i<ny*nx; i++) {
u[i]=0.0;
v[i]=0.0;
un[i]=0.0;
vn[i]=0.0;
pn[i]=1.0;
}
auto tic = chrono::steady_clock::now();
while(udiff>.001){
for(int i=0; i<nx; i++){
for(int j=0; j<ny; j++){
un[j*nx+i] = u[j*nx+i];
vn[j*nx+i] = v[j*nx+i];
}
}
build_up_b<<<ny,nx>>>(b,rho,dt,dx,dy,u,v);
hipDeviceSynchronize();
//b = build_up_b(rho, dt, dx, dy, u, v);
pressure_poisson_periodic<<<ny,nx>>>(p,pn,b, dx, dy);
hipDeviceSynchronize();
//p = pressure_poisson_periodic(p, b, dx, dy);
updated_u_v<<<ny,nx>>>(u,v,un,vn,p,dx,dy,dt,rho,nu,F);
hipDeviceSynchronize();
sumu = 0.0;
sumun = 0.0;
for(int i=0;i<nx;i++){
for(int j=0; j<ny;j++){
m = j*nx+i;
sumu += u[m];
sumun += un[m];
}
}
udiff = (sumu - sumun)/ sumu ;
if(stepcount % 50 ==0){
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
}
stepcount += 1;
}
auto toc = chrono::steady_clock::now();
double time = chrono::duration<double>(toc - tic).count();
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
std::cout<<"Step Count = " << stepcount <<std::endl;
std::cout<<"Time = " << time <<std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <vector>
#include <iostream>
#include <cmath>
#include <cstdlib>
#include <chrono>
using namespace std;
const int nx = 41;
const int ny = 41;
//const int nt = 10;
const int nit = 50;
//const int c = 1;
__global__ void build_up_b(float *b, int rho, float dt, float dx, float dy, float *u , float *v){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
b[m] = 0;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
b[m] = (rho*(1/dt* ((u[m+1]-u[m-1])/(2*dx)
+ (v[m+nx] - v[m-nx])/(2*dy))
- pow((u[m+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx] - u[m-nx])/(2*dy)*
(v[m+1]-v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @x = 2
b[m] = (rho*(1/dt*((u[m-nx+1] - u[m-1])/(2*dx)
+(v[m+nx] - v[m-nx])/(2*dy))
-pow((u[m-nx+1] - u[m-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m-nx+1] - v[m-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @x = 0
b[m] = (rho*(1/dt*((u[m+1] - u[m+nx-1])/(2*dx)
+(v[m+nx] - v[m-nx]) /(2*dy))
- pow((u[m+1] - u[m+nx-1])/(2*dx),2)
- 2*((u[m+nx]-u[m-nx])/(2*dy) *
(v[m+1] - v[m+nx-1])/(2*dx)) -
pow((v[m+nx] - v[m-nx])/(2*dy),2)));
}
}
__global__ void pressure_poisson_periodic(float *p, float *pn, float *b, float dx, float dy){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
for(int q=0; q<nit; q++){
__syncthreads();
pn[m] = p[m];
__syncthreads();
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
p[m]=(((pn[m+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC Pressure @ x = 2
p[m]=(((pn[m-nx+1]+pn[m-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId != 0 && bId != (ny-1) && tId == (0)){
//Periodic BC Pressure @ x = 0
p[m]=(((pn[m+1]+pn[m+nx-1])*pow(dy,2)+
(pn[m+nx]+pn[m-nx])*pow(dx,2))/
(2*(pow(dx,2)+pow(dy,2)))-
pow(dx,2)*pow(dy,2)/(2*(pow(dx,2)+pow(dy,2)))*b[m]);
}else if(bId == 0){
p[m] = p[m+nx];
}else if(bId == (ny-1)){
p[m] = p[m-nx];
}
}
}
__global__ void updated_u_v(float *u, float *v, float *un, float *vn, float *p, float dx, float dy, float dt, float rho, float nu, float F){
//m = j * nx + i
int m = blockIdx.x * blockDim.x + threadIdx.x;
int bId = blockIdx.x;
int tId = threadIdx.x;
if(bId != 0 && bId != (ny-1) && tId != 0 && tId != (nx-1)){
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId != 0 && bId != (ny-1) && tId == (nx-1)){
//Periodic BC u @ x = 2 u[j][nx-1]
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m-nx+1] - p[m-1]) +
nu * (dt/pow(dx,2)*
(un[m-nx+1] - 2*un[m] + un[m-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 2
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m-nx+1] - 2*vn[m] + vn[m-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId !=0 && bId != (ny-1) && tId == 0){
//Periodic BC u @ x = 0
u[m] = (un[m] -
un[m] * dt/dx *
(un[m] - un[m+nx-1]) -
vn[m] * dt/dy *
(un[m] - un[m-nx]) -
dt/(2*rho*dx) *
(p[m+1] - p[m+nx-1]) +
nu * (dt/pow(dx,2)*
(un[m+1] - 2*un[m] + un[m+nx-1]) +
dt/pow(dy,2) *
(un[m+nx] - 2*un[m] + un[m-nx])) +
F* dt);
//Periodic BC v @ x = 0
v[m] = (vn[m] -
un[m] * dt/dx *
(vn[m] - vn[m+nx-1]) -
vn[m] * dt/dy *
(vn[m] - vn[m-nx]) -
dt/(2*rho*dy) *
(p[m+nx] - p[m-nx]) +
nu * (dt/pow(dx,2)*
(vn[m+1] - 2*vn[m] + vn[m+nx-1]) +
dt/pow(dy,2) *
(vn[m+nx] - 2*vn[m] + vn[m-nx])));
}else if(bId == 0 || bId == (ny-1)){
//Wall BC: u,v = 0 @ y = 0,2
u[m] = 0;
v[m] = 0;
}
}
int main() {
//Variable Declarations
float dx = 2/(nx - 1.0);
float dy = 2/(ny - 1.0);
int m;
//Physical Variables
const float rho = 1.0;
const float nu = .1;
const float F = 1.0;
const float dt = .01;
//Initial Conditions
float udiff = 1.0;
int stepcount = 0;
float sumu = 0.0;
float sumun = 0.0;
float *b;
float *p;
float *u;
float *v;
float *un;
float *vn;
float *pn;
hipMallocManaged(&b,ny*nx*sizeof(float));
hipMallocManaged(&p,ny*nx*sizeof(float));
hipMallocManaged(&u,ny*nx*sizeof(float));
hipMallocManaged(&v,ny*nx*sizeof(float));
hipMallocManaged(&un,ny*nx*sizeof(float));
hipMallocManaged(&vn,ny*nx*sizeof(float));
hipMallocManaged(&pn,ny*nx*sizeof(float));
for(int i=0; i<ny*nx; i++) {
u[i]=0.0;
v[i]=0.0;
un[i]=0.0;
vn[i]=0.0;
pn[i]=1.0;
}
auto tic = chrono::steady_clock::now();
while(udiff>.001){
for(int i=0; i<nx; i++){
for(int j=0; j<ny; j++){
un[j*nx+i] = u[j*nx+i];
vn[j*nx+i] = v[j*nx+i];
}
}
build_up_b<<<ny,nx>>>(b,rho,dt,dx,dy,u,v);
hipDeviceSynchronize();
//b = build_up_b(rho, dt, dx, dy, u, v);
pressure_poisson_periodic<<<ny,nx>>>(p,pn,b, dx, dy);
hipDeviceSynchronize();
//p = pressure_poisson_periodic(p, b, dx, dy);
updated_u_v<<<ny,nx>>>(u,v,un,vn,p,dx,dy,dt,rho,nu,F);
hipDeviceSynchronize();
sumu = 0.0;
sumun = 0.0;
for(int i=0;i<nx;i++){
for(int j=0; j<ny;j++){
m = j*nx+i;
sumu += u[m];
sumun += un[m];
}
}
udiff = (sumu - sumun)/ sumu ;
if(stepcount % 50 ==0){
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
}
stepcount += 1;
}
auto toc = chrono::steady_clock::now();
double time = chrono::duration<double>(toc - tic).count();
std::cout<<"Step: "<<stepcount<<": udiff = "<<udiff<<std::endl;
std::cout<<"Step Count = " << stepcount <<std::endl;
std::cout<<"Time = " << time <<std::endl;
} | .text
.file "Final_Report_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__build_up_bPfifffS_S_ # -- Begin function _Z25__device_stub__build_up_bPfifffS_S_
.p2align 4, 0x90
.type _Z25__device_stub__build_up_bPfifffS_S_,@function
_Z25__device_stub__build_up_bPfifffS_S_: # @_Z25__device_stub__build_up_bPfifffS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10build_up_bPfifffS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__build_up_bPfifffS_S_, .Lfunc_end0-_Z25__device_stub__build_up_bPfifffS_S_
.cfi_endproc
# -- End function
.globl _Z40__device_stub__pressure_poisson_periodicPfS_S_ff # -- Begin function _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.p2align 4, 0x90
.type _Z40__device_stub__pressure_poisson_periodicPfS_S_ff,@function
_Z40__device_stub__pressure_poisson_periodicPfS_S_ff: # @_Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25pressure_poisson_periodicPfS_S_ff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z40__device_stub__pressure_poisson_periodicPfS_S_ff, .Lfunc_end1-_Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.cfi_endproc
# -- End function
.globl _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff # -- Begin function _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.p2align 4, 0x90
.type _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff,@function
_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff: # @_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff, .Lfunc_end2-_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_1:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 168(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 160(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 112(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 152(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq 112(%rsp), %rsi
xorl %edi, %edi
movq 152(%rsp), %r8
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rdi,4)
movl $0, (%rcx,%rdi,4)
movl $0, (%rdx,%rdi,4)
movl $0, (%rsi,%rdi,4)
movl $1065353216, (%r8,%rdi,4) # imm = 0x3F800000
incq %rdi
cmpq $1681, %rdi # imm = 0x691
jne .LBB3_1
# %bb.2:
movabsq $4294967337, %r15 # imm = 0x100000029
xorl %r14d, %r14d
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, 272(%rsp) # 8-byte Spill
leaq 128(%rsp), %rbx
leaq 120(%rsp), %r12
leaq 104(%rsp), %r13
leaq 4(%rsp), %rbp
jmp .LBB3_3
.LBB3_21: # in Loop: Header=BB3_3 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_3 Depth=1
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r13, %rbx
movq %r15, %r12
leaq 104(%rsp), %r13
movabsq $4294967337, %r15 # imm = 0x100000029
movq %rbp, %r14
leaq 4(%rsp), %rbp
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB3_23: # in Loop: Header=BB3_3 Depth=1
incl %r14d
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
ucomisd .LCPI3_0(%rip), %xmm0
jbe .LBB3_24
.LBB3_3: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
movq 16(%rsp), %rax
movq 88(%rsp), %rcx
movq 96(%rsp), %rdx
movq 112(%rsp), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_4: # %.preheader114
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%r8)
movss (%rdx,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%r8)
addq $164, %r8
cmpq $6724, %r8 # imm = 0x1A44
jne .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
incq %rdi
addq $4, %rsi
addq $4, %rdx
addq $4, %rcx
addq $4, %rax
cmpq $41, %rdi
jne .LBB3_4
# %bb.7: # in Loop: Header=BB3_3 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_3 Depth=1
movq 168(%rsp), %rax
movq 16(%rsp), %rcx
movq 96(%rsp), %rdx
movq %rax, 128(%rsp)
movl $1, 120(%rsp)
movl $1008981770, 104(%rsp) # imm = 0x3C23D70A
movl $1028443341, 4(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, (%rsp) # imm = 0x3D4CCCCD
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rbx, 176(%rsp)
movq %r12, 184(%rsp)
movq %r13, 192(%rsp)
movq %rbp, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z10build_up_bPfifffS_S_, %edi
leaq 176(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_3 Depth=1
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl $1028443341, 120(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, 104(%rsp) # imm = 0x3D4CCCCD
movq %rbx, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
movq %r12, 200(%rsp)
movq %r13, 208(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z25pressure_poisson_periodicPfS_S_ff, %edi
leaq 176(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_3 Depth=1
movq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movq 112(%rsp), %rax
movq %rax, 64(%rsp)
movq 160(%rsp), %rax
movq %rax, 56(%rsp)
movl $1028443341, 4(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, (%rsp) # imm = 0x3D4CCCCD
movl $1008981770, 148(%rsp) # imm = 0x3C23D70A
movl $1065353216, 144(%rsp) # imm = 0x3F800000
movl $1036831949, 140(%rsp) # imm = 0x3DCCCCCD
movl $1065353216, 136(%rsp) # imm = 0x3F800000
movq %rbx, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
movq %rbp, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 148(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rax
movq %rax, 240(%rsp)
leaq 140(%rsp), %rax
movq %rax, 248(%rsp)
leaq 136(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %edi
leaq 176(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rax
xorps %xmm0, %xmm0
movq 88(%rsp), %rcx
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB3_14: # %.preheader
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
addss (%rax,%rsi), %xmm0
addss (%rcx,%rsi), %xmm1
addq $164, %rsi
cmpq $6724, %rsi # imm = 0x1A44
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_14 Depth=2
incq %rdx
addq $4, %rcx
addq $4, %rax
cmpq $41, %rdx
jne .LBB3_14
# %bb.17: # in Loop: Header=BB3_3 Depth=1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
divss %xmm0, %xmm2
imull $-1030792151, %r14d, %eax # imm = 0xC28F5C29
rorl %eax
cmpl $85899346, %eax # imm = 0x51EB852
jae .LBB3_23
# %bb.18: # in Loop: Header=BB3_3 Depth=1
movq %r12, %r15
movq %rbx, %r13
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
movss %xmm2, 8(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rbp
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB3_37
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_3 Depth=1
cmpb $0, 56(%r12)
je .LBB3_21
# %bb.20: # in Loop: Header=BB3_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_22
.LBB3_24:
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_37
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%r15)
je .LBB3_27
# %bb.26:
movzbl 67(%r15), %ecx
jmp .LBB3_28
.LBB3_27:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_37
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i86
subq 272(%rsp), %rbx # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
je .LBB3_31
# %bb.30:
movzbl 67(%r14), %ecx
jmp .LBB3_32
.LBB3_31:
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit89
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_37
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
cmpb $0, 56(%rbx)
je .LBB3_35
# %bb.34:
movzbl 67(%rbx), %ecx
jmp .LBB3_36
.LBB3_35:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_37:
.cfi_def_cfa_offset 336
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10build_up_bPfifffS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25pressure_poisson_periodicPfS_S_ff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10build_up_bPfifffS_S_,@object # @_Z10build_up_bPfifffS_S_
.section .rodata,"a",@progbits
.globl _Z10build_up_bPfifffS_S_
.p2align 3, 0x0
_Z10build_up_bPfifffS_S_:
.quad _Z25__device_stub__build_up_bPfifffS_S_
.size _Z10build_up_bPfifffS_S_, 8
.type _Z25pressure_poisson_periodicPfS_S_ff,@object # @_Z25pressure_poisson_periodicPfS_S_ff
.globl _Z25pressure_poisson_periodicPfS_S_ff
.p2align 3, 0x0
_Z25pressure_poisson_periodicPfS_S_ff:
.quad _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.size _Z25pressure_poisson_periodicPfS_S_ff, 8
.type _Z11updated_u_vPfS_S_S_S_ffffff,@object # @_Z11updated_u_vPfS_S_S_S_ffffff
.globl _Z11updated_u_vPfS_S_S_S_ffffff
.p2align 3, 0x0
_Z11updated_u_vPfS_S_S_S_ffffff:
.quad _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.size _Z11updated_u_vPfS_S_S_S_ffffff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Step: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": udiff = "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Step Count = "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time = "
.size .L.str.3, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10build_up_bPfifffS_S_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25pressure_poisson_periodicPfS_S_ff"
.size .L__unnamed_2, 38
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11updated_u_vPfS_S_S_S_ffffff"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__build_up_bPfifffS_S_
.addrsig_sym _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.addrsig_sym _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10build_up_bPfifffS_S_
.addrsig_sym _Z25pressure_poisson_periodicPfS_S_ff
.addrsig_sym _Z11updated_u_vPfS_S_S_S_ffffff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094d0f_00000000-6_Final_Report_CUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4137:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4137:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
.type _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_, @function
_Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_:
.LFB4159:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10build_up_bPfifffS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_, .-_Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
.globl _Z10build_up_bPfifffS_S_
.type _Z10build_up_bPfifffS_S_, @function
_Z10build_up_bPfifffS_S_:
.LFB4160:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4160:
.size _Z10build_up_bPfifffS_S_, .-_Z10build_up_bPfifffS_S_
.globl _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
.type _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff, @function
_Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff:
.LFB4161:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25pressure_poisson_periodicPfS_S_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4161:
.size _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff, .-_Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
.globl _Z25pressure_poisson_periodicPfS_S_ff
.type _Z25pressure_poisson_periodicPfS_S_ff, @function
_Z25pressure_poisson_periodicPfS_S_ff:
.LFB4162:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4162:
.size _Z25pressure_poisson_periodicPfS_S_ff, .-_Z25pressure_poisson_periodicPfS_S_ff
.globl _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
.type _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff, @function
_Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff:
.LFB4163:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11updated_u_vPfS_S_S_S_ffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.size _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff, .-_Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
.globl _Z11updated_u_vPfS_S_S_S_ffffff
.type _Z11updated_u_vPfS_S_S_S_ffffff, @function
_Z11updated_u_vPfS_S_S_S_ffffff:
.LFB4164:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4164:
.size _Z11updated_u_vPfS_S_S_S_ffffff, .-_Z11updated_u_vPfS_S_S_S_ffffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Step: "
.LC6:
.string ": udiff = "
.LC9:
.string "Step Count = "
.LC10:
.string "Time = "
.text
.globl main
.type main, @function
main:
.LFB4131:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 64(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
leaq 72(%rsp), %rdi
movl $1, %edx
movl $6724, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
movss .LC1(%rip), %xmm0
.L28:
movq 40(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 48(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 56(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 64(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
movq 72(%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq $6724, %rbx
jne .L28
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r14
movl $0, %ebp
jmp .L29
.L52:
addl $1, %esi
addq $4, %rcx
cmpl $41, %esi
je .L31
.L45:
leaq -6724(%rcx), %rax
.L30:
movq 40(%rsp), %rdx
movss (%rdx,%rax), %xmm0
movq 56(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 48(%rsp), %rdx
movss (%rdx,%rax), %xmm0
movq 64(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $164, %rax
cmpq %rax, %rcx
jne .L30
jmp .L52
.L31:
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L32:
call cudaDeviceSynchronize@PLT
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L33:
call cudaDeviceSynchronize@PLT
movl $41, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $41, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L34:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rsi
movq 56(%rsp), %rcx
movq %rbx, %rdx
movl $0, %edi
pxor %xmm1, %xmm1
movaps %xmm1, %xmm0
.L35:
leaq -6724(%rdx), %rax
.L36:
addss (%rsi,%rax), %xmm0
addss (%rcx,%rax), %xmm1
addq $164, %rax
cmpq %rdx, %rax
jne .L36
addl $1, %edi
addq $4, %rdx
cmpl $41, %edi
jne .L35
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
movslq %ebp, %rax
imulq $1374389535, %rax, %rax
sarq $36, %rax
movl %ebp, %edx
sarl $31, %edx
subl %edx, %eax
imull $50, %eax, %eax
cmpl %eax, %ebp
je .L56
.L38:
addl $1, %ebp
pxor %xmm6, %xmm6
cvtss2sd 12(%rsp), %xmm6
movq %xmm6, %r12
comisd .LC7(%rip), %xmm6
jbe .L50
.L29:
movq %rbx, %rcx
movl $0, %esi
jmp .L45
.L53:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movss .LC2(%rip), %xmm2
movaps %xmm2, %xmm1
movss .LC3(%rip), %xmm0
movl $1, %esi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z10build_up_bPfifffS_S_PfifffS_S_
jmp .L32
.L54:
movss .LC2(%rip), %xmm1
movaps %xmm1, %xmm0
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z25pressure_poisson_periodicPfS_S_ffPfS_S_ff
jmp .L33
.L55:
movss .LC1(%rip), %xmm5
movss .LC4(%rip), %xmm4
movaps %xmm5, %xmm3
movss .LC3(%rip), %xmm2
movss .LC2(%rip), %xmm1
movaps %xmm1, %xmm0
movq 32(%rsp), %r8
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z11updated_u_vPfS_S_S_S_ffffffPfS_S_S_S_ffffff
jmp .L34
.L56:
movl $6, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $10, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L57
cmpb $0, 56(%r13)
je .L41
movzbl 67(%r13), %eax
.L42:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L38
.L57:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L41:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L42
.L50:
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
subq %r14, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4131:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z11updated_u_vPfS_S_S_S_ffffff"
.align 8
.LC12:
.string "_Z25pressure_poisson_periodicPfS_S_ff"
.section .rodata.str1.1
.LC13:
.string "_Z10build_up_bPfifffS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4166:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z11updated_u_vPfS_S_S_S_ffffff(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z25pressure_poisson_periodicPfS_S_ff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z10build_up_bPfifffS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1028443341
.align 4
.LC3:
.long 1008981770
.align 4
.LC4:
.long 1036831949
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -755914244
.long 1062232653
.align 8
.LC8:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Final_Report_CUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__build_up_bPfifffS_S_ # -- Begin function _Z25__device_stub__build_up_bPfifffS_S_
.p2align 4, 0x90
.type _Z25__device_stub__build_up_bPfifffS_S_,@function
_Z25__device_stub__build_up_bPfifffS_S_: # @_Z25__device_stub__build_up_bPfifffS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10build_up_bPfifffS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__build_up_bPfifffS_S_, .Lfunc_end0-_Z25__device_stub__build_up_bPfifffS_S_
.cfi_endproc
# -- End function
.globl _Z40__device_stub__pressure_poisson_periodicPfS_S_ff # -- Begin function _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.p2align 4, 0x90
.type _Z40__device_stub__pressure_poisson_periodicPfS_S_ff,@function
_Z40__device_stub__pressure_poisson_periodicPfS_S_ff: # @_Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25pressure_poisson_periodicPfS_S_ff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z40__device_stub__pressure_poisson_periodicPfS_S_ff, .Lfunc_end1-_Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.cfi_endproc
# -- End function
.globl _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff # -- Begin function _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.p2align 4, 0x90
.type _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff,@function
_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff: # @_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff, .Lfunc_end2-_Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_1:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 168(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 160(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 112(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
leaq 152(%rsp), %rdi
movl $6724, %esi # imm = 0x1A44
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq 112(%rsp), %rsi
xorl %edi, %edi
movq 152(%rsp), %r8
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rdi,4)
movl $0, (%rcx,%rdi,4)
movl $0, (%rdx,%rdi,4)
movl $0, (%rsi,%rdi,4)
movl $1065353216, (%r8,%rdi,4) # imm = 0x3F800000
incq %rdi
cmpq $1681, %rdi # imm = 0x691
jne .LBB3_1
# %bb.2:
movabsq $4294967337, %r15 # imm = 0x100000029
xorl %r14d, %r14d
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, 272(%rsp) # 8-byte Spill
leaq 128(%rsp), %rbx
leaq 120(%rsp), %r12
leaq 104(%rsp), %r13
leaq 4(%rsp), %rbp
jmp .LBB3_3
.LBB3_21: # in Loop: Header=BB3_3 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_3 Depth=1
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r13, %rbx
movq %r15, %r12
leaq 104(%rsp), %r13
movabsq $4294967337, %r15 # imm = 0x100000029
movq %rbp, %r14
leaq 4(%rsp), %rbp
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
.LBB3_23: # in Loop: Header=BB3_3 Depth=1
incl %r14d
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
ucomisd .LCPI3_0(%rip), %xmm0
jbe .LBB3_24
.LBB3_3: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_5 Depth 3
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
movq 16(%rsp), %rax
movq 88(%rsp), %rcx
movq 96(%rsp), %rdx
movq 112(%rsp), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_4: # %.preheader114
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_5 Depth 3
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rcx,%r8)
movss (%rdx,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%r8)
addq $164, %r8
cmpq $6724, %r8 # imm = 0x1A44
jne .LBB3_5
# %bb.6: # in Loop: Header=BB3_4 Depth=2
incq %rdi
addq $4, %rsi
addq $4, %rdx
addq $4, %rcx
addq $4, %rax
cmpq $41, %rdi
jne .LBB3_4
# %bb.7: # in Loop: Header=BB3_3 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_3 Depth=1
movq 168(%rsp), %rax
movq 16(%rsp), %rcx
movq 96(%rsp), %rdx
movq %rax, 128(%rsp)
movl $1, 120(%rsp)
movl $1008981770, 104(%rsp) # imm = 0x3C23D70A
movl $1028443341, 4(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, (%rsp) # imm = 0x3D4CCCCD
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rbx, 176(%rsp)
movq %r12, 184(%rsp)
movq %r13, 192(%rsp)
movq %rbp, 200(%rsp)
movq %rsp, %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z10build_up_bPfifffS_S_, %edi
leaq 176(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_3 Depth=1
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movl $1028443341, 120(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, 104(%rsp) # imm = 0x3D4CCCCD
movq %rbx, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
movq %r12, 200(%rsp)
movq %r13, 208(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z25pressure_poisson_periodicPfS_S_ff, %edi
leaq 176(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_3 Depth=1
movq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq 88(%rsp), %rax
movq %rax, 72(%rsp)
movq 112(%rsp), %rax
movq %rax, 64(%rsp)
movq 160(%rsp), %rax
movq %rax, 56(%rsp)
movl $1028443341, 4(%rsp) # imm = 0x3D4CCCCD
movl $1028443341, (%rsp) # imm = 0x3D4CCCCD
movl $1008981770, 148(%rsp) # imm = 0x3C23D70A
movl $1065353216, 144(%rsp) # imm = 0x3F800000
movl $1036831949, 140(%rsp) # imm = 0x3DCCCCCD
movl $1065353216, 136(%rsp) # imm = 0x3F800000
movq %rbx, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
movq %rbp, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 148(%rsp), %rax
movq %rax, 232(%rsp)
leaq 144(%rsp), %rax
movq %rax, 240(%rsp)
leaq 140(%rsp), %rax
movq %rax, 248(%rsp)
leaq 136(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %edi
leaq 176(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rax
xorps %xmm0, %xmm0
movq 88(%rsp), %rcx
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB3_14: # %.preheader
# Parent Loop BB3_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_15: # Parent Loop BB3_3 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
addss (%rax,%rsi), %xmm0
addss (%rcx,%rsi), %xmm1
addq $164, %rsi
cmpq $6724, %rsi # imm = 0x1A44
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_14 Depth=2
incq %rdx
addq $4, %rcx
addq $4, %rax
cmpq $41, %rdx
jne .LBB3_14
# %bb.17: # in Loop: Header=BB3_3 Depth=1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
divss %xmm0, %xmm2
imull $-1030792151, %r14d, %eax # imm = 0xC28F5C29
rorl %eax
cmpl $85899346, %eax # imm = 0x51EB852
jae .LBB3_23
# %bb.18: # in Loop: Header=BB3_3 Depth=1
movq %r12, %r15
movq %rbx, %r13
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
movss %xmm2, 8(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rbp
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB3_37
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_3 Depth=1
cmpb $0, 56(%r12)
je .LBB3_21
# %bb.20: # in Loop: Header=BB3_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_22
.LBB3_24:
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_37
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%r15)
je .LBB3_27
# %bb.26:
movzbl 67(%r15), %ecx
jmp .LBB3_28
.LBB3_27:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_37
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i86
subq 272(%rsp), %rbx # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
divsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
je .LBB3_31
# %bb.30:
movzbl 67(%r14), %ecx
jmp .LBB3_32
.LBB3_31:
movq %r14, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit89
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_37
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i91
cmpb $0, 56(%rbx)
je .LBB3_35
# %bb.34:
movzbl 67(%rbx), %ecx
jmp .LBB3_36
.LBB3_35:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit94
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_37:
.cfi_def_cfa_offset 336
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10build_up_bPfifffS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25pressure_poisson_periodicPfS_S_ff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11updated_u_vPfS_S_S_S_ffffff, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10build_up_bPfifffS_S_,@object # @_Z10build_up_bPfifffS_S_
.section .rodata,"a",@progbits
.globl _Z10build_up_bPfifffS_S_
.p2align 3, 0x0
_Z10build_up_bPfifffS_S_:
.quad _Z25__device_stub__build_up_bPfifffS_S_
.size _Z10build_up_bPfifffS_S_, 8
.type _Z25pressure_poisson_periodicPfS_S_ff,@object # @_Z25pressure_poisson_periodicPfS_S_ff
.globl _Z25pressure_poisson_periodicPfS_S_ff
.p2align 3, 0x0
_Z25pressure_poisson_periodicPfS_S_ff:
.quad _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.size _Z25pressure_poisson_periodicPfS_S_ff, 8
.type _Z11updated_u_vPfS_S_S_S_ffffff,@object # @_Z11updated_u_vPfS_S_S_S_ffffff
.globl _Z11updated_u_vPfS_S_S_S_ffffff
.p2align 3, 0x0
_Z11updated_u_vPfS_S_S_S_ffffff:
.quad _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.size _Z11updated_u_vPfS_S_S_S_ffffff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Step: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": udiff = "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Step Count = "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time = "
.size .L.str.3, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10build_up_bPfifffS_S_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25pressure_poisson_periodicPfS_S_ff"
.size .L__unnamed_2, 38
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11updated_u_vPfS_S_S_S_ffffff"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__build_up_bPfifffS_S_
.addrsig_sym _Z40__device_stub__pressure_poisson_periodicPfS_S_ff
.addrsig_sym _Z26__device_stub__updated_u_vPfS_S_S_S_ffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10build_up_bPfifffS_S_
.addrsig_sym _Z25pressure_poisson_periodicPfS_S_ff
.addrsig_sym _Z11updated_u_vPfS_S_S_S_ffffff
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} | .file "tmpxft_00176a62_00000000-6_cudaTools.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getBlockIdv
.type _Z10getBlockIdv, @function
_Z10getBlockIdv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getBlockIdv, .-_Z10getBlockIdv
.globl _Z11getThreadIdv
.type _Z11getThreadIdv, @function
_Z11getThreadIdv:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11getThreadIdv, .-_Z11getThreadIdv
.globl _Z11getGlobalIdv
.type _Z11getGlobalIdv, @function
_Z11getGlobalIdv:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11getGlobalIdv, .-_Z11getGlobalIdv
.globl _Z5indexii
.type _Z5indexii, @function
_Z5indexii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z5indexii, .-_Z5indexii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} | #include <hip/hip_runtime.h>
__device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ int getBlockId()
{
return blockIdx.x
+ blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
}
__device__ int getThreadId()
{
return (threadIdx.z * (blockDim.x * blockDim.y))
+ (threadIdx.y * blockDim.x)
+ threadIdx.x;
}
__device__ int getGlobalId()
{
int blockId = getBlockId();
int threadId = getThreadId();
return blockId * (blockDim.x * blockDim.y * blockDim.z) + threadId;
}
__device__ int index(int partid, int comp)
{
return 3*partid + comp;
} | .text
.file "cudaTools.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00176a62_00000000-6_cudaTools.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getBlockIdv
.type _Z10getBlockIdv, @function
_Z10getBlockIdv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getBlockIdv, .-_Z10getBlockIdv
.globl _Z11getThreadIdv
.type _Z11getThreadIdv, @function
_Z11getThreadIdv:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11getThreadIdv, .-_Z11getThreadIdv
.globl _Z11getGlobalIdv
.type _Z11getGlobalIdv, @function
_Z11getGlobalIdv:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11getGlobalIdv, .-_Z11getGlobalIdv
.globl _Z5indexii
.type _Z5indexii, @function
_Z5indexii:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z5indexii, .-_Z5indexii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaTools.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(cudaMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(cudaMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstarts, basestart, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstops, basestop, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), cudaMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(cudaFree(d_tooffsets));
gpuErrchk(cudaFree(d_fromstarts));
gpuErrchk(cudaFree(d_fromstops));
gpuErrchk(cudaFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} | code for sm_80
Function : _Z5adderIiEvPT_S1_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fc80003f06300 */
/*0070*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000702670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe200078010ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00e0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1405 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prefix_sum2IiEvPT_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fc600000001ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f06270 */
/*00d0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*00e0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*0100*/ @!P0 BRA 0x220 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fc80000000f00 */
/*0130*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe20003f06270 */
/*0140*/ IMAD R7, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x040fe200078e02ff */
/*0150*/ IADD3 R6, -R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe1ff */
/*0160*/ IMAD R11, R7, 0x4, R4 ; /* 0x00000004070b7824 */
/* 0x000fe400078e0204 */
/*0170*/ IMAD R9, R6, c[0x0][0x168], RZ ; /* 0x00005a0006097a24 */
/* 0x000fca00078e02ff */
/*0180*/ LEA R10, R9, R4, 0x2 ; /* 0x00000004090a7211 */
/* 0x000fe400078e10ff */
/*0190*/ @P0 IADD3 R8, -R5.reuse, R7, R0 ; /* 0x0000000705080210 */
/* 0x040fe40007ffe100 */
/*01a0*/ LDS R7, [R11] ; /* 0x000000000b077984 */
/* 0x000fe20000000800 */
/*01b0*/ SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105057819 */
/* 0x000fc600000006ff */
/*01c0*/ @P0 LDS R8, [R8.X4] ; /* 0x0000000008080984 */
/* 0x000e240000004800 */
/*01d0*/ @P0 IMAD.IADD R7, R7, 0x1, R8 ; /* 0x0000000107070824 */
/* 0x001fe200078e0208 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fc80003f06270 */
/*01f0*/ STS [R10], R7 ; /* 0x000000070a007388 */
/* 0x0001e80000000800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ @!P0 BRA 0x130 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*0220*/ IMAD R5, R6, c[0x0][0x168], RZ ; /* 0x00005a0006057a24 */
/* 0x001fca00078e02ff */
/*0230*/ LEA R5, R5, R4, 0x2 ; /* 0x0000000405057211 */
/* 0x000fcc00078e10ff */
/*0240*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e280000000800 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x190 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*00b0*/ @!P1 BRA 0x180 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*00d0*/ IADD3 R7, P1, R2.reuse, c[0x0][0x180], RZ ; /* 0x0000600002077a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R5, P2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fe40007f5e0ff */
/*00f0*/ IADD3.X R10, R4.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100040a7a10 */
/* 0x040fe40000ffe4ff */
/*0100*/ IADD3.X R8, R4, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0004087a10 */
/* 0x000fe400017fe4ff */
/*0110*/ LEA R6, P1, R7, c[0x0][0x170], 0x2 ; /* 0x00005c0007067a11 */
/* 0x000fc400078210ff */
/*0120*/ LEA R4, P2, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x000fe400078410ff */
/*0130*/ LEA.HI.X R7, R7, c[0x0][0x174], R10, 0x2, P1 ; /* 0x00005d0007077a11 */
/* 0x000fe400008f140a */
/*0140*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P2 ; /* 0x00005b0005057a11 */
/* 0x000fc800010f1408 */
/*0150*/ LDG.E R7, [R6.64+-0x4] ; /* 0xfffffc0606077981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64+-0x4] ; /* 0xfffffc0604047981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IMAD.IADD R8, R7, 0x1, -R4 ; /* 0x0000000107087824 */
/* 0x004fe400078e0a04 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe20000004800 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B0, 0x700 ; /* 0x0000054000007945 */
/* 0x000fe40003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P0 LDS R4, [R3.X4] ; /* 0x0000000003040984 */
/* 0x000fe80000004800 */
/*01e0*/ @P0 LDS R5, [R3.X4+-0x4] ; /* 0xfffffc0003050984 */
/* 0x000e240000004800 */
/*01f0*/ @P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104040824 */
/* 0x001fcc00078e0205 */
/*0200*/ @!P0 LDS R4, [RZ] ; /* 0x00000000ff048984 */
/* 0x000e220000000800 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, 0x2, PT ; /* 0x000000020300780c */
/* 0x000fc60003f06070 */
/*0220*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003060984 */
/* 0x000fe80000004800 */
/*0250*/ @P0 LDS R5, [R3.X4+0xff8] ; /* 0x000ff80003050984 */
/* 0x000e240000004800 */
/*0260*/ @P0 IMAD.IADD R6, R6, 0x1, R5 ; /* 0x0000000106060824 */
/* 0x001fcc00078e0205 */
/*0270*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fc60003f06070 */
/*0290*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*02c0*/ @P0 LDS R8, [R3.X4+-0x10] ; /* 0xfffff00003080984 */
/* 0x000e240000004800 */
/*02d0*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*02e0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x8, PT ; /* 0x000000080300780c */
/* 0x000fc60003f06070 */
/*0300*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*0330*/ @P0 LDS R8, [R3.X4+0xfe0] ; /* 0x000fe00003080984 */
/* 0x000e240000004800 */
/*0340*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0350*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, 0x10, PT ; /* 0x000000100300780c */
/* 0x000fc60003f06070 */
/*0370*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*03a0*/ @P0 LDS R8, [R3.X4+-0x40] ; /* 0xffffc00003080984 */
/* 0x000e240000004800 */
/*03b0*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*03c0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fc60003f06070 */
/*03e0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*0410*/ @P0 LDS R8, [R3.X4+0xf80] ; /* 0x000f800003080984 */
/* 0x000e240000004800 */
/*0420*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0430*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R3, 0x40, PT ; /* 0x000000400300780c */
/* 0x000fc60003f06070 */
/*0450*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*0480*/ @P0 LDS R8, [R3.X4+-0x100] ; /* 0xffff000003080984 */
/* 0x000e240000004800 */
/*0490*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*04a0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*04b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x80, PT ; /* 0x000000800300780c */
/* 0x000fc60003f06070 */
/*04c0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*04f0*/ @P0 LDS R8, [R3.X4+0xe00] ; /* 0x000e000003080984 */
/* 0x000e240000004800 */
/*0500*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0510*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R3, 0x100, PT ; /* 0x000001000300780c */
/* 0x000fc60003f06070 */
/*0530*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*0560*/ @P0 LDS R8, [R3.X4+-0x400] ; /* 0xfffc000003080984 */
/* 0x000e240000004800 */
/*0570*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*0580*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*0590*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fc60003f06070 */
/*05a0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*05d0*/ @P0 LDS R8, [R3.X4+0x800] ; /* 0x0008000003080984 */
/* 0x000e240000004800 */
/*05e0*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fc400078e0208 */
/*05f0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0209 */
/*0600*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0610*/ ISETP.NE.AND P0, PT, R2, 0x3ff, PT ; /* 0x000003ff0200780c */
/* 0x000fc60003f05270 */
/*0620*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ LDS R7, [R3.X4] ; /* 0x0000000003077984 */
/* 0x000e280000004800 */
/*0650*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101906 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ @!P0 BRA 0x6f0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0680*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000800 */
/*0690*/ LEA R3, R0, 0x3ff, 0xa ; /* 0x000003ff00037811 */
/* 0x000fe200078e50ff */
/*06a0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*06b0*/ ISETP.NE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fc60003f05270 */
/*06c0*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe4000bf25270 */
/*06d0*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*06e0*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x001ea2000c1e1900 */
/*0710*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x190] ; /* 0x0000640000027625 */
/* 0x000fca00078e0009 */
/*0720*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(cudaMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(cudaMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstarts, basestart, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstops, basestop, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), cudaMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(cudaFree(d_tooffsets));
gpuErrchk(cudaFree(d_fromstarts));
gpuErrchk(cudaFree(d_fromstops));
gpuErrchk(cudaFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} | .file "tmpxft_000273b9_00000000-6_hillisfinal.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_, @function
_ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_:
.LFB3702:
.cfi_startproc
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_, .-_ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, @function
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
.LFB4011:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4011:
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .-_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.text
.type _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii, @function
_ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii:
.LFB3704:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11prefix_sum2IiEvPT_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii, .-_ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.weak _Z11prefix_sum2IiEvPT_i
.type _Z11prefix_sum2IiEvPT_i, @function
_Z11prefix_sum2IiEvPT_i:
.LFB4013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4013:
.size _Z11prefix_sum2IiEvPT_i, .-_Z11prefix_sum2IiEvPT_i
.text
.type _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l, @function
_ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l:
.LFB3706:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5adderIiEvPT_S1_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l, .-_ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.weak _Z5adderIiEvPT_S1_l
.type _Z5adderIiEvPT_S1_l, @function
_Z5adderIiEvPT_S1_l:
.LFB4014:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4014:
.size _Z5adderIiEvPT_S1_l, .-_Z5adderIiEvPT_S1_l
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5adderIiEvPT_S1_l"
.LC1:
.string "_Z11prefix_sum2IiEvPT_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3709:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5adderIiEvPT_S1_l(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_sum2IiEvPT_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z7offloadIiiEvPT_PT0_S3_lll.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/reikdas/GSoC-Proposal-2020/master/testgsoc/hillisfinal.cu"
.section .rodata._Z7offloadIiiEvPT_PT0_S3_lll.str1.1,"aMS",@progbits,1
.LC4:
.string "GPUassert: %s %s %d\n"
.section .text._Z7offloadIiiEvPT_PT0_S3_lll,"axG",@progbits,_Z7offloadIiiEvPT_PT0_S3_lll,comdat
.weak _Z7offloadIiiEvPT_PT0_S3_lll
.type _Z7offloadIiiEvPT_PT0_S3_lll, @function
_Z7offloadIiiEvPT_PT0_S3_lll:
.LFB4009:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -144(%rbp)
movq %rdx, %rdi
movq %rcx, -128(%rbp)
movq %r8, -136(%rbp)
movq %r9, %rbx
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpq $1024, %r9
jle .L30
testl $1023, %r9d
je .L31
leaq 1023(%r9), %rax
testq %r9, %r9
cmovns %r9, %rax
sarq $10, %rax
addl $1, %eax
movl %eax, -116(%rbp)
.L32:
movl -116(%rbp), %r12d
sall $10, %r12d
movslq %r12d, %r15
salq $2, %r15
movq %r15, %rax
movq %r15, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L33:
cmpq %rdx, %rsp
je .L34
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L33
.L31:
leaq 1023(%r9), %rax
testq %r9, %r9
cmovns %r9, %rax
sarq $10, %rax
movl %eax, -116(%rbp)
jmp .L32
.L34:
movq %rax, %rdx
andl $4095, %edx
je .L35
orq $0, -8(%rsp,%rdx)
.L35:
movq %rsp, %r13
movq %r15, %rax
movq %r15, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L36:
cmpq %rdx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rax, %rdx
andl $4095, %edx
je .L38
orq $0, -8(%rsp,%rdx)
.L38:
movq %rsp, %r14
testl %r12d, %r12d
jg .L69
.L39:
leal 1(%r12), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -112(%rbp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L73
leaq -96(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq -88(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L77
movslq -116(%rbp), %rsi
salq $2, %rsi
leaq -104(%rbp), %rdi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L78
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -116(%rbp), %eax
movl %eax, -120(%rbp)
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $8192, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L49:
call cudaPeekAtLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L80
call cudaDeviceSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L81
movl -120(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl -116(%rbp), %eax
addl %eax, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L52:
call cudaPeekAtLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L84
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -120(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L55:
call cudaPeekAtLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L86
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L87
leaq 4(,%rbx,4), %r12
movl $2, %ecx
movq %r12, %rdx
movq -112(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L88
subq $1, %rbx
movq -136(%rbp), %rax
addq %rbx, %rax
movl (%r14,%rax,4), %eax
movq -144(%rbp), %rcx
addl -8(%rcx,%r12), %eax
movq -128(%rbp), %rdi
addq %rdi, %rbx
subl 0(%r13,%rbx,4), %eax
movl %eax, -4(%rcx,%r12)
movq -112(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L89
movq -96(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L90
movq -88(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
movq -104(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L92
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L93
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L40:
.cfi_restore_state
movl $0, 0(%r13,%rax,4)
movl %ecx, %edx
.L41:
movl %edx, (%r14,%rax,4)
addq $1, %rax
cmpl %eax, %r12d
jle .L39
.L42:
cmpq %rax, %rbx
jle .L40
movl (%rsi,%rax,4), %edx
movl %edx, 0(%r13,%rax,4)
movl (%rdi,%rax,4), %edx
jmp .L41
.L73:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $107, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L74:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $108, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L75:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $109, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L76:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $110, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L77:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $111, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L78:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $112, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L79:
subq $8, %rsp
pushq -104(%rbp)
movl %r12d, %r9d
movq -136(%rbp), %r8
movq -128(%rbp), %rcx
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -112(%rbp), %rdi
call _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
addq $16, %rsp
jmp .L49
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $114, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $115, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L82:
movl -116(%rbp), %esi
movq -104(%rbp), %rdi
call _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
jmp .L52
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $117, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $118, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L85:
movslq %r12d, %rdx
movq -104(%rbp), %rsi
movq -112(%rbp), %rdi
call _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
jmp .L55
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $120, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $122, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $124, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $125, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $126, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $127, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L30:
leaq -4096(%rsp), %rax
.L63:
cmpq %rax, %rsp
je .L64
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L63
.L64:
movq %rsp, %r13
leaq -4096(%rsp), %rax
.L66:
cmpq %rax, %rsp
je .L67
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L66
.L67:
movq %rsp, %r14
movl $1024, %r12d
movl $1, -116(%rbp)
movl $4096, %r15d
.L69:
movl $0, %eax
movl $0, %ecx
jmp .L42
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4009:
.size _Z7offloadIiiEvPT_PT0_S3_lll, .-_Z7offloadIiiEvPT_PT0_S3_lll
.section .rodata.str1.1
.LC5:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3677:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -4796416(%rsp), %r11
.cfi_def_cfa 11, 4796456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3608, %rsp
.cfi_def_cfa_offset 4800064
movq %fs:40, %rax
movq %rax, 4800008(%rsp)
xorl %eax, %eax
.L95:
movl %eax, (%rsp,%rax,4)
leal 10(%rax), %edx
movl %edx, 1600000(%rsp,%rax,4)
addq $1, %rax
cmpq $400000, %rax
jne .L95
leaq 1600000(%rsp), %rdx
movq %rsp, %rsi
leaq 3200000(%rsp), %rbx
movl $400000, %r9d
movl $0, %r8d
movl $0, %ecx
movq %rbx, %rdi
call _Z7offloadIiiEvPT_PT0_S3_lll
leaq 4800004(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L96:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L96
movq 4800008(%rsp), %rax
subq %fs:40, %rax
jne .L101
movl $0, %eax
addq $4800024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(cudaMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(cudaMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstarts, basestart, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(cudaMemcpy(d_fromstops, basestop, modlength * sizeof(C), cudaMemcpyHostToDevice));
gpuErrchk(cudaMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), cudaMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(cudaFree(d_tooffsets));
gpuErrchk(cudaFree(d_fromstarts));
gpuErrchk(cudaFree(d_fromstops));
gpuErrchk(cudaFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(hipMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(hipMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstarts, basestart, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstops, basestop, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), hipMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(hipFree(d_tooffsets));
gpuErrchk(hipFree(d_fromstarts));
gpuErrchk(hipFree(d_fromstops));
gpuErrchk(hipFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(hipMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(hipMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstarts, basestart, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstops, basestop, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), hipMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(hipFree(d_tooffsets));
gpuErrchk(hipFree(d_fromstarts));
gpuErrchk(hipFree(d_fromstops));
gpuErrchk(hipFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.protected _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.globl _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 8
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@function
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x28
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_16
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b256 s[8:15], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[6:7], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_lshl_b64 s[6:7], s[12:13], 2
v_add_co_u32 v5, vcc_lo, s10, v3
s_add_u32 s6, s6, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
s_addc_u32 s7, s7, s9
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off offset:-4
global_load_b32 v3, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v5, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v5, v0, 2, 0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s5, 1
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_sub_i32 s2, 1, s2
s_lshl_b32 s6, s5, 1
v_lshl_or_b32 v5, s2, 12, v3
s_cmpk_gt_u32 s5, 0x1ff
s_mov_b32 s5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, 0, v5
s_waitcnt lgkmcnt(0)
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_5:
v_lshl_or_b32 v6, s2, 10, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v6, 2, 0
v_cmpx_le_u32_e64 s5, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_7
v_subrev_nc_u32_e32 v4, s5, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
.LBB0_7:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_4
ds_load_b32 v4, v5
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_mov_b32 s2, 0
s_mov_b32 s5, exec_lo
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s6, -1
global_store_b32 v[2:3], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_ne_u32_e32 0x3ff, v1
s_cbranch_execz .LBB0_14
s_cmp_lg_u32 s4, 0
s_mov_b32 s6, 0
s_cbranch_scc0 .LBB0_17
s_lshl_b32 s2, s4, 10
s_add_i32 s7, s3, -1
s_or_b32 s2, s2, 0x3ff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
v_cmp_eq_u32_e64 s2, s7, v1
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_13
.LBB0_12:
s_add_i32 s3, s3, -1
s_and_not1_b32 s2, s2, exec_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v1
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s6, s2, exec_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_16
global_load_b32 v0, v[2:3], off
s_load_b64 s[0:1], s[0:1], 0x30
s_mov_b32 s5, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_17:
s_branch .LBB0_12
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.Lfunc_end0:
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .Lfunc_end0-_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.protected _Z11prefix_sum2IiEvPT_i
.globl _Z11prefix_sum2IiEvPT_i
.p2align 8
.type _Z11prefix_sum2IiEvPT_i,@function
_Z11prefix_sum2IiEvPT_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_9
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_add_u32 v4, v1, 2, 0
s_cmp_lt_i32 s2, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_8
s_mov_b32 s1, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_sub_i32 s0, 1, s0
s_lshl_b32 s1, s1, 1
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_cmp_ge_i32 s1, s2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_8
.LBB1_4:
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v4, 2, 0
v_cmpx_le_i32_e64 s1, v1
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB1_6
v_subrev_nc_u32_e32 v0, s1, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v0, v0
ds_load_b32 v4, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
.LBB1_6:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB1_3
ds_load_b32 v0, v5
s_branch .LBB1_3
.LBB1_8:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v4, 2, 0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v0, off
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_sum2IiEvPT_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.Lfunc_end1:
.size _Z11prefix_sum2IiEvPT_i, .Lfunc_end1-_Z11prefix_sum2IiEvPT_i
.section .AMDGPU.csdata,"",@progbits
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.protected _Z5adderIiEvPT_S1_l
.globl _Z5adderIiEvPT_S1_l
.p2align 8
.type _Z5adderIiEvPT_S1_l,@function
_Z5adderIiEvPT_S1_l:
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB2_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s15, -1
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
global_load_b32 v2, v[0:1], off
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5adderIiEvPT_S1_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.Lfunc_end2:
.size _Z5adderIiEvPT_S1_l, .Lfunc_end2-_Z5adderIiEvPT_S1_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_sum2IiEvPT_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_sum2IiEvPT_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5adderIiEvPT_S1_l
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5adderIiEvPT_S1_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
// https://stackoverflow.com/a/14038590/4647107
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
template <typename T, typename C>
__global__
void prefix_sum1(T* base, const C* basestart, const C* basestop, int64_t basestartoffset, int64_t basestopoffset, int length, T* sums) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
if (thid == 0) {
temp[threadIdx.x] = 0;
}
else {
temp[threadIdx.x] = basestop[basestopoffset + thid - 1] - basestart[basestartoffset + thid - 1];
}
__syncthreads();
for (int offset = 1; offset < 1024; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (threadIdx.x >= offset) {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x - offset] + temp[pin*1024 + threadIdx.x];
}
else {
temp[pout*1024 + threadIdx.x] = temp[pin*1024 + threadIdx.x];
}
__syncthreads();
}
base[thid] = temp[pout*1024 + threadIdx.x];
__syncthreads();
if ((thid == 1023) || ((blockIdx.x != 0) && (thid == ((1024 * (blockIdx.x + 1))-1))) || (thid == length-1)) {
sums[blockIdx.x] = base[thid];
}
}
}
// Need another kernel because of conditional __syncthreads()
template <typename T>
__global__
void prefix_sum2(T* base, int length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
extern __shared__ T temp[];
int pout = 0, pin = 1;
if (thid < length) {
temp[thid] = base[thid];
__syncthreads();
for (int offset = 1; offset < length; offset *=2) {
pout = 1 - pout;
pin = 1 - pout;
if (thid >= offset)
temp[pout*length + thid] = temp[pin*length + thid - offset] + temp[pin*length + thid];
else
temp[pout*length + thid] = temp[pin*length + thid];
__syncthreads();
}
base[thid] = temp[pout*length + thid];
}
}
template<typename T>
__global__
void adder(T* base, T* sums, int64_t length) {
int thid = threadIdx.x + (blockIdx.x * blockDim.x);
if (blockIdx.x != 0 && thid < length)
base[thid] += sums[blockIdx.x - 1];
}
template <typename T, typename C>
void offload(T* base, C* basestart1, C* basestop1, int64_t basestartoffset, int64_t basestopoffset, int64_t length) {
int block, thread=1024;
if (length > 1024) {
if (length%1024 != 0)
block = (length / 1024) + 1;
else
block = length/1024;
}
else {
block = 1;
}
int modlength = block*thread;
// Padding the input arrays
C basestart[modlength], basestop[modlength];
for (int i=0; i<modlength; i++) {
if (i<length){
basestart[i] = basestart1[i];
basestop[i] = basestop1[i];
}
else {
basestart[i] = 0;
basestop[i] = 0;
}
}
T* d_tooffsets, * d_sums;
C* d_fromstarts, * d_fromstops;
gpuErrchk(hipMalloc((void**)&d_tooffsets, (modlength+1) * sizeof(T)));
gpuErrchk(hipMalloc((void**)&d_fromstarts, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstarts, basestart, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_fromstops, modlength * sizeof(C)));
gpuErrchk(hipMemcpy(d_fromstops, basestop, modlength * sizeof(C), hipMemcpyHostToDevice));
gpuErrchk(hipMalloc((void**)&d_sums, block*sizeof(T)));
prefix_sum1<T, C><<<block, thread, thread*2*sizeof(T)>>>(d_tooffsets, d_fromstarts, d_fromstops, basestartoffset, basestopoffset, modlength, d_sums);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
prefix_sum2<T><<<1, block, block*2*sizeof(T)>>>(d_sums, block);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
adder<T><<<block, thread>>>(d_tooffsets, d_sums, modlength);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(base, d_tooffsets, (length + 1) * sizeof(T), hipMemcpyDeviceToHost));
base[length] = base[length - 1] + basestop[length - 1 + basestopoffset] - basestart[length - 1 + basestartoffset];
gpuErrchk(hipFree(d_tooffsets));
gpuErrchk(hipFree(d_fromstarts));
gpuErrchk(hipFree(d_fromstops));
gpuErrchk(hipFree(d_sums));
}
int main() {
const int size = 400000;
int base[size + 1], basestart[size], basestop[size];
for (int i = 0; i < size; i++) {
basestart[i] = i;
basestop[i] = i + 10;
}
offload<int, int>(base, basestart, basestop, 0, 0, size);
for (int i = 0; i < size + 1; i++) {
std::cout << base[i] << "\n";
}
return 0;
} | .text
.file "hillisfinal.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4800016, %rsp # imm = 0x493E10
.cfi_def_cfa_offset 4800032
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, 1600000(%rsp,%rax,4)
leal 10(%rax), %ecx
movl %ecx, (%rsp,%rax,4)
incq %rax
cmpq $400000, %rax # imm = 0x61A80
jne .LBB0_1
# %bb.2:
xorl %ebx, %ebx
leaq 3200000(%rsp), %rdi
leaq 1600000(%rsp), %rsi
movq %rsp, %rdx
movl $400000, %r9d # imm = 0x61A80
xorl %ecx, %ecx
xorl %r8d, %r8d
callq _Z7offloadIiiEvPT_PT0_S3_lll
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl 3200000(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $400001, %rbx # imm = 0x61A81
jne .LBB0_3
# %bb.4:
xorl %eax, %eax
addq $4800016, %rsp # imm = 0x493E10
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z7offloadIiiEvPT_PT0_S3_lll,"axG",@progbits,_Z7offloadIiiEvPT_PT0_S3_lll,comdat
.weak _Z7offloadIiiEvPT_PT0_S3_lll # -- Begin function _Z7offloadIiiEvPT_PT0_S3_lll
.p2align 4, 0x90
.type _Z7offloadIiiEvPT_PT0_S3_lll,@function
_Z7offloadIiiEvPT_PT0_S3_lll: # @_Z7offloadIiiEvPT_PT0_S3_lll
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %r9, %rbx
movq %r8, -160(%rbp) # 8-byte Spill
movq %rcx, -168(%rbp) # 8-byte Spill
movl $1, %r9d
cmpq $1025, %rbx # imm = 0x401
jl .LBB1_2
# %bb.1:
movl %ebx, %eax
andl $1023, %eax # imm = 0x3FF
movq %rbx, %r9
shrq $10, %r9
cmpq $1, %rax
sbbl $-1, %r9d
.LBB1_2:
movl %r9d, %r12d
shll $10, %r12d
movq %rsp, %r13
leaq (,%r12,4), %rax
subq %rax, %r13
movq %r13, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
testl %r9d, %r9d
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovgel %r12d, %eax
xorl %ecx, %ecx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_4 Depth=1
movl (%rsi,%rcx,4), %r8d
movl %r8d, (%r13,%rcx,4)
movl (%rdx,%rcx,4), %r8d
.LBB1_20: # in Loop: Header=BB1_4 Depth=1
movl %r8d, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
je .LBB1_6
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %rbx, %rcx
jl .LBB1_5
# %bb.19: # in Loop: Header=BB1_4 Depth=1
movl $0, (%r13,%rcx,4)
xorl %r8d, %r8d
jmp .LBB1_20
.LBB1_6: # %._crit_edge
movq %r9, -176(%rbp) # 8-byte Spill
movq %rdi, -256(%rbp) # 8-byte Spill
movl %r12d, %eax
orl $1, %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq -120(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit
movslq %r12d, %rax
movq %rax, -248(%rbp) # 8-byte Spill
leaq (,%rax,4), %r15
leaq -136(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit67
movq -136(%rbp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit69
leaq -128(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit71
movq -128(%rbp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit73
movq -176(%rbp), %r15 # 8-byte Reload
movslq %r15d, %rsi
shlq $2, %rsi
leaq -112(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_18
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit75
movabsq $4294968320, %rdx # imm = 0x100000400
movl %r15d, %eax
leaq (%rax,%rdx), %r15
addq $-1024, %r15 # imm = 0xFC00
movl $8192, %r8d # imm = 0x2000
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.22:
movq -120(%rbp), %rax
movq -136(%rbp), %rcx
movq -128(%rbp), %rdx
movq -112(%rbp), %rsi
movq %rax, -104(%rbp)
movq %rcx, -96(%rbp)
movq %rdx, -88(%rbp)
movq -168(%rbp), %rax # 8-byte Reload
movq %rax, -48(%rbp)
movq -160(%rbp), %rax # 8-byte Reload
movq %rax, -144(%rbp)
movl %r12d, -148(%rbp)
movq %rsi, -280(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -96(%rbp), %rax
movq %rax, -232(%rbp)
leaq -88(%rbp), %rax
movq %rax, -224(%rbp)
leaq -48(%rbp), %rax
movq %rax, -216(%rbp)
leaq -144(%rbp), %rax
movq %rax, -208(%rbp)
leaq -148(%rbp), %rax
movq %rax, -200(%rbp)
leaq -280(%rbp), %rax
movq %rax, -192(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -272(%rbp), %rdx
leaq -264(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %edi
pushq -264(%rbp)
pushq -272(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_23:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_49
# %bb.24: # %_Z9gpuAssert10hipError_tPKcib.exit77
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit79
movq -176(%rbp), %r12 # 8-byte Reload
leal (%r12,%r12), %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $4294968320, %rax # imm = 0x100000400
leaq -1023(%rax), %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_28
# %bb.27:
movq -112(%rbp), %rax
movq %rax, -104(%rbp)
movl %r12d, -48(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -48(%rbp), %rax
movq %rax, -232(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z11prefix_sum2IiEvPT_i, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_28:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_29
# %bb.30: # %_Z9gpuAssert10hipError_tPKcib.exit87
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit89
movq %r15, %rdi
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_34
# %bb.33:
movq -120(%rbp), %rax
movq -112(%rbp), %rcx
movq %rax, -104(%rbp)
movq %rcx, -96(%rbp)
movq -248(%rbp), %rax # 8-byte Reload
movq %rax, -88(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -96(%rbp), %rax
movq %rax, -232(%rbp)
leaq -88(%rbp), %rax
movq %rax, -224(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -48(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z5adderIiEvPT_S1_l, %edi
pushq -144(%rbp)
pushq -48(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_34:
callq hipPeekAtLastError
testl %eax, %eax
movq -256(%rbp), %r15 # 8-byte Reload
jne .LBB1_35
# %bb.36: # %_Z9gpuAssert10hipError_tPKcib.exit97
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit99
movq -120(%rbp), %rsi
leaq 4(,%rbx,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit101
leaq (%r14,%rbx,4), %rax
addq $-4, %rax
movq -160(%rbp), %rcx # 8-byte Reload
movl (%rax,%rcx,4), %eax
addl -4(%r15,%rbx,4), %eax
leaq -4(,%rbx,4), %rcx
addq %r13, %rcx
movq -168(%rbp), %rdx # 8-byte Reload
subl (%rcx,%rdx,4), %eax
movl %eax, (%r15,%rbx,4)
movq -120(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit103
movq -136(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit105
movq -128(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit107
movq -112(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_47
# %bb.48: # %_Z9gpuAssert10hipError_tPKcib.exit109
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_7:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $107, %r8d
jmp .LBB1_8
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB1_8
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB1_8
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $110, %r8d
jmp .LBB1_8
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_8
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $112, %r8d
jmp .LBB1_8
.LBB1_49:
movl %eax, %r12d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $114, %r8d
xorl %eax, %eax
callq fprintf
movl %r12d, %edi
callq exit
.LBB1_25:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_8
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $117, %r8d
jmp .LBB1_8
.LBB1_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $118, %r8d
jmp .LBB1_8
.LBB1_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $120, %r8d
jmp .LBB1_8
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $121, %r8d
jmp .LBB1_8
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $122, %r8d
jmp .LBB1_8
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB1_8
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_8
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_8
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $127, %r8d
.LBB1_8:
xorl %eax, %eax
callq fprintf
movl %r14d, %edi
callq exit
.Lfunc_end1:
.size _Z7offloadIiiEvPT_PT0_S3_lll, .Lfunc_end1-_Z7offloadIiiEvPT_PT0_S3_lll
.cfi_endproc
# -- End function
.section .text._Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_ # -- Begin function _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 4, 0x90
.type _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@function
_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_: # @_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .Lfunc_end2-_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.cfi_endproc
# -- End function
.section .text._Z26__device_stub__prefix_sum2IiEvPT_i,"axG",@progbits,_Z26__device_stub__prefix_sum2IiEvPT_i,comdat
.weak _Z26__device_stub__prefix_sum2IiEvPT_i # -- Begin function _Z26__device_stub__prefix_sum2IiEvPT_i
.p2align 4, 0x90
.type _Z26__device_stub__prefix_sum2IiEvPT_i,@function
_Z26__device_stub__prefix_sum2IiEvPT_i: # @_Z26__device_stub__prefix_sum2IiEvPT_i
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11prefix_sum2IiEvPT_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__prefix_sum2IiEvPT_i, .Lfunc_end3-_Z26__device_stub__prefix_sum2IiEvPT_i
.cfi_endproc
# -- End function
.section .text._Z20__device_stub__adderIiEvPT_S1_l,"axG",@progbits,_Z20__device_stub__adderIiEvPT_S1_l,comdat
.weak _Z20__device_stub__adderIiEvPT_S1_l # -- Begin function _Z20__device_stub__adderIiEvPT_S1_l
.p2align 4, 0x90
.type _Z20__device_stub__adderIiEvPT_S1_l,@function
_Z20__device_stub__adderIiEvPT_S1_l: # @_Z20__device_stub__adderIiEvPT_S1_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5adderIiEvPT_S1_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z20__device_stub__adderIiEvPT_S1_l, .Lfunc_end4-_Z20__device_stub__adderIiEvPT_S1_l
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_sum2IiEvPT_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5adderIiEvPT_S1_l, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/reikdas/GSoC-Proposal-2020/master/testgsoc/hillisfinal.hip"
.size .L.str.1, 116
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@object # @_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.section .rodata._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"aG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 3, 0x0
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
.quad _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, 8
.type _Z11prefix_sum2IiEvPT_i,@object # @_Z11prefix_sum2IiEvPT_i
.section .rodata._Z11prefix_sum2IiEvPT_i,"aG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.weak _Z11prefix_sum2IiEvPT_i
.p2align 3, 0x0
_Z11prefix_sum2IiEvPT_i:
.quad _Z26__device_stub__prefix_sum2IiEvPT_i
.size _Z11prefix_sum2IiEvPT_i, 8
.type _Z5adderIiEvPT_S1_l,@object # @_Z5adderIiEvPT_S1_l
.section .rodata._Z5adderIiEvPT_S1_l,"aG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.weak _Z5adderIiEvPT_S1_l
.p2align 3, 0x0
_Z5adderIiEvPT_S1_l:
.quad _Z20__device_stub__adderIiEvPT_S1_l
.size _Z5adderIiEvPT_S1_l, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11prefix_sum2IiEvPT_i"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5adderIiEvPT_S1_l"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.addrsig_sym _Z26__device_stub__prefix_sum2IiEvPT_i
.addrsig_sym _Z20__device_stub__adderIiEvPT_S1_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.addrsig_sym _Z11prefix_sum2IiEvPT_i
.addrsig_sym _Z5adderIiEvPT_S1_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5adderIiEvPT_S1_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fc80003f06300 */
/*0070*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000702670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe200078010ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0003 */
/*00e0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1405 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prefix_sum2IiEvPT_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fc600000001ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f06270 */
/*00d0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe200078e00ff */
/*00e0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*0100*/ @!P0 BRA 0x220 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fc80000000f00 */
/*0130*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe20003f06270 */
/*0140*/ IMAD R7, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006077a24 */
/* 0x040fe200078e02ff */
/*0150*/ IADD3 R6, -R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc60007ffe1ff */
/*0160*/ IMAD R11, R7, 0x4, R4 ; /* 0x00000004070b7824 */
/* 0x000fe400078e0204 */
/*0170*/ IMAD R9, R6, c[0x0][0x168], RZ ; /* 0x00005a0006097a24 */
/* 0x000fca00078e02ff */
/*0180*/ LEA R10, R9, R4, 0x2 ; /* 0x00000004090a7211 */
/* 0x000fe400078e10ff */
/*0190*/ @P0 IADD3 R8, -R5.reuse, R7, R0 ; /* 0x0000000705080210 */
/* 0x040fe40007ffe100 */
/*01a0*/ LDS R7, [R11] ; /* 0x000000000b077984 */
/* 0x000fe20000000800 */
/*01b0*/ SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105057819 */
/* 0x000fc600000006ff */
/*01c0*/ @P0 LDS R8, [R8.X4] ; /* 0x0000000008080984 */
/* 0x000e240000004800 */
/*01d0*/ @P0 IMAD.IADD R7, R7, 0x1, R8 ; /* 0x0000000107070824 */
/* 0x001fe200078e0208 */
/*01e0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fc80003f06270 */
/*01f0*/ STS [R10], R7 ; /* 0x000000070a007388 */
/* 0x0001e80000000800 */
/*0200*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0210*/ @!P0 BRA 0x130 ; /* 0xffffff1000008947 */
/* 0x001fea000383ffff */
/*0220*/ IMAD R5, R6, c[0x0][0x168], RZ ; /* 0x00005a0006057a24 */
/* 0x001fca00078e02ff */
/*0230*/ LEA R5, R5, R4, 0x2 ; /* 0x0000000405057211 */
/* 0x000fcc00078e10ff */
/*0240*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e280000000800 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x190 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0090*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*00b0*/ @!P1 BRA 0x180 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe40000011402 */
/*00d0*/ IADD3 R7, P1, R2.reuse, c[0x0][0x180], RZ ; /* 0x0000600002077a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R5, P2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fe40007f5e0ff */
/*00f0*/ IADD3.X R10, R4.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100040a7a10 */
/* 0x040fe40000ffe4ff */
/*0100*/ IADD3.X R8, R4, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0004087a10 */
/* 0x000fe400017fe4ff */
/*0110*/ LEA R6, P1, R7, c[0x0][0x170], 0x2 ; /* 0x00005c0007067a11 */
/* 0x000fc400078210ff */
/*0120*/ LEA R4, P2, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x000fe400078410ff */
/*0130*/ LEA.HI.X R7, R7, c[0x0][0x174], R10, 0x2, P1 ; /* 0x00005d0007077a11 */
/* 0x000fe400008f140a */
/*0140*/ LEA.HI.X R5, R5, c[0x0][0x16c], R8, 0x2, P2 ; /* 0x00005b0005057a11 */
/* 0x000fc800010f1408 */
/*0150*/ LDG.E R7, [R6.64+-0x4] ; /* 0xfffffc0606077981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R4, [R4.64+-0x4] ; /* 0xfffffc0604047981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IMAD.IADD R8, R7, 0x1, -R4 ; /* 0x0000000107087824 */
/* 0x004fe400078e0a04 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe20000004800 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B0, 0x700 ; /* 0x0000054000007945 */
/* 0x000fe40003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ @P0 LDS R4, [R3.X4] ; /* 0x0000000003040984 */
/* 0x000fe80000004800 */
/*01e0*/ @P0 LDS R5, [R3.X4+-0x4] ; /* 0xfffffc0003050984 */
/* 0x000e240000004800 */
/*01f0*/ @P0 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104040824 */
/* 0x001fcc00078e0205 */
/*0200*/ @!P0 LDS R4, [RZ] ; /* 0x00000000ff048984 */
/* 0x000e220000000800 */
/*0210*/ ISETP.GE.U32.AND P0, PT, R3, 0x2, PT ; /* 0x000000020300780c */
/* 0x000fc60003f06070 */
/*0220*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003060984 */
/* 0x000fe80000004800 */
/*0250*/ @P0 LDS R5, [R3.X4+0xff8] ; /* 0x000ff80003050984 */
/* 0x000e240000004800 */
/*0260*/ @P0 IMAD.IADD R6, R6, 0x1, R5 ; /* 0x0000000106060824 */
/* 0x001fcc00078e0205 */
/*0270*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fc60003f06070 */
/*0290*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*02c0*/ @P0 LDS R8, [R3.X4+-0x10] ; /* 0xfffff00003080984 */
/* 0x000e240000004800 */
/*02d0*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*02e0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x8, PT ; /* 0x000000080300780c */
/* 0x000fc60003f06070 */
/*0300*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*0330*/ @P0 LDS R8, [R3.X4+0xfe0] ; /* 0x000fe00003080984 */
/* 0x000e240000004800 */
/*0340*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0350*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, 0x10, PT ; /* 0x000000100300780c */
/* 0x000fc60003f06070 */
/*0370*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*03a0*/ @P0 LDS R8, [R3.X4+-0x40] ; /* 0xffffc00003080984 */
/* 0x000e240000004800 */
/*03b0*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*03c0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fc60003f06070 */
/*03e0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0400*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*0410*/ @P0 LDS R8, [R3.X4+0xf80] ; /* 0x000f800003080984 */
/* 0x000e240000004800 */
/*0420*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0430*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R3, 0x40, PT ; /* 0x000000400300780c */
/* 0x000fc60003f06070 */
/*0450*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*0480*/ @P0 LDS R8, [R3.X4+-0x100] ; /* 0xffff000003080984 */
/* 0x000e240000004800 */
/*0490*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*04a0*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*04b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x80, PT ; /* 0x000000800300780c */
/* 0x000fc60003f06070 */
/*04c0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*04d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04e0*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*04f0*/ @P0 LDS R8, [R3.X4+0xe00] ; /* 0x000e000003080984 */
/* 0x000e240000004800 */
/*0500*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fcc00078e0208 */
/*0510*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R3, 0x100, PT ; /* 0x000001000300780c */
/* 0x000fc60003f06070 */
/*0530*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ @P0 LDS R5, [R3.X4] ; /* 0x0000000003050984 */
/* 0x000fe80000004800 */
/*0560*/ @P0 LDS R8, [R3.X4+-0x400] ; /* 0xfffc000003080984 */
/* 0x000e240000004800 */
/*0570*/ @P0 IMAD.IADD R4, R5, 0x1, R8 ; /* 0x0000000105040824 */
/* 0x001fcc00078e0208 */
/*0580*/ @!P0 LDS R4, [R3.X4] ; /* 0x0000000003048984 */
/* 0x000e220000004800 */
/*0590*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fc60003f06070 */
/*05a0*/ STS [R3.X4+0x1000], R4 ; /* 0x0010000403007388 */
/* 0x001fe80000004800 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ @P0 LDS R5, [R3.X4+0x1000] ; /* 0x0010000003050984 */
/* 0x000fe80000004800 */
/*05d0*/ @P0 LDS R8, [R3.X4+0x800] ; /* 0x0008000003080984 */
/* 0x000e240000004800 */
/*05e0*/ @P0 IMAD.IADD R6, R5, 0x1, R8 ; /* 0x0000000105060824 */
/* 0x001fc400078e0208 */
/*05f0*/ IMAD.WIDE R4, R2, R9, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0209 */
/*0600*/ @!P0 LDS R6, [R3.X4+0x1000] ; /* 0x0010000003068984 */
/* 0x000e220000004800 */
/*0610*/ ISETP.NE.AND P0, PT, R2, 0x3ff, PT ; /* 0x000003ff0200780c */
/* 0x000fc60003f05270 */
/*0620*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000004800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ LDS R7, [R3.X4] ; /* 0x0000000003077984 */
/* 0x000e280000004800 */
/*0650*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e8000c101906 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0670*/ @!P0 BRA 0x6f0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0680*/ ULDC UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000800 */
/*0690*/ LEA R3, R0, 0x3ff, 0xa ; /* 0x000003ff00037811 */
/* 0x000fe200078e50ff */
/*06a0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*06b0*/ ISETP.NE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fc60003f05270 */
/*06c0*/ ISETP.NE.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe4000bf25270 */
/*06d0*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*06e0*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x001ea2000c1e1900 */
/*0710*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x190] ; /* 0x0000640000027625 */
/* 0x000fca00078e0009 */
/*0720*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.protected _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.globl _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 8
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@function
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x28
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_16
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, 0
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_3
s_load_b256 s[8:15], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[6:7], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s10, s6, s10
s_addc_u32 s11, s7, s11
s_lshl_b64 s[6:7], s[12:13], 2
v_add_co_u32 v5, vcc_lo, s10, v3
s_add_u32 s6, s6, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
s_addc_u32 s7, s7, s9
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v5, v[5:6], off offset:-4
global_load_b32 v3, v[3:4], off offset:-4
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v5, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v5, v0, 2, 0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s5, 1
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_sub_i32 s2, 1, s2
s_lshl_b32 s6, s5, 1
v_lshl_or_b32 v5, s2, 12, v3
s_cmpk_gt_u32 s5, 0x1ff
s_mov_b32 s5, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, 0, v5
s_waitcnt lgkmcnt(0)
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_5:
v_lshl_or_b32 v6, s2, 10, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v6, 2, 0
v_cmpx_le_u32_e64 s5, v0
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_7
v_subrev_nc_u32_e32 v4, s5, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v4, v4
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
.LBB0_7:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_4
ds_load_b32 v4, v5
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_mov_b32 s2, 0
s_mov_b32 s5, exec_lo
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s6, -1
global_store_b32 v[2:3], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_ne_u32_e32 0x3ff, v1
s_cbranch_execz .LBB0_14
s_cmp_lg_u32 s4, 0
s_mov_b32 s6, 0
s_cbranch_scc0 .LBB0_17
s_lshl_b32 s2, s4, 10
s_add_i32 s7, s3, -1
s_or_b32 s2, s2, 0x3ff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
v_cmp_eq_u32_e64 s2, s7, v1
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_13
.LBB0_12:
s_add_i32 s3, s3, -1
s_and_not1_b32 s2, s2, exec_lo
v_cmp_eq_u32_e32 vcc_lo, s3, v1
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s6, s2, exec_lo
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_16
global_load_b32 v0, v[2:3], off
s_load_b64 s[0:1], s[0:1], 0x30
s_mov_b32 s5, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_17:
s_branch .LBB0_12
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.Lfunc_end0:
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .Lfunc_end0-_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.protected _Z11prefix_sum2IiEvPT_i
.globl _Z11prefix_sum2IiEvPT_i
.p2align 8
.type _Z11prefix_sum2IiEvPT_i,@function
_Z11prefix_sum2IiEvPT_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_9
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_lshl_add_u32 v4, v1, 2, 0
s_cmp_lt_i32 s2, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_8
s_mov_b32 s1, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_sub_i32 s0, 1, s0
s_lshl_b32 s1, s1, 1
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_cmp_ge_i32 s1, s2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
s_waitcnt lgkmcnt(0)
ds_store_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_8
.LBB1_4:
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v5, v4, 2, 0
v_cmpx_le_i32_e64 s1, v1
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB1_6
v_subrev_nc_u32_e32 v0, s1, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v0, v0
ds_load_b32 v4, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
.LBB1_6:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB1_3
ds_load_b32 v0, v5
s_branch .LBB1_3
.LBB1_8:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[4:5], null, s0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v0, v4, 2, 0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v[2:3], v0, off
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_sum2IiEvPT_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.Lfunc_end1:
.size _Z11prefix_sum2IiEvPT_i, .Lfunc_end1-_Z11prefix_sum2IiEvPT_i
.section .AMDGPU.csdata,"",@progbits
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.protected _Z5adderIiEvPT_S1_l
.globl _Z5adderIiEvPT_S1_l
.p2align 8
.type _Z5adderIiEvPT_S1_l,@function
_Z5adderIiEvPT_S1_l:
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB2_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_3
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s15, -1
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
global_load_b32 v2, v[0:1], off
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5adderIiEvPT_S1_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.Lfunc_end2:
.size _Z5adderIiEvPT_S1_l, .Lfunc_end2-_Z5adderIiEvPT_S1_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
- .offset: 176
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_sum2IiEvPT_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_sum2IiEvPT_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5adderIiEvPT_S1_l
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5adderIiEvPT_S1_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000273b9_00000000-6_hillisfinal.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_, @function
_ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_:
.LFB3702:
.cfi_startproc
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_, .-_ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
.section .text._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, @function
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
.LFB4011:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4011:
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .-_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.text
.type _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii, @function
_ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii:
.LFB3704:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11prefix_sum2IiEvPT_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii, .-_ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
.section .text._Z11prefix_sum2IiEvPT_i,"axG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.weak _Z11prefix_sum2IiEvPT_i
.type _Z11prefix_sum2IiEvPT_i, @function
_Z11prefix_sum2IiEvPT_i:
.LFB4013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4013:
.size _Z11prefix_sum2IiEvPT_i, .-_Z11prefix_sum2IiEvPT_i
.text
.type _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l, @function
_ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l:
.LFB3706:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5adderIiEvPT_S1_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l, .-_ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
.section .text._Z5adderIiEvPT_S1_l,"axG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.weak _Z5adderIiEvPT_S1_l
.type _Z5adderIiEvPT_S1_l, @function
_Z5adderIiEvPT_S1_l:
.LFB4014:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4014:
.size _Z5adderIiEvPT_S1_l, .-_Z5adderIiEvPT_S1_l
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5adderIiEvPT_S1_l"
.LC1:
.string "_Z11prefix_sum2IiEvPT_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3709:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5adderIiEvPT_S1_l(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_sum2IiEvPT_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z7offloadIiiEvPT_PT0_S3_lll.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/reikdas/GSoC-Proposal-2020/master/testgsoc/hillisfinal.cu"
.section .rodata._Z7offloadIiiEvPT_PT0_S3_lll.str1.1,"aMS",@progbits,1
.LC4:
.string "GPUassert: %s %s %d\n"
.section .text._Z7offloadIiiEvPT_PT0_S3_lll,"axG",@progbits,_Z7offloadIiiEvPT_PT0_S3_lll,comdat
.weak _Z7offloadIiiEvPT_PT0_S3_lll
.type _Z7offloadIiiEvPT_PT0_S3_lll, @function
_Z7offloadIiiEvPT_PT0_S3_lll:
.LFB4009:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $104, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -144(%rbp)
movq %rdx, %rdi
movq %rcx, -128(%rbp)
movq %r8, -136(%rbp)
movq %r9, %rbx
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpq $1024, %r9
jle .L30
testl $1023, %r9d
je .L31
leaq 1023(%r9), %rax
testq %r9, %r9
cmovns %r9, %rax
sarq $10, %rax
addl $1, %eax
movl %eax, -116(%rbp)
.L32:
movl -116(%rbp), %r12d
sall $10, %r12d
movslq %r12d, %r15
salq $2, %r15
movq %r15, %rax
movq %r15, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L33:
cmpq %rdx, %rsp
je .L34
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L33
.L31:
leaq 1023(%r9), %rax
testq %r9, %r9
cmovns %r9, %rax
sarq $10, %rax
movl %eax, -116(%rbp)
jmp .L32
.L34:
movq %rax, %rdx
andl $4095, %edx
je .L35
orq $0, -8(%rsp,%rdx)
.L35:
movq %rsp, %r13
movq %r15, %rax
movq %r15, %rcx
andq $-4096, %rcx
movq %rsp, %rdx
subq %rcx, %rdx
.L36:
cmpq %rdx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rax, %rdx
andl $4095, %edx
je .L38
orq $0, -8(%rsp,%rdx)
.L38:
movq %rsp, %r14
testl %r12d, %r12d
jg .L69
.L39:
leal 1(%r12), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq -112(%rbp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L73
leaq -96(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L74
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L75
leaq -88(%rbp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L76
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L77
movslq -116(%rbp), %rsi
salq $2, %rsi
leaq -104(%rbp), %rdi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L78
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -116(%rbp), %eax
movl %eax, -120(%rbp)
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $8192, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L49:
call cudaPeekAtLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L80
call cudaDeviceSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L81
movl -120(%rbp), %eax
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl -116(%rbp), %eax
addl %eax, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L52:
call cudaPeekAtLastError@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L83
call cudaDeviceSynchronize@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L84
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl -120(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L55:
call cudaPeekAtLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L86
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L87
leaq 4(,%rbx,4), %r12
movl $2, %ecx
movq %r12, %rdx
movq -112(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L88
subq $1, %rbx
movq -136(%rbp), %rax
addq %rbx, %rax
movl (%r14,%rax,4), %eax
movq -144(%rbp), %rcx
addl -8(%rcx,%r12), %eax
movq -128(%rbp), %rdi
addq %rdi, %rbx
subl 0(%r13,%rbx,4), %eax
movl %eax, -4(%rcx,%r12)
movq -112(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L89
movq -96(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L90
movq -88(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L91
movq -104(%rbp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L92
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L93
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L40:
.cfi_restore_state
movl $0, 0(%r13,%rax,4)
movl %ecx, %edx
.L41:
movl %edx, (%r14,%rax,4)
addq $1, %rax
cmpl %eax, %r12d
jle .L39
.L42:
cmpq %rax, %rbx
jle .L40
movl (%rsi,%rax,4), %edx
movl %edx, 0(%r13,%rax,4)
movl (%rdi,%rax,4), %edx
jmp .L41
.L73:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $107, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L74:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $108, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L75:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $109, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L76:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $110, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L77:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $111, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L78:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $112, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L79:
subq $8, %rsp
pushq -104(%rbp)
movl %r12d, %r9d
movq -136(%rbp), %r8
movq -128(%rbp), %rcx
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
movq -112(%rbp), %rdi
call _ZL51__device_stub__Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_PiPKiS1_lliS_
addq $16, %rsp
jmp .L49
.L80:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $114, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $115, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L82:
movl -116(%rbp), %esi
movq -104(%rbp), %rdi
call _ZL37__device_stub__Z11prefix_sum2IiEvPT_iPii
jmp .L52
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $117, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $118, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L85:
movslq %r12d, %rdx
movq -104(%rbp), %rsi
movq -112(%rbp), %rdi
call _ZL33__device_stub__Z5adderIiEvPT_S1_lPiS_l
jmp .L55
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $120, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $122, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $124, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $125, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $126, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $127, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L30:
leaq -4096(%rsp), %rax
.L63:
cmpq %rax, %rsp
je .L64
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L63
.L64:
movq %rsp, %r13
leaq -4096(%rsp), %rax
.L66:
cmpq %rax, %rsp
je .L67
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L66
.L67:
movq %rsp, %r14
movl $1024, %r12d
movl $1, -116(%rbp)
movl $4096, %r15d
.L69:
movl $0, %eax
movl $0, %ecx
jmp .L42
.L93:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4009:
.size _Z7offloadIiiEvPT_PT0_S3_lll, .-_Z7offloadIiiEvPT_PT0_S3_lll
.section .rodata.str1.1
.LC5:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3677:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -4796416(%rsp), %r11
.cfi_def_cfa 11, 4796456
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3608, %rsp
.cfi_def_cfa_offset 4800064
movq %fs:40, %rax
movq %rax, 4800008(%rsp)
xorl %eax, %eax
.L95:
movl %eax, (%rsp,%rax,4)
leal 10(%rax), %edx
movl %edx, 1600000(%rsp,%rax,4)
addq $1, %rax
cmpq $400000, %rax
jne .L95
leaq 1600000(%rsp), %rdx
movq %rsp, %rsi
leaq 3200000(%rsp), %rbx
movl $400000, %r9d
movl $0, %r8d
movl $0, %ecx
movq %rbx, %rdi
call _Z7offloadIiiEvPT_PT0_S3_lll
leaq 4800004(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L96:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L96
movq 4800008(%rsp), %rax
subq %fs:40, %rax
jne .L101
movl $0, %eax
addq $4800024, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hillisfinal.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4800016, %rsp # imm = 0x493E10
.cfi_def_cfa_offset 4800032
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, 1600000(%rsp,%rax,4)
leal 10(%rax), %ecx
movl %ecx, (%rsp,%rax,4)
incq %rax
cmpq $400000, %rax # imm = 0x61A80
jne .LBB0_1
# %bb.2:
xorl %ebx, %ebx
leaq 3200000(%rsp), %rdi
leaq 1600000(%rsp), %rsi
movq %rsp, %rdx
movl $400000, %r9d # imm = 0x61A80
xorl %ecx, %ecx
xorl %r8d, %r8d
callq _Z7offloadIiiEvPT_PT0_S3_lll
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl 3200000(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $400001, %rbx # imm = 0x61A81
jne .LBB0_3
# %bb.4:
xorl %eax, %eax
addq $4800016, %rsp # imm = 0x493E10
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z7offloadIiiEvPT_PT0_S3_lll,"axG",@progbits,_Z7offloadIiiEvPT_PT0_S3_lll,comdat
.weak _Z7offloadIiiEvPT_PT0_S3_lll # -- Begin function _Z7offloadIiiEvPT_PT0_S3_lll
.p2align 4, 0x90
.type _Z7offloadIiiEvPT_PT0_S3_lll,@function
_Z7offloadIiiEvPT_PT0_S3_lll: # @_Z7offloadIiiEvPT_PT0_S3_lll
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %r9, %rbx
movq %r8, -160(%rbp) # 8-byte Spill
movq %rcx, -168(%rbp) # 8-byte Spill
movl $1, %r9d
cmpq $1025, %rbx # imm = 0x401
jl .LBB1_2
# %bb.1:
movl %ebx, %eax
andl $1023, %eax # imm = 0x3FF
movq %rbx, %r9
shrq $10, %r9
cmpq $1, %rax
sbbl $-1, %r9d
.LBB1_2:
movl %r9d, %r12d
shll $10, %r12d
movq %rsp, %r13
leaq (,%r12,4), %rax
subq %rax, %r13
movq %r13, %rsp
movq %rsp, %r14
subq %rax, %r14
movq %r14, %rsp
testl %r9d, %r9d
jle .LBB1_6
# %bb.3: # %.lr.ph.preheader
cmpl $2, %r12d
movl $1, %eax
cmovgel %r12d, %eax
xorl %ecx, %ecx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_4 Depth=1
movl (%rsi,%rcx,4), %r8d
movl %r8d, (%r13,%rcx,4)
movl (%rdx,%rcx,4), %r8d
.LBB1_20: # in Loop: Header=BB1_4 Depth=1
movl %r8d, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
je .LBB1_6
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %rbx, %rcx
jl .LBB1_5
# %bb.19: # in Loop: Header=BB1_4 Depth=1
movl $0, (%r13,%rcx,4)
xorl %r8d, %r8d
jmp .LBB1_20
.LBB1_6: # %._crit_edge
movq %r9, -176(%rbp) # 8-byte Spill
movq %rdi, -256(%rbp) # 8-byte Spill
movl %r12d, %eax
orl $1, %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq -120(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit
movslq %r12d, %rax
movq %rax, -248(%rbp) # 8-byte Spill
leaq (,%rax,4), %r15
leaq -136(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit67
movq -136(%rbp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit69
leaq -128(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit71
movq -128(%rbp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit73
movq -176(%rbp), %r15 # 8-byte Reload
movslq %r15d, %rsi
shlq $2, %rsi
leaq -112(%rbp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_18
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit75
movabsq $4294968320, %rdx # imm = 0x100000400
movl %r15d, %eax
leaq (%rax,%rdx), %r15
addq $-1024, %r15 # imm = 0xFC00
movl $8192, %r8d # imm = 0x2000
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_23
# %bb.22:
movq -120(%rbp), %rax
movq -136(%rbp), %rcx
movq -128(%rbp), %rdx
movq -112(%rbp), %rsi
movq %rax, -104(%rbp)
movq %rcx, -96(%rbp)
movq %rdx, -88(%rbp)
movq -168(%rbp), %rax # 8-byte Reload
movq %rax, -48(%rbp)
movq -160(%rbp), %rax # 8-byte Reload
movq %rax, -144(%rbp)
movl %r12d, -148(%rbp)
movq %rsi, -280(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -96(%rbp), %rax
movq %rax, -232(%rbp)
leaq -88(%rbp), %rax
movq %rax, -224(%rbp)
leaq -48(%rbp), %rax
movq %rax, -216(%rbp)
leaq -144(%rbp), %rax
movq %rax, -208(%rbp)
leaq -148(%rbp), %rax
movq %rax, -200(%rbp)
leaq -280(%rbp), %rax
movq %rax, -192(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -272(%rbp), %rdx
leaq -264(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %edi
pushq -264(%rbp)
pushq -272(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_23:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_49
# %bb.24: # %_Z9gpuAssert10hipError_tPKcib.exit77
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.26: # %_Z9gpuAssert10hipError_tPKcib.exit79
movq -176(%rbp), %r12 # 8-byte Reload
leal (%r12,%r12), %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $4294968320, %rax # imm = 0x100000400
leaq -1023(%rax), %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_28
# %bb.27:
movq -112(%rbp), %rax
movq %rax, -104(%rbp)
movl %r12d, -48(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -48(%rbp), %rax
movq %rax, -232(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z11prefix_sum2IiEvPT_i, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_28:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_29
# %bb.30: # %_Z9gpuAssert10hipError_tPKcib.exit87
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_31
# %bb.32: # %_Z9gpuAssert10hipError_tPKcib.exit89
movq %r15, %rdi
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_34
# %bb.33:
movq -120(%rbp), %rax
movq -112(%rbp), %rcx
movq %rax, -104(%rbp)
movq %rcx, -96(%rbp)
movq -248(%rbp), %rax # 8-byte Reload
movq %rax, -88(%rbp)
leaq -104(%rbp), %rax
movq %rax, -240(%rbp)
leaq -96(%rbp), %rax
movq %rax, -232(%rbp)
leaq -88(%rbp), %rax
movq %rax, -224(%rbp)
leaq -80(%rbp), %rdi
leaq -64(%rbp), %rsi
leaq -48(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -80(%rbp), %rsi
movl -72(%rbp), %edx
movq -64(%rbp), %rcx
movl -56(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z5adderIiEvPT_S1_l, %edi
pushq -144(%rbp)
pushq -48(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_34:
callq hipPeekAtLastError
testl %eax, %eax
movq -256(%rbp), %r15 # 8-byte Reload
jne .LBB1_35
# %bb.36: # %_Z9gpuAssert10hipError_tPKcib.exit97
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_37
# %bb.38: # %_Z9gpuAssert10hipError_tPKcib.exit99
movq -120(%rbp), %rsi
leaq 4(,%rbx,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_39
# %bb.40: # %_Z9gpuAssert10hipError_tPKcib.exit101
leaq (%r14,%rbx,4), %rax
addq $-4, %rax
movq -160(%rbp), %rcx # 8-byte Reload
movl (%rax,%rcx,4), %eax
addl -4(%r15,%rbx,4), %eax
leaq -4(,%rbx,4), %rcx
addq %r13, %rcx
movq -168(%rbp), %rdx # 8-byte Reload
subl (%rcx,%rdx,4), %eax
movl %eax, (%r15,%rbx,4)
movq -120(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_41
# %bb.42: # %_Z9gpuAssert10hipError_tPKcib.exit103
movq -136(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_43
# %bb.44: # %_Z9gpuAssert10hipError_tPKcib.exit105
movq -128(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_45
# %bb.46: # %_Z9gpuAssert10hipError_tPKcib.exit107
movq -112(%rbp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_47
# %bb.48: # %_Z9gpuAssert10hipError_tPKcib.exit109
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_7:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $107, %r8d
jmp .LBB1_8
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $108, %r8d
jmp .LBB1_8
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $109, %r8d
jmp .LBB1_8
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $110, %r8d
jmp .LBB1_8
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB1_8
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $112, %r8d
jmp .LBB1_8
.LBB1_49:
movl %eax, %r12d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $114, %r8d
xorl %eax, %eax
callq fprintf
movl %r12d, %edi
callq exit
.LBB1_25:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB1_8
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $117, %r8d
jmp .LBB1_8
.LBB1_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $118, %r8d
jmp .LBB1_8
.LBB1_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $120, %r8d
jmp .LBB1_8
.LBB1_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $121, %r8d
jmp .LBB1_8
.LBB1_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $122, %r8d
jmp .LBB1_8
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB1_8
.LBB1_43:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB1_8
.LBB1_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB1_8
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %r14d
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $127, %r8d
.LBB1_8:
xorl %eax, %eax
callq fprintf
movl %r14d, %edi
callq exit
.Lfunc_end1:
.size _Z7offloadIiiEvPT_PT0_S3_lll, .Lfunc_end1-_Z7offloadIiiEvPT_PT0_S3_lll
.cfi_endproc
# -- End function
.section .text._Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"axG",@progbits,_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_ # -- Begin function _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 4, 0x90
.type _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@function
_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_: # @_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_, .Lfunc_end2-_Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.cfi_endproc
# -- End function
.section .text._Z26__device_stub__prefix_sum2IiEvPT_i,"axG",@progbits,_Z26__device_stub__prefix_sum2IiEvPT_i,comdat
.weak _Z26__device_stub__prefix_sum2IiEvPT_i # -- Begin function _Z26__device_stub__prefix_sum2IiEvPT_i
.p2align 4, 0x90
.type _Z26__device_stub__prefix_sum2IiEvPT_i,@function
_Z26__device_stub__prefix_sum2IiEvPT_i: # @_Z26__device_stub__prefix_sum2IiEvPT_i
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11prefix_sum2IiEvPT_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__prefix_sum2IiEvPT_i, .Lfunc_end3-_Z26__device_stub__prefix_sum2IiEvPT_i
.cfi_endproc
# -- End function
.section .text._Z20__device_stub__adderIiEvPT_S1_l,"axG",@progbits,_Z20__device_stub__adderIiEvPT_S1_l,comdat
.weak _Z20__device_stub__adderIiEvPT_S1_l # -- Begin function _Z20__device_stub__adderIiEvPT_S1_l
.p2align 4, 0x90
.type _Z20__device_stub__adderIiEvPT_S1_l,@function
_Z20__device_stub__adderIiEvPT_S1_l: # @_Z20__device_stub__adderIiEvPT_S1_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5adderIiEvPT_S1_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z20__device_stub__adderIiEvPT_S1_l, .Lfunc_end4-_Z20__device_stub__adderIiEvPT_S1_l
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_sum2IiEvPT_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5adderIiEvPT_S1_l, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/reikdas/GSoC-Proposal-2020/master/testgsoc/hillisfinal.hip"
.size .L.str.1, 116
.type _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,@object # @_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.section .rodata._Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,"aG",@progbits,_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_,comdat
.weak _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.p2align 3, 0x0
_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_:
.quad _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.size _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_, 8
.type _Z11prefix_sum2IiEvPT_i,@object # @_Z11prefix_sum2IiEvPT_i
.section .rodata._Z11prefix_sum2IiEvPT_i,"aG",@progbits,_Z11prefix_sum2IiEvPT_i,comdat
.weak _Z11prefix_sum2IiEvPT_i
.p2align 3, 0x0
_Z11prefix_sum2IiEvPT_i:
.quad _Z26__device_stub__prefix_sum2IiEvPT_i
.size _Z11prefix_sum2IiEvPT_i, 8
.type _Z5adderIiEvPT_S1_l,@object # @_Z5adderIiEvPT_S1_l
.section .rodata._Z5adderIiEvPT_S1_l,"aG",@progbits,_Z5adderIiEvPT_S1_l,comdat
.weak _Z5adderIiEvPT_S1_l
.p2align 3, 0x0
_Z5adderIiEvPT_S1_l:
.quad _Z20__device_stub__adderIiEvPT_S1_l
.size _Z5adderIiEvPT_S1_l, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11prefix_sum2IiEvPT_i"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z5adderIiEvPT_S1_l"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.addrsig_sym _Z26__device_stub__prefix_sum2IiEvPT_i
.addrsig_sym _Z20__device_stub__adderIiEvPT_S1_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z11prefix_sum1IiiEvPT_PKT0_S4_lliS1_
.addrsig_sym _Z11prefix_sum2IiEvPT_i
.addrsig_sym _Z5adderIiEvPT_S1_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <stdio.h>
int main() {
cudaDeviceProp deviceProperties;
cudaError_t status;
int deviceCount;
if((status = cudaGetDeviceCount(&deviceCount)) != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = cudaGetDeviceProperties(&deviceProperties, i);
if(status != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case cudaComputeModeDefault:
computeMode = "default";
break;
case cudaComputeModeExclusive:
computeMode = "exclusive";
break;
case cudaComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <stdio.h>
int main() {
cudaDeviceProp deviceProperties;
cudaError_t status;
int deviceCount;
if((status = cudaGetDeviceCount(&deviceCount)) != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = cudaGetDeviceProperties(&deviceProperties, i);
if(status != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case cudaComputeModeDefault:
computeMode = "default";
break;
case cudaComputeModeExclusive:
computeMode = "exclusive";
break;
case cudaComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} | .file "tmpxft_00165162_00000000-6_cudainfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "true"
.LC1:
.string "false"
.LC2:
.string "default"
.LC3:
.string "exclusive"
.LC4:
.string "prohibited"
.LC5:
.string "unknown"
.LC6:
.string "CUDA error: %s\n"
.LC7:
.string "---\n"
.LC8:
.string "- name: \"%s\"\n"
.LC9:
.string " compute_version: \"%d.%d\"\n"
.LC10:
.string " pci_address: \"%02d:%02d\"\n"
.LC11:
.string " total_global_memory: %zu\n"
.LC12:
.string " total_constant_memory: %zu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC13:
.string " shared_memory_per_block: %zu\n"
.section .rodata.str1.1
.LC14:
.string " max_malloc_pitch: %zu\n"
.LC15:
.string " texture_alignment: %zu\n"
.LC16:
.string " registers_per_block: %d\n"
.LC17:
.string " max_threads_per_block: %d\n"
.section .rodata.str1.8
.align 8
.LC18:
.string " max_thread_block_dimension: [%d, %d, %d]\n"
.align 8
.LC19:
.string " max_grid_size: [%d, %d, %d]\n"
.section .rodata.str1.1
.LC20:
.string " warp_size_threads: %d\n"
.LC21:
.string " multi_processor_count: %d\n"
.LC22:
.string " clock_rate_khz: %d\n"
.LC23:
.string " pci_bus_id: %d\n"
.LC24:
.string " pci_device_id: %d\n"
.LC25:
.string " compute_major: %d\n"
.LC26:
.string " compute_minor: %d\n"
.LC27:
.string " integrated: %s\n"
.section .rodata.str1.8
.align 8
.LC28:
.string " supports_device_overlap: %s\n"
.align 8
.LC29:
.string " kernel_execution_timeout_enabled: %s\n"
.section .rodata.str1.1
.LC30:
.string " can_map_host_memory: %s\n"
.section .rodata.str1.8
.align 8
.LC31:
.string " supports_concurrent_kernels: %s\n"
.section .rodata.str1.1
.LC32:
.string " ecc_enabled: %s\n"
.LC33:
.string " using_tcc_driver: %s\n"
.LC34:
.string " compute_mode: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L30
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r12
leaq .LC11(%rip), %rbp
jmp .L15
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L31
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L14:
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L32
.L15:
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 604(%rsp), %ecx
movl 600(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 600(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 604(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 592(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 596(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 612(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %eax
leaq .LC3(%rip), %rdx
cmpl $1, %eax
je .L14
leaq .LC4(%rip), %rdx
cmpl $2, %eax
je .L14
testl %eax, %eax
leaq .LC2(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
jmp .L14
.L32:
movl $0, %eax
jmp .L3
.L17:
movl $0, %eax
jmp .L3
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <stdio.h>
int main() {
cudaDeviceProp deviceProperties;
cudaError_t status;
int deviceCount;
if((status = cudaGetDeviceCount(&deviceCount)) != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = cudaGetDeviceProperties(&deviceProperties, i);
if(status != cudaSuccess) {
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case cudaComputeModeDefault:
computeMode = "default";
break;
case cudaComputeModeExclusive:
computeMode = "exclusive";
break;
case cudaComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
hipDeviceProp_t deviceProperties;
hipError_t status;
int deviceCount;
if((status = hipGetDeviceCount(&deviceCount)) != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = hipGetDeviceProperties(&deviceProperties, i);
if(status != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case hipComputeModeDefault:
computeMode = "default";
break;
case hipComputeModeExclusive:
computeMode = "exclusive";
break;
case hipComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
hipDeviceProp_t deviceProperties;
hipError_t status;
int deviceCount;
if((status = hipGetDeviceCount(&deviceCount)) != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = hipGetDeviceProperties(&deviceProperties, i);
if(status != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case hipComputeModeDefault:
computeMode = "default";
break;
case hipComputeModeExclusive:
computeMode = "exclusive";
break;
case hipComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /** Prints CUDA GPU information in a machine-readable user-friendly format.
*
* The output can be read with a YAML parser, and is an array with one element
* per CUDA GPU.
*
* Build with:
* nvcc -o cudainfo cudainfo.cu
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
hipDeviceProp_t deviceProperties;
hipError_t status;
int deviceCount;
if((status = hipGetDeviceCount(&deviceCount)) != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("---\n");
for (int i = 0; i < deviceCount; ++i) {
status = hipGetDeviceProperties(&deviceProperties, i);
if(status != hipSuccess) {
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(status));
return 1;
}
printf("- name: \"%s\"\n", deviceProperties.name);
printf(" compute_version: \"%d.%d\"\n",
deviceProperties.major, deviceProperties.minor);
printf(" pci_address: \"%02d:%02d\"\n",
deviceProperties.pciBusID, deviceProperties.pciDeviceID);
printf(" total_global_memory: %zu\n", deviceProperties.totalGlobalMem);
printf(" total_constant_memory: %zu\n", deviceProperties.totalConstMem);
printf(" shared_memory_per_block: %zu\n",
deviceProperties.sharedMemPerBlock);
printf(" max_malloc_pitch: %zu\n", deviceProperties.memPitch);
printf(" texture_alignment: %zu\n", deviceProperties.textureAlignment);
printf(" registers_per_block: %d\n", deviceProperties.regsPerBlock);
printf(" max_threads_per_block: %d\n",
deviceProperties.maxThreadsPerBlock);
printf(" max_thread_block_dimension: [%d, %d, %d]\n",
deviceProperties.maxThreadsDim[0], deviceProperties.maxThreadsDim[1],
deviceProperties.maxThreadsDim[2]);
printf(" max_grid_size: [%d, %d, %d]\n",
deviceProperties.maxGridSize[0], deviceProperties.maxGridSize[1],
deviceProperties.maxGridSize[2]);
printf(" warp_size_threads: %d\n", deviceProperties.warpSize);
printf(" multi_processor_count: %d\n",
deviceProperties.multiProcessorCount);
printf(" clock_rate_khz: %d\n", deviceProperties.clockRate);
printf(" pci_bus_id: %d\n", deviceProperties.pciBusID);
printf(" pci_device_id: %d\n", deviceProperties.pciDeviceID);
printf(" compute_major: %d\n", deviceProperties.major);
printf(" compute_minor: %d\n", deviceProperties.minor);
printf(" integrated: %s\n",
deviceProperties.integrated ? "true" : "false");
printf(" supports_device_overlap: %s\n",
deviceProperties.deviceOverlap ? "true" : "false");
printf(" kernel_execution_timeout_enabled: %s\n",
deviceProperties.kernelExecTimeoutEnabled ? "true" : "false");
printf(" can_map_host_memory: %s\n",
deviceProperties.canMapHostMemory ? "true" : "false");
printf(" supports_concurrent_kernels: %s\n",
deviceProperties.concurrentKernels ? "true" : "false");
printf(" ecc_enabled: %s\n",
deviceProperties.ECCEnabled ? "true" : "false");
printf(" using_tcc_driver: %s\n",
deviceProperties.tccDriver ? "true" : "false");
const char* computeMode;
switch (deviceProperties.computeMode) {
case hipComputeModeDefault:
computeMode = "default";
break;
case hipComputeModeExclusive:
computeMode = "exclusive";
break;
case hipComputeModeProhibited:
computeMode = "prohibited";
break;
default:
computeMode = "unknown";
}
printf(" compute_mode: %s\n", computeMode);
}
return 0;
} | .text
.file "cudainfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_8
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.3: # %.lr.ph
leaq 8(%rsp), %rbx
movl $.L.str.23, %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.34, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.5: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 592(%rsp), %esi
movl 596(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movl 592(%rsp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 596(%rsp), %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 372(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 404(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
cmpl $0, 584(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
cmpl $0, 588(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
cmpl $0, 604(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 412(%rsp), %eax
movl $.L.str.33, %esi
cmpq $2, %rax
ja .LBB0_7
# %bb.6: # %switch.lookup
# in Loop: Header=BB0_4 Depth=1
movq .Lswitch.table.main(,%rax,8), %rsi
jmp .LBB0_7
.LBB0_2:
xorl %r14d, %r14d
jmp .LBB0_9
.LBB0_8: # %.loopexit.sink.split
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.LBB0_9: # %.loopexit
movl %r14d, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "- name: \"%s\"\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " compute_version: \"%d.%d\"\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " pci_address: \"%02d:%02d\"\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " total_global_memory: %zu\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " total_constant_memory: %zu\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " shared_memory_per_block: %zu\n"
.size .L.str.7, 32
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " max_malloc_pitch: %zu\n"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " texture_alignment: %zu\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " registers_per_block: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " max_threads_per_block: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " max_thread_block_dimension: [%d, %d, %d]\n"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " max_grid_size: [%d, %d, %d]\n"
.size .L.str.13, 31
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " warp_size_threads: %d\n"
.size .L.str.14, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " multi_processor_count: %d\n"
.size .L.str.15, 29
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " clock_rate_khz: %d\n"
.size .L.str.16, 22
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " pci_bus_id: %d\n"
.size .L.str.17, 18
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " pci_device_id: %d\n"
.size .L.str.18, 21
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " compute_major: %d\n"
.size .L.str.19, 21
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " compute_minor: %d\n"
.size .L.str.20, 21
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " integrated: %s\n"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "true"
.size .L.str.22, 5
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "false"
.size .L.str.23, 6
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " supports_device_overlap: %s\n"
.size .L.str.24, 31
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " kernel_execution_timeout_enabled: %s\n"
.size .L.str.25, 40
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz " can_map_host_memory: %s\n"
.size .L.str.26, 27
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " supports_concurrent_kernels: %s\n"
.size .L.str.27, 35
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz " ecc_enabled: %s\n"
.size .L.str.28, 19
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz " using_tcc_driver: %s\n"
.size .L.str.29, 24
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "default"
.size .L.str.30, 8
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "exclusive"
.size .L.str.31, 10
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "prohibited"
.size .L.str.32, 11
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "unknown"
.size .L.str.33, 8
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz " compute_mode: %s\n"
.size .L.str.34, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "---"
.size .Lstr, 4
.type .Lswitch.table.main,@object # @switch.table.main
.section .rodata,"a",@progbits
.p2align 3, 0x0
.Lswitch.table.main:
.quad .L.str.30
.quad .L.str.31
.quad .L.str.32
.size .Lswitch.table.main, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00165162_00000000-6_cudainfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "true"
.LC1:
.string "false"
.LC2:
.string "default"
.LC3:
.string "exclusive"
.LC4:
.string "prohibited"
.LC5:
.string "unknown"
.LC6:
.string "CUDA error: %s\n"
.LC7:
.string "---\n"
.LC8:
.string "- name: \"%s\"\n"
.LC9:
.string " compute_version: \"%d.%d\"\n"
.LC10:
.string " pci_address: \"%02d:%02d\"\n"
.LC11:
.string " total_global_memory: %zu\n"
.LC12:
.string " total_constant_memory: %zu\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC13:
.string " shared_memory_per_block: %zu\n"
.section .rodata.str1.1
.LC14:
.string " max_malloc_pitch: %zu\n"
.LC15:
.string " texture_alignment: %zu\n"
.LC16:
.string " registers_per_block: %d\n"
.LC17:
.string " max_threads_per_block: %d\n"
.section .rodata.str1.8
.align 8
.LC18:
.string " max_thread_block_dimension: [%d, %d, %d]\n"
.align 8
.LC19:
.string " max_grid_size: [%d, %d, %d]\n"
.section .rodata.str1.1
.LC20:
.string " warp_size_threads: %d\n"
.LC21:
.string " multi_processor_count: %d\n"
.LC22:
.string " clock_rate_khz: %d\n"
.LC23:
.string " pci_bus_id: %d\n"
.LC24:
.string " pci_device_id: %d\n"
.LC25:
.string " compute_major: %d\n"
.LC26:
.string " compute_minor: %d\n"
.LC27:
.string " integrated: %s\n"
.section .rodata.str1.8
.align 8
.LC28:
.string " supports_device_overlap: %s\n"
.align 8
.LC29:
.string " kernel_execution_timeout_enabled: %s\n"
.section .rodata.str1.1
.LC30:
.string " can_map_host_memory: %s\n"
.section .rodata.str1.8
.align 8
.LC31:
.string " supports_concurrent_kernels: %s\n"
.section .rodata.str1.1
.LC32:
.string " ecc_enabled: %s\n"
.LC33:
.string " using_tcc_driver: %s\n"
.LC34:
.string " compute_mode: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L30
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r12
leaq .LC11(%rip), %rbp
jmp .L15
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L31
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L14:
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L32
.L15:
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 604(%rsp), %ecx
movl 600(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 600(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 604(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 592(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 596(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 612(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %eax
leaq .LC3(%rip), %rdx
cmpl $1, %eax
je .L14
leaq .LC4(%rip), %rdx
cmpl $2, %eax
je .L14
testl %eax, %eax
leaq .LC2(%rip), %rdx
leaq .LC5(%rip), %rax
cmovne %rax, %rdx
jmp .L14
.L32:
movl $0, %eax
jmp .L3
.L17:
movl $0, %eax
jmp .L3
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudainfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_8
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB0_2
# %bb.3: # %.lr.ph
leaq 8(%rsp), %rbx
movl $.L.str.23, %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.34, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.5: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 592(%rsp), %esi
movl 596(%rsp), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movl 592(%rsp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl 596(%rsp), %esi
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 372(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 404(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
cmpl $0, 584(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
cmpl $0, 588(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
cmpl $0, 604(%rsp)
movl $.L.str.22, %esi
cmoveq %r15, %rsi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 412(%rsp), %eax
movl $.L.str.33, %esi
cmpq $2, %rax
ja .LBB0_7
# %bb.6: # %switch.lookup
# in Loop: Header=BB0_4 Depth=1
movq .Lswitch.table.main(,%rax,8), %rsi
jmp .LBB0_7
.LBB0_2:
xorl %r14d, %r14d
jmp .LBB0_9
.LBB0_8: # %.loopexit.sink.split
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.LBB0_9: # %.loopexit
movl %r14d, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "- name: \"%s\"\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " compute_version: \"%d.%d\"\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " pci_address: \"%02d:%02d\"\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " total_global_memory: %zu\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " total_constant_memory: %zu\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " shared_memory_per_block: %zu\n"
.size .L.str.7, 32
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " max_malloc_pitch: %zu\n"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " texture_alignment: %zu\n"
.size .L.str.9, 26
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " registers_per_block: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " max_threads_per_block: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " max_thread_block_dimension: [%d, %d, %d]\n"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " max_grid_size: [%d, %d, %d]\n"
.size .L.str.13, 31
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " warp_size_threads: %d\n"
.size .L.str.14, 25
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " multi_processor_count: %d\n"
.size .L.str.15, 29
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " clock_rate_khz: %d\n"
.size .L.str.16, 22
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " pci_bus_id: %d\n"
.size .L.str.17, 18
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " pci_device_id: %d\n"
.size .L.str.18, 21
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " compute_major: %d\n"
.size .L.str.19, 21
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " compute_minor: %d\n"
.size .L.str.20, 21
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " integrated: %s\n"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "true"
.size .L.str.22, 5
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "false"
.size .L.str.23, 6
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " supports_device_overlap: %s\n"
.size .L.str.24, 31
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " kernel_execution_timeout_enabled: %s\n"
.size .L.str.25, 40
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz " can_map_host_memory: %s\n"
.size .L.str.26, 27
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " supports_concurrent_kernels: %s\n"
.size .L.str.27, 35
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz " ecc_enabled: %s\n"
.size .L.str.28, 19
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz " using_tcc_driver: %s\n"
.size .L.str.29, 24
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "default"
.size .L.str.30, 8
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "exclusive"
.size .L.str.31, 10
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "prohibited"
.size .L.str.32, 11
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "unknown"
.size .L.str.33, 8
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz " compute_mode: %s\n"
.size .L.str.34, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "---"
.size .Lstr, 4
.type .Lswitch.table.main,@object # @switch.table.main
.section .rodata,"a",@progbits
.p2align 3, 0x0
.Lswitch.table.main:
.quad .L.str.30
.quad .L.str.31
.quad .L.str.32
.size .Lswitch.table.main, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} | code for sm_80
Function : _Z8Return64PyS_PKy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fcc0000000f00 */
/*0040*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fc600000001ff */
/*0060*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e2e0000002100 */
/*0070*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0007 */
/*0080*/ ATOMG.E.ADD.64.STRONG.GPU PT, R2, [R2.64], R4 ; /* 0x00000004020279a8 */
/* 0x004ea200081ee5c4 */
/*0090*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0007 */
/*00a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x004fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} | .file "tmpxft_0009e2b8_00000000-6_Return64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
.type _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy, @function
_Z32__device_stub__Z8Return64PyS_PKyPyS_PKy:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8Return64PyS_PKy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy, .-_Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
.globl _Z8Return64PyS_PKy
.type _Z8Return64PyS_PKy, @function
_Z8Return64PyS_PKy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8Return64PyS_PKy, .-_Z8Return64PyS_PKy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8Return64PyS_PKy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8Return64PyS_PKy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8Return64PyS_PKy
.globl _Z8Return64PyS_PKy
.p2align 8
.type _Z8Return64PyS_PKy,@function
_Z8Return64PyS_PKy:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8Return64PyS_PKy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8Return64PyS_PKy, .Lfunc_end0-_Z8Return64PyS_PKy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8Return64PyS_PKy
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8Return64PyS_PKy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Return64( unsigned long long *sum, unsigned long long *out, const unsigned long long *pIn )
{
out[threadIdx.x] = atomicAdd( &sum[threadIdx.x], *pIn );
} | .text
.file "Return64.hip"
.globl _Z23__device_stub__Return64PyS_PKy # -- Begin function _Z23__device_stub__Return64PyS_PKy
.p2align 4, 0x90
.type _Z23__device_stub__Return64PyS_PKy,@function
_Z23__device_stub__Return64PyS_PKy: # @_Z23__device_stub__Return64PyS_PKy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8Return64PyS_PKy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__Return64PyS_PKy, .Lfunc_end0-_Z23__device_stub__Return64PyS_PKy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8Return64PyS_PKy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8Return64PyS_PKy,@object # @_Z8Return64PyS_PKy
.section .rodata,"a",@progbits
.globl _Z8Return64PyS_PKy
.p2align 3, 0x0
_Z8Return64PyS_PKy:
.quad _Z23__device_stub__Return64PyS_PKy
.size _Z8Return64PyS_PKy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8Return64PyS_PKy"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__Return64PyS_PKy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8Return64PyS_PKy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8Return64PyS_PKy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fcc0000000f00 */
/*0040*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fc600000001ff */
/*0060*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e2e0000002100 */
/*0070*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fcc00078e0007 */
/*0080*/ ATOMG.E.ADD.64.STRONG.GPU PT, R2, [R2.64], R4 ; /* 0x00000004020279a8 */
/* 0x004ea200081ee5c4 */
/*0090*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0007 */
/*00a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x004fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8Return64PyS_PKy
.globl _Z8Return64PyS_PKy
.p2align 8
.type _Z8Return64PyS_PKy,@function
_Z8Return64PyS_PKy:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
global_atomic_add_u64 v[0:1], v2, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8Return64PyS_PKy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8Return64PyS_PKy, .Lfunc_end0-_Z8Return64PyS_PKy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8Return64PyS_PKy
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z8Return64PyS_PKy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009e2b8_00000000-6_Return64.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
.type _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy, @function
_Z32__device_stub__Z8Return64PyS_PKyPyS_PKy:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8Return64PyS_PKy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy, .-_Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
.globl _Z8Return64PyS_PKy
.type _Z8Return64PyS_PKy, @function
_Z8Return64PyS_PKy:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8Return64PyS_PKyPyS_PKy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8Return64PyS_PKy, .-_Z8Return64PyS_PKy
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8Return64PyS_PKy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8Return64PyS_PKy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Return64.hip"
.globl _Z23__device_stub__Return64PyS_PKy # -- Begin function _Z23__device_stub__Return64PyS_PKy
.p2align 4, 0x90
.type _Z23__device_stub__Return64PyS_PKy,@function
_Z23__device_stub__Return64PyS_PKy: # @_Z23__device_stub__Return64PyS_PKy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8Return64PyS_PKy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__Return64PyS_PKy, .Lfunc_end0-_Z23__device_stub__Return64PyS_PKy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8Return64PyS_PKy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8Return64PyS_PKy,@object # @_Z8Return64PyS_PKy
.section .rodata,"a",@progbits
.globl _Z8Return64PyS_PKy
.p2align 3, 0x0
_Z8Return64PyS_PKy:
.quad _Z23__device_stub__Return64PyS_PKy
.size _Z8Return64PyS_PKy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8Return64PyS_PKy"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__Return64PyS_PKy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8Return64PyS_PKy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/replace.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <iostream>
#include <cstdlib>
// #include "random.h"
#define MBIG 1000000000
#define MSEED 161803398
#define MZ 0
#define FAC (1.0/MBIG)
__host__ __device__ float ran3(int idum)
//int *idum;
{
static int inext,inextp;
static long ma[56];
static int iff=0;
long mj,mk;
int i,ii,k;
if (idum < 0 || iff == 0) {
iff=1;
mj=MSEED-(idum < 0 ? -idum : idum);
mj %= MBIG;
ma[55]=mj;
mk=1;
for (i=1;i<=54;i++) {
ii=(21*i) % 55;
ma[ii]=mk;
mk=mj-mk;
if (mk < MZ) mk += MBIG;
mj=ma[ii];
}
for (k=1;k<=4;k++)
for (i=1;i<=55;i++) {
ma[i] -= ma[1+(i+30) % 55];
if (ma[i] < MZ) ma[i] += MBIG;
}
inext=0;
inextp=31;
idum=1;
}
if (++inext == 56) inext=1;
if (++inextp == 56) inextp=1;
mj=ma[inext]-ma[inextp];
if (mj < MZ) mj += MBIG;
ma[inext]=mj;
return mj*FAC;
}
#undef MBIG
#undef MSEED
#undef MZ
#undef FAC
struct rand_vec4_bigaussian
{
__host__ __device__
float4 operator()(float4 a)
{
float ampx, ampy, amp, r1, r2, facc;
float x,px, y, py;
float betax;
float emix;
float betay;
float emiy;
uint seed;
betax = 10.0;
betay = 20.0;
emix = 1e-9;
emiy = 2e-9;
seed=12489;
// 1 sigma rms beam sizes using average ring betas
ampx = sqrt(betax*emix);
ampy = sqrt(betay*emiy);
do
{
r1 = 2*ran3(seed)-1;
r2 = 2*ran3(seed)-1;
amp = r1*r1+r2*r2;
}
while ((amp >=1) || (amp<=3.e-6));
facc = sqrt(-2*log(amp)/amp); // transforming [-1,1] uniform to gaussian - inverse transform
x = ampx * r1 * facc; // scaling the gaussian
px = ampx * r2 * facc; // scaling the gaussian
// generate bi-gaussian distribution in the y-py phase-space
do
{
r1 = 2*ran3(seed)-1;
r2 = 2*ran3(seed)-1;
amp = r1*r1+r2*r2;
}
while ((amp >=1) || (amp<=3.e-6));
facc = sqrt(-2*log(amp)/amp); // transforming [-1,1] uniform to gaussian - inverse transform
y = ampy* r1 * facc; // scaling the gaussian
py = ampy* r2 * facc; // scaling the gaussian
a = make_float4(x,px,y,py);
return a;
};
};
__host__ std::ostream& operator<< (std::ostream& os, const float4& p)
{
os << "["<< p.x << "," << p.y << "," << p.z <<"," << p.w <<"]";
return os;
}
int main(int argc, char const *argv[])
{
thrust::device_vector<float> Y(10);
thrust::fill(Y.begin(),Y.end(),ran3(12489));
rand_vec4_bigaussian func;
thrust::device_vector<float4> v(1000000);
thrust::transform(v.begin(),v.end(),v.begin(),func);
thrust::copy(Y.begin(),Y.end(),std::ostream_iterator<float>(std::cout,"\n"));
// std::copy(v.begin(), v.end(), std::ostream_iterator<float4>(std::cout, " $ ") );
// thrust::copy(v.begin(),v.end(),std::ostream_iterator<float>(std::cout,"\n"));
std::cout << ran3(12489);
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/replace.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <iostream>
#include <cstdlib>
// #include "random.h"
#define MBIG 1000000000
#define MSEED 161803398
#define MZ 0
#define FAC (1.0/MBIG)
__host__ __device__ float ran3(int idum)
//int *idum;
{
static int inext,inextp;
static long ma[56];
static int iff=0;
long mj,mk;
int i,ii,k;
if (idum < 0 || iff == 0) {
iff=1;
mj=MSEED-(idum < 0 ? -idum : idum);
mj %= MBIG;
ma[55]=mj;
mk=1;
for (i=1;i<=54;i++) {
ii=(21*i) % 55;
ma[ii]=mk;
mk=mj-mk;
if (mk < MZ) mk += MBIG;
mj=ma[ii];
}
for (k=1;k<=4;k++)
for (i=1;i<=55;i++) {
ma[i] -= ma[1+(i+30) % 55];
if (ma[i] < MZ) ma[i] += MBIG;
}
inext=0;
inextp=31;
idum=1;
}
if (++inext == 56) inext=1;
if (++inextp == 56) inextp=1;
mj=ma[inext]-ma[inextp];
if (mj < MZ) mj += MBIG;
ma[inext]=mj;
return mj*FAC;
}
#undef MBIG
#undef MSEED
#undef MZ
#undef FAC
struct rand_vec4_bigaussian
{
__host__ __device__
float4 operator()(float4 a)
{
float ampx, ampy, amp, r1, r2, facc;
float x,px, y, py;
float betax;
float emix;
float betay;
float emiy;
uint seed;
betax = 10.0;
betay = 20.0;
emix = 1e-9;
emiy = 2e-9;
seed=12489;
// 1 sigma rms beam sizes using average ring betas
ampx = sqrt(betax*emix);
ampy = sqrt(betay*emiy);
do
{
r1 = 2*ran3(seed)-1;
r2 = 2*ran3(seed)-1;
amp = r1*r1+r2*r2;
}
while ((amp >=1) || (amp<=3.e-6));
facc = sqrt(-2*log(amp)/amp); // transforming [-1,1] uniform to gaussian - inverse transform
x = ampx * r1 * facc; // scaling the gaussian
px = ampx * r2 * facc; // scaling the gaussian
// generate bi-gaussian distribution in the y-py phase-space
do
{
r1 = 2*ran3(seed)-1;
r2 = 2*ran3(seed)-1;
amp = r1*r1+r2*r2;
}
while ((amp >=1) || (amp<=3.e-6));
facc = sqrt(-2*log(amp)/amp); // transforming [-1,1] uniform to gaussian - inverse transform
y = ampy* r1 * facc; // scaling the gaussian
py = ampy* r2 * facc; // scaling the gaussian
a = make_float4(x,px,y,py);
return a;
};
};
__host__ std::ostream& operator<< (std::ostream& os, const float4& p)
{
os << "["<< p.x << "," << p.y << "," << p.z <<"," << p.w <<"]";
return os;
}
int main(int argc, char const *argv[])
{
thrust::device_vector<float> Y(10);
thrust::fill(Y.begin(),Y.end(),ran3(12489));
rand_vec4_bigaussian func;
thrust::device_vector<float4> v(1000000);
thrust::transform(v.begin(),v.end(),v.begin(),func);
thrust::copy(Y.begin(),Y.end(),std::ostream_iterator<float>(std::cout,"\n"));
// std::copy(v.begin(), v.end(), std::ostream_iterator<float4>(std::cout, " $ ") );
// thrust::copy(v.begin(),v.end(),std::ostream_iterator<float>(std::cout,"\n"));
std::cout << ran3(12489);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, sz_in_bytes);
cudaMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
// freeing on device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} | code for sm_80
Function : _Z6kernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, sz_in_bytes);
cudaMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
// freeing on device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .file "tmpxft_0015471e_00000000-6_Ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.globl _Z6kernelPdS_S_i
.type _Z6kernelPdS_S_i, @function
_Z6kernelPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_S_i, .-_Z6kernelPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
movl $8000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm2
addsd %xmm1, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
movsd %xmm3, 0(%rbp,%rax,8)
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
cudaMalloc((void**)&d_a, sz_in_bytes);
cudaMalloc((void**)&d_b, sz_in_bytes);
cudaMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
cudaMemcpy(d_a, h_a, sz_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sz_in_bytes, cudaMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
cudaMemcpy(h_c, d_c, sz_in_bytes, cudaMemcpyDeviceToHost);
// freeing on device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, sz_in_bytes);
hipMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
// freeing on device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} |
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