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You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <stdlib.h> #include <math.h> #define TILE_WIDTH 16 __global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns) { int i = TILE_WIDTH * blockIdx.y + threadIdx.y; int j = TILE_WIDTH * blockIdx.x + threadIdx.x; if (i < rows && j < columns) c[i * columns + j] = a[i * columns + j] + b[i * columns + j]; } int m_add(int *a, int *b, int *c, int rows, int columns) { int *da, *db, *dc, size = rows * columns * sizeof(int); cudaMalloc((void **)&da, size); cudaMalloc((void **)&db, size); cudaMalloc((void **)&dc, size); cudaMemcpy(da, a, size, cudaMemcpyHostToDevice); cudaMemcpy(db, b, size, cudaMemcpyHostToDevice); dim3 dimGrid(ceil((float)columns / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1); dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1); _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns); cudaMemcpy(c, dc, size, cudaMemcpyDeviceToHost); cudaFree(da); cudaFree(db); cudaFree(dc); return 0; } int main() { int *A, *B, *C; int i, j; //Input int linhas, colunas; scanf("%d", &linhas); scanf("%d", &colunas); //Alocando memória na CPU A = (int *)malloc(sizeof(int)*linhas*colunas); B = (int *)malloc(sizeof(int)*linhas*colunas); C = (int *)malloc(sizeof(int)*linhas*colunas); //Inicializar for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ A[i*colunas+j] = B[i*colunas+j] = i+j; } } m_add(A, B, C, linhas, colunas); long long int somador=0; //Manter esta computação na CPU for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ somador+=C[i*colunas+j]; } } printf("%lli\n", somador); free(A); free(B); free(C); }
.file "tmpxft_0018770d_00000000-6_parallel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii .type _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, @function _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z10_gpu_m_addPiS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii .globl _Z10_gpu_m_addPiS_S_ii .type _Z10_gpu_m_addPiS_S_ii, @function _Z10_gpu_m_addPiS_S_ii: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z10_gpu_m_addPiS_S_ii, .-_Z10_gpu_m_addPiS_S_ii .globl _Z5m_addPiS_S_ii .type _Z5m_addPiS_S_ii, @function _Z5m_addPiS_S_ii: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %rdi, %r15 movq %rsi, %r14 movq %rdx, %r13 movl %ecx, %ebp movl %r8d, %r12d movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl %ecx, %ebx imull %r8d, %ebx sall $2, %ebx movslq %ebx, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT pxor %xmm0, %xmm0 cvtsi2ssl %ebp, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm1 movss .LC4(%rip), %xmm3 movaps %xmm0, %xmm2 andps %xmm3, %xmm2 movss .LC1(%rip), %xmm4 ucomiss %xmm2, %xmm4 jbe .L12 cvttss2sil %xmm0, %eax pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 cmpnless %xmm2, %xmm1 movss .LC3(%rip), %xmm4 andps %xmm4, %xmm1 addss %xmm2, %xmm1 andnps %xmm0, %xmm3 orps %xmm3, %xmm1 .L12: pxor %xmm0, %xmm0 cvtsi2ssl %r12d, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm4 movss .LC4(%rip), %xmm3 movaps %xmm0, %xmm2 andps %xmm3, %xmm2 movss .LC1(%rip), %xmm5 ucomiss %xmm2, %xmm5 jbe .L13 cvttss2sil %xmm0, %eax pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 cmpnless %xmm2, %xmm4 movss .LC3(%rip), %xmm5 andps %xmm5, %xmm4 addss %xmm2, %xmm4 andnps %xmm0, %xmm3 orps %xmm3, %xmm4 .L13: cvttss2siq %xmm4, %rax movl %eax, 32(%rsp) cvttss2siq %xmm1, %rax movl %eax, 36(%rsp) movl $16, 44(%rsp) movl $16, 48(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L14: movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movl %r12d, %r8d movl %ebp, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii jmp .L14 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5m_addPiS_S_ii, .-_Z5m_addPiS_S_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "%d" .LC6: .string "%lli\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $16, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movq %rsp, %rsi leaq .LC5(%rip), %rbx movq %rbx, %rdi call __isoc23_scanf@PLT leaq 4(%rsp), %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_scanf@PLT movl (%rsp), %r14d movl 4(%rsp), %r12d movslq %r14d, %r13 movslq %r12d, %rax imulq %rax, %r13 salq $2, %r13 movq %r13, %rdi call malloc@PLT movq %rax, %rbp movq %r13, %rdi call malloc@PLT movq %rax, %rbx movq %r13, %rdi call malloc@PLT movq %rax, %r13 testl %r14d, %r14d jle .L20 movl %r12d, %ecx movl $0, %edi movl $0, %esi jmp .L21 .L22: movl %eax, (%rbx,%rdx) movl %eax, 0(%rbp,%rdx) addl $1, %eax addq $4, %rdx cmpl %ecx, %eax jne .L22 .L24: addl $1, %esi addl %r12d, %edi addl $1, %ecx cmpl %esi, %r14d je .L20 .L21: movl %esi, %eax movslq %edi, %rdx salq $2, %rdx testl %r12d, %r12d jg .L22 jmp .L24 .L20: movl %r12d, %r8d movl %r14d, %ecx movq %r13, %rdx movq %rbx, %rsi movq %rbp, %rdi call _Z5m_addPiS_S_ii movl (%rsp), %r10d testl %r10d, %r10d jle .L31 movl 4(%rsp), %r9d movl $0, %r8d movl $0, %edx movl $0, %edi movslq %r9d, %r11 jmp .L26 .L28: movslq %r8d, %rcx leaq 0(%r13,%rcx,4), %rax addq %r11, %rcx leaq 0(%r13,%rcx,4), %rsi .L27: movslq (%rax), %rcx addq %rcx, %rdx addq $4, %rax cmpq %rsi, %rax jne .L27 .L29: addl $1, %edi addl %r9d, %r8d cmpl %r10d, %edi je .L25 .L26: testl %r9d, %r9d jg .L28 jmp .L29 .L31: movl $0, %edx .L25: leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 8(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z10_gpu_m_addPiS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z10_gpu_m_addPiS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1031798784 .align 4 .LC1: .long 1258291200 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <stdlib.h> #include <math.h> #define TILE_WIDTH 16 __global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns) { int i = TILE_WIDTH * blockIdx.y + threadIdx.y; int j = TILE_WIDTH * blockIdx.x + threadIdx.x; if (i < rows && j < columns) c[i * columns + j] = a[i * columns + j] + b[i * columns + j]; } int m_add(int *a, int *b, int *c, int rows, int columns) { int *da, *db, *dc, size = rows * columns * sizeof(int); cudaMalloc((void **)&da, size); cudaMalloc((void **)&db, size); cudaMalloc((void **)&dc, size); cudaMemcpy(da, a, size, cudaMemcpyHostToDevice); cudaMemcpy(db, b, size, cudaMemcpyHostToDevice); dim3 dimGrid(ceil((float)columns / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1); dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1); _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns); cudaMemcpy(c, dc, size, cudaMemcpyDeviceToHost); cudaFree(da); cudaFree(db); cudaFree(dc); return 0; } int main() { int *A, *B, *C; int i, j; //Input int linhas, colunas; scanf("%d", &linhas); scanf("%d", &colunas); //Alocando memória na CPU A = (int *)malloc(sizeof(int)*linhas*colunas); B = (int *)malloc(sizeof(int)*linhas*colunas); C = (int *)malloc(sizeof(int)*linhas*colunas); //Inicializar for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ A[i*colunas+j] = B[i*colunas+j] = i+j; } } m_add(A, B, C, linhas, colunas); long long int somador=0; //Manter esta computação na CPU for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ somador+=C[i*colunas+j]; } } printf("%lli\n", somador); free(A); free(B); free(C); }
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> #define TILE_WIDTH 16 __global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns) { int i = TILE_WIDTH * blockIdx.y + threadIdx.y; int j = TILE_WIDTH * blockIdx.x + threadIdx.x; if (i < rows && j < columns) c[i * columns + j] = a[i * columns + j] + b[i * columns + j]; } int m_add(int *a, int *b, int *c, int rows, int columns) { int *da, *db, *dc, size = rows * columns * sizeof(int); hipMalloc((void **)&da, size); hipMalloc((void **)&db, size); hipMalloc((void **)&dc, size); hipMemcpy(da, a, size, hipMemcpyHostToDevice); hipMemcpy(db, b, size, hipMemcpyHostToDevice); dim3 dimGrid(ceil((float)columns / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1); dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1); _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns); hipMemcpy(c, dc, size, hipMemcpyDeviceToHost); hipFree(da); hipFree(db); hipFree(dc); return 0; } int main() { int *A, *B, *C; int i, j; //Input int linhas, colunas; scanf("%d", &linhas); scanf("%d", &colunas); //Alocando memória na CPU A = (int *)malloc(sizeof(int)*linhas*colunas); B = (int *)malloc(sizeof(int)*linhas*colunas); C = (int *)malloc(sizeof(int)*linhas*colunas); //Inicializar for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ A[i*colunas+j] = B[i*colunas+j] = i+j; } } m_add(A, B, C, linhas, colunas); long long int somador=0; //Manter esta computação na CPU for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ somador+=C[i*colunas+j]; } } printf("%lli\n", somador); free(A); free(B); free(C); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> #define TILE_WIDTH 16 __global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns) { int i = TILE_WIDTH * blockIdx.y + threadIdx.y; int j = TILE_WIDTH * blockIdx.x + threadIdx.x; if (i < rows && j < columns) c[i * columns + j] = a[i * columns + j] + b[i * columns + j]; } int m_add(int *a, int *b, int *c, int rows, int columns) { int *da, *db, *dc, size = rows * columns * sizeof(int); hipMalloc((void **)&da, size); hipMalloc((void **)&db, size); hipMalloc((void **)&dc, size); hipMemcpy(da, a, size, hipMemcpyHostToDevice); hipMemcpy(db, b, size, hipMemcpyHostToDevice); dim3 dimGrid(ceil((float)columns / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1); dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1); _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns); hipMemcpy(c, dc, size, hipMemcpyDeviceToHost); hipFree(da); hipFree(db); hipFree(dc); return 0; } int main() { int *A, *B, *C; int i, j; //Input int linhas, colunas; scanf("%d", &linhas); scanf("%d", &colunas); //Alocando memória na CPU A = (int *)malloc(sizeof(int)*linhas*colunas); B = (int *)malloc(sizeof(int)*linhas*colunas); C = (int *)malloc(sizeof(int)*linhas*colunas); //Inicializar for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ A[i*colunas+j] = B[i*colunas+j] = i+j; } } m_add(A, B, C, linhas, colunas); long long int somador=0; //Manter esta computação na CPU for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ somador+=C[i*colunas+j]; } } printf("%lli\n", somador); free(A); free(B); free(C); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10_gpu_m_addPiS_S_ii .globl _Z10_gpu_m_addPiS_S_ii .p2align 8 .type _Z10_gpu_m_addPiS_S_ii,@function _Z10_gpu_m_addPiS_S_ii: s_load_b64 s[2:3], s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v1, s15, 4, v1 v_lshl_add_u32 v0, s14, 4, v0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s2, v1 v_cmp_gt_i32_e64 s2, s3, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s4, s2 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1] s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10_gpu_m_addPiS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10_gpu_m_addPiS_S_ii, .Lfunc_end0-_Z10_gpu_m_addPiS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10_gpu_m_addPiS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10_gpu_m_addPiS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> #define TILE_WIDTH 16 __global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns) { int i = TILE_WIDTH * blockIdx.y + threadIdx.y; int j = TILE_WIDTH * blockIdx.x + threadIdx.x; if (i < rows && j < columns) c[i * columns + j] = a[i * columns + j] + b[i * columns + j]; } int m_add(int *a, int *b, int *c, int rows, int columns) { int *da, *db, *dc, size = rows * columns * sizeof(int); hipMalloc((void **)&da, size); hipMalloc((void **)&db, size); hipMalloc((void **)&dc, size); hipMemcpy(da, a, size, hipMemcpyHostToDevice); hipMemcpy(db, b, size, hipMemcpyHostToDevice); dim3 dimGrid(ceil((float)columns / TILE_WIDTH), ceil((float)rows / TILE_WIDTH), 1); dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1); _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns); hipMemcpy(c, dc, size, hipMemcpyDeviceToHost); hipFree(da); hipFree(db); hipFree(dc); return 0; } int main() { int *A, *B, *C; int i, j; //Input int linhas, colunas; scanf("%d", &linhas); scanf("%d", &colunas); //Alocando memória na CPU A = (int *)malloc(sizeof(int)*linhas*colunas); B = (int *)malloc(sizeof(int)*linhas*colunas); C = (int *)malloc(sizeof(int)*linhas*colunas); //Inicializar for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ A[i*colunas+j] = B[i*colunas+j] = i+j; } } m_add(A, B, C, linhas, colunas); long long int somador=0; //Manter esta computação na CPU for(i = 0; i < linhas; i++){ for(j = 0; j < colunas; j++){ somador+=C[i*colunas+j]; } } printf("%lli\n", somador); free(A); free(B); free(C); }
.text .file "parallel.hip" .globl _Z25__device_stub___gpu_m_addPiS_S_ii # -- Begin function _Z25__device_stub___gpu_m_addPiS_S_ii .p2align 4, 0x90 .type _Z25__device_stub___gpu_m_addPiS_S_ii,@function _Z25__device_stub___gpu_m_addPiS_S_ii: # @_Z25__device_stub___gpu_m_addPiS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z10_gpu_m_addPiS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z25__device_stub___gpu_m_addPiS_S_ii, .Lfunc_end0-_Z25__device_stub___gpu_m_addPiS_S_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z5m_addPiS_S_ii .LCPI1_0: .long 0x3d800000 # float 0.0625 .text .globl _Z5m_addPiS_S_ii .p2align 4, 0x90 .type _Z5m_addPiS_S_ii,@function _Z5m_addPiS_S_ii: # @_Z5m_addPiS_S_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r8d, %ebp movl %ecx, %r15d movq %rdx, %rbx movq %rsi, %r12 movq %rdi, %r13 movl %ecx, %eax imull %r8d, %eax shll $2, %eax movslq %eax, %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 24(%rsp), %rdi movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy cvtsi2ss %ebp, %xmm0 mulss .LCPI1_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %r12 xorps %xmm0, %xmm0 cvtsi2ss %r15d, %xmm0 mulss .LCPI1_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %rdi movl %r12d, %eax shlq $32, %rdi orq %rax, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl %r15d, 36(%rsp) movl %ebp, 32(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 32(%rsp), %rax movq %rax, 144(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10_gpu_m_addPiS_S_ii, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5m_addPiS_S_ii, .Lfunc_end1-_Z5m_addPiS_S_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 xorl %r12d, %r12d leaq 4(%rsp), %rsi movl $.L.str, %edi xorl %eax, %eax callq __isoc23_scanf movq %rsp, %rsi movl $.L.str, %edi xorl %eax, %eax callq __isoc23_scanf movslq 4(%rsp), %r13 movslq (%rsp), %rbp movq %r13, %r15 imulq %rbp, %r15 shlq $2, %r15 movq %r15, %rdi callq malloc movq %rax, %rbx movq %r15, %rdi callq malloc movq %rax, %r14 movq %r15, %rdi callq malloc movq %rax, %r15 movl %r13d, %ecx movl %ebp, %r8d testq %r13, %r13 jle .LBB2_6 # %bb.1: # %.preheader34.lr.ph xorl %eax, %eax jmp .LBB2_2 .p2align 4, 0x90 .LBB2_5: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 incq %rax addl %r8d, %r12d cmpq %rcx, %rax je .LBB2_6 .LBB2_2: # %.preheader34 # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 testl %r8d, %r8d jle .LBB2_5 # %bb.3: # %.lr.ph # in Loop: Header=BB2_2 Depth=1 movl %r12d, %esi leaq (%rbx,%rsi,4), %rdx leaq (%r14,%rsi,4), %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB2_4: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 leal (%rax,%rdi), %r9d movl %r9d, (%rsi,%rdi,4) movl %r9d, (%rdx,%rdi,4) incq %rdi cmpq %rdi, %r8 jne .LBB2_4 jmp .LBB2_5 .LBB2_6: # %._crit_edge37 movq %rbx, %rdi movq %r14, %rsi movq %r15, %rdx # kill: def $ecx killed $ecx killed $rcx # kill: def $r8d killed $r8d killed $r8 callq _Z5m_addPiS_S_ii movl 4(%rsp), %eax xorl %ecx, %ecx testl %eax, %eax jle .LBB2_7 # %bb.8: # %.preheader.lr.ph movl (%rsp), %edx xorl %edi, %edi xorl %esi, %esi jmp .LBB2_9 .p2align 4, 0x90 .LBB2_12: # %._crit_edge41 # in Loop: Header=BB2_9 Depth=1 incq %rdi addl %edx, %ecx cmpq %rax, %rdi je .LBB2_13 .LBB2_9: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_11 Depth 2 testl %edx, %edx jle .LBB2_12 # %bb.10: # %.lr.ph40 # in Loop: Header=BB2_9 Depth=1 movl %ecx, %r8d leaq (%r15,%r8,4), %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB2_11: # Parent Loop BB2_9 Depth=1 # => This Inner Loop Header: Depth=2 movslq (%r8,%r9,4), %r10 addq %r10, %rsi incq %r9 cmpq %r9, %rdx jne .LBB2_11 jmp .LBB2_12 .LBB2_7: xorl %esi, %esi .LBB2_13: # %._crit_edge44 movl $.L.str.1, %edi xorl %eax, %eax callq printf movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10_gpu_m_addPiS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z10_gpu_m_addPiS_S_ii,@object # @_Z10_gpu_m_addPiS_S_ii .section .rodata,"a",@progbits .globl _Z10_gpu_m_addPiS_S_ii .p2align 3, 0x0 _Z10_gpu_m_addPiS_S_ii: .quad _Z25__device_stub___gpu_m_addPiS_S_ii .size _Z10_gpu_m_addPiS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%lli\n" .size .L.str.1, 6 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10_gpu_m_addPiS_S_ii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub___gpu_m_addPiS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10_gpu_m_addPiS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z10_gpu_m_addPiS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e280000002100 */ /*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */ /* 0x000e680000002600 */ /*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */ /* 0x000e620000002200 */ /*0050*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */ /* 0x001fc800078e20ff */ /*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */ /* 0x000fe40003f06270 */ /*0070*/ LEA R0, R0, R5, 0x4 ; /* 0x0000000500007211 */ /* 0x002fc800078e20ff */ /*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */ /* 0x000fe200078e0203 */ /*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd00000000a00 */ /*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */ /* 0x000fc800078e0207 */ /*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x0c0fe400078e0207 */ /*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */ /* 0x000fe200078e0207 */ /*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */ /* 0x004fca0007ffe0ff */ /*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*0140*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0150*/ BRA 0x150; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10_gpu_m_addPiS_S_ii .globl _Z10_gpu_m_addPiS_S_ii .p2align 8 .type _Z10_gpu_m_addPiS_S_ii,@function _Z10_gpu_m_addPiS_S_ii: s_load_b64 s[2:3], s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_lshl_add_u32 v1, s15, 4, v1 v_lshl_add_u32 v0, s14, 4, v0 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cmp_gt_i32_e32 vcc_lo, s2, v1 v_cmp_gt_i32_e64 s2, s3, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_and_b32 s2, vcc_lo, s2 s_and_saveexec_b32 s4, s2 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1] s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_nc_u32_e32 v2, v3, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10_gpu_m_addPiS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10_gpu_m_addPiS_S_ii, .Lfunc_end0-_Z10_gpu_m_addPiS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10_gpu_m_addPiS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z10_gpu_m_addPiS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0018770d_00000000-6_parallel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii .type _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, @function _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z10_gpu_m_addPiS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii .globl _Z10_gpu_m_addPiS_S_ii .type _Z10_gpu_m_addPiS_S_ii, @function _Z10_gpu_m_addPiS_S_ii: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z10_gpu_m_addPiS_S_ii, .-_Z10_gpu_m_addPiS_S_ii .globl _Z5m_addPiS_S_ii .type _Z5m_addPiS_S_ii, @function _Z5m_addPiS_S_ii: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %rdi, %r15 movq %rsi, %r14 movq %rdx, %r13 movl %ecx, %ebp movl %r8d, %r12d movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl %ecx, %ebx imull %r8d, %ebx sall $2, %ebx movslq %ebx, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r15, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT pxor %xmm0, %xmm0 cvtsi2ssl %ebp, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm1 movss .LC4(%rip), %xmm3 movaps %xmm0, %xmm2 andps %xmm3, %xmm2 movss .LC1(%rip), %xmm4 ucomiss %xmm2, %xmm4 jbe .L12 cvttss2sil %xmm0, %eax pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 cmpnless %xmm2, %xmm1 movss .LC3(%rip), %xmm4 andps %xmm4, %xmm1 addss %xmm2, %xmm1 andnps %xmm0, %xmm3 orps %xmm3, %xmm1 .L12: pxor %xmm0, %xmm0 cvtsi2ssl %r12d, %xmm0 mulss .LC0(%rip), %xmm0 movaps %xmm0, %xmm4 movss .LC4(%rip), %xmm3 movaps %xmm0, %xmm2 andps %xmm3, %xmm2 movss .LC1(%rip), %xmm5 ucomiss %xmm2, %xmm5 jbe .L13 cvttss2sil %xmm0, %eax pxor %xmm2, %xmm2 cvtsi2ssl %eax, %xmm2 cmpnless %xmm2, %xmm4 movss .LC3(%rip), %xmm5 andps %xmm5, %xmm4 addss %xmm2, %xmm4 andnps %xmm0, %xmm3 orps %xmm3, %xmm4 .L13: cvttss2siq %xmm4, %rax movl %eax, 32(%rsp) cvttss2siq %xmm1, %rax movl %eax, 36(%rsp) movl $16, 44(%rsp) movl $16, 48(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L17 .L14: movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r13, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L18 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L17: .cfi_restore_state movl %r12d, %r8d movl %ebp, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii jmp .L14 .L18: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5m_addPiS_S_ii, .-_Z5m_addPiS_S_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC5: .string "%d" .LC6: .string "%lli\n" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $16, %rsp .cfi_def_cfa_offset 64 movq %fs:40, %rax movq %rax, 8(%rsp) xorl %eax, %eax movq %rsp, %rsi leaq .LC5(%rip), %rbx movq %rbx, %rdi call __isoc23_scanf@PLT leaq 4(%rsp), %rsi movq %rbx, %rdi movl $0, %eax call __isoc23_scanf@PLT movl (%rsp), %r14d movl 4(%rsp), %r12d movslq %r14d, %r13 movslq %r12d, %rax imulq %rax, %r13 salq $2, %r13 movq %r13, %rdi call malloc@PLT movq %rax, %rbp movq %r13, %rdi call malloc@PLT movq %rax, %rbx movq %r13, %rdi call malloc@PLT movq %rax, %r13 testl %r14d, %r14d jle .L20 movl %r12d, %ecx movl $0, %edi movl $0, %esi jmp .L21 .L22: movl %eax, (%rbx,%rdx) movl %eax, 0(%rbp,%rdx) addl $1, %eax addq $4, %rdx cmpl %ecx, %eax jne .L22 .L24: addl $1, %esi addl %r12d, %edi addl $1, %ecx cmpl %esi, %r14d je .L20 .L21: movl %esi, %eax movslq %edi, %rdx salq $2, %rdx testl %r12d, %r12d jg .L22 jmp .L24 .L20: movl %r12d, %r8d movl %r14d, %ecx movq %r13, %rdx movq %rbx, %rsi movq %rbp, %rdi call _Z5m_addPiS_S_ii movl (%rsp), %r10d testl %r10d, %r10d jle .L31 movl 4(%rsp), %r9d movl $0, %r8d movl $0, %edx movl $0, %edi movslq %r9d, %r11 jmp .L26 .L28: movslq %r8d, %rcx leaq 0(%r13,%rcx,4), %rax addq %r11, %rcx leaq 0(%r13,%rcx,4), %rsi .L27: movslq (%rax), %rcx addq %rcx, %rdx addq $4, %rax cmpq %rsi, %rax jne .L27 .L29: addl $1, %edi addl %r9d, %r8d cmpl %r10d, %edi je .L25 .L26: testl %r9d, %r9d jg .L28 jmp .L29 .L31: movl $0, %edx .L25: leaq .LC6(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq %r13, %rdi call free@PLT movq 8(%rsp), %rax subq %fs:40, %rax jne .L36 movl $0, %eax addq $16, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z10_gpu_m_addPiS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z10_gpu_m_addPiS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1031798784 .align 4 .LC1: .long 1258291200 .align 4 .LC3: .long 1065353216 .align 4 .LC4: .long 2147483647 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "parallel.hip" .globl _Z25__device_stub___gpu_m_addPiS_S_ii # -- Begin function _Z25__device_stub___gpu_m_addPiS_S_ii .p2align 4, 0x90 .type _Z25__device_stub___gpu_m_addPiS_S_ii,@function _Z25__device_stub___gpu_m_addPiS_S_ii: # @_Z25__device_stub___gpu_m_addPiS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z10_gpu_m_addPiS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z25__device_stub___gpu_m_addPiS_S_ii, .Lfunc_end0-_Z25__device_stub___gpu_m_addPiS_S_ii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function _Z5m_addPiS_S_ii .LCPI1_0: .long 0x3d800000 # float 0.0625 .text .globl _Z5m_addPiS_S_ii .p2align 4, 0x90 .type _Z5m_addPiS_S_ii,@function _Z5m_addPiS_S_ii: # @_Z5m_addPiS_S_ii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %r8d, %ebp movl %ecx, %r15d movq %rdx, %rbx movq %rsi, %r12 movq %rdi, %r13 movl %ecx, %eax imull %r8d, %eax shll $2, %eax movslq %eax, %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 24(%rsp), %rdi movq %r13, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy cvtsi2ss %ebp, %xmm0 mulss .LCPI1_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %r12 xorps %xmm0, %xmm0 cvtsi2ss %r15d, %xmm0 mulss .LCPI1_0(%rip), %xmm0 callq ceilf@PLT cvttss2si %xmm0, %rdi movl %r12d, %eax shlq $32, %rdi orq %rax, %rdi movabsq $68719476752, %rdx # imm = 0x1000000010 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl %r15d, 36(%rsp) movl %ebp, 32(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 32(%rsp), %rax movq %rax, 144(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z10_gpu_m_addPiS_S_ii, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree xorl %eax, %eax addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5m_addPiS_S_ii, .Lfunc_end1-_Z5m_addPiS_S_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 pushq %rax .cfi_def_cfa_offset 64 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 xorl %r12d, %r12d leaq 4(%rsp), %rsi movl $.L.str, %edi xorl %eax, %eax callq __isoc23_scanf movq %rsp, %rsi movl $.L.str, %edi xorl %eax, %eax callq __isoc23_scanf movslq 4(%rsp), %r13 movslq (%rsp), %rbp movq %r13, %r15 imulq %rbp, %r15 shlq $2, %r15 movq %r15, %rdi callq malloc movq %rax, %rbx movq %r15, %rdi callq malloc movq %rax, %r14 movq %r15, %rdi callq malloc movq %rax, %r15 movl %r13d, %ecx movl %ebp, %r8d testq %r13, %r13 jle .LBB2_6 # %bb.1: # %.preheader34.lr.ph xorl %eax, %eax jmp .LBB2_2 .p2align 4, 0x90 .LBB2_5: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 incq %rax addl %r8d, %r12d cmpq %rcx, %rax je .LBB2_6 .LBB2_2: # %.preheader34 # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 testl %r8d, %r8d jle .LBB2_5 # %bb.3: # %.lr.ph # in Loop: Header=BB2_2 Depth=1 movl %r12d, %esi leaq (%rbx,%rsi,4), %rdx leaq (%r14,%rsi,4), %rsi xorl %edi, %edi .p2align 4, 0x90 .LBB2_4: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 leal (%rax,%rdi), %r9d movl %r9d, (%rsi,%rdi,4) movl %r9d, (%rdx,%rdi,4) incq %rdi cmpq %rdi, %r8 jne .LBB2_4 jmp .LBB2_5 .LBB2_6: # %._crit_edge37 movq %rbx, %rdi movq %r14, %rsi movq %r15, %rdx # kill: def $ecx killed $ecx killed $rcx # kill: def $r8d killed $r8d killed $r8 callq _Z5m_addPiS_S_ii movl 4(%rsp), %eax xorl %ecx, %ecx testl %eax, %eax jle .LBB2_7 # %bb.8: # %.preheader.lr.ph movl (%rsp), %edx xorl %edi, %edi xorl %esi, %esi jmp .LBB2_9 .p2align 4, 0x90 .LBB2_12: # %._crit_edge41 # in Loop: Header=BB2_9 Depth=1 incq %rdi addl %edx, %ecx cmpq %rax, %rdi je .LBB2_13 .LBB2_9: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_11 Depth 2 testl %edx, %edx jle .LBB2_12 # %bb.10: # %.lr.ph40 # in Loop: Header=BB2_9 Depth=1 movl %ecx, %r8d leaq (%r15,%r8,4), %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB2_11: # Parent Loop BB2_9 Depth=1 # => This Inner Loop Header: Depth=2 movslq (%r8,%r9,4), %r10 addq %r10, %rsi incq %r9 cmpq %r9, %rdx jne .LBB2_11 jmp .LBB2_12 .LBB2_7: xorl %esi, %esi .LBB2_13: # %._crit_edge44 movl $.L.str.1, %edi xorl %eax, %eax callq printf movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free xorl %eax, %eax addq $8, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10_gpu_m_addPiS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z10_gpu_m_addPiS_S_ii,@object # @_Z10_gpu_m_addPiS_S_ii .section .rodata,"a",@progbits .globl _Z10_gpu_m_addPiS_S_ii .p2align 3, 0x0 _Z10_gpu_m_addPiS_S_ii: .quad _Z25__device_stub___gpu_m_addPiS_S_ii .size _Z10_gpu_m_addPiS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%d" .size .L.str, 3 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%lli\n" .size .L.str.1, 6 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10_gpu_m_addPiS_S_ii" .size .L__unnamed_1, 23 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub___gpu_m_addPiS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10_gpu_m_addPiS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
static const __constant__ int DIM = 128; __global__ void Normalize128( float *data, int N ) { float tmp[DIM]; float norm1 = 0; float *start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { tmp[i] = *start; norm1 += abs(tmp[i]); start += N; } float norm1_inv = 1.0f / norm1; start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { *start = tmp[i] * norm1_inv; start += N; } }
.file "tmpxft_000b5c4f_00000000-6_lab4e.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z12Normalize128PfiPfi .type _Z33__device_stub__Z12Normalize128PfiPfi, @function _Z33__device_stub__Z12Normalize128PfiPfi: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z12Normalize128Pfi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z33__device_stub__Z12Normalize128PfiPfi, .-_Z33__device_stub__Z12Normalize128PfiPfi .globl _Z12Normalize128Pfi .type _Z12Normalize128Pfi, @function _Z12Normalize128Pfi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z12Normalize128PfiPfi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12Normalize128Pfi, .-_Z12Normalize128Pfi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12Normalize128Pfi" .LC1: .string "DIM" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12Normalize128Pfi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL3DIM(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata .align 4 .type _ZL3DIM, @object .size _ZL3DIM, 4 _ZL3DIM: .long 128 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
static const __constant__ int DIM = 128; __global__ void Normalize128( float *data, int N ) { float tmp[DIM]; float norm1 = 0; float *start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { tmp[i] = *start; norm1 += abs(tmp[i]); start += N; } float norm1_inv = 1.0f / norm1; start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { *start = tmp[i] * norm1_inv; start += N; } }
#include <hip/hip_runtime.h> static const __constant__ int DIM = 128; __global__ void Normalize128( float *data, int N ) { float tmp[DIM]; float norm1 = 0; float *start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { tmp[i] = *start; norm1 += abs(tmp[i]); start += N; } float norm1_inv = 1.0f / norm1; start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { *start = tmp[i] * norm1_inv; start += N; } }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> static const __constant__ int DIM = 128; __global__ void Normalize128( float *data, int N ) { float tmp[DIM]; float norm1 = 0; float *start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { tmp[i] = *start; norm1 += abs(tmp[i]); start += N; } float norm1_inv = 1.0f / norm1; start = data + threadIdx.x + blockIdx.x*blockDim.x; #pragma unroll for ( int i = 0; i < DIM; ++i ) { *start = tmp[i] * norm1_inv; start += N; } }
.text .file "lab4e.hip" .globl _Z27__device_stub__Normalize128Pfi # -- Begin function _Z27__device_stub__Normalize128Pfi .p2align 4, 0x90 .type _Z27__device_stub__Normalize128Pfi,@function _Z27__device_stub__Normalize128Pfi: # @_Z27__device_stub__Normalize128Pfi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z12Normalize128Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z27__device_stub__Normalize128Pfi, .Lfunc_end0-_Z27__device_stub__Normalize128Pfi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12Normalize128Pfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12Normalize128Pfi,@object # @_Z12Normalize128Pfi .section .rodata,"a",@progbits .globl _Z12Normalize128Pfi .p2align 3, 0x0 _Z12Normalize128Pfi: .quad _Z27__device_stub__Normalize128Pfi .size _Z12Normalize128Pfi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12Normalize128Pfi" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__Normalize128Pfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12Normalize128Pfi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000b5c4f_00000000-6_lab4e.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z12Normalize128PfiPfi .type _Z33__device_stub__Z12Normalize128PfiPfi, @function _Z33__device_stub__Z12Normalize128PfiPfi: .LFB2051: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movl %esi, 4(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) leaq 4(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z12Normalize128Pfi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z33__device_stub__Z12Normalize128PfiPfi, .-_Z33__device_stub__Z12Normalize128PfiPfi .globl _Z12Normalize128Pfi .type _Z12Normalize128Pfi, @function _Z12Normalize128Pfi: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z12Normalize128PfiPfi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z12Normalize128Pfi, .-_Z12Normalize128Pfi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z12Normalize128Pfi" .LC1: .string "DIM" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z12Normalize128Pfi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $4, %r9d movl $0, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _ZL3DIM(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata .align 4 .type _ZL3DIM, @object .size _ZL3DIM, 4 _ZL3DIM: .long 128 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "lab4e.hip" .globl _Z27__device_stub__Normalize128Pfi # -- Begin function _Z27__device_stub__Normalize128Pfi .p2align 4, 0x90 .type _Z27__device_stub__Normalize128Pfi,@function _Z27__device_stub__Normalize128Pfi: # @_Z27__device_stub__Normalize128Pfi .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movl %esi, 4(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 4(%rsp), %rax movq %rax, 72(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z12Normalize128Pfi, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z27__device_stub__Normalize128Pfi, .Lfunc_end0-_Z27__device_stub__Normalize128Pfi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z12Normalize128Pfi, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z12Normalize128Pfi,@object # @_Z12Normalize128Pfi .section .rodata,"a",@progbits .globl _Z12Normalize128Pfi .p2align 3, 0x0 _Z12Normalize128Pfi: .quad _Z27__device_stub__Normalize128Pfi .size _Z12Normalize128Pfi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z12Normalize128Pfi" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z27__device_stub__Normalize128Pfi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z12Normalize128Pfi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
code for sm_80 Function : _Z5sommeiPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */ /* 0x001fca00078e0206 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
.file "tmpxft_000503cc_00000000-6_somme.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ .type _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, @function _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5sommeiPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, .-_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ .globl _Z5sommeiPfS_S_ .type _Z5sommeiPfS_S_, @function _Z5sommeiPfS_S_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z5sommeiPfS_S_, .-_Z5sommeiPfS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z5sommeiPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z5sommeiPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5sommeiPfS_S_ .globl _Z5sommeiPfS_S_ .p2align 8 .type _Z5sommeiPfS_S_,@function _Z5sommeiPfS_S_: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5sommeiPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5sommeiPfS_S_, .Lfunc_end0-_Z5sommeiPfS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5sommeiPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5sommeiPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void somme( int taille, float * a, float * b, float *c ){ int index=threadIdx.x+blockDim.x*blockIdx.x; if(index>=taille) return; c[index]=a[index]+b[index]; }
.text .file "somme.hip" .globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_ .p2align 4, 0x90 .type _Z20__device_stub__sommeiPfS_S_,@function _Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 4(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5sommeiPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z20__device_stub__sommeiPfS_S_, .Lfunc_end0-_Z20__device_stub__sommeiPfS_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5sommeiPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z5sommeiPfS_S_,@object # @_Z5sommeiPfS_S_ .section .rodata,"a",@progbits .globl _Z5sommeiPfS_S_ .p2align 3, 0x0 _Z5sommeiPfS_S_: .quad _Z20__device_stub__sommeiPfS_S_ .size _Z5sommeiPfS_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z5sommeiPfS_S_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__sommeiPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5sommeiPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z5sommeiPfS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */ /* 0x001fca00078e0206 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z5sommeiPfS_S_ .globl _Z5sommeiPfS_S_ .p2align 8 .type _Z5sommeiPfS_S_,@function _Z5sommeiPfS_S_: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x18 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z5sommeiPfS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z5sommeiPfS_S_, .Lfunc_end0-_Z5sommeiPfS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z5sommeiPfS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z5sommeiPfS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000503cc_00000000-6_somme.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ .type _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, @function _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movl %edi, 28(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %rcx, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movq %rsp, %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z5sommeiPfS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_, .-_Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ .globl _Z5sommeiPfS_S_ .type _Z5sommeiPfS_S_, @function _Z5sommeiPfS_S_: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z5sommeiPfS_S_iPfS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z5sommeiPfS_S_, .-_Z5sommeiPfS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z5sommeiPfS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z5sommeiPfS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "somme.hip" .globl _Z20__device_stub__sommeiPfS_S_ # -- Begin function _Z20__device_stub__sommeiPfS_S_ .p2align 4, 0x90 .type _Z20__device_stub__sommeiPfS_S_,@function _Z20__device_stub__sommeiPfS_S_: # @_Z20__device_stub__sommeiPfS_S_ .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 4(%rsp) movq %rsi, 72(%rsp) movq %rdx, 64(%rsp) movq %rcx, 56(%rsp) leaq 4(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 56(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z5sommeiPfS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z20__device_stub__sommeiPfS_S_, .Lfunc_end0-_Z20__device_stub__sommeiPfS_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z5sommeiPfS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z5sommeiPfS_S_,@object # @_Z5sommeiPfS_S_ .section .rodata,"a",@progbits .globl _Z5sommeiPfS_S_ .p2align 3, 0x0 _Z5sommeiPfS_S_: .quad _Z20__device_stub__sommeiPfS_S_ .size _Z5sommeiPfS_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z5sommeiPfS_S_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z20__device_stub__sommeiPfS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z5sommeiPfS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
code for sm_80 Function : _Z6vecSumPdS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */ /* 0x000e220000002600 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */ /* 0x000e280000002700 */ /*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e680000002500 */ /*0050*/ S2R R9, SR_TID.Z ; /* 0x0000000000097919 */ /* 0x000ea80000002300 */ /*0060*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */ /* 0x000ee80000002200 */ /*0070*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */ /* 0x000f220000002100 */ /*0080*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */ /* 0x001fc800078e0200 */ /*0090*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */ /* 0x002fc800078e0203 */ /*00a0*/ IMAD R0, R0, c[0x0][0x8], R9 ; /* 0x0000020000007a24 */ /* 0x004fe200078e0209 */ /*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */ /* 0x000fc600000001ff */ /*00c0*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */ /* 0x008fc800078e0207 */ /*00d0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */ /* 0x010fc800078e020b */ /*00e0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fc800078e0009 */ /*00f0*/ IMAD.WIDE.U32 R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */ /* 0x0c0fe400078e0009 */ /*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1b00 */ /*0110*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1b00 */ /*0120*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */ /* 0x000fe200078e0009 */ /*0130*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */ /* 0x004e0e0000000004 */ /*0140*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */ /* 0x001fe2000c101b04 */ /*0150*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0160*/ BRA 0x160; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
.file "tmpxft_0012f56a_00000000-6_vecSum.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z10getGid3d3dv .type _Z10getGid3d3dv, @function _Z10getGid3d3dv: .LFB2027: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2027: .size _Z10getGid3d3dv, .-_Z10getGid3d3dv .globl _Z29__device_stub__Z6vecSumPdS_S_PdS_S_ .type _Z29__device_stub__Z6vecSumPdS_S_PdS_S_, @function _Z29__device_stub__Z6vecSumPdS_S_PdS_S_: .LFB2052: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 120(%rsp), %rax subq %fs:40, %rax jne .L10 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6vecSumPdS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2052: .size _Z29__device_stub__Z6vecSumPdS_S_PdS_S_, .-_Z29__device_stub__Z6vecSumPdS_S_PdS_S_ .globl _Z6vecSumPdS_S_ .type _Z6vecSumPdS_S_, @function _Z6vecSumPdS_S_: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z6vecSumPdS_S_PdS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _Z6vecSumPdS_S_, .-_Z6vecSumPdS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6vecSumPdS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2055: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6vecSumPdS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2055: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
#include <hip/hip_runtime.h> #include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6vecSumPdS_S_ .globl _Z6vecSumPdS_S_ .p2align 8 .type _Z6vecSumPdS_S_,@function _Z6vecSumPdS_S_: s_load_b256 s[4:11], s[0:1], 0x0 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_load_b64 s[0:1], s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_mul_i32 s11, s11, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s11, s11, s14 s_mul_i32 s11, s11, s10 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s11, s11, s13 s_cmp_lt_u32 s13, s10 s_cselect_b32 s10, 12, 18 s_and_b32 s1, s1, 0xffff v_mov_b32_e32 v1, s10 s_lshr_b32 s0, s0, 16 global_load_u16 v5, v1, s[2:3] v_bfe_u32 v1, v0, 20, 10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mad_u64_u32 v[2:3], null, s11, s1, v[1:2] v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 v_mad_u64_u32 v[3:4], null, v2, s0, v[1:2] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, v3, v5, v[0:1] v_mov_b32_e32 v2, 0 v_lshlrev_b64 v[0:1], 3, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 global_load_b64 v[2:3], v[2:3], off global_load_b64 v[4:5], v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[2:3], v[4:5] global_store_b64 v[0:1], v[2:3], off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6vecSumPdS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6vecSumPdS_S_, .Lfunc_end0-_Z6vecSumPdS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6vecSumPdS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6vecSumPdS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __device__ unsigned int getGid3d3d(){ int blockId = blockIdx.x + blockIdx.y * gridDim.x + gridDim.x * gridDim.y * blockIdx.z; int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z) + (threadIdx.y * blockDim.x) + (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x; return threadId; } __global__ void vecSum(double *in, double *factor, double *out){ double result; unsigned int gid = getGid3d3d(); result = in[gid] + factor[gid]; out[gid] = result; }
.text .file "vecSum.hip" .globl _Z21__device_stub__vecSumPdS_S_ # -- Begin function _Z21__device_stub__vecSumPdS_S_ .p2align 4, 0x90 .type _Z21__device_stub__vecSumPdS_S_,@function _Z21__device_stub__vecSumPdS_S_: # @_Z21__device_stub__vecSumPdS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6vecSumPdS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z21__device_stub__vecSumPdS_S_, .Lfunc_end0-_Z21__device_stub__vecSumPdS_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6vecSumPdS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z6vecSumPdS_S_,@object # @_Z6vecSumPdS_S_ .section .rodata,"a",@progbits .globl _Z6vecSumPdS_S_ .p2align 3, 0x0 _Z6vecSumPdS_S_: .quad _Z21__device_stub__vecSumPdS_S_ .size _Z6vecSumPdS_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6vecSumPdS_S_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__vecSumPdS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6vecSumPdS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6vecSumPdS_S_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */ /* 0x000e220000002600 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */ /* 0x000e280000002700 */ /*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e680000002500 */ /*0050*/ S2R R9, SR_TID.Z ; /* 0x0000000000097919 */ /* 0x000ea80000002300 */ /*0060*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */ /* 0x000ee80000002200 */ /*0070*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */ /* 0x000f220000002100 */ /*0080*/ IMAD R0, R5, c[0x0][0x10], R0 ; /* 0x0000040005007a24 */ /* 0x001fc800078e0200 */ /*0090*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */ /* 0x002fc800078e0203 */ /*00a0*/ IMAD R0, R0, c[0x0][0x8], R9 ; /* 0x0000020000007a24 */ /* 0x004fe200078e0209 */ /*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */ /* 0x000fc600000001ff */ /*00c0*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */ /* 0x008fc800078e0207 */ /*00d0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */ /* 0x010fc800078e020b */ /*00e0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */ /* 0x000fc800078e0009 */ /*00f0*/ IMAD.WIDE.U32 R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */ /* 0x0c0fe400078e0009 */ /*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1b00 */ /*0110*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1b00 */ /*0120*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */ /* 0x000fe200078e0009 */ /*0130*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */ /* 0x004e0e0000000004 */ /*0140*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */ /* 0x001fe2000c101b04 */ /*0150*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0160*/ BRA 0x160; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z6vecSumPdS_S_ .globl _Z6vecSumPdS_S_ .p2align 8 .type _Z6vecSumPdS_S_,@function _Z6vecSumPdS_S_: s_load_b256 s[4:11], s[0:1], 0x0 s_add_u32 s2, s0, 24 s_addc_u32 s3, s1, 0 s_load_b64 s[0:1], s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_mul_i32 s11, s11, s15 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) s_add_i32 s11, s11, s14 s_mul_i32 s11, s11, s10 s_delay_alu instid0(SALU_CYCLE_1) s_add_i32 s11, s11, s13 s_cmp_lt_u32 s13, s10 s_cselect_b32 s10, 12, 18 s_and_b32 s1, s1, 0xffff v_mov_b32_e32 v1, s10 s_lshr_b32 s0, s0, 16 global_load_u16 v5, v1, s[2:3] v_bfe_u32 v1, v0, 20, 10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_mad_u64_u32 v[2:3], null, s11, s1, v[1:2] v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 v_mad_u64_u32 v[3:4], null, v2, s0, v[1:2] s_waitcnt vmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, v3, v5, v[0:1] v_mov_b32_e32 v2, 0 v_lshlrev_b64 v[0:1], 3, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v0 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s8, v0 global_load_b64 v[2:3], v[2:3], off global_load_b64 v[4:5], v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f64 v[2:3], v[2:3], v[4:5] global_store_b64 v[0:1], v[2:3], off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6vecSumPdS_S_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 13 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 1 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 2 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z6vecSumPdS_S_, .Lfunc_end0-_Z6vecSumPdS_S_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6vecSumPdS_S_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6vecSumPdS_S_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0012f56a_00000000-6_vecSum.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2030: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2030: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z10getGid3d3dv .type _Z10getGid3d3dv, @function _Z10getGid3d3dv: .LFB2027: .cfi_startproc endbr64 pushq %rax .cfi_def_cfa_offset 16 popq %rax .cfi_def_cfa_offset 8 subq $24, %rsp .cfi_def_cfa_offset 32 movl $1, 12(%rsp) movl 12(%rsp), %edi call exit@PLT .cfi_endproc .LFE2027: .size _Z10getGid3d3dv, .-_Z10getGid3d3dv .globl _Z29__device_stub__Z6vecSumPdS_S_PdS_S_ .type _Z29__device_stub__Z6vecSumPdS_S_PdS_S_, @function _Z29__device_stub__Z6vecSumPdS_S_PdS_S_: .LFB2052: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L9 .L5: movq 120(%rsp), %rax subq %fs:40, %rax jne .L10 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L9: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z6vecSumPdS_S_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L5 .L10: call __stack_chk_fail@PLT .cfi_endproc .LFE2052: .size _Z29__device_stub__Z6vecSumPdS_S_PdS_S_, .-_Z29__device_stub__Z6vecSumPdS_S_PdS_S_ .globl _Z6vecSumPdS_S_ .type _Z6vecSumPdS_S_, @function _Z6vecSumPdS_S_: .LFB2053: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z29__device_stub__Z6vecSumPdS_S_PdS_S_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2053: .size _Z6vecSumPdS_S_, .-_Z6vecSumPdS_S_ .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6vecSumPdS_S_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2055: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6vecSumPdS_S_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2055: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "vecSum.hip" .globl _Z21__device_stub__vecSumPdS_S_ # -- Begin function _Z21__device_stub__vecSumPdS_S_ .p2align 4, 0x90 .type _Z21__device_stub__vecSumPdS_S_,@function _Z21__device_stub__vecSumPdS_S_: # @_Z21__device_stub__vecSumPdS_S_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6vecSumPdS_S_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z21__device_stub__vecSumPdS_S_, .Lfunc_end0-_Z21__device_stub__vecSumPdS_S_ .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6vecSumPdS_S_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z6vecSumPdS_S_,@object # @_Z6vecSumPdS_S_ .section .rodata,"a",@progbits .globl _Z6vecSumPdS_S_ .p2align 3, 0x0 _Z6vecSumPdS_S_: .quad _Z21__device_stub__vecSumPdS_S_ .size _Z6vecSumPdS_S_, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z6vecSumPdS_S_" .size .L__unnamed_1, 16 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z21__device_stub__vecSumPdS_S_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z6vecSumPdS_S_ .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #include <time.h> int blockSize=256; int gridSize=256; __global__ void gameOfLife(int *indata, int *outdata, int width, int height) { __shared__ int sodata[2566]; __shared__ int sidata[256*3]; int tSize=width*height; int x, y, x0,x1,y0,y1, n; int tid; int bid; int cid; for(bid=0;bid<gridDim.x;bid++) { tid=threadIdx.x; cid=bid*blockDim.x+threadIdx.x; if(tid<width) { y=(blockIdx.x*blockDim.x+threadIdx.x) / width; // y position y0=(y-1+height) % height; // one row up y positional value y1=(y+1) % height; // one row below y positional value // load into shared memory sidata[tid]=indata[y0*width+tid]; // upper row sidata[width+tid]=indata[y*width+tid]; // computing cell containing row sidata[2*width+tid]=indata[y1*width+tid]; // lower row } __syncthreads(); } for(bid=0;bid<height;bid++) { if(threadIdx.x<width) { x=(bid*blockDim.x+threadIdx.x) % width; // x position x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too x1=(x+1) % width; // one right x positional value n=sidata[2*width+x0]+sidata[width+x0]+sidata[x0]+sidata[x]+sidata[x1]+sidata[width+x1]+sidata[2*width+x1]+sidata[2*width+x]; // no. of alive neighbor cells if(n==3 || (n==2 && sidata[width+x]==1)) { sodata[threadIdx.x]=1; } else { sodata[threadIdx.x]=0; } } __syncthreads(); //cid+=gridDim.x*blockDim.x; } __syncthreads(); outdata[cid]=sodata[tid]; __syncthreads(); } int main() { clock_t sTime=clock(); int width=256; int height=256; int dsize=width*height; int iteration=1; int i, j; int *data; int *d_indata, *d_outdata, *temp; // allocate memory for data in host data=(int *)malloc(dsize*sizeof(int)); // allocate memory for data in device cudaMalloc(&d_indata, dsize*sizeof(int)); cudaMalloc(&d_outdata, dsize*sizeof(int)); // initialize data in host as randomly 0 or 1 for(i=0;i<dsize;i++) { data[i]=rand()%2; } // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // copy initialized data to gpu device cudaMemcpy( d_indata, data, dsize, cudaMemcpyHostToDevice ); for(i=0;i<iteration;i++) { // call kernel gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height); // synchronize between thread blocks cudaDeviceSynchronize(); // swap d_indata and d_outdata for next iteration temp=d_indata; d_indata=d_outdata; d_outdata=temp; } // copy data back from device to host memory cudaMemcpy( data, d_indata, dsize, cudaMemcpyDeviceToHost); // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // free memory allocated cudaFree(d_indata); cudaFree(d_outdata); free(data); clock_t eTime=clock(); printf("time taken = %ld",eTime-sTime); cudaDeviceReset(); return 0; }
.file "tmpxft_0015fe45_00000000-6_gof.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii .type _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, @function _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z10gameOfLifePiS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, .-_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii .globl _Z10gameOfLifePiS_ii .type _Z10gameOfLifePiS_ii, @function _Z10gameOfLifePiS_ii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z10gameOfLifePiS_ii, .-_Z10gameOfLifePiS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\n board status # \n" .LC1: .string " %d" .LC2: .string "\n" .LC3: .string "time taken = %ld" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call clock@PLT movq %rax, 8(%rsp) movl $262144, %edi call malloc@PLT movq %rax, %r15 leaq 16(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq 262144(%r15), %rbp movq %r15, %rbx .L12: call rand@PLT movl %eax, %edx shrl $31, %edx addl %edx, %eax andl $1, %eax subl %edx, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L12 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 1024(%r15), %rbx leaq 263168(%r15), %r14 movq %rbx, %r12 leaq .LC1(%rip), %r13 .L13: leaq -1024(%r12), %rbp .L14: movl 0(%rbp), %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbp cmpq %r12, %rbp jne .L14 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1024, %r12 cmpq %r14, %r12 jne .L13 movl $1, %ecx movl $65536, %edx movq %r15, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl blockSize(%rip), %eax movl %eax, 44(%rsp) movl $1, 48(%rsp) movl gridSize(%rip), %eax movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L25 .L16: call cudaDeviceSynchronize@PLT movq 16(%rsp), %rax movq 24(%rsp), %rsi movq %rsi, 16(%rsp) movq %rax, 24(%rsp) movl $2, %ecx movl $65536, %edx movq %r15, %rdi call cudaMemcpy@PLT leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC1(%rip), %r12 leaq .LC2(%rip), %r13 .L17: leaq -1024(%rbx), %rbp .L18: movl 0(%rbp), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbp cmpq %rbx, %rbp jne .L18 movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1024, %rbx cmpq %r14, %rbx jne .L17 movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r15, %rdi call free@PLT call clock@PLT movq 8(%rsp), %rcx subq %rcx, %rax movq %rax, %rdx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT call cudaDeviceReset@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L26 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state movl $256, %ecx movl $256, %edx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii jmp .L16 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z10gameOfLifePiS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _Z10gameOfLifePiS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl gridSize .data .align 4 .type gridSize, @object .size gridSize, 4 gridSize: .long 256 .globl blockSize .align 4 .type blockSize, @object .size blockSize, 4 blockSize: .long 256 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #include <time.h> int blockSize=256; int gridSize=256; __global__ void gameOfLife(int *indata, int *outdata, int width, int height) { __shared__ int sodata[2566]; __shared__ int sidata[256*3]; int tSize=width*height; int x, y, x0,x1,y0,y1, n; int tid; int bid; int cid; for(bid=0;bid<gridDim.x;bid++) { tid=threadIdx.x; cid=bid*blockDim.x+threadIdx.x; if(tid<width) { y=(blockIdx.x*blockDim.x+threadIdx.x) / width; // y position y0=(y-1+height) % height; // one row up y positional value y1=(y+1) % height; // one row below y positional value // load into shared memory sidata[tid]=indata[y0*width+tid]; // upper row sidata[width+tid]=indata[y*width+tid]; // computing cell containing row sidata[2*width+tid]=indata[y1*width+tid]; // lower row } __syncthreads(); } for(bid=0;bid<height;bid++) { if(threadIdx.x<width) { x=(bid*blockDim.x+threadIdx.x) % width; // x position x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too x1=(x+1) % width; // one right x positional value n=sidata[2*width+x0]+sidata[width+x0]+sidata[x0]+sidata[x]+sidata[x1]+sidata[width+x1]+sidata[2*width+x1]+sidata[2*width+x]; // no. of alive neighbor cells if(n==3 || (n==2 && sidata[width+x]==1)) { sodata[threadIdx.x]=1; } else { sodata[threadIdx.x]=0; } } __syncthreads(); //cid+=gridDim.x*blockDim.x; } __syncthreads(); outdata[cid]=sodata[tid]; __syncthreads(); } int main() { clock_t sTime=clock(); int width=256; int height=256; int dsize=width*height; int iteration=1; int i, j; int *data; int *d_indata, *d_outdata, *temp; // allocate memory for data in host data=(int *)malloc(dsize*sizeof(int)); // allocate memory for data in device cudaMalloc(&d_indata, dsize*sizeof(int)); cudaMalloc(&d_outdata, dsize*sizeof(int)); // initialize data in host as randomly 0 or 1 for(i=0;i<dsize;i++) { data[i]=rand()%2; } // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // copy initialized data to gpu device cudaMemcpy( d_indata, data, dsize, cudaMemcpyHostToDevice ); for(i=0;i<iteration;i++) { // call kernel gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height); // synchronize between thread blocks cudaDeviceSynchronize(); // swap d_indata and d_outdata for next iteration temp=d_indata; d_indata=d_outdata; d_outdata=temp; } // copy data back from device to host memory cudaMemcpy( data, d_indata, dsize, cudaMemcpyDeviceToHost); // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // free memory allocated cudaFree(d_indata); cudaFree(d_outdata); free(data); clock_t eTime=clock(); printf("time taken = %ld",eTime-sTime); cudaDeviceReset(); return 0; }
#include <hip/hip_runtime.h> #include <stdio.h> #include <time.h> int blockSize=256; int gridSize=256; __global__ void gameOfLife(int *indata, int *outdata, int width, int height) { __shared__ int sodata[2566]; __shared__ int sidata[256*3]; int tSize=width*height; int x, y, x0,x1,y0,y1, n; int tid; int bid; int cid; for(bid=0;bid<gridDim.x;bid++) { tid=threadIdx.x; cid=bid*blockDim.x+threadIdx.x; if(tid<width) { y=(blockIdx.x*blockDim.x+threadIdx.x) / width; // y position y0=(y-1+height) % height; // one row up y positional value y1=(y+1) % height; // one row below y positional value // load into shared memory sidata[tid]=indata[y0*width+tid]; // upper row sidata[width+tid]=indata[y*width+tid]; // computing cell containing row sidata[2*width+tid]=indata[y1*width+tid]; // lower row } __syncthreads(); } for(bid=0;bid<height;bid++) { if(threadIdx.x<width) { x=(bid*blockDim.x+threadIdx.x) % width; // x position x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too x1=(x+1) % width; // one right x positional value n=sidata[2*width+x0]+sidata[width+x0]+sidata[x0]+sidata[x]+sidata[x1]+sidata[width+x1]+sidata[2*width+x1]+sidata[2*width+x]; // no. of alive neighbor cells if(n==3 || (n==2 && sidata[width+x]==1)) { sodata[threadIdx.x]=1; } else { sodata[threadIdx.x]=0; } } __syncthreads(); //cid+=gridDim.x*blockDim.x; } __syncthreads(); outdata[cid]=sodata[tid]; __syncthreads(); } int main() { clock_t sTime=clock(); int width=256; int height=256; int dsize=width*height; int iteration=1; int i, j; int *data; int *d_indata, *d_outdata, *temp; // allocate memory for data in host data=(int *)malloc(dsize*sizeof(int)); // allocate memory for data in device hipMalloc(&d_indata, dsize*sizeof(int)); hipMalloc(&d_outdata, dsize*sizeof(int)); // initialize data in host as randomly 0 or 1 for(i=0;i<dsize;i++) { data[i]=rand()%2; } // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // copy initialized data to gpu device hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice ); for(i=0;i<iteration;i++) { // call kernel gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height); // synchronize between thread blocks hipDeviceSynchronize(); // swap d_indata and d_outdata for next iteration temp=d_indata; d_indata=d_outdata; d_outdata=temp; } // copy data back from device to host memory hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost); // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // free memory allocated hipFree(d_indata); hipFree(d_outdata); free(data); clock_t eTime=clock(); printf("time taken = %ld",eTime-sTime); hipDeviceReset(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <time.h> int blockSize=256; int gridSize=256; __global__ void gameOfLife(int *indata, int *outdata, int width, int height) { __shared__ int sodata[2566]; __shared__ int sidata[256*3]; int tSize=width*height; int x, y, x0,x1,y0,y1, n; int tid; int bid; int cid; for(bid=0;bid<gridDim.x;bid++) { tid=threadIdx.x; cid=bid*blockDim.x+threadIdx.x; if(tid<width) { y=(blockIdx.x*blockDim.x+threadIdx.x) / width; // y position y0=(y-1+height) % height; // one row up y positional value y1=(y+1) % height; // one row below y positional value // load into shared memory sidata[tid]=indata[y0*width+tid]; // upper row sidata[width+tid]=indata[y*width+tid]; // computing cell containing row sidata[2*width+tid]=indata[y1*width+tid]; // lower row } __syncthreads(); } for(bid=0;bid<height;bid++) { if(threadIdx.x<width) { x=(bid*blockDim.x+threadIdx.x) % width; // x position x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too x1=(x+1) % width; // one right x positional value n=sidata[2*width+x0]+sidata[width+x0]+sidata[x0]+sidata[x]+sidata[x1]+sidata[width+x1]+sidata[2*width+x1]+sidata[2*width+x]; // no. of alive neighbor cells if(n==3 || (n==2 && sidata[width+x]==1)) { sodata[threadIdx.x]=1; } else { sodata[threadIdx.x]=0; } } __syncthreads(); //cid+=gridDim.x*blockDim.x; } __syncthreads(); outdata[cid]=sodata[tid]; __syncthreads(); } int main() { clock_t sTime=clock(); int width=256; int height=256; int dsize=width*height; int iteration=1; int i, j; int *data; int *d_indata, *d_outdata, *temp; // allocate memory for data in host data=(int *)malloc(dsize*sizeof(int)); // allocate memory for data in device hipMalloc(&d_indata, dsize*sizeof(int)); hipMalloc(&d_outdata, dsize*sizeof(int)); // initialize data in host as randomly 0 or 1 for(i=0;i<dsize;i++) { data[i]=rand()%2; } // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // copy initialized data to gpu device hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice ); for(i=0;i<iteration;i++) { // call kernel gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height); // synchronize between thread blocks hipDeviceSynchronize(); // swap d_indata and d_outdata for next iteration temp=d_indata; d_indata=d_outdata; d_outdata=temp; } // copy data back from device to host memory hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost); // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // free memory allocated hipFree(d_indata); hipFree(d_outdata); free(data); clock_t eTime=clock(); printf("time taken = %ld",eTime-sTime); hipDeviceReset(); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z10gameOfLifePiS_ii .globl _Z10gameOfLifePiS_ii .p2align 8 .type _Z10gameOfLifePiS_ii,@function _Z10gameOfLifePiS_ii: s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x10 s_load_b32 s3, s[0:1], 0x18 s_add_u32 s6, s0, 24 s_addc_u32 s7, s1, 0 s_waitcnt lgkmcnt(0) v_cvt_f32_u32_e32 v3, s4 s_cmp_eq_u32 s3, 0 s_cbranch_scc1 .LBB0_6 s_ashr_i32 s8, s5, 31 s_delay_alu instid0(VALU_DEP_1) v_rcp_iflag_f32_e32 v1, v3 s_add_i32 s9, s5, s8 s_load_b32 s2, s[6:7], 0xc s_xor_b32 s10, s9, s8 s_sub_i32 s11, 0, s4 v_cvt_f32_u32_e32 v4, s10 s_load_b64 s[8:9], s[0:1], 0x0 v_lshl_add_u32 v7, s4, 1, v0 v_cmp_gt_i32_e32 vcc_lo, s4, v0 s_add_i32 s12, s5, -1 v_rcp_iflag_f32_e32 v6, v4 s_waitcnt_depctr 0xfff v_mul_f32_e32 v1, 0x4f7ffffe, v1 s_mov_b32 s13, s3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cvt_u32_f32_e32 v1, v1 v_mul_lo_u32 v2, s11, v1 s_waitcnt lgkmcnt(0) s_and_b32 s11, s2, 0xffff s_sub_i32 s2, 0, s10 v_mad_u64_u32 v[4:5], null, s15, s11, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_hi_u32 v2, v1, v2 v_add_nc_u32_e32 v1, v1, v2 v_mul_f32_e32 v2, 0x4f7ffffe, v6 v_add_nc_u32_e32 v6, s4, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_hi_u32 v1, v4, v1 v_cvt_u32_f32_e32 v9, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_mul_lo_u32 v2, s2, v9 v_mul_lo_u32 v5, v1, s4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v10, v9, v2 v_sub_nc_u32_e32 v2, v4, v5 v_lshl_add_u32 v4, v0, 2, 0x2820 v_lshl_add_u32 v5, v6, 2, 0x2820 v_lshl_add_u32 v6, v7, 2, 0x2820 v_add_nc_u32_e32 v7, 1, v1 v_subrev_nc_u32_e32 v8, s4, v2 v_add_nc_u32_e32 v9, v9, v10 s_branch .LBB0_3 .LBB0_2: s_or_b32 exec_lo, exec_lo, s14 s_add_i32 s13, s13, -1 s_waitcnt lgkmcnt(0) s_cmp_eq_u32 s13, 0 s_barrier buffer_gl0_inv s_cbranch_scc1 .LBB0_5 .LBB0_3: s_and_saveexec_b32 s14, vcc_lo s_cbranch_execz .LBB0_2 v_cmp_le_u32_e64 s2, s4, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_cndmask_b32_e64 v10, v1, v7, s2 v_cndmask_b32_e64 v11, v2, v8, s2 v_add_nc_u32_e32 v12, 1, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_le_u32_e64 s2, s4, v11 v_cndmask_b32_e64 v12, v10, v12, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v10, s12, v12 v_add_nc_u32_e32 v11, 1, v12 v_ashrrev_i32_e32 v13, 31, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v14, 31, v11 v_add_nc_u32_e32 v10, v10, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v11, v11, v14 v_xor_b32_e32 v10, v10, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v11, v11, v14 v_mul_hi_u32 v15, v10, v9 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v16, v11, v9 v_mul_lo_u32 v15, v15, s10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v16, v16, s10 v_sub_nc_u32_e32 v10, v10, v15 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v11, v11, v16 v_subrev_nc_u32_e32 v15, s10, v10 v_cmp_le_u32_e64 s2, s10, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v16, s10, v11 v_cndmask_b32_e64 v10, v10, v15, s2 v_cmp_le_u32_e64 s2, s10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v15, s10, v10 v_cndmask_b32_e64 v11, v11, v16, s2 v_cmp_le_u32_e64 s2, s10, v10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v16, s10, v11 v_cndmask_b32_e64 v10, v10, v15, s2 v_cmp_le_u32_e64 s2, s10, v11 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v15, v10, v13 v_cndmask_b32_e64 v11, v11, v16, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_xor_b32_e32 v16, v11, v14 v_mad_u64_u32 v[10:11], null, v12, s4, v[0:1] v_sub_nc_u32_e32 v11, v15, v13 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v16, v16, v14 v_mad_u64_u32 v[12:13], null, v11, s4, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mad_u64_u32 v[14:15], null, v16, s4, v[0:1] v_ashrrev_i32_e32 v11, 31, v10 v_ashrrev_i32_e32 v13, 31, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) v_lshlrev_b64 v[10:11], 2, v[10:11] v_ashrrev_i32_e32 v15, 31, v14 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64 v[12:13], 2, v[12:13] v_add_co_u32 v10, s2, s8, v10 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) v_lshlrev_b64 v[14:15], 2, v[14:15] v_add_co_ci_u32_e64 v11, s2, s9, v11, s2 v_add_co_u32 v12, s2, s8, v12 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_co_ci_u32_e64 v13, s2, s9, v13, s2 v_add_co_u32 v14, s2, s8, v14 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v15, s2, s9, v15, s2 s_clause 0x2 global_load_b32 v12, v[12:13], off global_load_b32 v10, v[10:11], off global_load_b32 v11, v[14:15], off s_waitcnt vmcnt(2) ds_store_b32 v4, v12 s_waitcnt vmcnt(1) ds_store_b32 v5, v10 s_waitcnt vmcnt(0) ds_store_b32 v6, v11 s_branch .LBB0_2 .LBB0_5: s_add_i32 s3, s3, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s3, s11, v[0:1] v_ashrrev_i32_e32 v2, 31, v1 s_cmp_lt_i32 s5, 1 s_cbranch_scc0 .LBB0_7 s_branch .LBB0_20 .LBB0_6: v_mov_b32_e32 v1, 0 v_mov_b32_e32 v2, 0 s_cmp_lt_i32 s5, 1 s_cbranch_scc1 .LBB0_20 .LBB0_7: s_ashr_i32 s2, s4, 31 v_rcp_iflag_f32_e32 v3, v3 s_add_i32 s3, s4, s2 v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_xor_b32 s8, s3, s2 s_sub_i32 s2, 0, s4 v_cvt_f32_u32_e32 v4, s8 s_sub_i32 s3, 0, s8 s_add_i32 s9, s4, -1 s_lshl_b32 s10, s4, 1 s_mov_b32 s11, 0 v_rcp_iflag_f32_e32 v4, v4 s_waitcnt_depctr 0xfff v_mul_f32_e32 v3, 0x4f7ffffe, v3 v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v10, 1 v_mul_f32_e32 v4, 0x4f7ffffe, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_u32_f32_e32 v3, v3 v_cvt_u32_f32_e32 v4, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v5, s2, v3 v_mul_lo_u32 v6, s3, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_hi_u32 v5, v3, v5 v_mul_hi_u32 v9, v4, v6 v_lshlrev_b32_e32 v6, 2, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v8, v3, v5 v_add_nc_u32_e32 v9, v4, v9 s_branch .LBB0_9 .LBB0_8: s_or_b32 exec_lo, exec_lo, s12 s_add_i32 s11, s11, 1 s_waitcnt lgkmcnt(0) s_cmp_lg_u32 s5, s11 s_barrier buffer_gl0_inv s_cbranch_scc0 .LBB0_20 .LBB0_9: s_and_saveexec_b32 s12, vcc_lo s_cbranch_execz .LBB0_8 s_load_b32 s2, s[6:7], 0xc s_mov_b32 s14, 0 s_mov_b32 s13, 0 s_mov_b32 s3, exec_lo s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_u64_u32 v[3:4], null, s11, s2, v[0:1] v_mul_hi_u32 v4, v3, v8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v4, v4, s4 v_sub_nc_u32_e32 v3, v3, v4 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v4, s4, v3 v_cmp_le_u32_e64 s2, s4, v3 v_cndmask_b32_e64 v3, v3, v4, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_subrev_nc_u32_e32 v4, s4, v3 v_cmp_le_u32_e64 s2, s4, v3 v_cndmask_b32_e64 v11, v3, v4, s2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) v_add_nc_u32_e32 v3, s9, v11 v_add_nc_u32_e32 v4, 1, v11 v_add_lshl_u32 v16, v11, s10, 2 v_ashrrev_i32_e32 v13, 31, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v12, 31, v4 v_add_nc_u32_e32 v3, v3, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_nc_u32_e32 v4, v4, v12 v_xor_b32_e32 v15, v3, v13 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_xor_b32_e32 v14, v4, v12 v_mad_u64_u32 v[4:5], null, v15, v9, 0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_u64_u32 v[3:4], null, v14, v9, 0 v_mul_lo_u32 v3, v5, s8 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v4, v4, s8 v_sub_nc_u32_e32 v3, v15, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v4, v14, v4 v_subrev_nc_u32_e32 v5, s8, v3 v_cmp_le_u32_e64 s2, s8, v3 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) v_cndmask_b32_e64 v3, v3, v5, s2 v_subrev_nc_u32_e32 v5, s8, v4 v_cmp_le_u32_e64 s2, s8, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v14, s8, v3 v_cndmask_b32_e64 v4, v4, v5, s2 v_cmp_le_u32_e64 s2, s8, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v5, s8, v4 v_cndmask_b32_e64 v3, v3, v14, s2 v_cmp_le_u32_e64 s2, s8, v4 v_lshlrev_b32_e32 v14, 2, v11 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_xor_b32_e32 v3, v3, v13 v_cndmask_b32_e64 v4, v4, v5, s2 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_sub_nc_u32_e32 v3, v3, v13 v_xor_b32_e32 v4, v4, v12 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_lshl_u32 v5, v3, s10, 2 v_add_lshl_u32 v13, v3, s4, 2 v_sub_nc_u32_e32 v4, v4, v12 v_lshlrev_b32_e32 v3, 2, v3 ds_load_b32 v5, v5 offset:10272 ds_load_b32 v12, v13 offset:10272 ds_load_b32 v3, v3 offset:10272 ds_load_b32 v14, v14 offset:10272 v_lshlrev_b32_e32 v13, 2, v4 v_add_lshl_u32 v15, v4, s4, 2 v_add_lshl_u32 v4, v4, s10, 2 ds_load_b32 v13, v13 offset:10272 ds_load_b32 v15, v15 offset:10272 ds_load_b32 v4, v4 offset:10272 ds_load_b32 v16, v16 offset:10272 s_waitcnt lgkmcnt(6) v_add_nc_u32_e32 v5, v12, v5 s_waitcnt lgkmcnt(4) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_add3_u32 v3, v5, v3, v14 s_waitcnt lgkmcnt(2) v_add3_u32 v3, v3, v13, v15 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add3_u32 v3, v3, v4, v16 v_cmpx_lt_i32_e32 2, v3 s_xor_b32 s3, exec_lo, s3 v_cmp_ne_u32_e64 s2, 3, v3 s_mov_b32 s13, exec_lo s_delay_alu instid0(VALU_DEP_1) s_and_b32 s14, s2, exec_lo s_and_not1_saveexec_b32 s15, s3 s_cbranch_execz .LBB0_16 s_mov_b32 s3, -1 s_mov_b32 s17, s13 s_mov_b32 s16, exec_lo v_cmpx_eq_u32_e32 2, v3 s_cbranch_execz .LBB0_15 v_add_lshl_u32 v3, v11, s4, 2 s_and_not1_b32 s17, s13, exec_lo ds_load_b32 v3, v3 offset:10272 s_waitcnt lgkmcnt(0) v_cmp_eq_u32_e64 s2, 1, v3 v_cmp_ne_u32_e64 s3, 1, v3 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) s_and_b32 s2, s2, exec_lo s_or_not1_b32 s3, s3, exec_lo s_or_b32 s17, s17, s2 .LBB0_15: s_or_b32 exec_lo, exec_lo, s16 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 s2, s13, exec_lo s_and_b32 s13, s17, exec_lo s_and_not1_b32 s14, s14, exec_lo s_and_b32 s3, s3, exec_lo s_or_b32 s13, s2, s13 s_or_b32 s14, s14, s3 .LBB0_16: s_or_b32 exec_lo, exec_lo, s15 s_and_saveexec_b32 s2, s14 s_cbranch_execz .LBB0_18 s_and_not1_b32 s13, s13, exec_lo ds_store_b32 v6, v7 .LBB0_18: s_or_b32 exec_lo, exec_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 exec_lo, exec_lo, s13 s_cbranch_execz .LBB0_8 ds_store_b32 v6, v10 s_branch .LBB0_8 .LBB0_20: s_load_b64 s[0:1], s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv ds_load_b32 v3, v0 v_lshlrev_b64 v[0:1], 2, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt lgkmcnt(0) global_store_b32 v[0:1], v3, off s_waitcnt_vscnt null, 0x0 s_barrier buffer_gl0_inv s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z10gameOfLifePiS_ii .amdhsa_group_segment_fixed_size 13344 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 17 .amdhsa_next_free_sgpr 18 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z10gameOfLifePiS_ii, .Lfunc_end0-_Z10gameOfLifePiS_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 13344 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z10gameOfLifePiS_ii .private_segment_fixed_size: 0 .sgpr_count: 20 .sgpr_spill_count: 0 .symbol: _Z10gameOfLifePiS_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 17 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #include <time.h> int blockSize=256; int gridSize=256; __global__ void gameOfLife(int *indata, int *outdata, int width, int height) { __shared__ int sodata[2566]; __shared__ int sidata[256*3]; int tSize=width*height; int x, y, x0,x1,y0,y1, n; int tid; int bid; int cid; for(bid=0;bid<gridDim.x;bid++) { tid=threadIdx.x; cid=bid*blockDim.x+threadIdx.x; if(tid<width) { y=(blockIdx.x*blockDim.x+threadIdx.x) / width; // y position y0=(y-1+height) % height; // one row up y positional value y1=(y+1) % height; // one row below y positional value // load into shared memory sidata[tid]=indata[y0*width+tid]; // upper row sidata[width+tid]=indata[y*width+tid]; // computing cell containing row sidata[2*width+tid]=indata[y1*width+tid]; // lower row } __syncthreads(); } for(bid=0;bid<height;bid++) { if(threadIdx.x<width) { x=(bid*blockDim.x+threadIdx.x) % width; // x position x0=(x-1+width) % width; // one left x positional value assuming circular edge connecting every cell in edges too x1=(x+1) % width; // one right x positional value n=sidata[2*width+x0]+sidata[width+x0]+sidata[x0]+sidata[x]+sidata[x1]+sidata[width+x1]+sidata[2*width+x1]+sidata[2*width+x]; // no. of alive neighbor cells if(n==3 || (n==2 && sidata[width+x]==1)) { sodata[threadIdx.x]=1; } else { sodata[threadIdx.x]=0; } } __syncthreads(); //cid+=gridDim.x*blockDim.x; } __syncthreads(); outdata[cid]=sodata[tid]; __syncthreads(); } int main() { clock_t sTime=clock(); int width=256; int height=256; int dsize=width*height; int iteration=1; int i, j; int *data; int *d_indata, *d_outdata, *temp; // allocate memory for data in host data=(int *)malloc(dsize*sizeof(int)); // allocate memory for data in device hipMalloc(&d_indata, dsize*sizeof(int)); hipMalloc(&d_outdata, dsize*sizeof(int)); // initialize data in host as randomly 0 or 1 for(i=0;i<dsize;i++) { data[i]=rand()%2; } // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // copy initialized data to gpu device hipMemcpy( d_indata, data, dsize, hipMemcpyHostToDevice ); for(i=0;i<iteration;i++) { // call kernel gameOfLife<<<gridSize, blockSize>>>(d_indata, d_outdata, width, height); // synchronize between thread blocks hipDeviceSynchronize(); // swap d_indata and d_outdata for next iteration temp=d_indata; d_indata=d_outdata; d_outdata=temp; } // copy data back from device to host memory hipMemcpy( data, d_indata, dsize, hipMemcpyDeviceToHost); // diplay cell status in console printf("\n board status # \n"); for(i=0;i<height;i++) { for(j=0;j<width;j++) { printf(" %d",data[i*width+j]); } printf("\n"); } // free memory allocated hipFree(d_indata); hipFree(d_outdata); free(data); clock_t eTime=clock(); printf("time taken = %ld",eTime-sTime); hipDeviceReset(); return 0; }
.text .file "gof.hip" .globl _Z25__device_stub__gameOfLifePiS_ii # -- Begin function _Z25__device_stub__gameOfLifePiS_ii .p2align 4, 0x90 .type _Z25__device_stub__gameOfLifePiS_ii,@function _Z25__device_stub__gameOfLifePiS_ii: # @_Z25__device_stub__gameOfLifePiS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z10gameOfLifePiS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z25__device_stub__gameOfLifePiS_ii, .Lfunc_end0-_Z25__device_stub__gameOfLifePiS_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 callq clock movq %rax, %rbx movl $262144, %edi # imm = 0x40000 callq malloc movq %rax, %r14 leaq 8(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc leaq 16(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movl %eax, %ecx shrl $31, %ecx addl %eax, %ecx andl $-2, %ecx subl %ecx, %eax movl %eax, (%r14,%r15,4) incq %r15 cmpq $65536, %r15 # imm = 0x10000 jne .LBB1_1 # %bb.2: movl $.Lstr.1, %edi callq puts@PLT movq %r14, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_3: # %.preheader51 # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_3 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $256, %r13 # imm = 0x100 jne .LBB1_4 # %bb.5: # in Loop: Header=BB1_3 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $1024, %r15 # imm = 0x400 cmpq $256, %r12 # imm = 0x100 jne .LBB1_3 # %bb.6: # %.critedge movq 8(%rsp), %rdi movl $65536, %edx # imm = 0x10000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl gridSize(%rip), %edi movl blockSize(%rip), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: movq 8(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl $256, 28(%rsp) # imm = 0x100 movl $256, 24(%rsp) # imm = 0x100 leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10gameOfLifePiS_ii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_8: callq hipDeviceSynchronize movq 8(%rsp), %rax movq 16(%rsp), %rsi movq %rsi, 8(%rsp) movq %rax, 16(%rsp) movl $65536, %edx # imm = 0x10000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $.Lstr.1, %edi callq puts@PLT movq %r14, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_9: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_10 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_10: # Parent Loop BB1_9 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $256, %r13 # imm = 0x100 jne .LBB1_10 # %bb.11: # in Loop: Header=BB1_9 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $1024, %r15 # imm = 0x400 cmpq $256, %r12 # imm = 0x100 jne .LBB1_9 # %bb.12: movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %r14, %rdi callq free callq clock subq %rbx, %rax movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf callq hipDeviceReset xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10gameOfLifePiS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type blockSize,@object # @blockSize .data .globl blockSize .p2align 2, 0x0 blockSize: .long 256 # 0x100 .size blockSize, 4 .type gridSize,@object # @gridSize .globl gridSize .p2align 2, 0x0 gridSize: .long 256 # 0x100 .size gridSize, 4 .type _Z10gameOfLifePiS_ii,@object # @_Z10gameOfLifePiS_ii .section .rodata,"a",@progbits .globl _Z10gameOfLifePiS_ii .p2align 3, 0x0 _Z10gameOfLifePiS_ii: .quad _Z25__device_stub__gameOfLifePiS_ii .size _Z10gameOfLifePiS_ii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz " %d" .size .L.str.1, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "time taken = %ld" .size .L.str.3, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10gameOfLifePiS_ii" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr.1,@object # @str.1 .section .rodata.str1.1,"aMS",@progbits,1 .Lstr.1: .asciz "\n board status # " .size .Lstr.1, 18 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__gameOfLifePiS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10gameOfLifePiS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0015fe45_00000000-6_gof.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii .type _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, @function _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii: .LFB2082: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z10gameOfLifePiS_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii, .-_Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii .globl _Z10gameOfLifePiS_ii .type _Z10gameOfLifePiS_ii, @function _Z10gameOfLifePiS_ii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z10gameOfLifePiS_ii, .-_Z10gameOfLifePiS_ii .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "\n board status # \n" .LC1: .string " %d" .LC2: .string "\n" .LC3: .string "time taken = %ld" .text .globl main .type main, @function main: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax call clock@PLT movq %rax, 8(%rsp) movl $262144, %edi call malloc@PLT movq %rax, %r15 leaq 16(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $262144, %esi call cudaMalloc@PLT leaq 262144(%r15), %rbp movq %r15, %rbx .L12: call rand@PLT movl %eax, %edx shrl $31, %edx addl %edx, %eax andl $1, %eax subl %edx, %eax movl %eax, (%rbx) addq $4, %rbx cmpq %rbp, %rbx jne .L12 leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq 1024(%r15), %rbx leaq 263168(%r15), %r14 movq %rbx, %r12 leaq .LC1(%rip), %r13 .L13: leaq -1024(%r12), %rbp .L14: movl 0(%rbp), %edx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbp cmpq %r12, %rbp jne .L14 leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1024, %r12 cmpq %r14, %r12 jne .L13 movl $1, %ecx movl $65536, %edx movq %r15, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl blockSize(%rip), %eax movl %eax, 44(%rsp) movl $1, 48(%rsp) movl gridSize(%rip), %eax movl %eax, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L25 .L16: call cudaDeviceSynchronize@PLT movq 16(%rsp), %rax movq 24(%rsp), %rsi movq %rsi, 16(%rsp) movq %rax, 24(%rsp) movl $2, %ecx movl $65536, %edx movq %r15, %rdi call cudaMemcpy@PLT leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC1(%rip), %r12 leaq .LC2(%rip), %r13 .L17: leaq -1024(%rbx), %rbp .L18: movl 0(%rbp), %edx movq %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $4, %rbp cmpq %rbx, %rbp jne .L18 movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1024, %rbx cmpq %r14, %rbx jne .L17 movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r15, %rdi call free@PLT call clock@PLT movq 8(%rsp), %rcx subq %rcx, %rax movq %rax, %rdx leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT call cudaDeviceReset@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L26 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L25: .cfi_restore_state movl $256, %ecx movl $256, %edx movq 24(%rsp), %rsi movq 16(%rsp), %rdi call _Z34__device_stub__Z10gameOfLifePiS_iiPiS_ii jmp .L16 .L26: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size main, .-main .section .rodata.str1.1 .LC4: .string "_Z10gameOfLifePiS_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _Z10gameOfLifePiS_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .globl gridSize .data .align 4 .type gridSize, @object .size gridSize, 4 gridSize: .long 256 .globl blockSize .align 4 .type blockSize, @object .size blockSize, 4 blockSize: .long 256 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "gof.hip" .globl _Z25__device_stub__gameOfLifePiS_ii # -- Begin function _Z25__device_stub__gameOfLifePiS_ii .p2align 4, 0x90 .type _Z25__device_stub__gameOfLifePiS_ii,@function _Z25__device_stub__gameOfLifePiS_ii: # @_Z25__device_stub__gameOfLifePiS_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movl %edx, 12(%rsp) movl %ecx, 8(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 12(%rsp), %rax movq %rax, 96(%rsp) leaq 8(%rsp), %rax movq %rax, 104(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z10gameOfLifePiS_ii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z25__device_stub__gameOfLifePiS_ii, .Lfunc_end0-_Z25__device_stub__gameOfLifePiS_ii .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 callq clock movq %rax, %rbx movl $262144, %edi # imm = 0x40000 callq malloc movq %rax, %r14 leaq 8(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc leaq 16(%rsp), %rdi movl $262144, %esi # imm = 0x40000 callq hipMalloc xorl %r15d, %r15d .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 callq rand movl %eax, %ecx shrl $31, %ecx addl %eax, %ecx andl $-2, %ecx subl %ecx, %eax movl %eax, (%r14,%r15,4) incq %r15 cmpq $65536, %r15 # imm = 0x10000 jne .LBB1_1 # %bb.2: movl $.Lstr.1, %edi callq puts@PLT movq %r14, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_3: # %.preheader51 # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_3 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $256, %r13 # imm = 0x100 jne .LBB1_4 # %bb.5: # in Loop: Header=BB1_3 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $1024, %r15 # imm = 0x400 cmpq $256, %r12 # imm = 0x100 jne .LBB1_3 # %bb.6: # %.critedge movq 8(%rsp), %rdi movl $65536, %edx # imm = 0x10000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movl gridSize(%rip), %edi movl blockSize(%rip), %edx movabsq $4294967296, %rax # imm = 0x100000000 orq %rax, %rdi orq %rax, %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_8 # %bb.7: movq 8(%rsp), %rax movq 16(%rsp), %rcx movq %rax, 88(%rsp) movq %rcx, 80(%rsp) movl $256, 28(%rsp) # imm = 0x100 movl $256, 24(%rsp) # imm = 0x100 leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 28(%rsp), %rax movq %rax, 112(%rsp) leaq 24(%rsp), %rax movq %rax, 120(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z10gameOfLifePiS_ii, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_8: callq hipDeviceSynchronize movq 8(%rsp), %rax movq 16(%rsp), %rsi movq %rsi, 8(%rsp) movq %rax, 16(%rsp) movl $65536, %edx # imm = 0x10000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $.Lstr.1, %edi callq puts@PLT movq %r14, %r15 xorl %r12d, %r12d .p2align 4, 0x90 .LBB1_9: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_10 Depth 2 xorl %r13d, %r13d .p2align 4, 0x90 .LBB1_10: # Parent Loop BB1_9 Depth=1 # => This Inner Loop Header: Depth=2 movl (%r15,%r13,4), %esi movl $.L.str.1, %edi xorl %eax, %eax callq printf incq %r13 cmpq $256, %r13 # imm = 0x100 jne .LBB1_10 # %bb.11: # in Loop: Header=BB1_9 Depth=1 movl $10, %edi callq putchar@PLT incq %r12 addq $1024, %r15 # imm = 0x400 cmpq $256, %r12 # imm = 0x100 jne .LBB1_9 # %bb.12: movq 8(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %r14, %rdi callq free callq clock subq %rbx, %rax movl $.L.str.3, %edi movq %rax, %rsi xorl %eax, %eax callq printf callq hipDeviceReset xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z10gameOfLifePiS_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type blockSize,@object # @blockSize .data .globl blockSize .p2align 2, 0x0 blockSize: .long 256 # 0x100 .size blockSize, 4 .type gridSize,@object # @gridSize .globl gridSize .p2align 2, 0x0 gridSize: .long 256 # 0x100 .size gridSize, 4 .type _Z10gameOfLifePiS_ii,@object # @_Z10gameOfLifePiS_ii .section .rodata,"a",@progbits .globl _Z10gameOfLifePiS_ii .p2align 3, 0x0 _Z10gameOfLifePiS_ii: .quad _Z25__device_stub__gameOfLifePiS_ii .size _Z10gameOfLifePiS_ii, 8 .type .L.str.1,@object # @.str.1 .section .rodata.str1.1,"aMS",@progbits,1 .L.str.1: .asciz " %d" .size .L.str.1, 4 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "time taken = %ld" .size .L.str.3, 17 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z10gameOfLifePiS_ii" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr.1,@object # @str.1 .section .rodata.str1.1,"aMS",@progbits,1 .Lstr.1: .asciz "\n board status # " .size .Lstr.1, 18 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z25__device_stub__gameOfLifePiS_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z10gameOfLifePiS_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
code for sm_80 Function : _Z15vectorAddKernelPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
.file "tmpxft_00063ad9_00000000-6_vectorAddKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i .type _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i, @function _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z15vectorAddKernelPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i .globl _Z15vectorAddKernelPfS_S_i .type _Z15vectorAddKernelPfS_S_i, @function _Z15vectorAddKernelPfS_S_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z15vectorAddKernelPfS_S_i, .-_Z15vectorAddKernelPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z15vectorAddKernelPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z15vectorAddKernelPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
#include <hip/hip_runtime.h> #include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15vectorAddKernelPfS_S_i .globl _Z15vectorAddKernelPfS_S_i .p2align 8 .type _Z15vectorAddKernelPfS_S_i,@function _Z15vectorAddKernelPfS_S_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15vectorAddKernelPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15vectorAddKernelPfS_S_i, .Lfunc_end0-_Z15vectorAddKernelPfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15vectorAddKernelPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15vectorAddKernelPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include "includes.h" __global__ void vectorAddKernel(float* inputA, float* inputB, float* output, int length){ //compute element index int idx = blockIdx.x * blockDim.x + threadIdx.x; //add an vector element if(idx < length) output[idx] = inputA[idx] + inputB[idx]; }
.text .file "vectorAddKernel.hip" .globl _Z30__device_stub__vectorAddKernelPfS_S_i # -- Begin function _Z30__device_stub__vectorAddKernelPfS_S_i .p2align 4, 0x90 .type _Z30__device_stub__vectorAddKernelPfS_S_i,@function _Z30__device_stub__vectorAddKernelPfS_S_i: # @_Z30__device_stub__vectorAddKernelPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z15vectorAddKernelPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z30__device_stub__vectorAddKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPfS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15vectorAddKernelPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z15vectorAddKernelPfS_S_i,@object # @_Z15vectorAddKernelPfS_S_i .section .rodata,"a",@progbits .globl _Z15vectorAddKernelPfS_S_i .p2align 3, 0x0 _Z15vectorAddKernelPfS_S_i: .quad _Z30__device_stub__vectorAddKernelPfS_S_i .size _Z15vectorAddKernelPfS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z15vectorAddKernelPfS_S_i" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__vectorAddKernelPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15vectorAddKernelPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z15vectorAddKernelPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */ /* 0x000e280000002500 */ /*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e240000002100 */ /*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */ /* 0x001fca00078e0203 */ /*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */ /* 0x000fda0003f06270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */ /* 0x000fc800078e0207 */ /*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */ /* 0x0c0fe400078e0207 */ /*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea8000c1e1900 */ /*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea2000c1e1900 */ /*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */ /* 0x000fc800078e0207 */ /*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */ /* 0x004fca0000000000 */ /*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00f0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0100*/ BRA 0x100; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z15vectorAddKernelPfS_S_i .globl _Z15vectorAddKernelPfS_S_i .p2align 8 .type _Z15vectorAddKernelPfS_S_i,@function _Z15vectorAddKernelPfS_S_i: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b32 s3, s[0:1], 0x18 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e64 s3, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_ashrrev_i32_e32 v2, 31, v1 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v4, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s0, v0 global_load_b32 v2, v[2:3], off global_load_b32 v3, v[4:5], off v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z15vectorAddKernelPfS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z15vectorAddKernelPfS_S_i, .Lfunc_end0-_Z15vectorAddKernelPfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z15vectorAddKernelPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z15vectorAddKernelPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_00063ad9_00000000-6_vectorAddKernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2029: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2029: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i .type _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i, @function _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i: .LFB2051: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z15vectorAddKernelPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2051: .size _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i .globl _Z15vectorAddKernelPfS_S_i .type _Z15vectorAddKernelPfS_S_i, @function _Z15vectorAddKernelPfS_S_i: .LFB2052: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z40__device_stub__Z15vectorAddKernelPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2052: .size _Z15vectorAddKernelPfS_S_i, .-_Z15vectorAddKernelPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z15vectorAddKernelPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2054: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z15vectorAddKernelPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2054: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "vectorAddKernel.hip" .globl _Z30__device_stub__vectorAddKernelPfS_S_i # -- Begin function _Z30__device_stub__vectorAddKernelPfS_S_i .p2align 4, 0x90 .type _Z30__device_stub__vectorAddKernelPfS_S_i,@function _Z30__device_stub__vectorAddKernelPfS_S_i: # @_Z30__device_stub__vectorAddKernelPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z15vectorAddKernelPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z30__device_stub__vectorAddKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__vectorAddKernelPfS_S_i .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB1_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB1_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z15vectorAddKernelPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end1: .size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB2_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB2_2: retq .Lfunc_end2: .size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor .cfi_endproc # -- End function .type _Z15vectorAddKernelPfS_S_i,@object # @_Z15vectorAddKernelPfS_S_i .section .rodata,"a",@progbits .globl _Z15vectorAddKernelPfS_S_i .p2align 3, 0x0 _Z15vectorAddKernelPfS_S_i: .quad _Z30__device_stub__vectorAddKernelPfS_S_i .size _Z15vectorAddKernelPfS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z15vectorAddKernelPfS_S_i" .size .L__unnamed_1, 27 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z30__device_stub__vectorAddKernelPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z15vectorAddKernelPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
code for sm_80 Function : kernelShuffle .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */ /* 0x000fe200078e00ff */ /*0040*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */ /* 0x000fe2000800063f */ /*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e2a0000002100 */ /*0060*/ IMAD R13, R5.reuse, UR4, R2 ; /* 0x00000004050d7c24 */ /* 0x041fe2000f8e0202 */ /*0070*/ SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105057819 */ /* 0x000fe200000006ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc40000000a00 */ /*0090*/ IMAD.WIDE R6, R13.reuse, R0, c[0x0][0x170] ; /* 0x00005c000d067625 */ /* 0x040fe200078e0200 */ /*00a0*/ IADD3 R3, R13, c[0x0][0x0], RZ ; /* 0x000000000d037a10 */ /* 0x000fc60007ffe0ff */ /*00b0*/ IMAD.WIDE.U32 R4, R5, R0.reuse, c[0x0][0x178] ; /* 0x00005e0005047625 */ /* 0x080fe400078e0000 */ /*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*00d0*/ IMAD.WIDE R8, R3, R0, c[0x0][0x170] ; /* 0x00005c0003087625 */ /* 0x000fe400078e0200 */ /*00e0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */ /* 0x000ea8000c1e1900 */ /*00f0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */ /* 0x000ee8000c1e1900 */ /*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */ /* 0x000ee2000c1e1900 */ /*0110*/ IMAD.IADD R15, R6, 0x1, R11 ; /* 0x00000001060f7824 */ /* 0x004fe200078e020b */ /*0120*/ IADD3 R17, R8, R17, RZ ; /* 0x0000001108117210 */ /* 0x008fc80007ffe0ff */ /*0130*/ STS [R2.X4], R15 ; /* 0x0000000f02007388 */ /* 0x000fe80000004800 */ /*0140*/ STS [R2.X4+0x1000], R17 ; /* 0x0010001102007388 */ /* 0x000fe20000004800 */ /*0150*/ IMAD.WIDE R10, R13, R0, c[0x0][0x160] ; /* 0x000058000d0a7625 */ /* 0x000fc600078e0200 */ /*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0170*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */ /* 0x000ea2000c1e1900 */ /*0180*/ LEA R8, P1, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003087a11 */ /* 0x000fe400078210ff */ /*0190*/ LOP3.LUT P0, RZ, R11, c[0x0][0x180], RZ, 0xc0, !PT ; /* 0x000060000bff7a12 */ /* 0x004fda000780c0ff */ /*01a0*/ @P0 LDS R4, [R2.X4] ; /* 0x0000000002040984 */ /* 0x000e280000004800 */ /*01b0*/ @!P0 LDS R6, [R2.X4] ; /* 0x0000000002068984 */ /* 0x000e620000004800 */ /*01c0*/ @P0 IADD3 R5, -R4, c[0x0][0x184], R13 ; /* 0x0000610004050a10 */ /* 0x001fe40007ffe10d */ /*01d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R3 ; /* 0x0000001fff047819 */ /* 0x000fe40000011403 */ /*01e0*/ @!P0 IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06058810 */ /* 0x002fe40007ffe0ff */ /*01f0*/ LEA.HI.X R9, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x0000590003097a11 */ /* 0x000fc600008f1404 */ /*0200*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */ /* 0x000fca00078e0200 */ /*0210*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */ /* 0x000fe8000c101904 */ /*0220*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */ /* 0x000ea4000c1e1900 */ /*0230*/ LOP3.LUT P0, RZ, R9, c[0x0][0x180], RZ, 0xc0, !PT ; /* 0x0000600009ff7a12 */ /* 0x004fda000780c0ff */ /*0240*/ @P0 LDS R6, [R2.X4+0x1000] ; /* 0x0010000002060984 */ /* 0x000e280000004800 */ /*0250*/ @!P0 LDS R10, [R2.X4+0x1000] ; /* 0x00100000020a8984 */ /* 0x000e620000004800 */ /*0260*/ @P0 IADD3 R7, -R6, c[0x0][0x184], R3 ; /* 0x0000610006070a10 */ /* 0x001fe40007ffe103 */ /*0270*/ @!P0 IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a078810 */ /* 0x002fca0007ffe0ff */ /*0280*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */ /* 0x000fca00078e0200 */ /*0290*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*02a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : kernelMain .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe200078e00ff */ /*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */ /* 0x000fe2000800063f */ /*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0070*/ IMAD R5, R7, UR5, R0 ; /* 0x0000000507057c24 */ /* 0x001fc8000f8e0200 */ /*0080*/ IMAD.WIDE.U32 R8, R5.reuse, R2, c[0x0][0x160] ; /* 0x0000580005087625 */ /* 0x040fe200078e0002 */ /*0090*/ IADD3 R3, R5, c[0x0][0x0], RZ ; /* 0x0000000005037a10 */ /* 0x000fca0007ffe0ff */ /*00a0*/ IMAD.WIDE.U32 R10, R3, R2, c[0x0][0x160] ; /* 0x00005800030a7625 */ /* 0x000fe200078e0002 */ /*00b0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */ /* 0x000eaa000c1e1900 */ /*00c0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */ /* 0x000ee2000c1e1900 */ /*00d0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe20003f45270 */ /*00e0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*00f0*/ LOP3.LUT P0, RZ, R8, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e0008ff7a12 */ /* 0x004fc8000780c0ff */ /*0100*/ SEL R13, RZ, 0x1, P0 ; /* 0x00000001ff0d7807 */ /* 0x000fe40000000000 */ /*0110*/ LOP3.LUT P1, RZ, R10, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e000aff7a12 */ /* 0x008fe4000782c0ff */ /*0120*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x2, PT ; /* 0x000000020000780c */ /* 0x040fe20003f06070 */ /*0130*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */ /* 0x000fe20000004800 */ /*0140*/ SEL R15, RZ, 0x1, P1 ; /* 0x00000001ff0f7807 */ /* 0x000fe40000800000 */ /*0150*/ ISETP.GE.U32.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */ /* 0x000fc60003f26070 */ /*0160*/ STS [R0.X4+0x100c], R15 ; /* 0x00100c0f00007388 */ /* 0x000fe80000004800 */ /*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0180*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */ /* 0x000fe80000004800 */ /*0190*/ @P2 LDS R4, [R0.X4+-0x4] ; /* 0xfffffc0000042984 */ /* 0x000e280000004800 */ /*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*01b0*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*01c0*/ @P2 IMAD.IADD R17, R17, 0x1, R4 ; /* 0x0000000111112824 */ /* 0x001fc600078e0204 */ /*01d0*/ @P2 LDS R4, [R0.X4+0x1008] ; /* 0x0010080000042984 */ /* 0x000e280000004800 */ /*01e0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */ /* 0x000fe80000004800 */ /*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0200*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0210*/ @P0 LDS R6, [R0.X4+-0x8] ; /* 0xfffff80000060984 */ /* 0x000e620000004800 */ /*0220*/ @P2 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109092824 */ /* 0x001fca00078e0204 */ /*0230*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0250*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0260*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0270*/ @P0 LDS R4, [R0.X4+0x1004] ; /* 0x0010040000040984 */ /* 0x000e280000004800 */ /*0280*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*02a0*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*02b0*/ @P1 LDS R6, [R0.X4+-0x10] ; /* 0xfffff00000061984 */ /* 0x000e620000004800 */ /*02c0*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*02d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */ /* 0x000fc80003f06070 */ /*02e0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0300*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0310*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0320*/ @P1 LDS R4, [R0.X4+0xffc] ; /* 0x000ffc0000041984 */ /* 0x000e280000004800 */ /*0330*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0350*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0360*/ @P0 LDS R6, [R0.X4+-0x20] ; /* 0xffffe00000060984 */ /* 0x000e620000004800 */ /*0370*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*0380*/ ISETP.GE.U32.AND P1, PT, R0, 0x10, PT ; /* 0x000000100000780c */ /* 0x000fc80003f26070 */ /*0390*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*03b0*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*03c0*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*03d0*/ @P0 LDS R4, [R0.X4+0xfec] ; /* 0x000fec0000040984 */ /* 0x000e280000004800 */ /*03e0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0400*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*0410*/ @P1 LDS R6, [R0.X4+-0x40] ; /* 0xffffc00000061984 */ /* 0x000e620000004800 */ /*0420*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*0430*/ ISETP.GE.U32.AND P0, PT, R0, 0x20, PT ; /* 0x000000200000780c */ /* 0x000fc80003f06070 */ /*0440*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0460*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0470*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0480*/ @P1 LDS R4, [R0.X4+0xfcc] ; /* 0x000fcc0000041984 */ /* 0x000e280000004800 */ /*0490*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*04b0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*04c0*/ @P0 LDS R6, [R0.X4+-0x80] ; /* 0xffff800000060984 */ /* 0x000e620000004800 */ /*04d0*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*04e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x40, PT ; /* 0x000000400000780c */ /* 0x000fc80003f26070 */ /*04f0*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0510*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0520*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0530*/ @P0 LDS R4, [R0.X4+0xf8c] ; /* 0x000f8c0000040984 */ /* 0x000e280000004800 */ /*0540*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0560*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*0570*/ @P1 LDS R6, [R0.X4+-0x100] ; /* 0xffff000000061984 */ /* 0x000e620000004800 */ /*0580*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*0590*/ ISETP.GE.U32.AND P0, PT, R0, 0x80, PT ; /* 0x000000800000780c */ /* 0x000fc80003f06070 */ /*05a0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*05c0*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*05d0*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*05e0*/ @P1 LDS R4, [R0.X4+0xf0c] ; /* 0x000f0c0000041984 */ /* 0x000e280000004800 */ /*05f0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0610*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0620*/ @P0 LDS R6, [R0.X4+-0x200] ; /* 0xfffe000000060984 */ /* 0x000e620000004800 */ /*0630*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*0640*/ ISETP.GE.U32.AND P1, PT, R0, 0x100, PT ; /* 0x000001000000780c */ /* 0x000fc80003f26070 */ /*0650*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0670*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0680*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0690*/ @P0 LDS R4, [R0.X4+0xe0c] ; /* 0x000e0c0000040984 */ /* 0x000e280000004800 */ /*06a0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*06c0*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*06d0*/ @P1 LDS R6, [R0.X4+-0x400] ; /* 0xfffc000000061984 */ /* 0x000e620000004800 */ /*06e0*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*06f0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */ /* 0x000fc80003f06070 */ /*0700*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0720*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0730*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0740*/ @P1 LDS R4, [R0.X4+0xc0c] ; /* 0x000c0c0000041984 */ /* 0x000e280000004800 */ /*0750*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0770*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0780*/ @P0 LDS R6, [R0.X4+-0x800] ; /* 0xfff8000000060984 */ /* 0x000e620000004800 */ /*0790*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*07a0*/ ISETP.NE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fc4000bf25270 */ /*07b0*/ LEA R4, P2, R5.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */ /* 0x040fe400078410ff */ /*07c0*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x0001e40000004800 */ /*07d0*/ LEA.HI.X R5, R5, c[0x0][0x16c], RZ, 0x2, P2 ; /* 0x00005b0005057a11 */ /* 0x000fe400010f14ff */ /*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fe20000010000 */ /*07f0*/ IMAD.SHL.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097824 */ /* 0x001fca00078e00ff */ /*0800*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0810*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0820*/ @P0 LDS R8, [R0.X4+0x80c] ; /* 0x00080c0000080984 */ /* 0x000e220000004800 */ /*0830*/ LEA R6, P3, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */ /* 0x000fc600078610ff */ /*0840*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe20000004800 */ /*0850*/ LEA.HI.X R7, R3, c[0x0][0x16c], RZ, 0x2, P3 ; /* 0x00005b0003077a11 */ /* 0x000fe200018f14ff */ /*0860*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x170] ; /* 0x00005c0009027625 */ /* 0x000fe400078e0002 */ /*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0880*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000e620000004800 */ /*0890*/ @P0 IMAD.IADD R13, R13, 0x1, R8 ; /* 0x000000010d0d0824 */ /* 0x001fca00078e0208 */ /*08a0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x0001e80000004800 */ /*08b0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */ /* 0x0021e8000c101906 */ /*08c0*/ @!P1 STG.E [R2.64+0x4], R15 ; /* 0x0000040f02009986 */ /* 0x0001e8000c101906 */ /*08d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */ /* 0x0001e2000c101906 */ /*08e0*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*08f0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */ /* 0x000fe2000c101906 */ /*0900*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0910*/ BRA 0x910; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0920*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0930*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0940*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0950*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0960*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0970*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0980*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0990*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
.file "tmpxft_000a80b2_00000000-6_radixsort.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i .type _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i, @function _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i: .LFB2081: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq kernelMain(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2081: .size _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i .globl kernelMain .type kernelMain, @function kernelMain: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size kernelMain, .-kernelMain .globl _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii .type _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii, @function _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii: .LFB2083: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 168(%rsp), %rax subq %fs:40, %rax jne .L16 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq kernelShuffle(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii, .-_Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii .globl kernelShuffle .type kernelShuffle, @function kernelShuffle: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size kernelShuffle, .-kernelShuffle .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "kernelShuffle" .LC1: .string "kernelMain" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq kernelShuffle(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq kernelMain(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
#include <hip/hip_runtime.h> #include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected kernelMain .globl kernelMain .p2align 8 .type kernelMain,@function kernelMain: s_clause 0x2 s_load_b32 s5, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x0 s_load_b32 s4, s[0:1], 0x18 s_lshl_b32 s9, s15, 1 v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s5, 0xffff s_mov_b32 s5, 0 s_mul_i32 s10, s9, s8 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v1, s10, v0 .p2align 6 .LBB0_1: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_nc_u32_e32 v1, s8, v1 v_add_co_u32 v4, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo global_load_b32 v4, v[4:5], off v_add_nc_u32_e32 v5, s5, v3 s_addk_i32 s5, 0x100c s_cmpk_lg_i32 s5, 0x100c s_waitcnt vmcnt(0) v_and_b32_e32 v4, s4, v4 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v4 v_cndmask_b32_e64 v4, 0, 1, vcc_lo ds_store_b32 v5, v4 s_cbranch_scc0 .LBB0_1 v_lshlrev_b32_e32 v1, 2, v0 s_mov_b32 s2, 1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_set_inst_prefetch_distance 0x1 s_branch .LBB0_4 .p2align 6 .LBB0_3: s_lshl_b32 s3, s2, 1 s_cmpk_gt_u32 s2, 0x1ff s_mov_b32 s2, s3 s_cbranch_scc1 .LBB0_8 .LBB0_4: s_lshl_b32 s3, s2, 2 v_cmp_le_u32_e32 vcc_lo, s2, v0 v_subrev_nc_u32_e32 v2, s3, v1 s_mov_b32 s3, 0 s_branch .LBB0_6 .p2align 6 .LBB0_5: s_or_b32 exec_lo, exec_lo, s4 s_addk_i32 s3, 0x100c s_waitcnt lgkmcnt(0) s_cmpk_lg_i32 s3, 0x100c s_barrier buffer_gl0_inv ds_store_b32 v3, v4 s_cbranch_scc1 .LBB0_3 .LBB0_6: v_add_nc_u32_e32 v3, s3, v1 ds_load_b32 v4, v3 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_5 v_add_nc_u32_e32 v5, s3, v2 ds_load_b32 v5, v5 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v4, v5, v4 s_branch .LBB0_5 .LBB0_8: s_set_inst_prefetch_distance 0x2 s_load_b128 s[4:7], s[0:1], 0x8 s_add_i32 s0, s8, -1 v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s10, v0 v_cmp_eq_u32_e32 vcc_lo, s0, v0 v_lshlrev_b32_e32 v0, 2, v0 s_add_i32 s2, s9, 1 s_movk_i32 s1, 0xeff4 s_mov_b32 s3, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_10 .p2align 6 .LBB0_9: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, s8, v1 s_addk_i32 s1, 0x100c s_add_i32 s2, s2, 1 s_cmp_lg_u32 s1, 0 s_cbranch_scc1 .LBB0_12 .LBB0_10: v_add_nc_u32_e32 v3, s1, v0 v_lshlrev_b64 v[4:5], 2, v[1:2] ds_load_b32 v3, v3 offset:4108 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, s0, s4, v4 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s5, v5, s0 global_store_b32 v[4:5], v3, off s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB0_9 s_lshl_b64 s[10:11], s[2:3], 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s10, s6, s10 s_addc_u32 s11, s7, s11 global_store_b32 v2, v3, s[10:11] s_branch .LBB0_9 .LBB0_12: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel kernelMain .amdhsa_group_segment_fixed_size 8216 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size kernelMain, .Lfunc_end0-kernelMain .section .AMDGPU.csdata,"",@progbits .text .protected kernelShuffle .globl kernelShuffle .p2align 8 .type kernelShuffle,@function kernelShuffle: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 1 v_lshlrev_b32_e32 v3, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s3, 0xffff s_mov_b32 s3, 0 s_mul_i32 s9, s2, s8 s_lshl_b64 s[10:11], s[2:3], 2 v_add_nc_u32_e32 v1, s9, v0 s_add_u32 s6, s6, s10 s_addc_u32 s7, s7, s11 .p2align 6 .LBB1_1: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 s_load_b32 s2, s[6:7], 0x0 v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_nc_u32_e32 v1, s8, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v2, v[4:5], off v_add_nc_u32_e32 v4, s3, v3 s_addk_i32 s3, 0x1000 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmpk_lg_i32 s3, 0x1000 s_waitcnt vmcnt(0) lgkmcnt(0) v_add_nc_u32_e32 v2, s2, v2 ds_store_b32 v4, v2 s_cbranch_scc0 .LBB1_1 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x20 v_add_nc_u32_e32 v1, s9, v0 v_lshlrev_b32_e32 v0, 2, v0 s_mov_b32 s9, 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_add_u32 s2, s6, -4 s_addc_u32 s3, s7, -1 s_set_inst_prefetch_distance 0x1 s_branch .LBB1_4 .p2align 6 .LBB1_3: s_or_b32 exec_lo, exec_lo, s10 s_waitcnt lgkmcnt(0) v_ashrrev_i32_e32 v3, 31, v2 v_add_nc_u32_e32 v1, s8, v1 s_addk_i32 s9, 0x1000 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmpk_lg_i32 s9, 0x1000 v_lshlrev_b64 v[2:3], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo global_store_b32 v[2:3], v6, off s_cbranch_scc1 .LBB1_8 .LBB1_4: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v6, v[2:3], off v_add_nc_u32_e32 v3, s9, v0 s_waitcnt vmcnt(0) v_and_b32_e32 v2, s0, v6 v_cmp_ne_u32_e32 vcc_lo, 0, v2 s_and_saveexec_b32 s10, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s10, exec_lo, s10 s_cbranch_execz .LBB1_6 ds_load_b32 v2, v3 v_add_nc_u32_e32 v3, s1, v1 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_sub_nc_u32_e32 v2, v3, v2 .LBB1_6: s_or_saveexec_b32 s10, s10 v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7 s_xor_b32 exec_lo, exec_lo, s10 s_cbranch_execz .LBB1_3 ds_load_b32 v2, v3 v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 s_branch .LBB1_3 .LBB1_8: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel kernelShuffle .amdhsa_group_segment_fixed_size 8192 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size kernelShuffle, .Lfunc_end1-kernelShuffle .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 8216 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: kernelMain .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: kernelMain.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 8192 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: kernelShuffle .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: kernelShuffle.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <cstdio> #include <climits> #define SERIAL_SCALE 1 #define SERIAL_PART (1<<SERIAL_SCALE) extern "C" { /** * @param input Cała tablica do posortowania * @param output Wynik: Wszystkie prefix sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30) */ __global__ void kernelMain(int *input, int *output, int *sumGlobal, int bitMask){ //int thid = (blockIdx.x * blockDim.x) + threadIdx.x; // Globalny ID wątku (mało przydatne) __shared__ int mem[SERIAL_PART][1024+3]; int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków for(int i=0;i<SERIAL_PART;++i) { mem[i][threadIdx.x]= ((input[baseOffset+i*blockDim.x+threadIdx.x]&bitMask)==0); } __syncthreads(); for(int shift=1;shift<1024;shift*=2) { //scan for(int i=0;i<SERIAL_PART;++i) { int v=mem[i][threadIdx.x]; if(threadIdx.x>=shift) { v+=mem[i][threadIdx.x-shift]; } __syncthreads(); mem[i][threadIdx.x]=v; } } //__syncthreads(); for(int i=0;i<SERIAL_PART;++i) { output[baseOffset+i*blockDim.x+threadIdx.x]=mem[i][threadIdx.x]; if(threadIdx.x == blockDim.x-1) { sumGlobal[blockIdx.x * SERIAL_PART + i + 1] = mem[i][threadIdx.x]; } } } /** * @param input Wejściowa tablica liczb * @param output Wyjściowa tablica liczb * @param sumLocal Tablica prefix sum kolejnych bloków * @param sumGlobal Tablica prefix sum (zewnętrzna) ostatnich sum z kolejnych bloków * @param args args[0]=pozycja bitu (0..30), args[1]=pozycja pierwszej liczby z 1 w output * @param */ __global__ void kernelShuffle(int *input,int *output,int *sumLocal,int *sumGlobal,int bitMask,int sumLast) { int baseOffset=(blockIdx.x * blockDim.x)*SERIAL_PART; // Przesunięcie obecnego ciągu bloków __shared__ int sumGlobalS[SERIAL_PART][1024]; for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; sumGlobalS[i][threadIdx.x]=sumGlobal[blockIdx.x*SERIAL_PART+i]+sumLocal[in]; } __syncthreads(); for(int i=0;i<SERIAL_PART;++i) { int in=baseOffset+i*blockDim.x+threadIdx.x; if((input[in]&bitMask)==0) { //printf("%d -> [%d]\n",input[in],sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i]-1); output[sumGlobalS[i][threadIdx.x]-1]=input[in]; } else { //printf("%d -> [%d]\n",input[in],args[1]+in-(sumLocal[in]+sumGlobal[blockIdx.x*SERIAL_PART+i])); output[sumLast+in-(sumGlobalS[i][threadIdx.x])]=input[in]; } } } }
.text .file "radixsort.hip" .globl __device_stub__kernelMain # -- Begin function __device_stub__kernelMain .p2align 4, 0x90 .type __device_stub__kernelMain,@function __device_stub__kernelMain: # @__device_stub__kernelMain .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $kernelMain, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size __device_stub__kernelMain, .Lfunc_end0-__device_stub__kernelMain .cfi_endproc # -- End function .globl __device_stub__kernelShuffle # -- Begin function __device_stub__kernelShuffle .p2align 4, 0x90 .type __device_stub__kernelShuffle,@function __device_stub__kernelShuffle: # @__device_stub__kernelShuffle .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $kernelShuffle, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end1: .size __device_stub__kernelShuffle, .Lfunc_end1-__device_stub__kernelShuffle .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $kernelMain, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $kernelShuffle, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type kernelMain,@object # @kernelMain .section .rodata,"a",@progbits .globl kernelMain .p2align 3, 0x0 kernelMain: .quad __device_stub__kernelMain .size kernelMain, 8 .type kernelShuffle,@object # @kernelShuffle .globl kernelShuffle .p2align 3, 0x0 kernelShuffle: .quad __device_stub__kernelShuffle .size kernelShuffle, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "kernelMain" .size .L__unnamed_1, 11 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "kernelShuffle" .size .L__unnamed_2, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__kernelMain .addrsig_sym __device_stub__kernelShuffle .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym kernelMain .addrsig_sym kernelShuffle .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : kernelShuffle .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */ /* 0x000fe200078e00ff */ /*0040*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */ /* 0x000fe2000800063f */ /*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */ /* 0x000e2a0000002100 */ /*0060*/ IMAD R13, R5.reuse, UR4, R2 ; /* 0x00000004050d7c24 */ /* 0x041fe2000f8e0202 */ /*0070*/ SHF.L.U32 R5, R5, 0x1, RZ ; /* 0x0000000105057819 */ /* 0x000fe200000006ff */ /*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc40000000a00 */ /*0090*/ IMAD.WIDE R6, R13.reuse, R0, c[0x0][0x170] ; /* 0x00005c000d067625 */ /* 0x040fe200078e0200 */ /*00a0*/ IADD3 R3, R13, c[0x0][0x0], RZ ; /* 0x000000000d037a10 */ /* 0x000fc60007ffe0ff */ /*00b0*/ IMAD.WIDE.U32 R4, R5, R0.reuse, c[0x0][0x178] ; /* 0x00005e0005047625 */ /* 0x080fe400078e0000 */ /*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x000ea4000c1e1900 */ /*00d0*/ IMAD.WIDE R8, R3, R0, c[0x0][0x170] ; /* 0x00005c0003087625 */ /* 0x000fe400078e0200 */ /*00e0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */ /* 0x000ea8000c1e1900 */ /*00f0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */ /* 0x000ee8000c1e1900 */ /*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */ /* 0x000ee2000c1e1900 */ /*0110*/ IMAD.IADD R15, R6, 0x1, R11 ; /* 0x00000001060f7824 */ /* 0x004fe200078e020b */ /*0120*/ IADD3 R17, R8, R17, RZ ; /* 0x0000001108117210 */ /* 0x008fc80007ffe0ff */ /*0130*/ STS [R2.X4], R15 ; /* 0x0000000f02007388 */ /* 0x000fe80000004800 */ /*0140*/ STS [R2.X4+0x1000], R17 ; /* 0x0010001102007388 */ /* 0x000fe20000004800 */ /*0150*/ IMAD.WIDE R10, R13, R0, c[0x0][0x160] ; /* 0x000058000d0a7625 */ /* 0x000fc600078e0200 */ /*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0170*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */ /* 0x000ea2000c1e1900 */ /*0180*/ LEA R8, P1, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003087a11 */ /* 0x000fe400078210ff */ /*0190*/ LOP3.LUT P0, RZ, R11, c[0x0][0x180], RZ, 0xc0, !PT ; /* 0x000060000bff7a12 */ /* 0x004fda000780c0ff */ /*01a0*/ @P0 LDS R4, [R2.X4] ; /* 0x0000000002040984 */ /* 0x000e280000004800 */ /*01b0*/ @!P0 LDS R6, [R2.X4] ; /* 0x0000000002068984 */ /* 0x000e620000004800 */ /*01c0*/ @P0 IADD3 R5, -R4, c[0x0][0x184], R13 ; /* 0x0000610004050a10 */ /* 0x001fe40007ffe10d */ /*01d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R3 ; /* 0x0000001fff047819 */ /* 0x000fe40000011403 */ /*01e0*/ @!P0 IADD3 R5, R6, -0x1, RZ ; /* 0xffffffff06058810 */ /* 0x002fe40007ffe0ff */ /*01f0*/ LEA.HI.X R9, R3, c[0x0][0x164], R4, 0x2, P1 ; /* 0x0000590003097a11 */ /* 0x000fc600008f1404 */ /*0200*/ IMAD.WIDE R4, R5, R0, c[0x0][0x168] ; /* 0x00005a0005047625 */ /* 0x000fca00078e0200 */ /*0210*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */ /* 0x000fe8000c101904 */ /*0220*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */ /* 0x000ea4000c1e1900 */ /*0230*/ LOP3.LUT P0, RZ, R9, c[0x0][0x180], RZ, 0xc0, !PT ; /* 0x0000600009ff7a12 */ /* 0x004fda000780c0ff */ /*0240*/ @P0 LDS R6, [R2.X4+0x1000] ; /* 0x0010000002060984 */ /* 0x000e280000004800 */ /*0250*/ @!P0 LDS R10, [R2.X4+0x1000] ; /* 0x00100000020a8984 */ /* 0x000e620000004800 */ /*0260*/ @P0 IADD3 R7, -R6, c[0x0][0x184], R3 ; /* 0x0000610006070a10 */ /* 0x001fe40007ffe103 */ /*0270*/ @!P0 IADD3 R7, R10, -0x1, RZ ; /* 0xffffffff0a078810 */ /* 0x002fca0007ffe0ff */ /*0280*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */ /* 0x000fca00078e0200 */ /*0290*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*02a0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*02c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*02f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0300*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0310*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0320*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0330*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0340*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0350*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0360*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0370*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : kernelMain .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */ /* 0x000e220000002500 */ /*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */ /* 0x000fe20000000800 */ /*0030*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */ /* 0x000fe200078e00ff */ /*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */ /* 0x000fe2000800063f */ /*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */ /* 0x000fc80000000a00 */ /*0070*/ IMAD R5, R7, UR5, R0 ; /* 0x0000000507057c24 */ /* 0x001fc8000f8e0200 */ /*0080*/ IMAD.WIDE.U32 R8, R5.reuse, R2, c[0x0][0x160] ; /* 0x0000580005087625 */ /* 0x040fe200078e0002 */ /*0090*/ IADD3 R3, R5, c[0x0][0x0], RZ ; /* 0x0000000005037a10 */ /* 0x000fca0007ffe0ff */ /*00a0*/ IMAD.WIDE.U32 R10, R3, R2, c[0x0][0x160] ; /* 0x00005800030a7625 */ /* 0x000fe200078e0002 */ /*00b0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */ /* 0x000eaa000c1e1900 */ /*00c0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */ /* 0x000ee2000c1e1900 */ /*00d0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */ /* 0x000fe20003f45270 */ /*00e0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */ /* 0x000fe2000fffe03f */ /*00f0*/ LOP3.LUT P0, RZ, R8, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e0008ff7a12 */ /* 0x004fc8000780c0ff */ /*0100*/ SEL R13, RZ, 0x1, P0 ; /* 0x00000001ff0d7807 */ /* 0x000fe40000000000 */ /*0110*/ LOP3.LUT P1, RZ, R10, c[0x0][0x178], RZ, 0xc0, !PT ; /* 0x00005e000aff7a12 */ /* 0x008fe4000782c0ff */ /*0120*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x2, PT ; /* 0x000000020000780c */ /* 0x040fe20003f06070 */ /*0130*/ STS [R0.X4], R13 ; /* 0x0000000d00007388 */ /* 0x000fe20000004800 */ /*0140*/ SEL R15, RZ, 0x1, P1 ; /* 0x00000001ff0f7807 */ /* 0x000fe40000800000 */ /*0150*/ ISETP.GE.U32.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */ /* 0x000fc60003f26070 */ /*0160*/ STS [R0.X4+0x100c], R15 ; /* 0x00100c0f00007388 */ /* 0x000fe80000004800 */ /*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0180*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */ /* 0x000fe80000004800 */ /*0190*/ @P2 LDS R4, [R0.X4+-0x4] ; /* 0xfffffc0000042984 */ /* 0x000e280000004800 */ /*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*01b0*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*01c0*/ @P2 IMAD.IADD R17, R17, 0x1, R4 ; /* 0x0000000111112824 */ /* 0x001fc600078e0204 */ /*01d0*/ @P2 LDS R4, [R0.X4+0x1008] ; /* 0x0010080000042984 */ /* 0x000e280000004800 */ /*01e0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */ /* 0x000fe80000004800 */ /*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0200*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0210*/ @P0 LDS R6, [R0.X4+-0x8] ; /* 0xfffff80000060984 */ /* 0x000e620000004800 */ /*0220*/ @P2 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109092824 */ /* 0x001fca00078e0204 */ /*0230*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0250*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0260*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0270*/ @P0 LDS R4, [R0.X4+0x1004] ; /* 0x0010040000040984 */ /* 0x000e280000004800 */ /*0280*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*02a0*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*02b0*/ @P1 LDS R6, [R0.X4+-0x10] ; /* 0xfffff00000061984 */ /* 0x000e620000004800 */ /*02c0*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*02d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */ /* 0x000fc80003f06070 */ /*02e0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0300*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0310*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0320*/ @P1 LDS R4, [R0.X4+0xffc] ; /* 0x000ffc0000041984 */ /* 0x000e280000004800 */ /*0330*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0350*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0360*/ @P0 LDS R6, [R0.X4+-0x20] ; /* 0xffffe00000060984 */ /* 0x000e620000004800 */ /*0370*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*0380*/ ISETP.GE.U32.AND P1, PT, R0, 0x10, PT ; /* 0x000000100000780c */ /* 0x000fc80003f26070 */ /*0390*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*03b0*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*03c0*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*03d0*/ @P0 LDS R4, [R0.X4+0xfec] ; /* 0x000fec0000040984 */ /* 0x000e280000004800 */ /*03e0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0400*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*0410*/ @P1 LDS R6, [R0.X4+-0x40] ; /* 0xffffc00000061984 */ /* 0x000e620000004800 */ /*0420*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*0430*/ ISETP.GE.U32.AND P0, PT, R0, 0x20, PT ; /* 0x000000200000780c */ /* 0x000fc80003f06070 */ /*0440*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0460*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0470*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0480*/ @P1 LDS R4, [R0.X4+0xfcc] ; /* 0x000fcc0000041984 */ /* 0x000e280000004800 */ /*0490*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*04b0*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*04c0*/ @P0 LDS R6, [R0.X4+-0x80] ; /* 0xffff800000060984 */ /* 0x000e620000004800 */ /*04d0*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*04e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x40, PT ; /* 0x000000400000780c */ /* 0x000fc80003f26070 */ /*04f0*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0510*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0520*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0530*/ @P0 LDS R4, [R0.X4+0xf8c] ; /* 0x000f8c0000040984 */ /* 0x000e280000004800 */ /*0540*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0560*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*0570*/ @P1 LDS R6, [R0.X4+-0x100] ; /* 0xffff000000061984 */ /* 0x000e620000004800 */ /*0580*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*0590*/ ISETP.GE.U32.AND P0, PT, R0, 0x80, PT ; /* 0x000000800000780c */ /* 0x000fc80003f06070 */ /*05a0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*05c0*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*05d0*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*05e0*/ @P1 LDS R4, [R0.X4+0xf0c] ; /* 0x000f0c0000041984 */ /* 0x000e280000004800 */ /*05f0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0610*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0620*/ @P0 LDS R6, [R0.X4+-0x200] ; /* 0xfffe000000060984 */ /* 0x000e620000004800 */ /*0630*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*0640*/ ISETP.GE.U32.AND P1, PT, R0, 0x100, PT ; /* 0x000001000000780c */ /* 0x000fc80003f26070 */ /*0650*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x000fe80000004800 */ /*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0670*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0680*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0690*/ @P0 LDS R4, [R0.X4+0xe0c] ; /* 0x000e0c0000040984 */ /* 0x000e280000004800 */ /*06a0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe80000004800 */ /*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*06c0*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000fe80000004800 */ /*06d0*/ @P1 LDS R6, [R0.X4+-0x400] ; /* 0xfffc000000061984 */ /* 0x000e620000004800 */ /*06e0*/ @P0 IMAD.IADD R13, R13, 0x1, R4 ; /* 0x000000010d0d0824 */ /* 0x001fe200078e0204 */ /*06f0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */ /* 0x000fc80003f06070 */ /*0700*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x000fe80000004800 */ /*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0720*/ LDS R9, [R0.X4+0x100c] ; /* 0x00100c0000097984 */ /* 0x000fe20000004800 */ /*0730*/ @P1 IMAD.IADD R15, R15, 0x1, R6 ; /* 0x000000010f0f1824 */ /* 0x002fc600078e0206 */ /*0740*/ @P1 LDS R4, [R0.X4+0xc0c] ; /* 0x000c0c0000041984 */ /* 0x000e280000004800 */ /*0750*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */ /* 0x000fe80000004800 */ /*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0770*/ LDS R11, [R0.X4] ; /* 0x00000000000b7984 */ /* 0x000fe80000004800 */ /*0780*/ @P0 LDS R6, [R0.X4+-0x800] ; /* 0xfff8000000060984 */ /* 0x000e620000004800 */ /*0790*/ @P1 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109091824 */ /* 0x001fe200078e0204 */ /*07a0*/ ISETP.NE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */ /* 0x000fc4000bf25270 */ /*07b0*/ LEA R4, P2, R5.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */ /* 0x040fe400078410ff */ /*07c0*/ STS [R0.X4+0x100c], R9 ; /* 0x00100c0900007388 */ /* 0x0001e40000004800 */ /*07d0*/ LEA.HI.X R5, R5, c[0x0][0x16c], RZ, 0x2, P2 ; /* 0x00005b0005057a11 */ /* 0x000fe400010f14ff */ /*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fe20000010000 */ /*07f0*/ IMAD.SHL.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097824 */ /* 0x001fca00078e00ff */ /*0800*/ LDS R13, [R0.X4+0x100c] ; /* 0x00100c00000d7984 */ /* 0x000fe20000004800 */ /*0810*/ @P0 IADD3 R11, R11, R6, RZ ; /* 0x000000060b0b0210 */ /* 0x002fc60007ffe0ff */ /*0820*/ @P0 LDS R8, [R0.X4+0x80c] ; /* 0x00080c0000080984 */ /* 0x000e220000004800 */ /*0830*/ LEA R6, P3, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */ /* 0x000fc600078610ff */ /*0840*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */ /* 0x000fe20000004800 */ /*0850*/ LEA.HI.X R7, R3, c[0x0][0x16c], RZ, 0x2, P3 ; /* 0x00005b0003077a11 */ /* 0x000fe200018f14ff */ /*0860*/ IMAD.WIDE.U32 R2, R9, R2, c[0x0][0x170] ; /* 0x00005c0009027625 */ /* 0x000fe400078e0002 */ /*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*0880*/ LDS R15, [R0.X4] ; /* 0x00000000000f7984 */ /* 0x000e620000004800 */ /*0890*/ @P0 IMAD.IADD R13, R13, 0x1, R8 ; /* 0x000000010d0d0824 */ /* 0x001fca00078e0208 */ /*08a0*/ STS [R0.X4+0x100c], R13 ; /* 0x00100c0d00007388 */ /* 0x0001e80000004800 */ /*08b0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */ /* 0x0021e8000c101906 */ /*08c0*/ @!P1 STG.E [R2.64+0x4], R15 ; /* 0x0000040f02009986 */ /* 0x0001e8000c101906 */ /*08d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */ /* 0x0001e2000c101906 */ /*08e0*/ @P1 EXIT ; /* 0x000000000000194d */ /* 0x000fea0003800000 */ /*08f0*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */ /* 0x000fe2000c101906 */ /*0900*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0910*/ BRA 0x910; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0920*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0930*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0940*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0950*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0960*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0970*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0980*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0990*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*09f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected kernelMain .globl kernelMain .p2align 8 .type kernelMain,@function kernelMain: s_clause 0x2 s_load_b32 s5, s[0:1], 0x2c s_load_b64 s[2:3], s[0:1], 0x0 s_load_b32 s4, s[0:1], 0x18 s_lshl_b32 s9, s15, 1 v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s5, 0xffff s_mov_b32 s5, 0 s_mul_i32 s10, s9, s8 s_delay_alu instid0(SALU_CYCLE_1) v_add_nc_u32_e32 v1, s10, v0 .p2align 6 .LBB0_1: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_nc_u32_e32 v1, s8, v1 v_add_co_u32 v4, vcc_lo, s2, v4 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo global_load_b32 v4, v[4:5], off v_add_nc_u32_e32 v5, s5, v3 s_addk_i32 s5, 0x100c s_cmpk_lg_i32 s5, 0x100c s_waitcnt vmcnt(0) v_and_b32_e32 v4, s4, v4 s_delay_alu instid0(VALU_DEP_1) v_cmp_eq_u32_e32 vcc_lo, 0, v4 v_cndmask_b32_e64 v4, 0, 1, vcc_lo ds_store_b32 v5, v4 s_cbranch_scc0 .LBB0_1 v_lshlrev_b32_e32 v1, 2, v0 s_mov_b32 s2, 1 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_set_inst_prefetch_distance 0x1 s_branch .LBB0_4 .p2align 6 .LBB0_3: s_lshl_b32 s3, s2, 1 s_cmpk_gt_u32 s2, 0x1ff s_mov_b32 s2, s3 s_cbranch_scc1 .LBB0_8 .LBB0_4: s_lshl_b32 s3, s2, 2 v_cmp_le_u32_e32 vcc_lo, s2, v0 v_subrev_nc_u32_e32 v2, s3, v1 s_mov_b32 s3, 0 s_branch .LBB0_6 .p2align 6 .LBB0_5: s_or_b32 exec_lo, exec_lo, s4 s_addk_i32 s3, 0x100c s_waitcnt lgkmcnt(0) s_cmpk_lg_i32 s3, 0x100c s_barrier buffer_gl0_inv ds_store_b32 v3, v4 s_cbranch_scc1 .LBB0_3 .LBB0_6: v_add_nc_u32_e32 v3, s3, v1 ds_load_b32 v4, v3 s_and_saveexec_b32 s4, vcc_lo s_cbranch_execz .LBB0_5 v_add_nc_u32_e32 v5, s3, v2 ds_load_b32 v5, v5 s_waitcnt lgkmcnt(0) v_add_nc_u32_e32 v4, v5, v4 s_branch .LBB0_5 .LBB0_8: s_set_inst_prefetch_distance 0x2 s_load_b128 s[4:7], s[0:1], 0x8 s_add_i32 s0, s8, -1 v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s10, v0 v_cmp_eq_u32_e32 vcc_lo, s0, v0 v_lshlrev_b32_e32 v0, 2, v0 s_add_i32 s2, s9, 1 s_movk_i32 s1, 0xeff4 s_mov_b32 s3, 0 s_set_inst_prefetch_distance 0x1 s_branch .LBB0_10 .p2align 6 .LBB0_9: s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v1, s8, v1 s_addk_i32 s1, 0x100c s_add_i32 s2, s2, 1 s_cmp_lg_u32 s1, 0 s_cbranch_scc1 .LBB0_12 .LBB0_10: v_add_nc_u32_e32 v3, s1, v0 v_lshlrev_b64 v[4:5], 2, v[1:2] ds_load_b32 v3, v3 offset:4108 s_waitcnt lgkmcnt(0) v_add_co_u32 v4, s0, s4, v4 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v5, s0, s5, v5, s0 global_store_b32 v[4:5], v3, off s_and_saveexec_b32 s0, vcc_lo s_cbranch_execz .LBB0_9 s_lshl_b64 s[10:11], s[2:3], 2 s_delay_alu instid0(SALU_CYCLE_1) s_add_u32 s10, s6, s10 s_addc_u32 s11, s7, s11 global_store_b32 v2, v3, s[10:11] s_branch .LBB0_9 .LBB0_12: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel kernelMain .amdhsa_group_segment_fixed_size 8216 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 6 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size kernelMain, .Lfunc_end0-kernelMain .section .AMDGPU.csdata,"",@progbits .text .protected kernelShuffle .globl kernelShuffle .p2align 8 .type kernelShuffle,@function kernelShuffle: s_clause 0x1 s_load_b32 s3, s[0:1], 0x34 s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 1 v_lshlrev_b32_e32 v3, 2, v0 s_waitcnt lgkmcnt(0) s_and_b32 s8, s3, 0xffff s_mov_b32 s3, 0 s_mul_i32 s9, s2, s8 s_lshl_b64 s[10:11], s[2:3], 2 v_add_nc_u32_e32 v1, s9, v0 s_add_u32 s6, s6, s10 s_addc_u32 s7, s7, s11 .p2align 6 .LBB1_1: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v2, 31, v1 s_load_b32 s2, s[6:7], 0x0 v_lshlrev_b64 v[4:5], 2, v[1:2] v_add_nc_u32_e32 v1, s8, v1 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v4, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo global_load_b32 v2, v[4:5], off v_add_nc_u32_e32 v4, s3, v3 s_addk_i32 s3, 0x1000 s_add_u32 s6, s6, 4 s_addc_u32 s7, s7, 0 s_cmpk_lg_i32 s3, 0x1000 s_waitcnt vmcnt(0) lgkmcnt(0) v_add_nc_u32_e32 v2, s2, v2 ds_store_b32 v4, v2 s_cbranch_scc0 .LBB1_1 s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x20 v_add_nc_u32_e32 v1, s9, v0 v_lshlrev_b32_e32 v0, 2, v0 s_mov_b32 s9, 0 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv s_add_u32 s2, s6, -4 s_addc_u32 s3, s7, -1 s_set_inst_prefetch_distance 0x1 s_branch .LBB1_4 .p2align 6 .LBB1_3: s_or_b32 exec_lo, exec_lo, s10 s_waitcnt lgkmcnt(0) v_ashrrev_i32_e32 v3, 31, v2 v_add_nc_u32_e32 v1, s8, v1 s_addk_i32 s9, 0x1000 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2) s_cmpk_lg_i32 s9, 0x1000 v_lshlrev_b64 v[2:3], 2, v[2:3] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo global_store_b32 v[2:3], v6, off s_cbranch_scc1 .LBB1_8 .LBB1_4: v_ashrrev_i32_e32 v2, 31, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[2:3], 2, v[1:2] v_add_co_u32 v2, vcc_lo, s4, v2 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo global_load_b32 v6, v[2:3], off v_add_nc_u32_e32 v3, s9, v0 s_waitcnt vmcnt(0) v_and_b32_e32 v2, s0, v6 v_cmp_ne_u32_e32 vcc_lo, 0, v2 s_and_saveexec_b32 s10, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s10, exec_lo, s10 s_cbranch_execz .LBB1_6 ds_load_b32 v2, v3 v_add_nc_u32_e32 v3, s1, v1 s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) v_sub_nc_u32_e32 v2, v3, v2 .LBB1_6: s_or_saveexec_b32 s10, s10 v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7 s_xor_b32 exec_lo, exec_lo, s10 s_cbranch_execz .LBB1_3 ds_load_b32 v2, v3 v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 s_branch .LBB1_3 .LBB1_8: s_set_inst_prefetch_distance 0x2 s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel kernelShuffle .amdhsa_group_segment_fixed_size 8192 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size kernelShuffle, .Lfunc_end1-kernelShuffle .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 8216 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: kernelMain .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: kernelMain.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 6 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 8192 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: kernelShuffle .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: kernelShuffle.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000a80b2_00000000-6_radixsort.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2059: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2059: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i .type _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i, @function _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i: .LFB2081: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq kernelMain(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2081: .size _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i .globl kernelMain .type kernelMain, @function kernelMain: .LFB2082: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z10kernelMainPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2082: .size kernelMain, .-kernelMain .globl _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii .type _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii, @function _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii: .LFB2083: .cfi_startproc endbr64 subq $184, %rsp .cfi_def_cfa_offset 192 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) movq %fs:40, %rax movq %rax, 168(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) leaq 8(%rsp), %rax movq %rax, 152(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 168(%rsp), %rax subq %fs:40, %rax jne .L16 addq $184, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 200 pushq 56(%rsp) .cfi_def_cfa_offset 208 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq kernelShuffle(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 192 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii, .-_Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii .globl kernelShuffle .type kernelShuffle, @function kernelShuffle: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z41__device_stub__Z13kernelShufflePiS_S_S_iiPiS_S_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size kernelShuffle, .-kernelShuffle .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "kernelShuffle" .LC1: .string "kernelMain" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq kernelShuffle(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq kernelMain(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "radixsort.hip" .globl __device_stub__kernelMain # -- Begin function __device_stub__kernelMain .p2align 4, 0x90 .type __device_stub__kernelMain,@function __device_stub__kernelMain: # @__device_stub__kernelMain .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $kernelMain, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size __device_stub__kernelMain, .Lfunc_end0-__device_stub__kernelMain .cfi_endproc # -- End function .globl __device_stub__kernelShuffle # -- Begin function __device_stub__kernelShuffle .p2align 4, 0x90 .type __device_stub__kernelShuffle,@function __device_stub__kernelShuffle: # @__device_stub__kernelShuffle .cfi_startproc # %bb.0: subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 12(%rsp) movl %r9d, 8(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $kernelShuffle, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $168, %rsp .cfi_adjust_cfa_offset -168 retq .Lfunc_end1: .size __device_stub__kernelShuffle, .Lfunc_end1-__device_stub__kernelShuffle .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $kernelMain, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $kernelShuffle, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type kernelMain,@object # @kernelMain .section .rodata,"a",@progbits .globl kernelMain .p2align 3, 0x0 kernelMain: .quad __device_stub__kernelMain .size kernelMain, 8 .type kernelShuffle,@object # @kernelShuffle .globl kernelShuffle .p2align 3, 0x0 kernelShuffle: .quad __device_stub__kernelShuffle .size kernelShuffle, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "kernelMain" .size .L__unnamed_1, 11 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "kernelShuffle" .size .L__unnamed_2, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __device_stub__kernelMain .addrsig_sym __device_stub__kernelShuffle .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym kernelMain .addrsig_sym kernelShuffle .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<cuda.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince cudaError_t error = cudaSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = cudaMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = cudaMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = cudaMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } cudaMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), cudaMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); cudaMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), cudaMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); cudaFree(d_m1); cudaFree(d_m2); cudaFree(d_m3); return 0; }
code for sm_80 Function : _Z21multiplicationKernellPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e280000002100 */ /*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e680000002600 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e620000002200 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0205 */ /*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */ /* 0x002fca00078e0202 */ /*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */ /* 0x000fe20000000f00 */ /*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */ /* 0x000fe200000001ff */ /*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */ /* 0x000fe200078e02ff */ /*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */ /* 0x000fda0003f06270 */ /*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */ /* 0x000fea0003800000 */ /*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */ /* 0x040fe40007ffe0ff */ /*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */ /* 0x000fe400078ec0ff */ /*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */ /* 0x000fe40003f06070 */ /*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fe40000000f00 */ /*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */ /* 0x000fd20000000f00 */ /*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */ /* 0x000fea0003800000 */ /*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */ /* 0x000fe20007ffe1ff */ /*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */ /* 0x000fe200000001ff */ /*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */ /* 0x000fe200000001ff */ /*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe40003f04270 */ /*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fca0000000f00 */ /*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */ /* 0x000fcc00078e0219 */ /*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */ /* 0x000fea0003800000 */ /*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe40003f24270 */ /*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */ /* 0x000fea0003800000 */ /*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */ /* 0x000fe20008000f00 */ /*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */ /* 0x0000a2000c1e1900 */ /*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */ /* 0x000fca0008000f00 */ /*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */ /* 0x000fca00078e020c */ /*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */ /* 0x000ea2000c1e1900 */ /*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */ /* 0x000fc600078e0218 */ /*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */ /* 0x000ee6000c1e1900 */ /*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */ /* 0x040fe200078e020a */ /*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */ /* 0x0002e8000c1e1900 */ /*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */ /* 0x000f22000c1e1900 */ /*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */ /* 0x000fc600078e0212 */ /*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x000b26000c1e1900 */ /*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */ /* 0x040fe200078e020e */ /*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */ /* 0x000128000c1e1900 */ /*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */ /* 0x000f28000c1e1900 */ /*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */ /* 0x020f22000c1e1900 */ /*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */ /* 0x001fc600078e0214 */ /*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */ /* 0x000166000c1e1900 */ /*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */ /* 0x040fe200078e020e */ /*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */ /* 0x002f62000c1e1900 */ /*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */ /* 0x000fc600078e0216 */ /*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */ /* 0x000368000c1e1900 */ /*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */ /* 0x001f62000c1e1900 */ /*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */ /* 0x004fc6000000001c */ /*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */ /* 0x000ea8000c1e1900 */ /*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */ /* 0x0000a2000c1e1900 */ /*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */ /* 0x000fc800078e0218 */ /*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */ /* 0x008fe4000000001d */ /*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */ /* 0x000fe400078e020e */ /*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x0006a4000c1e1900 */ /*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */ /* 0x010fe4000000001d */ /*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */ /* 0x000fe400078e0210 */ /*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x0008a4000c1e1900 */ /*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */ /* 0x000fc4000000001d */ /*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */ /* 0x042fe200078e0212 */ /*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */ /* 0x000ea8000c1e1900 */ /*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */ /* 0x001fc600078e0216 */ /*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x0000a2000c1e1900 */ /*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */ /* 0x020fc6000000001a */ /*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */ /* 0x000f62000c1e1900 */ /*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */ /* 0x000fe40000000009 */ /*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */ /* 0x000fe200078e0218 */ /*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */ /* 0x000368000c1e1900 */ /*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */ /* 0x010f22000c1e1900 */ /*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */ /* 0x000fc6000000000b */ /*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */ /* 0x008722000c1e1900 */ /*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */ /* 0x000fc600078e0208 */ /*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */ /* 0x001128000c1e1900 */ /*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */ /* 0x002f28000c1e1900 */ /*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */ /* 0x008ee8000c1e1900 */ /*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */ /* 0x000ee8000c1e1900 */ /*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */ /* 0x001ee2000c1e1900 */ /*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */ /* 0x004fc60000000015 */ /*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */ /* 0x000ea2000c1e1900 */ /*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */ /* 0x000fca00078e020a */ /*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */ /* 0x000ea2000c1e1900 */ /*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */ /* 0x000fc80007ffe0ff */ /*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe20003f24270 */ /*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */ /* 0x000fc80000000009 */ /*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */ /* 0x000fc80000000007 */ /*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */ /* 0x020fc80000000007 */ /*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */ /* 0x010fe20000000007 */ /*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff1e03f */ /*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */ /* 0x000fc60007ffe0ff */ /*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */ /* 0x008fc80000000007 */ /*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */ /* 0x004fc80000000007 */ /*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */ /* 0x000fe4000000001c */ /*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */ /* 0x000fc800078e0214 */ /*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */ /* 0x000fe2000000001c */ /*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */ /* 0x000fea000383ffff */ /*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */ /* 0x000fda0003f24270 */ /*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */ /* 0x000fea0003800000 */ /*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */ /* 0x000fe200078e0218 */ /*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */ /* 0x0000a2000c1e1900 */ /*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fc60008000f00 */ /*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */ /* 0x040fe200078e0210 */ /*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */ /* 0x0002e6000c1e1900 */ /*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */ /* 0x000fe200078e0208 */ /*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */ /* 0x000966000c1e1900 */ /*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */ /* 0x040fe200078e020c */ /*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */ /* 0x000ea8000c1e1900 */ /*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */ /* 0x000ee2000c1e1900 */ /*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */ /* 0x000fc600078e020e */ /*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */ /* 0x000f66000c1e1900 */ /*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */ /* 0x042fe200078e020a */ /*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000368000c1e1900 */ /*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */ /* 0x000f62000c1e1900 */ /*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */ /* 0x000fc600078e0210 */ /*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */ /* 0x000368000c1e1900 */ /*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */ /* 0x001f62000c1e1900 */ /*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */ /* 0x010fc600078e0212 */ /*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x000f28000c1e1900 */ /*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */ /* 0x000f28000c1e1900 */ /*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */ /* 0x000128000c1e1900 */ /*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */ /* 0x002f28000c1e1900 */ /*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */ /* 0x000f28000c1e1900 */ /*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */ /* 0x001f22000c1e1900 */ /*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */ /* 0x000fe2000ff1e03f */ /*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */ /* 0x000fe40007ffe0ff */ /*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */ /* 0x000fe20007ffe0ff */ /*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */ /* 0x004fc8000000001c */ /*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */ /* 0x008fc80000000007 */ /*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */ /* 0x020fc80000000007 */ /*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */ /* 0x000fc80000000007 */ /*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */ /* 0x000fc80000000007 */ /*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */ /* 0x010fc80000000007 */ /*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */ /* 0x000fe40000000007 */ /*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */ /* 0x000fc800078e020c */ /*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */ /* 0x000fe40000000007 */ /*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0000705670 */ /*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */ /* 0x000fea0003800000 */ /*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */ /* 0x000fe200078e0218 */ /*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fe20008000f00 */ /*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */ /* 0x000ea8000c1e1900 */ /*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */ /* 0x000fc800078e0208 */ /*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */ /* 0x040fe200078e020e */ /*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea8000c1e1900 */ /*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000ee2000c1e1900 */ /*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */ /* 0x000fc600078e020c */ /*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */ /* 0x000ee8000c1e1900 */ /*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x000f28000c1e1900 */ /*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */ /* 0x000f28000c1e1900 */ /*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */ /* 0x000f68000c1e1900 */ /*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */ /* 0x000f62000c1e1900 */ /*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */ /* 0x000fc80007ffe0ff */ /*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe20003f05270 */ /*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */ /* 0x000fe2000ff1e03f */ /*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */ /* 0x000fc60007ffe0ff */ /*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */ /* 0x004fc8000000001c */ /*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */ /* 0x008fe40000000007 */ /*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */ /* 0x000fc800078e020a */ /*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */ /* 0x010fc80000000007 */ /*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */ /* 0x020fe20000000007 */ /*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */ /* 0x000fea000383ffff */ /*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f05270 */ /*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */ /* 0x000fea0003800000 */ /*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */ /* 0x000fe20007ffe0ff */ /*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */ /* 0x000fd000078e0200 */ /*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fc800078e0209 */ /*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */ /* 0x000fca00078e0209 */ /*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */ /* 0x0000a8000c1e1900 */ /*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */ /* 0x0002a2000c1e1900 */ /*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */ /* 0x000fc80007ffe0ff */ /*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */ /* 0x001fe200078e0208 */ /*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x002fc80007f3e0ff */ /*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x000fe20000ffe4ff */ /*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */ /* 0x004fcc000000001c */ /*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */ /* 0x000fea000383ffff */ /*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */ /* 0x000fe40007ffe0ff */ /*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fca0000000f00 */ /*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */ /* 0x000fca00078e0202 */ /*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */ /* 0x000fe2000c101904 */ /*0c40*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0c60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ca0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ce0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<cuda.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince cudaError_t error = cudaSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = cudaMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = cudaMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = cudaMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } cudaMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), cudaMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); cudaMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), cudaMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); cudaFree(d_m1); cudaFree(d_m2); cudaFree(d_m3); return 0; }
.file "tmpxft_001966b6_00000000-6_MatrizCuda.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%f" .text .globl _Z8toMatrixPfP8_IO_FILEii .type _Z8toMatrixPfP8_IO_FILEii, @function _Z8toMatrixPfP8_IO_FILEii: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, 8(%rsp) movq %rsi, %r12 movl %edx, 4(%rsp) testl %edx, %edx jle .L4 movl %ecx, %r14d movl $0, (%rsp) movl $0, %r15d leaq .LC0(%rip), %r13 jmp .L5 .L7: movslq (%rsp), %rdx movq 8(%rsp), %rcx leaq (%rcx,%rdx,4), %rbx movslq %r14d, %rax addq %rdx, %rax leaq (%rcx,%rax,4), %rbp .L6: movq %rbx, %rdx movq %r13, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L6 .L8: addl $1, %r15d addl %r14d, (%rsp) cmpl %r15d, 4(%rsp) je .L4 .L5: testl %r14d, %r14d jg .L7 jmp .L8 .L4: movq %r12, %rdi call fclose@PLT addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z8toMatrixPfP8_IO_FILEii, .-_Z8toMatrixPfP8_IO_FILEii .section .rodata.str1.1 .LC1: .string "----------MATRIX----------\n" .LC2: .string "[%f]" .LC3: .string "\n" .text .globl _Z5printPfii .type _Z5printPfii, @function _Z5printPfii: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, 16(%rsp) movl %esi, %ebx movl %esi, 12(%rsp) movl %edx, %r15d leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %ebx, %ebx jle .L11 movl $0, %r14d movl $0, %r13d movslq %r15d, %rax movq %rax, 24(%rsp) leaq .LC2(%rip), %r12 jmp .L13 .L15: movslq %r14d, %rax movq 16(%rsp), %rcx leaq (%rcx,%rax,4), %rbx movq 24(%rsp), %rdx addq %rdx, %rax leaq (%rcx,%rax,4), %rbp .L14: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L14 .L16: leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %r13d addl %r15d, %r14d cmpl %r13d, 12(%rsp) je .L11 .L13: testl %r15d, %r15d jg .L15 jmp .L16 .L11: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z5printPfii, .-_Z5printPfii .globl _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii .type _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii, @function _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 136(%rsp), %rax subq %fs:40, %rax jne .L24 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z21multiplicationKernellPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii, .-_Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii .globl _Z21multiplicationKernellPfS_S_ii .type _Z21multiplicationKernellPfS_S_ii, @function _Z21multiplicationKernellPfS_S_ii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z21multiplicationKernellPfS_S_ii, .-_Z21multiplicationKernellPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string "Error, no se encontraron todos los parametros necesarios." .section .rodata.str1.1 .LC5: .string "r" .LC6: .string "%d" .section .rodata.str1.8 .align 8 .LC7: .string "Error los tama\303\261os de las matrices no son compatibles." .align 8 .LC9: .string "Imposible asignar memoria para d_m1" .align 8 .LC10: .string "Imposible asignar memoria para d_m2" .align 8 .LC11: .string "Imposible asignar memoria para d_m3" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax cmpl $3, %edi je .L28 leaq .LC4(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %eax .L27: movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L37 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L28: .cfi_restore_state movq %rsi, %rbx movq 8(%rsi), %rdi leaq .LC5(%rip), %rbp movq %rbp, %rsi call fopen@PLT movq %rax, %r12 movq 16(%rbx), %rdi movq %rbp, %rsi call fopen@PLT movq %rax, %rbp leaq 24(%rsp), %rdx leaq .LC6(%rip), %rbx movq %rbx, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 32(%rsp), %rdx movq %rbx, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 28(%rsp), %rdx movq %rbx, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 36(%rsp), %rdx movq %rbx, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl 24(%rsp), %r14d movl 32(%rsp), %r15d movl %r14d, %edi imull %r15d, %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, %r13 movl 36(%rsp), %ebx movl %ebx, %edi imull 28(%rsp), %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, (%rsp) imull %r14d, %ebx movslq %ebx, %rdi salq $2, %rdi call malloc@PLT movq %rax, %rbx movl %r15d, %ecx movl %r14d, %edx movq %r12, %rsi movq %r13, %rdi call _Z8toMatrixPfP8_IO_FILEii movl 36(%rsp), %ecx movl 28(%rsp), %edx movq %rbp, %rsi movq (%rsp), %r15 movq %r15, %rdi call _Z8toMatrixPfP8_IO_FILEii movl 32(%rsp), %edx movl 24(%rsp), %esi movq %r13, %rdi call _Z5printPfii movl 36(%rsp), %edx movl 28(%rsp), %esi movq %r15, %rdi call _Z5printPfii movl 24(%rsp), %ebp cmpl 36(%rsp), %ebp je .L30 leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L30: movl $32, 64(%rsp) movl $32, 68(%rsp) movl $1, 72(%rsp) pxor %xmm0, %xmm0 cvtsi2ssl %ebp, %xmm0 mulss .LC8(%rip), %xmm0 call ceilf@PLT movss %xmm0, 12(%rsp) movl 32(%rsp), %r12d pxor %xmm0, %xmm0 cvtsi2ssl %r12d, %xmm0 mulss .LC8(%rip), %xmm0 call ceilf@PLT cvttss2siq %xmm0, %rax movl %eax, 76(%rsp) cvttss2siq 12(%rsp), %rax movl %eax, 80(%rsp) movl $1, 84(%rsp) imull %r12d, %ebp movslq %ebp, %rsi salq $2, %rsi leaq 40(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax jne .L38 movl 28(%rsp), %esi imull 36(%rsp), %esi movslq %esi, %rsi salq $2, %rsi leaq 48(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax jne .L39 leaq 56(%rsp), %rdi movl $0, %esi call cudaMalloc@PLT testl %eax, %eax jne .L40 movl 24(%rsp), %edx imull 32(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq %r13, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl 28(%rsp), %edx imull 36(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq (%rsp), %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx movq 76(%rsp), %rdi movl 84(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L41 .L34: movl 24(%rsp), %edx imull 36(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $2, %ecx movq 56(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movl 36(%rsp), %edx movl 24(%rsp), %esi movq %rbx, %rdi call _Z5printPfii movq %r13, %rdi call free@PLT movq (%rsp), %rdi call free@PLT movq %rbx, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movl $0, %eax jmp .L27 .L38: leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L39: leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L40: leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L41: movl 36(%rsp), %r8d movl 24(%rsp), %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii jmp .L34 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.8 .align 8 .LC12: .string "_Z21multiplicationKernellPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z21multiplicationKernellPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC8: .long 1023410176 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<cuda.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince cudaError_t error = cudaSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = cudaMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = cudaMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = cudaMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != cudaSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } cudaMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), cudaMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); cudaMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), cudaMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); cudaFree(d_m1); cudaFree(d_m2); cudaFree(d_m3); return 0; }
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<hip/hip_runtime.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince hipError_t error = hipSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = hipMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = hipMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = hipMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } hipMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), hipMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); hipMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), hipMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); hipFree(d_m1); hipFree(d_m2); hipFree(d_m3); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<hip/hip_runtime.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince hipError_t error = hipSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = hipMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = hipMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = hipMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } hipMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), hipMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); hipMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), hipMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); hipFree(d_m1); hipFree(d_m2); hipFree(d_m3); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21multiplicationKernellPfS_S_ii .globl _Z21multiplicationKernellPfS_S_ii .p2align 8 .type _Z21multiplicationKernellPfS_S_ii,@function _Z21multiplicationKernellPfS_S_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b64 s[8:9], s[0:1], 0x18 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s8, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s9, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_6 s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB0_4 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v0, s8 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v4, v1 s_mov_b32 s2, s8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .p2align 6 .LBB0_3: v_ashrrev_i32_e32 v5, 31, v4 s_add_i32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_cmp_eq_u32 s2, 0 v_lshlrev_b64 v[7:8], 2, v[4:5] v_add_nc_u32_e32 v4, s8, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b32 v5, v[2:3], off global_load_b32 v7, v[7:8], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v6, v5, v7 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_5 .LBB0_4: v_mov_b32_e32 v6, 0 .LBB0_5: s_load_b64 s[0:1], s[0:1], 0x10 v_mad_u64_u32 v[2:3], null, v0, s8, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v6, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21multiplicationKernellPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21multiplicationKernellPfS_S_ii, .Lfunc_end0-_Z21multiplicationKernellPfS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21multiplicationKernellPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21multiplicationKernellPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include<stdio.h> #include<stdlib.h> #include<malloc.h> #include<time.h> #include<hip/hip_runtime.h> #include<string.h> __global__ void multiplicationKernell(float* m1, float* m2, float* m3, int rowsM1, int colsM2) { int Row = blockIdx.y * blockDim.y + threadIdx.y; int Col = blockIdx.x * blockDim.x + threadIdx.x; if((Row < rowsM1) && (Col < colsM2)) { float resul = 0.0; for(int i = 0; i < rowsM1; i++) { resul = resul + m1[Row*rowsM1+i] * m2[i*rowsM1+Col]; } m3[Row*rowsM1+Col] = resul; } } __host__ void toMatrix(float *M, FILE *content, int rows, int cols) { for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { fscanf(content,"%f",&M[i*cols+j]); } } fclose(content); } __host__ void print(float *M, int rows, int cols) { printf("----------MATRIX----------\n"); for(int i=0; i<rows;i++) { for(int j=0; j<cols; j++) { printf("[%f]",M[i*cols+j]); } printf("\n"); } } int main(int argc, char** argv) { if(argc != 3) { printf("Error, no se encontraron todos los parametros necesarios."); return 1; } FILE *inputMatrix1; FILE *inputMatrix2; inputMatrix1 = fopen(argv[1],"r"); inputMatrix2 = fopen(argv[2],"r"); float *m1, *m2, *m3; int rowsM1, rowsM2, colsM1, colsM2, rowsM3, colsM3; fscanf(inputMatrix1,"%d",&rowsM1); fscanf(inputMatrix1,"%d",&colsM1); fscanf(inputMatrix2,"%d",&rowsM2); fscanf(inputMatrix2,"%d",&colsM2); m1 = (float*) malloc(rowsM1*colsM1*sizeof(float)); m2 = (float*) malloc(rowsM2*colsM2*sizeof(float)); m3 = (float*) malloc(rowsM1*colsM2*sizeof(float)); toMatrix(m1, inputMatrix1, rowsM1, colsM1); toMatrix(m2, inputMatrix2, rowsM2, colsM2); print(m1, rowsM1, colsM1); print(m2, rowsM2, colsM2); if((rowsM1 != colsM2)) { printf("Error los tamaños de las matrices no son compatibles."); return 1; } //Para el Devince hipError_t error = hipSuccess; float *d_m1, *d_m2, *d_m3; int blockSize = 32; dim3 dimBlockSize(blockSize,blockSize,1); dim3 dimGridSize(ceil(colsM1 / float(blockSize)), ceil(rowsM1 / float(blockSize)), 1); error = hipMalloc((void**)&d_m1, rowsM1 * colsM1 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m1"); return 1; } error = hipMalloc((void**)&d_m2, rowsM2 * colsM2 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m2"); return 1; } error = hipMalloc((void**)&d_m3, rowsM3 * colsM3 * sizeof(float)); if(error != hipSuccess) { printf("Imposible asignar memoria para d_m3"); return 1; } hipMemcpy(d_m1, m1, rowsM1 * colsM1 * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(d_m2, m2, rowsM2 * colsM2 * sizeof(float), hipMemcpyHostToDevice); multiplicationKernell<<<dimGridSize, dimBlockSize>>>(d_m1, d_m2, d_m3, rowsM1, colsM2); hipMemcpy(m3, d_m3, rowsM1 * colsM2 * sizeof(float), hipMemcpyDeviceToHost); print(m3, rowsM1, colsM2); free(m1); free(m2); free(m3); hipFree(d_m1); hipFree(d_m2); hipFree(d_m3); return 0; }
.text .file "MatrizCuda.hip" .globl _Z36__device_stub__multiplicationKernellPfS_S_ii # -- Begin function _Z36__device_stub__multiplicationKernellPfS_S_ii .p2align 4, 0x90 .type _Z36__device_stub__multiplicationKernellPfS_S_ii,@function _Z36__device_stub__multiplicationKernellPfS_S_ii: # @_Z36__device_stub__multiplicationKernellPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z21multiplicationKernellPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z36__device_stub__multiplicationKernellPfS_S_ii, .Lfunc_end0-_Z36__device_stub__multiplicationKernellPfS_S_ii .cfi_endproc # -- End function .globl _Z8toMatrixPfP8_IO_FILEii # -- Begin function _Z8toMatrixPfP8_IO_FILEii .p2align 4, 0x90 .type _Z8toMatrixPfP8_IO_FILEii,@function _Z8toMatrixPfP8_IO_FILEii: # @_Z8toMatrixPfP8_IO_FILEii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r14 movq %rdi, 8(%rsp) # 8-byte Spill testl %edx, %edx jle .LBB1_6 # %bb.1: # %.preheader.lr.ph movl %ecx, %ebx movl %edx, %eax movq %rax, 16(%rsp) # 8-byte Spill movl %ecx, %eax movq %rax, (%rsp) # 8-byte Spill xorl %r15d, %r15d xorl %ebp, %ebp jmp .LBB1_2 .p2align 4, 0x90 .LBB1_5: # %._crit_edge # in Loop: Header=BB1_2 Depth=1 incq %rbp addl %ebx, %r15d cmpq 16(%rsp), %rbp # 8-byte Folded Reload je .LBB1_6 .LBB1_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 testl %ebx, %ebx jle .LBB1_5 # %bb.3: # in Loop: Header=BB1_2 Depth=1 movl %r15d, %eax movq 8(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r12 movq (%rsp), %r13 # 8-byte Reload .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_2 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r14, %rdi movq %r12, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %r12 decq %r13 jne .LBB1_4 jmp .LBB1_5 .LBB1_6: # %._crit_edge15 movq %r14, %rdi addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .Lfunc_end1: .size _Z8toMatrixPfP8_IO_FILEii, .Lfunc_end1-_Z8toMatrixPfP8_IO_FILEii .cfi_endproc # -- End function .globl _Z5printPfii # -- Begin function _Z5printPfii .p2align 4, 0x90 .type _Z5printPfii,@function _Z5printPfii: # @_Z5printPfii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebx movl %esi, %ebp movq %rdi, 8(%rsp) # 8-byte Spill movl $.Lstr, %edi callq puts@PLT testl %ebp, %ebp jle .LBB2_6 # %bb.1: # %.preheader.lr.ph movl %ebp, %eax movq %rax, 16(%rsp) # 8-byte Spill movl %ebx, %r12d xorl %r13d, %r13d xorl %ebp, %ebp jmp .LBB2_2 .p2align 4, 0x90 .LBB2_5: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 movl $10, %edi callq putchar@PLT incq %rbp addl %ebx, %r13d cmpq 16(%rsp), %rbp # 8-byte Folded Reload je .LBB2_6 .LBB2_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 testl %ebx, %ebx jle .LBB2_5 # %bb.3: # %.lr.ph # in Loop: Header=BB2_2 Depth=1 movl %r13d, %eax movq 8(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_4: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %r15 cmpq %r15, %r12 jne .LBB2_4 jmp .LBB2_5 .LBB2_6: # %._crit_edge13 addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z5printPfii, .Lfunc_end2-_Z5printPfii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x3d000000 # float 0.03125 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $88, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $3, %edi jne .LBB3_1 # %bb.2: movq 8(%rsi), %rdi movq %rsi, %rbx movl $.L.str.5, %esi callq fopen movq %rax, %r13 movq 16(%rbx), %rdi movl $.L.str.5, %esi callq fopen movq %rax, %r12 leaq 12(%rsp), %rdx movl $.L.str.6, %esi movq %r13, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 20(%rsp), %rdx movl $.L.str.6, %esi movq %r13, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 16(%rsp), %rdx movl $.L.str.6, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 8(%rsp), %rdx movl $.L.str.6, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf movslq 12(%rsp), %r14 movl 20(%rsp), %ebx movl %ebx, %eax imull %r14d, %eax movslq %eax, %rdi shlq $2, %rdi callq malloc movq %rax, 48(%rsp) # 8-byte Spill movslq 16(%rsp), %rdi movslq 8(%rsp), %r15 imulq %r15, %rdi shlq $2, %rdi callq malloc movq %rax, 40(%rsp) # 8-byte Spill imulq %r14, %r15 shlq $2, %r15 movq %r15, %rdi callq malloc movq %rax, 80(%rsp) # 8-byte Spill testq %r14, %r14 jle .LBB3_8 # %bb.3: # %.preheader.lr.ph.i movl %r14d, %eax movq %rax, 32(%rsp) # 8-byte Spill xorl %r14d, %r14d xorl %r15d, %r15d movq %rbx, 24(%rsp) # 8-byte Spill jmp .LBB3_4 .p2align 4, 0x90 .LBB3_7: # %._crit_edge.i # in Loop: Header=BB3_4 Depth=1 incq %r15 movq 24(%rsp), %rbx # 8-byte Reload addl %ebx, %r14d cmpq 32(%rsp), %r15 # 8-byte Folded Reload je .LBB3_8 .LBB3_4: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 testl %ebx, %ebx jle .LBB3_7 # %bb.5: # in Loop: Header=BB3_4 Depth=1 movl %r14d, %eax movq 48(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %rbp movq 24(%rsp), %rbx # 8-byte Reload .p2align 4, 0x90 .LBB3_6: # Parent Loop BB3_4 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r13, %rdi movq %rbp, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %rbp decq %rbx jne .LBB3_6 jmp .LBB3_7 .LBB3_1: movl $.L.str.4, %edi jmp .LBB3_30 .LBB3_8: # %_Z8toMatrixPfP8_IO_FILEii.exit movq %r13, %rdi callq fclose movl 16(%rsp), %eax movq %rax, 24(%rsp) # 8-byte Spill testl %eax, %eax jle .LBB3_14 # %bb.9: # %.preheader.lr.ph.i40 movl 8(%rsp), %ebx xorl %r14d, %r14d xorl %r15d, %r15d jmp .LBB3_10 .p2align 4, 0x90 .LBB3_13: # %._crit_edge.i44 # in Loop: Header=BB3_10 Depth=1 incq %r15 addl %ebx, %r14d cmpq 24(%rsp), %r15 # 8-byte Folded Reload je .LBB3_14 .LBB3_10: # %.preheader.i42 # =>This Loop Header: Depth=1 # Child Loop BB3_12 Depth 2 testl %ebx, %ebx jle .LBB3_13 # %bb.11: # in Loop: Header=BB3_10 Depth=1 movl %r14d, %eax movq 40(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r13 movq %rbx, %rbp .p2align 4, 0x90 .LBB3_12: # Parent Loop BB3_10 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r12, %rdi movq %r13, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %r13 decq %rbp jne .LBB3_12 jmp .LBB3_13 .LBB3_14: # %_Z8toMatrixPfP8_IO_FILEii.exit52 movq %r12, %rdi callq fclose movl 12(%rsp), %ebx movl 20(%rsp), %r12d movl $.Lstr, %edi callq puts@PLT testl %ebx, %ebx jle .LBB3_20 # %bb.15: # %.preheader.lr.ph.i53 xorl %r13d, %r13d xorl %r14d, %r14d jmp .LBB3_16 .p2align 4, 0x90 .LBB3_19: # %._crit_edge.i55 # in Loop: Header=BB3_16 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addl %r12d, %r13d cmpq %rbx, %r14 je .LBB3_20 .LBB3_16: # %.preheader.i54 # =>This Loop Header: Depth=1 # Child Loop BB3_18 Depth 2 testl %r12d, %r12d jle .LBB3_19 # %bb.17: # %.lr.ph.i56 # in Loop: Header=BB3_16 Depth=1 movl %r13d, %eax movq 48(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r15 xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_18: # Parent Loop BB3_16 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %rbp cmpq %rbp, %r12 jne .LBB3_18 jmp .LBB3_19 .LBB3_20: # %_Z5printPfii.exit movl 16(%rsp), %ebx movl 8(%rsp), %r12d movl $.Lstr, %edi callq puts@PLT testl %ebx, %ebx jle .LBB3_26 # %bb.21: # %.preheader.lr.ph.i62 xorl %r13d, %r13d xorl %r14d, %r14d jmp .LBB3_22 .p2align 4, 0x90 .LBB3_25: # %._crit_edge.i66 # in Loop: Header=BB3_22 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addl %r12d, %r13d cmpq %rbx, %r14 je .LBB3_26 .LBB3_22: # %.preheader.i64 # =>This Loop Header: Depth=1 # Child Loop BB3_24 Depth 2 testl %r12d, %r12d jle .LBB3_25 # %bb.23: # %.lr.ph.i70 # in Loop: Header=BB3_22 Depth=1 movl %r13d, %eax movq 40(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r15 xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_24: # Parent Loop BB3_22 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %rbp cmpq %rbp, %r12 jne .LBB3_24 jmp .LBB3_25 .LBB3_26: # %_Z5printPfii.exit75 movl 12(%rsp), %ebx cmpl 8(%rsp), %ebx jne .LBB3_27 # %bb.28: movl 20(%rsp), %ebp xorps %xmm0, %xmm0 cvtsi2ss %ebp, %xmm0 mulss .LCPI3_0(%rip), %xmm0 callq ceilf@PLT movss %xmm0, 24(%rsp) # 4-byte Spill xorps %xmm0, %xmm0 cvtsi2ss %ebx, %xmm0 mulss .LCPI3_0(%rip), %xmm0 callq ceilf@PLT movss %xmm0, 32(%rsp) # 4-byte Spill imull %ebx, %ebp movslq %ebp, %rsi shlq $2, %rsi leaq 72(%rsp), %rdi callq hipMalloc testl %eax, %eax je .LBB3_31 # %bb.29: movl $.L.str.8, %edi jmp .LBB3_30 .LBB3_27: movl $.L.str.7, %edi .LBB3_30: xorl %eax, %eax callq printf movl $1, %r12d .LBB3_38: movl %r12d, %eax addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_31: .cfi_def_cfa_offset 144 movslq 16(%rsp), %rax movslq 8(%rsp), %rsi imulq %rax, %rsi shlq $2, %rsi leaq 64(%rsp), %rdi callq hipMalloc testl %eax, %eax je .LBB3_33 # %bb.32: movl $.L.str.9, %edi jmp .LBB3_30 .LBB3_33: leaq 56(%rsp), %rdi xorl %esi, %esi callq hipMalloc testl %eax, %eax je .LBB3_35 # %bb.34: movl $.L.str.10, %edi jmp .LBB3_30 .LBB3_35: cvttss2si 24(%rsp), %rax # 4-byte Folded Reload cvttss2si 32(%rsp), %r13 # 4-byte Folded Reload movl %eax, %eax shlq $32, %r13 orq %rax, %r13 movq 72(%rsp), %rdi movslq 12(%rsp), %rax movslq 20(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 48(%rsp), %rbx # 8-byte Reload movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 64(%rsp), %rdi movslq 16(%rsp), %rax movslq 8(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 40(%rsp), %r14 # 8-byte Reload movq %r14, %rsi movl $1, %ecx callq hipMemcpy xorl %r12d, %r12d movabsq $137438953504, %rdx # imm = 0x2000000020 movq %r13, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_37 # %bb.36: movq 72(%rsp), %rdi movq 64(%rsp), %rsi movq 56(%rsp), %rdx movl 12(%rsp), %ecx movl 8(%rsp), %r8d callq _Z36__device_stub__multiplicationKernellPfS_S_ii .LBB3_37: movq 56(%rsp), %rsi movslq 12(%rsp), %rax movslq 8(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 80(%rsp), %r15 # 8-byte Reload movq %r15, %rdi movl $2, %ecx callq hipMemcpy movl 12(%rsp), %esi movl 8(%rsp), %edx movq %r15, %rdi callq _Z5printPfii movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq 72(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree jmp .LBB3_38 .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21multiplicationKernellPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z21multiplicationKernellPfS_S_ii,@object # @_Z21multiplicationKernellPfS_S_ii .section .rodata,"a",@progbits .globl _Z21multiplicationKernellPfS_S_ii .p2align 3, 0x0 _Z21multiplicationKernellPfS_S_ii: .quad _Z36__device_stub__multiplicationKernellPfS_S_ii .size _Z21multiplicationKernellPfS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "[%f]" .size .L.str.2, 5 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error, no se encontraron todos los parametros necesarios." .size .L.str.4, 58 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "r" .size .L.str.5, 2 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "%d" .size .L.str.6, 3 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Error los tama\303\261os de las matrices no son compatibles." .size .L.str.7, 55 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Imposible asignar memoria para d_m1" .size .L.str.8, 36 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Imposible asignar memoria para d_m2" .size .L.str.9, 36 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Imposible asignar memoria para d_m3" .size .L.str.10, 36 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21multiplicationKernellPfS_S_ii" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "----------MATRIX----------" .size .Lstr, 27 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__multiplicationKernellPfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21multiplicationKernellPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z21multiplicationKernellPfS_S_ii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */ /* 0x000e280000002500 */ /*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e280000002100 */ /*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */ /* 0x000e680000002600 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e620000002200 */ /*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */ /* 0x001fca00078e0205 */ /*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */ /* 0x000fe20003f06270 */ /*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */ /* 0x002fca00078e0202 */ /*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */ /* 0x000fda0000706670 */ /*0090*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */ /* 0x000fe20000000f00 */ /*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */ /* 0x000fe200000001ff */ /*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */ /* 0x000fe200078e02ff */ /*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */ /* 0x000fda0003f06270 */ /*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */ /* 0x000fea0003800000 */ /*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */ /* 0x040fe40007ffe0ff */ /*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */ /* 0x000fe400078ec0ff */ /*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */ /* 0x000fe40003f06070 */ /*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fe40000000f00 */ /*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */ /* 0x000fd20000000f00 */ /*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */ /* 0x000fea0003800000 */ /*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */ /* 0x000fe20007ffe1ff */ /*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */ /* 0x000fe200000001ff */ /*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */ /* 0x000fe200000001ff */ /*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe40003f04270 */ /*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fca0000000f00 */ /*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */ /* 0x000fcc00078e0219 */ /*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */ /* 0x000fea0003800000 */ /*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe40003f24270 */ /*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */ /* 0x000fea0003800000 */ /*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */ /* 0x000fe20008000f00 */ /*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */ /* 0x0000a2000c1e1900 */ /*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */ /* 0x000fca0008000f00 */ /*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */ /* 0x000fca00078e020c */ /*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */ /* 0x000ea2000c1e1900 */ /*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */ /* 0x000fc600078e0218 */ /*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */ /* 0x000ee6000c1e1900 */ /*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */ /* 0x040fe200078e020a */ /*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */ /* 0x0002e8000c1e1900 */ /*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */ /* 0x000f22000c1e1900 */ /*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */ /* 0x000fc600078e0212 */ /*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x000b26000c1e1900 */ /*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */ /* 0x040fe200078e020e */ /*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */ /* 0x000128000c1e1900 */ /*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */ /* 0x000f28000c1e1900 */ /*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */ /* 0x020f22000c1e1900 */ /*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */ /* 0x001fc600078e0214 */ /*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */ /* 0x000166000c1e1900 */ /*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */ /* 0x040fe200078e020e */ /*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */ /* 0x000168000c1e1900 */ /*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */ /* 0x002f62000c1e1900 */ /*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */ /* 0x000fc600078e0216 */ /*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */ /* 0x000368000c1e1900 */ /*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */ /* 0x001f62000c1e1900 */ /*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */ /* 0x004fc6000000001c */ /*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */ /* 0x000ea8000c1e1900 */ /*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */ /* 0x0000a2000c1e1900 */ /*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */ /* 0x000fc800078e0218 */ /*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */ /* 0x008fe4000000001d */ /*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */ /* 0x000fe400078e020e */ /*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x0006a4000c1e1900 */ /*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */ /* 0x010fe4000000001d */ /*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */ /* 0x000fe400078e0210 */ /*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x0008a4000c1e1900 */ /*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */ /* 0x000fc4000000001d */ /*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */ /* 0x042fe200078e0212 */ /*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */ /* 0x000ea8000c1e1900 */ /*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */ /* 0x000ea2000c1e1900 */ /*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */ /* 0x001fc600078e0216 */ /*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x0000a2000c1e1900 */ /*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */ /* 0x020fc6000000001a */ /*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */ /* 0x000f62000c1e1900 */ /*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */ /* 0x000fe40000000009 */ /*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */ /* 0x000fe200078e0218 */ /*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */ /* 0x000368000c1e1900 */ /*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */ /* 0x010f22000c1e1900 */ /*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */ /* 0x000fc6000000000b */ /*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */ /* 0x008722000c1e1900 */ /*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */ /* 0x000fc600078e0208 */ /*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */ /* 0x001128000c1e1900 */ /*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */ /* 0x002f28000c1e1900 */ /*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */ /* 0x008ee8000c1e1900 */ /*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */ /* 0x000ee8000c1e1900 */ /*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */ /* 0x001ee2000c1e1900 */ /*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */ /* 0x004fc60000000015 */ /*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */ /* 0x000ea2000c1e1900 */ /*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */ /* 0x000fca00078e020a */ /*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */ /* 0x000ea2000c1e1900 */ /*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */ /* 0x000fc80007ffe0ff */ /*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe20003f24270 */ /*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */ /* 0x000fc80000000009 */ /*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */ /* 0x000fc80000000007 */ /*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */ /* 0x020fc80000000007 */ /*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */ /* 0x010fe20000000007 */ /*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff1e03f */ /*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */ /* 0x000fc60007ffe0ff */ /*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */ /* 0x008fc80000000007 */ /*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */ /* 0x004fc80000000007 */ /*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */ /* 0x000fe4000000001c */ /*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */ /* 0x000fc800078e0214 */ /*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */ /* 0x000fe2000000001c */ /*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */ /* 0x000fea000383ffff */ /*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */ /* 0x000fda0003f24270 */ /*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */ /* 0x000fea0003800000 */ /*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */ /* 0x000fe200078e0218 */ /*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */ /* 0x0000a2000c1e1900 */ /*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fc60008000f00 */ /*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */ /* 0x040fe200078e0210 */ /*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */ /* 0x0002e6000c1e1900 */ /*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */ /* 0x000fe200078e0208 */ /*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */ /* 0x000966000c1e1900 */ /*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */ /* 0x040fe200078e020c */ /*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */ /* 0x000ea8000c1e1900 */ /*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */ /* 0x000ee2000c1e1900 */ /*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */ /* 0x000fc600078e020e */ /*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */ /* 0x000f66000c1e1900 */ /*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */ /* 0x042fe200078e020a */ /*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000368000c1e1900 */ /*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */ /* 0x000f62000c1e1900 */ /*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */ /* 0x000fc600078e0210 */ /*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */ /* 0x000368000c1e1900 */ /*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */ /* 0x001f62000c1e1900 */ /*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */ /* 0x010fc600078e0212 */ /*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x000f28000c1e1900 */ /*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */ /* 0x000f28000c1e1900 */ /*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */ /* 0x000128000c1e1900 */ /*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */ /* 0x002f28000c1e1900 */ /*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */ /* 0x000f28000c1e1900 */ /*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */ /* 0x001f22000c1e1900 */ /*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */ /* 0x000fe2000ff1e03f */ /*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */ /* 0x000fe40007ffe0ff */ /*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */ /* 0x000fe20007ffe0ff */ /*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */ /* 0x004fc8000000001c */ /*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */ /* 0x008fc80000000007 */ /*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */ /* 0x020fc80000000007 */ /*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */ /* 0x000fc80000000007 */ /*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */ /* 0x000fc80000000007 */ /*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */ /* 0x010fc80000000007 */ /*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */ /* 0x000fe40000000007 */ /*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */ /* 0x000fc800078e020c */ /*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */ /* 0x000fe40000000007 */ /*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0000705670 */ /*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */ /* 0x000fea0003800000 */ /*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */ /* 0x000fe200078e0218 */ /*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fe20008000f00 */ /*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */ /* 0x000ea8000c1e1900 */ /*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */ /* 0x000fc800078e0208 */ /*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */ /* 0x040fe200078e020e */ /*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea8000c1e1900 */ /*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000ee2000c1e1900 */ /*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */ /* 0x000fc600078e020c */ /*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */ /* 0x000ee8000c1e1900 */ /*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x000f28000c1e1900 */ /*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */ /* 0x000f28000c1e1900 */ /*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */ /* 0x000f68000c1e1900 */ /*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */ /* 0x000f62000c1e1900 */ /*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */ /* 0x000fc80007ffe0ff */ /*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe20003f05270 */ /*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */ /* 0x000fe2000ff1e03f */ /*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */ /* 0x000fc60007ffe0ff */ /*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */ /* 0x004fc8000000001c */ /*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */ /* 0x008fe40000000007 */ /*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */ /* 0x000fc800078e020a */ /*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */ /* 0x010fc80000000007 */ /*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */ /* 0x020fe20000000007 */ /*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */ /* 0x000fea000383ffff */ /*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f05270 */ /*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */ /* 0x000fea0003800000 */ /*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */ /* 0x000fe200000001ff */ /*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */ /* 0x000fe20007ffe0ff */ /*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */ /* 0x000fd000078e0200 */ /*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fc800078e0209 */ /*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */ /* 0x000fca00078e0209 */ /*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */ /* 0x0000a8000c1e1900 */ /*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */ /* 0x0002a2000c1e1900 */ /*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */ /* 0x000fc80007ffe0ff */ /*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */ /* 0x001fe200078e0208 */ /*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */ /* 0x002fc80007f3e0ff */ /*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x000fe20000ffe4ff */ /*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */ /* 0x004fcc000000001c */ /*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */ /* 0x000fea000383ffff */ /*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */ /* 0x000fe40007ffe0ff */ /*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fca0000000f00 */ /*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */ /* 0x000fca00078e0202 */ /*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */ /* 0x000fe2000c101904 */ /*0c40*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0c60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ca0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ce0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z21multiplicationKernellPfS_S_ii .globl _Z21multiplicationKernellPfS_S_ii .p2align 8 .type _Z21multiplicationKernellPfS_S_ii,@function _Z21multiplicationKernellPfS_S_ii: s_clause 0x1 s_load_b32 s2, s[0:1], 0x2c s_load_b64 s[8:9], s[0:1], 0x18 v_bfe_u32 v2, v0, 10, 10 v_and_b32_e32 v3, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s3, s2, 16 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3] v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4] v_cmp_gt_i32_e32 vcc_lo, s8, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i32_e64 s2, s9, v1 s_and_b32 s2, vcc_lo, s2 s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB0_6 s_cmp_lt_i32 s8, 1 s_cbranch_scc1 .LBB0_4 s_load_b128 s[4:7], s[0:1], 0x0 v_mul_lo_u32 v2, v0, s8 v_mov_b32_e32 v6, 0 v_mov_b32_e32 v4, v1 s_mov_b32 s2, s8 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[2:3], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, s4, v2 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo .p2align 6 .LBB0_3: v_ashrrev_i32_e32 v5, 31, v4 s_add_i32 s2, s2, -1 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) s_cmp_eq_u32 s2, 0 v_lshlrev_b64 v[7:8], 2, v[4:5] v_add_nc_u32_e32 v4, s8, v4 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_u32 v7, vcc_lo, s6, v7 v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo global_load_b32 v5, v[2:3], off global_load_b32 v7, v[7:8], off v_add_co_u32 v2, vcc_lo, v2, 4 v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo s_waitcnt vmcnt(0) v_fmac_f32_e32 v6, v5, v7 s_cbranch_scc0 .LBB0_3 s_branch .LBB0_5 .LBB0_4: v_mov_b32_e32 v6, 0 .LBB0_5: s_load_b64 s[0:1], s[0:1], 0x10 v_mad_u64_u32 v[2:3], null, v0, s8, v[1:2] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v3, 31, v2 v_lshlrev_b64 v[0:1], 2, v[2:3] s_waitcnt lgkmcnt(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, s0, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v6, off .LBB0_6: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z21multiplicationKernellPfS_S_ii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 9 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z21multiplicationKernellPfS_S_ii, .Lfunc_end0-_Z21multiplicationKernellPfS_S_ii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z21multiplicationKernellPfS_S_ii .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z21multiplicationKernellPfS_S_ii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 9 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001966b6_00000000-6_MatrizCuda.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "%f" .text .globl _Z8toMatrixPfP8_IO_FILEii .type _Z8toMatrixPfP8_IO_FILEii, @function _Z8toMatrixPfP8_IO_FILEii: .LFB2057: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $24, %rsp .cfi_def_cfa_offset 80 movq %rdi, 8(%rsp) movq %rsi, %r12 movl %edx, 4(%rsp) testl %edx, %edx jle .L4 movl %ecx, %r14d movl $0, (%rsp) movl $0, %r15d leaq .LC0(%rip), %r13 jmp .L5 .L7: movslq (%rsp), %rdx movq 8(%rsp), %rcx leaq (%rcx,%rdx,4), %rbx movslq %r14d, %rax addq %rdx, %rax leaq (%rcx,%rax,4), %rbp .L6: movq %rbx, %rdx movq %r13, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L6 .L8: addl $1, %r15d addl %r14d, (%rsp) cmpl %r15d, 4(%rsp) je .L4 .L5: testl %r14d, %r14d jg .L7 jmp .L8 .L4: movq %r12, %rdi call fclose@PLT addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z8toMatrixPfP8_IO_FILEii, .-_Z8toMatrixPfP8_IO_FILEii .section .rodata.str1.1 .LC1: .string "----------MATRIX----------\n" .LC2: .string "[%f]" .LC3: .string "\n" .text .globl _Z5printPfii .type _Z5printPfii, @function _Z5printPfii: .LFB2058: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $40, %rsp .cfi_def_cfa_offset 96 movq %rdi, 16(%rsp) movl %esi, %ebx movl %esi, 12(%rsp) movl %edx, %r15d leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT testl %ebx, %ebx jle .L11 movl $0, %r14d movl $0, %r13d movslq %r15d, %rax movq %rax, 24(%rsp) leaq .LC2(%rip), %r12 jmp .L13 .L15: movslq %r14d, %rax movq 16(%rsp), %rcx leaq (%rcx,%rax,4), %rbx movq 24(%rsp), %rdx addq %rdx, %rax leaq (%rcx,%rax,4), %rbp .L14: pxor %xmm0, %xmm0 cvtss2sd (%rbx), %xmm0 movq %r12, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $4, %rbx cmpq %rbp, %rbx jne .L14 .L16: leaq .LC3(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addl $1, %r13d addl %r15d, %r14d cmpl %r13d, 12(%rsp) je .L11 .L13: testl %r15d, %r15d jg .L15 jmp .L16 .L11: addq $40, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2058: .size _Z5printPfii, .-_Z5printPfii .globl _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii .type _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii, @function _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movq %rsp, %rax movq %rax, 128(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L23 .L19: movq 136(%rsp), %rax subq %fs:40, %rax jne .L24 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z21multiplicationKernellPfS_S_ii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L19 .L24: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii, .-_Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii .globl _Z21multiplicationKernellPfS_S_ii .type _Z21multiplicationKernellPfS_S_ii, @function _Z21multiplicationKernellPfS_S_ii: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z21multiplicationKernellPfS_S_ii, .-_Z21multiplicationKernellPfS_S_ii .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC4: .string "Error, no se encontraron todos los parametros necesarios." .section .rodata.str1.1 .LC5: .string "r" .LC6: .string "%d" .section .rodata.str1.8 .align 8 .LC7: .string "Error los tama\303\261os de las matrices no son compatibles." .align 8 .LC9: .string "Imposible asignar memoria para d_m1" .align 8 .LC10: .string "Imposible asignar memoria para d_m2" .align 8 .LC11: .string "Imposible asignar memoria para d_m3" .text .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $104, %rsp .cfi_def_cfa_offset 160 movq %fs:40, %rax movq %rax, 88(%rsp) xorl %eax, %eax cmpl $3, %edi je .L28 leaq .LC4(%rip), %rsi movl $2, %edi call __printf_chk@PLT movl $1, %eax .L27: movq 88(%rsp), %rdx subq %fs:40, %rdx jne .L37 addq $104, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L28: .cfi_restore_state movq %rsi, %rbx movq 8(%rsi), %rdi leaq .LC5(%rip), %rbp movq %rbp, %rsi call fopen@PLT movq %rax, %r12 movq 16(%rbx), %rdi movq %rbp, %rsi call fopen@PLT movq %rax, %rbp leaq 24(%rsp), %rdx leaq .LC6(%rip), %rbx movq %rbx, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 32(%rsp), %rdx movq %rbx, %rsi movq %r12, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 28(%rsp), %rdx movq %rbx, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT leaq 36(%rsp), %rdx movq %rbx, %rsi movq %rbp, %rdi movl $0, %eax call __isoc23_fscanf@PLT movl 24(%rsp), %r14d movl 32(%rsp), %r15d movl %r14d, %edi imull %r15d, %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, %r13 movl 36(%rsp), %ebx movl %ebx, %edi imull 28(%rsp), %edi movslq %edi, %rdi salq $2, %rdi call malloc@PLT movq %rax, (%rsp) imull %r14d, %ebx movslq %ebx, %rdi salq $2, %rdi call malloc@PLT movq %rax, %rbx movl %r15d, %ecx movl %r14d, %edx movq %r12, %rsi movq %r13, %rdi call _Z8toMatrixPfP8_IO_FILEii movl 36(%rsp), %ecx movl 28(%rsp), %edx movq %rbp, %rsi movq (%rsp), %r15 movq %r15, %rdi call _Z8toMatrixPfP8_IO_FILEii movl 32(%rsp), %edx movl 24(%rsp), %esi movq %r13, %rdi call _Z5printPfii movl 36(%rsp), %edx movl 28(%rsp), %esi movq %r15, %rdi call _Z5printPfii movl 24(%rsp), %ebp cmpl 36(%rsp), %ebp je .L30 leaq .LC7(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L30: movl $32, 64(%rsp) movl $32, 68(%rsp) movl $1, 72(%rsp) pxor %xmm0, %xmm0 cvtsi2ssl %ebp, %xmm0 mulss .LC8(%rip), %xmm0 call ceilf@PLT movss %xmm0, 12(%rsp) movl 32(%rsp), %r12d pxor %xmm0, %xmm0 cvtsi2ssl %r12d, %xmm0 mulss .LC8(%rip), %xmm0 call ceilf@PLT cvttss2siq %xmm0, %rax movl %eax, 76(%rsp) cvttss2siq 12(%rsp), %rax movl %eax, 80(%rsp) movl $1, 84(%rsp) imull %r12d, %ebp movslq %ebp, %rsi salq $2, %rsi leaq 40(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax jne .L38 movl 28(%rsp), %esi imull 36(%rsp), %esi movslq %esi, %rsi salq $2, %rsi leaq 48(%rsp), %rdi call cudaMalloc@PLT testl %eax, %eax jne .L39 leaq 56(%rsp), %rdi movl $0, %esi call cudaMalloc@PLT testl %eax, %eax jne .L40 movl 24(%rsp), %edx imull 32(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq %r13, %rsi movq 40(%rsp), %rdi call cudaMemcpy@PLT movl 28(%rsp), %edx imull 36(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $1, %ecx movq (%rsp), %rsi movq 48(%rsp), %rdi call cudaMemcpy@PLT movl 72(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 64(%rsp), %rdx movq 76(%rsp), %rdi movl 84(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L41 .L34: movl 24(%rsp), %edx imull 36(%rsp), %edx movslq %edx, %rdx salq $2, %rdx movl $2, %ecx movq 56(%rsp), %rsi movq %rbx, %rdi call cudaMemcpy@PLT movl 36(%rsp), %edx movl 24(%rsp), %esi movq %rbx, %rdi call _Z5printPfii movq %r13, %rdi call free@PLT movq (%rsp), %rdi call free@PLT movq %rbx, %rdi call free@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq 48(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rdi call cudaFree@PLT movl $0, %eax jmp .L27 .L38: leaq .LC9(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L39: leaq .LC10(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L40: leaq .LC11(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl $1, %eax jmp .L27 .L41: movl 36(%rsp), %r8d movl 24(%rsp), %ecx movq 56(%rsp), %rdx movq 48(%rsp), %rsi movq 40(%rsp), %rdi call _Z47__device_stub__Z21multiplicationKernellPfS_S_iiPfS_S_ii jmp .L34 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.8 .align 8 .LC12: .string "_Z21multiplicationKernellPfS_S_ii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z21multiplicationKernellPfS_S_ii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC8: .long 1023410176 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "MatrizCuda.hip" .globl _Z36__device_stub__multiplicationKernellPfS_S_ii # -- Begin function _Z36__device_stub__multiplicationKernellPfS_S_ii .p2align 4, 0x90 .type _Z36__device_stub__multiplicationKernellPfS_S_ii,@function _Z36__device_stub__multiplicationKernellPfS_S_ii: # @_Z36__device_stub__multiplicationKernellPfS_S_ii .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) movl %r8d, (%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) movq %rsp, %rax movq %rax, 112(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z21multiplicationKernellPfS_S_ii, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z36__device_stub__multiplicationKernellPfS_S_ii, .Lfunc_end0-_Z36__device_stub__multiplicationKernellPfS_S_ii .cfi_endproc # -- End function .globl _Z8toMatrixPfP8_IO_FILEii # -- Begin function _Z8toMatrixPfP8_IO_FILEii .p2align 4, 0x90 .type _Z8toMatrixPfP8_IO_FILEii,@function _Z8toMatrixPfP8_IO_FILEii: # @_Z8toMatrixPfP8_IO_FILEii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rsi, %r14 movq %rdi, 8(%rsp) # 8-byte Spill testl %edx, %edx jle .LBB1_6 # %bb.1: # %.preheader.lr.ph movl %ecx, %ebx movl %edx, %eax movq %rax, 16(%rsp) # 8-byte Spill movl %ecx, %eax movq %rax, (%rsp) # 8-byte Spill xorl %r15d, %r15d xorl %ebp, %ebp jmp .LBB1_2 .p2align 4, 0x90 .LBB1_5: # %._crit_edge # in Loop: Header=BB1_2 Depth=1 incq %rbp addl %ebx, %r15d cmpq 16(%rsp), %rbp # 8-byte Folded Reload je .LBB1_6 .LBB1_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB1_4 Depth 2 testl %ebx, %ebx jle .LBB1_5 # %bb.3: # in Loop: Header=BB1_2 Depth=1 movl %r15d, %eax movq 8(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r12 movq (%rsp), %r13 # 8-byte Reload .p2align 4, 0x90 .LBB1_4: # Parent Loop BB1_2 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r14, %rdi movq %r12, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %r12 decq %r13 jne .LBB1_4 jmp .LBB1_5 .LBB1_6: # %._crit_edge15 movq %r14, %rdi addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 jmp fclose # TAILCALL .Lfunc_end1: .size _Z8toMatrixPfP8_IO_FILEii, .Lfunc_end1-_Z8toMatrixPfP8_IO_FILEii .cfi_endproc # -- End function .globl _Z5printPfii # -- Begin function _Z5printPfii .p2align 4, 0x90 .type _Z5printPfii,@function _Z5printPfii: # @_Z5printPfii .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $24, %rsp .cfi_def_cfa_offset 80 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebx movl %esi, %ebp movq %rdi, 8(%rsp) # 8-byte Spill movl $.Lstr, %edi callq puts@PLT testl %ebp, %ebp jle .LBB2_6 # %bb.1: # %.preheader.lr.ph movl %ebp, %eax movq %rax, 16(%rsp) # 8-byte Spill movl %ebx, %r12d xorl %r13d, %r13d xorl %ebp, %ebp jmp .LBB2_2 .p2align 4, 0x90 .LBB2_5: # %._crit_edge # in Loop: Header=BB2_2 Depth=1 movl $10, %edi callq putchar@PLT incq %rbp addl %ebx, %r13d cmpq 16(%rsp), %rbp # 8-byte Folded Reload je .LBB2_6 .LBB2_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB2_4 Depth 2 testl %ebx, %ebx jle .LBB2_5 # %bb.3: # %.lr.ph # in Loop: Header=BB2_2 Depth=1 movl %r13d, %eax movq 8(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB2_4: # Parent Loop BB2_2 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %r15 cmpq %r15, %r12 jne .LBB2_4 jmp .LBB2_5 .LBB2_6: # %._crit_edge13 addq $24, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size _Z5printPfii, .Lfunc_end2-_Z5printPfii .cfi_endproc # -- End function .section .rodata.cst4,"aM",@progbits,4 .p2align 2, 0x0 # -- Begin function main .LCPI3_0: .long 0x3d000000 # float 0.03125 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $88, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 cmpl $3, %edi jne .LBB3_1 # %bb.2: movq 8(%rsi), %rdi movq %rsi, %rbx movl $.L.str.5, %esi callq fopen movq %rax, %r13 movq 16(%rbx), %rdi movl $.L.str.5, %esi callq fopen movq %rax, %r12 leaq 12(%rsp), %rdx movl $.L.str.6, %esi movq %r13, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 20(%rsp), %rdx movl $.L.str.6, %esi movq %r13, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 16(%rsp), %rdx movl $.L.str.6, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf leaq 8(%rsp), %rdx movl $.L.str.6, %esi movq %r12, %rdi xorl %eax, %eax callq __isoc23_fscanf movslq 12(%rsp), %r14 movl 20(%rsp), %ebx movl %ebx, %eax imull %r14d, %eax movslq %eax, %rdi shlq $2, %rdi callq malloc movq %rax, 48(%rsp) # 8-byte Spill movslq 16(%rsp), %rdi movslq 8(%rsp), %r15 imulq %r15, %rdi shlq $2, %rdi callq malloc movq %rax, 40(%rsp) # 8-byte Spill imulq %r14, %r15 shlq $2, %r15 movq %r15, %rdi callq malloc movq %rax, 80(%rsp) # 8-byte Spill testq %r14, %r14 jle .LBB3_8 # %bb.3: # %.preheader.lr.ph.i movl %r14d, %eax movq %rax, 32(%rsp) # 8-byte Spill xorl %r14d, %r14d xorl %r15d, %r15d movq %rbx, 24(%rsp) # 8-byte Spill jmp .LBB3_4 .p2align 4, 0x90 .LBB3_7: # %._crit_edge.i # in Loop: Header=BB3_4 Depth=1 incq %r15 movq 24(%rsp), %rbx # 8-byte Reload addl %ebx, %r14d cmpq 32(%rsp), %r15 # 8-byte Folded Reload je .LBB3_8 .LBB3_4: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 testl %ebx, %ebx jle .LBB3_7 # %bb.5: # in Loop: Header=BB3_4 Depth=1 movl %r14d, %eax movq 48(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %rbp movq 24(%rsp), %rbx # 8-byte Reload .p2align 4, 0x90 .LBB3_6: # Parent Loop BB3_4 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r13, %rdi movq %rbp, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %rbp decq %rbx jne .LBB3_6 jmp .LBB3_7 .LBB3_1: movl $.L.str.4, %edi jmp .LBB3_30 .LBB3_8: # %_Z8toMatrixPfP8_IO_FILEii.exit movq %r13, %rdi callq fclose movl 16(%rsp), %eax movq %rax, 24(%rsp) # 8-byte Spill testl %eax, %eax jle .LBB3_14 # %bb.9: # %.preheader.lr.ph.i40 movl 8(%rsp), %ebx xorl %r14d, %r14d xorl %r15d, %r15d jmp .LBB3_10 .p2align 4, 0x90 .LBB3_13: # %._crit_edge.i44 # in Loop: Header=BB3_10 Depth=1 incq %r15 addl %ebx, %r14d cmpq 24(%rsp), %r15 # 8-byte Folded Reload je .LBB3_14 .LBB3_10: # %.preheader.i42 # =>This Loop Header: Depth=1 # Child Loop BB3_12 Depth 2 testl %ebx, %ebx jle .LBB3_13 # %bb.11: # in Loop: Header=BB3_10 Depth=1 movl %r14d, %eax movq 40(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r13 movq %rbx, %rbp .p2align 4, 0x90 .LBB3_12: # Parent Loop BB3_10 Depth=1 # => This Inner Loop Header: Depth=2 movl $.L.str, %esi movq %r12, %rdi movq %r13, %rdx xorl %eax, %eax callq __isoc23_fscanf addq $4, %r13 decq %rbp jne .LBB3_12 jmp .LBB3_13 .LBB3_14: # %_Z8toMatrixPfP8_IO_FILEii.exit52 movq %r12, %rdi callq fclose movl 12(%rsp), %ebx movl 20(%rsp), %r12d movl $.Lstr, %edi callq puts@PLT testl %ebx, %ebx jle .LBB3_20 # %bb.15: # %.preheader.lr.ph.i53 xorl %r13d, %r13d xorl %r14d, %r14d jmp .LBB3_16 .p2align 4, 0x90 .LBB3_19: # %._crit_edge.i55 # in Loop: Header=BB3_16 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addl %r12d, %r13d cmpq %rbx, %r14 je .LBB3_20 .LBB3_16: # %.preheader.i54 # =>This Loop Header: Depth=1 # Child Loop BB3_18 Depth 2 testl %r12d, %r12d jle .LBB3_19 # %bb.17: # %.lr.ph.i56 # in Loop: Header=BB3_16 Depth=1 movl %r13d, %eax movq 48(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r15 xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_18: # Parent Loop BB3_16 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %rbp cmpq %rbp, %r12 jne .LBB3_18 jmp .LBB3_19 .LBB3_20: # %_Z5printPfii.exit movl 16(%rsp), %ebx movl 8(%rsp), %r12d movl $.Lstr, %edi callq puts@PLT testl %ebx, %ebx jle .LBB3_26 # %bb.21: # %.preheader.lr.ph.i62 xorl %r13d, %r13d xorl %r14d, %r14d jmp .LBB3_22 .p2align 4, 0x90 .LBB3_25: # %._crit_edge.i66 # in Loop: Header=BB3_22 Depth=1 movl $10, %edi callq putchar@PLT incq %r14 addl %r12d, %r13d cmpq %rbx, %r14 je .LBB3_26 .LBB3_22: # %.preheader.i64 # =>This Loop Header: Depth=1 # Child Loop BB3_24 Depth 2 testl %r12d, %r12d jle .LBB3_25 # %bb.23: # %.lr.ph.i70 # in Loop: Header=BB3_22 Depth=1 movl %r13d, %eax movq 40(%rsp), %rcx # 8-byte Reload leaq (%rcx,%rax,4), %r15 xorl %ebp, %ebp .p2align 4, 0x90 .LBB3_24: # Parent Loop BB3_22 Depth=1 # => This Inner Loop Header: Depth=2 movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $.L.str.2, %edi movb $1, %al callq printf incq %rbp cmpq %rbp, %r12 jne .LBB3_24 jmp .LBB3_25 .LBB3_26: # %_Z5printPfii.exit75 movl 12(%rsp), %ebx cmpl 8(%rsp), %ebx jne .LBB3_27 # %bb.28: movl 20(%rsp), %ebp xorps %xmm0, %xmm0 cvtsi2ss %ebp, %xmm0 mulss .LCPI3_0(%rip), %xmm0 callq ceilf@PLT movss %xmm0, 24(%rsp) # 4-byte Spill xorps %xmm0, %xmm0 cvtsi2ss %ebx, %xmm0 mulss .LCPI3_0(%rip), %xmm0 callq ceilf@PLT movss %xmm0, 32(%rsp) # 4-byte Spill imull %ebx, %ebp movslq %ebp, %rsi shlq $2, %rsi leaq 72(%rsp), %rdi callq hipMalloc testl %eax, %eax je .LBB3_31 # %bb.29: movl $.L.str.8, %edi jmp .LBB3_30 .LBB3_27: movl $.L.str.7, %edi .LBB3_30: xorl %eax, %eax callq printf movl $1, %r12d .LBB3_38: movl %r12d, %eax addq $88, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_31: .cfi_def_cfa_offset 144 movslq 16(%rsp), %rax movslq 8(%rsp), %rsi imulq %rax, %rsi shlq $2, %rsi leaq 64(%rsp), %rdi callq hipMalloc testl %eax, %eax je .LBB3_33 # %bb.32: movl $.L.str.9, %edi jmp .LBB3_30 .LBB3_33: leaq 56(%rsp), %rdi xorl %esi, %esi callq hipMalloc testl %eax, %eax je .LBB3_35 # %bb.34: movl $.L.str.10, %edi jmp .LBB3_30 .LBB3_35: cvttss2si 24(%rsp), %rax # 4-byte Folded Reload cvttss2si 32(%rsp), %r13 # 4-byte Folded Reload movl %eax, %eax shlq $32, %r13 orq %rax, %r13 movq 72(%rsp), %rdi movslq 12(%rsp), %rax movslq 20(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 48(%rsp), %rbx # 8-byte Reload movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 64(%rsp), %rdi movslq 16(%rsp), %rax movslq 8(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 40(%rsp), %r14 # 8-byte Reload movq %r14, %rsi movl $1, %ecx callq hipMemcpy xorl %r12d, %r12d movabsq $137438953504, %rdx # imm = 0x2000000020 movq %r13, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_37 # %bb.36: movq 72(%rsp), %rdi movq 64(%rsp), %rsi movq 56(%rsp), %rdx movl 12(%rsp), %ecx movl 8(%rsp), %r8d callq _Z36__device_stub__multiplicationKernellPfS_S_ii .LBB3_37: movq 56(%rsp), %rsi movslq 12(%rsp), %rax movslq 8(%rsp), %rdx imulq %rax, %rdx shlq $2, %rdx movq 80(%rsp), %r15 # 8-byte Reload movq %r15, %rdi movl $2, %ecx callq hipMemcpy movl 12(%rsp), %esi movl 8(%rsp), %edx movq %r15, %rdi callq _Z5printPfii movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq 72(%rsp), %rdi callq hipFree movq 64(%rsp), %rdi callq hipFree movq 56(%rsp), %rdi callq hipFree jmp .LBB3_38 .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z21multiplicationKernellPfS_S_ii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z21multiplicationKernellPfS_S_ii,@object # @_Z21multiplicationKernellPfS_S_ii .section .rodata,"a",@progbits .globl _Z21multiplicationKernellPfS_S_ii .p2align 3, 0x0 _Z21multiplicationKernellPfS_S_ii: .quad _Z36__device_stub__multiplicationKernellPfS_S_ii .size _Z21multiplicationKernellPfS_S_ii, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "%f" .size .L.str, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "[%f]" .size .L.str.2, 5 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Error, no se encontraron todos los parametros necesarios." .size .L.str.4, 58 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "r" .size .L.str.5, 2 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "%d" .size .L.str.6, 3 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "Error los tama\303\261os de las matrices no son compatibles." .size .L.str.7, 55 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "Imposible asignar memoria para d_m1" .size .L.str.8, 36 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "Imposible asignar memoria para d_m2" .size .L.str.9, 36 .type .L.str.10,@object # @.str.10 .L.str.10: .asciz "Imposible asignar memoria para d_m3" .size .L.str.10, 36 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z21multiplicationKernellPfS_S_ii" .size .L__unnamed_1, 34 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "----------MATRIX----------" .size .Lstr, 27 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z36__device_stub__multiplicationKernellPfS_S_ii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z21multiplicationKernellPfS_S_ii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include<cuda.h> #include<stdio.h> #include<cuda_runtime.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams cudaEvent_t start, stop; cudaEventCreate(&start); cudaEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation cudaMalloc((void**)&d_A, BufferSize); cudaMalloc((void**)&d_B, BufferSize); cudaMalloc((void**)&d_C, BufferSize); cudaEventRecord(start); // Copy data from Host to Device cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice); cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost); cudaEventRecord(stop); cudaEventSynchronize(stop); float time; cudaEventElapsedTime(&time, start, stop); cudaEventDestroy(start); cudaEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
code for sm_80 Function : _Z13matrixMulGmemPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */ /* 0x000e220000002600 */ /*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */ /* 0x000fe20000000f00 */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */ /* 0x000fe200000001ff */ /*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */ /* 0x000e220000002200 */ /*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fc60003f06270 */ /*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e680000002500 */ /*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e620000002100 */ /*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */ /* 0x001fc800078e0205 */ /*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */ /* 0x000fe400078e02ff */ /*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */ /* 0x002fe200078e0203 */ /*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */ /* 0x000fea0003800000 */ /*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */ /* 0x040fe40007ffe0ff */ /*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */ /* 0x000fe400078ec0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */ /* 0x000fe40003f06070 */ /*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */ /* 0x000fe40000000f00 */ /*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fd20000000f00 */ /*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */ /* 0x000fea0003800000 */ /*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */ /* 0x000fe20007ffe1ff */ /*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */ /* 0x000fe200000001ff */ /*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */ /* 0x000fe40000000f00 */ /*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fcc0003f04270 */ /*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */ /* 0x000fce00078e0219 */ /*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */ /* 0x000fea0003800000 */ /*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe40003f24270 */ /*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */ /* 0x000fea0003800000 */ /*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */ /* 0x000fe20008000f00 */ /*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */ /* 0x0000a2000c1e1900 */ /*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */ /* 0x000fca0008000f00 */ /*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */ /* 0x000fca00078e020c */ /*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */ /* 0x000ea2000c1e1900 */ /*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */ /* 0x000fc600078e0218 */ /*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */ /* 0x000ee6000c1e1900 */ /*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */ /* 0x040fe200078e020a */ /*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */ /* 0x0002e8000c1e1900 */ /*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */ /* 0x000f22000c1e1900 */ /*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */ /* 0x000fc600078e0212 */ /*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x000b26000c1e1900 */ /*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */ /* 0x040fe200078e020e */ /*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */ /* 0x000128000c1e1900 */ /*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */ /* 0x000f28000c1e1900 */ /*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */ /* 0x020f22000c1e1900 */ /*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */ /* 0x001fc600078e0214 */ /*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */ /* 0x000166000c1e1900 */ /*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */ /* 0x040fe200078e020e */ /*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */ /* 0x000168000c1e1900 */ /*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */ /* 0x002f62000c1e1900 */ /*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */ /* 0x000fc600078e0216 */ /*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */ /* 0x000368000c1e1900 */ /*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */ /* 0x001f62000c1e1900 */ /*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */ /* 0x004fc600078e021c */ /*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */ /* 0x000ea8000c1e1900 */ /*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */ /* 0x0000a2000c1e1900 */ /*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */ /* 0x000fc800078e0218 */ /*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */ /* 0x008fe400078e021d */ /*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */ /* 0x000fe400078e020e */ /*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x0006a4000c1e1900 */ /*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */ /* 0x010fe400078e021d */ /*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */ /* 0x000fe400078e0210 */ /*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x0008a4000c1e1900 */ /*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */ /* 0x000fc400078e021d */ /*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */ /* 0x042fe200078e0212 */ /*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */ /* 0x000ea8000c1e1900 */ /*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */ /* 0x000ea2000c1e1900 */ /*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */ /* 0x001fc600078e0216 */ /*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x0000a2000c1e1900 */ /*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */ /* 0x020fc600078e021a */ /*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */ /* 0x000f62000c1e1900 */ /*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */ /* 0x000fe400078e0209 */ /*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */ /* 0x000fe200078e0218 */ /*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */ /* 0x000368000c1e1900 */ /*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */ /* 0x010f22000c1e1900 */ /*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */ /* 0x000fc600078e020b */ /*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */ /* 0x008722000c1e1900 */ /*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */ /* 0x000fc600078e0208 */ /*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */ /* 0x001128000c1e1900 */ /*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */ /* 0x002f28000c1e1900 */ /*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */ /* 0x008ee8000c1e1900 */ /*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */ /* 0x000ee8000c1e1900 */ /*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */ /* 0x001ee2000c1e1900 */ /*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */ /* 0x004fc600078e0215 */ /*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */ /* 0x000ea2000c1e1900 */ /*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */ /* 0x000fca00078e020a */ /*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */ /* 0x000ea2000c1e1900 */ /*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */ /* 0x000fc80007ffe0ff */ /*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe20003f24270 */ /*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */ /* 0x000fc800078e0209 */ /*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */ /* 0x000fc800078e0207 */ /*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */ /* 0x020fc800078e0207 */ /*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */ /* 0x010fe200078e0207 */ /*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff1e03f */ /*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */ /* 0x000fc60007ffe0ff */ /*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */ /* 0x008fc800078e0207 */ /*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */ /* 0x004fc800078e0207 */ /*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */ /* 0x000fe400078e021c */ /*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */ /* 0x000fc800078e0214 */ /*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */ /* 0x000fe200078e021c */ /*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */ /* 0x000fea000383ffff */ /*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */ /* 0x000fda0003f24270 */ /*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */ /* 0x000fea0003800000 */ /*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */ /* 0x000fe200078e0218 */ /*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */ /* 0x0000a2000c1e1900 */ /*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fc60008000f00 */ /*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */ /* 0x000fe200078e0210 */ /*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */ /* 0x0002e6000c1e1900 */ /*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */ /* 0x000fe200078e0208 */ /*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */ /* 0x000966000c1e1900 */ /*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */ /* 0x040fe200078e020c */ /*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */ /* 0x000ea8000c1e1900 */ /*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */ /* 0x000ee2000c1e1900 */ /*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */ /* 0x000fc600078e020e */ /*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */ /* 0x000f66000c1e1900 */ /*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */ /* 0x042fe200078e020a */ /*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000368000c1e1900 */ /*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */ /* 0x000f62000c1e1900 */ /*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */ /* 0x000fc600078e0210 */ /*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */ /* 0x000368000c1e1900 */ /*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */ /* 0x001f62000c1e1900 */ /*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */ /* 0x010fc600078e0212 */ /*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x000f28000c1e1900 */ /*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */ /* 0x000f28000c1e1900 */ /*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */ /* 0x000128000c1e1900 */ /*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */ /* 0x002f28000c1e1900 */ /*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */ /* 0x000f28000c1e1900 */ /*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */ /* 0x001f22000c1e1900 */ /*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */ /* 0x000fe2000ff1e03f */ /*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */ /* 0x000fe40007ffe0ff */ /*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */ /* 0x000fe20007ffe0ff */ /*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */ /* 0x004fc800078e021c */ /*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */ /* 0x008fc800078e0207 */ /*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */ /* 0x020fc800078e0207 */ /*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */ /* 0x000fc800078e0207 */ /*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */ /* 0x000fc800078e0207 */ /*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */ /* 0x010fc800078e0207 */ /*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */ /* 0x000fe400078e0207 */ /*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */ /* 0x000fc800078e020c */ /*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */ /* 0x000fe400078e0207 */ /*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0000705670 */ /*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */ /* 0x000fea0003800000 */ /*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */ /* 0x000fe200078e0218 */ /*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fe20008000f00 */ /*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */ /* 0x000ea8000c1e1900 */ /*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */ /* 0x000fc800078e0208 */ /*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */ /* 0x040fe200078e020e */ /*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea8000c1e1900 */ /*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000ee2000c1e1900 */ /*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */ /* 0x000fc600078e020c */ /*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x000f28000c1e1900 */ /*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */ /* 0x000f28000c1e1900 */ /*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */ /* 0x000f68000c1e1900 */ /*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */ /* 0x000f62000c1e1900 */ /*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */ /* 0x000fc80007ffe0ff */ /*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe20003f05270 */ /*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */ /* 0x000fe2000ff1e03f */ /*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */ /* 0x000fc60007ffe0ff */ /*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */ /* 0x004fc800078e021c */ /*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */ /* 0x008fe400078e0207 */ /*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */ /* 0x000fc800078e020a */ /*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */ /* 0x010fc800078e0207 */ /*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */ /* 0x020fe200078e0207 */ /*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */ /* 0x000fea000383ffff */ /*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f05270 */ /*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */ /* 0x000fea0003800000 */ /*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */ /* 0x000fe200000001ff */ /*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */ /* 0x000fe20007ffe0ff */ /*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */ /* 0x000fd000078e0202 */ /*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fc800078e0208 */ /*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */ /* 0x000fe200078e0208 */ /*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */ /* 0x000fc80000000f00 */ /*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */ /* 0x000fe20000000f00 */ /*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */ /* 0x0000aa000c1e1900 */ /*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x0002a2000c1e1900 */ /*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */ /* 0x000fe40007ffe0ff */ /*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */ /* 0x000fc40007f3e0ff */ /*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */ /* 0x001fe200078e0208 */ /*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x002fc60000ffe4ff */ /*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */ /* 0x004fd000078e021c */ /*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */ /* 0x000fea000383ffff */ /*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */ /* 0x000fe40007ffe0ff */ /*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */ /* 0x000fca0000000f00 */ /*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */ /* 0x000fca00078e0203 */ /*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */ /* 0x000fe2000c101904 */ /*0c20*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0c40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ca0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ce0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include<cuda.h> #include<stdio.h> #include<cuda_runtime.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams cudaEvent_t start, stop; cudaEventCreate(&start); cudaEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation cudaMalloc((void**)&d_A, BufferSize); cudaMalloc((void**)&d_B, BufferSize); cudaMalloc((void**)&d_C, BufferSize); cudaEventRecord(start); // Copy data from Host to Device cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice); cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost); cudaEventRecord(stop); cudaEventSynchronize(stop); float time; cudaEventElapsedTime(&time, start, stop); cudaEventDestroy(start); cudaEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
.file "tmpxft_0016a9ef_00000000-6_matrixMulGmem.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z9matricMulPiS_S_i .type _Z9matricMulPiS_S_i, @function _Z9matricMulPiS_S_i: .LFB2057: .cfi_startproc endbr64 testl %ecx, %ecx jle .L11 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r8 movq %rsi, %r12 movq %rdx, %rbp movl %ecx, %ebx movslq %ecx, %rdi salq $2, %rdi movq %r8, %r11 addq %rdi, %r8 movl $0, %r13d movl $0, %r14d jmp .L5 .L8: movl %eax, %r10d .L7: movq %r9, %rcx movq %r11, %rax .L6: movl (%rax), %edx imull (%rcx), %edx addl %edx, (%rsi) addq $4, %rax addq %rdi, %rcx cmpq %r8, %rax jne .L6 leal 1(%r10), %eax addq $4, %r9 addq $4, %rsi cmpl %eax, %ebx jne .L8 leal 1(%r13), %eax addq %rdi, %r11 addq %rdi, %r8 addq %rdi, %rbp cmpl %r10d, %r13d je .L3 movl %eax, %r13d .L5: movq %r12, %r9 movq %rbp, %rsi movl %r14d, %r10d jmp .L7 .L3: popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L11: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2057: .size _Z9matricMulPiS_S_i, .-_Z9matricMulPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Matrix Multiplication Error!\n" .LC2: .string "Matrix Multiplication OK!\n" .text .globl _Z14matrixMulCheckPiS_i .type _Z14matrixMulCheckPiS_i, @function _Z14matrixMulCheckPiS_i: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 testl %edx, %edx jle .L15 movslq %edx, %rdx movl $0, %r8d .L18: movl (%rdi,%r8,4), %ecx movl (%rsi,%r8,4), %r9d cmpl %r9d, %ecx jne .L21 addq $1, %r8 cmpq %rdx, %r8 jne .L18 .L15: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L14: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movl %r8d, %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L14 .cfi_endproc .LFE2058: .size _Z14matrixMulCheckPiS_i, .-_Z14matrixMulCheckPiS_i .globl _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i .type _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i, @function _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L26 .L22: movq 136(%rsp), %rax subq %fs:40, %rax jne .L27 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13matrixMulGmemPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L22 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i .globl _Z13matrixMulGmemPiS_S_i .type _Z13matrixMulGmemPiS_S_i, @function _Z13matrixMulGmemPiS_S_i: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z13matrixMulGmemPiS_S_i, .-_Z13matrixMulGmemPiS_S_i .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $88, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 56(%rsp) movl $50, 60(%rsp) movl $100, 64(%rsp) movl $1, 68(%rsp) leaq 8(%rsp), %rdi call cudaEventCreate@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT movl $10240000, %edi call malloc@PLT movq %rax, %r13 movl $10240000, %edi call malloc@PLT movq %rax, %r12 movl $10240000, %edi call malloc@PLT movq %rax, %rbp movl $10240000, %edi call malloc@PLT movq %rax, %rbx movl $0, %edx .L31: movslq %edx, %rax imulq $1374389535, %rax, %rax sarq $37, %rax movl %edx, %ecx sarl $31, %ecx subl %ecx, %eax imull $100, %eax, %ecx movl %edx, %eax subl %ecx, %eax movl %eax, 0(%r13,%rdx,4) movl %eax, (%r12,%rdx,4) movl $0, 0(%rbp,%rdx,4) movl $0, (%rbx,%rdx,4) addq $1, %rdx cmpq $2560000, %rdx jne .L31 leaq 24(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT movl $0, %esi movq 8(%rsp), %rdi call cudaEventRecord@PLT movl $1, %ecx movl $10240000, %edx movq %r13, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $10240000, %edx movq %r12, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $32, 48(%rsp) movl $16, 52(%rsp) movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L36 .L32: movl $2, %ecx movl $10240000, %edx movq 40(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movq 16(%rsp), %rdi call cudaEventSynchronize@PLT leaq 4(%rsp), %rdi movq 16(%rsp), %rdx movq 8(%rsp), %rsi call cudaEventElapsedTime@PLT movq 8(%rsp), %rdi call cudaEventDestroy@PLT movq 16(%rsp), %rdi call cudaEventDestroy@PLT movl $1600, %ecx movq %rbx, %rdx movq %r12, %rsi movq %r13, %rdi call _Z9matricMulPiS_S_i movl $1600, %edx movq %rbp, %rsi movq %rbx, %rdi call _Z14matrixMulCheckPiS_i movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state movl $1600, %ecx movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i jmp .L32 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z13matrixMulGmemPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z13matrixMulGmemPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include<cuda.h> #include<stdio.h> #include<cuda_runtime.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams cudaEvent_t start, stop; cudaEventCreate(&start); cudaEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation cudaMalloc((void**)&d_A, BufferSize); cudaMalloc((void**)&d_B, BufferSize); cudaMalloc((void**)&d_C, BufferSize); cudaEventRecord(start); // Copy data from Host to Device cudaMemcpy(d_A, h_A, BufferSize, cudaMemcpyHostToDevice); cudaMemcpy(d_B, h_B, BufferSize, cudaMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host cudaMemcpy(h_C, d_C, BufferSize, cudaMemcpyDeviceToHost); cudaEventRecord(stop); cudaEventSynchronize(stop); float time; cudaEventElapsedTime(&time, start, stop); cudaEventDestroy(start); cudaEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
#include<hip/hip_runtime.h> #include<stdio.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams hipEvent_t start, stop; hipEventCreate(&start); hipEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation hipMalloc((void**)&d_A, BufferSize); hipMalloc((void**)&d_B, BufferSize); hipMalloc((void**)&d_C, BufferSize); hipEventRecord(start); // Copy data from Host to Device hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice); hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost); hipEventRecord(stop); hipEventSynchronize(stop); float time; hipEventElapsedTime(&time, start, stop); hipEventDestroy(start); hipEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory hipFree(d_A); hipFree(d_B); hipFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include<hip/hip_runtime.h> #include<stdio.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams hipEvent_t start, stop; hipEventCreate(&start); hipEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation hipMalloc((void**)&d_A, BufferSize); hipMalloc((void**)&d_B, BufferSize); hipMalloc((void**)&d_C, BufferSize); hipEventRecord(start); // Copy data from Host to Device hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice); hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost); hipEventRecord(stop); hipEventSynchronize(stop); float time; hipEventElapsedTime(&time, start, stop); hipEventDestroy(start); hipEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory hipFree(d_A); hipFree(d_B); hipFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13matrixMulGmemPiS_S_i .globl _Z13matrixMulGmemPiS_S_i .p2align 8 .type _Z13matrixMulGmemPiS_S_i,@function _Z13matrixMulGmemPiS_S_i: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s3, 16 s_and_b32 s3, s3, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2] v_and_b32_e32 v3, 0x3ff, v0 s_cmp_lt_i32 s2, 1 v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4] s_delay_alu instid0(VALU_DEP_3) v_mul_lo_u32 v1, v2, s2 s_cbranch_scc1 .LBB0_3 s_load_b128 s[4:7], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s3, s2 v_mov_b32_e32 v5, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[3:4], 2, v[1:2] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo .p2align 6 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v6, 31, v5 s_add_i32 s3, s3, -1 s_cmp_eq_u32 s3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[5:6] v_add_co_u32 v6, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo global_load_b32 v8, v[3:4], off global_load_b32 v9, v[6:7], off s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3] v_add_co_u32 v3, vcc_lo, v3, 4 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5 s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v2, 0 .LBB0_4: s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13matrixMulGmemPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13matrixMulGmemPiS_S_i, .Lfunc_end0-_Z13matrixMulGmemPiS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13matrixMulGmemPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13matrixMulGmemPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include<hip/hip_runtime.h> #include<stdio.h> void matricMul(int *A, int *B, int *C, int size) { for (int col = 0; col < size; col++) { for (int row = 0; row < size; row++) { int outidx = col * size + row; for (int idx = 0; idx < size; idx++) { C[outidx] += A[col*size + idx] * B[idx*size + row]; } } } } void matrixMulCheck(int *C_cpu, int *C_gpu, int size) { bool ResultFlag = true; // Print the result for (int i = 0; i < size; i++) { if (C_cpu[i] != C_gpu[i]) { ResultFlag = false; printf("Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n", i, C_cpu[i], i, C_gpu[i]); break; } } if (ResultFlag == true) printf("Matrix Multiplication OK!\n"); else printf("Matrix Multiplication Error!\n"); } __global__ void matrixMulGmem(int *A, int *B, int *C, int size) { int tid, tx, ty; tx = threadIdx.x + blockDim.x * blockIdx.x; ty = threadIdx.y + blockDim.y * blockIdx.y; tid = size * ty + tx; int Aval = 0; int Bval = 0; int Cval = 0; for (int i = 0; i < size; i++) { Aval = A[ty * size + i]; Bval = B[i * size + tx]; Cval += Aval * Bval; } C[tid] = Cval; } int main() { int nx = 1600; int ny = 1600; int dimx = 32; int dimy = 16; dim3 block(dimx, dimy); // Block dimension 32x16 dim3 grid((nx+block.x-1)/block.x, (ny+block.y-1)/block.y); int MatrixSize = nx * ny; int BufferSize = MatrixSize * sizeof(int); // Create events and streams hipEvent_t start, stop; hipEventCreate(&start); hipEventCreate(&stop); int *h_A, *h_B, *h_C; int *C_cpu; // Host memory allocation h_A = (int*)malloc(BufferSize); h_B = (int*)malloc(BufferSize); h_C = (int*)malloc(BufferSize); C_cpu = (int*)malloc(BufferSize); // Data input for (int i = 0; i < MatrixSize; i++) { h_A[i] = i % 100; h_B[i] = i % 100; h_C[i] = 0; C_cpu[i] = 0; } int *d_A, *d_B, *d_C; // Device memory allocation hipMalloc((void**)&d_A, BufferSize); hipMalloc((void**)&d_B, BufferSize); hipMalloc((void**)&d_C, BufferSize); hipEventRecord(start); // Copy data from Host to Device hipMemcpy(d_A, h_A, BufferSize, hipMemcpyHostToDevice); hipMemcpy(d_B, h_B, BufferSize, hipMemcpyHostToDevice); // Matrix Multiplication using only the global memory matrixMulGmem<<<grid, block>>>(d_A, d_B, d_C, nx); // Copy result from Device to Host hipMemcpy(h_C, d_C, BufferSize, hipMemcpyDeviceToHost); hipEventRecord(stop); hipEventSynchronize(stop); float time; hipEventElapsedTime(&time, start, stop); hipEventDestroy(start); hipEventDestroy(stop); // Check result matricMul(h_A, h_B, C_cpu, nx); matrixMulCheck(C_cpu, h_C, nx); // Free memory hipFree(d_A); hipFree(d_B); hipFree(d_C); free(h_A); free(h_B); free(h_C); free(C_cpu); return 0; }
.text .file "matrixMulGmem.hip" .globl _Z9matricMulPiS_S_i # -- Begin function _Z9matricMulPiS_S_i .p2align 4, 0x90 .type _Z9matricMulPiS_S_i,@function _Z9matricMulPiS_S_i: # @_Z9matricMulPiS_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, -8(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB0_7 # %bb.1: # %.preheader.lr.ph movl %ecx, %eax leaq (,%rax,4), %r8 xorl %edx, %edx xorl %r10d, %r10d .p2align 4, 0x90 .LBB0_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB0_3 Depth 2 # Child Loop BB0_4 Depth 3 movl %edx, %r11d leaq (%rdi,%r11,4), %r11 movq %r10, %rbx imulq %rax, %rbx movq -8(%rsp), %r9 # 8-byte Reload leaq (%r9,%rbx,4), %rbx movq %rsi, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_3: # %.lr.ph # Parent Loop BB0_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_4 Depth 3 movl (%rbx,%r15,4), %ebp movq %r14, %r12 xorl %r13d, %r13d .p2align 4, 0x90 .LBB0_4: # Parent Loop BB0_2 Depth=1 # Parent Loop BB0_3 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r12), %r9d imull (%r11,%r13,4), %r9d addl %r9d, %ebp movl %ebp, (%rbx,%r15,4) incq %r13 addq %r8, %r12 cmpq %r13, %rax jne .LBB0_4 # %bb.5: # %._crit_edge # in Loop: Header=BB0_3 Depth=2 incq %r15 addq $4, %r14 cmpq %rax, %r15 jne .LBB0_3 # %bb.6: # %._crit_edge27 # in Loop: Header=BB0_2 Depth=1 incq %r10 addl %ecx, %edx cmpq %rax, %r10 jne .LBB0_2 .LBB0_7: # %._crit_edge29 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z9matricMulPiS_S_i, .Lfunc_end0-_Z9matricMulPiS_S_i .cfi_endproc # -- End function .globl _Z14matrixMulCheckPiS_i # -- Begin function _Z14matrixMulCheckPiS_i .p2align 4, 0x90 .type _Z14matrixMulCheckPiS_i,@function _Z14matrixMulCheckPiS_i: # @_Z14matrixMulCheckPiS_i .cfi_startproc # %bb.0: movq %rdi, %rax movl $.Lstr.1, %edi testl %edx, %edx jle puts@PLT # TAILCALL # %bb.1: # %.lr.ph.preheader movl %edx, %r9d xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rax,%rcx,4), %edx movl (%rsi,%rcx,4), %r8d cmpl %r8d, %edx jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=1 incq %rcx cmpq %rcx, %r9 jne .LBB1_2 # %bb.5: # %.critedge jmp puts@PLT # TAILCALL .LBB1_3: pushq %rax .cfi_def_cfa_offset 16 movl $.L.str, %edi movl %ecx, %esi # kill: def $ecx killed $ecx killed $rcx xorl %eax, %eax callq printf movl $.Lstr, %edi addq $8, %rsp .cfi_def_cfa_offset 8 jmp puts@PLT # TAILCALL .Lfunc_end1: .size _Z14matrixMulCheckPiS_i, .Lfunc_end1-_Z14matrixMulCheckPiS_i .cfi_endproc # -- End function .globl _Z28__device_stub__matrixMulGmemPiS_S_i # -- Begin function _Z28__device_stub__matrixMulGmemPiS_S_i .p2align 4, 0x90 .type _Z28__device_stub__matrixMulGmemPiS_S_i,@function _Z28__device_stub__matrixMulGmemPiS_S_i: # @_Z28__device_stub__matrixMulGmemPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13matrixMulGmemPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z28__device_stub__matrixMulGmemPiS_S_i, .Lfunc_end2-_Z28__device_stub__matrixMulGmemPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $160, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %rbx movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r14 movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r15 movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r12 xorl %r13d, %r13d movl $10240000, %edx # imm = 0x9C4000 movq %r15, %rdi xorl %esi, %esi callq memset@PLT movl $10240000, %edx # imm = 0x9C4000 movq %r12, %rdi xorl %esi, %esi callq memset@PLT .p2align 4, 0x90 .LBB3_1: # =>This Inner Loop Header: Depth=1 movl %r13d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $37, %rax imull $100, %eax, %eax movl %r13d, %ecx subl %eax, %ecx movl %ecx, (%rbx,%r13,4) movl %ecx, (%r14,%r13,4) incq %r13 cmpq $2560000, %r13 # imm = 0x271000 jne .LBB3_1 # %bb.2: leaq 32(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc leaq 24(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc leaq 16(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc movq 40(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi movl $10240000, %edx # imm = 0x9C4000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $10240000, %edx # imm = 0x9C4000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $429496729650, %rdi # imm = 0x6400000032 movabsq $68719476768, %rdx # imm = 0x1000000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 120(%rsp) movq %rcx, 112(%rsp) movq %rdx, 104(%rsp) movl $1600, 52(%rsp) # imm = 0x640 leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 52(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z13matrixMulGmemPiS_S_i, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_4: movq 16(%rsp), %rsi movl $10240000, %edx # imm = 0x9C4000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi xorl %r13d, %r13d xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 40(%rsp), %rsi movq 8(%rsp), %rdx leaq 128(%rsp), %rdi callq hipEventElapsedTime movq 40(%rsp), %rdi callq hipEventDestroy movq 8(%rsp), %rdi callq hipEventDestroy movq %rbx, %rax .p2align 4, 0x90 .LBB3_5: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 # Child Loop BB3_7 Depth 3 imulq $6400, %r13, %rcx # imm = 0x1900 addq %r12, %rcx movq %r14, %rdx xorl %esi, %esi .p2align 4, 0x90 .LBB3_6: # %.lr.ph.i # Parent Loop BB3_5 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_7 Depth 3 movl (%rcx,%rsi,4), %edi movq %rdx, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_7: # Parent Loop BB3_5 Depth=1 # Parent Loop BB3_6 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r8), %r10d imull (%rax,%r9,4), %r10d addl %r10d, %edi incq %r9 addq $6400, %r8 # imm = 0x1900 cmpq $1600, %r9 # imm = 0x640 jne .LBB3_7 # %bb.8: # %._crit_edge.i # in Loop: Header=BB3_6 Depth=2 movl %edi, (%rcx,%rsi,4) incq %rsi addq $4, %rdx cmpq $1600, %rsi # imm = 0x640 jne .LBB3_6 # %bb.9: # %._crit_edge27.i # in Loop: Header=BB3_5 Depth=1 incq %r13 addq $6400, %rax # imm = 0x1900 cmpq $1600, %r13 # imm = 0x640 jne .LBB3_5 # %bb.10: # %.lr.ph.i50.preheader xorl %ecx, %ecx .p2align 4, 0x90 .LBB3_11: # %.lr.ph.i50 # =>This Inner Loop Header: Depth=1 movl (%r12,%rcx,4), %edx movl (%r15,%rcx,4), %r8d cmpl %r8d, %edx jne .LBB3_12 # %bb.13: # in Loop: Header=BB3_11 Depth=1 incq %rcx cmpq $1600, %rcx # imm = 0x640 jne .LBB3_11 # %bb.14: movl $.Lstr.1, %edi jmp .LBB3_15 .LBB3_12: movl $.L.str, %edi movl %ecx, %esi # kill: def $ecx killed $ecx killed $rcx xorl %eax, %eax callq printf movl $.Lstr, %edi .LBB3_15: # %_Z14matrixMulCheckPiS_i.exit callq puts@PLT movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r12, %rdi callq free xorl %eax, %eax addq $160, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13matrixMulGmemPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error: C_cpu[%d] = %d .size .L.str, 40 .type _Z13matrixMulGmemPiS_S_i,@object # @_Z13matrixMulGmemPiS_S_i .section .rodata,"a",@progbits .globl _Z13matrixMulGmemPiS_S_i .p2align 3, 0x0 _Z13matrixMulGmemPiS_S_i: .quad _Z28__device_stub__matrixMulGmemPiS_S_i .size _Z13matrixMulGmemPiS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13matrixMulGmemPiS_S_i" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Matrix Multiplication Error!" .size .Lstr, 29 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Matrix Multiplication OK!" .size .Lstr.1, 26 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__matrixMulGmemPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13matrixMulGmemPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z13matrixMulGmemPiS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */ /* 0x000e220000002600 */ /*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */ /* 0x000fe20000000f00 */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */ /* 0x000fe200000001ff */ /*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */ /* 0x000e220000002200 */ /*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fc60003f06270 */ /*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e680000002500 */ /*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */ /* 0x000e620000002100 */ /*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */ /* 0x001fc800078e0205 */ /*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */ /* 0x000fe400078e02ff */ /*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */ /* 0x002fe200078e0203 */ /*00c0*/ @!P0 BRA 0xbe0 ; /* 0x00000b1000008947 */ /* 0x000fea0003800000 */ /*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */ /* 0x040fe40007ffe0ff */ /*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */ /* 0x000fe400078ec0ff */ /*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */ /* 0x000fe40003f06070 */ /*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */ /* 0x000fe40000000f00 */ /*0110*/ MOV R28, RZ ; /* 0x000000ff001c7202 */ /* 0x000fd20000000f00 */ /*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */ /* 0x000fea0003800000 */ /*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */ /* 0x000fe20007ffe1ff */ /*0140*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */ /* 0x000fe200000001ff */ /*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */ /* 0x000fe20000000a00 */ /*0160*/ MOV R3, RZ ; /* 0x000000ff00037202 */ /* 0x000fe40000000f00 */ /*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fcc0003f04270 */ /*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */ /* 0x000fce00078e0219 */ /*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */ /* 0x000fea0003800000 */ /*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe40003f24270 */ /*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fd60003f0f070 */ /*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */ /* 0x000fea0003800000 */ /*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fe40003f0e170 */ /*01e0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */ /* 0x000fe20008000f00 */ /*01f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */ /* 0x0000a2000c1e1900 */ /*0200*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */ /* 0x000fca0008000f00 */ /*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */ /* 0x000fca00078e020c */ /*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */ /* 0x000ea2000c1e1900 */ /*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */ /* 0x000fc600078e0218 */ /*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */ /* 0x000ee6000c1e1900 */ /*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */ /* 0x040fe200078e020a */ /*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */ /* 0x0002e8000c1e1900 */ /*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */ /* 0x000f22000c1e1900 */ /*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */ /* 0x000fc600078e0212 */ /*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x000b26000c1e1900 */ /*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */ /* 0x040fe200078e020e */ /*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */ /* 0x000128000c1e1900 */ /*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */ /* 0x000f28000c1e1900 */ /*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */ /* 0x020f22000c1e1900 */ /*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */ /* 0x001fc600078e0214 */ /*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */ /* 0x000166000c1e1900 */ /*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */ /* 0x040fe200078e020e */ /*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */ /* 0x000168000c1e1900 */ /*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */ /* 0x002f62000c1e1900 */ /*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */ /* 0x000fc600078e0216 */ /*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */ /* 0x000368000c1e1900 */ /*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */ /* 0x001f62000c1e1900 */ /*0360*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */ /* 0x004fc600078e021c */ /*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */ /* 0x000ea8000c1e1900 */ /*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */ /* 0x0000a2000c1e1900 */ /*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */ /* 0x000fc800078e0218 */ /*03a0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */ /* 0x008fe400078e021d */ /*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */ /* 0x000fe400078e020e */ /*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x0006a4000c1e1900 */ /*03d0*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */ /* 0x010fe400078e021d */ /*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */ /* 0x000fe400078e0210 */ /*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x0008a4000c1e1900 */ /*0400*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */ /* 0x000fc400078e021d */ /*0410*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */ /* 0x042fe200078e0212 */ /*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */ /* 0x000ea8000c1e1900 */ /*0430*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */ /* 0x000ea2000c1e1900 */ /*0440*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */ /* 0x001fc600078e0216 */ /*0450*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */ /* 0x0000a2000c1e1900 */ /*0460*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */ /* 0x020fc600078e021a */ /*0470*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */ /* 0x000f62000c1e1900 */ /*0480*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */ /* 0x000fe400078e0209 */ /*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */ /* 0x000fe200078e0218 */ /*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */ /* 0x000368000c1e1900 */ /*04b0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */ /* 0x010f22000c1e1900 */ /*04c0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */ /* 0x000fc600078e020b */ /*04d0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */ /* 0x008722000c1e1900 */ /*04e0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */ /* 0x000fc600078e0208 */ /*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */ /* 0x001128000c1e1900 */ /*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */ /* 0x002f28000c1e1900 */ /*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */ /* 0x008ee8000c1e1900 */ /*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */ /* 0x000ee8000c1e1900 */ /*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */ /* 0x001ee2000c1e1900 */ /*0540*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */ /* 0x004fc600078e0215 */ /*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */ /* 0x000ea2000c1e1900 */ /*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */ /* 0x000fca00078e020a */ /*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */ /* 0x000ea2000c1e1900 */ /*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */ /* 0x000fc80007ffe0ff */ /*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */ /* 0x000fe20003f24270 */ /*05a0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */ /* 0x000fc800078e0209 */ /*05b0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */ /* 0x000fc800078e0207 */ /*05c0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */ /* 0x020fc800078e0207 */ /*05d0*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */ /* 0x010fe200078e0207 */ /*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */ /* 0x000fe2000ff1e03f */ /*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */ /* 0x000fc60007ffe0ff */ /*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0610*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */ /* 0x008fc800078e0207 */ /*0620*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */ /* 0x004fc800078e0207 */ /*0630*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */ /* 0x000fe400078e021c */ /*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */ /* 0x000fc800078e0214 */ /*0650*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */ /* 0x000fe200078e021c */ /*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */ /* 0x000fea000383ffff */ /*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */ /* 0x000fda0003f24270 */ /*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */ /* 0x000fea0003800000 */ /*0690*/ IMAD.WIDE R16, R0, 0x4, R24 ; /* 0x0000000400107825 */ /* 0x000fe200078e0218 */ /*06a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*06b0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */ /* 0x0000a2000c1e1900 */ /*06c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fc60008000f00 */ /*06d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */ /* 0x000fe200078e0210 */ /*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */ /* 0x0002e6000c1e1900 */ /*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */ /* 0x000fe200078e0208 */ /*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */ /* 0x000966000c1e1900 */ /*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */ /* 0x040fe200078e020c */ /*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */ /* 0x000ea8000c1e1900 */ /*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */ /* 0x000ee2000c1e1900 */ /*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */ /* 0x000fc600078e020e */ /*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */ /* 0x000f66000c1e1900 */ /*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */ /* 0x042fe200078e020a */ /*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000368000c1e1900 */ /*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */ /* 0x000f62000c1e1900 */ /*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */ /* 0x000fc600078e0210 */ /*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */ /* 0x000368000c1e1900 */ /*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */ /* 0x001f62000c1e1900 */ /*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */ /* 0x010fc600078e0212 */ /*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */ /* 0x000f28000c1e1900 */ /*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */ /* 0x000f28000c1e1900 */ /*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */ /* 0x000128000c1e1900 */ /*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */ /* 0x002f28000c1e1900 */ /*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */ /* 0x000f28000c1e1900 */ /*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */ /* 0x001f22000c1e1900 */ /*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */ /* 0x000fe2000ff1e03f */ /*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */ /* 0x000fc40003f0e170 */ /*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */ /* 0x000fe40007ffe0ff */ /*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */ /* 0x000fe20007ffe0ff */ /*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0880*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */ /* 0x004fc800078e021c */ /*0890*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */ /* 0x008fc800078e0207 */ /*08a0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */ /* 0x020fc800078e0207 */ /*08b0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */ /* 0x000fc800078e0207 */ /*08c0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */ /* 0x000fc800078e0207 */ /*08d0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */ /* 0x010fc800078e0207 */ /*08e0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */ /* 0x000fe400078e0207 */ /*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */ /* 0x000fc800078e020c */ /*0900*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */ /* 0x000fe400078e0207 */ /*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0000705670 */ /*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */ /* 0x000fea0003800000 */ /*0930*/ MOV R8, UR6 ; /* 0x0000000600087c02 */ /* 0x000fe20008000f00 */ /*0940*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */ /* 0x000fe200078e0218 */ /*0950*/ MOV R9, UR7 ; /* 0x0000000700097c02 */ /* 0x000fe20008000f00 */ /*0960*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */ /* 0x000ea8000c1e1900 */ /*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */ /* 0x000fc800078e0208 */ /*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */ /* 0x040fe200078e020e */ /*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */ /* 0x000ea8000c1e1900 */ /*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */ /* 0x000ee2000c1e1900 */ /*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */ /* 0x000fc600078e020c */ /*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */ /* 0x000ee8000c1e1900 */ /*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */ /* 0x000f28000c1e1900 */ /*09e0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */ /* 0x000f28000c1e1900 */ /*09f0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */ /* 0x000f68000c1e1900 */ /*0a00*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */ /* 0x000f62000c1e1900 */ /*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */ /* 0x000fc80007ffe0ff */ /*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */ /* 0x000fe20003f05270 */ /*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */ /* 0x000fe2000ff1e03f */ /*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */ /* 0x000fc60007ffe0ff */ /*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */ /* 0x000fe200087fe43f */ /*0a60*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */ /* 0x004fc800078e021c */ /*0a70*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */ /* 0x008fe400078e0207 */ /*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */ /* 0x000fc800078e020a */ /*0a90*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */ /* 0x010fc800078e0207 */ /*0aa0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */ /* 0x020fe200078e0207 */ /*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */ /* 0x000fea000383ffff */ /*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fda0003f05270 */ /*0ad0*/ @!P0 BRA 0xbe0 ; /* 0x0000010000008947 */ /* 0x000fea0003800000 */ /*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */ /* 0x000fe200000001ff */ /*0af0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */ /* 0x000fe20007ffe0ff */ /*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */ /* 0x000fd000078e0202 */ /*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fc800078e0208 */ /*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */ /* 0x000fe200078e0208 */ /*0b30*/ MOV R10, R6 ; /* 0x00000006000a7202 */ /* 0x000fc80000000f00 */ /*0b40*/ MOV R6, R10 ; /* 0x0000000a00067202 */ /* 0x000fe20000000f00 */ /*0b50*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */ /* 0x0000aa000c1e1900 */ /*0b60*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */ /* 0x0002a2000c1e1900 */ /*0b70*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */ /* 0x000fe40007ffe0ff */ /*0b80*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */ /* 0x000fc40007f3e0ff */ /*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */ /* 0x000fe20003f05270 */ /*0ba0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */ /* 0x001fe200078e0208 */ /*0bb0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */ /* 0x002fc60000ffe4ff */ /*0bc0*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */ /* 0x004fd000078e021c */ /*0bd0*/ @P0 BRA 0xb40 ; /* 0xffffff6000000947 */ /* 0x000fea000383ffff */ /*0be0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */ /* 0x000fe40007ffe0ff */ /*0bf0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */ /* 0x000fca0000000f00 */ /*0c00*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */ /* 0x000fca00078e0203 */ /*0c10*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */ /* 0x000fe2000c101904 */ /*0c20*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0c30*/ BRA 0xc30; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0c40*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c50*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c60*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c70*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c80*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0c90*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ca0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cb0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cc0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cd0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0ce0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0cf0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z13matrixMulGmemPiS_S_i .globl _Z13matrixMulGmemPiS_S_i .p2align 8 .type _Z13matrixMulGmemPiS_S_i,@function _Z13matrixMulGmemPiS_S_i: s_clause 0x1 s_load_b32 s3, s[0:1], 0x2c s_load_b32 s2, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s3, 16 s_and_b32 s3, s3, 0xffff s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2] v_and_b32_e32 v3, 0x3ff, v0 s_cmp_lt_i32 s2, 1 v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4] s_delay_alu instid0(VALU_DEP_3) v_mul_lo_u32 v1, v2, s2 s_cbranch_scc1 .LBB0_3 s_load_b128 s[4:7], s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_ashrrev_i32_e32 v2, 31, v1 s_mov_b32 s3, s2 v_mov_b32_e32 v5, v0 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_lshlrev_b64 v[3:4], 2, v[1:2] v_mov_b32_e32 v2, 0 s_waitcnt lgkmcnt(0) v_add_co_u32 v3, vcc_lo, s4, v3 s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo .p2align 6 .LBB0_2: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_ashrrev_i32_e32 v6, 31, v5 s_add_i32 s3, s3, -1 s_cmp_eq_u32 s3, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_lshlrev_b64 v[6:7], 2, v[5:6] v_add_co_u32 v6, vcc_lo, s6, v6 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo global_load_b32 v8, v[3:4], off global_load_b32 v9, v[6:7], off s_waitcnt vmcnt(0) v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3] v_add_co_u32 v3, vcc_lo, v3, 4 v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo s_delay_alu instid0(VALU_DEP_3) v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5 s_cbranch_scc0 .LBB0_2 s_branch .LBB0_4 .LBB0_3: v_mov_b32_e32 v2, 0 .LBB0_4: s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v0, v1, v0 v_ashrrev_i32_e32 v1, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[0:1] s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s0, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo global_store_b32 v[0:1], v2, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z13matrixMulGmemPiS_S_i .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 288 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 10 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z13matrixMulGmemPiS_S_i, .Lfunc_end0-_Z13matrixMulGmemPiS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: hidden_block_count_x - .offset: 36 .size: 4 .value_kind: hidden_block_count_y - .offset: 40 .size: 4 .value_kind: hidden_block_count_z - .offset: 44 .size: 2 .value_kind: hidden_group_size_x - .offset: 46 .size: 2 .value_kind: hidden_group_size_y - .offset: 48 .size: 2 .value_kind: hidden_group_size_z - .offset: 50 .size: 2 .value_kind: hidden_remainder_x - .offset: 52 .size: 2 .value_kind: hidden_remainder_y - .offset: 54 .size: 2 .value_kind: hidden_remainder_z - .offset: 72 .size: 8 .value_kind: hidden_global_offset_x - .offset: 80 .size: 8 .value_kind: hidden_global_offset_y - .offset: 88 .size: 8 .value_kind: hidden_global_offset_z - .offset: 96 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 288 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z13matrixMulGmemPiS_S_i .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z13matrixMulGmemPiS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 10 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0016a9ef_00000000-6_matrixMulGmem.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2062: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2062: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z9matricMulPiS_S_i .type _Z9matricMulPiS_S_i, @function _Z9matricMulPiS_S_i: .LFB2057: .cfi_startproc endbr64 testl %ecx, %ecx jle .L11 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 movq %rdi, %r8 movq %rsi, %r12 movq %rdx, %rbp movl %ecx, %ebx movslq %ecx, %rdi salq $2, %rdi movq %r8, %r11 addq %rdi, %r8 movl $0, %r13d movl $0, %r14d jmp .L5 .L8: movl %eax, %r10d .L7: movq %r9, %rcx movq %r11, %rax .L6: movl (%rax), %edx imull (%rcx), %edx addl %edx, (%rsi) addq $4, %rax addq %rdi, %rcx cmpq %r8, %rax jne .L6 leal 1(%r10), %eax addq $4, %r9 addq $4, %rsi cmpl %eax, %ebx jne .L8 leal 1(%r13), %eax addq %rdi, %r11 addq %rdi, %r8 addq %rdi, %rbp cmpl %r10d, %r13d je .L3 movl %eax, %r13d .L5: movq %r12, %r9 movq %rbp, %rsi movl %r14d, %r10d jmp .L7 .L3: popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L11: .cfi_restore 3 .cfi_restore 6 .cfi_restore 12 .cfi_restore 13 .cfi_restore 14 ret .cfi_endproc .LFE2057: .size _Z9matricMulPiS_S_i, .-_Z9matricMulPiS_S_i .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "Error: C_cpu[%d] = %d; C_gpu[%d] = %d;\n" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Matrix Multiplication Error!\n" .LC2: .string "Matrix Multiplication OK!\n" .text .globl _Z14matrixMulCheckPiS_i .type _Z14matrixMulCheckPiS_i, @function _Z14matrixMulCheckPiS_i: .LFB2058: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 testl %edx, %edx jle .L15 movslq %edx, %rdx movl $0, %r8d .L18: movl (%rdi,%r8,4), %ecx movl (%rsi,%r8,4), %r9d cmpl %r9d, %ecx jne .L21 addq $1, %r8 cmpq %rdx, %r8 jne .L18 .L15: leaq .LC2(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT .L14: addq $8, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L21: .cfi_restore_state movl %r8d, %edx leaq .LC0(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT leaq .LC1(%rip), %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT jmp .L14 .cfi_endproc .LFE2058: .size _Z14matrixMulCheckPiS_i, .-_Z14matrixMulCheckPiS_i .globl _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i .type _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i, @function _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i: .LFB2084: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L26 .L22: movq 136(%rsp), %rax subq %fs:40, %rax jne .L27 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L26: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z13matrixMulGmemPiS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L22 .L27: call __stack_chk_fail@PLT .cfi_endproc .LFE2084: .size _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i .globl _Z13matrixMulGmemPiS_S_i .type _Z13matrixMulGmemPiS_S_i, @function _Z13matrixMulGmemPiS_S_i: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _Z13matrixMulGmemPiS_S_i, .-_Z13matrixMulGmemPiS_S_i .globl main .type main, @function main: .LFB2059: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 subq $88, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 72(%rsp) xorl %eax, %eax movl $1, 56(%rsp) movl $50, 60(%rsp) movl $100, 64(%rsp) movl $1, 68(%rsp) leaq 8(%rsp), %rdi call cudaEventCreate@PLT leaq 16(%rsp), %rdi call cudaEventCreate@PLT movl $10240000, %edi call malloc@PLT movq %rax, %r13 movl $10240000, %edi call malloc@PLT movq %rax, %r12 movl $10240000, %edi call malloc@PLT movq %rax, %rbp movl $10240000, %edi call malloc@PLT movq %rax, %rbx movl $0, %edx .L31: movslq %edx, %rax imulq $1374389535, %rax, %rax sarq $37, %rax movl %edx, %ecx sarl $31, %ecx subl %ecx, %eax imull $100, %eax, %ecx movl %edx, %eax subl %ecx, %eax movl %eax, 0(%r13,%rdx,4) movl %eax, (%r12,%rdx,4) movl $0, 0(%rbp,%rdx,4) movl $0, (%rbx,%rdx,4) addq $1, %rdx cmpq $2560000, %rdx jne .L31 leaq 24(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT leaq 32(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT leaq 40(%rsp), %rdi movl $10240000, %esi call cudaMalloc@PLT movl $0, %esi movq 8(%rsp), %rdi call cudaEventRecord@PLT movl $1, %ecx movl $10240000, %edx movq %r13, %rsi movq 24(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movl $10240000, %edx movq %r12, %rsi movq 32(%rsp), %rdi call cudaMemcpy@PLT movl $32, 48(%rsp) movl $16, 52(%rsp) movl 56(%rsp), %ecx movl $0, %r9d movl $0, %r8d movq 48(%rsp), %rdx movq 60(%rsp), %rdi movl 68(%rsp), %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L36 .L32: movl $2, %ecx movl $10240000, %edx movq 40(%rsp), %rsi movq %rbp, %rdi call cudaMemcpy@PLT movl $0, %esi movq 16(%rsp), %rdi call cudaEventRecord@PLT movq 16(%rsp), %rdi call cudaEventSynchronize@PLT leaq 4(%rsp), %rdi movq 16(%rsp), %rdx movq 8(%rsp), %rsi call cudaEventElapsedTime@PLT movq 8(%rsp), %rdi call cudaEventDestroy@PLT movq 16(%rsp), %rdi call cudaEventDestroy@PLT movl $1600, %ecx movq %rbx, %rdx movq %r12, %rsi movq %r13, %rdi call _Z9matricMulPiS_S_i movl $1600, %edx movq %rbp, %rsi movq %rbx, %rdi call _Z14matrixMulCheckPiS_i movq 24(%rsp), %rdi call cudaFree@PLT movq 32(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call free@PLT movq %r12, %rdi call free@PLT movq %rbp, %rdi call free@PLT movq %rbx, %rdi call free@PLT movq 72(%rsp), %rax subq %fs:40, %rax jne .L37 movl $0, %eax addq $88, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L36: .cfi_restore_state movl $1600, %ecx movq 40(%rsp), %rdx movq 32(%rsp), %rsi movq 24(%rsp), %rdi call _Z38__device_stub__Z13matrixMulGmemPiS_S_iPiS_S_i jmp .L32 .L37: call __stack_chk_fail@PLT .cfi_endproc .LFE2059: .size main, .-main .section .rodata.str1.1 .LC3: .string "_Z13matrixMulGmemPiS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2087: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _Z13matrixMulGmemPiS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2087: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "matrixMulGmem.hip" .globl _Z9matricMulPiS_S_i # -- Begin function _Z9matricMulPiS_S_i .p2align 4, 0x90 .type _Z9matricMulPiS_S_i,@function _Z9matricMulPiS_S_i: # @_Z9matricMulPiS_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movq %rdx, -8(%rsp) # 8-byte Spill testl %ecx, %ecx jle .LBB0_7 # %bb.1: # %.preheader.lr.ph movl %ecx, %eax leaq (,%rax,4), %r8 xorl %edx, %edx xorl %r10d, %r10d .p2align 4, 0x90 .LBB0_2: # %.preheader # =>This Loop Header: Depth=1 # Child Loop BB0_3 Depth 2 # Child Loop BB0_4 Depth 3 movl %edx, %r11d leaq (%rdi,%r11,4), %r11 movq %r10, %rbx imulq %rax, %rbx movq -8(%rsp), %r9 # 8-byte Reload leaq (%r9,%rbx,4), %rbx movq %rsi, %r14 xorl %r15d, %r15d .p2align 4, 0x90 .LBB0_3: # %.lr.ph # Parent Loop BB0_2 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB0_4 Depth 3 movl (%rbx,%r15,4), %ebp movq %r14, %r12 xorl %r13d, %r13d .p2align 4, 0x90 .LBB0_4: # Parent Loop BB0_2 Depth=1 # Parent Loop BB0_3 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r12), %r9d imull (%r11,%r13,4), %r9d addl %r9d, %ebp movl %ebp, (%rbx,%r15,4) incq %r13 addq %r8, %r12 cmpq %r13, %rax jne .LBB0_4 # %bb.5: # %._crit_edge # in Loop: Header=BB0_3 Depth=2 incq %r15 addq $4, %r14 cmpq %rax, %r15 jne .LBB0_3 # %bb.6: # %._crit_edge27 # in Loop: Header=BB0_2 Depth=1 incq %r10 addl %ecx, %edx cmpq %rax, %r10 jne .LBB0_2 .LBB0_7: # %._crit_edge29 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end0: .size _Z9matricMulPiS_S_i, .Lfunc_end0-_Z9matricMulPiS_S_i .cfi_endproc # -- End function .globl _Z14matrixMulCheckPiS_i # -- Begin function _Z14matrixMulCheckPiS_i .p2align 4, 0x90 .type _Z14matrixMulCheckPiS_i,@function _Z14matrixMulCheckPiS_i: # @_Z14matrixMulCheckPiS_i .cfi_startproc # %bb.0: movq %rdi, %rax movl $.Lstr.1, %edi testl %edx, %edx jle puts@PLT # TAILCALL # %bb.1: # %.lr.ph.preheader movl %edx, %r9d xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_2: # %.lr.ph # =>This Inner Loop Header: Depth=1 movl (%rax,%rcx,4), %edx movl (%rsi,%rcx,4), %r8d cmpl %r8d, %edx jne .LBB1_3 # %bb.4: # in Loop: Header=BB1_2 Depth=1 incq %rcx cmpq %rcx, %r9 jne .LBB1_2 # %bb.5: # %.critedge jmp puts@PLT # TAILCALL .LBB1_3: pushq %rax .cfi_def_cfa_offset 16 movl $.L.str, %edi movl %ecx, %esi # kill: def $ecx killed $ecx killed $rcx xorl %eax, %eax callq printf movl $.Lstr, %edi addq $8, %rsp .cfi_def_cfa_offset 8 jmp puts@PLT # TAILCALL .Lfunc_end1: .size _Z14matrixMulCheckPiS_i, .Lfunc_end1-_Z14matrixMulCheckPiS_i .cfi_endproc # -- End function .globl _Z28__device_stub__matrixMulGmemPiS_S_i # -- Begin function _Z28__device_stub__matrixMulGmemPiS_S_i .p2align 4, 0x90 .type _Z28__device_stub__matrixMulGmemPiS_S_i,@function _Z28__device_stub__matrixMulGmemPiS_S_i: # @_Z28__device_stub__matrixMulGmemPiS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z13matrixMulGmemPiS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end2: .size _Z28__device_stub__matrixMulGmemPiS_S_i, .Lfunc_end2-_Z28__device_stub__matrixMulGmemPiS_S_i .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $160, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 leaq 40(%rsp), %rdi callq hipEventCreate leaq 8(%rsp), %rdi callq hipEventCreate movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %rbx movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r14 movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r15 movl $10240000, %edi # imm = 0x9C4000 callq malloc movq %rax, %r12 xorl %r13d, %r13d movl $10240000, %edx # imm = 0x9C4000 movq %r15, %rdi xorl %esi, %esi callq memset@PLT movl $10240000, %edx # imm = 0x9C4000 movq %r12, %rdi xorl %esi, %esi callq memset@PLT .p2align 4, 0x90 .LBB3_1: # =>This Inner Loop Header: Depth=1 movl %r13d, %eax imulq $1374389535, %rax, %rax # imm = 0x51EB851F shrq $37, %rax imull $100, %eax, %eax movl %r13d, %ecx subl %eax, %ecx movl %ecx, (%rbx,%r13,4) movl %ecx, (%r14,%r13,4) incq %r13 cmpq $2560000, %r13 # imm = 0x271000 jne .LBB3_1 # %bb.2: leaq 32(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc leaq 24(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc leaq 16(%rsp), %rdi movl $10240000, %esi # imm = 0x9C4000 callq hipMalloc movq 40(%rsp), %rdi xorl %esi, %esi callq hipEventRecord movq 32(%rsp), %rdi movl $10240000, %edx # imm = 0x9C4000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movq 24(%rsp), %rdi movl $10240000, %edx # imm = 0x9C4000 movq %r14, %rsi movl $1, %ecx callq hipMemcpy movabsq $429496729650, %rdi # imm = 0x6400000032 movabsq $68719476768, %rdx # imm = 0x1000000020 movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_4 # %bb.3: movq 32(%rsp), %rax movq 24(%rsp), %rcx movq 16(%rsp), %rdx movq %rax, 120(%rsp) movq %rcx, 112(%rsp) movq %rdx, 104(%rsp) movl $1600, 52(%rsp) # imm = 0x640 leaq 120(%rsp), %rax movq %rax, 128(%rsp) leaq 112(%rsp), %rax movq %rax, 136(%rsp) leaq 104(%rsp), %rax movq %rax, 144(%rsp) leaq 52(%rsp), %rax movq %rax, 152(%rsp) leaq 88(%rsp), %rdi leaq 72(%rsp), %rsi leaq 64(%rsp), %rdx leaq 56(%rsp), %rcx callq __hipPopCallConfiguration movq 88(%rsp), %rsi movl 96(%rsp), %edx movq 72(%rsp), %rcx movl 80(%rsp), %r8d leaq 128(%rsp), %r9 movl $_Z13matrixMulGmemPiS_S_i, %edi pushq 56(%rsp) .cfi_adjust_cfa_offset 8 pushq 72(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_4: movq 16(%rsp), %rsi movl $10240000, %edx # imm = 0x9C4000 movq %r15, %rdi movl $2, %ecx callq hipMemcpy movq 8(%rsp), %rdi xorl %r13d, %r13d xorl %esi, %esi callq hipEventRecord movq 8(%rsp), %rdi callq hipEventSynchronize movq 40(%rsp), %rsi movq 8(%rsp), %rdx leaq 128(%rsp), %rdi callq hipEventElapsedTime movq 40(%rsp), %rdi callq hipEventDestroy movq 8(%rsp), %rdi callq hipEventDestroy movq %rbx, %rax .p2align 4, 0x90 .LBB3_5: # %.preheader.i # =>This Loop Header: Depth=1 # Child Loop BB3_6 Depth 2 # Child Loop BB3_7 Depth 3 imulq $6400, %r13, %rcx # imm = 0x1900 addq %r12, %rcx movq %r14, %rdx xorl %esi, %esi .p2align 4, 0x90 .LBB3_6: # %.lr.ph.i # Parent Loop BB3_5 Depth=1 # => This Loop Header: Depth=2 # Child Loop BB3_7 Depth 3 movl (%rcx,%rsi,4), %edi movq %rdx, %r8 xorl %r9d, %r9d .p2align 4, 0x90 .LBB3_7: # Parent Loop BB3_5 Depth=1 # Parent Loop BB3_6 Depth=2 # => This Inner Loop Header: Depth=3 movl (%r8), %r10d imull (%rax,%r9,4), %r10d addl %r10d, %edi incq %r9 addq $6400, %r8 # imm = 0x1900 cmpq $1600, %r9 # imm = 0x640 jne .LBB3_7 # %bb.8: # %._crit_edge.i # in Loop: Header=BB3_6 Depth=2 movl %edi, (%rcx,%rsi,4) incq %rsi addq $4, %rdx cmpq $1600, %rsi # imm = 0x640 jne .LBB3_6 # %bb.9: # %._crit_edge27.i # in Loop: Header=BB3_5 Depth=1 incq %r13 addq $6400, %rax # imm = 0x1900 cmpq $1600, %r13 # imm = 0x640 jne .LBB3_5 # %bb.10: # %.lr.ph.i50.preheader xorl %ecx, %ecx .p2align 4, 0x90 .LBB3_11: # %.lr.ph.i50 # =>This Inner Loop Header: Depth=1 movl (%r12,%rcx,4), %edx movl (%r15,%rcx,4), %r8d cmpl %r8d, %edx jne .LBB3_12 # %bb.13: # in Loop: Header=BB3_11 Depth=1 incq %rcx cmpq $1600, %rcx # imm = 0x640 jne .LBB3_11 # %bb.14: movl $.Lstr.1, %edi jmp .LBB3_15 .LBB3_12: movl $.L.str, %edi movl %ecx, %esi # kill: def $ecx killed $ecx killed $rcx xorl %eax, %eax callq printf movl $.Lstr, %edi .LBB3_15: # %_Z14matrixMulCheckPiS_i.exit callq puts@PLT movq 32(%rsp), %rdi callq hipFree movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq %rbx, %rdi callq free movq %r14, %rdi callq free movq %r15, %rdi callq free movq %r12, %rdi callq free xorl %eax, %eax addq $160, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .Lfunc_end3: .size main, .Lfunc_end3-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z13matrixMulGmemPiS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Error: C_cpu[%d] = %d .size .L.str, 40 .type _Z13matrixMulGmemPiS_S_i,@object # @_Z13matrixMulGmemPiS_S_i .section .rodata,"a",@progbits .globl _Z13matrixMulGmemPiS_S_i .p2align 3, 0x0 _Z13matrixMulGmemPiS_S_i: .quad _Z28__device_stub__matrixMulGmemPiS_S_i .size _Z13matrixMulGmemPiS_S_i, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z13matrixMulGmemPiS_S_i" .size .L__unnamed_1, 25 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .type .Lstr,@object # @str .section .rodata.str1.1,"aMS",@progbits,1 .Lstr: .asciz "Matrix Multiplication Error!" .size .Lstr, 29 .type .Lstr.1,@object # @str.1 .Lstr.1: .asciz "Matrix Multiplication OK!" .size .Lstr.1, 26 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z28__device_stub__matrixMulGmemPiS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z13matrixMulGmemPiS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
/* * HostDeviceVector.cpp * * Created on: 11 янв. 2016 г. * Author: aleksandr */ #include "HostDeviceVector.h" #include <thrust/fill.h> #include <thrust/copy.h> #include <iostream> HostDeviceVector::HostDeviceVector() {} HostDeviceVector::~HostDeviceVector() {} HostDeviceVector::HostDeviceVector(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::resize(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::fill(float placeholder) { thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::GPUtoCPU() { thrust::copy(deviceVector.begin(), deviceVector.end(), hostVector.begin()); } void HostDeviceVector::CPUtoGPU() { thrust::copy(hostVector.begin(), hostVector.end(), deviceVector.begin()); } thrust::device_ptr<float> HostDeviceVector::getDevicePtr() { return deviceVector.data(); } float* HostDeviceVector::getHostPtr() { return &hostVector[0]; } std::size_t HostDeviceVector::getSize() const { return hostVector.size(); } float& HostDeviceVector::operator [] (std::size_t index) { return hostVector[index]; }
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04300 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04300 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04300 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04100 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* * HostDeviceVector.cpp * * Created on: 11 янв. 2016 г. * Author: aleksandr */ #include "HostDeviceVector.h" #include <thrust/fill.h> #include <thrust/copy.h> #include <iostream> HostDeviceVector::HostDeviceVector() {} HostDeviceVector::~HostDeviceVector() {} HostDeviceVector::HostDeviceVector(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::resize(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::fill(float placeholder) { thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::GPUtoCPU() { thrust::copy(deviceVector.begin(), deviceVector.end(), hostVector.begin()); } void HostDeviceVector::CPUtoGPU() { thrust::copy(hostVector.begin(), hostVector.end(), deviceVector.begin()); } thrust::device_ptr<float> HostDeviceVector::getDevicePtr() { return deviceVector.data(); } float* HostDeviceVector::getHostPtr() { return &hostVector[0]; } std::size_t HostDeviceVector::getSize() const { return hostVector.size(); } float& HostDeviceVector::operator [] (std::size_t index) { return hostVector[index]; }
/* * HostDeviceVector.cpp * * Created on: 11 янв. 2016 г. * Author: aleksandr */ #include <hip/hip_runtime.h> #include "HostDeviceVector.h" #include <thrust/fill.h> #include <thrust/copy.h> #include <iostream> HostDeviceVector::HostDeviceVector() {} HostDeviceVector::~HostDeviceVector() {} HostDeviceVector::HostDeviceVector(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::resize(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::fill(float placeholder) { thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::GPUtoCPU() { thrust::copy(deviceVector.begin(), deviceVector.end(), hostVector.begin()); } void HostDeviceVector::CPUtoGPU() { thrust::copy(hostVector.begin(), hostVector.end(), deviceVector.begin()); } thrust::device_ptr<float> HostDeviceVector::getDevicePtr() { return deviceVector.data(); } float* HostDeviceVector::getHostPtr() { return &hostVector[0]; } std::size_t HostDeviceVector::getSize() const { return hostVector.size(); } float& HostDeviceVector::operator [] (std::size_t index) { return hostVector[index]; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
/* * HostDeviceVector.cpp * * Created on: 11 янв. 2016 г. * Author: aleksandr */ #include <hip/hip_runtime.h> #include "HostDeviceVector.h" #include <thrust/fill.h> #include <thrust/copy.h> #include <iostream> HostDeviceVector::HostDeviceVector() {} HostDeviceVector::~HostDeviceVector() {} HostDeviceVector::HostDeviceVector(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::resize(std::size_t size, float placeholder) { deviceVector.resize(size); thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); hostVector.resize(size); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::fill(float placeholder) { thrust::fill(deviceVector.begin(), deviceVector.end(), placeholder); thrust::fill(hostVector.begin(), hostVector.end(), placeholder); } void HostDeviceVector::GPUtoCPU() { thrust::copy(deviceVector.begin(), deviceVector.end(), hostVector.begin()); } void HostDeviceVector::CPUtoGPU() { thrust::copy(hostVector.begin(), hostVector.end(), deviceVector.begin()); } thrust::device_ptr<float> HostDeviceVector::getDevicePtr() { return deviceVector.data(); } float* HostDeviceVector::getHostPtr() { return &hostVector[0]; } std::size_t HostDeviceVector::getSize() const { return hostVector.size(); } float& HostDeviceVector::operator [] (std::size_t index) { return hostVector[index]; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB0_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end0: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_: s_load_b128 s[4:7], s[0:1], 0x18 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB1_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x8 s_load_b32 s6, s[0:1], 0x10 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB1_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 40 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .Lfunc_end1: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 24 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 40 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04300 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04300 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04300 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */ /* 0x000e220000002500 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */ /* 0x000e620000002100 */ /*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */ /* 0x001fca00078e00ff */ /*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */ /* 0x040fe40007f3e1ff */ /*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */ /* 0x002fe40007f5e0ff */ /*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */ /* 0x000fe40003f04070 */ /*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */ /* 0x000fe20000ffe5ff */ /*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */ /* 0x000fe200010e0603 */ /*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */ /* 0x000fe400078210ff */ /*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fc40003f04100 */ /*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */ /* 0x000fd600008f1403 */ /*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */ /* 0x000fea0003800000 */ /*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */ /* 0x000fe40003f04070 */ /*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */ /* 0x000fe40000011404 */ /*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */ /* 0x000fe40007ffe0ff */ /*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */ /* 0x000fca00078e00ff */ /*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */ /* 0x0001e2000c101904 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */ /* 0x000fda0003f04100 */ /*0160*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x001fca00078e00ff */ /*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*0190*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */ /* 0x000fca00078e00ff */ /*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x000fe8000c101904 */ /*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */ /* 0x000fe2000c101904 */ /*01d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0020*/ BRA 0x20; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0030*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0040*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0050*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0060*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0070*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0080*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0090*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_: s_load_b128 s[4:7], s[0:1], 0x10 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_u64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB0_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x0 s_load_b32 s6, s[0:1], 0x8 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB0_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 32 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat .Lfunc_end0: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .section .AMDGPU.csdata,"",@progbits .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .p2align 8 .type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_: s_load_b128 s[4:7], s[0:1], 0x18 s_lshl_b32 s2, s15, 8 s_waitcnt lgkmcnt(0) s_add_u32 s2, s2, s6 s_addc_u32 s3, 0, s7 s_sub_u32 s4, s4, s2 s_subb_u32 s5, s5, s3 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_gt_i64_e64 s5, 0x100, s[4:5] s_and_b32 s5, s5, exec_lo s_cselect_b32 s4, s4, 0x100 s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) v_cmp_gt_u32_e32 vcc_lo, s4, v0 s_cmpk_eq_i32 s4, 0x100 s_cselect_b32 s4, -1, 0 s_or_b32 s4, s4, vcc_lo s_delay_alu instid0(SALU_CYCLE_1) s_and_saveexec_b32 s5, s4 s_cbranch_execz .LBB1_2 s_clause 0x1 s_load_b64 s[4:5], s[0:1], 0x8 s_load_b32 s6, s[0:1], 0x10 v_lshlrev_b32_e32 v0, 2, v0 s_lshl_b64 s[0:1], s[2:3], 2 s_waitcnt lgkmcnt(0) s_add_u32 s0, s4, s0 s_addc_u32 s1, s5, s1 v_add_co_u32 v0, s0, s0, v0 s_delay_alu instid0(VALU_DEP_1) v_add_co_ci_u32_e64 v1, null, s1, 0, s0 v_mov_b32_e32 v2, s6 flat_store_b32 v[0:1], v2 .LBB1_2: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 40 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat .Lfunc_end1: .size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 16 .value_kind: by_value - .offset: 16 .size: 8 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 32 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .offset: 0 .size: 24 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 8 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 40 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 256 .name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIfEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_lfEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
/* This is a automatically generated test. Do not modify */ #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) { if (comp > var_1 - var_2) { if (comp <= ldexpf((var_3 + +0.0f), 2)) { float tmp_1 = (var_4 - var_5); float tmp_2 = +0.0f * var_6; comp += tmp_2 * tmp_1 - floorf(+1.2953E-9f + (-0.0f + var_7 / (-1.9780E36f - powf(var_8 * +1.6747E-44f - var_9 / fmodf(-1.9290E34f / var_10 - -0.0f, (-1.0991E-44f - sinhf(var_11 * var_12 * -1.3232E-36f))), -1.6650E-35f * (+1.2151E-42f - (var_13 * (+1.8866E36f * (-1.7231E-41f * var_14)))))))); comp += +1.2812E10f / var_15; if (comp <= atanf(-1.0044E-42f + (var_16 * -1.9840E8f * +1.6481E35f - var_17))) { float tmp_3 = +0.0f; comp = tmp_3 / var_18 - var_19 - -1.3206E-36f - var_20 / -1.0774E-41f; } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); float tmp_2 = atof(argv[2]); float tmp_3 = atof(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); float tmp_6 = atof(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); float tmp_12 = atof(argv[12]); float tmp_13 = atof(argv[13]); float tmp_14 = atof(argv[14]); float tmp_15 = atof(argv[15]); float tmp_16 = atof(argv[16]); float tmp_17 = atof(argv[17]); float tmp_18 = atof(argv[18]); float tmp_19 = atof(argv[19]); float tmp_20 = atof(argv[20]); float tmp_21 = atof(argv[21]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21); cudaDeviceSynchronize(); return 0; }
.file "tmpxft_0001c5a3_00000000-6_test.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff .type _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, @function _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff: .LFB2083: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) movq %rsp, %rax movq %rax, 152(%rsp) leaq 288(%rsp), %rax movq %rax, 160(%rsp) leaq 296(%rsp), %rax movq %rax, 168(%rsp) leaq 304(%rsp), %rax movq %rax, 176(%rsp) leaq 312(%rsp), %rax movq %rax, 184(%rsp) leaq 320(%rsp), %rax movq %rax, 192(%rsp) leaq 328(%rsp), %rax movq %rax, 200(%rsp) leaq 336(%rsp), %rax movq %rax, 208(%rsp) leaq 344(%rsp), %rax movq %rax, 216(%rsp) leaq 352(%rsp), %rax movq %rax, 224(%rsp) leaq 360(%rsp), %rax movq %rax, 232(%rsp) leaq 368(%rsp), %rax movq %rax, 240(%rsp) leaq 376(%rsp), %rax movq %rax, 248(%rsp) leaq 384(%rsp), %rax movq %rax, 256(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 264(%rsp), %rax subq %fs:40, %rax jne .L12 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 296 pushq 40(%rsp) .cfi_def_cfa_offset 304 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7computefffffffffffffffffffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, .-_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff .globl _Z7computefffffffffffffffffffff .type _Z7computefffffffffffffffffffff, @function _Z7computefffffffffffffffffffff: .LFB2084: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movss 224(%rsp), %xmm8 movss %xmm8, 96(%rsp) movss 216(%rsp), %xmm8 movss %xmm8, 88(%rsp) movss 208(%rsp), %xmm8 movss %xmm8, 80(%rsp) movss 200(%rsp), %xmm8 movss %xmm8, 72(%rsp) movss 192(%rsp), %xmm8 movss %xmm8, 64(%rsp) movss 184(%rsp), %xmm8 movss %xmm8, 56(%rsp) movss 176(%rsp), %xmm8 movss %xmm8, 48(%rsp) movss 168(%rsp), %xmm8 movss %xmm8, 40(%rsp) movss 160(%rsp), %xmm8 movss %xmm8, 32(%rsp) movss 152(%rsp), %xmm8 movss %xmm8, 24(%rsp) movss 144(%rsp), %xmm8 movss %xmm8, 16(%rsp) movss 136(%rsp), %xmm8 movss %xmm8, 8(%rsp) movss 128(%rsp), %xmm8 movss %xmm8, (%rsp) call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computefffffffffffffffffffff, .-_Z7computefffffffffffffffffffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $208, %rsp .cfi_def_cfa_offset 224 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 168(%rsp) movq 16(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 160(%rsp) movq 24(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 152(%rsp) movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 144(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 136(%rsp) movq 48(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 128(%rsp) movq 56(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 120(%rsp) movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 112(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 104(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 96(%rsp) movq 88(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 88(%rsp) movq 96(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 80(%rsp) movq 104(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 72(%rsp) movq 112(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 64(%rsp) movq 120(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 128(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 136(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 144(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 152(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 160(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 168(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movl $1, 196(%rsp) movl $1, 200(%rsp) movl $1, 184(%rsp) movl $1, 188(%rsp) movl $0, %r9d movl $0, %r8d movq 196(%rsp), %rdx movl $1, %ecx movq 184(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $208, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 168(%rsp), %xmm0 subq $112, %rsp .cfi_def_cfa_offset 336 pxor %xmm1, %xmm1 cvtsd2ss 120(%rsp), %xmm1 movss %xmm1, 96(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 128(%rsp), %xmm1 movss %xmm1, 88(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 136(%rsp), %xmm1 movss %xmm1, 80(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 144(%rsp), %xmm1 movss %xmm1, 72(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 152(%rsp), %xmm1 movss %xmm1, 64(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 160(%rsp), %xmm1 movss %xmm1, 56(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 168(%rsp), %xmm1 movss %xmm1, 48(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 176(%rsp), %xmm1 movss %xmm1, 40(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 184(%rsp), %xmm1 movss %xmm1, 32(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 192(%rsp), %xmm1 movss %xmm1, 24(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 200(%rsp), %xmm1 movss %xmm1, 16(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 208(%rsp), %xmm1 movss %xmm1, 8(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 216(%rsp), %xmm1 movss %xmm1, (%rsp) pxor %xmm7, %xmm7 cvtsd2ss 224(%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 232(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 240(%rsp), %xmm5 pxor %xmm4, %xmm4 cvtsd2ss 248(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 256(%rsp), %xmm3 pxor %xmm2, %xmm2 cvtsd2ss 264(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 272(%rsp), %xmm1 call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff addq $112, %rsp .cfi_def_cfa_offset 224 jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z7computefffffffffffffffffffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computefffffffffffffffffffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
/* This is a automatically generated test. Do not modify */ #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) { if (comp > var_1 - var_2) { if (comp <= ldexpf((var_3 + +0.0f), 2)) { float tmp_1 = (var_4 - var_5); float tmp_2 = +0.0f * var_6; comp += tmp_2 * tmp_1 - floorf(+1.2953E-9f + (-0.0f + var_7 / (-1.9780E36f - powf(var_8 * +1.6747E-44f - var_9 / fmodf(-1.9290E34f / var_10 - -0.0f, (-1.0991E-44f - sinhf(var_11 * var_12 * -1.3232E-36f))), -1.6650E-35f * (+1.2151E-42f - (var_13 * (+1.8866E36f * (-1.7231E-41f * var_14)))))))); comp += +1.2812E10f / var_15; if (comp <= atanf(-1.0044E-42f + (var_16 * -1.9840E8f * +1.6481E35f - var_17))) { float tmp_3 = +0.0f; comp = tmp_3 / var_18 - var_19 - -1.3206E-36f - var_20 / -1.0774E-41f; } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); float tmp_2 = atof(argv[2]); float tmp_3 = atof(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); float tmp_6 = atof(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); float tmp_12 = atof(argv[12]); float tmp_13 = atof(argv[13]); float tmp_14 = atof(argv[14]); float tmp_15 = atof(argv[15]); float tmp_16 = atof(argv[16]); float tmp_17 = atof(argv[17]); float tmp_18 = atof(argv[18]); float tmp_19 = atof(argv[19]); float tmp_20 = atof(argv[20]); float tmp_21 = atof(argv[21]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21); cudaDeviceSynchronize(); return 0; }
/* This is a automatically generated test. Do not modify */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) { if (comp > var_1 - var_2) { if (comp <= ldexpf((var_3 + +0.0f), 2)) { float tmp_1 = (var_4 - var_5); float tmp_2 = +0.0f * var_6; comp += tmp_2 * tmp_1 - floorf(+1.2953E-9f + (-0.0f + var_7 / (-1.9780E36f - powf(var_8 * +1.6747E-44f - var_9 / fmodf(-1.9290E34f / var_10 - -0.0f, (-1.0991E-44f - sinhf(var_11 * var_12 * -1.3232E-36f))), -1.6650E-35f * (+1.2151E-42f - (var_13 * (+1.8866E36f * (-1.7231E-41f * var_14)))))))); comp += +1.2812E10f / var_15; if (comp <= atanf(-1.0044E-42f + (var_16 * -1.9840E8f * +1.6481E35f - var_17))) { float tmp_3 = +0.0f; comp = tmp_3 / var_18 - var_19 - -1.3206E-36f - var_20 / -1.0774E-41f; } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); float tmp_2 = atof(argv[2]); float tmp_3 = atof(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); float tmp_6 = atof(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); float tmp_12 = atof(argv[12]); float tmp_13 = atof(argv[13]); float tmp_14 = atof(argv[14]); float tmp_15 = atof(argv[15]); float tmp_16 = atof(argv[16]); float tmp_17 = atof(argv[17]); float tmp_18 = atof(argv[18]); float tmp_19 = atof(argv[19]); float tmp_20 = atof(argv[20]); float tmp_21 = atof(argv[21]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21); hipDeviceSynchronize(); return 0; }
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
/* This is a automatically generated test. Do not modify */ #include <hip/hip_runtime.h> #include <stdio.h> #include <stdlib.h> #include <math.h> __global__ void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) { if (comp > var_1 - var_2) { if (comp <= ldexpf((var_3 + +0.0f), 2)) { float tmp_1 = (var_4 - var_5); float tmp_2 = +0.0f * var_6; comp += tmp_2 * tmp_1 - floorf(+1.2953E-9f + (-0.0f + var_7 / (-1.9780E36f - powf(var_8 * +1.6747E-44f - var_9 / fmodf(-1.9290E34f / var_10 - -0.0f, (-1.0991E-44f - sinhf(var_11 * var_12 * -1.3232E-36f))), -1.6650E-35f * (+1.2151E-42f - (var_13 * (+1.8866E36f * (-1.7231E-41f * var_14)))))))); comp += +1.2812E10f / var_15; if (comp <= atanf(-1.0044E-42f + (var_16 * -1.9840E8f * +1.6481E35f - var_17))) { float tmp_3 = +0.0f; comp = tmp_3 / var_18 - var_19 - -1.3206E-36f - var_20 / -1.0774E-41f; } } } printf("%.17g\n", comp); } float* initPointer(float v) { float *ret = (float*) malloc(sizeof(float)*10); for(int i=0; i < 10; ++i) ret[i] = v; return ret; } int main(int argc, char** argv) { /* Program variables */ float tmp_1 = atof(argv[1]); float tmp_2 = atof(argv[2]); float tmp_3 = atof(argv[3]); float tmp_4 = atof(argv[4]); float tmp_5 = atof(argv[5]); float tmp_6 = atof(argv[6]); float tmp_7 = atof(argv[7]); float tmp_8 = atof(argv[8]); float tmp_9 = atof(argv[9]); float tmp_10 = atof(argv[10]); float tmp_11 = atof(argv[11]); float tmp_12 = atof(argv[12]); float tmp_13 = atof(argv[13]); float tmp_14 = atof(argv[14]); float tmp_15 = atof(argv[15]); float tmp_16 = atof(argv[16]); float tmp_17 = atof(argv[17]); float tmp_18 = atof(argv[18]); float tmp_19 = atof(argv[19]); float tmp_20 = atof(argv[20]); float tmp_21 = atof(argv[21]); compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21); hipDeviceSynchronize(); return 0; }
.text .file "test.hip" .globl _Z22__device_stub__computefffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffff .p2align 4, 0x90 .type _Z22__device_stub__computefffffffffffffffffffff,@function _Z22__device_stub__computefffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffff .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) leaq 28(%rsp), %rax movq %rax, 80(%rsp) leaq 24(%rsp), %rax movq %rax, 88(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 256(%rsp), %rax movq %rax, 144(%rsp) leaq 264(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 344(%rsp), %rax movq %rax, 232(%rsp) leaq 352(%rsp), %rax movq %rax, 240(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7computefffffffffffffffffffff, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end0: .size _Z22__device_stub__computefffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 288 .cfi_offset %rbx, -16 movq %rsi, %rbx movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 264(%rsp) # 8-byte Spill movq 16(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 256(%rsp) # 8-byte Spill movq 24(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 248(%rsp) # 8-byte Spill movq 32(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 240(%rsp) # 8-byte Spill movq 40(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 136(%rsp) # 8-byte Spill movq 48(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 128(%rsp) # 8-byte Spill movq 56(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 120(%rsp) # 8-byte Spill movq 64(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 112(%rsp) # 8-byte Spill movq 72(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 80(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 232(%rsp) # 8-byte Spill movq 88(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 224(%rsp) # 8-byte Spill movq 96(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 216(%rsp) # 8-byte Spill movq 104(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 208(%rsp) # 8-byte Spill movq 112(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 200(%rsp) # 8-byte Spill movq 120(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 192(%rsp) # 8-byte Spill movq 128(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 184(%rsp) # 8-byte Spill movq 136(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 176(%rsp) # 8-byte Spill movq 144(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 168(%rsp) # 8-byte Spill movq 152(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 160(%rsp) # 8-byte Spill movq 160(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 152(%rsp) # 8-byte Spill movq 168(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 144(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 144(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm8 movsd 152(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm9 movsd 160(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm10 movsd 168(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm11 movsd 176(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm12 movsd 184(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm13 movsd 192(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm14 movsd 200(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm15 movsd 208(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm4 movsd 216(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm5 movsd 224(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm6 movsd 232(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm7 movsd 104(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 104(%rsp) # 4-byte Spill movsd 112(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 112(%rsp) # 4-byte Spill movsd 120(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 120(%rsp) # 4-byte Spill movsd 128(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 128(%rsp) # 4-byte Spill movsd 136(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 136(%rsp) # 4-byte Spill movsd 240(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm3 movsd 248(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm2 movsd 256(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm1 movsd 264(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm8, 96(%rsp) movss %xmm9, 88(%rsp) movss %xmm10, 80(%rsp) movss %xmm11, 72(%rsp) movss %xmm12, 64(%rsp) movss %xmm13, 56(%rsp) movss %xmm14, 48(%rsp) movss %xmm15, 40(%rsp) movss %xmm4, 32(%rsp) movss %xmm5, 24(%rsp) movss %xmm6, 16(%rsp) movss %xmm7, 8(%rsp) movss 104(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movss %xmm4, (%rsp) movss 136(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movss 128(%rsp), %xmm5 # 4-byte Reload # xmm5 = mem[0],zero,zero,zero movss 120(%rsp), %xmm6 # 4-byte Reload # xmm6 = mem[0],zero,zero,zero movss 112(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero callq _Z22__device_stub__computefffffffffffffffffffff .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computefffffffffffffffffffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computefffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffff .section .rodata,"a",@progbits .globl _Z7computefffffffffffffffffffff .p2align 3, 0x0 _Z7computefffffffffffffffffffff: .quad _Z22__device_stub__computefffffffffffffffffffff .size _Z7computefffffffffffffffffffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computefffffffffffffffffffff" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computefffffffffffffffffffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computefffffffffffffffffffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0001c5a3_00000000-6_test.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z11initPointerf .type _Z11initPointerf, @function _Z11initPointerf: .LFB2057: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movd %xmm0, %ebx movl $40, %edi call malloc@PLT movq %rax, %rdx leaq 40(%rax), %rcx .L4: movl %ebx, (%rdx) addq $4, %rdx cmpq %rcx, %rdx jne .L4 popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2057: .size _Z11initPointerf, .-_Z11initPointerf .globl _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff .type _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, @function _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff: .LFB2083: .cfi_startproc endbr64 subq $280, %rsp .cfi_def_cfa_offset 288 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) movq %fs:40, %rax movq %rax, 264(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 24(%rsp), %rax movq %rax, 104(%rsp) leaq 20(%rsp), %rax movq %rax, 112(%rsp) leaq 16(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 8(%rsp), %rax movq %rax, 136(%rsp) leaq 4(%rsp), %rax movq %rax, 144(%rsp) movq %rsp, %rax movq %rax, 152(%rsp) leaq 288(%rsp), %rax movq %rax, 160(%rsp) leaq 296(%rsp), %rax movq %rax, 168(%rsp) leaq 304(%rsp), %rax movq %rax, 176(%rsp) leaq 312(%rsp), %rax movq %rax, 184(%rsp) leaq 320(%rsp), %rax movq %rax, 192(%rsp) leaq 328(%rsp), %rax movq %rax, 200(%rsp) leaq 336(%rsp), %rax movq %rax, 208(%rsp) leaq 344(%rsp), %rax movq %rax, 216(%rsp) leaq 352(%rsp), %rax movq %rax, 224(%rsp) leaq 360(%rsp), %rax movq %rax, 232(%rsp) leaq 368(%rsp), %rax movq %rax, 240(%rsp) leaq 376(%rsp), %rax movq %rax, 248(%rsp) leaq 384(%rsp), %rax movq %rax, 256(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L11 .L7: movq 264(%rsp), %rax subq %fs:40, %rax jne .L12 addq $280, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L11: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 296 pushq 40(%rsp) .cfi_def_cfa_offset 304 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z7computefffffffffffffffffffff(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 288 jmp .L7 .L12: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, .-_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff .globl _Z7computefffffffffffffffffffff .type _Z7computefffffffffffffffffffff, @function _Z7computefffffffffffffffffffff: .LFB2084: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movss 224(%rsp), %xmm8 movss %xmm8, 96(%rsp) movss 216(%rsp), %xmm8 movss %xmm8, 88(%rsp) movss 208(%rsp), %xmm8 movss %xmm8, 80(%rsp) movss 200(%rsp), %xmm8 movss %xmm8, 72(%rsp) movss 192(%rsp), %xmm8 movss %xmm8, 64(%rsp) movss 184(%rsp), %xmm8 movss %xmm8, 56(%rsp) movss 176(%rsp), %xmm8 movss %xmm8, 48(%rsp) movss 168(%rsp), %xmm8 movss %xmm8, 40(%rsp) movss 160(%rsp), %xmm8 movss %xmm8, 32(%rsp) movss 152(%rsp), %xmm8 movss %xmm8, 24(%rsp) movss 144(%rsp), %xmm8 movss %xmm8, 16(%rsp) movss 136(%rsp), %xmm8 movss %xmm8, 8(%rsp) movss 128(%rsp), %xmm8 movss %xmm8, (%rsp) call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff addq $120, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z7computefffffffffffffffffffff, .-_Z7computefffffffffffffffffffff .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 subq $208, %rsp .cfi_def_cfa_offset 224 movq %rsi, %rbx movq 8(%rsi), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 168(%rsp) movq 16(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 160(%rsp) movq 24(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 152(%rsp) movq 32(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 144(%rsp) movq 40(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 136(%rsp) movq 48(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 128(%rsp) movq 56(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 120(%rsp) movq 64(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 112(%rsp) movq 72(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 104(%rsp) movq 80(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 96(%rsp) movq 88(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 88(%rsp) movq 96(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 80(%rsp) movq 104(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 72(%rsp) movq 112(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 64(%rsp) movq 120(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 56(%rsp) movq 128(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 48(%rsp) movq 136(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 40(%rsp) movq 144(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 32(%rsp) movq 152(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 24(%rsp) movq 160(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 16(%rsp) movq 168(%rbx), %rdi movl $0, %esi call strtod@PLT movsd %xmm0, 8(%rsp) movl $1, 196(%rsp) movl $1, 200(%rsp) movl $1, 184(%rsp) movl $1, 188(%rsp) movl $0, %r9d movl $0, %r8d movq 196(%rsp), %rdx movl $1, %ecx movq 184(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L18 .L16: call cudaDeviceSynchronize@PLT movl $0, %eax addq $208, %rsp .cfi_remember_state .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 ret .L18: .cfi_restore_state pxor %xmm0, %xmm0 cvtsd2ss 168(%rsp), %xmm0 subq $112, %rsp .cfi_def_cfa_offset 336 pxor %xmm1, %xmm1 cvtsd2ss 120(%rsp), %xmm1 movss %xmm1, 96(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 128(%rsp), %xmm1 movss %xmm1, 88(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 136(%rsp), %xmm1 movss %xmm1, 80(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 144(%rsp), %xmm1 movss %xmm1, 72(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 152(%rsp), %xmm1 movss %xmm1, 64(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 160(%rsp), %xmm1 movss %xmm1, 56(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 168(%rsp), %xmm1 movss %xmm1, 48(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 176(%rsp), %xmm1 movss %xmm1, 40(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 184(%rsp), %xmm1 movss %xmm1, 32(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 192(%rsp), %xmm1 movss %xmm1, 24(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 200(%rsp), %xmm1 movss %xmm1, 16(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 208(%rsp), %xmm1 movss %xmm1, 8(%rsp) pxor %xmm1, %xmm1 cvtsd2ss 216(%rsp), %xmm1 movss %xmm1, (%rsp) pxor %xmm7, %xmm7 cvtsd2ss 224(%rsp), %xmm7 pxor %xmm6, %xmm6 cvtsd2ss 232(%rsp), %xmm6 pxor %xmm5, %xmm5 cvtsd2ss 240(%rsp), %xmm5 pxor %xmm4, %xmm4 cvtsd2ss 248(%rsp), %xmm4 pxor %xmm3, %xmm3 cvtsd2ss 256(%rsp), %xmm3 pxor %xmm2, %xmm2 cvtsd2ss 264(%rsp), %xmm2 pxor %xmm1, %xmm1 cvtsd2ss 272(%rsp), %xmm1 call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff addq $112, %rsp .cfi_def_cfa_offset 224 jmp .L16 .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "_Z7computefffffffffffffffffffff" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z7computefffffffffffffffffffff(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "test.hip" .globl _Z22__device_stub__computefffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffff .p2align 4, 0x90 .type _Z22__device_stub__computefffffffffffffffffffff,@function _Z22__device_stub__computefffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffff .cfi_startproc # %bb.0: subq $248, %rsp .cfi_def_cfa_offset 256 movss %xmm0, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm2, 20(%rsp) movss %xmm3, 16(%rsp) movss %xmm4, 12(%rsp) movss %xmm5, 8(%rsp) movss %xmm6, 4(%rsp) movss %xmm7, (%rsp) leaq 28(%rsp), %rax movq %rax, 80(%rsp) leaq 24(%rsp), %rax movq %rax, 88(%rsp) leaq 20(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 12(%rsp), %rax movq %rax, 112(%rsp) leaq 8(%rsp), %rax movq %rax, 120(%rsp) leaq 4(%rsp), %rax movq %rax, 128(%rsp) movq %rsp, %rax movq %rax, 136(%rsp) leaq 256(%rsp), %rax movq %rax, 144(%rsp) leaq 264(%rsp), %rax movq %rax, 152(%rsp) leaq 272(%rsp), %rax movq %rax, 160(%rsp) leaq 280(%rsp), %rax movq %rax, 168(%rsp) leaq 288(%rsp), %rax movq %rax, 176(%rsp) leaq 296(%rsp), %rax movq %rax, 184(%rsp) leaq 304(%rsp), %rax movq %rax, 192(%rsp) leaq 312(%rsp), %rax movq %rax, 200(%rsp) leaq 320(%rsp), %rax movq %rax, 208(%rsp) leaq 328(%rsp), %rax movq %rax, 216(%rsp) leaq 336(%rsp), %rax movq %rax, 224(%rsp) leaq 344(%rsp), %rax movq %rax, 232(%rsp) leaq 352(%rsp), %rax movq %rax, 240(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z7computefffffffffffffffffffff, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $264, %rsp # imm = 0x108 .cfi_adjust_cfa_offset -264 retq .Lfunc_end0: .size _Z22__device_stub__computefffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffff .cfi_endproc # -- End function .globl _Z11initPointerf # -- Begin function _Z11initPointerf .p2align 4, 0x90 .type _Z11initPointerf,@function _Z11initPointerf: # @_Z11initPointerf .cfi_startproc # %bb.0: pushq %rax .cfi_def_cfa_offset 16 movss %xmm0, 4(%rsp) # 4-byte Spill movl $40, %edi callq malloc movss 4(%rsp), %xmm0 # 4-byte Reload # xmm0 = mem[0],zero,zero,zero xorl %ecx, %ecx .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 movss %xmm0, (%rax,%rcx,4) incq %rcx cmpq $10, %rcx jne .LBB1_1 # %bb.2: popq %rcx .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 288 .cfi_offset %rbx, -16 movq %rsi, %rbx movq 8(%rsi), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 264(%rsp) # 8-byte Spill movq 16(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 256(%rsp) # 8-byte Spill movq 24(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 248(%rsp) # 8-byte Spill movq 32(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 240(%rsp) # 8-byte Spill movq 40(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 136(%rsp) # 8-byte Spill movq 48(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 128(%rsp) # 8-byte Spill movq 56(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 120(%rsp) # 8-byte Spill movq 64(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 112(%rsp) # 8-byte Spill movq 72(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 104(%rsp) # 8-byte Spill movq 80(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 232(%rsp) # 8-byte Spill movq 88(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 224(%rsp) # 8-byte Spill movq 96(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 216(%rsp) # 8-byte Spill movq 104(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 208(%rsp) # 8-byte Spill movq 112(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 200(%rsp) # 8-byte Spill movq 120(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 192(%rsp) # 8-byte Spill movq 128(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 184(%rsp) # 8-byte Spill movq 136(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 176(%rsp) # 8-byte Spill movq 144(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 168(%rsp) # 8-byte Spill movq 152(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 160(%rsp) # 8-byte Spill movq 160(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 152(%rsp) # 8-byte Spill movq 168(%rbx), %rdi xorl %esi, %esi callq strtod movsd %xmm0, 144(%rsp) # 8-byte Spill movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %esi movq %rdi, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB2_2 # %bb.1: movsd 144(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm8 movsd 152(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm9 movsd 160(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm10 movsd 168(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm11 movsd 176(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm12 movsd 184(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm13 movsd 192(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm14 movsd 200(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm15 movsd 208(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm4 movsd 216(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm5 movsd 224(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm6 movsd 232(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm7 movsd 104(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 104(%rsp) # 4-byte Spill movsd 112(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 112(%rsp) # 4-byte Spill movsd 120(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 120(%rsp) # 4-byte Spill movsd 128(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 128(%rsp) # 4-byte Spill movsd 136(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm0, 136(%rsp) # 4-byte Spill movsd 240(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm3 movsd 248(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm2 movsd 256(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm1 movsd 264(%rsp), %xmm0 # 8-byte Reload # xmm0 = mem[0],zero cvtsd2ss %xmm0, %xmm0 movss %xmm8, 96(%rsp) movss %xmm9, 88(%rsp) movss %xmm10, 80(%rsp) movss %xmm11, 72(%rsp) movss %xmm12, 64(%rsp) movss %xmm13, 56(%rsp) movss %xmm14, 48(%rsp) movss %xmm15, 40(%rsp) movss %xmm4, 32(%rsp) movss %xmm5, 24(%rsp) movss %xmm6, 16(%rsp) movss %xmm7, 8(%rsp) movss 104(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movss %xmm4, (%rsp) movss 136(%rsp), %xmm4 # 4-byte Reload # xmm4 = mem[0],zero,zero,zero movss 128(%rsp), %xmm5 # 4-byte Reload # xmm5 = mem[0],zero,zero,zero movss 120(%rsp), %xmm6 # 4-byte Reload # xmm6 = mem[0],zero,zero,zero movss 112(%rsp), %xmm7 # 4-byte Reload # xmm7 = mem[0],zero,zero,zero callq _Z22__device_stub__computefffffffffffffffffffff .LBB2_2: callq hipDeviceSynchronize xorl %eax, %eax addq $272, %rsp # imm = 0x110 .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z7computefffffffffffffffffffff, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z7computefffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffff .section .rodata,"a",@progbits .globl _Z7computefffffffffffffffffffff .p2align 3, 0x0 _Z7computefffffffffffffffffffff: .quad _Z22__device_stub__computefffffffffffffffffffff .size _Z7computefffffffffffffffffffff, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z7computefffffffffffffffffffff" .size .L__unnamed_1, 32 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z22__device_stub__computefffffffffffffffffffff .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z7computefffffffffffffffffffff .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(cudaStream_t stream, int kernel_time){ int cuda_device = 7; cudaDeviceProp deviceProp; cudaGetDevice(&cuda_device); cudaGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
code for sm_80 Function : _Z11clock_blockii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */ /* 0x000fca00078e00ff */ /*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fda0003f06270 */ /*0030*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0040*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */ /* 0x000fe200078e00ff */ /*0050*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */ /* 0x000fe40000000800 */ /*0060*/ UISETP.GT.AND UP0, UPT, URZ, UR4, UPT ; /* 0x000000043f00728c */ /* 0x000fca000bf04270 */ /*0070*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0080*/ IADD3 R5, R2, c[0x0][0x164], RZ ; /* 0x0000590002057a10 */ /* 0x000fe40007ffe0ff */ /*0090*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fcc0000015000 */ /*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fe20003f06070 */ /*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff027624 */ /* 0x000fe200078e00ff */ /*00c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */ /* 0x000fe40000011405 */ /*00d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */ /* 0x000fe40007ffe0ff */ /*00e0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */ /* 0x000fe40003f06300 */ /*00f0*/ ISETP.GT.AND P2, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */ /* 0x000fc40003f44270 */ /*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fd60003f26270 */ /*0110*/ @P0 BRA P2, 0x1a0 ; /* 0x0000008000000947 */ /* 0x000fea0001000000 */ /*0120*/ PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fcc0003f4f008 */ /*0130*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.AND.EX P2, PT, R3, RZ, P2, P0 ; /* 0x000000ff0300720c */ /* 0x000fcc0001744300 */ /*0160*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0170*/ ISETP.LT.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fc80003f01070 */ /*0180*/ ISETP.LT.OR.EX P0, PT, R3, R7, P2, P0 ; /* 0x000000070300720c */ /* 0x000fda0001701700 */ /*0190*/ @P0 BRA 0x130 ; /* 0xffffff9000000947 */ /* 0x000fea000383ffff */ /*01a0*/ @!P1 BRA 0x70 ; /* 0xfffffec000009947 */ /* 0x000fea000383ffff */ /*01b0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(cudaStream_t stream, int kernel_time){ int cuda_device = 7; cudaDeviceProp deviceProp; cudaGetDevice(&cuda_device); cudaGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
.file "tmpxft_0019e8af_00000000-6_sleep_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z11clock_blockiiii .type _Z31__device_stub__Z11clock_blockiiii, @function _Z31__device_stub__Z11clock_blockiiii: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z11clock_blockii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z31__device_stub__Z11clock_blockiiii, .-_Z31__device_stub__Z11clock_blockiiii .globl _Z11clock_blockii .type _Z11clock_blockii, @function _Z11clock_blockii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z11clock_blockiiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z11clock_blockii, .-_Z11clock_blockii .globl _Z5sleepP11CUstream_sti .type _Z5sleepP11CUstream_sti, @function _Z5sleepP11CUstream_sti: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $1072, %rsp .cfi_def_cfa_offset 1104 movq %rdi, %rbx movl %esi, %ebp movq %fs:40, %rax movq %rax, 1064(%rsp) xorl %eax, %eax movl $7, 4(%rsp) leaq 4(%rsp), %rdi call cudaGetDevice@PLT leaq 32(%rsp), %rdi movl 4(%rsp), %esi call cudaGetDeviceProperties_v2@PLT movl 380(%rsp), %r12d movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movq %rbx, %r9 movl $1, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 1064(%rsp), %rax subq %fs:40, %rax jne .L16 addq $1072, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movl %r12d, %esi movl %ebp, %edi call _Z31__device_stub__Z11clock_blockiiii jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5sleepP11CUstream_sti, .-_Z5sleepP11CUstream_sti .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11clock_blockii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11clock_blockii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(cudaStream_t stream, int kernel_time){ int cuda_device = 7; cudaDeviceProp deviceProp; cudaGetDevice(&cuda_device); cudaGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
#include <hip/hip_runtime.h> #include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(hipStream_t stream, int kernel_time){ int cuda_device = 7; hipDeviceProp_t deviceProp; hipGetDevice(&cuda_device); hipGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(hipStream_t stream, int kernel_time){ int cuda_device = 7; hipDeviceProp_t deviceProp; hipGetDevice(&cuda_device); hipGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11clock_blockii .globl _Z11clock_blockii .p2align 8 .type _Z11clock_blockii,@function _Z11clock_blockii: s_load_b32 s4, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB0_5 s_load_b32 s5, s[0:1], 0x4 s_mov_b32 s1, 0 s_mov_b32 s8, 0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s5, 0 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s7, s6, -1 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_add_i32 s8, s8, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s8, s4 s_cbranch_scc1 .LBB0_5 .LBB0_3: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_mov_b32 s9, s6 s_add_i32 s2, s0, s5 s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i64_e64 s0, s[0:1], s[2:3] s_and_b32 s0, s0, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_2 .LBB0_4: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i64_e64 s10, s[0:1], 0 s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) v_cmp_lt_i64_e64 s0, s[0:1], s[2:3] s_delay_alu instid0(VALU_DEP_2) s_and_b32 s9, s10, s9 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_or_b32 s0, s0, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_4 s_branch .LBB0_2 .LBB0_5: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11clock_blockii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 8 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 11 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11clock_blockii, .Lfunc_end0-_Z11clock_blockii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 8 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11clock_blockii .private_segment_fixed_size: 0 .sgpr_count: 13 .sgpr_spill_count: 0 .symbol: _Z11clock_blockii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> //__global__ void clock_block(int kernel_time, int clockRate, int *d_result) __global__ void clock_block(int kernel_time, int clockRate) { int finish_clock; int start_time; for(int temp=0; temp<kernel_time; temp++){ start_time = clock(); finish_clock = start_time + clockRate; bool wrapped = finish_clock < start_time; while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped; } // (*d_result)= kernel_tim;e } //void sleep(cudaStream_t stream, int kernel_time, int *d_result){ void sleep(hipStream_t stream, int kernel_time){ int cuda_device = 7; hipDeviceProp_t deviceProp; hipGetDevice(&cuda_device); hipGetDeviceProperties(&deviceProp, cuda_device); int clockRate = deviceProp.clockRate; // clock_block<<<1,1,1,stream>>>(kernel_time, clockRate, d_result); clock_block<<<1,1,1,stream>>>(kernel_time, clockRate); }
.text .file "sleep_kernel.hip" .globl _Z26__device_stub__clock_blockii # -- Begin function _Z26__device_stub__clock_blockii .p2align 4, 0x90 .type _Z26__device_stub__clock_blockii,@function _Z26__device_stub__clock_blockii: # @_Z26__device_stub__clock_blockii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movl %edi, 12(%rsp) movl %esi, 8(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) leaq 8(%rsp), %rax movq %rax, 72(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z11clock_blockii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z26__device_stub__clock_blockii, .Lfunc_end0-_Z26__device_stub__clock_blockii .cfi_endproc # -- End function .globl _Z5sleepP12ihipStream_ti # -- Begin function _Z5sleepP12ihipStream_ti .p2align 4, 0x90 .type _Z5sleepP12ihipStream_ti,@function _Z5sleepP12ihipStream_ti: # @_Z5sleepP12ihipStream_ti .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $1552, %rsp # imm = 0x610 .cfi_def_cfa_offset 1584 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %esi, %ebx movq %rdi, %r14 movl $7, 4(%rsp) leaq 4(%rsp), %rdi callq hipGetDevice movl 4(%rsp), %esi leaq 80(%rsp), %rdi callq hipGetDevicePropertiesR0600 movl 428(%rsp), %ebp movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %r8d movl $1, %esi movq %rdi, %rdx movl $1, %ecx movq %r14, %r9 callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movl %ebx, 12(%rsp) movl %ebp, 8(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) leaq 8(%rsp), %rax movq %rax, 72(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z11clock_blockii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $1552, %rsp # imm = 0x610 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5sleepP12ihipStream_ti, .Lfunc_end1-_Z5sleepP12ihipStream_ti .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11clock_blockii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11clock_blockii,@object # @_Z11clock_blockii .section .rodata,"a",@progbits .globl _Z11clock_blockii .p2align 3, 0x0 _Z11clock_blockii: .quad _Z26__device_stub__clock_blockii .size _Z11clock_blockii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z11clock_blockii" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__clock_blockii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11clock_blockii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z11clock_blockii .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */ /* 0x000fca00078e00ff */ /*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */ /* 0x000fda0003f06270 */ /*0030*/ @!P0 EXIT ; /* 0x000000000000894d */ /* 0x000fea0003800000 */ /*0040*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */ /* 0x000fe200078e00ff */ /*0050*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */ /* 0x000fe40000000800 */ /*0060*/ UISETP.GT.AND UP0, UPT, URZ, UR4, UPT ; /* 0x000000043f00728c */ /* 0x000fca000bf04270 */ /*0070*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0080*/ IADD3 R5, R2, c[0x0][0x164], RZ ; /* 0x0000590002057a10 */ /* 0x000fe40007ffe0ff */ /*0090*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fcc0000015000 */ /*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fe20003f06070 */ /*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff027624 */ /* 0x000fe200078e00ff */ /*00c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */ /* 0x000fe40000011405 */ /*00d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */ /* 0x000fe40007ffe0ff */ /*00e0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */ /* 0x000fe40003f06300 */ /*00f0*/ ISETP.GT.AND P2, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */ /* 0x000fc40003f44270 */ /*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */ /* 0x000fd60003f26270 */ /*0110*/ @P0 BRA P2, 0x1a0 ; /* 0x0000008000000947 */ /* 0x000fea0001000000 */ /*0120*/ PLOP3.LUT P2, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */ /* 0x000fcc0003f4f008 */ /*0130*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0140*/ ISETP.GT.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */ /* 0x000fc80003f04070 */ /*0150*/ ISETP.GT.AND.EX P2, PT, R3, RZ, P2, P0 ; /* 0x000000ff0300720c */ /* 0x000fcc0001744300 */ /*0160*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */ /* 0x000fce0000015000 */ /*0170*/ ISETP.LT.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */ /* 0x000fc80003f01070 */ /*0180*/ ISETP.LT.OR.EX P0, PT, R3, R7, P2, P0 ; /* 0x000000070300720c */ /* 0x000fda0001701700 */ /*0190*/ @P0 BRA 0x130 ; /* 0xffffff9000000947 */ /* 0x000fea000383ffff */ /*01a0*/ @!P1 BRA 0x70 ; /* 0xfffffec000009947 */ /* 0x000fea000383ffff */ /*01b0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0200*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0210*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0220*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0230*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0240*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0250*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0260*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0270*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11clock_blockii .globl _Z11clock_blockii .p2align 8 .type _Z11clock_blockii,@function _Z11clock_blockii: s_load_b32 s4, s[0:1], 0x0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s4, 1 s_cbranch_scc1 .LBB0_5 s_load_b32 s5, s[0:1], 0x4 s_mov_b32 s1, 0 s_mov_b32 s8, 0 s_waitcnt lgkmcnt(0) s_cmp_lt_i32 s5, 0 s_cselect_b32 s6, -1, 0 s_delay_alu instid0(SALU_CYCLE_1) s_xor_b32 s7, s6, -1 s_branch .LBB0_3 .p2align 6 .LBB0_2: s_add_i32 s8, s8, 1 s_delay_alu instid0(SALU_CYCLE_1) s_cmp_eq_u32 s8, s4 s_cbranch_scc1 .LBB0_5 .LBB0_3: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_mov_b32 s9, s6 s_add_i32 s2, s0, s5 s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_ashr_i32 s3, s2, 31 s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_cmp_ge_i64_e64 s0, s[0:1], s[2:3] s_and_b32 s0, s0, s7 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_2 .LBB0_4: s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i64_e64 s10, s[0:1], 0 s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20) v_cmp_lt_i64_e64 s0, s[0:1], s[2:3] s_delay_alu instid0(VALU_DEP_2) s_and_b32 s9, s10, s9 s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) s_or_b32 s0, s0, s9 s_delay_alu instid0(SALU_CYCLE_1) s_and_b32 vcc_lo, exec_lo, s0 s_cbranch_vccnz .LBB0_4 s_branch .LBB0_2 .LBB0_5: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11clock_blockii .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 8 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 11 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11clock_blockii, .Lfunc_end0-_Z11clock_blockii .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .offset: 4 .size: 4 .value_kind: by_value .group_segment_fixed_size: 0 .kernarg_segment_align: 4 .kernarg_segment_size: 8 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11clock_blockii .private_segment_fixed_size: 0 .sgpr_count: 13 .sgpr_spill_count: 0 .symbol: _Z11clock_blockii.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 0 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_0019e8af_00000000-6_sleep_kernel.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2060: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2060: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z31__device_stub__Z11clock_blockiiii .type _Z31__device_stub__Z11clock_blockiiii, @function _Z31__device_stub__Z11clock_blockiiii: .LFB2082: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movl %edi, 12(%rsp) movl %esi, 8(%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 8(%rsp), %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 104(%rsp), %rax subq %fs:40, %rax jne .L8 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z11clock_blockii(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2082: .size _Z31__device_stub__Z11clock_blockiiii, .-_Z31__device_stub__Z11clock_blockiiii .globl _Z11clock_blockii .type _Z11clock_blockii, @function _Z11clock_blockii: .LFB2083: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z11clock_blockiiii addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2083: .size _Z11clock_blockii, .-_Z11clock_blockii .globl _Z5sleepP11CUstream_sti .type _Z5sleepP11CUstream_sti, @function _Z5sleepP11CUstream_sti: .LFB2057: .cfi_startproc endbr64 pushq %r12 .cfi_def_cfa_offset 16 .cfi_offset 12, -16 pushq %rbp .cfi_def_cfa_offset 24 .cfi_offset 6, -24 pushq %rbx .cfi_def_cfa_offset 32 .cfi_offset 3, -32 subq $1072, %rsp .cfi_def_cfa_offset 1104 movq %rdi, %rbx movl %esi, %ebp movq %fs:40, %rax movq %rax, 1064(%rsp) xorl %eax, %eax movl $7, 4(%rsp) leaq 4(%rsp), %rdi call cudaGetDevice@PLT leaq 32(%rsp), %rdi movl 4(%rsp), %esi call cudaGetDeviceProperties_v2@PLT movl 380(%rsp), %r12d movl $1, 20(%rsp) movl $1, 24(%rsp) movl $1, 8(%rsp) movl $1, 12(%rsp) movq %rbx, %r9 movl $1, %r8d movq 20(%rsp), %rdx movl $1, %ecx movq 8(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 1064(%rsp), %rax subq %fs:40, %rax jne .L16 addq $1072, %rsp .cfi_remember_state .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %rbp .cfi_def_cfa_offset 16 popq %r12 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movl %r12d, %esi movl %ebp, %edi call _Z31__device_stub__Z11clock_blockiiii jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5sleepP11CUstream_sti, .-_Z5sleepP11CUstream_sti .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z11clock_blockii" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2085: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z11clock_blockii(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2085: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "sleep_kernel.hip" .globl _Z26__device_stub__clock_blockii # -- Begin function _Z26__device_stub__clock_blockii .p2align 4, 0x90 .type _Z26__device_stub__clock_blockii,@function _Z26__device_stub__clock_blockii: # @_Z26__device_stub__clock_blockii .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movl %edi, 12(%rsp) movl %esi, 8(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) leaq 8(%rsp), %rax movq %rax, 72(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z11clock_blockii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end0: .size _Z26__device_stub__clock_blockii, .Lfunc_end0-_Z26__device_stub__clock_blockii .cfi_endproc # -- End function .globl _Z5sleepP12ihipStream_ti # -- Begin function _Z5sleepP12ihipStream_ti .p2align 4, 0x90 .type _Z5sleepP12ihipStream_ti,@function _Z5sleepP12ihipStream_ti: # @_Z5sleepP12ihipStream_ti .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %rbx .cfi_def_cfa_offset 32 subq $1552, %rsp # imm = 0x610 .cfi_def_cfa_offset 1584 .cfi_offset %rbx, -32 .cfi_offset %r14, -24 .cfi_offset %rbp, -16 movl %esi, %ebx movq %rdi, %r14 movl $7, 4(%rsp) leaq 4(%rsp), %rdi callq hipGetDevice movl 4(%rsp), %esi leaq 80(%rsp), %rdi callq hipGetDevicePropertiesR0600 movl 428(%rsp), %ebp movabsq $4294967297, %rdi # imm = 0x100000001 movl $1, %r8d movl $1, %esi movq %rdi, %rdx movl $1, %ecx movq %r14, %r9 callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movl %ebx, 12(%rsp) movl %ebp, 8(%rsp) leaq 12(%rsp), %rax movq %rax, 64(%rsp) leaq 8(%rsp), %rax movq %rax, 72(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z11clock_blockii, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: addq $1552, %rsp # imm = 0x610 .cfi_def_cfa_offset 32 popq %rbx .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5sleepP12ihipStream_ti, .Lfunc_end1-_Z5sleepP12ihipStream_ti .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11clock_blockii, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11clock_blockii,@object # @_Z11clock_blockii .section .rodata,"a",@progbits .globl _Z11clock_blockii .p2align 3, 0x0 _Z11clock_blockii: .quad _Z26__device_stub__clock_blockii .size _Z11clock_blockii, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z11clock_blockii" .size .L__unnamed_1, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__clock_blockii .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11clock_blockii .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> using namespace std; cudaError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; cudaError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != cudaSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = cudaDeviceReset(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceReset failed!"); return 1; } cin.get(); return 0; } cudaError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; cudaError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = cudaMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } cudaStatus = cudaMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = cudaMemcpy(dev_input, input, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } cudaStatus = cudaMemcpy(dev_output, output, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = cudaGetLastError(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = cudaDeviceSynchronize(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = cudaMemcpy(output, dev_output, size * sizeof(long), cudaMemcpyDeviceToHost); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } Error: cudaFree(dev_input); cudaFree(dev_output); return cudaStatus; }
code for sm_80 Function : _Z6squarePlS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x001fcc00078e0209 */ /*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea4000c1e1b00 */ /*0060*/ IMAD R5, R3, R2.reuse, RZ ; /* 0x0000000203057224 */ /* 0x084fe400078e02ff */ /*0070*/ IMAD.WIDE.U32 R6, R2, R2, RZ ; /* 0x0000000202067225 */ /* 0x000fc800078e00ff */ /*0080*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */ /* 0x000fca00078e0205 */ /*0090*/ IADD3 R7, R7, R5, RZ ; /* 0x0000000507077210 */ /* 0x000fe20007ffe0ff */ /*00a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fca00078e0209 */ /*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */ /* 0x000fe2000c101b04 */ /*00c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z9addKernelPiPKiS1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x001fc800078e0207 */ /*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */ /* 0x0c0fe400078e0207 */ /*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1900 */ /*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fe200078e0207 */ /*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */ /* 0x004fca0007ffe0ff */ /*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00b0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> using namespace std; cudaError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; cudaError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != cudaSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = cudaDeviceReset(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceReset failed!"); return 1; } cin.get(); return 0; } cudaError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; cudaError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = cudaMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } cudaStatus = cudaMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = cudaMemcpy(dev_input, input, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } cudaStatus = cudaMemcpy(dev_output, output, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = cudaGetLastError(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = cudaDeviceSynchronize(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = cudaMemcpy(output, dev_output, size * sizeof(long), cudaMemcpyDeviceToHost); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } Error: cudaFree(dev_input); cudaFree(dev_output); return cudaStatus; }
.file "tmpxft_001410ac_00000000-6_kernel.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ .type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_: .LFB3695: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9addKernelPiPKiS1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3695: .size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ .globl _Z9addKernelPiPKiS1_ .type _Z9addKernelPiPKiS1_, @function _Z9addKernelPiPKiS1_: .LFB3696: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3696: .size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_ .globl _Z27__device_stub__Z6squarePlS_PlS_ .type _Z27__device_stub__Z6squarePlS_PlS_, @function _Z27__device_stub__Z6squarePlS_PlS_: .LFB3697: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 104(%rsp), %rax subq %fs:40, %rax jne .L16 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6squarePlS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z27__device_stub__Z6squarePlS_PlS_, .-_Z27__device_stub__Z6squarePlS_PlS_ .globl _Z6squarePlS_ .type _Z6squarePlS_, @function _Z6squarePlS_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6squarePlS_PlS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z6squarePlS_, .-_Z6squarePlS_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "cudaMalloc failed!" .LC2: .string "cudaMemcpy failed!" .LC3: .string "addKernel launch failed: %s\n" .section .rodata.str1.8 .align 8 .LC4: .string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n" .text .globl _Z14squareWithCudaPlS_j .type _Z14squareWithCudaPlS_j, @function _Z14squareWithCudaPlS_j: .LFB3670: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %rdi, %rbp movq %rsi, %r12 movl %edx, %r13d movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq $0, (%rsp) movq $0, 8(%rsp) movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L31 movl %r13d, %r14d salq $3, %r14 movq %rsp, %rdi movq %r14, %rsi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L32 leaq 8(%rsp), %rdi movq %r14, %rsi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L33 movl $1, %ecx movq %r14, %rdx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax jne .L34 movl $1, %ecx movq %r14, %rdx movq %r12, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax jne .L35 movl %r13d, 28(%rsp) movl $1, 32(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L36 .L26: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L37 call cudaDeviceSynchronize@PLT movl %eax, %ebx testl %eax, %eax jne .L38 movl $2, %ecx movq %r14, %rdx movq 8(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax je .L21 leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L31: movl %eax, %ebx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT .L21: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L39 movl %ebx, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state leaq .LC1(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L33: leaq .LC1(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L34: leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L35: leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L36: movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z27__device_stub__Z6squarePlS_PlS_ jmp .L26 .L37: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC3(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L38: movl %eax, %ecx leaq .LC4(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L39: call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size _Z14squareWithCudaPlS_j, .-_Z14squareWithCudaPlS_j .section .rodata.str1.1 .LC5: .string "\t" .LC6: .string "\n" .LC7: .string "Square With Cuda failed!" .LC8: .string "%d" .LC9: .string "cudaDeviceReset failed!" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 leaq -16384(%rsp), %r11 .cfi_def_cfa 11, 16424 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $24, %rsp .cfi_def_cfa_offset 16448 movq %fs:40, %rax movq %rax, 16392(%rsp) xorl %eax, %eax .L41: movq %rax, (%rsp,%rax,8) addq $1, %rax cmpq $1024, %rax jne .L41 leaq 8192(%rsp), %rdi movl $1024, %ecx movl $0, %eax rep stosq leaq 8192(%rsp), %rsi movq %rsp, %rdi movl $1024, %edx call _Z14squareWithCudaPlS_j movl $0, %ebx leaq .LC8(%rip), %r13 leaq .LC6(%rip), %r12 leaq .LC5(%rip), %rbp testl %eax, %eax jne .L53 .L42: movq 8192(%rsp,%rbx,8), %rdx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $1024, %rbx jne .L42 call cudaDeviceReset@PLT testl %eax, %eax jne .L54 leaq _ZSt3cin(%rip), %rdi call _ZNSi3getEv@PLT movl $0, %eax .L40: movq 16392(%rsp), %rdx subq %fs:40, %rdx jne .L55 addq $16408, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L53: .cfi_restore_state leaq .LC7(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT leaq _ZSt3cin(%rip), %rdi call _ZNSi3getEv@PLT movl $1, %eax jmp .L40 .L54: leaq .LC9(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %eax jmp .L40 .L55: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z6squarePlS_" .LC11: .string "_Z9addKernelPiPKiS1_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z6squarePlS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z9addKernelPiPKiS1_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include "cuda_runtime.h" #include "device_launch_parameters.h" #include <stdio.h> #include <iostream> using namespace std; cudaError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; cudaError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != cudaSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = cudaDeviceReset(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceReset failed!"); return 1; } cin.get(); return 0; } cudaError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; cudaError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = cudaSetDevice(0); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = cudaMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } cudaStatus = cudaMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = cudaMemcpy(dev_input, input, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } cudaStatus = cudaMemcpy(dev_output, output, size * sizeof(long), cudaMemcpyHostToDevice); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = cudaGetLastError(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = cudaDeviceSynchronize(); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = cudaMemcpy(output, dev_output, size * sizeof(long), cudaMemcpyDeviceToHost); if (cudaStatus != cudaSuccess) { fprintf(stderr, "cudaMemcpy failed!"); goto Error; } Error: cudaFree(dev_input); cudaFree(dev_output); return cudaStatus; }
#include "hip/hip_runtime.h" #include <stdio.h> #include <iostream> using namespace std; hipError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; hipError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != hipSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = hipDeviceReset(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceReset failed!"); return 1; } cin.get(); return 0; } hipError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; hipError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = hipMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } cudaStatus = hipMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = hipMemcpy(dev_input, input, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } cudaStatus = hipMemcpy(dev_output, output, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = hipGetLastError(); if (cudaStatus != hipSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = hipDeviceSynchronize(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = hipMemcpy(output, dev_output, size * sizeof(long), hipMemcpyDeviceToHost); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } Error: hipFree(dev_input); hipFree(dev_output); return cudaStatus; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include "hip/hip_runtime.h" #include <stdio.h> #include <iostream> using namespace std; hipError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; hipError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != hipSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = hipDeviceReset(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceReset failed!"); return 1; } cin.get(); return 0; } hipError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; hipError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = hipMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } cudaStatus = hipMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = hipMemcpy(dev_input, input, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } cudaStatus = hipMemcpy(dev_output, output, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = hipGetLastError(); if (cudaStatus != hipSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = hipDeviceSynchronize(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = hipMemcpy(output, dev_output, size * sizeof(long), hipMemcpyDeviceToHost); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } Error: hipFree(dev_input); hipFree(dev_output); return cudaStatus; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9addKernelPiPKiS1_ .globl _Z9addKernelPiPKiS1_ .p2align 8 .type _Z9addKernelPiPKiS1_,@function _Z9addKernelPiPKiS1_: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v1, v0, s[6:7] global_load_b32 v2, v0, s[0:1] s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v2, v1 global_store_b32 v0, v1, s[4:5] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9addKernelPiPKiS1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z6squarePlS_ .globl _Z6squarePlS_ .p2align 8 .type _Z6squarePlS_,@function _Z6squarePlS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v3, 3, v0 s_waitcnt lgkmcnt(0) global_load_b64 v[0:1], v3, s[2:3] s_waitcnt vmcnt(0) v_mul_lo_u32 v4, v0, v1 v_mad_u64_u32 v[1:2], null, v0, v0, 0 s_delay_alu instid0(VALU_DEP_1) v_add3_u32 v2, v2, v4, v4 global_store_b64 v3, v[1:2], s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6squarePlS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6squarePlS_, .Lfunc_end1-_Z6squarePlS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9addKernelPiPKiS1_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9addKernelPiPKiS1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6squarePlS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z6squarePlS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include "hip/hip_runtime.h" #include <stdio.h> #include <iostream> using namespace std; hipError_t squareWithCuda(long *input, long *output, unsigned int size); __global__ void addKernel(int *c, const int *a, const int *b) { int i = threadIdx.x; c[i] = a[i] + b[i]; } __global__ void square(long *d_out, long *d_in) { int idx = threadIdx.x; long f = d_in[idx]; d_out[idx] = f * f; } int main() { const int ARRAY_SIZE = 1024; long h_in[ARRAY_SIZE]; for (int i = 0; i < ARRAY_SIZE; i++) { h_in[i] = long(i); } long h_out[ARRAY_SIZE] = { 0 }; hipError_t cudaStatus = squareWithCuda(h_in, h_out, ARRAY_SIZE); if (cudaStatus != hipSuccess) { fprintf(stderr, "Square With Cuda failed!"); cin.get(); return 1; } for (int i = 0; i < ARRAY_SIZE; i++) { printf("%d", h_out[i]); printf(((i % 4) != 3) ? "\t" : "\n"); } /* const int arraySize = 5; const int a[arraySize] = { 1, 2, 3, 4, 5 }; const int b[arraySize] = { 10, 20, 30, 40, 50 }; int c[arraySize] = { 0 }; // Add vectors in parallel. cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize); if (cudaStatus != cudaSuccess) { fprintf(stderr, "addWithCuda failed!"); return 1; } printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n", c[0], c[1], c[2], c[3], c[4]); */ // cudaDeviceReset must be called before exiting in order for profiling and // tracing tools such as Nsight and Visual Profiler to show complete traces. cudaStatus = hipDeviceReset(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceReset failed!"); return 1; } cin.get(); return 0; } hipError_t squareWithCuda(long *input, long *output, unsigned int size) { long *dev_input = 0; long *dev_output = 0; hipError_t cudaStatus; // Choose which GPU to run on, change this on a multi-GPU system. cudaStatus = hipSetDevice(0); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"); goto Error; } // Allocate GPU buffers for three vectors (two input, one output) . cudaStatus = hipMalloc((void**)&dev_input, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } cudaStatus = hipMalloc((void**)&dev_output, size * sizeof(long)); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMalloc failed!"); goto Error; } // Copy input vectors from host memory to GPU buffers. cudaStatus = hipMemcpy(dev_input, input, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } cudaStatus = hipMemcpy(dev_output, output, size * sizeof(long), hipMemcpyHostToDevice); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } // Launch a kernel on the GPU with one thread for each element. square<<<1.0, size>>>(dev_output, dev_input); // Check for any errors launching the kernel cudaStatus = hipGetLastError(); if (cudaStatus != hipSuccess) { fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus)); goto Error; } // cudaDeviceSynchronize waits for the kernel to finish, and returns // any errors encountered during the launch. cudaStatus = hipDeviceSynchronize(); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus); goto Error; } // Copy output vector from GPU buffer to host memory. cudaStatus = hipMemcpy(output, dev_output, size * sizeof(long), hipMemcpyDeviceToHost); if (cudaStatus != hipSuccess) { fprintf(stderr, "hipMemcpy failed!"); goto Error; } Error: hipFree(dev_input); hipFree(dev_output); return cudaStatus; }
.text .file "kernel.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_ .p2align 4, 0x90 .type _Z24__device_stub__addKernelPiPKiS1_,@function _Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9addKernelPiPKiS1_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_ .cfi_endproc # -- End function .globl _Z21__device_stub__squarePlS_ # -- Begin function _Z21__device_stub__squarePlS_ .p2align 4, 0x90 .type _Z21__device_stub__squarePlS_,@function _Z21__device_stub__squarePlS_: # @_Z21__device_stub__squarePlS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6squarePlS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z21__device_stub__squarePlS_, .Lfunc_end1-_Z21__device_stub__squarePlS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $16392, %rsp # imm = 0x4008 .cfi_def_cfa_offset 16416 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 movq %rax, 8192(%rsp,%rax,8) incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB2_1 # %bb.2: movq %rsp, %rbx movl $8192, %edx # imm = 0x2000 movq %rbx, %rdi xorl %esi, %esi callq memset@PLT leaq 8192(%rsp), %rdi movq %rbx, %rsi movl $1024, %edx # imm = 0x400 callq _Z14squareWithCudaPlS_j testl %eax, %eax jne .LBB2_9 # %bb.3: # %.preheader.preheader movl $.L.str.3, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_4: # %.preheader # =>This Inner Loop Header: Depth=1 movq (%rsp,%r14,8), %rsi movl $.L.str.1, %edi xorl %eax, %eax callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.2, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $1024, %r14 # imm = 0x400 jne .LBB2_4 # %bb.5: callq hipDeviceReset testl %eax, %eax jne .LBB2_6 # %bb.7: movl $_ZSt3cin, %edi callq _ZNSi3getEv xorl %eax, %eax .LBB2_8: addq $16392, %rsp # imm = 0x4008 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB2_9: .cfi_def_cfa_offset 16416 movq stderr(%rip), %rcx movl $.L.str, %edi movl $24, %esi movl $1, %edx callq fwrite@PLT movl $_ZSt3cin, %edi callq _ZNSi3getEv movl $1, %eax jmp .LBB2_8 .LBB2_6: movq stderr(%rip), %rcx movl $.L.str.4, %edi movl $22, %esi movl $1, %edx callq fwrite@PLT movl $1, %eax jmp .LBB2_8 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .globl _Z14squareWithCudaPlS_j # -- Begin function _Z14squareWithCudaPlS_j .p2align 4, 0x90 .type _Z14squareWithCudaPlS_j,@function _Z14squareWithCudaPlS_j: # @_Z14squareWithCudaPlS_j .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebp movq %rsi, %rbx movq %rdi, %r12 movq $0, 8(%rsp) movq $0, (%rsp) xorl %edi, %edi callq hipSetDevice testl %eax, %eax jne .LBB3_14 # %bb.1: movl %ebp, %r15d leaq (,%r15,8), %r14 leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc testl %eax, %eax jne .LBB3_11 # %bb.2: movq %rsp, %rdi movq %r14, %rsi callq hipMalloc testl %eax, %eax jne .LBB3_11 # %bb.3: movq 8(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB3_12 # %bb.4: movq (%rsp), %rdi movq %rbx, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB3_12 # %bb.5: movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %r15 orq $1, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_7 # %bb.6: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6squarePlS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_7: callq hipGetLastError testl %eax, %eax jne .LBB3_18 # %bb.8: callq hipDeviceSynchronize testl %eax, %eax jne .LBB3_19 # %bb.9: movq (%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy xorl %ebx, %ebx testl %eax, %eax je .LBB3_17 # %bb.10: movq stderr(%rip), %rcx movl $.L.str.7, %edi movl $17, %esi movl $1, %edx movl %eax, %ebx jmp .LBB3_16 .LBB3_11: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.6, %edi jmp .LBB3_13 .LBB3_12: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.7, %edi .LBB3_13: movl $17, %esi jmp .LBB3_15 .LBB3_14: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.5, %edi movl $63, %esi .LBB3_15: movl $1, %edx .LBB3_16: callq fwrite@PLT .LBB3_17: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movl %ebx, %eax addq $96, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_18: .cfi_def_cfa_offset 144 movq stderr(%rip), %r14 movl %eax, %ebx movl %eax, %edi callq hipGetErrorString movl $.L.str.8, %esi movq %r14, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf jmp .LBB3_17 .LBB3_19: movq stderr(%rip), %rdi movl $.L.str.9, %esi movl %eax, %ebx movl %eax, %edx xorl %eax, %eax callq fprintf jmp .LBB3_17 .Lfunc_end3: .size _Z14squareWithCudaPlS_j, .Lfunc_end3-_Z14squareWithCudaPlS_j .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9addKernelPiPKiS1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6squarePlS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_ .section .rodata,"a",@progbits .globl _Z9addKernelPiPKiS1_ .p2align 3, 0x0 _Z9addKernelPiPKiS1_: .quad _Z24__device_stub__addKernelPiPKiS1_ .size _Z9addKernelPiPKiS1_, 8 .type _Z6squarePlS_,@object # @_Z6squarePlS_ .globl _Z6squarePlS_ .p2align 3, 0x0 _Z6squarePlS_: .quad _Z21__device_stub__squarePlS_ .size _Z6squarePlS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Square With Cuda failed!" .size .L.str, 25 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\t" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\n" .size .L.str.3, 2 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipDeviceReset failed!" .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?" .size .L.str.5, 64 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMalloc failed!" .size .L.str.6, 18 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMemcpy failed!" .size .L.str.7, 18 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "addKernel launch failed: %s\n" .size .L.str.8, 29 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n" .size .L.str.9, 72 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9addKernelPiPKiS1_" .size .L__unnamed_1, 21 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6squarePlS_" .size .L__unnamed_2, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__addKernelPiPKiS1_ .addrsig_sym _Z21__device_stub__squarePlS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9addKernelPiPKiS1_ .addrsig_sym _Z6squarePlS_ .addrsig_sym _ZSt3cin .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6squarePlS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x001fcc00078e0209 */ /*0050*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea4000c1e1b00 */ /*0060*/ IMAD R5, R3, R2.reuse, RZ ; /* 0x0000000203057224 */ /* 0x084fe400078e02ff */ /*0070*/ IMAD.WIDE.U32 R6, R2, R2, RZ ; /* 0x0000000202067225 */ /* 0x000fc800078e00ff */ /*0080*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */ /* 0x000fca00078e0205 */ /*0090*/ IADD3 R7, R7, R5, RZ ; /* 0x0000000507077210 */ /* 0x000fe20007ffe0ff */ /*00a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */ /* 0x000fca00078e0209 */ /*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */ /* 0x000fe2000c101b04 */ /*00c0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z9addKernelPiPKiS1_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */ /* 0x000e220000002100 */ /*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */ /* 0x000fe200000001ff */ /*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */ /* 0x001fc800078e0207 */ /*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */ /* 0x0c0fe400078e0207 */ /*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea8000c1e1900 */ /*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */ /* 0x000ea2000c1e1900 */ /*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */ /* 0x000fe200078e0207 */ /*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */ /* 0x004fca0007ffe0ff */ /*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101904 */ /*00b0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9addKernelPiPKiS1_ .globl _Z9addKernelPiPKiS1_ .p2align 8 .type _Z9addKernelPiPKiS1_,@function _Z9addKernelPiPKiS1_: s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[0:1], s[0:1], 0x10 v_lshlrev_b32_e32 v0, 2, v0 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v1, v0, s[6:7] global_load_b32 v2, v0, s[0:1] s_waitcnt vmcnt(0) v_add_nc_u32_e32 v1, v2, v1 global_store_b32 v0, v1, s[4:5] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9addKernelPiPKiS1_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 24 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 3 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_ .section .AMDGPU.csdata,"",@progbits .text .protected _Z6squarePlS_ .globl _Z6squarePlS_ .p2align 8 .type _Z6squarePlS_,@function _Z6squarePlS_: s_load_b128 s[0:3], s[0:1], 0x0 v_lshlrev_b32_e32 v3, 3, v0 s_waitcnt lgkmcnt(0) global_load_b64 v[0:1], v3, s[2:3] s_waitcnt vmcnt(0) v_mul_lo_u32 v4, v0, v1 v_mad_u64_u32 v[1:2], null, v0, v0, 0 s_delay_alu instid0(VALU_DEP_1) v_add3_u32 v2, v2, v4, v4 global_store_b64 v3, v[1:2], s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6squarePlS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 16 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 5 .amdhsa_next_free_sgpr 4 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6squarePlS_, .Lfunc_end1-_Z6squarePlS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 24 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9addKernelPiPKiS1_ .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9addKernelPiPKiS1_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 3 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 16 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6squarePlS_ .private_segment_fixed_size: 0 .sgpr_count: 4 .sgpr_spill_count: 0 .symbol: _Z6squarePlS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 5 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001410ac_00000000-6_kernel.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3673: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3673: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ .type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_: .LFB3695: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9addKernelPiPKiS1_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3695: .size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ .globl _Z9addKernelPiPKiS1_ .type _Z9addKernelPiPKiS1_, @function _Z9addKernelPiPKiS1_: .LFB3696: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3696: .size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_ .globl _Z27__device_stub__Z6squarePlS_PlS_ .type _Z27__device_stub__Z6squarePlS_PlS_, @function _Z27__device_stub__Z6squarePlS_PlS_: .LFB3697: .cfi_startproc endbr64 subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 8(%rsp) movq %rsi, (%rsp) movq %fs:40, %rax movq %rax, 104(%rsp) xorl %eax, %eax leaq 8(%rsp), %rax movq %rax, 80(%rsp) movq %rsp, %rax movq %rax, 88(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $1, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) leaq 24(%rsp), %rcx leaq 16(%rsp), %rdx leaq 44(%rsp), %rsi leaq 32(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 104(%rsp), %rax subq %fs:40, %rax jne .L16 addq $120, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 24(%rsp) .cfi_def_cfa_offset 136 pushq 24(%rsp) .cfi_def_cfa_offset 144 leaq 96(%rsp), %r9 movq 60(%rsp), %rcx movl 68(%rsp), %r8d movq 48(%rsp), %rsi movl 56(%rsp), %edx leaq _Z6squarePlS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 128 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE3697: .size _Z27__device_stub__Z6squarePlS_PlS_, .-_Z27__device_stub__Z6squarePlS_PlS_ .globl _Z6squarePlS_ .type _Z6squarePlS_, @function _Z6squarePlS_: .LFB3698: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z27__device_stub__Z6squarePlS_PlS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3698: .size _Z6squarePlS_, .-_Z6squarePlS_ .section .rodata.str1.8,"aMS",@progbits,1 .align 8 .LC0: .string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?" .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "cudaMalloc failed!" .LC2: .string "cudaMemcpy failed!" .LC3: .string "addKernel launch failed: %s\n" .section .rodata.str1.8 .align 8 .LC4: .string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n" .text .globl _Z14squareWithCudaPlS_j .type _Z14squareWithCudaPlS_j, @function _Z14squareWithCudaPlS_j: .LFB3670: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $48, %rsp .cfi_def_cfa_offset 96 movq %rdi, %rbp movq %rsi, %r12 movl %edx, %r13d movq %fs:40, %rax movq %rax, 40(%rsp) xorl %eax, %eax movq $0, (%rsp) movq $0, 8(%rsp) movl $0, %edi call cudaSetDevice@PLT testl %eax, %eax jne .L31 movl %r13d, %r14d salq $3, %r14 movq %rsp, %rdi movq %r14, %rsi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L32 leaq 8(%rsp), %rdi movq %r14, %rsi call cudaMalloc@PLT movl %eax, %ebx testl %eax, %eax jne .L33 movl $1, %ecx movq %r14, %rdx movq %rbp, %rsi movq (%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax jne .L34 movl $1, %ecx movq %r14, %rdx movq %r12, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax jne .L35 movl %r13d, 28(%rsp) movl $1, 32(%rsp) movl $1, 16(%rsp) movl $1, 20(%rsp) movl $0, %r9d movl $0, %r8d movq 28(%rsp), %rdx movl $1, %ecx movq 16(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L36 .L26: call cudaGetLastError@PLT movl %eax, %ebx testl %eax, %eax jne .L37 call cudaDeviceSynchronize@PLT movl %eax, %ebx testl %eax, %eax jne .L38 movl $2, %ecx movq %r14, %rdx movq 8(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movl %eax, %ebx testl %eax, %eax je .L21 leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L31: movl %eax, %ebx leaq .LC0(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT .L21: movq (%rsp), %rdi call cudaFree@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 40(%rsp), %rax subq %fs:40, %rax jne .L39 movl %ebx, %eax addq $48, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L32: .cfi_restore_state leaq .LC1(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L33: leaq .LC1(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L34: leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L35: leaq .LC2(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L36: movq (%rsp), %rsi movq 8(%rsp), %rdi call _Z27__device_stub__Z6squarePlS_PlS_ jmp .L26 .L37: movl %eax, %edi call cudaGetErrorString@PLT movq %rax, %rcx leaq .LC3(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L38: movl %eax, %ecx leaq .LC4(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT jmp .L21 .L39: call __stack_chk_fail@PLT .cfi_endproc .LFE3670: .size _Z14squareWithCudaPlS_j, .-_Z14squareWithCudaPlS_j .section .rodata.str1.1 .LC5: .string "\t" .LC6: .string "\n" .LC7: .string "Square With Cuda failed!" .LC8: .string "%d" .LC9: .string "cudaDeviceReset failed!" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r13 .cfi_def_cfa_offset 16 .cfi_offset 13, -16 pushq %r12 .cfi_def_cfa_offset 24 .cfi_offset 12, -24 pushq %rbp .cfi_def_cfa_offset 32 .cfi_offset 6, -32 pushq %rbx .cfi_def_cfa_offset 40 .cfi_offset 3, -40 leaq -16384(%rsp), %r11 .cfi_def_cfa 11, 16424 .LPSRL0: subq $4096, %rsp orq $0, (%rsp) cmpq %r11, %rsp jne .LPSRL0 .cfi_def_cfa_register 7 subq $24, %rsp .cfi_def_cfa_offset 16448 movq %fs:40, %rax movq %rax, 16392(%rsp) xorl %eax, %eax .L41: movq %rax, (%rsp,%rax,8) addq $1, %rax cmpq $1024, %rax jne .L41 leaq 8192(%rsp), %rdi movl $1024, %ecx movl $0, %eax rep stosq leaq 8192(%rsp), %rsi movq %rsp, %rdi movl $1024, %edx call _Z14squareWithCudaPlS_j movl $0, %ebx leaq .LC8(%rip), %r13 leaq .LC6(%rip), %r12 leaq .LC5(%rip), %rbp testl %eax, %eax jne .L53 .L42: movq 8192(%rsp,%rbx,8), %rdx movq %r13, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT movl %ebx, %edx sarl $31, %edx shrl $30, %edx leal (%rdx,%rbx), %eax andl $3, %eax subl %edx, %eax cmpl $3, %eax movq %rbp, %rsi cmove %r12, %rsi movl $2, %edi movl $0, %eax call __printf_chk@PLT addq $1, %rbx cmpq $1024, %rbx jne .L42 call cudaDeviceReset@PLT testl %eax, %eax jne .L54 leaq _ZSt3cin(%rip), %rdi call _ZNSi3getEv@PLT movl $0, %eax .L40: movq 16392(%rsp), %rdx subq %fs:40, %rdx jne .L55 addq $16408, %rsp .cfi_remember_state .cfi_def_cfa_offset 40 popq %rbx .cfi_def_cfa_offset 32 popq %rbp .cfi_def_cfa_offset 24 popq %r12 .cfi_def_cfa_offset 16 popq %r13 .cfi_def_cfa_offset 8 ret .L53: .cfi_restore_state leaq .LC7(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT leaq _ZSt3cin(%rip), %rdi call _ZNSi3getEv@PLT movl $1, %eax jmp .L40 .L54: leaq .LC9(%rip), %rdx movl $2, %esi movq stderr(%rip), %rdi movl $0, %eax call __fprintf_chk@PLT movl $1, %eax jmp .L40 .L55: call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC10: .string "_Z6squarePlS_" .LC11: .string "_Z9addKernelPiPKiS1_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3700: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _Z6squarePlS_(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC11(%rip), %rdx movq %rdx, %rcx leaq _Z9addKernelPiPKiS1_(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3700: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "kernel.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_ .p2align 4, 0x90 .type _Z24__device_stub__addKernelPiPKiS1_,@function _Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9addKernelPiPKiS1_, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_ .cfi_endproc # -- End function .globl _Z21__device_stub__squarePlS_ # -- Begin function _Z21__device_stub__squarePlS_ .p2align 4, 0x90 .type _Z21__device_stub__squarePlS_,@function _Z21__device_stub__squarePlS_: # @_Z21__device_stub__squarePlS_ .cfi_startproc # %bb.0: subq $88, %rsp .cfi_def_cfa_offset 96 movq %rdi, 56(%rsp) movq %rsi, 48(%rsp) leaq 56(%rsp), %rax movq %rax, 64(%rsp) leaq 48(%rsp), %rax movq %rax, 72(%rsp) leaq 32(%rsp), %rdi leaq 16(%rsp), %rsi leaq 8(%rsp), %rdx movq %rsp, %rcx callq __hipPopCallConfiguration movq 32(%rsp), %rsi movl 40(%rsp), %edx movq 16(%rsp), %rcx movl 24(%rsp), %r8d leaq 64(%rsp), %r9 movl $_Z6squarePlS_, %edi pushq (%rsp) .cfi_adjust_cfa_offset 8 pushq 16(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $104, %rsp .cfi_adjust_cfa_offset -104 retq .Lfunc_end1: .size _Z21__device_stub__squarePlS_, .Lfunc_end1-_Z21__device_stub__squarePlS_ .cfi_endproc # -- End function .globl main # -- Begin function main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $16392, %rsp # imm = 0x4008 .cfi_def_cfa_offset 16416 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 xorl %eax, %eax .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 movq %rax, 8192(%rsp,%rax,8) incq %rax cmpq $1024, %rax # imm = 0x400 jne .LBB2_1 # %bb.2: movq %rsp, %rbx movl $8192, %edx # imm = 0x2000 movq %rbx, %rdi xorl %esi, %esi callq memset@PLT leaq 8192(%rsp), %rdi movq %rbx, %rsi movl $1024, %edx # imm = 0x400 callq _Z14squareWithCudaPlS_j testl %eax, %eax jne .LBB2_9 # %bb.3: # %.preheader.preheader movl $.L.str.3, %ebx xorl %r14d, %r14d .p2align 4, 0x90 .LBB2_4: # %.preheader # =>This Inner Loop Header: Depth=1 movq (%rsp,%r14,8), %rsi movl $.L.str.1, %edi xorl %eax, %eax callq printf movl %r14d, %eax notl %eax testb $3, %al movl $.L.str.2, %edi cmoveq %rbx, %rdi xorl %eax, %eax callq printf incq %r14 cmpq $1024, %r14 # imm = 0x400 jne .LBB2_4 # %bb.5: callq hipDeviceReset testl %eax, %eax jne .LBB2_6 # %bb.7: movl $_ZSt3cin, %edi callq _ZNSi3getEv xorl %eax, %eax .LBB2_8: addq $16392, %rsp # imm = 0x4008 .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .LBB2_9: .cfi_def_cfa_offset 16416 movq stderr(%rip), %rcx movl $.L.str, %edi movl $24, %esi movl $1, %edx callq fwrite@PLT movl $_ZSt3cin, %edi callq _ZNSi3getEv movl $1, %eax jmp .LBB2_8 .LBB2_6: movq stderr(%rip), %rcx movl $.L.str.4, %edi movl $22, %esi movl $1, %edx callq fwrite@PLT movl $1, %eax jmp .LBB2_8 .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .globl _Z14squareWithCudaPlS_j # -- Begin function _Z14squareWithCudaPlS_j .p2align 4, 0x90 .type _Z14squareWithCudaPlS_j,@function _Z14squareWithCudaPlS_j: # @_Z14squareWithCudaPlS_j .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $96, %rsp .cfi_def_cfa_offset 144 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %edx, %ebp movq %rsi, %rbx movq %rdi, %r12 movq $0, 8(%rsp) movq $0, (%rsp) xorl %edi, %edi callq hipSetDevice testl %eax, %eax jne .LBB3_14 # %bb.1: movl %ebp, %r15d leaq (,%r15,8), %r14 leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc testl %eax, %eax jne .LBB3_11 # %bb.2: movq %rsp, %rdi movq %r14, %rsi callq hipMalloc testl %eax, %eax jne .LBB3_11 # %bb.3: movq 8(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB3_12 # %bb.4: movq (%rsp), %rdi movq %rbx, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy testl %eax, %eax jne .LBB3_12 # %bb.5: movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %r15 orq $1, %rdi movl $1, %esi movq %r15, %rdx movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB3_7 # %bb.6: movq (%rsp), %rax movq 8(%rsp), %rcx movq %rax, 72(%rsp) movq %rcx, 64(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z6squarePlS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB3_7: callq hipGetLastError testl %eax, %eax jne .LBB3_18 # %bb.8: callq hipDeviceSynchronize testl %eax, %eax jne .LBB3_19 # %bb.9: movq (%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy xorl %ebx, %ebx testl %eax, %eax je .LBB3_17 # %bb.10: movq stderr(%rip), %rcx movl $.L.str.7, %edi movl $17, %esi movl $1, %edx movl %eax, %ebx jmp .LBB3_16 .LBB3_11: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.6, %edi jmp .LBB3_13 .LBB3_12: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.7, %edi .LBB3_13: movl $17, %esi jmp .LBB3_15 .LBB3_14: movl %eax, %ebx movq stderr(%rip), %rcx movl $.L.str.5, %edi movl $63, %esi .LBB3_15: movl $1, %edx .LBB3_16: callq fwrite@PLT .LBB3_17: movq 8(%rsp), %rdi callq hipFree movq (%rsp), %rdi callq hipFree movl %ebx, %eax addq $96, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .LBB3_18: .cfi_def_cfa_offset 144 movq stderr(%rip), %r14 movl %eax, %ebx movl %eax, %edi callq hipGetErrorString movl $.L.str.8, %esi movq %r14, %rdi movq %rax, %rdx xorl %eax, %eax callq fprintf jmp .LBB3_17 .LBB3_19: movq stderr(%rip), %rdi movl $.L.str.9, %esi movl %eax, %ebx movl %eax, %edx xorl %eax, %eax callq fprintf jmp .LBB3_17 .Lfunc_end3: .size _Z14squareWithCudaPlS_j, .Lfunc_end3-_Z14squareWithCudaPlS_j .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB4_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB4_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9addKernelPiPKiS1_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6squarePlS_, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end4: .size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB5_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB5_2: retq .Lfunc_end5: .size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor .cfi_endproc # -- End function .type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_ .section .rodata,"a",@progbits .globl _Z9addKernelPiPKiS1_ .p2align 3, 0x0 _Z9addKernelPiPKiS1_: .quad _Z24__device_stub__addKernelPiPKiS1_ .size _Z9addKernelPiPKiS1_, 8 .type _Z6squarePlS_,@object # @_Z6squarePlS_ .globl _Z6squarePlS_ .p2align 3, 0x0 _Z6squarePlS_: .quad _Z21__device_stub__squarePlS_ .size _Z6squarePlS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Square With Cuda failed!" .size .L.str, 25 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "%d" .size .L.str.1, 3 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "\t" .size .L.str.2, 2 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "\n" .size .L.str.3, 2 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "hipDeviceReset failed!" .size .L.str.4, 23 .type .L.str.5,@object # @.str.5 .L.str.5: .asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?" .size .L.str.5, 64 .type .L.str.6,@object # @.str.6 .L.str.6: .asciz "hipMalloc failed!" .size .L.str.6, 18 .type .L.str.7,@object # @.str.7 .L.str.7: .asciz "hipMemcpy failed!" .size .L.str.7, 18 .type .L.str.8,@object # @.str.8 .L.str.8: .asciz "addKernel launch failed: %s\n" .size .L.str.8, 29 .type .L.str.9,@object # @.str.9 .L.str.9: .asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n" .size .L.str.9, 72 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9addKernelPiPKiS1_" .size .L__unnamed_1, 21 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6squarePlS_" .size .L__unnamed_2, 14 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__addKernelPiPKiS1_ .addrsig_sym _Z21__device_stub__squarePlS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9addKernelPiPKiS1_ .addrsig_sym _Z6squarePlS_ .addrsig_sym _ZSt3cin .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; cudaMalloc( (void**)&d_a, N*sizeof(float) ); cudaMalloc( (void**)&d_b, N*sizeof(float) ); cudaMemcpy( d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; cudaMemcpy( h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; cudaFree(d_a); cudaFree(d_b); delete [] h_a; delete [] h_b; }
code for sm_80 Function : _Z11scaleVectorfPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */ /* 0x001fca00078e0204 */ /*0040*/ ISETP.GT.AND P0, PT, R4, 0x7fff, PT ; /* 0x00007fff0400780c */ /* 0x000fda0003f04270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x000fcc00078e0205 */ /*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */ /* 0x000fc800078e0205 */ /*00b0*/ FMUL R7, R2, c[0x0][0x160] ; /* 0x0000580002077a20 */ /* 0x004fca0000400000 */ /*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*00d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; cudaMalloc( (void**)&d_a, N*sizeof(float) ); cudaMalloc( (void**)&d_b, N*sizeof(float) ); cudaMemcpy( d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; cudaMemcpy( h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; cudaFree(d_a); cudaFree(d_b); delete [] h_a; delete [] h_b; }
.file "tmpxft_000ed61c_00000000-6_scale.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ .type _Z34__device_stub__Z11scaleVectorfPfS_fPfS_, @function _Z34__device_stub__Z11scaleVectorfPfS_fPfS_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movss %xmm0, 28(%rsp) movq %rdi, 16(%rsp) movq %rsi, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11scaleVectorfPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z34__device_stub__Z11scaleVectorfPfS_fPfS_, .-_Z34__device_stub__Z11scaleVectorfPfS_fPfS_ .globl _Z11scaleVectorfPfS_ .type _Z11scaleVectorfPfS_, @function _Z11scaleVectorfPfS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z11scaleVectorfPfS_, .-_Z11scaleVectorfPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Initializing data on GPU\n" .LC2: .string "Launching kernels on GPU\n" .LC4: .string "Downloading data\n" .LC5: .string "Verifying results\n" .LC6: .string "Done!\n" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $131072, %edi call _Znam@PLT movq %rax, %r13 movl $131072, %edi call _Znam@PLT movq %rax, 8(%rsp) movl $0, %eax movss .LC0(%rip), %xmm1 .L12: pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, 0(%r13,%rax,4) addq $1, %rax cmpq $32768, %rax jne .L12 leaq .LC1(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq 16(%rsp), %rdi movl $131072, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $131072, %esi call cudaMalloc@PLT movl $1, %ecx movl $131072, %edx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT leaq .LC2(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $256, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $128, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L13: leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $2, %ecx movl $131072, %edx movq 24(%rsp), %rsi movq 8(%rsp), %r15 movq %r15, %rdi call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %r15, %r12 leaq 131072(%r15), %r15 movq %rbx, %r14 jmp .L18 .L23: movq 24(%rsp), %rsi movq 16(%rsp), %rdi movss .LC3(%rip), %xmm0 call _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ jmp .L13 .L26: movq 56(%rsp), %rax subq %fs:40, %rax jne .L24 call _ZSt16__throw_bad_castv@PLT .L24: call __stack_chk_fail@PLT .L16: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi .L17: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $4, %r12 cmpq %r15, %r12 je .L25 .L18: pxor %xmm0, %xmm0 cvtss2sd (%r12), %xmm0 movq %r14, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L26 cmpb $0, 56(%rbp) je .L16 movzbl 67(%rbp), %esi jmp .L17 .L25: leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call _ZdaPv@PLT movq 8(%rsp), %rdi call _ZdaPv@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L27 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z11scaleVectorfPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z11scaleVectorfPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1056964608 .align 4 .LC3: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; cudaMalloc( (void**)&d_a, N*sizeof(float) ); cudaMalloc( (void**)&d_b, N*sizeof(float) ); cudaMemcpy( d_a, h_a, N*sizeof(float), cudaMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; cudaMemcpy( h_b, d_b, N*sizeof(float), cudaMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; cudaFree(d_a); cudaFree(d_b); delete [] h_a; delete [] h_b; }
#include <hip/hip_runtime.h> #include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; hipMalloc( (void**)&d_a, N*sizeof(float) ); hipMalloc( (void**)&d_b, N*sizeof(float) ); hipMemcpy( d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; hipMemcpy( h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; hipFree(d_a); hipFree(d_b); delete [] h_a; delete [] h_b; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; hipMalloc( (void**)&d_a, N*sizeof(float) ); hipMalloc( (void**)&d_b, N*sizeof(float) ); hipMemcpy( d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; hipMemcpy( h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; hipFree(d_a); hipFree(d_b); delete [] h_a; delete [] h_b; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11scaleVectorfPfS_ .globl _Z11scaleVectorfPfS_ .p2align 8 .type _Z11scaleVectorfPfS_,@function _Z11scaleVectorfPfS_: s_load_b32 s2, s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x8000, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_load_b32 s0, s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v2, s0, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11scaleVectorfPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11scaleVectorfPfS_, .Lfunc_end0-_Z11scaleVectorfPfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11scaleVectorfPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11scaleVectorfPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <iostream> #include <cassert> #define N 32768 __global__ void scaleVector(float scale, float * input, float * output) { int tid = threadIdx.x + blockIdx.x * blockDim.x; if (tid < N) { output[tid] = input[tid] * scale; } } int main() { float * h_a = new float[N]; float * h_b = new float[N]; float * d_a; float * d_b; const float scale = 2.; for (int i=0; i<N; i++) h_a[i] = (float)i/2.; std::cout << "Initializing data on GPU\n"; hipMalloc( (void**)&d_a, N*sizeof(float) ); hipMalloc( (void**)&d_b, N*sizeof(float) ); hipMemcpy( d_a, h_a, N*sizeof(float), hipMemcpyHostToDevice ); std::cout << "Launching kernels on GPU\n"; const int nblocks = 128; const int nthreads = 256; scaleVector<<< nblocks, nthreads >>>(scale, d_a, d_b); std::cout << "Downloading data\n"; hipMemcpy( h_b, d_b, N*sizeof(float), hipMemcpyDeviceToHost ); std::cout << "Verifying results\n"; for (int i=0; i<N; i++) { std::cout << h_b[i] << std::endl; assert((double)i == h_b[i]); } std::cout << "Done!\n"; hipFree(d_a); hipFree(d_b); delete [] h_a; delete [] h_b; }
.text .file "scale.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__scaleVectorfPfS_ # -- Begin function _Z26__device_stub__scaleVectorfPfS_ .p2align 4, 0x90 .type _Z26__device_stub__scaleVectorfPfS_,@function _Z26__device_stub__scaleVectorfPfS_: # @_Z26__device_stub__scaleVectorfPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movss %xmm0, 12(%rsp) movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11scaleVectorfPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z26__device_stub__scaleVectorfPfS_, .Lfunc_end0-_Z26__device_stub__scaleVectorfPfS_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x3fe0000000000000 # double 0.5 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $131072, %edi # imm = 0x20000 callq _Znam movq %rax, %rbx movl $131072, %edi # imm = 0x20000 callq _Znam movq %rax, %r14 xorl %eax, %eax movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm1, %xmm1 cvtsi2sd %eax, %xmm1 mulsd %xmm0, %xmm1 cvtsd2ss %xmm1, %xmm1 movss %xmm1, (%rbx,%rax,4) incq %rax cmpq $32768, %rax # imm = 0x8000 jne .LBB1_1 # %bb.2: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 16(%rsp), %rdi movl $131072, %esi # imm = 0x20000 callq hipMalloc leaq 8(%rsp), %rdi movl $131072, %esi # imm = 0x20000 callq hipMalloc movq 16(%rsp), %rdi movl $131072, %edx # imm = 0x20000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movabsq $4294967424, %rdi # imm = 0x100000080 leaq 128(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movl $1073741824, 28(%rsp) # imm = 0x40000000 movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11scaleVectorfPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 8(%rsp), %rsi movl $131072, %edx # imm = 0x20000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $18, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %r12d, %r12d jmp .LBB1_5 .p2align 4, 0x90 .LBB1_8: # in Loop: Header=BB1_5 Depth=1 movq %r15, %rdi movq %rax, %r13 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r13, %rax .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit # in Loop: Header=BB1_5 Depth=1 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r12 cmpq $32768, %r12 # imm = 0x8000 je .LBB1_10 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB1_11 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # in Loop: Header=BB1_5 Depth=1 cmpb $0, 56(%r15) je .LBB1_8 # %bb.7: # in Loop: Header=BB1_5 Depth=1 movzbl 67(%r15), %ecx jmp .LBB1_9 .LBB1_10: movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_11: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11scaleVectorfPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11scaleVectorfPfS_,@object # @_Z11scaleVectorfPfS_ .section .rodata,"a",@progbits .globl _Z11scaleVectorfPfS_ .p2align 3, 0x0 _Z11scaleVectorfPfS_: .quad _Z26__device_stub__scaleVectorfPfS_ .size _Z11scaleVectorfPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Initializing data on GPU\n" .size .L.str, 26 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Launching kernels on GPU\n" .size .L.str.1, 26 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Downloading data\n" .size .L.str.2, 18 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Verifying results\n" .size .L.str.3, 19 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Done!\n" .size .L.str.4, 7 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11scaleVectorfPfS_" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__scaleVectorfPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11scaleVectorfPfS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z11scaleVectorfPfS_ .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */ /* 0x000e280000002100 */ /*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e240000002500 */ /*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */ /* 0x001fca00078e0204 */ /*0040*/ ISETP.GT.AND P0, PT, R4, 0x7fff, PT ; /* 0x00007fff0400780c */ /* 0x000fda0003f04270 */ /*0050*/ @P0 EXIT ; /* 0x000000000000094d */ /* 0x000fea0003800000 */ /*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */ /* 0x000fe200000001ff */ /*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fd20000000a00 */ /*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */ /* 0x000fcc00078e0205 */ /*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */ /* 0x000ea2000c1e1900 */ /*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */ /* 0x000fc800078e0205 */ /*00b0*/ FMUL R7, R2, c[0x0][0x160] ; /* 0x0000580002077a20 */ /* 0x004fca0000400000 */ /*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */ /* 0x000fe2000c101904 */ /*00d0*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*00f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0100*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0110*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0120*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0130*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z11scaleVectorfPfS_ .globl _Z11scaleVectorfPfS_ .p2align 8 .type _Z11scaleVectorfPfS_,@function _Z11scaleVectorfPfS_: s_load_b32 s2, s[0:1], 0x24 s_waitcnt lgkmcnt(0) s_and_b32 s2, s2, 0xffff s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1] s_mov_b32 s2, exec_lo v_cmpx_gt_i32_e32 0x8000, v1 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x8 v_ashrrev_i32_e32 v2, 31, v1 s_load_b32 s0, s[0:1], 0x0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_lshlrev_b64 v[0:1], 2, v[1:2] s_waitcnt lgkmcnt(0) v_add_co_u32 v2, vcc_lo, s4, v0 s_delay_alu instid0(VALU_DEP_2) v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo v_add_co_u32 v0, vcc_lo, s6, v0 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo global_load_b32 v2, v[2:3], off s_waitcnt vmcnt(0) v_mul_f32_e32 v2, s0, v2 global_store_b32 v[0:1], v2, off .LBB0_2: s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z11scaleVectorfPfS_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 280 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z11scaleVectorfPfS_, .Lfunc_end0-_Z11scaleVectorfPfS_ .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .offset: 0 .size: 4 .value_kind: by_value - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: hidden_block_count_x - .offset: 28 .size: 4 .value_kind: hidden_block_count_y - .offset: 32 .size: 4 .value_kind: hidden_block_count_z - .offset: 36 .size: 2 .value_kind: hidden_group_size_x - .offset: 38 .size: 2 .value_kind: hidden_group_size_y - .offset: 40 .size: 2 .value_kind: hidden_group_size_z - .offset: 42 .size: 2 .value_kind: hidden_remainder_x - .offset: 44 .size: 2 .value_kind: hidden_remainder_y - .offset: 46 .size: 2 .value_kind: hidden_remainder_z - .offset: 64 .size: 8 .value_kind: hidden_global_offset_x - .offset: 72 .size: 8 .value_kind: hidden_global_offset_y - .offset: 80 .size: 8 .value_kind: hidden_global_offset_z - .offset: 88 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 280 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z11scaleVectorfPfS_ .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z11scaleVectorfPfS_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000ed61c_00000000-6_scale.cudafe1.cpp" .text #APP .globl _ZSt21ios_base_library_initv #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB3672: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3672: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ .type _Z34__device_stub__Z11scaleVectorfPfS_fPfS_, @function _Z34__device_stub__Z11scaleVectorfPfS_fPfS_: .LFB3694: .cfi_startproc endbr64 subq $136, %rsp .cfi_def_cfa_offset 144 movss %xmm0, 28(%rsp) movq %rdi, 16(%rsp) movq %rsi, 8(%rsp) movq %fs:40, %rax movq %rax, 120(%rsp) xorl %eax, %eax leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 120(%rsp), %rax subq %fs:40, %rax jne .L8 addq $136, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 152 pushq 40(%rsp) .cfi_def_cfa_offset 160 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z11scaleVectorfPfS_(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 144 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE3694: .size _Z34__device_stub__Z11scaleVectorfPfS_fPfS_, .-_Z34__device_stub__Z11scaleVectorfPfS_fPfS_ .globl _Z11scaleVectorfPfS_ .type _Z11scaleVectorfPfS_, @function _Z11scaleVectorfPfS_: .LFB3695: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3695: .size _Z11scaleVectorfPfS_, .-_Z11scaleVectorfPfS_ .section .rodata.str1.1,"aMS",@progbits,1 .LC1: .string "Initializing data on GPU\n" .LC2: .string "Launching kernels on GPU\n" .LC4: .string "Downloading data\n" .LC5: .string "Verifying results\n" .LC6: .string "Done!\n" .text .globl main .type main, @function main: .LFB3669: .cfi_startproc endbr64 pushq %r15 .cfi_def_cfa_offset 16 .cfi_offset 15, -16 pushq %r14 .cfi_def_cfa_offset 24 .cfi_offset 14, -24 pushq %r13 .cfi_def_cfa_offset 32 .cfi_offset 13, -32 pushq %r12 .cfi_def_cfa_offset 40 .cfi_offset 12, -40 pushq %rbp .cfi_def_cfa_offset 48 .cfi_offset 6, -48 pushq %rbx .cfi_def_cfa_offset 56 .cfi_offset 3, -56 subq $72, %rsp .cfi_def_cfa_offset 128 movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movl $131072, %edi call _Znam@PLT movq %rax, %r13 movl $131072, %edi call _Znam@PLT movq %rax, 8(%rsp) movl $0, %eax movss .LC0(%rip), %xmm1 .L12: pxor %xmm0, %xmm0 cvtsi2ssl %eax, %xmm0 mulss %xmm1, %xmm0 movss %xmm0, 0(%r13,%rax,4) addq $1, %rax cmpq $32768, %rax jne .L12 leaq .LC1(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT leaq 16(%rsp), %rdi movl $131072, %esi call cudaMalloc@PLT leaq 24(%rsp), %rdi movl $131072, %esi call cudaMalloc@PLT movl $1, %ecx movl $131072, %edx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT leaq .LC2(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $256, 44(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $128, 32(%rsp) movl $1, 36(%rsp) movl $1, 40(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L23 .L13: leaq .LC4(%rip), %rsi leaq _ZSt4cout(%rip), %rbx movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movl $2, %ecx movl $131072, %edx movq 24(%rsp), %rsi movq 8(%rsp), %r15 movq %r15, %rdi call cudaMemcpy@PLT leaq .LC5(%rip), %rsi movq %rbx, %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq %r15, %r12 leaq 131072(%r15), %r15 movq %rbx, %r14 jmp .L18 .L23: movq 24(%rsp), %rsi movq 16(%rsp), %rdi movss .LC3(%rip), %xmm0 call _Z34__device_stub__Z11scaleVectorfPfS_fPfS_ jmp .L13 .L26: movq 56(%rsp), %rax subq %fs:40, %rax jne .L24 call _ZSt16__throw_bad_castv@PLT .L24: call __stack_chk_fail@PLT .L16: movq %rbp, %rdi call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT movq 0(%rbp), %rax movl $10, %esi movq %rbp, %rdi call *48(%rax) movl %eax, %esi .L17: movsbl %sil, %esi movq %rbx, %rdi call _ZNSo3putEc@PLT movq %rax, %rdi call _ZNSo5flushEv@PLT addq $4, %r12 cmpq %r15, %r12 je .L25 .L18: pxor %xmm0, %xmm0 cvtss2sd (%r12), %xmm0 movq %r14, %rdi call _ZNSo9_M_insertIdEERSoT_@PLT movq %rax, %rbx movq (%rax), %rax movq -24(%rax), %rax movq 240(%rbx,%rax), %rbp testq %rbp, %rbp je .L26 cmpb $0, 56(%rbp) je .L16 movzbl 67(%rbp), %esi jmp .L17 .L25: leaq .LC6(%rip), %rsi leaq _ZSt4cout(%rip), %rdi call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq %r13, %rdi call _ZdaPv@PLT movq 8(%rsp), %rdi call _ZdaPv@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L27 movl $0, %eax addq $72, %rsp .cfi_remember_state .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %rbp .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 ret .L27: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE3669: .size main, .-main .section .rodata.str1.1 .LC7: .string "_Z11scaleVectorfPfS_" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB3697: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _Z11scaleVectorfPfS_(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE3697: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC0: .long 1056964608 .align 4 .LC3: .long 1073741824 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "scale.hip" # Start of file scope inline assembly .globl _ZSt21ios_base_library_initv # End of file scope inline assembly .globl _Z26__device_stub__scaleVectorfPfS_ # -- Begin function _Z26__device_stub__scaleVectorfPfS_ .p2align 4, 0x90 .type _Z26__device_stub__scaleVectorfPfS_,@function _Z26__device_stub__scaleVectorfPfS_: # @_Z26__device_stub__scaleVectorfPfS_ .cfi_startproc # %bb.0: subq $104, %rsp .cfi_def_cfa_offset 112 movss %xmm0, 12(%rsp) movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) leaq 12(%rsp), %rax movq %rax, 80(%rsp) leaq 72(%rsp), %rax movq %rax, 88(%rsp) leaq 64(%rsp), %rax movq %rax, 96(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z11scaleVectorfPfS_, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $120, %rsp .cfi_adjust_cfa_offset -120 retq .Lfunc_end0: .size _Z26__device_stub__scaleVectorfPfS_, .Lfunc_end0-_Z26__device_stub__scaleVectorfPfS_ .cfi_endproc # -- End function .section .rodata.cst8,"aM",@progbits,8 .p2align 3, 0x0 # -- Begin function main .LCPI1_0: .quad 0x3fe0000000000000 # double 0.5 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r15 .cfi_def_cfa_offset 16 pushq %r14 .cfi_def_cfa_offset 24 pushq %r13 .cfi_def_cfa_offset 32 pushq %r12 .cfi_def_cfa_offset 40 pushq %rbx .cfi_def_cfa_offset 48 subq $128, %rsp .cfi_def_cfa_offset 176 .cfi_offset %rbx, -48 .cfi_offset %r12, -40 .cfi_offset %r13, -32 .cfi_offset %r14, -24 .cfi_offset %r15, -16 movl $131072, %edi # imm = 0x20000 callq _Znam movq %rax, %rbx movl $131072, %edi # imm = 0x20000 callq _Znam movq %rax, %r14 xorl %eax, %eax movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero .p2align 4, 0x90 .LBB1_1: # =>This Inner Loop Header: Depth=1 xorps %xmm1, %xmm1 cvtsi2sd %eax, %xmm1 mulsd %xmm0, %xmm1 cvtsd2ss %xmm1, %xmm1 movss %xmm1, (%rbx,%rax,4) incq %rax cmpq $32768, %rax # imm = 0x8000 jne .LBB1_1 # %bb.2: movl $_ZSt4cout, %edi movl $.L.str, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l leaq 16(%rsp), %rdi movl $131072, %esi # imm = 0x20000 callq hipMalloc leaq 8(%rsp), %rdi movl $131072, %esi # imm = 0x20000 callq hipMalloc movq 16(%rsp), %rdi movl $131072, %edx # imm = 0x20000 movq %rbx, %rsi movl $1, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.1, %esi movl $25, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movabsq $4294967424, %rdi # imm = 0x100000080 leaq 128(%rdi), %rdx movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_4 # %bb.3: movq 16(%rsp), %rax movq 8(%rsp), %rcx movl $1073741824, 28(%rsp) # imm = 0x40000000 movq %rax, 88(%rsp) movq %rcx, 80(%rsp) leaq 28(%rsp), %rax movq %rax, 96(%rsp) leaq 88(%rsp), %rax movq %rax, 104(%rsp) leaq 80(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rdi leaq 48(%rsp), %rsi leaq 40(%rsp), %rdx leaq 32(%rsp), %rcx callq __hipPopCallConfiguration movq 64(%rsp), %rsi movl 72(%rsp), %edx movq 48(%rsp), %rcx movl 56(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z11scaleVectorfPfS_, %edi pushq 32(%rsp) .cfi_adjust_cfa_offset 8 pushq 48(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_4: movl $_ZSt4cout, %edi movl $.L.str.2, %esi movl $17, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 8(%rsp), %rsi movl $131072, %edx # imm = 0x20000 movq %r14, %rdi movl $2, %ecx callq hipMemcpy movl $_ZSt4cout, %edi movl $.L.str.3, %esi movl $18, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l xorl %r12d, %r12d jmp .LBB1_5 .p2align 4, 0x90 .LBB1_8: # in Loop: Header=BB1_5 Depth=1 movq %r15, %rdi movq %rax, %r13 callq _ZNKSt5ctypeIcE13_M_widen_initEv movq (%r15), %rax movq %r15, %rdi movl $10, %esi callq *48(%rax) movl %eax, %ecx movq %r13, %rax .LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit # in Loop: Header=BB1_5 Depth=1 movsbl %cl, %esi movq %rax, %rdi callq _ZNSo3putEc movq %rax, %rdi callq _ZNSo5flushEv incq %r12 cmpq $32768, %r12 # imm = 0x8000 je .LBB1_10 .LBB1_5: # =>This Inner Loop Header: Depth=1 movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 movl $_ZSt4cout, %edi callq _ZNSo9_M_insertIdEERSoT_ movq (%rax), %rcx movq -24(%rcx), %rcx movq 240(%rax,%rcx), %r15 testq %r15, %r15 je .LBB1_11 # %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i # in Loop: Header=BB1_5 Depth=1 cmpb $0, 56(%r15) je .LBB1_8 # %bb.7: # in Loop: Header=BB1_5 Depth=1 movzbl 67(%r15), %ecx jmp .LBB1_9 .LBB1_10: movl $_ZSt4cout, %edi movl $.L.str.4, %esi movl $6, %edx callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree movq %rbx, %rdi callq _ZdaPv movq %r14, %rdi callq _ZdaPv xorl %eax, %eax addq $128, %rsp .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %r12 .cfi_def_cfa_offset 32 popq %r13 .cfi_def_cfa_offset 24 popq %r14 .cfi_def_cfa_offset 16 popq %r15 .cfi_def_cfa_offset 8 retq .LBB1_11: .cfi_def_cfa_offset 176 callq _ZSt16__throw_bad_castv .Lfunc_end1: .size main, .Lfunc_end1-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z11scaleVectorfPfS_, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z11scaleVectorfPfS_,@object # @_Z11scaleVectorfPfS_ .section .rodata,"a",@progbits .globl _Z11scaleVectorfPfS_ .p2align 3, 0x0 _Z11scaleVectorfPfS_: .quad _Z26__device_stub__scaleVectorfPfS_ .size _Z11scaleVectorfPfS_, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "Initializing data on GPU\n" .size .L.str, 26 .type .L.str.1,@object # @.str.1 .L.str.1: .asciz "Launching kernels on GPU\n" .size .L.str.1, 26 .type .L.str.2,@object # @.str.2 .L.str.2: .asciz "Downloading data\n" .size .L.str.2, 18 .type .L.str.3,@object # @.str.3 .L.str.3: .asciz "Verifying results\n" .size .L.str.3, 19 .type .L.str.4,@object # @.str.4 .L.str.4: .asciz "Done!\n" .size .L.str.4, 7 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z11scaleVectorfPfS_" .size .L__unnamed_1, 21 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z26__device_stub__scaleVectorfPfS_ .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z11scaleVectorfPfS_ .addrsig_sym _ZSt4cout .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; cudaMalloc(&dev_a, n * sizeof(float)); cudaMalloc(&dev_b, n * sizeof(float)); cudaMalloc(&dev_c, n * sizeof(float)); cudaMemcpy(dev_a, a, n * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(dev_b, b, n * sizeof(float), cudaMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); cudaMemcpy(c, dev_c, n * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
code for sm_80 Function : _Z9dev_add_nPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0030*/ ISETP.GE.AND P0, PT, R7, 0x5, PT ; /* 0x000000050700780c */ /* 0x001fda0003f06270 */ /*0040*/ @P0 BRA 0xe0 ; /* 0x0000009000000947 */ /* 0x000fea0003800000 */ /*0050*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */ /* 0x000fd400000001ff */ /*0060*/ IMAD.WIDE R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */ /* 0x000fc800078e0204 */ /*0070*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */ /* 0x000fe400078e0204 */ /*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1900 */ /*00a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */ /* 0x000fe20003800000 */ /*00b0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */ /* 0x004fca0000000000 */ /*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */ /* 0x0001e80000004800 */ /*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*00e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */ /* 0x000e620000004800 */ /*00f0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fca0000000f00 */ /*0100*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */ /* 0x000fca00078e0202 */ /*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x002fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; cudaMalloc(&dev_a, n * sizeof(float)); cudaMalloc(&dev_b, n * sizeof(float)); cudaMalloc(&dev_c, n * sizeof(float)); cudaMemcpy(dev_a, a, n * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(dev_b, b, n * sizeof(float), cudaMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); cudaMemcpy(c, dev_c, n * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
.file "tmpxft_001581e9_00000000-6_fail.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i .type _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i, @function _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9dev_add_nPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i .globl _Z9dev_add_nPfS_S_i .type _Z9dev_add_nPfS_S_i, @function _Z9dev_add_nPfS_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z9dev_add_nPfS_S_i, .-_Z9dev_add_nPfS_S_i .globl _Z5add_nPfS_S_i .type _Z5add_nPfS_S_i, @function _Z5add_nPfS_S_i: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r14 movq %rsi, %r13 movq %rdx, %r12 movl %ecx, %ebp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movslq %ecx, %rbx salq $2, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl %ebp, 44(%rsp) movl $1, 48(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L16 addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movl %ebp, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5add_nPfS_S_i, .-_Z5add_nPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC10: .string "c[%d] = %.3f%c" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $152, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movl $0x00000000, (%rsp) movss .LC1(%rip), %xmm8 movss %xmm8, 4(%rsp) movss .LC2(%rip), %xmm7 movss %xmm7, 8(%rsp) movss .LC3(%rip), %xmm6 movss %xmm6, 12(%rsp) movss .LC4(%rip), %xmm5 movss %xmm5, 16(%rsp) movss .LC5(%rip), %xmm4 movss %xmm4, 20(%rsp) movss .LC6(%rip), %xmm3 movss %xmm3, 24(%rsp) movss .LC7(%rip), %xmm2 movss %xmm2, 28(%rsp) movss .LC8(%rip), %xmm1 movss %xmm1, 32(%rsp) movss .LC9(%rip), %xmm0 movss %xmm0, 36(%rsp) movl $0x00000000, 48(%rsp) movss %xmm8, 52(%rsp) movss %xmm7, 56(%rsp) movss %xmm6, 60(%rsp) movss %xmm5, 64(%rsp) movss %xmm4, 68(%rsp) movss %xmm3, 72(%rsp) movss %xmm2, 76(%rsp) movss %xmm1, 80(%rsp) movss %xmm0, 84(%rsp) pxor %xmm0, %xmm0 movaps %xmm0, 96(%rsp) movaps %xmm0, 112(%rsp) movq $0, 128(%rsp) leaq 96(%rsp), %rdx leaq 48(%rsp), %rsi movq %rsp, %rdi movl $10, %ecx call _Z5add_nPfS_S_i movl $0, %ebx leaq .LC10(%rip), %rbp jmp .L19 .L22: pxor %xmm0, %xmm0 cvtss2sd 96(%rsp,%rbx,4), %xmm0 movl $32, %ecx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx .L19: movl %ebx, %edx cmpq $9, %rbx jne .L22 pxor %xmm0, %xmm0 cvtss2sd 132(%rsp), %xmm0 movl $10, %ecx movl $9, %edx leaq .LC10(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L23 movl $0, %eax addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z9dev_add_nPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z9dev_add_nPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .align 4 .LC3: .long 1077936128 .align 4 .LC4: .long 1082130432 .align 4 .LC5: .long 1084227584 .align 4 .LC6: .long 1086324736 .align 4 .LC7: .long 1088421888 .align 4 .LC8: .long 1090519040 .align 4 .LC9: .long 1091567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; cudaMalloc(&dev_a, n * sizeof(float)); cudaMalloc(&dev_b, n * sizeof(float)); cudaMalloc(&dev_c, n * sizeof(float)); cudaMemcpy(dev_a, a, n * sizeof(float), cudaMemcpyHostToDevice); cudaMemcpy(dev_b, b, n * sizeof(float), cudaMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); cudaMemcpy(c, dev_c, n * sizeof(float), cudaMemcpyDeviceToHost); cudaFree(dev_a); cudaFree(dev_b); cudaFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
#include <hip/hip_runtime.h> #include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; hipMalloc(&dev_a, n * sizeof(float)); hipMalloc(&dev_b, n * sizeof(float)); hipMalloc(&dev_c, n * sizeof(float)); hipMemcpy(dev_a, a, n * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(dev_b, b, n * sizeof(float), hipMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); hipMemcpy(c, dev_c, n * sizeof(float), hipMemcpyDeviceToHost); hipFree(dev_a); hipFree(dev_b); hipFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; hipMalloc(&dev_a, n * sizeof(float)); hipMalloc(&dev_b, n * sizeof(float)); hipMalloc(&dev_c, n * sizeof(float)); hipMemcpy(dev_a, a, n * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(dev_b, b, n * sizeof(float), hipMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); hipMemcpy(c, dev_c, n * sizeof(float), hipMemcpyDeviceToHost); hipFree(dev_a); hipFree(dev_b); hipFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9dev_add_nPfS_S_i .globl _Z9dev_add_nPfS_S_i .p2align 8 .type _Z9dev_add_nPfS_S_i,@function _Z9dev_add_nPfS_S_i: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 5, v0 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v2, v1, s[4:5] global_load_b32 v3, v1, s[6:7] s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 v_lshlrev_b32_e32 v0, 2, v0 s_load_b64 s[0:1], s[0:1], 0x10 ds_load_b32 v1, v0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9dev_add_nPfS_S_i .amdhsa_group_segment_fixed_size 40 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9dev_add_nPfS_S_i, .Lfunc_end0-_Z9dev_add_nPfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 40 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9dev_add_nPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9dev_add_nPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <stdio.h> #define N 10 __global__ void dev_add_n(float *a, float *b, float *c, int n) { __shared__ float tmp[N]; int id = threadIdx.x; if (id < N / 2) { tmp[id] = a[id] + b[id]; __syncthreads(); } c[id] = tmp[id]; } void add_n(float a[], float b[], float c[], int n) { float *dev_a, *dev_b, *dev_c; hipMalloc(&dev_a, n * sizeof(float)); hipMalloc(&dev_b, n * sizeof(float)); hipMalloc(&dev_c, n * sizeof(float)); hipMemcpy(dev_a, a, n * sizeof(float), hipMemcpyHostToDevice); hipMemcpy(dev_b, b, n * sizeof(float), hipMemcpyHostToDevice); dev_add_n<<<1, n>>>(dev_a, dev_b, dev_c, n); hipMemcpy(c, dev_c, n * sizeof(float), hipMemcpyDeviceToHost); hipFree(dev_a); hipFree(dev_b); hipFree(dev_c); } int main() { float a[N] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, b[N] = {0, 1, 2 ,3, 4, 5, 6 ,7, 8, 9}, c[N] = {0}; add_n(a, b, c, N); for (int i = 0; i < N; ++i) printf("c[%d] = %.3f%c", i, c[i], i + 1 == N ? '\n' : ' '); }
.text .file "fail.hip" .globl _Z24__device_stub__dev_add_nPfS_S_i # -- Begin function _Z24__device_stub__dev_add_nPfS_S_i .p2align 4, 0x90 .type _Z24__device_stub__dev_add_nPfS_S_i,@function _Z24__device_stub__dev_add_nPfS_S_i: # @_Z24__device_stub__dev_add_nPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9dev_add_nPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z24__device_stub__dev_add_nPfS_S_i, .Lfunc_end0-_Z24__device_stub__dev_add_nPfS_S_i .cfi_endproc # -- End function .globl _Z5add_nPfS_S_i # -- Begin function _Z5add_nPfS_S_i .p2align 4, 0x90 .type _Z5add_nPfS_S_i,@function _Z5add_nPfS_S_i: # @_Z5add_nPfS_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %ebp movq %rdx, %rbx movq %rsi, %r15 movq %rdi, %r12 movslq %ecx, %r13 leaq (,%r13,4), %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 24(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movl %r13d, %edx movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %rdx orq $1, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl %ebp, 36(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z9dev_add_nPfS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5add_nPfS_S_i, .Lfunc_end1-_Z5add_nPfS_S_i .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI2_0: .long 0x00000000 # float 0 .long 0x3f800000 # float 1 .long 0x40000000 # float 2 .long 0x40400000 # float 3 .LCPI2_1: .long 0x40800000 # float 4 .long 0x40a00000 # float 5 .long 0x40c00000 # float 6 .long 0x40e00000 # float 7 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $136, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0] movaps %xmm0, 96(%rsp) movaps .LCPI2_1(%rip), %xmm1 # xmm1 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0] movaps %xmm1, 112(%rsp) movabsq $4688247213183205376, %rax # imm = 0x4110000041000000 movq %rax, 128(%rsp) movaps %xmm0, 48(%rsp) movaps %xmm1, 64(%rsp) movq %rax, 80(%rsp) xorps %xmm0, %xmm0 movaps %xmm0, 16(%rsp) movaps %xmm0, (%rsp) movq $0, 32(%rsp) leaq 96(%rsp), %rdi leaq 48(%rsp), %rsi movq %rsp, %rdx movl $10, %ebx movl $10, %ecx callq _Z5add_nPfS_S_i xorl %esi, %esi .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 movss (%rsp,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 leaq 1(%rsi), %r14 cmpq $9, %rsi movl $32, %edx cmovel %ebx, %edx movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi movb $1, %al callq printf movq %r14, %rsi cmpq $10, %r14 jne .LBB2_1 # %bb.2: xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9dev_add_nPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z9dev_add_nPfS_S_i,@object # @_Z9dev_add_nPfS_S_i .section .rodata,"a",@progbits .globl _Z9dev_add_nPfS_S_i .p2align 3, 0x0 _Z9dev_add_nPfS_S_i: .quad _Z24__device_stub__dev_add_nPfS_S_i .size _Z9dev_add_nPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "c[%d] = %.3f%c" .size .L.str, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9dev_add_nPfS_S_i" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__dev_add_nPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9dev_add_nPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z9dev_add_nPfS_S_i .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */ /* 0x000fe40000000f00 */ /*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fe20000000a00 */ /*0030*/ ISETP.GE.AND P0, PT, R7, 0x5, PT ; /* 0x000000050700780c */ /* 0x001fda0003f06270 */ /*0040*/ @P0 BRA 0xe0 ; /* 0x0000009000000947 */ /* 0x000fea0003800000 */ /*0050*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */ /* 0x000fd400000001ff */ /*0060*/ IMAD.WIDE R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */ /* 0x000fc800078e0204 */ /*0070*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */ /* 0x000fe400078e0204 */ /*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */ /* 0x000ea8000c1e1900 */ /*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */ /* 0x000ea2000c1e1900 */ /*00a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */ /* 0x000fe20003800000 */ /*00b0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */ /* 0x004fca0000000000 */ /*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */ /* 0x0001e80000004800 */ /*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */ /* 0x000fec0000010000 */ /*00e0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */ /* 0x000e620000004800 */ /*00f0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */ /* 0x000fca0000000f00 */ /*0100*/ IMAD.WIDE R2, R7, R2, c[0x0][0x170] ; /* 0x00005c0007027625 */ /* 0x000fca00078e0202 */ /*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */ /* 0x002fe2000c101904 */ /*0120*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0130*/ BRA 0x130; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0140*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0150*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0160*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0170*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9dev_add_nPfS_S_i .globl _Z9dev_add_nPfS_S_i .p2align 8 .type _Z9dev_add_nPfS_S_i,@function _Z9dev_add_nPfS_S_i: s_mov_b32 s2, exec_lo v_cmpx_gt_u32_e32 5, v0 s_cbranch_execz .LBB0_2 s_load_b128 s[4:7], s[0:1], 0x0 v_lshlrev_b32_e32 v1, 2, v0 s_waitcnt lgkmcnt(0) s_clause 0x1 global_load_b32 v2, v1, s[4:5] global_load_b32 v3, v1, s[6:7] s_waitcnt vmcnt(0) v_add_f32_e32 v2, v2, v3 ds_store_b32 v1, v2 s_waitcnt lgkmcnt(0) s_barrier buffer_gl0_inv .LBB0_2: s_or_b32 exec_lo, exec_lo, s2 v_lshlrev_b32_e32 v0, 2, v0 s_load_b64 s[0:1], s[0:1], 0x10 ds_load_b32 v1, v0 s_waitcnt lgkmcnt(0) global_store_b32 v0, v1, s[0:1] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9dev_add_nPfS_S_i .amdhsa_group_segment_fixed_size 40 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 28 .amdhsa_user_sgpr_count 15 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 4 .amdhsa_next_free_sgpr 8 .amdhsa_reserve_vcc 0 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9dev_add_nPfS_S_i, .Lfunc_end0-_Z9dev_add_nPfS_S_i .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 4 .value_kind: by_value .group_segment_fixed_size: 40 .kernarg_segment_align: 8 .kernarg_segment_size: 28 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9dev_add_nPfS_S_i .private_segment_fixed_size: 0 .sgpr_count: 8 .sgpr_spill_count: 0 .symbol: _Z9dev_add_nPfS_S_i.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 4 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_001581e9_00000000-6_fail.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2061: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2061: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i .type _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i, @function _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i: .LFB2083: .cfi_startproc endbr64 subq $152, %rsp .cfi_def_cfa_offset 160 movq %rdi, 24(%rsp) movq %rsi, 16(%rsp) movq %rdx, 8(%rsp) movl %ecx, 4(%rsp) movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax leaq 24(%rsp), %rax movq %rax, 96(%rsp) leaq 16(%rsp), %rax movq %rax, 104(%rsp) leaq 8(%rsp), %rax movq %rax, 112(%rsp) leaq 4(%rsp), %rax movq %rax, 120(%rsp) movl $1, 48(%rsp) movl $1, 52(%rsp) movl $1, 56(%rsp) movl $1, 60(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) leaq 40(%rsp), %rcx leaq 32(%rsp), %rdx leaq 60(%rsp), %rsi leaq 48(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 136(%rsp), %rax subq %fs:40, %rax jne .L8 addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 40(%rsp) .cfi_def_cfa_offset 168 pushq 40(%rsp) .cfi_def_cfa_offset 176 leaq 112(%rsp), %r9 movq 76(%rsp), %rcx movl 84(%rsp), %r8d movq 64(%rsp), %rsi movl 72(%rsp), %edx leaq _Z9dev_add_nPfS_S_i(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 160 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2083: .size _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i .globl _Z9dev_add_nPfS_S_i .type _Z9dev_add_nPfS_S_i, @function _Z9dev_add_nPfS_S_i: .LFB2084: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2084: .size _Z9dev_add_nPfS_S_i, .-_Z9dev_add_nPfS_S_i .globl _Z5add_nPfS_S_i .type _Z5add_nPfS_S_i, @function _Z5add_nPfS_S_i: .LFB2057: .cfi_startproc endbr64 pushq %r14 .cfi_def_cfa_offset 16 .cfi_offset 14, -16 pushq %r13 .cfi_def_cfa_offset 24 .cfi_offset 13, -24 pushq %r12 .cfi_def_cfa_offset 32 .cfi_offset 12, -32 pushq %rbp .cfi_def_cfa_offset 40 .cfi_offset 6, -40 pushq %rbx .cfi_def_cfa_offset 48 .cfi_offset 3, -48 subq $64, %rsp .cfi_def_cfa_offset 112 movq %rdi, %r14 movq %rsi, %r13 movq %rdx, %r12 movl %ecx, %ebp movq %fs:40, %rax movq %rax, 56(%rsp) xorl %eax, %eax movslq %ecx, %rbx salq $2, %rbx leaq 8(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 16(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT leaq 24(%rsp), %rdi movq %rbx, %rsi call cudaMalloc@PLT movl $1, %ecx movq %rbx, %rdx movq %r14, %rsi movq 8(%rsp), %rdi call cudaMemcpy@PLT movl $1, %ecx movq %rbx, %rdx movq %r13, %rsi movq 16(%rsp), %rdi call cudaMemcpy@PLT movl %ebp, 44(%rsp) movl $1, 48(%rsp) movl $1, 32(%rsp) movl $1, 36(%rsp) movl $0, %r9d movl $0, %r8d movq 44(%rsp), %rdx movl $1, %ecx movq 32(%rsp), %rdi movl $1, %esi call __cudaPushCallConfiguration@PLT testl %eax, %eax je .L15 .L12: movl $2, %ecx movq %rbx, %rdx movq 24(%rsp), %rsi movq %r12, %rdi call cudaMemcpy@PLT movq 8(%rsp), %rdi call cudaFree@PLT movq 16(%rsp), %rdi call cudaFree@PLT movq 24(%rsp), %rdi call cudaFree@PLT movq 56(%rsp), %rax subq %fs:40, %rax jne .L16 addq $64, %rsp .cfi_remember_state .cfi_def_cfa_offset 48 popq %rbx .cfi_def_cfa_offset 40 popq %rbp .cfi_def_cfa_offset 32 popq %r12 .cfi_def_cfa_offset 24 popq %r13 .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state movl %ebp, %ecx movq 24(%rsp), %rdx movq 16(%rsp), %rsi movq 8(%rsp), %rdi call _Z33__device_stub__Z9dev_add_nPfS_S_iPfS_S_i jmp .L12 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2057: .size _Z5add_nPfS_S_i, .-_Z5add_nPfS_S_i .section .rodata.str1.1,"aMS",@progbits,1 .LC10: .string "c[%d] = %.3f%c" .text .globl main .type main, @function main: .LFB2058: .cfi_startproc endbr64 pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 pushq %rbx .cfi_def_cfa_offset 24 .cfi_offset 3, -24 subq $152, %rsp .cfi_def_cfa_offset 176 movq %fs:40, %rax movq %rax, 136(%rsp) xorl %eax, %eax movl $0x00000000, (%rsp) movss .LC1(%rip), %xmm8 movss %xmm8, 4(%rsp) movss .LC2(%rip), %xmm7 movss %xmm7, 8(%rsp) movss .LC3(%rip), %xmm6 movss %xmm6, 12(%rsp) movss .LC4(%rip), %xmm5 movss %xmm5, 16(%rsp) movss .LC5(%rip), %xmm4 movss %xmm4, 20(%rsp) movss .LC6(%rip), %xmm3 movss %xmm3, 24(%rsp) movss .LC7(%rip), %xmm2 movss %xmm2, 28(%rsp) movss .LC8(%rip), %xmm1 movss %xmm1, 32(%rsp) movss .LC9(%rip), %xmm0 movss %xmm0, 36(%rsp) movl $0x00000000, 48(%rsp) movss %xmm8, 52(%rsp) movss %xmm7, 56(%rsp) movss %xmm6, 60(%rsp) movss %xmm5, 64(%rsp) movss %xmm4, 68(%rsp) movss %xmm3, 72(%rsp) movss %xmm2, 76(%rsp) movss %xmm1, 80(%rsp) movss %xmm0, 84(%rsp) pxor %xmm0, %xmm0 movaps %xmm0, 96(%rsp) movaps %xmm0, 112(%rsp) movq $0, 128(%rsp) leaq 96(%rsp), %rdx leaq 48(%rsp), %rsi movq %rsp, %rdi movl $10, %ecx call _Z5add_nPfS_S_i movl $0, %ebx leaq .LC10(%rip), %rbp jmp .L19 .L22: pxor %xmm0, %xmm0 cvtss2sd 96(%rsp,%rbx,4), %xmm0 movl $32, %ecx movq %rbp, %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT addq $1, %rbx .L19: movl %ebx, %edx cmpq $9, %rbx jne .L22 pxor %xmm0, %xmm0 cvtss2sd 132(%rsp), %xmm0 movl $10, %ecx movl $9, %edx leaq .LC10(%rip), %rsi movl $2, %edi movl $1, %eax call __printf_chk@PLT movq 136(%rsp), %rax subq %fs:40, %rax jne .L23 movl $0, %eax addq $152, %rsp .cfi_remember_state .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 ret .L23: .cfi_restore_state call __stack_chk_fail@PLT .cfi_endproc .LFE2058: .size main, .-main .section .rodata.str1.1 .LC12: .string "_Z9dev_add_nPfS_S_i" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2086: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rdi movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC12(%rip), %rdx movq %rdx, %rcx leaq _Z9dev_add_nPfS_S_i(%rip), %rsi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2086: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .section .rodata.cst4,"aM",@progbits,4 .align 4 .LC1: .long 1065353216 .align 4 .LC2: .long 1073741824 .align 4 .LC3: .long 1077936128 .align 4 .LC4: .long 1082130432 .align 4 .LC5: .long 1084227584 .align 4 .LC6: .long 1086324736 .align 4 .LC7: .long 1088421888 .align 4 .LC8: .long 1090519040 .align 4 .LC9: .long 1091567616 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "fail.hip" .globl _Z24__device_stub__dev_add_nPfS_S_i # -- Begin function _Z24__device_stub__dev_add_nPfS_S_i .p2align 4, 0x90 .type _Z24__device_stub__dev_add_nPfS_S_i,@function _Z24__device_stub__dev_add_nPfS_S_i: # @_Z24__device_stub__dev_add_nPfS_S_i .cfi_startproc # %bb.0: subq $120, %rsp .cfi_def_cfa_offset 128 movq %rdi, 72(%rsp) movq %rsi, 64(%rsp) movq %rdx, 56(%rsp) movl %ecx, 4(%rsp) leaq 72(%rsp), %rax movq %rax, 80(%rsp) leaq 64(%rsp), %rax movq %rax, 88(%rsp) leaq 56(%rsp), %rax movq %rax, 96(%rsp) leaq 4(%rsp), %rax movq %rax, 104(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 80(%rsp), %r9 movl $_Z9dev_add_nPfS_S_i, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $136, %rsp .cfi_adjust_cfa_offset -136 retq .Lfunc_end0: .size _Z24__device_stub__dev_add_nPfS_S_i, .Lfunc_end0-_Z24__device_stub__dev_add_nPfS_S_i .cfi_endproc # -- End function .globl _Z5add_nPfS_S_i # -- Begin function _Z5add_nPfS_S_i .p2align 4, 0x90 .type _Z5add_nPfS_S_i,@function _Z5add_nPfS_S_i: # @_Z5add_nPfS_S_i .cfi_startproc # %bb.0: pushq %rbp .cfi_def_cfa_offset 16 pushq %r15 .cfi_def_cfa_offset 24 pushq %r14 .cfi_def_cfa_offset 32 pushq %r13 .cfi_def_cfa_offset 40 pushq %r12 .cfi_def_cfa_offset 48 pushq %rbx .cfi_def_cfa_offset 56 subq $152, %rsp .cfi_def_cfa_offset 208 .cfi_offset %rbx, -56 .cfi_offset %r12, -48 .cfi_offset %r13, -40 .cfi_offset %r14, -32 .cfi_offset %r15, -24 .cfi_offset %rbp, -16 movl %ecx, %ebp movq %rdx, %rbx movq %rsi, %r15 movq %rdi, %r12 movslq %ecx, %r13 leaq (,%r13,4), %r14 leaq 24(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 16(%rsp), %rdi movq %r14, %rsi callq hipMalloc leaq 8(%rsp), %rdi movq %r14, %rsi callq hipMalloc movq 24(%rsp), %rdi movq %r12, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movq 16(%rsp), %rdi movq %r15, %rsi movq %r14, %rdx movl $1, %ecx callq hipMemcpy movl %r13d, %edx movabsq $4294967296, %rdi # imm = 0x100000000 orq %rdi, %rdx orq $1, %rdi movl $1, %esi movl $1, %ecx xorl %r8d, %r8d xorl %r9d, %r9d callq __hipPushCallConfiguration testl %eax, %eax jne .LBB1_2 # %bb.1: movq 24(%rsp), %rax movq 16(%rsp), %rcx movq 8(%rsp), %rdx movq %rax, 104(%rsp) movq %rcx, 96(%rsp) movq %rdx, 88(%rsp) movl %ebp, 36(%rsp) leaq 104(%rsp), %rax movq %rax, 112(%rsp) leaq 96(%rsp), %rax movq %rax, 120(%rsp) leaq 88(%rsp), %rax movq %rax, 128(%rsp) leaq 36(%rsp), %rax movq %rax, 136(%rsp) leaq 72(%rsp), %rdi leaq 56(%rsp), %rsi leaq 48(%rsp), %rdx leaq 40(%rsp), %rcx callq __hipPopCallConfiguration movq 72(%rsp), %rsi movl 80(%rsp), %edx movq 56(%rsp), %rcx movl 64(%rsp), %r8d leaq 112(%rsp), %r9 movl $_Z9dev_add_nPfS_S_i, %edi pushq 40(%rsp) .cfi_adjust_cfa_offset 8 pushq 56(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $16, %rsp .cfi_adjust_cfa_offset -16 .LBB1_2: movq 8(%rsp), %rsi movq %rbx, %rdi movq %r14, %rdx movl $2, %ecx callq hipMemcpy movq 24(%rsp), %rdi callq hipFree movq 16(%rsp), %rdi callq hipFree movq 8(%rsp), %rdi callq hipFree addq $152, %rsp .cfi_def_cfa_offset 56 popq %rbx .cfi_def_cfa_offset 48 popq %r12 .cfi_def_cfa_offset 40 popq %r13 .cfi_def_cfa_offset 32 popq %r14 .cfi_def_cfa_offset 24 popq %r15 .cfi_def_cfa_offset 16 popq %rbp .cfi_def_cfa_offset 8 retq .Lfunc_end1: .size _Z5add_nPfS_S_i, .Lfunc_end1-_Z5add_nPfS_S_i .cfi_endproc # -- End function .section .rodata.cst16,"aM",@progbits,16 .p2align 4, 0x0 # -- Begin function main .LCPI2_0: .long 0x00000000 # float 0 .long 0x3f800000 # float 1 .long 0x40000000 # float 2 .long 0x40400000 # float 3 .LCPI2_1: .long 0x40800000 # float 4 .long 0x40a00000 # float 5 .long 0x40c00000 # float 6 .long 0x40e00000 # float 7 .text .globl main .p2align 4, 0x90 .type main,@function main: # @main .cfi_startproc # %bb.0: pushq %r14 .cfi_def_cfa_offset 16 pushq %rbx .cfi_def_cfa_offset 24 subq $136, %rsp .cfi_def_cfa_offset 160 .cfi_offset %rbx, -24 .cfi_offset %r14, -16 movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0] movaps %xmm0, 96(%rsp) movaps .LCPI2_1(%rip), %xmm1 # xmm1 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0] movaps %xmm1, 112(%rsp) movabsq $4688247213183205376, %rax # imm = 0x4110000041000000 movq %rax, 128(%rsp) movaps %xmm0, 48(%rsp) movaps %xmm1, 64(%rsp) movq %rax, 80(%rsp) xorps %xmm0, %xmm0 movaps %xmm0, 16(%rsp) movaps %xmm0, (%rsp) movq $0, 32(%rsp) leaq 96(%rsp), %rdi leaq 48(%rsp), %rsi movq %rsp, %rdx movl $10, %ebx movl $10, %ecx callq _Z5add_nPfS_S_i xorl %esi, %esi .p2align 4, 0x90 .LBB2_1: # =>This Inner Loop Header: Depth=1 movss (%rsp,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero cvtss2sd %xmm0, %xmm0 leaq 1(%rsi), %r14 cmpq $9, %rsi movl $32, %edx cmovel %ebx, %edx movl $.L.str, %edi # kill: def $esi killed $esi killed $rsi movb $1, %al callq printf movq %r14, %rsi cmpq $10, %r14 jne .LBB2_1 # %bb.2: xorl %eax, %eax addq $136, %rsp .cfi_def_cfa_offset 24 popq %rbx .cfi_def_cfa_offset 16 popq %r14 .cfi_def_cfa_offset 8 retq .Lfunc_end2: .size main, .Lfunc_end2-main .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: subq $40, %rsp .cfi_def_cfa_offset 48 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB3_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB3_2: movq __hip_gpubin_handle(%rip), %rdi xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9dev_add_nPfS_S_i, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $40, %rsp .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end3: .size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB4_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB4_2: retq .Lfunc_end4: .size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor .cfi_endproc # -- End function .type _Z9dev_add_nPfS_S_i,@object # @_Z9dev_add_nPfS_S_i .section .rodata,"a",@progbits .globl _Z9dev_add_nPfS_S_i .p2align 3, 0x0 _Z9dev_add_nPfS_S_i: .quad _Z24__device_stub__dev_add_nPfS_S_i .size _Z9dev_add_nPfS_S_i, 8 .type .L.str,@object # @.str .section .rodata.str1.1,"aMS",@progbits,1 .L.str: .asciz "c[%d] = %.3f%c" .size .L.str, 15 .type .L__unnamed_1,@object # @0 .L__unnamed_1: .asciz "_Z9dev_add_nPfS_S_i" .size .L__unnamed_1, 20 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__dev_add_nPfS_S_i .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9dev_add_nPfS_S_i .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
#include <curand.h> #include <curand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
code for sm_80 Function : _Z6binaryPhS_S_mi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e680000002200 */ /*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */ /* 0x001fe400078e0200 */ /*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */ /* 0x002fc800078e0202 */ /*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */ /* 0x000fca00078e0200 */ /*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */ /* 0x000fe40000011400 */ /*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */ /* 0x000fc80007f1e0ff */ /*00b0*/ IADD3.X R3, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007037a10 */ /* 0x000fca00007fe4ff */ /*00c0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */ /* 0x000ea2000c1e1100 */ /*00d0*/ IADD3 R4, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R6, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */ /* 0x000fe40007f5e0ff */ /*00f0*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */ /* 0x004fe40003f04270 */ /*0100*/ IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0007057a10 */ /* 0x040fe40000ffe4ff */ /*0110*/ SEL R9, RZ, 0xffff, !P0 ; /* 0x0000ffffff097807 */ /* 0x000fe40004000000 */ /*0120*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0007077a10 */ /* 0x000fc600017fe4ff */ /*0130*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x000fe8000c101104 */ /*0140*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */ /* 0x000fe8000c101104 */ /*0150*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101104 */ /*0160*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0170*/ BRA 0x170; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z9grayscalePhS_S_mPj .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e680000002200 */ /*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */ /* 0x001fe400078e0200 */ /*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */ /* 0x002fc800078e0202 */ /*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */ /* 0x000fca00078e0200 */ /*0090*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fe40000011400 */ /*00a0*/ IADD3 R6, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */ /* 0x040fe40007f3e0ff */ /*00b0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */ /* 0x040fe40007f1e0ff */ /*00c0*/ IADD3.X R7, R5.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005077a10 */ /* 0x040fe40000ffe4ff */ /*00d0*/ IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */ /* 0x040fe400007fe4ff */ /*00e0*/ IADD3 R4, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */ /* 0x000fe20007f3e0ff */ /*00f0*/ LDG.E.U8 R14, [R6.64] ; /* 0x00000004060e7981 */ /* 0x000ea6000c1e1100 */ /*0100*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0005057a10 */ /* 0x000fe20000ffe4ff */ /*0110*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ee8000c1e1100 */ /*0120*/ LDG.E.U8 R15, [R4.64] ; /* 0x00000004040f7981 */ /* 0x000f22000c1e1100 */ /*0130*/ I2F.F64.U16 R10, R14 ; /* 0x0000000e000a7312 */ /* 0x004e300000101800 */ /*0140*/ I2F.F64.U16 R8, R0 ; /* 0x0000000000087312 */ /* 0x008e700000101800 */ /*0150*/ I2F.F64.U16 R12, R15 ; /* 0x0000000f000c7312 */ /* 0x010ea20000101800 */ /*0160*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */ /* 0x001e4c0000000000 */ /*0170*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */ /* 0x002e8c000000000a */ /*0180*/ DFMA R8, R12, c[0x2][0x10], R8 ; /* 0x008004000c087a2b */ /* 0x004e140000000008 */ /*0190*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */ /* 0x001e24000030d000 */ /*01a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x0011e8000c101104 */ /*01b0*/ LDG.E.U8 R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000ea8000c1e1100 */ /*01c0*/ LDG.E.U8 R18, [R4.64] ; /* 0x0000000404127981 */ /* 0x000ee2000c1e1100 */ /*01d0*/ LOP3.LUT R16, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09107812 */ /* 0x000fc800078ec0ff */ /*01e0*/ I2F.F64.U16 R10, R16 ; /* 0x00000010000a7312 */ /* 0x000ff00000101800 */ /*01f0*/ I2F.F64.U16 R12, R17 ; /* 0x00000011000c7312 */ /* 0x004e700000101800 */ /*0200*/ I2F.F64.U16 R14, R18 ; /* 0x00000012000e7312 */ /* 0x008ea20000101800 */ /*0210*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */ /* 0x002e4c0000000000 */ /*0220*/ DFMA R10, R10, c[0x2][0x8], R12 ; /* 0x008002000a0a7a2b */ /* 0x002e8c000000000c */ /*0230*/ DFMA R10, R14, c[0x2][0x10], R10 ; /* 0x008004000e0a7a2b */ /* 0x004e54000000000a */ /*0240*/ F2I.U32.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */ /* 0x002e64000030d000 */ /*0250*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0023e8000c101104 */ /*0260*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000e28000c1e1100 */ /*0270*/ LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e7981 */ /* 0x000ea2000c1e1100 */ /*0280*/ LOP3.LUT R12, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0c7812 */ /* 0x000fcc00078ec0ff */ /*0290*/ I2F.F64.U16 R12, R12 ; /* 0x0000000c000c7312 */ /* 0x000ff00000101800 */ /*02a0*/ I2F.F64.U16 R8, R0 ; /* 0x0000000000087312 */ /* 0x001e300000101800 */ /*02b0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */ /* 0x004ea20000101800 */ /*02c0*/ DMUL R8, R8, c[0x2][0x8] ; /* 0x0080020008087a28 */ /* 0x001e0c0000000000 */ /*02d0*/ DFMA R8, R12, c[0x2][0x0], R8 ; /* 0x008000000c087a2b */ /* 0x001e8c0000000008 */ /*02e0*/ DFMA R8, R14, c[0x2][0x10], R8 ; /* 0x008004000e087a2b */ /* 0x004e140000000008 */ /*02f0*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */ /* 0x001e24000030d000 */ /*0300*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */ /* 0x001fe8000c101104 */ /*0310*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */ /* 0x002ea2000c1e1100 */ /*0320*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */ /* 0x000fe400078e00ff */ /*0330*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */ /* 0x000fe400078e00ff */ /*0340*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */ /* 0x004fca00078e0007 */ /*0350*/ RED.E.ADD.STRONG.GPU [R6.64], R11 ; /* 0x0000000b0600798e */ /* 0x000fe2000c10e184 */ /*0360*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0370*/ BRA 0x370; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0380*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0390*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
#include <curand.h> #include <curand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
.file "tmpxft_000a69b4_00000000-6_threshold.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2243: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2243: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj .type _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj, @function _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj: .LFB2265: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z9grayscalePhS_S_mPj(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2265: .size _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj, .-_Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj .globl _Z9grayscalePhS_S_mPj .type _Z9grayscalePhS_S_mPj, @function _Z9grayscalePhS_S_mPj: .LFB2266: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2266: .size _Z9grayscalePhS_S_mPj, .-_Z9grayscalePhS_S_mPj .globl _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi .type _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi, @function _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi: .LFB2267: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 12(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 152(%rsp), %rax subq %fs:40, %rax jne .L16 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z6binaryPhS_S_mi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2267: .size _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi, .-_Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi .globl _Z6binaryPhS_S_mi .type _Z6binaryPhS_S_mi, @function _Z6binaryPhS_S_mi: .LFB2268: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2268: .size _Z6binaryPhS_S_mi, .-_Z6binaryPhS_S_mi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6binaryPhS_S_mi" .LC1: .string "_Z9grayscalePhS_S_mPj" .LC2: .string "precalc_xorwow_matrix" .LC3: .string "precalc_xorwow_offset_matrix" .LC4: .string "mrg32k3aM1" .LC5: .string "mrg32k3aM2" .LC6: .string "mrg32k3aM1SubSeq" .LC7: .string "mrg32k3aM2SubSeq" .LC8: .string "mrg32k3aM1Seq" .LC9: .string "mrg32k3aM2Seq" .LC10: .string "__cr_lgamma_table" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2270: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6binaryPhS_S_mi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z9grayscalePhS_S_mPj(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL21precalc_xorwow_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM1(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM2(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM1Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM2Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $72, %r9d movl $0, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2270: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
#include <curand.h> #include <curand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
#include <hip/hip_runtime.h> #include <hiprand/hiprand.h> #include <hiprand/hiprand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
#include <hip/hip_runtime.h> #include <hiprand/hiprand.h> #include <hiprand/hiprand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9grayscalePhS_S_mPj .globl _Z9grayscalePhS_S_mPj .p2align 8 .type _Z9grayscalePhS_S_mPj,@function _Z9grayscalePhS_S_mPj: s_clause 0x1 s_load_b32 s8, s[0:1], 0x34 s_load_b32 s9, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s2, s8, 16 s_and_b32 s8, s8, 0xffff v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2] s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x20 s_mul_i32 s14, s14, s8 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v1, v2, s9 v_add3_u32 v4, s14, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v4 s_mov_b32 s6, 0x9fbe76c9 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo global_load_u8 v6, v[0:1], off v_add_co_u32 v4, vcc_lo, s0, v4 global_load_u8 v8, v[2:3], off v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_mov_b32 s1, 0x3fe2c8b4 s_mov_b32 s0, 0x39581062 s_mov_b32 s5, 0x3fd3212d global_load_u8 v10, v[4:5], off s_mov_b32 s4, 0x77318fc5 s_mov_b32 s7, 0x3fbd2f1a s_waitcnt vmcnt(2) v_cvt_f64_u32_e32 v[6:7], v6 s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[8:9], v8 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[10:11], v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], s[0:1] v_fma_f64 v[6:7], v[8:9], s[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7] v_cvt_i32_f64_e32 v6, v[6:7] global_store_b8 v[2:3], v6, off global_load_u8 v8, v[0:1], off global_load_u8 v10, v[4:5], off v_cvt_f64_u32_e32 v[6:7], v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_mul_f64 v[6:7], v[6:7], s[4:5] s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[8:9], v8 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[10:11], v10 v_fma_f64 v[6:7], v[8:9], s[0:1], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7] v_cvt_i32_f64_e32 v6, v[6:7] global_store_b8 v[0:1], v6, off global_load_u8 v7, v[2:3], off global_load_u8 v8, v[4:5], off v_cvt_f64_u32_e32 v[0:1], v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_mul_f64 v[0:1], v[0:1], s[0:1] s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[6:7], v7 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[8:9], v8 v_fma_f64 v[0:1], v[6:7], s[4:5], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], v[8:9], s[6:7], v[0:1] v_cvt_i32_f64_e32 v0, v[0:1] v_mov_b32_e32 v1, 1 global_store_b8 v[4:5], v0, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v0, 2, v0 global_atomic_add_u32 v0, v1, s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9grayscalePhS_S_mPj .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9grayscalePhS_S_mPj, .Lfunc_end0-_Z9grayscalePhS_S_mPj .section .AMDGPU.csdata,"",@progbits .text .protected _Z6binaryPhS_S_mi .globl _Z6binaryPhS_S_mi .p2align 8 .type _Z6binaryPhS_S_mi,@function _Z6binaryPhS_S_mi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b32 s3, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s2, 16 s_and_b32 s2, s2, 0xffff v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2] s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x20 s_mul_i32 s14, s14, s2 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v1, v2, s3 v_add3_u32 v4, s14, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[0:1], off s_waitcnt vmcnt(0) v_cmp_lt_i32_e32 vcc_lo, s8, v6 v_cndmask_b32_e64 v6, 0, -1, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo global_store_b8 v[0:1], v6, off global_store_b8 v[2:3], v6, off global_store_b8 v[4:5], v6, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6binaryPhS_S_mi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6binaryPhS_S_mi, .Lfunc_end1-_Z6binaryPhS_S_mi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9grayscalePhS_S_mPj .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9grayscalePhS_S_mPj.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6binaryPhS_S_mi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6binaryPhS_S_mi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
#include <hip/hip_runtime.h> #include <hiprand/hiprand.h> #include <hiprand/hiprand_kernel.h> #define DIM 1600 #define PI 3.14159265 __global__ void grayscale(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, unsigned int *hist) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; R_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; G_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; B_input[offset] = 0.2989 * R_input[offset] + 0.587 * G_input[offset] + 0.1140 * B_input[offset]; atomicAdd( &(hist[R_input[offset]]), 1); } __global__ void binary(unsigned char *R_input, unsigned char *G_input, unsigned char *B_input, size_t i_size, int um) { int x = threadIdx.x + (blockIdx.x * blockDim.x); int y = threadIdx.y + (blockIdx.y * blockDim.y); int offset = x + y * i_size; unsigned char c; if (R_input[offset] > um) c = 255; else c = 0; R_input[offset] = c; G_input[offset] = c; B_input[offset] = c; }
.text .file "threshold.hip" .globl _Z24__device_stub__grayscalePhS_S_mPj # -- Begin function _Z24__device_stub__grayscalePhS_S_mPj .p2align 4, 0x90 .type _Z24__device_stub__grayscalePhS_S_mPj,@function _Z24__device_stub__grayscalePhS_S_mPj: # @_Z24__device_stub__grayscalePhS_S_mPj .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9grayscalePhS_S_mPj, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z24__device_stub__grayscalePhS_S_mPj, .Lfunc_end0-_Z24__device_stub__grayscalePhS_S_mPj .cfi_endproc # -- End function .globl _Z21__device_stub__binaryPhS_S_mi # -- Begin function _Z21__device_stub__binaryPhS_S_mi .p2align 4, 0x90 .type _Z21__device_stub__binaryPhS_S_mi,@function _Z21__device_stub__binaryPhS_S_mi: # @_Z21__device_stub__binaryPhS_S_mi .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6binaryPhS_S_mi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size _Z21__device_stub__binaryPhS_S_mi, .Lfunc_end1-_Z21__device_stub__binaryPhS_S_mi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9grayscalePhS_S_mPj, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6binaryPhS_S_mi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9grayscalePhS_S_mPj,@object # @_Z9grayscalePhS_S_mPj .section .rodata,"a",@progbits .globl _Z9grayscalePhS_S_mPj .p2align 3, 0x0 _Z9grayscalePhS_S_mPj: .quad _Z24__device_stub__grayscalePhS_S_mPj .size _Z9grayscalePhS_S_mPj, 8 .type _Z6binaryPhS_S_mi,@object # @_Z6binaryPhS_S_mi .globl _Z6binaryPhS_S_mi .p2align 3, 0x0 _Z6binaryPhS_S_mi: .quad _Z21__device_stub__binaryPhS_S_mi .size _Z6binaryPhS_S_mi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9grayscalePhS_S_mPj" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6binaryPhS_S_mi" .size .L__unnamed_2, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__grayscalePhS_S_mPj .addrsig_sym _Z21__device_stub__binaryPhS_S_mi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9grayscalePhS_S_mPj .addrsig_sym _Z6binaryPhS_S_mi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
code for sm_80 Function : _Z6binaryPhS_S_mi .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e680000002200 */ /*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */ /* 0x001fe400078e0200 */ /*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */ /* 0x002fc800078e0202 */ /*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */ /* 0x000fca00078e0200 */ /*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */ /* 0x000fe40000011400 */ /*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */ /* 0x000fc80007f1e0ff */ /*00b0*/ IADD3.X R3, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007037a10 */ /* 0x000fca00007fe4ff */ /*00c0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */ /* 0x000ea2000c1e1100 */ /*00d0*/ IADD3 R4, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */ /* 0x040fe40007f3e0ff */ /*00e0*/ IADD3 R6, P2, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */ /* 0x000fe40007f5e0ff */ /*00f0*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x180], PT ; /* 0x0000600005007a0c */ /* 0x004fe40003f04270 */ /*0100*/ IADD3.X R5, R7.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0007057a10 */ /* 0x040fe40000ffe4ff */ /*0110*/ SEL R9, RZ, 0xffff, !P0 ; /* 0x0000ffffff097807 */ /* 0x000fe40004000000 */ /*0120*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0007077a10 */ /* 0x000fc600017fe4ff */ /*0130*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x000fe8000c101104 */ /*0140*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */ /* 0x000fe8000c101104 */ /*0150*/ STG.E.U8 [R6.64], R9 ; /* 0x0000000906007986 */ /* 0x000fe2000c101104 */ /*0160*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0170*/ BRA 0x170; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0180*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0190*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*01f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ .......... Function : _Z9grayscalePhS_S_mPj .headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)" /*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */ /* 0x000fe400078e00ff */ /*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */ /* 0x000e220000002100 */ /*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */ /* 0x000fc60000000a00 */ /*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */ /* 0x000e280000002500 */ /*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */ /* 0x000e680000002200 */ /*0050*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */ /* 0x000e620000002600 */ /*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */ /* 0x001fe400078e0200 */ /*0070*/ IMAD R3, R5, c[0x0][0x4], R2 ; /* 0x0000010005037a24 */ /* 0x002fc800078e0202 */ /*0080*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */ /* 0x000fca00078e0200 */ /*0090*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */ /* 0x000fe40000011400 */ /*00a0*/ IADD3 R6, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */ /* 0x040fe40007f3e0ff */ /*00b0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */ /* 0x040fe40007f1e0ff */ /*00c0*/ IADD3.X R7, R5.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0005077a10 */ /* 0x040fe40000ffe4ff */ /*00d0*/ IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */ /* 0x040fe400007fe4ff */ /*00e0*/ IADD3 R4, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */ /* 0x000fe20007f3e0ff */ /*00f0*/ LDG.E.U8 R14, [R6.64] ; /* 0x00000004060e7981 */ /* 0x000ea6000c1e1100 */ /*0100*/ IADD3.X R5, R5, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0005057a10 */ /* 0x000fe20000ffe4ff */ /*0110*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000ee8000c1e1100 */ /*0120*/ LDG.E.U8 R15, [R4.64] ; /* 0x00000004040f7981 */ /* 0x000f22000c1e1100 */ /*0130*/ I2F.F64.U16 R10, R14 ; /* 0x0000000e000a7312 */ /* 0x004e300000101800 */ /*0140*/ I2F.F64.U16 R8, R0 ; /* 0x0000000000087312 */ /* 0x008e700000101800 */ /*0150*/ I2F.F64.U16 R12, R15 ; /* 0x0000000f000c7312 */ /* 0x010ea20000101800 */ /*0160*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */ /* 0x001e4c0000000000 */ /*0170*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */ /* 0x002e8c000000000a */ /*0180*/ DFMA R8, R12, c[0x2][0x10], R8 ; /* 0x008004000c087a2b */ /* 0x004e140000000008 */ /*0190*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */ /* 0x001e24000030d000 */ /*01a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */ /* 0x0011e8000c101104 */ /*01b0*/ LDG.E.U8 R17, [R6.64] ; /* 0x0000000406117981 */ /* 0x000ea8000c1e1100 */ /*01c0*/ LDG.E.U8 R18, [R4.64] ; /* 0x0000000404127981 */ /* 0x000ee2000c1e1100 */ /*01d0*/ LOP3.LUT R16, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09107812 */ /* 0x000fc800078ec0ff */ /*01e0*/ I2F.F64.U16 R10, R16 ; /* 0x00000010000a7312 */ /* 0x000ff00000101800 */ /*01f0*/ I2F.F64.U16 R12, R17 ; /* 0x00000011000c7312 */ /* 0x004e700000101800 */ /*0200*/ I2F.F64.U16 R14, R18 ; /* 0x00000012000e7312 */ /* 0x008ea20000101800 */ /*0210*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */ /* 0x002e4c0000000000 */ /*0220*/ DFMA R10, R10, c[0x2][0x8], R12 ; /* 0x008002000a0a7a2b */ /* 0x002e8c000000000c */ /*0230*/ DFMA R10, R14, c[0x2][0x10], R10 ; /* 0x008004000e0a7a2b */ /* 0x004e54000000000a */ /*0240*/ F2I.U32.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */ /* 0x002e64000030d000 */ /*0250*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */ /* 0x0023e8000c101104 */ /*0260*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */ /* 0x000e28000c1e1100 */ /*0270*/ LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e7981 */ /* 0x000ea2000c1e1100 */ /*0280*/ LOP3.LUT R12, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0c7812 */ /* 0x000fcc00078ec0ff */ /*0290*/ I2F.F64.U16 R12, R12 ; /* 0x0000000c000c7312 */ /* 0x000ff00000101800 */ /*02a0*/ I2F.F64.U16 R8, R0 ; /* 0x0000000000087312 */ /* 0x001e300000101800 */ /*02b0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */ /* 0x004ea20000101800 */ /*02c0*/ DMUL R8, R8, c[0x2][0x8] ; /* 0x0080020008087a28 */ /* 0x001e0c0000000000 */ /*02d0*/ DFMA R8, R12, c[0x2][0x0], R8 ; /* 0x008000000c087a2b */ /* 0x001e8c0000000008 */ /*02e0*/ DFMA R8, R14, c[0x2][0x10], R8 ; /* 0x008004000e087a2b */ /* 0x004e140000000008 */ /*02f0*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */ /* 0x001e24000030d000 */ /*0300*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */ /* 0x001fe8000c101104 */ /*0310*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */ /* 0x002ea2000c1e1100 */ /*0320*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */ /* 0x000fe400078e00ff */ /*0330*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */ /* 0x000fe400078e00ff */ /*0340*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */ /* 0x004fca00078e0007 */ /*0350*/ RED.E.ADD.STRONG.GPU [R6.64], R11 ; /* 0x0000000b0600798e */ /* 0x000fe2000c10e184 */ /*0360*/ EXIT ; /* 0x000000000000794d */ /* 0x000fea0003800000 */ /*0370*/ BRA 0x370; /* 0xfffffff000007947 */ /* 0x000fc0000383ffff */ /*0380*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*0390*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03a0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03b0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03c0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03d0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03e0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ /*03f0*/ NOP; /* 0x0000000000007918 */ /* 0x000fc00000000000 */ ..........
.text .amdgcn_target "amdgcn-amd-amdhsa--gfx1100" .protected _Z9grayscalePhS_S_mPj .globl _Z9grayscalePhS_S_mPj .p2align 8 .type _Z9grayscalePhS_S_mPj,@function _Z9grayscalePhS_S_mPj: s_clause 0x1 s_load_b32 s8, s[0:1], 0x34 s_load_b32 s9, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s2, s8, 16 s_and_b32 s8, s8, 0xffff v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2] s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b64 s[2:3], s[0:1], 0x20 s_mul_i32 s14, s14, s8 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v1, v2, s9 v_add3_u32 v4, s14, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s6, v4 s_mov_b32 s6, 0x9fbe76c9 v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo global_load_u8 v6, v[0:1], off v_add_co_u32 v4, vcc_lo, s0, v4 global_load_u8 v8, v[2:3], off v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo s_mov_b32 s1, 0x3fe2c8b4 s_mov_b32 s0, 0x39581062 s_mov_b32 s5, 0x3fd3212d global_load_u8 v10, v[4:5], off s_mov_b32 s4, 0x77318fc5 s_mov_b32 s7, 0x3fbd2f1a s_waitcnt vmcnt(2) v_cvt_f64_u32_e32 v[6:7], v6 s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[8:9], v8 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[10:11], v10 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64 v[6:7], v[6:7], s[0:1] v_fma_f64 v[6:7], v[8:9], s[4:5], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7] v_cvt_i32_f64_e32 v6, v[6:7] global_store_b8 v[2:3], v6, off global_load_u8 v8, v[0:1], off global_load_u8 v10, v[4:5], off v_cvt_f64_u32_e32 v[6:7], v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_mul_f64 v[6:7], v[6:7], s[4:5] s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[8:9], v8 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[10:11], v10 v_fma_f64 v[6:7], v[8:9], s[0:1], v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7] v_cvt_i32_f64_e32 v6, v[6:7] global_store_b8 v[0:1], v6, off global_load_u8 v7, v[2:3], off global_load_u8 v8, v[4:5], off v_cvt_f64_u32_e32 v[0:1], v6 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) v_mul_f64 v[0:1], v[0:1], s[0:1] s_waitcnt vmcnt(1) v_cvt_f64_u32_e32 v[6:7], v7 s_waitcnt vmcnt(0) v_cvt_f64_u32_e32 v[8:9], v8 v_fma_f64 v[0:1], v[6:7], s[4:5], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], v[8:9], s[6:7], v[0:1] v_cvt_i32_f64_e32 v0, v[0:1] v_mov_b32_e32 v1, 1 global_store_b8 v[4:5], v0, off global_load_u8 v0, v[2:3], off s_waitcnt vmcnt(0) v_lshlrev_b32_e32 v0, 2, v0 global_atomic_add_u32 v0, v1, s[2:3] s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z9grayscalePhS_S_mPj .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 12 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end0: .size _Z9grayscalePhS_S_mPj, .Lfunc_end0-_Z9grayscalePhS_S_mPj .section .AMDGPU.csdata,"",@progbits .text .protected _Z6binaryPhS_S_mi .globl _Z6binaryPhS_S_mi .p2align 8 .type _Z6binaryPhS_S_mi,@function _Z6binaryPhS_S_mi: s_clause 0x1 s_load_b32 s2, s[0:1], 0x34 s_load_b32 s3, s[0:1], 0x18 v_bfe_u32 v1, v0, 10, 10 v_and_b32_e32 v0, 0x3ff, v0 s_waitcnt lgkmcnt(0) s_lshr_b32 s4, s2, 16 s_and_b32 s2, s2, 0xffff v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2] s_clause 0x1 s_load_b128 s[4:7], s[0:1], 0x0 s_load_b32 s8, s[0:1], 0x20 s_mul_i32 s14, s14, s2 s_load_b64 s[0:1], s[0:1], 0x10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v1, v2, s3 v_add3_u32 v4, s14, v0, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v5, 31, v4 s_waitcnt lgkmcnt(0) v_add_co_u32 v0, vcc_lo, s4, v4 v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo v_add_co_u32 v2, vcc_lo, s6, v4 v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo global_load_u8 v6, v[0:1], off s_waitcnt vmcnt(0) v_cmp_lt_i32_e32 vcc_lo, s8, v6 v_cndmask_b32_e64 v6, 0, -1, vcc_lo v_add_co_u32 v4, vcc_lo, s0, v4 v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo global_store_b8 v[0:1], v6, off global_store_b8 v[2:3], v6, off global_store_b8 v[4:5], v6, off s_nop 0 s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _Z6binaryPhS_S_mi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 296 .amdhsa_user_sgpr_count 14 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 1 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 1 .amdhsa_next_free_vgpr 7 .amdhsa_next_free_sgpr 16 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_dx10_clamp 1 .amdhsa_ieee_mode 1 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 0 .amdhsa_shared_vgpr_count 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .text .Lfunc_end1: .size _Z6binaryPhS_S_mi, .Lfunc_end1-_Z6binaryPhS_S_mi .section .AMDGPU.csdata,"",@progbits .text .p2alignl 7, 3214868480 .fill 96, 4, 3214868480 .type __hip_cuid_,@object .section .bss,"aw",@nobits .globl __hip_cuid_ __hip_cuid_: .byte 0 .size __hip_cuid_, 1 .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_ .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z9grayscalePhS_S_mPj .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z9grayscalePhS_S_mPj.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 12 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .offset: 24 .size: 8 .value_kind: by_value - .offset: 32 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: hidden_block_count_x - .offset: 44 .size: 4 .value_kind: hidden_block_count_y - .offset: 48 .size: 4 .value_kind: hidden_block_count_z - .offset: 52 .size: 2 .value_kind: hidden_group_size_x - .offset: 54 .size: 2 .value_kind: hidden_group_size_y - .offset: 56 .size: 2 .value_kind: hidden_group_size_z - .offset: 58 .size: 2 .value_kind: hidden_remainder_x - .offset: 60 .size: 2 .value_kind: hidden_remainder_y - .offset: 62 .size: 2 .value_kind: hidden_remainder_z - .offset: 80 .size: 8 .value_kind: hidden_global_offset_x - .offset: 88 .size: 8 .value_kind: hidden_global_offset_y - .offset: 96 .size: 8 .value_kind: hidden_global_offset_z - .offset: 104 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 296 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _Z6binaryPhS_S_mi .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _Z6binaryPhS_S_mi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 7 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1100 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
.file "tmpxft_000a69b4_00000000-6_threshold.cudafe1.cpp" .text #APP #NO_APP .type _ZL26__cudaUnregisterBinaryUtilv, @function _ZL26__cudaUnregisterBinaryUtilv: .LFB2243: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaUnregisterFatBinary@PLT addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2243: .size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv .globl _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj .type _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj, @function _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj: .LFB2265: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movq %r8, 8(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 8(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L7 .L3: movq 152(%rsp), %rax subq %fs:40, %rax jne .L8 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L7: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z9grayscalePhS_S_mPj(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L3 .L8: call __stack_chk_fail@PLT .cfi_endproc .LFE2265: .size _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj, .-_Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj .globl _Z9grayscalePhS_S_mPj .type _Z9grayscalePhS_S_mPj, @function _Z9grayscalePhS_S_mPj: .LFB2266: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z35__device_stub__Z9grayscalePhS_S_mPjPhS_S_mPj addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2266: .size _Z9grayscalePhS_S_mPj, .-_Z9grayscalePhS_S_mPj .globl _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi .type _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi, @function _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi: .LFB2267: .cfi_startproc endbr64 subq $168, %rsp .cfi_def_cfa_offset 176 movq %rdi, 40(%rsp) movq %rsi, 32(%rsp) movq %rdx, 24(%rsp) movq %rcx, 16(%rsp) movl %r8d, 12(%rsp) movq %fs:40, %rax movq %rax, 152(%rsp) xorl %eax, %eax leaq 40(%rsp), %rax movq %rax, 112(%rsp) leaq 32(%rsp), %rax movq %rax, 120(%rsp) leaq 24(%rsp), %rax movq %rax, 128(%rsp) leaq 16(%rsp), %rax movq %rax, 136(%rsp) leaq 12(%rsp), %rax movq %rax, 144(%rsp) movl $1, 64(%rsp) movl $1, 68(%rsp) movl $1, 72(%rsp) movl $1, 76(%rsp) movl $1, 80(%rsp) movl $1, 84(%rsp) leaq 56(%rsp), %rcx leaq 48(%rsp), %rdx leaq 76(%rsp), %rsi leaq 64(%rsp), %rdi call __cudaPopCallConfiguration@PLT testl %eax, %eax je .L15 .L11: movq 152(%rsp), %rax subq %fs:40, %rax jne .L16 addq $168, %rsp .cfi_remember_state .cfi_def_cfa_offset 8 ret .L15: .cfi_restore_state pushq 56(%rsp) .cfi_def_cfa_offset 184 pushq 56(%rsp) .cfi_def_cfa_offset 192 leaq 128(%rsp), %r9 movq 92(%rsp), %rcx movl 100(%rsp), %r8d movq 80(%rsp), %rsi movl 88(%rsp), %edx leaq _Z6binaryPhS_S_mi(%rip), %rdi call cudaLaunchKernel@PLT addq $16, %rsp .cfi_def_cfa_offset 176 jmp .L11 .L16: call __stack_chk_fail@PLT .cfi_endproc .LFE2267: .size _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi, .-_Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi .globl _Z6binaryPhS_S_mi .type _Z6binaryPhS_S_mi, @function _Z6binaryPhS_S_mi: .LFB2268: .cfi_startproc endbr64 subq $8, %rsp .cfi_def_cfa_offset 16 call _Z31__device_stub__Z6binaryPhS_S_miPhS_S_mi addq $8, %rsp .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2268: .size _Z6binaryPhS_S_mi, .-_Z6binaryPhS_S_mi .section .rodata.str1.1,"aMS",@progbits,1 .LC0: .string "_Z6binaryPhS_S_mi" .LC1: .string "_Z9grayscalePhS_S_mPj" .LC2: .string "precalc_xorwow_matrix" .LC3: .string "precalc_xorwow_offset_matrix" .LC4: .string "mrg32k3aM1" .LC5: .string "mrg32k3aM2" .LC6: .string "mrg32k3aM1SubSeq" .LC7: .string "mrg32k3aM2SubSeq" .LC8: .string "mrg32k3aM1Seq" .LC9: .string "mrg32k3aM2Seq" .LC10: .string "__cr_lgamma_table" .text .type _ZL24__sti____cudaRegisterAllv, @function _ZL24__sti____cudaRegisterAllv: .LFB2270: .cfi_startproc endbr64 pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 leaq _ZL15__fatDeviceText(%rip), %rdi call __cudaRegisterFatBinary@PLT movq %rax, %rbx movq %rax, _ZL20__cudaFatCubinHandle(%rip) pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC0(%rip), %rdx movq %rdx, %rcx leaq _Z6binaryPhS_S_mi(%rip), %rsi movq %rax, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 pushq $0 .cfi_def_cfa_offset 40 pushq $0 .cfi_def_cfa_offset 48 movl $0, %r9d movl $-1, %r8d leaq .LC1(%rip), %rdx movq %rdx, %rcx leaq _Z9grayscalePhS_S_mPj(%rip), %rsi movq %rbx, %rdi call __cudaRegisterFunction@PLT addq $32, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC2(%rip), %rdx movq %rdx, %rcx leaq _ZL21precalc_xorwow_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $102400, %r9d movl $0, %r8d leaq .LC3(%rip), %rdx movq %rdx, %rcx leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC4(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM1(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC5(%rip), %rdx movq %rdx, %rcx leaq _ZL10mrg32k3aM2(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC6(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2016, %r9d movl $0, %r8d leaq .LC7(%rip), %rdx movq %rdx, %rcx leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC8(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM1Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $0 .cfi_def_cfa_offset 32 movl $2304, %r9d movl $0, %r8d leaq .LC9(%rip), %rdx movq %rdx, %rcx leaq _ZL13mrg32k3aM2Seq(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 pushq $0 .cfi_def_cfa_offset 24 pushq $1 .cfi_def_cfa_offset 32 movl $72, %r9d movl $0, %r8d leaq .LC10(%rip), %rdx movq %rdx, %rcx leaq _ZL17__cr_lgamma_table(%rip), %rsi movq %rbx, %rdi call __cudaRegisterVar@PLT addq $16, %rsp .cfi_def_cfa_offset 16 movq _ZL20__cudaFatCubinHandle(%rip), %rdi call __cudaRegisterFatBinaryEnd@PLT leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi call atexit@PLT popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE2270: .size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv .section .init_array,"aw" .align 8 .quad _ZL24__sti____cudaRegisterAllv .section .nvFatBinSegment,"aw" .align 8 .type _ZL15__fatDeviceText, @object .size _ZL15__fatDeviceText, 24 _ZL15__fatDeviceText: .long 1180844977 .long 1 .quad fatbinData .quad 0 .local _ZL20__cudaFatCubinHandle .comm _ZL20__cudaFatCubinHandle,8,8 .local _ZL17__cr_lgamma_table .comm _ZL17__cr_lgamma_table,72,32 .local _ZL13mrg32k3aM2Seq .comm _ZL13mrg32k3aM2Seq,2304,32 .local _ZL13mrg32k3aM1Seq .comm _ZL13mrg32k3aM1Seq,2304,32 .local _ZL16mrg32k3aM2SubSeq .comm _ZL16mrg32k3aM2SubSeq,2016,32 .local _ZL16mrg32k3aM1SubSeq .comm _ZL16mrg32k3aM1SubSeq,2016,32 .local _ZL10mrg32k3aM2 .comm _ZL10mrg32k3aM2,2304,32 .local _ZL10mrg32k3aM1 .comm _ZL10mrg32k3aM1,2304,32 .local _ZL28precalc_xorwow_offset_matrix .comm _ZL28precalc_xorwow_offset_matrix,102400,32 .local _ZL21precalc_xorwow_matrix .comm _ZL21precalc_xorwow_matrix,102400,32 .ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0" .section .note.GNU-stack,"",@progbits .section .note.gnu.property,"a" .align 8 .long 1f - 0f .long 4f - 1f .long 5 0: .string "GNU" 1: .align 8 .long 0xc0000002 .long 3f - 2f 2: .long 0x3 3: .align 8 4:
.text .file "threshold.hip" .globl _Z24__device_stub__grayscalePhS_S_mPj # -- Begin function _Z24__device_stub__grayscalePhS_S_mPj .p2align 4, 0x90 .type _Z24__device_stub__grayscalePhS_S_mPj,@function _Z24__device_stub__grayscalePhS_S_mPj: # @_Z24__device_stub__grayscalePhS_S_mPj .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movq %r8, 56(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 56(%rsp), %rax movq %rax, 128(%rsp) leaq 40(%rsp), %rdi leaq 24(%rsp), %rsi leaq 16(%rsp), %rdx leaq 8(%rsp), %rcx callq __hipPopCallConfiguration movq 40(%rsp), %rsi movl 48(%rsp), %edx movq 24(%rsp), %rcx movl 32(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z9grayscalePhS_S_mPj, %edi pushq 8(%rsp) .cfi_adjust_cfa_offset 8 pushq 24(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end0: .size _Z24__device_stub__grayscalePhS_S_mPj, .Lfunc_end0-_Z24__device_stub__grayscalePhS_S_mPj .cfi_endproc # -- End function .globl _Z21__device_stub__binaryPhS_S_mi # -- Begin function _Z21__device_stub__binaryPhS_S_mi .p2align 4, 0x90 .type _Z21__device_stub__binaryPhS_S_mi,@function _Z21__device_stub__binaryPhS_S_mi: # @_Z21__device_stub__binaryPhS_S_mi .cfi_startproc # %bb.0: subq $136, %rsp .cfi_def_cfa_offset 144 movq %rdi, 88(%rsp) movq %rsi, 80(%rsp) movq %rdx, 72(%rsp) movq %rcx, 64(%rsp) movl %r8d, 12(%rsp) leaq 88(%rsp), %rax movq %rax, 96(%rsp) leaq 80(%rsp), %rax movq %rax, 104(%rsp) leaq 72(%rsp), %rax movq %rax, 112(%rsp) leaq 64(%rsp), %rax movq %rax, 120(%rsp) leaq 12(%rsp), %rax movq %rax, 128(%rsp) leaq 48(%rsp), %rdi leaq 32(%rsp), %rsi leaq 24(%rsp), %rdx leaq 16(%rsp), %rcx callq __hipPopCallConfiguration movq 48(%rsp), %rsi movl 56(%rsp), %edx movq 32(%rsp), %rcx movl 40(%rsp), %r8d leaq 96(%rsp), %r9 movl $_Z6binaryPhS_S_mi, %edi pushq 16(%rsp) .cfi_adjust_cfa_offset 8 pushq 32(%rsp) .cfi_adjust_cfa_offset 8 callq hipLaunchKernel addq $152, %rsp .cfi_adjust_cfa_offset -152 retq .Lfunc_end1: .size _Z21__device_stub__binaryPhS_S_mi, .Lfunc_end1-_Z21__device_stub__binaryPhS_S_mi .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_ctor .type __hip_module_ctor,@function __hip_module_ctor: # @__hip_module_ctor .cfi_startproc # %bb.0: pushq %rbx .cfi_def_cfa_offset 16 subq $32, %rsp .cfi_def_cfa_offset 48 .cfi_offset %rbx, -16 cmpq $0, __hip_gpubin_handle(%rip) jne .LBB2_2 # %bb.1: movl $__hip_fatbin_wrapper, %edi callq __hipRegisterFatBinary movq %rax, __hip_gpubin_handle(%rip) .LBB2_2: movq __hip_gpubin_handle(%rip), %rbx xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z9grayscalePhS_S_mPj, %esi movl $.L__unnamed_1, %edx movl $.L__unnamed_1, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction xorps %xmm0, %xmm0 movups %xmm0, 16(%rsp) movups %xmm0, (%rsp) movl $_Z6binaryPhS_S_mi, %esi movl $.L__unnamed_2, %edx movl $.L__unnamed_2, %ecx movq %rbx, %rdi movl $-1, %r8d xorl %r9d, %r9d callq __hipRegisterFunction movl $__hip_module_dtor, %edi addq $32, %rsp .cfi_def_cfa_offset 16 popq %rbx .cfi_def_cfa_offset 8 jmp atexit # TAILCALL .Lfunc_end2: .size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor .cfi_endproc # -- End function .p2align 4, 0x90 # -- Begin function __hip_module_dtor .type __hip_module_dtor,@function __hip_module_dtor: # @__hip_module_dtor .cfi_startproc # %bb.0: movq __hip_gpubin_handle(%rip), %rdi testq %rdi, %rdi je .LBB3_2 # %bb.1: pushq %rax .cfi_def_cfa_offset 16 callq __hipUnregisterFatBinary movq $0, __hip_gpubin_handle(%rip) addq $8, %rsp .cfi_def_cfa_offset 8 .LBB3_2: retq .Lfunc_end3: .size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor .cfi_endproc # -- End function .type _Z9grayscalePhS_S_mPj,@object # @_Z9grayscalePhS_S_mPj .section .rodata,"a",@progbits .globl _Z9grayscalePhS_S_mPj .p2align 3, 0x0 _Z9grayscalePhS_S_mPj: .quad _Z24__device_stub__grayscalePhS_S_mPj .size _Z9grayscalePhS_S_mPj, 8 .type _Z6binaryPhS_S_mi,@object # @_Z6binaryPhS_S_mi .globl _Z6binaryPhS_S_mi .p2align 3, 0x0 _Z6binaryPhS_S_mi: .quad _Z21__device_stub__binaryPhS_S_mi .size _Z6binaryPhS_S_mi, 8 .type .L__unnamed_1,@object # @0 .section .rodata.str1.1,"aMS",@progbits,1 .L__unnamed_1: .asciz "_Z9grayscalePhS_S_mPj" .size .L__unnamed_1, 22 .type .L__unnamed_2,@object # @1 .L__unnamed_2: .asciz "_Z6binaryPhS_S_mi" .size .L__unnamed_2, 18 .type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper .section .hipFatBinSegment,"a",@progbits .p2align 3, 0x0 __hip_fatbin_wrapper: .long 1212764230 # 0x48495046 .long 1 # 0x1 .quad __hip_fatbin .quad 0 .size __hip_fatbin_wrapper, 24 .type __hip_gpubin_handle,@object # @__hip_gpubin_handle .local __hip_gpubin_handle .comm __hip_gpubin_handle,8,8 .section .init_array,"aw",@init_array .p2align 3, 0x0 .quad __hip_module_ctor .type __hip_cuid_,@object # @__hip_cuid_ .bss .globl __hip_cuid_ __hip_cuid_: .byte 0 # 0x0 .size __hip_cuid_, 1 .section ".linker-options","e",@llvm_linker_options .ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym _Z24__device_stub__grayscalePhS_S_mPj .addrsig_sym _Z21__device_stub__binaryPhS_S_mi .addrsig_sym __hip_module_ctor .addrsig_sym __hip_module_dtor .addrsig_sym _Z9grayscalePhS_S_mPj .addrsig_sym _Z6binaryPhS_S_mi .addrsig_sym __hip_fatbin .addrsig_sym __hip_fatbin_wrapper .addrsig_sym __hip_cuid_