system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, sz_in_bytes);
hipMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
// freeing on device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdS_S_i
.globl _Z6kernelPdS_S_i
.p2align 8
.type _Z6kernelPdS_S_i,@function
_Z6kernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdS_S_i, .Lfunc_end0-_Z6kernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Compilation:
// nvcc Ex1.cu -o Ex1.exe
// __global__ => this function executes on the GPU.
// Please note that it also could be: __device__.
// This is this only code that executes on the GPU.
__global__ void kernel(double *a, double *b, double *c, int N)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = a[i] + b[i];
}
}
int main(int argc, char **argv)
{
int N = 1000;
int sz_in_bytes = N*sizeof(double);
double *h_a, *h_b, *h_c; // "h" for "host" (allocated in RAM).
double *d_a, *d_b, *d_c; // "d" for "device" (allocated in the GPU).
// Allocate memory in RAM (that is, the "host"):
// 3 arrays that contain N elements. Each element is a "double".
h_a = (double*)malloc(sz_in_bytes);
h_b = (double*)malloc(sz_in_bytes);
h_c = (double*)malloc(sz_in_bytes);
// Initiate values on h_a and h_b
for(int i = 0 ; i < N ; i++) {
h_a[i] = 1./(1.+i);
h_b[i] = (i-1.)/(i+1.);
}
// Allocate memory in the GPU (that is, the "device").
hipMalloc((void**)&d_a, sz_in_bytes);
hipMalloc((void**)&d_b, sz_in_bytes);
hipMalloc((void**)&d_c, sz_in_bytes);
// Copy the data from the RAM (host) to the GPU (device).
// Note: cudaMemcpy(dst, src, count, kind)
hipMemcpy(d_a, h_a, sz_in_bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sz_in_bytes, hipMemcpyHostToDevice);
// Set 64*1*1 thread per blocks.
// x: 64
// y: 1
// z: 1
// Note: we statically initialize *structure**.
dim3 dimBlock(64, 1, 1);
// Set (N + dimBlock.x - 1)/dimBlock.x * 1 * 1 blocs.
// If N=1000: (N + dimBlock.x - 1)/dimBlock.x => 16 blocks
// (1000 + 64 - 1) / 64 = 16
// (1000 + 64 - 1) % 64 = 39
// => There are more threads that elements in the array.
// Note: dimBlock.x = 64.
// Note: we statically initialize *structure**.
dim3 dimGrid((N + dimBlock.x - 1)/dimBlock.x, 1, 1);
// Thus, we have 64*16 = 1024 threads.
// Run the "kernel" (in the GPU).
// dimGrid: number of block in the grid => 16
// dimBlock: number of threads per bloc => 64
kernel<<<dimGrid , dimBlock>>>(d_a, d_b, d_c, N);
// Result is pointed by d_c on device.
// Copy this result on host (result pointed by h_c on host)
hipMemcpy(h_c, d_c, sz_in_bytes, hipMemcpyDeviceToHost);
// freeing on device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
return 0;
} | .text
.file "Ex1.hip"
.globl _Z21__device_stub__kernelPdS_S_i # -- Begin function _Z21__device_stub__kernelPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_i,@function
_Z21__device_stub__kernelPdS_S_i: # @_Z21__device_stub__kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
movapd %xmm2, %xmm3
addsd %xmm0, %xmm3
movapd %xmm0, %xmm4
divsd %xmm3, %xmm4
movsd %xmm4, (%rbx,%rax,8)
addsd %xmm1, %xmm2
divsd %xmm3, %xmm2
movsd %xmm2, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 48(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_i,@object # @_Z6kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_i
.p2align 3, 0x0
_Z6kernelPdS_S_i:
.quad _Z21__device_stub__kernelPdS_S_i
.size _Z6kernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPdS_S_i
.globl _Z6kernelPdS_S_i
.p2align 8
.type _Z6kernelPdS_S_i,@function
_Z6kernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPdS_S_i, .Lfunc_end0-_Z6kernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015471e_00000000-6_Ex1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
.globl _Z6kernelPdS_S_i
.type _Z6kernelPdS_S_i, @function
_Z6kernelPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPdS_S_i, .-_Z6kernelPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8000, %edi
call malloc@PLT
movq %rax, %rbp
movl $8000, %edi
call malloc@PLT
movq %rax, %rbx
movl $8000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC0(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm2
addsd %xmm1, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
movsd %xmm3, 0(%rbp,%rax,8)
subsd %xmm1, %xmm0
divsd %xmm2, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $8000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $1000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6kernelPdS_S_iPdS_S_i
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6kernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Ex1.hip"
.globl _Z21__device_stub__kernelPdS_S_i # -- Begin function _Z21__device_stub__kernelPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPdS_S_i,@function
_Z21__device_stub__kernelPdS_S_i: # @_Z21__device_stub__kernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPdS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
movapd %xmm2, %xmm3
addsd %xmm0, %xmm3
movapd %xmm0, %xmm4
divsd %xmm3, %xmm4
movsd %xmm4, (%rbx,%rax,8)
addsd %xmm1, %xmm2
divsd %xmm3, %xmm2
movsd %xmm2, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 48(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1000, 36(%rsp) # imm = 0x3E8
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6kernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPdS_S_i,@object # @_Z6kernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPdS_S_i
.p2align 3, 0x0
_Z6kernelPdS_S_i:
.quad _Z21__device_stub__kernelPdS_S_i
.size _Z6kernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <math.h>
#include <iostream>
#include <iomanip>
__global__ void ingenuo(double *out, double step, long num_steps) {
long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= num_steps) return;
double val = (i + 0.5) * step;
out[i] = 4.0 / (1.0 + val * val);
}
__global__ void esperto(double *out, double step, long num_steps, long sz) {
long i = blockIdx.x * blockDim.x + threadIdx.x;
long start = i * sz;
long end = (i+1) * sz;
double sum = 0.0;
for (int k = start; k < end; k++) {
if (k >= num_steps) break;
double val = (k + 0.5) * step;
sum += 4.0 / (1.0 + val * val);
}
out[i] = sum;
}
int main() {
long num_steps = 1000000000;
double step = 1.0 / num_steps;
int nthreads = 1024;
thrust::device_vector<double> ingenuo_data(num_steps);
int nblocks = ceil(double(num_steps) / nthreads);
ingenuo<<<nblocks, nthreads>>>(thrust::raw_pointer_cast(ingenuo_data.data()), step, num_steps);
double pi = step * thrust::reduce(ingenuo_data.begin(), ingenuo_data.end(), 0.0, thrust::plus<double>());
std::cout << std::setprecision(13);
std::cout << pi << "\n";
int els_per_thread = 4096;
thrust::device_vector<double> esperto_data(num_steps/els_per_thread+1, 0);
int nblocks2 = ceil(double(num_steps)/(nthreads * els_per_thread));
esperto<<<nblocks2, nthreads>>>(thrust::raw_pointer_cast(esperto_data.data()), step, num_steps, els_per_thread);
double pi2 = step * thrust::reduce(esperto_data.begin(), esperto_data.end(), 0.0, thrust::plus<double>());
std::cout << std::setprecision(13);
std::cout << pi2 << "\n";
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <math.h>
#include <iostream>
#include <iomanip>
__global__ void ingenuo(double *out, double step, long num_steps) {
long i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= num_steps) return;
double val = (i + 0.5) * step;
out[i] = 4.0 / (1.0 + val * val);
}
__global__ void esperto(double *out, double step, long num_steps, long sz) {
long i = blockIdx.x * blockDim.x + threadIdx.x;
long start = i * sz;
long end = (i+1) * sz;
double sum = 0.0;
for (int k = start; k < end; k++) {
if (k >= num_steps) break;
double val = (k + 0.5) * step;
sum += 4.0 / (1.0 + val * val);
}
out[i] = sum;
}
int main() {
long num_steps = 1000000000;
double step = 1.0 / num_steps;
int nthreads = 1024;
thrust::device_vector<double> ingenuo_data(num_steps);
int nblocks = ceil(double(num_steps) / nthreads);
ingenuo<<<nblocks, nthreads>>>(thrust::raw_pointer_cast(ingenuo_data.data()), step, num_steps);
double pi = step * thrust::reduce(ingenuo_data.begin(), ingenuo_data.end(), 0.0, thrust::plus<double>());
std::cout << std::setprecision(13);
std::cout << pi << "\n";
int els_per_thread = 4096;
thrust::device_vector<double> esperto_data(num_steps/els_per_thread+1, 0);
int nblocks2 = ceil(double(num_steps)/(nthreads * els_per_thread));
esperto<<<nblocks2, nthreads>>>(thrust::raw_pointer_cast(esperto_data.data()), step, num_steps, els_per_thread);
double pi2 = step * thrust::reduce(esperto_data.begin(), esperto_data.end(), 0.0, thrust::plus<double>());
std::cout << std::setprecision(13);
std::cout << pi2 << "\n";
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void step(
int n,
float *xy,
int *num_edges,
int *first,
int *num,
int *map,
int *potential,
float stp,
float reject_stp,
float attract_stp,
float spring_stp,
float spring_reject_rad,
float spring_attract_rad,
float node_rad
){
const int i = blockIdx.x*512 + threadIdx.x;
if (i>=n) {
return;
}
float sx = 0;
float sy = 0;
float dx = 0;
float dy = 0;
float dd = 0;
int j;
int jj;
int aa;
int count = 0;
bool linked;
float ja;
float ia;
const int ii = 2*i;
for (int k=0;k<num[i];k++){
j = map[first[i]+k];
jj = 2*j;
dx = xy[ii] - xy[jj];
dy = xy[ii+1] - xy[jj+1];
dd = sqrt(dx*dx + dy*dy);
linked = true;
for (int l=0;l<num[i];l++){
aa = 2*map[first[i]+l];
ia = sqrt(powf(xy[ii] - xy[aa],2.0) + powf(xy[ii+1] - xy[aa+1],2.0));
ja = sqrt(powf(xy[jj] - xy[aa],2.0) + powf(xy[jj+1] - xy[aa+1],2.0));
if (dd>max(ia,ja)){
linked = false;
break;
}
}
if (dd>0.0){
dx /= dd;
dy /= dd;
if (linked){
/*if (dd<2*spring_attract_rad && linked){*/
count += 1;
if (dd>spring_attract_rad){
sx += -dx*spring_stp;
sy += -dy*spring_stp;
}
else if(dd<spring_reject_rad){
sx += dx*spring_stp;
sy += dy*spring_stp;
}
}
else{ // unlinked
if (potential[i]>0 && potential[j]>0){
sx += -dx*attract_stp;
sy += -dy*attract_stp;
}
else{
sx += dx*reject_stp;
sy += dy*reject_stp;
}
}
}
}
__syncthreads();
xy[ii] = xy[ii] + sx*stp;
xy[ii+1] = xy[ii+1] + sy*stp;
num_edges[i] = count;
} | .file "tmpxft_00049b61_00000000-6_step.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
.type _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff, @function
_Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 72(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movss %xmm4, 8(%rsp)
movss %xmm5, 4(%rsp)
movss %xmm6, (%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 4(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z4stepiPfPiS0_S0_S0_S0_fffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff, .-_Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
.globl _Z4stepiPfPiS0_S0_S0_S0_fffffff
.type _Z4stepiPfPiS0_S0_S0_S0_fffffff, @function
_Z4stepiPfPiS0_S0_S0_S0_fffffff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4stepiPfPiS0_S0_S0_S0_fffffff, .-_Z4stepiPfPiS0_S0_S0_S0_fffffff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z4stepiPfPiS0_S0_S0_S0_fffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4stepiPfPiS0_S0_S0_S0_fffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void step(
int n,
float *xy,
int *num_edges,
int *first,
int *num,
int *map,
int *potential,
float stp,
float reject_stp,
float attract_stp,
float spring_stp,
float spring_reject_rad,
float spring_attract_rad,
float node_rad
){
const int i = blockIdx.x*512 + threadIdx.x;
if (i>=n) {
return;
}
float sx = 0;
float sy = 0;
float dx = 0;
float dy = 0;
float dd = 0;
int j;
int jj;
int aa;
int count = 0;
bool linked;
float ja;
float ia;
const int ii = 2*i;
for (int k=0;k<num[i];k++){
j = map[first[i]+k];
jj = 2*j;
dx = xy[ii] - xy[jj];
dy = xy[ii+1] - xy[jj+1];
dd = sqrt(dx*dx + dy*dy);
linked = true;
for (int l=0;l<num[i];l++){
aa = 2*map[first[i]+l];
ia = sqrt(powf(xy[ii] - xy[aa],2.0) + powf(xy[ii+1] - xy[aa+1],2.0));
ja = sqrt(powf(xy[jj] - xy[aa],2.0) + powf(xy[jj+1] - xy[aa+1],2.0));
if (dd>max(ia,ja)){
linked = false;
break;
}
}
if (dd>0.0){
dx /= dd;
dy /= dd;
if (linked){
/*if (dd<2*spring_attract_rad && linked){*/
count += 1;
if (dd>spring_attract_rad){
sx += -dx*spring_stp;
sy += -dy*spring_stp;
}
else if(dd<spring_reject_rad){
sx += dx*spring_stp;
sy += dy*spring_stp;
}
}
else{ // unlinked
if (potential[i]>0 && potential[j]>0){
sx += -dx*attract_stp;
sy += -dy*attract_stp;
}
else{
sx += dx*reject_stp;
sy += dy*reject_stp;
}
}
}
}
__syncthreads();
xy[ii] = xy[ii] + sx*stp;
xy[ii+1] = xy[ii+1] + sy*stp;
num_edges[i] = count;
} | #include <hip/hip_runtime.h>
__global__ void step(
int n,
float *xy,
int *num_edges,
int *first,
int *num,
int *map,
int *potential,
float stp,
float reject_stp,
float attract_stp,
float spring_stp,
float spring_reject_rad,
float spring_attract_rad,
float node_rad
){
const int i = blockIdx.x*512 + threadIdx.x;
if (i>=n) {
return;
}
float sx = 0;
float sy = 0;
float dx = 0;
float dy = 0;
float dd = 0;
int j;
int jj;
int aa;
int count = 0;
bool linked;
float ja;
float ia;
const int ii = 2*i;
for (int k=0;k<num[i];k++){
j = map[first[i]+k];
jj = 2*j;
dx = xy[ii] - xy[jj];
dy = xy[ii+1] - xy[jj+1];
dd = sqrt(dx*dx + dy*dy);
linked = true;
for (int l=0;l<num[i];l++){
aa = 2*map[first[i]+l];
ia = sqrt(powf(xy[ii] - xy[aa],2.0) + powf(xy[ii+1] - xy[aa+1],2.0));
ja = sqrt(powf(xy[jj] - xy[aa],2.0) + powf(xy[jj+1] - xy[aa+1],2.0));
if (dd>max(ia,ja)){
linked = false;
break;
}
}
if (dd>0.0){
dx /= dd;
dy /= dd;
if (linked){
/*if (dd<2*spring_attract_rad && linked){*/
count += 1;
if (dd>spring_attract_rad){
sx += -dx*spring_stp;
sy += -dy*spring_stp;
}
else if(dd<spring_reject_rad){
sx += dx*spring_stp;
sy += dy*spring_stp;
}
}
else{ // unlinked
if (potential[i]>0 && potential[j]>0){
sx += -dx*attract_stp;
sy += -dy*attract_stp;
}
else{
sx += dx*reject_stp;
sy += dy*reject_stp;
}
}
}
}
__syncthreads();
xy[ii] = xy[ii] + sx*stp;
xy[ii+1] = xy[ii+1] + sy*stp;
num_edges[i] = count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void step(
int n,
float *xy,
int *num_edges,
int *first,
int *num,
int *map,
int *potential,
float stp,
float reject_stp,
float attract_stp,
float spring_stp,
float spring_reject_rad,
float spring_attract_rad,
float node_rad
){
const int i = blockIdx.x*512 + threadIdx.x;
if (i>=n) {
return;
}
float sx = 0;
float sy = 0;
float dx = 0;
float dy = 0;
float dd = 0;
int j;
int jj;
int aa;
int count = 0;
bool linked;
float ja;
float ia;
const int ii = 2*i;
for (int k=0;k<num[i];k++){
j = map[first[i]+k];
jj = 2*j;
dx = xy[ii] - xy[jj];
dy = xy[ii+1] - xy[jj+1];
dd = sqrt(dx*dx + dy*dy);
linked = true;
for (int l=0;l<num[i];l++){
aa = 2*map[first[i]+l];
ia = sqrt(powf(xy[ii] - xy[aa],2.0) + powf(xy[ii+1] - xy[aa+1],2.0));
ja = sqrt(powf(xy[jj] - xy[aa],2.0) + powf(xy[jj+1] - xy[aa+1],2.0));
if (dd>max(ia,ja)){
linked = false;
break;
}
}
if (dd>0.0){
dx /= dd;
dy /= dd;
if (linked){
/*if (dd<2*spring_attract_rad && linked){*/
count += 1;
if (dd>spring_attract_rad){
sx += -dx*spring_stp;
sy += -dy*spring_stp;
}
else if(dd<spring_reject_rad){
sx += dx*spring_stp;
sy += dy*spring_stp;
}
}
else{ // unlinked
if (potential[i]>0 && potential[j]>0){
sx += -dx*attract_stp;
sy += -dy*attract_stp;
}
else{
sx += dx*reject_stp;
sy += dy*reject_stp;
}
}
}
}
__syncthreads();
xy[ii] = xy[ii] + sx*stp;
xy[ii+1] = xy[ii+1] + sy*stp;
num_edges[i] = count;
} | .text
.file "step.hip"
.globl _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff # -- Begin function _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.p2align 4, 0x90
.type _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff,@function
_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff: # @_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 36(%rsp)
movq %rsi, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rcx, 104(%rsp)
movq %r8, 96(%rsp)
movq %r9, 88(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4stepiPfPiS0_S0_S0_S0_fffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff, .Lfunc_end0-_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4stepiPfPiS0_S0_S0_S0_fffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4stepiPfPiS0_S0_S0_S0_fffffff,@object # @_Z4stepiPfPiS0_S0_S0_S0_fffffff
.section .rodata,"a",@progbits
.globl _Z4stepiPfPiS0_S0_S0_S0_fffffff
.p2align 3, 0x0
_Z4stepiPfPiS0_S0_S0_S0_fffffff:
.quad _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.size _Z4stepiPfPiS0_S0_S0_S0_fffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4stepiPfPiS0_S0_S0_S0_fffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4stepiPfPiS0_S0_S0_S0_fffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00049b61_00000000-6_step.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
.type _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff, @function
_Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 72(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movss %xmm4, 8(%rsp)
movss %xmm5, 4(%rsp)
movss %xmm6, (%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 4(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z4stepiPfPiS0_S0_S0_S0_fffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff, .-_Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
.globl _Z4stepiPfPiS0_S0_S0_S0_fffffff
.type _Z4stepiPfPiS0_S0_S0_S0_fffffff, @function
_Z4stepiPfPiS0_S0_S0_S0_fffffff:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z4stepiPfPiS0_S0_S0_S0_fffffffiPfPiS0_S0_S0_S0_fffffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4stepiPfPiS0_S0_S0_S0_fffffff, .-_Z4stepiPfPiS0_S0_S0_S0_fffffff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z4stepiPfPiS0_S0_S0_S0_fffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4stepiPfPiS0_S0_S0_S0_fffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "step.hip"
.globl _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff # -- Begin function _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.p2align 4, 0x90
.type _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff,@function
_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff: # @_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 36(%rsp)
movq %rsi, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rcx, 104(%rsp)
movq %r8, 96(%rsp)
movq %r9, 88(%rsp)
movss %xmm0, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 20(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 12(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4stepiPfPiS0_S0_S0_S0_fffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff, .Lfunc_end0-_Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4stepiPfPiS0_S0_S0_S0_fffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4stepiPfPiS0_S0_S0_S0_fffffff,@object # @_Z4stepiPfPiS0_S0_S0_S0_fffffff
.section .rodata,"a",@progbits
.globl _Z4stepiPfPiS0_S0_S0_S0_fffffff
.p2align 3, 0x0
_Z4stepiPfPiS0_S0_S0_S0_fffffff:
.quad _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.size _Z4stepiPfPiS0_S0_S0_S0_fffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4stepiPfPiS0_S0_S0_S0_fffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__stepiPfPiS0_S0_S0_S0_fffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4stepiPfPiS0_S0_S0_S0_fffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} | code for sm_80
Function : _Z17create_fpr_kernelPfPKiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R5, c[0x0][0x17c] ; /* 0x00005f0000057b06 */
/* 0x000ea40000201400 */
/*00d0*/ FADD R5, -R0, R5 ; /* 0x0000000500057221 */
/* 0x004fcc0000000100 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*00f0*/ IMAD.WIDE R8, R4, R3, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*0120*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0130*/ MUFU.RCP R10, R5 ; /* 0x00000005000a7308 */
/* 0x000e220000001000 */
/*0140*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0150*/ BSSY B0, 0x280 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0160*/ FFMA R11, -R5, R10, 1 ; /* 0x3f800000050b7423 */
/* 0x001fc8000000010a */
/*0170*/ FFMA R11, R10, R11, R10 ; /* 0x0000000b0a0b7223 */
/* 0x000fe2000000000a */
/*0180*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x004e240000201400 */
/*0190*/ FADD R6, R6, 1 ; /* 0x3f80000006067421 */
/* 0x001fc80000000000 */
/*01a0*/ FADD R12, R6, -R7 ; /* 0x80000007060c7221 */
/* 0x008fe40000000000 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R4.reuse ; /* 0x000000ffff067224 */
/* 0x100fe400078e0004 */
/*01c0*/ FCHK P0, R12, R5 ; /* 0x000000050c007302 */
/* 0x000e220000000000 */
/*01d0*/ FFMA R10, R12, R11, RZ ; /* 0x0000000b0c0a7223 */
/* 0x000fe400000000ff */
/*01e0*/ IMAD R4, R13, c[0x0][0xc], R4 ; /* 0x000003000d047a24 */
/* 0x000fe400078e0204 */
/*01f0*/ FFMA R8, -R5, R10, R12 ; /* 0x0000000a05087223 */
/* 0x000fc6000000010c */
/*0200*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f46270 */
/*0210*/ FFMA R11, R11, R8, R10 ; /* 0x000000080b0b7223 */
/* 0x000fe2000000000a */
/*0220*/ @!P0 BRA 0x270 ; /* 0x0000004000008947 */
/* 0x001fec0003800000 */
/*0230*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000c */
/*0240*/ MOV R8, 0x270 ; /* 0x0000027000087802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0005 */
/*0260*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000016000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ MUFU.RCP R13, R0 ; /* 0x00000000000d7308 */
/* 0x000e220000001000 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*02a0*/ BSSY B0, 0x3a0 ; /* 0x000000f000007945 */
/* 0x000fe60003800000 */
/*02b0*/ IMAD.WIDE R8, R6, R9, c[0x0][0x170] ; /* 0x00005c0006087625 */
/* 0x000fc600078e0209 */
/*02c0*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000e640000000000 */
/*02d0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0005e2000c101904 */
/*02e0*/ FFMA R6, -R0, R13, 1 ; /* 0x3f80000000067423 */
/* 0x001fc8000000010d */
/*02f0*/ FFMA R6, R13, R6, R13 ; /* 0x000000060d067223 */
/* 0x000fc8000000000d */
/*0300*/ FFMA R13, R7, R6, RZ ; /* 0x00000006070d7223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R10, -R0, R13, R7 ; /* 0x0000000d000a7223 */
/* 0x000fc80000000107 */
/*0320*/ FFMA R13, R6, R10, R13 ; /* 0x0000000a060d7223 */
/* 0x000fe2000000000d */
/*0330*/ @!P0 BRA 0x390 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0340*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x004fe200078e0007 */
/*0350*/ MOV R8, 0x380 ; /* 0x0000038000087802 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*0370*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0380*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*03a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*03b0*/ @!P2 BRA 0xe0 ; /* 0xfffffd200000a947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R11, RZ, 0x17, R12 ; /* 0x00000017ff0b7819 */
/* 0x000fe2000001160c */
/*03e0*/ BSSY B1, 0xa20 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*03f0*/ SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; /* 0x00000017ff097819 */
/* 0x100fe4000001160d */
/*0400*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0410*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe200078ec0ff */
/*0420*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0430*/ IADD3 R16, R11, -0x1, RZ ; /* 0xffffffff0b107810 */
/* 0x000fc40007ffe0ff */
/*0440*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fc80003f04070 */
/*0460*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0470*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0480*/ @!P0 BRA 0x600 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*04a0*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*04b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04c0*/ @P0 BRA 0xa00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c809 */
/*04e0*/ @!P0 BRA 0x9e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04f0*/ FSETP.NEU.FTZ.AND P3, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f7d200 */
/*0500*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*0510*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0520*/ @!P1 BRA !P3, 0x9e0 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0530*/ LOP3.LUT P3, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000786c0ff */
/*0540*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0550*/ @P1 BRA 0x9c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0560*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0570*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0580*/ @P0 BRA 0x990 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*05a0*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*05b0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*05c0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*05d0*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*05e0*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*05f0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0600*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0610*/ BSSY B2, 0x980 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0620*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0630*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0640*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x0000620000001000 */
/*0650*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*0660*/ IMAD R9, R12.reuse, -0x800000, R9 ; /* 0xff8000000c097824 */
/* 0x040fe200078e0209 */
/*0670*/ IADD3 R13, R12, 0x7f, -R11 ; /* 0x0000007f0c0d7810 */
/* 0x001fca0007ffe80b */
/*0680*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fe400078e020a */
/*0690*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x002fc80000000010 */
/*06a0*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*06b0*/ FFMA R14, R9, R18, RZ ; /* 0x00000012090e7223 */
/* 0x000fc800000000ff */
/*06c0*/ FFMA R15, R16, R14, R9 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000009 */
/*06d0*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*06e0*/ FFMA R16, R16, R15, R9 ; /* 0x0000000f10107223 */
/* 0x000fc80000000009 */
/*06f0*/ FFMA R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fca000000000f */
/*0700*/ SHF.R.U32.HI R11, RZ, 0x17, R9 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011609 */
/*0710*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R14, R11, 0x1, R10 ; /* 0x000000010b0e7824 */
/* 0x000fca00078e020a */
/*0730*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0750*/ @!P0 BRA 0x960 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0770*/ @P0 BRA 0x930 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0790*/ @P0 BRA 0x970 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*07b0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*07c0*/ @!P0 BRA 0x970 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07d0*/ FFMA.RZ R10, R18, R16.reuse, R15.reuse ; /* 0x00000010120a7223 */
/* 0x180fe2000000c00f */
/*07e0*/ IADD3 R13, R14, 0x20, RZ ; /* 0x000000200e0d7810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ FFMA.RM R11, R18, R16.reuse, R15.reuse ; /* 0x00000010120b7223 */
/* 0x180fe2000000400f */
/*0800*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f65270 */
/*0810*/ LOP3.LUT R12, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0c7812 */
/* 0x000fe200078ec0ff */
/*0820*/ FFMA.RP R10, R18, R16, R15 ; /* 0x00000010120a7223 */
/* 0x000fe2000000800f */
/*0830*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0840*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*0850*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0860*/ FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x000fc40003f1d000 */
/*0870*/ SHF.L.U32 R13, R12, R13, RZ ; /* 0x0000000d0c0d7219 */
/* 0x000fe400000006ff */
/*0880*/ SEL R11, R14, RZ, P3 ; /* 0x000000ff0e0b7207 */
/* 0x000fe40001800000 */
/*0890*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*08a0*/ SHF.R.U32.HI R11, RZ, R11, R12 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160c */
/*08b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*08c0*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fc4000001160b */
/*08d0*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fc80004000000 */
/*08e0*/ LOP3.LUT R10, R10, 0x1, R13, 0xf8, !PT ; /* 0x000000010a0a7812 */
/* 0x000fc800078ef80d */
/*08f0*/ LOP3.LUT R10, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fca00078ec0ff */
/*0900*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fca00078e020a */
/*0910*/ LOP3.LUT R9, R10, R9, RZ, 0xfc, !PT ; /* 0x000000090a097212 */
/* 0x000fe200078efcff */
/*0920*/ BRA 0x970 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0930*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0940*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ IMAD R9, R10, 0x800000, R9 ; /* 0x008000000a097824 */
/* 0x000fe400078e0209 */
/*0970*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0980*/ BRA 0xa10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fc800078e4809 */
/*09a0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*09b0*/ BRA 0xa10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09c0*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078e4809 */
/*09d0*/ BRA 0xa10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09e0*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*09f0*/ BRA 0xa10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a00*/ FADD.FTZ R9, R13, R12 ; /* 0x0000000c0d097221 */
/* 0x000fe40000010000 */
/*0a10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a20*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0009 */
/*0a30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff5b008007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} | .file "tmpxft_001983d6_00000000-6_create_fpr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
.type _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii, @function
_Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17create_fpr_kernelPfPKiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii, .-_Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
.globl _Z17create_fpr_kernelPfPKiS_ii
.type _Z17create_fpr_kernelPfPKiS_ii, @function
_Z17create_fpr_kernelPfPKiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17create_fpr_kernelPfPKiS_ii, .-_Z17create_fpr_kernelPfPKiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17create_fpr_kernelPfPKiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17create_fpr_kernelPfPKiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17create_fpr_kernelPfPKiS_ii
.globl _Z17create_fpr_kernelPfPKiS_ii
.p2align 8
.type _Z17create_fpr_kernelPfPKiS_ii,@function
_Z17create_fpr_kernelPfPKiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
s_load_b32 s13, s[0:1], 0x1c
s_lshl_b64 s[14:15], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s14
s_addc_u32 s1, s5, s15
s_add_u32 s0, s0, -4
s_addc_u32 s1, s1, -1
v_cvt_f32_i32_e32 v0, s13
s_load_b32 s3, s[0:1], 0x0
s_load_b32 s10, s[10:11], 0x0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v0, s3, v0
s_mul_i32 s10, s10, s12
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_cmp_le_i32_e64 s1, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
s_or_b32 s11, s1, s11
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(0)
v_div_scale_f32 v9, null, s3, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v9, v11, 1.0
v_dual_add_f32 v6, 1.0, v6 :: v_dual_fmac_f32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_div_scale_f32 v8, null, v0, v0, v6
v_div_scale_f32 v14, vcc_lo, v6, v0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v8, v10, 1.0
v_fmac_f32_e32 v10, v12, v10
v_div_scale_f32 v12, s0, v7, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v12, v11
v_fma_f32 v17, -v9, v15, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v15, v17, v11
v_mul_f32_e32 v13, v14, v10
v_fma_f32 v9, -v9, v15, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v8, v13, v14
v_fmac_f32_e32 v13, v16, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v13, v14
v_div_fmas_f32 v8, v8, v10, v13
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v9, v9, v11, v15
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v6, v8, v0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_div_fixup_f32 v7, v9, s3, v7
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17create_fpr_kernelPfPKiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17create_fpr_kernelPfPKiS_ii, .Lfunc_end0-_Z17create_fpr_kernelPfPKiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17create_fpr_kernelPfPKiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17create_fpr_kernelPfPKiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void create_fpr_kernel(float* tpr, const int* unique_index, float* fpr, int num_selected, int num_total) {
float pos_cnt = tpr[num_selected - 1];
float neg_cnt = num_total - pos_cnt;
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_selected; gid += blockDim.x * gridDim.x) {
float tp = tpr[gid];
fpr[gid] = (1.0f + unique_index[gid] - tp) / neg_cnt;
tpr[gid] = tp / pos_cnt;
}
} | .text
.file "create_fpr_kernel.hip"
.globl _Z32__device_stub__create_fpr_kernelPfPKiS_ii # -- Begin function _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.p2align 4, 0x90
.type _Z32__device_stub__create_fpr_kernelPfPKiS_ii,@function
_Z32__device_stub__create_fpr_kernelPfPKiS_ii: # @_Z32__device_stub__create_fpr_kernelPfPKiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17create_fpr_kernelPfPKiS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__create_fpr_kernelPfPKiS_ii, .Lfunc_end0-_Z32__device_stub__create_fpr_kernelPfPKiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17create_fpr_kernelPfPKiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17create_fpr_kernelPfPKiS_ii,@object # @_Z17create_fpr_kernelPfPKiS_ii
.section .rodata,"a",@progbits
.globl _Z17create_fpr_kernelPfPKiS_ii
.p2align 3, 0x0
_Z17create_fpr_kernelPfPKiS_ii:
.quad _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.size _Z17create_fpr_kernelPfPKiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17create_fpr_kernelPfPKiS_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17create_fpr_kernelPfPKiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17create_fpr_kernelPfPKiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0203 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R5, c[0x0][0x17c] ; /* 0x00005f0000057b06 */
/* 0x000ea40000201400 */
/*00d0*/ FADD R5, -R0, R5 ; /* 0x0000000500057221 */
/* 0x004fcc0000000100 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*00f0*/ IMAD.WIDE R8, R4, R3, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*0120*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*0130*/ MUFU.RCP R10, R5 ; /* 0x00000005000a7308 */
/* 0x000e220000001000 */
/*0140*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0150*/ BSSY B0, 0x280 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0160*/ FFMA R11, -R5, R10, 1 ; /* 0x3f800000050b7423 */
/* 0x001fc8000000010a */
/*0170*/ FFMA R11, R10, R11, R10 ; /* 0x0000000b0a0b7223 */
/* 0x000fe2000000000a */
/*0180*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x004e240000201400 */
/*0190*/ FADD R6, R6, 1 ; /* 0x3f80000006067421 */
/* 0x001fc80000000000 */
/*01a0*/ FADD R12, R6, -R7 ; /* 0x80000007060c7221 */
/* 0x008fe40000000000 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R4.reuse ; /* 0x000000ffff067224 */
/* 0x100fe400078e0004 */
/*01c0*/ FCHK P0, R12, R5 ; /* 0x000000050c007302 */
/* 0x000e220000000000 */
/*01d0*/ FFMA R10, R12, R11, RZ ; /* 0x0000000b0c0a7223 */
/* 0x000fe400000000ff */
/*01e0*/ IMAD R4, R13, c[0x0][0xc], R4 ; /* 0x000003000d047a24 */
/* 0x000fe400078e0204 */
/*01f0*/ FFMA R8, -R5, R10, R12 ; /* 0x0000000a05087223 */
/* 0x000fc6000000010c */
/*0200*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f46270 */
/*0210*/ FFMA R11, R11, R8, R10 ; /* 0x000000080b0b7223 */
/* 0x000fe2000000000a */
/*0220*/ @!P0 BRA 0x270 ; /* 0x0000004000008947 */
/* 0x001fec0003800000 */
/*0230*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000c */
/*0240*/ MOV R8, 0x270 ; /* 0x0000027000087802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0005 */
/*0260*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000016000007944 */
/* 0x000fea0003c00000 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ MUFU.RCP R13, R0 ; /* 0x00000000000d7308 */
/* 0x000e220000001000 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*02a0*/ BSSY B0, 0x3a0 ; /* 0x000000f000007945 */
/* 0x000fe60003800000 */
/*02b0*/ IMAD.WIDE R8, R6, R9, c[0x0][0x170] ; /* 0x00005c0006087625 */
/* 0x000fc600078e0209 */
/*02c0*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000e640000000000 */
/*02d0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0005e2000c101904 */
/*02e0*/ FFMA R6, -R0, R13, 1 ; /* 0x3f80000000067423 */
/* 0x001fc8000000010d */
/*02f0*/ FFMA R6, R13, R6, R13 ; /* 0x000000060d067223 */
/* 0x000fc8000000000d */
/*0300*/ FFMA R13, R7, R6, RZ ; /* 0x00000006070d7223 */
/* 0x000fc800000000ff */
/*0310*/ FFMA R10, -R0, R13, R7 ; /* 0x0000000d000a7223 */
/* 0x000fc80000000107 */
/*0320*/ FFMA R13, R6, R10, R13 ; /* 0x0000000a060d7223 */
/* 0x000fe2000000000d */
/*0330*/ @!P0 BRA 0x390 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0340*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x004fe200078e0007 */
/*0350*/ MOV R8, 0x380 ; /* 0x0000038000087802 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*0370*/ CALL.REL.NOINC 0x3d0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0380*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*03a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*03b0*/ @!P2 BRA 0xe0 ; /* 0xfffffd200000a947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R11, RZ, 0x17, R12 ; /* 0x00000017ff0b7819 */
/* 0x000fe2000001160c */
/*03e0*/ BSSY B1, 0xa20 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*03f0*/ SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; /* 0x00000017ff097819 */
/* 0x100fe4000001160d */
/*0400*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0410*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe200078ec0ff */
/*0420*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0430*/ IADD3 R16, R11, -0x1, RZ ; /* 0xffffffff0b107810 */
/* 0x000fc40007ffe0ff */
/*0440*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fc80003f04070 */
/*0460*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0470*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0480*/ @!P0 BRA 0x600 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*04a0*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*04b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*04c0*/ @P0 BRA 0xa00 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*04d0*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c809 */
/*04e0*/ @!P0 BRA 0x9e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04f0*/ FSETP.NEU.FTZ.AND P3, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f7d200 */
/*0500*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*0510*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0520*/ @!P1 BRA !P3, 0x9e0 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0530*/ LOP3.LUT P3, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000786c0ff */
/*0540*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0550*/ @P1 BRA 0x9c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0560*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0570*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0580*/ @P0 BRA 0x990 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*05a0*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*05b0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*05c0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*05d0*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*05e0*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*05f0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0600*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0610*/ BSSY B2, 0x980 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0620*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0630*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0640*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x0000620000001000 */
/*0650*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*0660*/ IMAD R9, R12.reuse, -0x800000, R9 ; /* 0xff8000000c097824 */
/* 0x040fe200078e0209 */
/*0670*/ IADD3 R13, R12, 0x7f, -R11 ; /* 0x0000007f0c0d7810 */
/* 0x001fca0007ffe80b */
/*0680*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fe400078e020a */
/*0690*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x002fc80000000010 */
/*06a0*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*06b0*/ FFMA R14, R9, R18, RZ ; /* 0x00000012090e7223 */
/* 0x000fc800000000ff */
/*06c0*/ FFMA R15, R16, R14, R9 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000009 */
/*06d0*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*06e0*/ FFMA R16, R16, R15, R9 ; /* 0x0000000f10107223 */
/* 0x000fc80000000009 */
/*06f0*/ FFMA R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fca000000000f */
/*0700*/ SHF.R.U32.HI R11, RZ, 0x17, R9 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011609 */
/*0710*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R14, R11, 0x1, R10 ; /* 0x000000010b0e7824 */
/* 0x000fca00078e020a */
/*0730*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fc80007ffe0ff */
/*0740*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0750*/ @!P0 BRA 0x960 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0770*/ @P0 BRA 0x930 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0780*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0790*/ @P0 BRA 0x970 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*07a0*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*07b0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*07c0*/ @!P0 BRA 0x970 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*07d0*/ FFMA.RZ R10, R18, R16.reuse, R15.reuse ; /* 0x00000010120a7223 */
/* 0x180fe2000000c00f */
/*07e0*/ IADD3 R13, R14, 0x20, RZ ; /* 0x000000200e0d7810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ FFMA.RM R11, R18, R16.reuse, R15.reuse ; /* 0x00000010120b7223 */
/* 0x180fe2000000400f */
/*0800*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f65270 */
/*0810*/ LOP3.LUT R12, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0c7812 */
/* 0x000fe200078ec0ff */
/*0820*/ FFMA.RP R10, R18, R16, R15 ; /* 0x00000010120a7223 */
/* 0x000fe2000000800f */
/*0830*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25270 */
/*0840*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*0850*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0860*/ FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x000fc40003f1d000 */
/*0870*/ SHF.L.U32 R13, R12, R13, RZ ; /* 0x0000000d0c0d7219 */
/* 0x000fe400000006ff */
/*0880*/ SEL R11, R14, RZ, P3 ; /* 0x000000ff0e0b7207 */
/* 0x000fe40001800000 */
/*0890*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*08a0*/ SHF.R.U32.HI R11, RZ, R11, R12 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160c */
/*08b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*08c0*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fc4000001160b */
/*08d0*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fc80004000000 */
/*08e0*/ LOP3.LUT R10, R10, 0x1, R13, 0xf8, !PT ; /* 0x000000010a0a7812 */
/* 0x000fc800078ef80d */
/*08f0*/ LOP3.LUT R10, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fca00078ec0ff */
/*0900*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fca00078e020a */
/*0910*/ LOP3.LUT R9, R10, R9, RZ, 0xfc, !PT ; /* 0x000000090a097212 */
/* 0x000fe200078efcff */
/*0920*/ BRA 0x970 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0930*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0940*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ IMAD R9, R10, 0x800000, R9 ; /* 0x008000000a097824 */
/* 0x000fe400078e0209 */
/*0970*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0980*/ BRA 0xa10 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fc800078e4809 */
/*09a0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*09b0*/ BRA 0xa10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09c0*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078e4809 */
/*09d0*/ BRA 0xa10 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*09e0*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*09f0*/ BRA 0xa10 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a00*/ FADD.FTZ R9, R13, R12 ; /* 0x0000000c0d097221 */
/* 0x000fe40000010000 */
/*0a10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a20*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x001fe400078e0009 */
/*0a30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0a40*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff5b008007950 */
/* 0x000fea0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17create_fpr_kernelPfPKiS_ii
.globl _Z17create_fpr_kernelPfPKiS_ii
.p2align 8
.type _Z17create_fpr_kernelPfPKiS_ii,@function
_Z17create_fpr_kernelPfPKiS_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
s_load_b32 s13, s[0:1], 0x1c
s_lshl_b64 s[14:15], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s14
s_addc_u32 s1, s5, s15
s_add_u32 s0, s0, -4
s_addc_u32 s1, s1, -1
v_cvt_f32_i32_e32 v0, s13
s_load_b32 s3, s[0:1], 0x0
s_load_b32 s10, s[10:11], 0x0
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
v_subrev_f32_e32 v0, s3, v0
s_mul_i32 s10, s10, s12
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_cmp_le_i32_e64 s1, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
s_or_b32 s11, s1, s11
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v6, v6
s_waitcnt vmcnt(0)
v_div_scale_f32 v9, null, s3, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v9, v11, 1.0
v_dual_add_f32 v6, 1.0, v6 :: v_dual_fmac_f32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_div_scale_f32 v8, null, v0, v0, v6
v_div_scale_f32 v14, vcc_lo, v6, v0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v8, v10, 1.0
v_fmac_f32_e32 v10, v12, v10
v_div_scale_f32 v12, s0, v7, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v12, v11
v_fma_f32 v17, -v9, v15, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v15, v17, v11
v_mul_f32_e32 v13, v14, v10
v_fma_f32 v9, -v9, v15, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v8, v13, v14
v_fmac_f32_e32 v13, v16, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v13, v14
v_div_fmas_f32 v8, v8, v10, v13
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v9, v9, v11, v15
v_add_co_u32 v2, vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v6, v8, v0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_div_fixup_f32 v7, v9, s3, v7
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17create_fpr_kernelPfPKiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17create_fpr_kernelPfPKiS_ii, .Lfunc_end0-_Z17create_fpr_kernelPfPKiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17create_fpr_kernelPfPKiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17create_fpr_kernelPfPKiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001983d6_00000000-6_create_fpr_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
.type _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii, @function
_Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17create_fpr_kernelPfPKiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii, .-_Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
.globl _Z17create_fpr_kernelPfPKiS_ii
.type _Z17create_fpr_kernelPfPKiS_ii, @function
_Z17create_fpr_kernelPfPKiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17create_fpr_kernelPfPKiS_iiPfPKiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17create_fpr_kernelPfPKiS_ii, .-_Z17create_fpr_kernelPfPKiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17create_fpr_kernelPfPKiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17create_fpr_kernelPfPKiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "create_fpr_kernel.hip"
.globl _Z32__device_stub__create_fpr_kernelPfPKiS_ii # -- Begin function _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.p2align 4, 0x90
.type _Z32__device_stub__create_fpr_kernelPfPKiS_ii,@function
_Z32__device_stub__create_fpr_kernelPfPKiS_ii: # @_Z32__device_stub__create_fpr_kernelPfPKiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17create_fpr_kernelPfPKiS_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__create_fpr_kernelPfPKiS_ii, .Lfunc_end0-_Z32__device_stub__create_fpr_kernelPfPKiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17create_fpr_kernelPfPKiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17create_fpr_kernelPfPKiS_ii,@object # @_Z17create_fpr_kernelPfPKiS_ii
.section .rodata,"a",@progbits
.globl _Z17create_fpr_kernelPfPKiS_ii
.p2align 3, 0x0
_Z17create_fpr_kernelPfPKiS_ii:
.quad _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.size _Z17create_fpr_kernelPfPKiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17create_fpr_kernelPfPKiS_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__create_fpr_kernelPfPKiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17create_fpr_kernelPfPKiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Includes for IntelliSense
#define _SIZE_T_DEFINED
#include <cuda.h>
#include <curand_kernel.h>
#include <device_launch_parameters.h>
#include "float.h"
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#define PI acos(-1.0)
extern "C"{
// Write coefficients back into the matrix, ready for fitness evaluation/ Inverse DCT
__global__ void implantCoeffs(float* matrices, float *coeffArray, int savedCoeffs, int dimsize){
int id = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = id * dimsize * dimsize,
offsetCoeff = id * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
matrices[offsetMatrix] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1){
numberinrow = x_n + 1;
}
else{
numberinrow = x_n - (y_n - 1);
}
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Creates a square cosine matrix and its inverse
__global__ void createCosineMatrix(float* matrix, int xsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int i;
for (i = 0; i < xsize; i++){
if (threadGlobalID == 0)
matrix[threadGlobalID + i * xsize] = 1 / sqrt((float)xsize);
else
matrix[threadGlobalID + i * xsize] = (sqrt((float)2 / xsize) * cos((PI * (2 * i + 1) * threadGlobalID) / (2 * xsize)));
}
}
// This is obscenely complex for something so seemingly simple
// Each thread, extracts savedCoeffs from a matrix, assumes square martix
__global__ void extractCoeffs(const float *matrices, float *coeffArray, int savedCoeffs, int dimsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = threadGlobalID * dimsize * dimsize,
offsetCoeff = threadGlobalID * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1)
numberinrow = x_n + 1;
else
numberinrow = x_n - (y_n - 1);
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Generates chromSize random numbers between alpha and -alpha and stores them in the chromosomes array
__global__ void generateCoefficients(float *chromosomes, const int chromSize, const float* noise, const int population, const int alpha){
int i;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
curandState st;
curand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
if (threadGlobalID > 0){
for (i = 0; i < chromSize; i++){
if (curand_uniform(&st) < 0.5){
chromosomes[chromSize*threadGlobalID + i] = curand_uniform(&st) *alpha;
}
else{
chromosomes[chromSize*threadGlobalID + i] = -1 * curand_uniform(&st) * alpha;
}
}
}
}
// Performs the CoSyNE genetic algorithm.
// -- Replace all non-survivors with crossover from two random parents
// -- Randomly mutate the new population members
// -- Permute the genes of the chromosome population
__global__ void grow(float *matrices, const int dimension, const int coefficients, const int population, float *chromosomes, const float * noise, const float mutationRate, const int kept, const float* fitnesses, int *mark, const int alpha){
int i, wloc;
curandState st;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int chromOffset = threadGlobalID * coefficients;
int parent1, parent2, point;
float tmp1, tmp2;
// Init the random number generator
curand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
// Repopulate
// The threads with the keepmask are kept, all others are replaced with crossovers
if (threadGlobalID > kept - 1){
// pick two parents -- 0 is not included in the random distribution
parent1 = floor(curand_uniform(&st) * kept);
parent2 = floor(curand_uniform(&st) * kept);
//pick a point on the chromosome
point = floor(curand_uniform(&st) * coefficients);
for (i = 0; i < point; i++){
chromosomes[chromOffset + i] = chromosomes[parent1 * coefficients + i];
}
//Copy past the point for parent 2
for (i = point; i < coefficients; i++){
chromosomes[chromOffset + i] = chromosomes[parent2 * coefficients + i];
}
}
// Mutate children
if (threadGlobalID > kept - 1){
for (i = 0; i < coefficients; i++){
if (curand_uniform(&st) <= mutationRate){
if (curand_uniform(&st) < 0.5){
chromosomes[chromOffset + i] = curand_uniform(&st) * -1 * alpha;
}
else{
chromosomes[chromOffset + i] = curand_uniform(&st) * alpha;
}
}
}
}
// Permute
if (threadGlobalID < coefficients){
// Mark genes for permutation
for (i = 0; i < population; i++){
if (curand_uniform(&st) < (1 - sqrt((fitnesses[i] - fitnesses[population - 1]) / (fitnesses[0] - fitnesses[population - 1])))){
mark[coefficients * i + threadGlobalID] = 1;
}
else{
mark[coefficients * i + threadGlobalID] = 0;
}
}
wloc = -1;
// Permute selected genes
for (i = 0; i < population; i++){
if (mark[coefficients * i + threadGlobalID] == 1){
if (wloc == -1){
wloc = i;
tmp1 = chromosomes[coefficients * i + threadGlobalID];
}
else{
tmp2 = chromosomes[coefficients * i + threadGlobalID];
chromosomes[coefficients * i + threadGlobalID] = tmp1;
tmp1 = tmp2;
}
}
}
if (wloc != -1){
chromosomes[coefficients * wloc + threadGlobalID] = tmp1;
}
}
__syncthreads();
//Place into relevant matrix
for (i = 0; i < dimension*dimension; i++){
matrices[threadGlobalID * dimension * dimension + i] = 0.0f;
}
}
} | .file "tmpxft_00122b23_00000000-6_CosyneGenetics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
.type _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii, @function
_Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii:
.LFB2295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq implantCoeffs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii, .-_Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
.globl implantCoeffs
.type implantCoeffs, @function
implantCoeffs:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size implantCoeffs, .-implantCoeffs
.globl _Z39__device_stub__Z18createCosineMatrixPfiPfi
.type _Z39__device_stub__Z18createCosineMatrixPfiPfi, @function
_Z39__device_stub__Z18createCosineMatrixPfiPfi:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq createCosineMatrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z39__device_stub__Z18createCosineMatrixPfiPfi, .-_Z39__device_stub__Z18createCosineMatrixPfiPfi
.globl createCosineMatrix
.type createCosineMatrix, @function
createCosineMatrix:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18createCosineMatrixPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size createCosineMatrix, .-createCosineMatrix
.globl _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
.type _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii, @function
_Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii:
.LFB2299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq extractCoeffs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii, .-_Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
.globl extractCoeffs
.type extractCoeffs, @function
extractCoeffs:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size extractCoeffs, .-extractCoeffs
.globl _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
.type _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii, @function
_Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii:
.LFB2301:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq generateCoefficients(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii, .-_Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
.globl generateCoefficients
.type generateCoefficients, @function
generateCoefficients:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size generateCoefficients, .-generateCoefficients
.globl _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
.type _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii, @function
_Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii:
.LFB2303:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 40(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq grow(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii, .-_Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
.globl grow
.type grow, @function
grow:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size grow, .-grow
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grow"
.LC1:
.string "generateCoefficients"
.LC2:
.string "extractCoeffs"
.LC3:
.string "createCosineMatrix"
.LC4:
.string "implantCoeffs"
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2306:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq grow(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq generateCoefficients(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq extractCoeffs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq createCosineMatrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq implantCoeffs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Includes for IntelliSense
#define _SIZE_T_DEFINED
#include <cuda.h>
#include <curand_kernel.h>
#include <device_launch_parameters.h>
#include "float.h"
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#define PI acos(-1.0)
extern "C"{
// Write coefficients back into the matrix, ready for fitness evaluation/ Inverse DCT
__global__ void implantCoeffs(float* matrices, float *coeffArray, int savedCoeffs, int dimsize){
int id = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = id * dimsize * dimsize,
offsetCoeff = id * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
matrices[offsetMatrix] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1){
numberinrow = x_n + 1;
}
else{
numberinrow = x_n - (y_n - 1);
}
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Creates a square cosine matrix and its inverse
__global__ void createCosineMatrix(float* matrix, int xsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int i;
for (i = 0; i < xsize; i++){
if (threadGlobalID == 0)
matrix[threadGlobalID + i * xsize] = 1 / sqrt((float)xsize);
else
matrix[threadGlobalID + i * xsize] = (sqrt((float)2 / xsize) * cos((PI * (2 * i + 1) * threadGlobalID) / (2 * xsize)));
}
}
// This is obscenely complex for something so seemingly simple
// Each thread, extracts savedCoeffs from a matrix, assumes square martix
__global__ void extractCoeffs(const float *matrices, float *coeffArray, int savedCoeffs, int dimsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = threadGlobalID * dimsize * dimsize,
offsetCoeff = threadGlobalID * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1)
numberinrow = x_n + 1;
else
numberinrow = x_n - (y_n - 1);
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Generates chromSize random numbers between alpha and -alpha and stores them in the chromosomes array
__global__ void generateCoefficients(float *chromosomes, const int chromSize, const float* noise, const int population, const int alpha){
int i;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
curandState st;
curand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
if (threadGlobalID > 0){
for (i = 0; i < chromSize; i++){
if (curand_uniform(&st) < 0.5){
chromosomes[chromSize*threadGlobalID + i] = curand_uniform(&st) *alpha;
}
else{
chromosomes[chromSize*threadGlobalID + i] = -1 * curand_uniform(&st) * alpha;
}
}
}
}
// Performs the CoSyNE genetic algorithm.
// -- Replace all non-survivors with crossover from two random parents
// -- Randomly mutate the new population members
// -- Permute the genes of the chromosome population
__global__ void grow(float *matrices, const int dimension, const int coefficients, const int population, float *chromosomes, const float * noise, const float mutationRate, const int kept, const float* fitnesses, int *mark, const int alpha){
int i, wloc;
curandState st;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int chromOffset = threadGlobalID * coefficients;
int parent1, parent2, point;
float tmp1, tmp2;
// Init the random number generator
curand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
// Repopulate
// The threads with the keepmask are kept, all others are replaced with crossovers
if (threadGlobalID > kept - 1){
// pick two parents -- 0 is not included in the random distribution
parent1 = floor(curand_uniform(&st) * kept);
parent2 = floor(curand_uniform(&st) * kept);
//pick a point on the chromosome
point = floor(curand_uniform(&st) * coefficients);
for (i = 0; i < point; i++){
chromosomes[chromOffset + i] = chromosomes[parent1 * coefficients + i];
}
//Copy past the point for parent 2
for (i = point; i < coefficients; i++){
chromosomes[chromOffset + i] = chromosomes[parent2 * coefficients + i];
}
}
// Mutate children
if (threadGlobalID > kept - 1){
for (i = 0; i < coefficients; i++){
if (curand_uniform(&st) <= mutationRate){
if (curand_uniform(&st) < 0.5){
chromosomes[chromOffset + i] = curand_uniform(&st) * -1 * alpha;
}
else{
chromosomes[chromOffset + i] = curand_uniform(&st) * alpha;
}
}
}
}
// Permute
if (threadGlobalID < coefficients){
// Mark genes for permutation
for (i = 0; i < population; i++){
if (curand_uniform(&st) < (1 - sqrt((fitnesses[i] - fitnesses[population - 1]) / (fitnesses[0] - fitnesses[population - 1])))){
mark[coefficients * i + threadGlobalID] = 1;
}
else{
mark[coefficients * i + threadGlobalID] = 0;
}
}
wloc = -1;
// Permute selected genes
for (i = 0; i < population; i++){
if (mark[coefficients * i + threadGlobalID] == 1){
if (wloc == -1){
wloc = i;
tmp1 = chromosomes[coefficients * i + threadGlobalID];
}
else{
tmp2 = chromosomes[coefficients * i + threadGlobalID];
chromosomes[coefficients * i + threadGlobalID] = tmp1;
tmp1 = tmp2;
}
}
}
if (wloc != -1){
chromosomes[coefficients * wloc + threadGlobalID] = tmp1;
}
}
__syncthreads();
//Place into relevant matrix
for (i = 0; i < dimension*dimension; i++){
matrices[threadGlobalID * dimension * dimension + i] = 0.0f;
}
}
} | //Includes for IntelliSense
#define _SIZE_T_DEFINED
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include "float.h"
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#define PI acos(-1.0)
extern "C"{
// Write coefficients back into the matrix, ready for fitness evaluation/ Inverse DCT
__global__ void implantCoeffs(float* matrices, float *coeffArray, int savedCoeffs, int dimsize){
int id = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = id * dimsize * dimsize,
offsetCoeff = id * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
matrices[offsetMatrix] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1){
numberinrow = x_n + 1;
}
else{
numberinrow = x_n - (y_n - 1);
}
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Creates a square cosine matrix and its inverse
__global__ void createCosineMatrix(float* matrix, int xsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int i;
for (i = 0; i < xsize; i++){
if (threadGlobalID == 0)
matrix[threadGlobalID + i * xsize] = 1 / sqrt((float)xsize);
else
matrix[threadGlobalID + i * xsize] = (sqrt((float)2 / xsize) * cos((PI * (2 * i + 1) * threadGlobalID) / (2 * xsize)));
}
}
// This is obscenely complex for something so seemingly simple
// Each thread, extracts savedCoeffs from a matrix, assumes square martix
__global__ void extractCoeffs(const float *matrices, float *coeffArray, int savedCoeffs, int dimsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = threadGlobalID * dimsize * dimsize,
offsetCoeff = threadGlobalID * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1)
numberinrow = x_n + 1;
else
numberinrow = x_n - (y_n - 1);
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Generates chromSize random numbers between alpha and -alpha and stores them in the chromosomes array
__global__ void generateCoefficients(float *chromosomes, const int chromSize, const float* noise, const int population, const int alpha){
int i;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
hiprandState st;
hiprand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
if (threadGlobalID > 0){
for (i = 0; i < chromSize; i++){
if (hiprand_uniform(&st) < 0.5){
chromosomes[chromSize*threadGlobalID + i] = hiprand_uniform(&st) *alpha;
}
else{
chromosomes[chromSize*threadGlobalID + i] = -1 * hiprand_uniform(&st) * alpha;
}
}
}
}
// Performs the CoSyNE genetic algorithm.
// -- Replace all non-survivors with crossover from two random parents
// -- Randomly mutate the new population members
// -- Permute the genes of the chromosome population
__global__ void grow(float *matrices, const int dimension, const int coefficients, const int population, float *chromosomes, const float * noise, const float mutationRate, const int kept, const float* fitnesses, int *mark, const int alpha){
int i, wloc;
hiprandState st;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int chromOffset = threadGlobalID * coefficients;
int parent1, parent2, point;
float tmp1, tmp2;
// Init the random number generator
hiprand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
// Repopulate
// The threads with the keepmask are kept, all others are replaced with crossovers
if (threadGlobalID > kept - 1){
// pick two parents -- 0 is not included in the random distribution
parent1 = floor(hiprand_uniform(&st) * kept);
parent2 = floor(hiprand_uniform(&st) * kept);
//pick a point on the chromosome
point = floor(hiprand_uniform(&st) * coefficients);
for (i = 0; i < point; i++){
chromosomes[chromOffset + i] = chromosomes[parent1 * coefficients + i];
}
//Copy past the point for parent 2
for (i = point; i < coefficients; i++){
chromosomes[chromOffset + i] = chromosomes[parent2 * coefficients + i];
}
}
// Mutate children
if (threadGlobalID > kept - 1){
for (i = 0; i < coefficients; i++){
if (hiprand_uniform(&st) <= mutationRate){
if (hiprand_uniform(&st) < 0.5){
chromosomes[chromOffset + i] = hiprand_uniform(&st) * -1 * alpha;
}
else{
chromosomes[chromOffset + i] = hiprand_uniform(&st) * alpha;
}
}
}
}
// Permute
if (threadGlobalID < coefficients){
// Mark genes for permutation
for (i = 0; i < population; i++){
if (hiprand_uniform(&st) < (1 - sqrt((fitnesses[i] - fitnesses[population - 1]) / (fitnesses[0] - fitnesses[population - 1])))){
mark[coefficients * i + threadGlobalID] = 1;
}
else{
mark[coefficients * i + threadGlobalID] = 0;
}
}
wloc = -1;
// Permute selected genes
for (i = 0; i < population; i++){
if (mark[coefficients * i + threadGlobalID] == 1){
if (wloc == -1){
wloc = i;
tmp1 = chromosomes[coefficients * i + threadGlobalID];
}
else{
tmp2 = chromosomes[coefficients * i + threadGlobalID];
chromosomes[coefficients * i + threadGlobalID] = tmp1;
tmp1 = tmp2;
}
}
}
if (wloc != -1){
chromosomes[coefficients * wloc + threadGlobalID] = tmp1;
}
}
__syncthreads();
//Place into relevant matrix
for (i = 0; i < dimension*dimension; i++){
matrices[threadGlobalID * dimension * dimension + i] = 0.0f;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Includes for IntelliSense
#define _SIZE_T_DEFINED
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include "float.h"
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#define PI acos(-1.0)
extern "C"{
// Write coefficients back into the matrix, ready for fitness evaluation/ Inverse DCT
__global__ void implantCoeffs(float* matrices, float *coeffArray, int savedCoeffs, int dimsize){
int id = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = id * dimsize * dimsize,
offsetCoeff = id * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
matrices[offsetMatrix] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1){
numberinrow = x_n + 1;
}
else{
numberinrow = x_n - (y_n - 1);
}
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
matrices[offsetMatrix + x + y * dimsize] = coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Creates a square cosine matrix and its inverse
__global__ void createCosineMatrix(float* matrix, int xsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int i;
for (i = 0; i < xsize; i++){
if (threadGlobalID == 0)
matrix[threadGlobalID + i * xsize] = 1 / sqrt((float)xsize);
else
matrix[threadGlobalID + i * xsize] = (sqrt((float)2 / xsize) * cos((PI * (2 * i + 1) * threadGlobalID) / (2 * xsize)));
}
}
// This is obscenely complex for something so seemingly simple
// Each thread, extracts savedCoeffs from a matrix, assumes square martix
__global__ void extractCoeffs(const float *matrices, float *coeffArray, int savedCoeffs, int dimsize){
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int offsetMatrix = threadGlobalID * dimsize * dimsize,
offsetCoeff = threadGlobalID * savedCoeffs,
coeffsLeft = savedCoeffs,
x, y, y_n = 0, x_n = 1,
numberinrow, tmp;
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix];
coeffsLeft -= 1;
while (coeffsLeft > 0){
// Work out number in row
x = x_n;
y = y_n;
if (x_n < dimsize - 1)
numberinrow = x_n + 1;
else
numberinrow = x_n - (y_n - 1);
if (numberinrow % 2 == 0){
// Even
while (numberinrow > 0 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 0){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
}
else{
// Odd
while (numberinrow > 1 && coeffsLeft > 0){
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
if ((numberinrow + 1) % 2 == 1){
// Swap x and y
tmp = x;
x = y;
y = tmp;
}
else{
// Swap x and y
tmp = x;
x = y;
y = tmp;
x--;
y++;
}
}
if (coeffsLeft > 0){
// add the odd one
coeffArray[offsetCoeff + (savedCoeffs - coeffsLeft)] = matrices[offsetMatrix + x + y * dimsize];
numberinrow--;
coeffsLeft--;
}
}
if (x_n == dimsize - 1){
y_n++;
}
else{
x_n++;
}
}
}
// Generates chromSize random numbers between alpha and -alpha and stores them in the chromosomes array
__global__ void generateCoefficients(float *chromosomes, const int chromSize, const float* noise, const int population, const int alpha){
int i;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
hiprandState st;
hiprand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
if (threadGlobalID > 0){
for (i = 0; i < chromSize; i++){
if (hiprand_uniform(&st) < 0.5){
chromosomes[chromSize*threadGlobalID + i] = hiprand_uniform(&st) *alpha;
}
else{
chromosomes[chromSize*threadGlobalID + i] = -1 * hiprand_uniform(&st) * alpha;
}
}
}
}
// Performs the CoSyNE genetic algorithm.
// -- Replace all non-survivors with crossover from two random parents
// -- Randomly mutate the new population members
// -- Permute the genes of the chromosome population
__global__ void grow(float *matrices, const int dimension, const int coefficients, const int population, float *chromosomes, const float * noise, const float mutationRate, const int kept, const float* fitnesses, int *mark, const int alpha){
int i, wloc;
hiprandState st;
// For up to a 1D grid of 3D blocks...
int threadGlobalID = blockIdx.x * blockDim.x * blockDim.y * blockDim.z
+ threadIdx.z * blockDim.y * blockDim.x + threadIdx.y * blockDim.x + threadIdx.x;
int chromOffset = threadGlobalID * coefficients;
int parent1, parent2, point;
float tmp1, tmp2;
// Init the random number generator
hiprand_init((int)noise[threadGlobalID] << threadGlobalID, threadGlobalID * (threadGlobalID == population - 1 ? noise[0] : noise[threadGlobalID]), 0, &st);
// Repopulate
// The threads with the keepmask are kept, all others are replaced with crossovers
if (threadGlobalID > kept - 1){
// pick two parents -- 0 is not included in the random distribution
parent1 = floor(hiprand_uniform(&st) * kept);
parent2 = floor(hiprand_uniform(&st) * kept);
//pick a point on the chromosome
point = floor(hiprand_uniform(&st) * coefficients);
for (i = 0; i < point; i++){
chromosomes[chromOffset + i] = chromosomes[parent1 * coefficients + i];
}
//Copy past the point for parent 2
for (i = point; i < coefficients; i++){
chromosomes[chromOffset + i] = chromosomes[parent2 * coefficients + i];
}
}
// Mutate children
if (threadGlobalID > kept - 1){
for (i = 0; i < coefficients; i++){
if (hiprand_uniform(&st) <= mutationRate){
if (hiprand_uniform(&st) < 0.5){
chromosomes[chromOffset + i] = hiprand_uniform(&st) * -1 * alpha;
}
else{
chromosomes[chromOffset + i] = hiprand_uniform(&st) * alpha;
}
}
}
}
// Permute
if (threadGlobalID < coefficients){
// Mark genes for permutation
for (i = 0; i < population; i++){
if (hiprand_uniform(&st) < (1 - sqrt((fitnesses[i] - fitnesses[population - 1]) / (fitnesses[0] - fitnesses[population - 1])))){
mark[coefficients * i + threadGlobalID] = 1;
}
else{
mark[coefficients * i + threadGlobalID] = 0;
}
}
wloc = -1;
// Permute selected genes
for (i = 0; i < population; i++){
if (mark[coefficients * i + threadGlobalID] == 1){
if (wloc == -1){
wloc = i;
tmp1 = chromosomes[coefficients * i + threadGlobalID];
}
else{
tmp2 = chromosomes[coefficients * i + threadGlobalID];
chromosomes[coefficients * i + threadGlobalID] = tmp1;
tmp1 = tmp2;
}
}
}
if (wloc != -1){
chromosomes[coefficients * wloc + threadGlobalID] = tmp1;
}
}
__syncthreads();
//Place into relevant matrix
for (i = 0; i < dimension*dimension; i++){
matrices[threadGlobalID * dimension * dimension + i] = 0.0f;
}
}
} | .text
.file "CosyneGenetics.hip"
.globl __device_stub__implantCoeffs # -- Begin function __device_stub__implantCoeffs
.p2align 4, 0x90
.type __device_stub__implantCoeffs,@function
__device_stub__implantCoeffs: # @__device_stub__implantCoeffs
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $implantCoeffs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__implantCoeffs, .Lfunc_end0-__device_stub__implantCoeffs
.cfi_endproc
# -- End function
.globl __device_stub__createCosineMatrix # -- Begin function __device_stub__createCosineMatrix
.p2align 4, 0x90
.type __device_stub__createCosineMatrix,@function
__device_stub__createCosineMatrix: # @__device_stub__createCosineMatrix
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $createCosineMatrix, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__createCosineMatrix, .Lfunc_end1-__device_stub__createCosineMatrix
.cfi_endproc
# -- End function
.globl __device_stub__extractCoeffs # -- Begin function __device_stub__extractCoeffs
.p2align 4, 0x90
.type __device_stub__extractCoeffs,@function
__device_stub__extractCoeffs: # @__device_stub__extractCoeffs
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $extractCoeffs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__extractCoeffs, .Lfunc_end2-__device_stub__extractCoeffs
.cfi_endproc
# -- End function
.globl __device_stub__generateCoefficients # -- Begin function __device_stub__generateCoefficients
.p2align 4, 0x90
.type __device_stub__generateCoefficients,@function
__device_stub__generateCoefficients: # @__device_stub__generateCoefficients
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $generateCoefficients, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__generateCoefficients, .Lfunc_end3-__device_stub__generateCoefficients
.cfi_endproc
# -- End function
.globl __device_stub__grow # -- Begin function __device_stub__grow
.p2align 4, 0x90
.type __device_stub__grow,@function
__device_stub__grow: # @__device_stub__grow
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 192(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $grow, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end4:
.size __device_stub__grow, .Lfunc_end4-__device_stub__grow
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $implantCoeffs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $createCosineMatrix, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $extractCoeffs, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $generateCoefficients, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $grow, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type implantCoeffs,@object # @implantCoeffs
.section .rodata,"a",@progbits
.globl implantCoeffs
.p2align 3, 0x0
implantCoeffs:
.quad __device_stub__implantCoeffs
.size implantCoeffs, 8
.type createCosineMatrix,@object # @createCosineMatrix
.globl createCosineMatrix
.p2align 3, 0x0
createCosineMatrix:
.quad __device_stub__createCosineMatrix
.size createCosineMatrix, 8
.type extractCoeffs,@object # @extractCoeffs
.globl extractCoeffs
.p2align 3, 0x0
extractCoeffs:
.quad __device_stub__extractCoeffs
.size extractCoeffs, 8
.type generateCoefficients,@object # @generateCoefficients
.globl generateCoefficients
.p2align 3, 0x0
generateCoefficients:
.quad __device_stub__generateCoefficients
.size generateCoefficients, 8
.type grow,@object # @grow
.globl grow
.p2align 3, 0x0
grow:
.quad __device_stub__grow
.size grow, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "implantCoeffs"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "createCosineMatrix"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "extractCoeffs"
.size .L__unnamed_3, 14
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "generateCoefficients"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "grow"
.size .L__unnamed_5, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__implantCoeffs
.addrsig_sym __device_stub__createCosineMatrix
.addrsig_sym __device_stub__extractCoeffs
.addrsig_sym __device_stub__generateCoefficients
.addrsig_sym __device_stub__grow
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym implantCoeffs
.addrsig_sym createCosineMatrix
.addrsig_sym extractCoeffs
.addrsig_sym generateCoefficients
.addrsig_sym grow
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122b23_00000000-6_CosyneGenetics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
.type _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii, @function
_Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii:
.LFB2295:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq implantCoeffs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii, .-_Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
.globl implantCoeffs
.type implantCoeffs, @function
implantCoeffs:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13implantCoeffsPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size implantCoeffs, .-implantCoeffs
.globl _Z39__device_stub__Z18createCosineMatrixPfiPfi
.type _Z39__device_stub__Z18createCosineMatrixPfiPfi, @function
_Z39__device_stub__Z18createCosineMatrixPfiPfi:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq createCosineMatrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z39__device_stub__Z18createCosineMatrixPfiPfi, .-_Z39__device_stub__Z18createCosineMatrixPfiPfi
.globl createCosineMatrix
.type createCosineMatrix, @function
createCosineMatrix:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z18createCosineMatrixPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size createCosineMatrix, .-createCosineMatrix
.globl _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
.type _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii, @function
_Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii:
.LFB2299:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq extractCoeffs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii, .-_Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
.globl extractCoeffs
.type extractCoeffs, @function
extractCoeffs:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13extractCoeffsPKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size extractCoeffs, .-extractCoeffs
.globl _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
.type _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii, @function
_Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii:
.LFB2301:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq generateCoefficients(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii, .-_Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
.globl generateCoefficients
.type generateCoefficients, @function
generateCoefficients:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z20generateCoefficientsPfiPKfiiPfiPKfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size generateCoefficients, .-generateCoefficients
.globl _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
.type _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii, @function
_Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii:
.LFB2303:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movl %ecx, 44(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 40(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq grow(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii, .-_Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
.globl grow
.type grow, @function
grow:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z39__device_stub__Z4growPfiiiS_PKffiS1_PiiPfiiiS_PKffiS1_Pii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size grow, .-grow
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "grow"
.LC1:
.string "generateCoefficients"
.LC2:
.string "extractCoeffs"
.LC3:
.string "createCosineMatrix"
.LC4:
.string "implantCoeffs"
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2306:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq grow(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq generateCoefficients(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq extractCoeffs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq createCosineMatrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq implantCoeffs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CosyneGenetics.hip"
.globl __device_stub__implantCoeffs # -- Begin function __device_stub__implantCoeffs
.p2align 4, 0x90
.type __device_stub__implantCoeffs,@function
__device_stub__implantCoeffs: # @__device_stub__implantCoeffs
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $implantCoeffs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__implantCoeffs, .Lfunc_end0-__device_stub__implantCoeffs
.cfi_endproc
# -- End function
.globl __device_stub__createCosineMatrix # -- Begin function __device_stub__createCosineMatrix
.p2align 4, 0x90
.type __device_stub__createCosineMatrix,@function
__device_stub__createCosineMatrix: # @__device_stub__createCosineMatrix
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $createCosineMatrix, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size __device_stub__createCosineMatrix, .Lfunc_end1-__device_stub__createCosineMatrix
.cfi_endproc
# -- End function
.globl __device_stub__extractCoeffs # -- Begin function __device_stub__extractCoeffs
.p2align 4, 0x90
.type __device_stub__extractCoeffs,@function
__device_stub__extractCoeffs: # @__device_stub__extractCoeffs
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $extractCoeffs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__extractCoeffs, .Lfunc_end2-__device_stub__extractCoeffs
.cfi_endproc
# -- End function
.globl __device_stub__generateCoefficients # -- Begin function __device_stub__generateCoefficients
.p2align 4, 0x90
.type __device_stub__generateCoefficients,@function
__device_stub__generateCoefficients: # @__device_stub__generateCoefficients
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $generateCoefficients, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__generateCoefficients, .Lfunc_end3-__device_stub__generateCoefficients
.cfi_endproc
# -- End function
.globl __device_stub__grow # -- Begin function __device_stub__grow
.p2align 4, 0x90
.type __device_stub__grow,@function
__device_stub__grow: # @__device_stub__grow
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 192(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $grow, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end4:
.size __device_stub__grow, .Lfunc_end4-__device_stub__grow
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $implantCoeffs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $createCosineMatrix, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $extractCoeffs, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $generateCoefficients, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $grow, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type implantCoeffs,@object # @implantCoeffs
.section .rodata,"a",@progbits
.globl implantCoeffs
.p2align 3, 0x0
implantCoeffs:
.quad __device_stub__implantCoeffs
.size implantCoeffs, 8
.type createCosineMatrix,@object # @createCosineMatrix
.globl createCosineMatrix
.p2align 3, 0x0
createCosineMatrix:
.quad __device_stub__createCosineMatrix
.size createCosineMatrix, 8
.type extractCoeffs,@object # @extractCoeffs
.globl extractCoeffs
.p2align 3, 0x0
extractCoeffs:
.quad __device_stub__extractCoeffs
.size extractCoeffs, 8
.type generateCoefficients,@object # @generateCoefficients
.globl generateCoefficients
.p2align 3, 0x0
generateCoefficients:
.quad __device_stub__generateCoefficients
.size generateCoefficients, 8
.type grow,@object # @grow
.globl grow
.p2align 3, 0x0
grow:
.quad __device_stub__grow
.size grow, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "implantCoeffs"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "createCosineMatrix"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "extractCoeffs"
.size .L__unnamed_3, 14
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "generateCoefficients"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "grow"
.size .L__unnamed_5, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__implantCoeffs
.addrsig_sym __device_stub__createCosineMatrix
.addrsig_sym __device_stub__extractCoeffs
.addrsig_sym __device_stub__generateCoefficients
.addrsig_sym __device_stub__grow
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym implantCoeffs
.addrsig_sym createCosineMatrix
.addrsig_sym extractCoeffs
.addrsig_sym generateCoefficients
.addrsig_sym grow
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void compute_d_w_kernel(float *v, float *h, float *dw, bool is_init, int input_size, int lu_padding, int channel_num, int filter_num, int filter_size, int feature_map_size){
int imgIdx = blockIdx.y / (feature_map_size / 32);
int filterIdx = blockIdx.x / (channel_num * feature_map_size / 32);
int channelIdx = (blockIdx.x % (channel_num * feature_map_size / 32)) /
(feature_map_size / 32);
int tx = (blockIdx.x % (channel_num * feature_map_size / 32)) %
(feature_map_size / 32) *32 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / 32)) * 32 + threadIdx.y;
__shared__ float shV[32+MAX_FILETER_SIZE][32+MAX_FILETER_SIZE];
__shared__ float shH[32][32];
float sign;
if(is_init){
sign = 1.0f;
}else{
sign = -1.0f;
}
v = v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;
h = h + imgIdx * filter_num * feature_map_size * feature_map_size +
filterIdx * feature_map_size * feature_map_size;
dw = dw + filterIdx * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;
float local_dw = 0.0f;
for(int loadX = 0; loadX <= 32; loadX += filter_size){
for(int loadY = 0; loadY <= 32; loadY += filter_size){
if(loadX < 32 && loadY < 32){
//TODO:feature map overflow
shH[threadIdx.y+loadY][threadIdx.x+loadX] =
h[(ty+loadY)*feature_map_size + (tx+loadX)];
}
if((tx+loadX) < lu_padding ||
(ty+loadY) < lu_padding ||
(tx+loadX) >= (input_size+lu_padding) ||
(ty+loadY) >= (input_size+lu_padding)){
shV[threadIdx.y+loadY][threadIdx.x+loadX] = 0;
}else{
shV[threadIdx.y+loadY][threadIdx.x+loadX] =
v[(ty+loadY-lu_padding)*input_size + (tx+loadX-lu_padding)];
}
}
}
__syncthreads();
for(int i = 0; i < 32; i++){
for(int j = 0; j < 32; j++){
local_dw += shV[threadIdx.y+i][threadIdx.x+j] *
shH[i][j];
}
}
atomicAdd(dw + threadIdx.y*filter_size + threadIdx.x, sign * local_dw);
} | .file "tmpxft_001805ab_00000000-6_compute_d_w_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
.type _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii, @function
_Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movb %cl, 20(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18compute_d_w_kernelPfS_S_biiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii, .-_Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
.globl _Z18compute_d_w_kernelPfS_S_biiiiii
.type _Z18compute_d_w_kernelPfS_S_biiiiii, @function
_Z18compute_d_w_kernelPfS_S_biiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18compute_d_w_kernelPfS_S_biiiiii, .-_Z18compute_d_w_kernelPfS_S_biiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18compute_d_w_kernelPfS_S_biiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compute_d_w_kernelPfS_S_biiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void compute_d_w_kernel(float *v, float *h, float *dw, bool is_init, int input_size, int lu_padding, int channel_num, int filter_num, int filter_size, int feature_map_size){
int imgIdx = blockIdx.y / (feature_map_size / 32);
int filterIdx = blockIdx.x / (channel_num * feature_map_size / 32);
int channelIdx = (blockIdx.x % (channel_num * feature_map_size / 32)) /
(feature_map_size / 32);
int tx = (blockIdx.x % (channel_num * feature_map_size / 32)) %
(feature_map_size / 32) *32 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / 32)) * 32 + threadIdx.y;
__shared__ float shV[32+MAX_FILETER_SIZE][32+MAX_FILETER_SIZE];
__shared__ float shH[32][32];
float sign;
if(is_init){
sign = 1.0f;
}else{
sign = -1.0f;
}
v = v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;
h = h + imgIdx * filter_num * feature_map_size * feature_map_size +
filterIdx * feature_map_size * feature_map_size;
dw = dw + filterIdx * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;
float local_dw = 0.0f;
for(int loadX = 0; loadX <= 32; loadX += filter_size){
for(int loadY = 0; loadY <= 32; loadY += filter_size){
if(loadX < 32 && loadY < 32){
//TODO:feature map overflow
shH[threadIdx.y+loadY][threadIdx.x+loadX] =
h[(ty+loadY)*feature_map_size + (tx+loadX)];
}
if((tx+loadX) < lu_padding ||
(ty+loadY) < lu_padding ||
(tx+loadX) >= (input_size+lu_padding) ||
(ty+loadY) >= (input_size+lu_padding)){
shV[threadIdx.y+loadY][threadIdx.x+loadX] = 0;
}else{
shV[threadIdx.y+loadY][threadIdx.x+loadX] =
v[(ty+loadY-lu_padding)*input_size + (tx+loadX-lu_padding)];
}
}
}
__syncthreads();
for(int i = 0; i < 32; i++){
for(int j = 0; j < 32; j++){
local_dw += shV[threadIdx.y+i][threadIdx.x+j] *
shH[i][j];
}
}
atomicAdd(dw + threadIdx.y*filter_size + threadIdx.x, sign * local_dw);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_d_w_kernel(float *v, float *h, float *dw, bool is_init, int input_size, int lu_padding, int channel_num, int filter_num, int filter_size, int feature_map_size){
int imgIdx = blockIdx.y / (feature_map_size / 32);
int filterIdx = blockIdx.x / (channel_num * feature_map_size / 32);
int channelIdx = (blockIdx.x % (channel_num * feature_map_size / 32)) /
(feature_map_size / 32);
int tx = (blockIdx.x % (channel_num * feature_map_size / 32)) %
(feature_map_size / 32) *32 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / 32)) * 32 + threadIdx.y;
__shared__ float shV[32+MAX_FILETER_SIZE][32+MAX_FILETER_SIZE];
__shared__ float shH[32][32];
float sign;
if(is_init){
sign = 1.0f;
}else{
sign = -1.0f;
}
v = v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;
h = h + imgIdx * filter_num * feature_map_size * feature_map_size +
filterIdx * feature_map_size * feature_map_size;
dw = dw + filterIdx * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;
float local_dw = 0.0f;
for(int loadX = 0; loadX <= 32; loadX += filter_size){
for(int loadY = 0; loadY <= 32; loadY += filter_size){
if(loadX < 32 && loadY < 32){
//TODO:feature map overflow
shH[threadIdx.y+loadY][threadIdx.x+loadX] =
h[(ty+loadY)*feature_map_size + (tx+loadX)];
}
if((tx+loadX) < lu_padding ||
(ty+loadY) < lu_padding ||
(tx+loadX) >= (input_size+lu_padding) ||
(ty+loadY) >= (input_size+lu_padding)){
shV[threadIdx.y+loadY][threadIdx.x+loadX] = 0;
}else{
shV[threadIdx.y+loadY][threadIdx.x+loadX] =
v[(ty+loadY-lu_padding)*input_size + (tx+loadX-lu_padding)];
}
}
}
__syncthreads();
for(int i = 0; i < 32; i++){
for(int j = 0; j < 32; j++){
local_dw += shV[threadIdx.y+i][threadIdx.x+j] *
shH[i][j];
}
}
atomicAdd(dw + threadIdx.y*filter_size + threadIdx.x, sign * local_dw);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_d_w_kernel(float *v, float *h, float *dw, bool is_init, int input_size, int lu_padding, int channel_num, int filter_num, int filter_size, int feature_map_size){
int imgIdx = blockIdx.y / (feature_map_size / 32);
int filterIdx = blockIdx.x / (channel_num * feature_map_size / 32);
int channelIdx = (blockIdx.x % (channel_num * feature_map_size / 32)) /
(feature_map_size / 32);
int tx = (blockIdx.x % (channel_num * feature_map_size / 32)) %
(feature_map_size / 32) *32 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / 32)) * 32 + threadIdx.y;
__shared__ float shV[32+MAX_FILETER_SIZE][32+MAX_FILETER_SIZE];
__shared__ float shH[32][32];
float sign;
if(is_init){
sign = 1.0f;
}else{
sign = -1.0f;
}
v = v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;
h = h + imgIdx * filter_num * feature_map_size * feature_map_size +
filterIdx * feature_map_size * feature_map_size;
dw = dw + filterIdx * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;
float local_dw = 0.0f;
for(int loadX = 0; loadX <= 32; loadX += filter_size){
for(int loadY = 0; loadY <= 32; loadY += filter_size){
if(loadX < 32 && loadY < 32){
//TODO:feature map overflow
shH[threadIdx.y+loadY][threadIdx.x+loadX] =
h[(ty+loadY)*feature_map_size + (tx+loadX)];
}
if((tx+loadX) < lu_padding ||
(ty+loadY) < lu_padding ||
(tx+loadX) >= (input_size+lu_padding) ||
(ty+loadY) >= (input_size+lu_padding)){
shV[threadIdx.y+loadY][threadIdx.x+loadX] = 0;
}else{
shV[threadIdx.y+loadY][threadIdx.x+loadX] =
v[(ty+loadY-lu_padding)*input_size + (tx+loadX-lu_padding)];
}
}
}
__syncthreads();
for(int i = 0; i < 32; i++){
for(int j = 0; j < 32; j++){
local_dw += shV[threadIdx.y+i][threadIdx.x+j] *
shH[i][j];
}
}
atomicAdd(dw + threadIdx.y*filter_size + threadIdx.x, sign * local_dw);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18compute_d_w_kernelPfS_S_biiiiii
.globl _Z18compute_d_w_kernelPfS_S_biiiiii
.p2align 8
.type _Z18compute_d_w_kernelPfS_S_biiiiii,@function
_Z18compute_d_w_kernelPfS_S_biiiiii:
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x1c
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v5, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v2, 7, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s13, 31
s_mul_i32 s19, s4, s4
s_lshr_b32 s2, s2, 27
s_mul_i32 s21, s13, s13
s_add_i32 s2, s13, s2
s_mul_i32 s7, s21, s7
s_ashr_i32 s17, s2, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s17
s_sub_i32 s3, 0, s17
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_mul_hi_u32 s3, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s3, s17
s_add_i32 s9, s3, 1
s_sub_i32 s8, s15, s8
s_sub_i32 s10, s8, s17
s_cmp_ge_u32 s8, s17
s_cselect_b32 s3, s9, s3
s_cselect_b32 s8, s10, s8
s_add_i32 s9, s3, 1
s_cmp_ge_u32 s8, s17
s_mul_i32 s8, s13, s6
s_cselect_b32 s20, s9, s3
s_ashr_i32 s3, s8, 31
s_mul_i32 s24, s20, s17
s_lshr_b32 s3, s3, 27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s3
s_ashr_i32 s3, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s9, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_lshl_add_u32 v1, s15, 5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s14, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s3
s_add_i32 s10, s8, 1
s_sub_i32 s9, s14, s9
s_sub_i32 s11, s9, s3
s_cmp_ge_u32 s9, s3
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s3
s_cselect_b32 s16, s10, s8
s_load_b128 s[8:11], s[0:1], 0x0
s_mul_i32 s3, s16, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s18, s14, s3
s_mul_i32 s14, s19, s6
s_mul_hi_u32 s2, s18, s2
s_mul_i32 s3, s2, s17
s_add_i32 s22, s2, 1
s_sub_i32 s3, s18, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s23, s3, s17
s_cmp_ge_u32 s3, s17
s_cselect_b32 s22, s22, s2
s_cselect_b32 s2, s23, s3
s_add_i32 s3, s22, 1
s_cmp_ge_u32 s2, s17
s_mul_i32 s2, s14, s20
s_cselect_b32 s14, s3, s22
s_ashr_i32 s3, s2, 31
s_mul_i32 s17, s14, s17
s_lshl_b64 s[2:3], s[2:3], 2
s_sub_i32 s17, s18, s17
s_sub_i32 s22, s15, s24
s_mul_i32 s18, s19, s14
s_lshl_b32 s23, s17, 5
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s8, s2
s_addc_u32 s9, s9, s3
s_ashr_i32 s19, s18, 31
v_lshl_add_u32 v6, s22, 5, v4
s_lshl_b64 s[2:3], s[18:19], 2
s_mul_i32 s18, s7, s20
s_add_u32 s7, s8, s2
s_addc_u32 s8, s9, s3
s_ashr_i32 s19, s18, 31
v_mul_lo_u32 v3, s13, v6
s_lshl_b64 s[2:3], s[18:19], 2
s_mul_i32 s18, s21, s16
s_add_u32 s9, s10, s2
s_addc_u32 s10, s11, s3
s_ashr_i32 s19, s18, 31
v_add_nc_u32_e32 v9, s23, v5
s_lshl_b64 s[2:3], s[18:19], 2
v_add3_u32 v11, v5, v3, s23
s_add_u32 s9, s9, s2
s_addc_u32 s10, s10, s3
s_lshl_b32 s2, s24, 5
s_mov_b32 s11, 0
v_subrev_nc_u32_e32 v1, s2, v1
s_mul_i32 s15, s12, 0xa0
s_add_i32 s17, s5, s4
s_lshl_b32 s18, s12, 2
s_mul_i32 s19, s12, s4
v_subrev_nc_u32_e32 v0, s5, v1
v_lshlrev_b32_e32 v1, 2, v5
s_lshl_b32 s20, s12, 7
s_mul_i32 s13, s13, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s4, v0
v_mad_u32_u24 v7, v4, 0xa0, v1
v_add3_u32 v8, v2, v1, 0x1900
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v5, v0, s23
v_subrev_nc_u32_e32 v10, s5, v0
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v7, s18, v7
v_add_nc_u32_e32 v10, s12, v10
v_add_nc_u32_e32 v8, s18, v8
v_add_nc_u32_e32 v11, s12, v11
s_add_i32 s11, s11, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s11, 32
s_cbranch_scc1 .LBB0_10
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mov_b32 v0, v11 :: v_dual_add_nc_u32 v1, s11, v9
s_cmp_lg_u32 s11, 32
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v13, v7
v_cmp_le_i32_e64 s2, s5, v1
v_cmp_gt_i32_e64 s3, s17, v1
v_mov_b32_e32 v2, v10
s_cselect_b32 s4, -1, 0
s_mov_b32 s22, 0
s_xor_b32 s21, s4, -1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
s_waitcnt vmcnt(0)
ds_store_b32 v13, v1
v_add_nc_u32_e32 v13, s15, v13
v_add_nc_u32_e32 v2, s19, v2
v_add_nc_u32_e32 v12, s20, v12
v_add_nc_u32_e32 v0, s13, v0
s_add_i32 s22, s22, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s22, 32
s_cbranch_scc1 .LBB0_1
.LBB0_5:
s_cmp_eq_u32 s22, 32
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s21, s4
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_7
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], 2, v[0:1]
v_add_co_u32 v14, vcc_lo, s9, v14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, s10, v15, vcc_lo
global_load_b32 v1, v[14:15], off
s_waitcnt vmcnt(0)
ds_store_b32 v12, v1
.LBB0_7:
v_mov_b32_e32 v1, 0
s_and_saveexec_b32 s23, s2
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v1, s22, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s17, v1
v_cmp_le_i32_e64 s4, s5, v1
v_mov_b32_e32 v1, 0
s_and_b32 s24, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s24, s4, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s24
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], 2, v[2:3]
v_add_co_u32 v14, vcc_lo, s7, v14
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, s8, v15, vcc_lo
global_load_b32 v1, v[14:15], off
s_branch .LBB0_3
.LBB0_10:
v_lshlrev_b32_e32 v0, 2, v5
v_mov_b32_e32 v2, 0
s_mov_b32 s2, 0
s_movk_i32 s3, 0x1900
s_waitcnt lgkmcnt(0)
v_mad_u32_u24 v0, v4, 0xa0, v0
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_11:
s_mov_b32 s4, 0
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s3, s4
v_add_nc_u32_e32 v1, s4, v0
v_mov_b32_e32 v3, s5
s_add_i32 s4, s4, 4
ds_load_b32 v1, v1
ds_load_b32 v3, v3
s_cmpk_eq_i32 s4, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v1, v3
s_cbranch_scc0 .LBB0_12
v_add_nc_u32_e32 v0, 0xa0, v0
s_add_i32 s2, s2, 1
s_addk_i32 s3, 0x80
s_cmp_eq_u32 s2, 32
s_cbranch_scc0 .LBB0_11
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x10
s_mul_i32 s4, s12, s12
v_mul_lo_u32 v0, v4, s12
s_mul_i32 s3, s4, s6
v_mov_b32_e32 v1, 0
s_mul_i32 s4, s4, s14
v_lshlrev_b32_e32 v3, 2, v5
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_bitcmp1_b32 s2, 0
s_mul_i32 s2, s3, s16
s_cselect_b32 s6, -1, 0
s_ashr_i32 s3, s2, 31
v_cndmask_b32_e64 v4, -v2, v2, s6
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
v_add_co_u32 v0, vcc_lo, v0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
global_load_b32 v3, v[0:1], off
.LBB0_15:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v4
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_15
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18compute_d_w_kernelPfS_S_biiiiii
.amdhsa_group_segment_fixed_size 10496
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18compute_d_w_kernelPfS_S_biiiiii, .Lfunc_end0-_Z18compute_d_w_kernelPfS_S_biiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 1
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 10496
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18compute_d_w_kernelPfS_S_biiiiii
.private_segment_fixed_size: 0
.sgpr_count: 27
.sgpr_spill_count: 0
.symbol: _Z18compute_d_w_kernelPfS_S_biiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void compute_d_w_kernel(float *v, float *h, float *dw, bool is_init, int input_size, int lu_padding, int channel_num, int filter_num, int filter_size, int feature_map_size){
int imgIdx = blockIdx.y / (feature_map_size / 32);
int filterIdx = blockIdx.x / (channel_num * feature_map_size / 32);
int channelIdx = (blockIdx.x % (channel_num * feature_map_size / 32)) /
(feature_map_size / 32);
int tx = (blockIdx.x % (channel_num * feature_map_size / 32)) %
(feature_map_size / 32) *32 + threadIdx.x;
int ty = (blockIdx.y % (feature_map_size / 32)) * 32 + threadIdx.y;
__shared__ float shV[32+MAX_FILETER_SIZE][32+MAX_FILETER_SIZE];
__shared__ float shH[32][32];
float sign;
if(is_init){
sign = 1.0f;
}else{
sign = -1.0f;
}
v = v + imgIdx * channel_num * input_size * input_size +
channelIdx * input_size * input_size;
h = h + imgIdx * filter_num * feature_map_size * feature_map_size +
filterIdx * feature_map_size * feature_map_size;
dw = dw + filterIdx * channel_num * filter_size * filter_size +
channelIdx * filter_size * filter_size;
float local_dw = 0.0f;
for(int loadX = 0; loadX <= 32; loadX += filter_size){
for(int loadY = 0; loadY <= 32; loadY += filter_size){
if(loadX < 32 && loadY < 32){
//TODO:feature map overflow
shH[threadIdx.y+loadY][threadIdx.x+loadX] =
h[(ty+loadY)*feature_map_size + (tx+loadX)];
}
if((tx+loadX) < lu_padding ||
(ty+loadY) < lu_padding ||
(tx+loadX) >= (input_size+lu_padding) ||
(ty+loadY) >= (input_size+lu_padding)){
shV[threadIdx.y+loadY][threadIdx.x+loadX] = 0;
}else{
shV[threadIdx.y+loadY][threadIdx.x+loadX] =
v[(ty+loadY-lu_padding)*input_size + (tx+loadX-lu_padding)];
}
}
}
__syncthreads();
for(int i = 0; i < 32; i++){
for(int j = 0; j < 32; j++){
local_dw += shV[threadIdx.y+i][threadIdx.x+j] *
shH[i][j];
}
}
atomicAdd(dw + threadIdx.y*filter_size + threadIdx.x, sign * local_dw);
} | .text
.file "compute_d_w_kernel.hip"
.globl _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii # -- Begin function _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.p2align 4, 0x90
.type _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii,@function
_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii: # @_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movb %cl, 15(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 15(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18compute_d_w_kernelPfS_S_biiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii, .Lfunc_end0-_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compute_d_w_kernelPfS_S_biiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18compute_d_w_kernelPfS_S_biiiiii,@object # @_Z18compute_d_w_kernelPfS_S_biiiiii
.section .rodata,"a",@progbits
.globl _Z18compute_d_w_kernelPfS_S_biiiiii
.p2align 3, 0x0
_Z18compute_d_w_kernelPfS_S_biiiiii:
.quad _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.size _Z18compute_d_w_kernelPfS_S_biiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18compute_d_w_kernelPfS_S_biiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18compute_d_w_kernelPfS_S_biiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001805ab_00000000-6_compute_d_w_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
.type _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii, @function
_Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movb %cl, 20(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18compute_d_w_kernelPfS_S_biiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii, .-_Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
.globl _Z18compute_d_w_kernelPfS_S_biiiiii
.type _Z18compute_d_w_kernelPfS_S_biiiiii, @function
_Z18compute_d_w_kernelPfS_S_biiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z18compute_d_w_kernelPfS_S_biiiiiiPfS_S_biiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18compute_d_w_kernelPfS_S_biiiiii, .-_Z18compute_d_w_kernelPfS_S_biiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18compute_d_w_kernelPfS_S_biiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compute_d_w_kernelPfS_S_biiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compute_d_w_kernel.hip"
.globl _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii # -- Begin function _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.p2align 4, 0x90
.type _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii,@function
_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii: # @_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movb %cl, 15(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 15(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18compute_d_w_kernelPfS_S_biiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii, .Lfunc_end0-_Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compute_d_w_kernelPfS_S_biiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18compute_d_w_kernelPfS_S_biiiiii,@object # @_Z18compute_d_w_kernelPfS_S_biiiiii
.section .rodata,"a",@progbits
.globl _Z18compute_d_w_kernelPfS_S_biiiiii
.p2align 3, 0x0
_Z18compute_d_w_kernelPfS_S_biiiiii:
.quad _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.size _Z18compute_d_w_kernelPfS_S_biiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18compute_d_w_kernelPfS_S_biiiiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__compute_d_w_kernelPfS_S_biiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18compute_d_w_kernelPfS_S_biiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <algorithm>
#include <cstdlib>
#include <cuda.h>
int main(int argc, char* argv[])
{
size_t N = 10000; // Default value
cudaEvent_t start;
cudaEvent_t end;
float elapsed_time;
cudaEventCreate(&start);
cudaEventCreate(&end);
// generate 32M random numbers serially
if (argc > 1) {
N = atoi(argv[1]);
std::cout << "Using number of elements = " << N << std::endl;
}
thrust::host_vector<int> h_vec(N);
std::generate(h_vec.begin(), h_vec.end(), rand);
thrust::device_vector<int> d_vec = h_vec;
cudaEventRecord(start,0);
// starting sorting data on the host
thrust::sort(h_vec.begin(), h_vec.end());
// finished sorting data on the host
cudaEventSynchronize(end);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&elapsed_time, start, end);
std::cout << "host sort took " << elapsed_time << " milliseconds" << std::endl;
// output smallest/largest value
std::cout << "Smallest value is\n" << h_vec[0] << std::endl;
std::cout << "Largest value is\n" << h_vec[h_vec.size()-1] << std::endl;
cudaEventRecord(start,0);
// starting sorting data on the host
thrust::sort(d_vec.begin(), d_vec.end());
// finished sorting data on the host
cudaEventSynchronize(end);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&elapsed_time, start, end);
std::cout << "device sort took " << elapsed_time << " milliseconds" << std::endl;
// output smallest/largest value
std::cout << "Smallest value is\n" << d_vec[0] << std::endl;
std::cout << "Largest value is\n" << d_vec[d_vec.size()-1] << std::endl;
return 0;
} | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <algorithm>
#include <cstdlib>
#include <hip/hip_runtime.h>
int main(int argc, char* argv[])
{
size_t N = 10000; // Default value
hipEvent_t start;
hipEvent_t end;
float elapsed_time;
hipEventCreate(&start);
hipEventCreate(&end);
// generate 32M random numbers serially
if (argc > 1) {
N = atoi(argv[1]);
std::cout << "Using number of elements = " << N << std::endl;
}
thrust::host_vector<int> h_vec(N);
std::generate(h_vec.begin(), h_vec.end(), rand);
thrust::device_vector<int> d_vec = h_vec;
hipEventRecord(start,0);
// starting sorting data on the host
thrust::sort(h_vec.begin(), h_vec.end());
// finished sorting data on the host
hipEventSynchronize(end);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&elapsed_time, start, end);
std::cout << "host sort took " << elapsed_time << " milliseconds" << std::endl;
// output smallest/largest value
std::cout << "Smallest value is\n" << h_vec[0] << std::endl;
std::cout << "Largest value is\n" << h_vec[h_vec.size()-1] << std::endl;
hipEventRecord(start,0);
// starting sorting data on the host
thrust::sort(d_vec.begin(), d_vec.end());
// finished sorting data on the host
hipEventSynchronize(end);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&elapsed_time, start, end);
std::cout << "device sort took " << elapsed_time << " milliseconds" << std::endl;
// output smallest/largest value
std::cout << "Smallest value is\n" << d_vec[0] << std::endl;
std::cout << "Largest value is\n" << d_vec[d_vec.size()-1] << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
cudaMalloc(&dnum, LINE*sizeof(int));
cudaMemcpy(dnum, num, LINE*sizeof(int), cudaMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
cudaMemcpy(num, dnum, LINE*sizeof(int), cudaMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} | code for sm_80
Function : _Z3oddPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4evenPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0070*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
cudaMalloc(&dnum, LINE*sizeof(int));
cudaMemcpy(dnum, num, LINE*sizeof(int), cudaMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
cudaMemcpy(num, dnum, LINE*sizeof(int), cudaMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} | .file "tmpxft_001a91a5_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "number.txt"
.LC2:
.string "Error loading file!!\n"
.LC3:
.string "%d"
.text
.globl _Z8readfilePi
.type _Z8readfilePi, @function
_Z8readfilePi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L4
movq %rax, %rbp
leaq .LC3(%rip), %r12
jmp .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L6:
leaq 4(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
.L5:
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
je .L6
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8readfilePi, .-_Z8readfilePi
.section .rodata.str1.1
.LC4:
.string "w"
.LC5:
.string "update.txt"
.LC6:
.string "%d "
.text
.globl _Z9printfilePi
.type _Z9printfilePi, @function
_Z9printfilePi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbp, %rbx
addq $400000, %rbp
leaq .LC6(%rip), %r13
.L11:
movl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9printfilePi, .-_Z9printfilePi
.globl _Z8copyDataPiS_
.type _Z8copyDataPiS_, @function
_Z8copyDataPiS_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %eax
.L15:
movl (%rdi,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L15
ret
.cfi_endproc
.LFE2059:
.size _Z8copyDataPiS_, .-_Z8copyDataPiS_
.globl _Z24__device_stub__Z4evenPiiPii
.type _Z24__device_stub__Z4evenPiiPii, @function
_Z24__device_stub__Z4evenPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4evenPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z24__device_stub__Z4evenPiiPii, .-_Z24__device_stub__Z4evenPiiPii
.globl _Z4evenPii
.type _Z4evenPii, @function
_Z4evenPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4evenPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z4evenPii, .-_Z4evenPii
.globl _Z23__device_stub__Z3oddPiiPii
.type _Z23__device_stub__Z3oddPiiPii, @function
_Z23__device_stub__Z3oddPiiPii:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3oddPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z23__device_stub__Z3oddPiiPii, .-_Z23__device_stub__Z3oddPiiPii
.globl _Z3oddPii
.type _Z3oddPii, @function
_Z3oddPii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3oddPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z3oddPii, .-_Z3oddPii
.globl _Z6docudaPii
.type _Z6docudaPii, @function
_Z6docudaPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L40
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %ebp
movl $0, %ebx
jmp .L37
.L44:
movl %ebp, %esi
movq %r12, %rdi
call _Z24__device_stub__Z4evenPiiPii
jmp .L35
.L36:
addl $1, %ebx
cmpl %ebx, %ebp
je .L43
.L37:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $100000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L35:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $100000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L36
movl %ebp, %esi
movq %r12, %rdi
call _Z23__device_stub__Z3oddPiiPii
jmp .L36
.L43:
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _Z6docudaPii, .-_Z6docudaPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n"
.align 8
.LC9:
.string "================================================================================\n"
.align 8
.LC10:
.string " Number of data 1st time 2nd time 3rd time average \n"
.align 8
.LC13:
.string " %i %fs %fs %fs %fs\n"
.text
.globl _Z4cudaPiS_
.type _Z4cudaPiS_, @function
_Z4cudaPiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC9(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0x000000000, 24(%rsp)
movq $0x000000000, 16(%rsp)
movl $10000, %r14d
leaq 32(%rsp), %r15
jmp .L46
.L56:
movq %r12, %xmm4
subsd (%rsp), %xmm4
movsd %xmm4, 16(%rsp)
.L48:
addl $1, %ebx
.L51:
movq 8(%rsp), %rsi
movq %rbp, %rdi
call _Z8copyDataPiS_
movl $400000, %esi
movq %r15, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %r13
leaq 48(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movl %r14d, %esi
movq 32(%rsp), %rdi
call _Z6docudaPii
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
divsd .LC11(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
addsd %xmm0, %xmm2
movq %xmm2, %r12
movl $2, %ecx
movl $400000, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
je .L56
cmpl $1, %ebx
je .L57
cmpl $2, %ebx
jne .L48
movq %r12, %xmm2
subsd (%rsp), %xmm2
movsd 16(%rsp), %xmm0
movapd %xmm0, %xmm3
movsd 24(%rsp), %xmm1
addsd %xmm1, %xmm3
addsd %xmm2, %xmm3
divsd .LC12(%rip), %xmm3
movl %r14d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addl $10000, %r14d
cmpl $110000, %r14d
je .L58
.L46:
movl $0, %ebx
jmp .L51
.L57:
movq %r12, %xmm7
subsd (%rsp), %xmm7
movsd %xmm7, 24(%rsp)
jmp .L48
.L58:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z4cudaPiS_, .-_Z4cudaPiS_
.section .rodata.str1.1
.LC14:
.string "Getting data...\n"
.LC15:
.string "Sorting data...\n\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "\nParallel bubble sort in CUDA sucessfully.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -798720(%rsp), %r11
.cfi_def_cfa 11, 798736
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1296, %rsp
.cfi_def_cfa_offset 800032
movq %fs:40, %rax
movq %rax, 800008(%rsp)
xorl %eax, %eax
leaq .LC14(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbx
movq %rbx, %rdi
call _Z8readfilePi
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 400000(%rsp), %rsi
movq %rbx, %rdi
call _Z4cudaPiS_
movq %rbx, %rdi
call _Z9printfilePi
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 800008(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $800016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z3oddPii"
.LC18:
.string "_Z4evenPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3oddPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z4evenPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long 0
.long 1093567616
.align 8
.LC12:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
cudaMalloc(&dnum, LINE*sizeof(int));
cudaMemcpy(dnum, num, LINE*sizeof(int), cudaMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
cudaMemcpy(num, dnum, LINE*sizeof(int), cudaMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
hipMalloc(&dnum, LINE*sizeof(int));
hipMemcpy(dnum, num, LINE*sizeof(int), hipMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
hipMemcpy(num, dnum, LINE*sizeof(int), hipMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
hipMalloc(&dnum, LINE*sizeof(int));
hipMemcpy(dnum, num, LINE*sizeof(int), hipMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
hipMemcpy(num, dnum, LINE*sizeof(int), hipMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4evenPii
.globl _Z4evenPii
.p2align 8
.type _Z4evenPii,@function
_Z4evenPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -2
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4evenPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4evenPii, .Lfunc_end0-_Z4evenPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3oddPii
.globl _Z3oddPii
.p2align 8
.type _Z3oddPii,@function
_Z3oddPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -2
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_or_b32_e32 v1, 1, v0
v_add_nc_u32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3oddPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3oddPii, .Lfunc_end1-_Z3oddPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4evenPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4evenPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3oddPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3oddPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define LINE 100000
void readfile(int num[LINE]){
int temp;
int i;
FILE *fp;
fp = fopen("number.txt", "r");
i = 0;
if(fp == NULL){
printf("Error loading file!!\n");
exit(1);
}else{
while(!feof(fp)){
fscanf(fp, "%d", &temp);
num[i] = temp;
i++;
}
}
fclose(fp);
}
void printfile(int num[LINE]){
int i;
FILE *fp = fopen("update.txt", "w");
for (i = 0; i < LINE; i++)
fprintf(fp, "%d ", num[i]);
fclose(fp);
}
void copyData(int num[LINE], int num1[LINE]){
int i;
for(i = 0; i < LINE; i++)
num1[i] = num[i];
}
__global__ void even(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
__global__ void odd(int *dnum, int n){
int k = threadIdx.x + blockIdx.x * blockDim.x;
int temp;
k = k * 2 + 1;
if(k <= n - 2){
if(dnum[k] > dnum[k + 1]){
temp = dnum[k];
dnum[k] = dnum[k + 1];
dnum[k + 1] = temp;
}
}
}
void docuda(int *dnum, int line){
int i;
for(i = 0; i < line; i++){
even<<<LINE, 256>>>(dnum, line);
odd<<<LINE, 256>>>(dnum, line);
}
}
void cuda(int num[LINE], int num1[LINE]){
int line, i;
int *dnum;
struct timeval tv;
struct timezone tz;
double start, end, time, time1, time2, average;
start = 0;
end = 0;
time = 0;
time1 = 0;
time2 = 0;
line = 10000;
average = 0;
printf("Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n");
printf("================================================================================\n");
printf(" Number of data 1st time 2nd time 3rd time average \n");
printf("================================================================================\n");
while (line <= LINE){
for (i = 0; i < 3; i++){
copyData(num, num1);
hipMalloc(&dnum, LINE*sizeof(int));
hipMemcpy(dnum, num, LINE*sizeof(int), hipMemcpyHostToDevice);
gettimeofday(&tv, &tz);
start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
docuda(dnum, line);
gettimeofday(&tv, &tz);
end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000;
hipMemcpy(num, dnum, LINE*sizeof(int), hipMemcpyDeviceToHost);
if (i == 0)
time = end - start;
else if (i == 1)
time1 = end - start;
else if (i == 2)
time2 = end - start;
}
average = (time + time1 + time2) / 3;
printf(" %i %fs %fs %fs %fs\n", line, time, time1, time2, average);
line += 10000;
}
}
int main(){
int num[LINE];
int num1[LINE];
printf("Getting data...\n");
readfile(num);
printf("Sorting data...\n\n");
cuda(num, num1);
printfile(num);
printf("\nParallel bubble sort in CUDA sucessfully.\n");
return 0;
} | .text
.file "cuda.hip"
.globl _Z8readfilePi # -- Begin function _Z8readfilePi
.p2align 4, 0x90
.type _Z8readfilePi,@function
_Z8readfilePi: # @_Z8readfilePi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB0_5
# %bb.1: # %.preheader
movq %rax, %r14
movq %rax, %rdi
callq feof
testl %eax, %eax
jne .LBB0_4
# %bb.2:
leaq 12(%rsp), %r15
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movl %eax, (%rbx)
movq %r14, %rdi
callq feof
addq $4, %rbx
testl %eax, %eax
je .LBB0_3
.LBB0_4: # %._crit_edge
movq %r14, %rdi
callq fclose
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8readfilePi, .Lfunc_end0-_Z8readfilePi
.cfi_endproc
# -- End function
.globl _Z9printfilePi # -- Begin function _Z9printfilePi
.p2align 4, 0x90
.type _Z9printfilePi,@function
_Z9printfilePi: # @_Z9printfilePi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $100000, %r15 # imm = 0x186A0
jne .LBB1_1
# %bb.2:
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z9printfilePi, .Lfunc_end1-_Z9printfilePi
.cfi_endproc
# -- End function
.globl _Z8copyDataPiS_ # -- Begin function _Z8copyDataPiS_
.p2align 4, 0x90
.type _Z8copyDataPiS_,@function
_Z8copyDataPiS_: # @_Z8copyDataPiS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %ecx
movl %ecx, (%rsi,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z8copyDataPiS_, .Lfunc_end2-_Z8copyDataPiS_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__evenPii # -- Begin function _Z19__device_stub__evenPii
.p2align 4, 0x90
.type _Z19__device_stub__evenPii,@function
_Z19__device_stub__evenPii: # @_Z19__device_stub__evenPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4evenPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z19__device_stub__evenPii, .Lfunc_end3-_Z19__device_stub__evenPii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__oddPii # -- Begin function _Z18__device_stub__oddPii
.p2align 4, 0x90
.type _Z18__device_stub__oddPii,@function
_Z18__device_stub__oddPii: # @_Z18__device_stub__oddPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3oddPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z18__device_stub__oddPii, .Lfunc_end4-_Z18__device_stub__oddPii
.cfi_endproc
# -- End function
.globl _Z6docudaPii # -- Begin function _Z6docudaPii
.p2align 4, 0x90
.type _Z6docudaPii,@function
_Z6docudaPii: # @_Z6docudaPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_8
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967552, %r15 # imm = 0x100000100
leaq 99744(%r15), %r12
leaq 64(%rsp), %r13
movl %esi, %ebx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
decl %ebx
je .LBB5_7
.LBB5_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z4evenPii, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_2 Depth=1
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z3oddPii, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_6
.LBB5_7:
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_8: # %._crit_edge
retq
.Lfunc_end5:
.size _Z6docudaPii, .Lfunc_end5-_Z6docudaPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4cudaPiS_
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI6_1:
.quad 0x4008000000000000 # double 3
.text
.globl _Z4cudaPiS_
.p2align 4, 0x90
.type _Z4cudaPiS_,@function
_Z4cudaPiS_: # @_Z4cudaPiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $10000, %r12d # imm = 0x2710
xorpd %xmm0, %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
leaq 48(%rsp), %r13
leaq 64(%rsp), %rbp
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_11: # in Loop: Header=BB6_1 Depth=1
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movapd %xmm0, %xmm3
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm1, %xmm3
movsd 40(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
addsd %xmm2, %xmm3
divsd .LCPI6_1(%rip), %xmm3
movl $.L.str.10, %edi
movl %r12d, %esi
movb $4, %al
callq printf
leal 10000(%r12), %eax
cmpl $90001, %r12d # imm = 0x15F91
movl %eax, %r12d
jae .LBB6_12
.LBB6_1: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
xorl %r15d, %r15d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_8: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
.LBB6_10: # in Loop: Header=BB6_2 Depth=2
incl %r15d
cmpl $3, %r15d
je .LBB6_11
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14,%rax,4), %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB6_3
# %bb.4: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
movl $400000, %esi # imm = 0x61A80
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movq %rbp, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movl %r12d, %esi
callq _Z6docudaPii
movq %r13, %rdi
movq %rbp, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
divsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq 16(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $2, %r15d
je .LBB6_9
# %bb.5: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
cmpl $1, %r15d
je .LBB6_8
# %bb.6: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
testl %r15d, %r15d
jne .LBB6_10
# %bb.7: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB6_10
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 40(%rsp) # 8-byte Spill
jmp .LBB6_10
.LBB6_12:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z4cudaPiS_, .Lfunc_end6-_Z4cudaPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $800008, %rsp # imm = 0xC3508
.cfi_def_cfa_offset 800032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr.5, %edi
callq puts@PLT
movq %rsp, %rbx
movq %rbx, %rdi
callq _Z8readfilePi
movl $.Lstr.6, %edi
callq puts@PLT
leaq 400000(%rsp), %rsi
movq %rbx, %rdi
callq _Z4cudaPiS_
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB7_1
# %bb.2: # %_Z9printfilePi.exit
movq %rbx, %rdi
callq fclose
movl $.Lstr.7, %edi
callq puts@PLT
xorl %eax, %eax
addq $800008, %rsp # imm = 0xC3508
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4evenPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3oddPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "number.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "update.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 6
.type _Z4evenPii,@object # @_Z4evenPii
.section .rodata,"a",@progbits
.globl _Z4evenPii
.p2align 3, 0x0
_Z4evenPii:
.quad _Z19__device_stub__evenPii
.size _Z4evenPii, 8
.type _Z3oddPii,@object # @_Z3oddPii
.globl _Z3oddPii
.p2align 3, 0x0
_Z3oddPii:
.quad _Z18__device_stub__oddPii
.size _Z3oddPii, 8
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz " %i %fs %fs %fs %fs\n"
.size .L.str.10, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4evenPii"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3oddPii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error loading file!!"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Time execution for parallel bubble sort using CUDA using 100k block and 256 threads"
.size .Lstr.1, 84
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " Number of data 1st time 2nd time 3rd time average "
.size .Lstr.3, 81
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "================================================================================"
.size .Lstr.4, 81
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Getting data..."
.size .Lstr.5, 16
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Sorting data...\n"
.size .Lstr.6, 17
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "\nParallel bubble sort in CUDA sucessfully."
.size .Lstr.7, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__evenPii
.addrsig_sym _Z18__device_stub__oddPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4evenPii
.addrsig_sym _Z3oddPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3oddPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4evenPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0070*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4evenPii
.globl _Z4evenPii
.p2align 8
.type _Z4evenPii,@function
_Z4evenPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -2
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4evenPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4evenPii, .Lfunc_end0-_Z4evenPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3oddPii
.globl _Z3oddPii
.p2align 8
.type _Z3oddPii,@function
_Z3oddPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_i32 s3, s3, -2
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_or_b32_e32 v1, 1, v0
v_add_nc_u32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3oddPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3oddPii, .Lfunc_end1-_Z3oddPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4evenPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4evenPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3oddPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3oddPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a91a5_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "number.txt"
.LC2:
.string "Error loading file!!\n"
.LC3:
.string "%d"
.text
.globl _Z8readfilePi
.type _Z8readfilePi, @function
_Z8readfilePi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L4
movq %rax, %rbp
leaq .LC3(%rip), %r12
jmp .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L6:
leaq 4(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 4(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
.L5:
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
je .L6
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8readfilePi, .-_Z8readfilePi
.section .rodata.str1.1
.LC4:
.string "w"
.LC5:
.string "update.txt"
.LC6:
.string "%d "
.text
.globl _Z9printfilePi
.type _Z9printfilePi, @function
_Z9printfilePi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
leaq .LC4(%rip), %rsi
leaq .LC5(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbp, %rbx
addq $400000, %rbp
leaq .LC6(%rip), %r13
.L11:
movl (%rbx), %ecx
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
movq %r12, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9printfilePi, .-_Z9printfilePi
.globl _Z8copyDataPiS_
.type _Z8copyDataPiS_, @function
_Z8copyDataPiS_:
.LFB2059:
.cfi_startproc
endbr64
movl $0, %eax
.L15:
movl (%rdi,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L15
ret
.cfi_endproc
.LFE2059:
.size _Z8copyDataPiS_, .-_Z8copyDataPiS_
.globl _Z24__device_stub__Z4evenPiiPii
.type _Z24__device_stub__Z4evenPiiPii, @function
_Z24__device_stub__Z4evenPiiPii:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4evenPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z24__device_stub__Z4evenPiiPii, .-_Z24__device_stub__Z4evenPiiPii
.globl _Z4evenPii
.type _Z4evenPii, @function
_Z4evenPii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4evenPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z4evenPii, .-_Z4evenPii
.globl _Z23__device_stub__Z3oddPiiPii
.type _Z23__device_stub__Z3oddPiiPii, @function
_Z23__device_stub__Z3oddPiiPii:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3oddPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z23__device_stub__Z3oddPiiPii, .-_Z23__device_stub__Z3oddPiiPii
.globl _Z3oddPii
.type _Z3oddPii, @function
_Z3oddPii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3oddPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z3oddPii, .-_Z3oddPii
.globl _Z6docudaPii
.type _Z6docudaPii, @function
_Z6docudaPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L40
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %ebp
movl $0, %ebx
jmp .L37
.L44:
movl %ebp, %esi
movq %r12, %rdi
call _Z24__device_stub__Z4evenPiiPii
jmp .L35
.L36:
addl $1, %ebx
cmpl %ebx, %ebp
je .L43
.L37:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $100000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L35:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $100000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L36
movl %ebp, %esi
movq %r12, %rdi
call _Z23__device_stub__Z3oddPiiPii
jmp .L36
.L43:
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _Z6docudaPii, .-_Z6docudaPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Time execution for parallel bubble sort using CUDA using 100k block and 256 threads\n"
.align 8
.LC9:
.string "================================================================================\n"
.align 8
.LC10:
.string " Number of data 1st time 2nd time 3rd time average \n"
.align 8
.LC13:
.string " %i %fs %fs %fs %fs\n"
.text
.globl _Z4cudaPiS_
.type _Z4cudaPiS_, @function
_Z4cudaPiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbp
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC9(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0x000000000, 24(%rsp)
movq $0x000000000, 16(%rsp)
movl $10000, %r14d
leaq 32(%rsp), %r15
jmp .L46
.L56:
movq %r12, %xmm4
subsd (%rsp), %xmm4
movsd %xmm4, 16(%rsp)
.L48:
addl $1, %ebx
.L51:
movq 8(%rsp), %rsi
movq %rbp, %rdi
call _Z8copyDataPiS_
movl $400000, %esi
movq %r15, %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %r13
leaq 48(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movl %r14d, %esi
movq 32(%rsp), %rdi
call _Z6docudaPii
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
divsd .LC11(%rip), %xmm2
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
addsd %xmm0, %xmm2
movq %xmm2, %r12
movl $2, %ecx
movl $400000, %edx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
je .L56
cmpl $1, %ebx
je .L57
cmpl $2, %ebx
jne .L48
movq %r12, %xmm2
subsd (%rsp), %xmm2
movsd 16(%rsp), %xmm0
movapd %xmm0, %xmm3
movsd 24(%rsp), %xmm1
addsd %xmm1, %xmm3
addsd %xmm2, %xmm3
divsd .LC12(%rip), %xmm3
movl %r14d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addl $10000, %r14d
cmpl $110000, %r14d
je .L58
.L46:
movl $0, %ebx
jmp .L51
.L57:
movq %r12, %xmm7
subsd (%rsp), %xmm7
movsd %xmm7, 24(%rsp)
jmp .L48
.L58:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z4cudaPiS_, .-_Z4cudaPiS_
.section .rodata.str1.1
.LC14:
.string "Getting data...\n"
.LC15:
.string "Sorting data...\n\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "\nParallel bubble sort in CUDA sucessfully.\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -798720(%rsp), %r11
.cfi_def_cfa 11, 798736
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1296, %rsp
.cfi_def_cfa_offset 800032
movq %fs:40, %rax
movq %rax, 800008(%rsp)
xorl %eax, %eax
leaq .LC14(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbx
movq %rbx, %rdi
call _Z8readfilePi
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 400000(%rsp), %rsi
movq %rbx, %rdi
call _Z4cudaPiS_
movq %rbx, %rdi
call _Z9printfilePi
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 800008(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $800016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC17:
.string "_Z3oddPii"
.LC18:
.string "_Z4evenPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3oddPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z4evenPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long 0
.long 1093567616
.align 8
.LC12:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z8readfilePi # -- Begin function _Z8readfilePi
.p2align 4, 0x90
.type _Z8readfilePi,@function
_Z8readfilePi: # @_Z8readfilePi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB0_5
# %bb.1: # %.preheader
movq %rax, %r14
movq %rax, %rdi
callq feof
testl %eax, %eax
jne .LBB0_4
# %bb.2:
leaq 12(%rsp), %r15
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movl %eax, (%rbx)
movq %r14, %rdi
callq feof
addq $4, %rbx
testl %eax, %eax
je .LBB0_3
.LBB0_4: # %._crit_edge
movq %r14, %rdi
callq fclose
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8readfilePi, .Lfunc_end0-_Z8readfilePi
.cfi_endproc
# -- End function
.globl _Z9printfilePi # -- Begin function _Z9printfilePi
.p2align 4, 0x90
.type _Z9printfilePi,@function
_Z9printfilePi: # @_Z9printfilePi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $100000, %r15 # imm = 0x186A0
jne .LBB1_1
# %bb.2:
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z9printfilePi, .Lfunc_end1-_Z9printfilePi
.cfi_endproc
# -- End function
.globl _Z8copyDataPiS_ # -- Begin function _Z8copyDataPiS_
.p2align 4, 0x90
.type _Z8copyDataPiS_,@function
_Z8copyDataPiS_: # @_Z8copyDataPiS_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl (%rdi,%rax,4), %ecx
movl %ecx, (%rsi,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_1
# %bb.2:
retq
.Lfunc_end2:
.size _Z8copyDataPiS_, .Lfunc_end2-_Z8copyDataPiS_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__evenPii # -- Begin function _Z19__device_stub__evenPii
.p2align 4, 0x90
.type _Z19__device_stub__evenPii,@function
_Z19__device_stub__evenPii: # @_Z19__device_stub__evenPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4evenPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z19__device_stub__evenPii, .Lfunc_end3-_Z19__device_stub__evenPii
.cfi_endproc
# -- End function
.globl _Z18__device_stub__oddPii # -- Begin function _Z18__device_stub__oddPii
.p2align 4, 0x90
.type _Z18__device_stub__oddPii,@function
_Z18__device_stub__oddPii: # @_Z18__device_stub__oddPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3oddPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z18__device_stub__oddPii, .Lfunc_end4-_Z18__device_stub__oddPii
.cfi_endproc
# -- End function
.globl _Z6docudaPii # -- Begin function _Z6docudaPii
.p2align 4, 0x90
.type _Z6docudaPii,@function
_Z6docudaPii: # @_Z6docudaPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_8
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967552, %r15 # imm = 0x100000100
leaq 99744(%r15), %r12
leaq 64(%rsp), %r13
movl %esi, %ebx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
decl %ebx
je .LBB5_7
.LBB5_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z4evenPii, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_2 Depth=1
movq %r14, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z3oddPii, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_6
.LBB5_7:
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB5_8: # %._crit_edge
retq
.Lfunc_end5:
.size _Z6docudaPii, .Lfunc_end5-_Z6docudaPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4cudaPiS_
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI6_1:
.quad 0x4008000000000000 # double 3
.text
.globl _Z4cudaPiS_
.p2align 4, 0x90
.type _Z4cudaPiS_,@function
_Z4cudaPiS_: # @_Z4cudaPiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movl $10000, %r12d # imm = 0x2710
xorpd %xmm0, %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
leaq 48(%rsp), %r13
leaq 64(%rsp), %rbp
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_11: # in Loop: Header=BB6_1 Depth=1
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movapd %xmm0, %xmm3
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm1, %xmm3
movsd 40(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
addsd %xmm2, %xmm3
divsd .LCPI6_1(%rip), %xmm3
movl $.L.str.10, %edi
movl %r12d, %esi
movb $4, %al
callq printf
leal 10000(%r12), %eax
cmpl $90001, %r12d # imm = 0x15F91
movl %eax, %r12d
jae .LBB6_12
.LBB6_1: # %.preheader36
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
xorl %r15d, %r15d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_8: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
.LBB6_10: # in Loop: Header=BB6_2 Depth=2
incl %r15d
cmpl $3, %r15d
je .LBB6_11
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r14,%rax,4), %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB6_3
# %bb.4: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
movl $400000, %esi # imm = 0x61A80
leaq 16(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
movq %rbp, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 56(%rsp), %xmm2
movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
movl %r12d, %esi
callq _Z6docudaPii
movq %r13, %rdi
movq %rbp, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
divsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq 16(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $2, %r15d
je .LBB6_9
# %bb.5: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
cmpl $1, %r15d
je .LBB6_8
# %bb.6: # %_Z8copyDataPiS_.exit
# in Loop: Header=BB6_2 Depth=2
testl %r15d, %r15d
jne .LBB6_10
# %bb.7: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
jmp .LBB6_10
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_2 Depth=2
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 40(%rsp) # 8-byte Spill
jmp .LBB6_10
.LBB6_12:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z4cudaPiS_, .Lfunc_end6-_Z4cudaPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $800008, %rsp # imm = 0xC3508
.cfi_def_cfa_offset 800032
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr.5, %edi
callq puts@PLT
movq %rsp, %rbx
movq %rbx, %rdi
callq _Z8readfilePi
movl $.Lstr.6, %edi
callq puts@PLT
leaq 400000(%rsp), %rsi
movq %rbx, %rdi
callq _Z4cudaPiS_
movl $.L.str.4, %edi
movl $.L.str.5, %esi
callq fopen
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl (%rsp,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB7_1
# %bb.2: # %_Z9printfilePi.exit
movq %rbx, %rdi
callq fclose
movl $.Lstr.7, %edi
callq puts@PLT
xorl %eax, %eax
addq $800008, %rsp # imm = 0xC3508
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4evenPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3oddPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "number.txt"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "update.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 6
.type _Z4evenPii,@object # @_Z4evenPii
.section .rodata,"a",@progbits
.globl _Z4evenPii
.p2align 3, 0x0
_Z4evenPii:
.quad _Z19__device_stub__evenPii
.size _Z4evenPii, 8
.type _Z3oddPii,@object # @_Z3oddPii
.globl _Z3oddPii
.p2align 3, 0x0
_Z3oddPii:
.quad _Z18__device_stub__oddPii
.size _Z3oddPii, 8
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz " %i %fs %fs %fs %fs\n"
.size .L.str.10, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4evenPii"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3oddPii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error loading file!!"
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Time execution for parallel bubble sort using CUDA using 100k block and 256 threads"
.size .Lstr.1, 84
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " Number of data 1st time 2nd time 3rd time average "
.size .Lstr.3, 81
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "================================================================================"
.size .Lstr.4, 81
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Getting data..."
.size .Lstr.5, 16
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Sorting data...\n"
.size .Lstr.6, 17
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "\nParallel bubble sort in CUDA sucessfully."
.size .Lstr.7, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__evenPii
.addrsig_sym _Z18__device_stub__oddPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4evenPii
.addrsig_sym _Z3oddPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} | code for sm_80
Function : _Z8mAddDripPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x190 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0040*/ IADD3 R0, R7, -c[0x0][0x168], RZ ; /* 0x80005a0007007a10 */
/* 0x001fe40007ffe0ff */
/*0050*/ IADD3 R3, R6, -c[0x0][0x16c], RZ ; /* 0x80005b0006037a10 */
/* 0x002fc60007ffe0ff */
/*0060*/ IMAD R2, R0, R0, RZ ; /* 0x0000000000027224 */
/* 0x000fe400078e02ff */
/*0070*/ IMAD R3, R3, R3, RZ ; /* 0x0000000303037224 */
/* 0x000fc800078e02ff */
/*0080*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000ff00000201400 */
/*0090*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e240000201400 */
/*00a0*/ FADD R4, R2, R3 ; /* 0x0000000302047221 */
/* 0x001fcc0000000000 */
/*00b0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00c0*/ IADD3 R0, R4, -0xd000000, RZ ; /* 0xf300000004007810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*00e0*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x000fd800078e0207 */
/*00f0*/ @!P0 BRA 0x140 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0100*/ MOV R8, 0x120 ; /* 0x0000012000087802 */
/* 0x003fe40000000f00 */
/*0110*/ CALL.REL.NOINC 0x220 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0120*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe20000000f00 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R3, R3, R4 ; /* 0x0000000303027223 */
/* 0x000fc80000000104 */
/*0170*/ FFMA R2, R2, R5, R3 ; /* 0x0000000502027223 */
/* 0x000fe40000000003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0b */
/* 0x000fda0003f0e000 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*01d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ FADD R5, R0, 200 ; /* 0x4348000000057421 */
/* 0x004fca0000000000 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*0230*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P0 BRA 0x350 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0260*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0270*/ @!P0 BRA 0x350 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0290*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*02a0*/ @P0 BRA 0x350 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*02c0*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*02d0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*02e0*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*02f0*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*0300*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*0310*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*0330*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*0340*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0350*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0360*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0370*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0380*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc7002007950 */
/* 0x000fea0003c3ffff */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} | .file "tmpxft_00142375_00000000-6_mAddDrip.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8mAddDripPfiifPfiif
.type _Z30__device_stub__Z8mAddDripPfiifPfiif, @function
_Z30__device_stub__Z8mAddDripPfiifPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mAddDripPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8mAddDripPfiifPfiif, .-_Z30__device_stub__Z8mAddDripPfiifPfiif
.globl _Z8mAddDripPfiif
.type _Z8mAddDripPfiif, @function
_Z8mAddDripPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8mAddDripPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8mAddDripPfiif, .-_Z8mAddDripPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mAddDripPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mAddDripPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mAddDripPfiif
.globl _Z8mAddDripPfiif
.p2align 8
.type _Z8mAddDripPfiif,@function
_Z8mAddDripPfiif:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v1, s2, v0
s_sub_i32 s2, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s2
v_cvt_f32_i32_e32 v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, v1
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cmpx_gt_f32_e32 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x43480000, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mAddDripPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mAddDripPfiif, .Lfunc_end0-_Z8mAddDripPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mAddDripPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mAddDripPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mAddDrip(float *dense, int centerX, int centerY, float redius) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
float length = sqrt((float)((x-centerX)*(x-centerX))+(float)((y-centerY)*(y-centerY)));
if(length < redius) {
dense[Idx] += 200;
}
} | .text
.file "mAddDrip.hip"
.globl _Z23__device_stub__mAddDripPfiif # -- Begin function _Z23__device_stub__mAddDripPfiif
.p2align 4, 0x90
.type _Z23__device_stub__mAddDripPfiif,@function
_Z23__device_stub__mAddDripPfiif: # @_Z23__device_stub__mAddDripPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mAddDripPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mAddDripPfiif, .Lfunc_end0-_Z23__device_stub__mAddDripPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mAddDripPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mAddDripPfiif,@object # @_Z8mAddDripPfiif
.section .rodata,"a",@progbits
.globl _Z8mAddDripPfiif
.p2align 3, 0x0
_Z8mAddDripPfiif:
.quad _Z23__device_stub__mAddDripPfiif
.size _Z8mAddDripPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mAddDripPfiif"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mAddDripPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mAddDripPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mAddDripPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x190 ; /* 0x0000016000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0040*/ IADD3 R0, R7, -c[0x0][0x168], RZ ; /* 0x80005a0007007a10 */
/* 0x001fe40007ffe0ff */
/*0050*/ IADD3 R3, R6, -c[0x0][0x16c], RZ ; /* 0x80005b0006037a10 */
/* 0x002fc60007ffe0ff */
/*0060*/ IMAD R2, R0, R0, RZ ; /* 0x0000000000027224 */
/* 0x000fe400078e02ff */
/*0070*/ IMAD R3, R3, R3, RZ ; /* 0x0000000303037224 */
/* 0x000fc800078e02ff */
/*0080*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000ff00000201400 */
/*0090*/ I2F R3, R3 ; /* 0x0000000300037306 */
/* 0x000e240000201400 */
/*00a0*/ FADD R4, R2, R3 ; /* 0x0000000302047221 */
/* 0x001fcc0000000000 */
/*00b0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00c0*/ IADD3 R0, R4, -0xd000000, RZ ; /* 0xf300000004007810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*00e0*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x000fd800078e0207 */
/*00f0*/ @!P0 BRA 0x140 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0100*/ MOV R8, 0x120 ; /* 0x0000012000087802 */
/* 0x003fe40000000f00 */
/*0110*/ CALL.REL.NOINC 0x220 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0120*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe20000000f00 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R3, R3, R4 ; /* 0x0000000303027223 */
/* 0x000fc80000000104 */
/*0170*/ FFMA R2, R2, R5, R3 ; /* 0x0000000502027223 */
/* 0x000fe40000000003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0b */
/* 0x000fda0003f0e000 */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*01c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*01d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ FADD R5, R0, 200 ; /* 0x4348000000057421 */
/* 0x004fca0000000000 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*0230*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*0240*/ @!P0 BRA 0x350 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0260*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0270*/ @!P0 BRA 0x350 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0290*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*02a0*/ @P0 BRA 0x350 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*02c0*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*02d0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*02e0*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*02f0*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*0300*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*0310*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*0320*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*0330*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*0340*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0350*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0360*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0370*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0380*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffc7002007950 */
/* 0x000fea0003c3ffff */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mAddDripPfiif
.globl _Z8mAddDripPfiif
.p2align 8
.type _Z8mAddDripPfiif,@function
_Z8mAddDripPfiif:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v1, s2, v0
s_sub_i32 s2, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s2
v_cvt_f32_i32_e32 v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, v1
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cmpx_gt_f32_e32 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x43480000, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mAddDripPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mAddDripPfiif, .Lfunc_end0-_Z8mAddDripPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mAddDripPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mAddDripPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142375_00000000-6_mAddDrip.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8mAddDripPfiifPfiif
.type _Z30__device_stub__Z8mAddDripPfiifPfiif, @function
_Z30__device_stub__Z8mAddDripPfiifPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mAddDripPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z8mAddDripPfiifPfiif, .-_Z30__device_stub__Z8mAddDripPfiifPfiif
.globl _Z8mAddDripPfiif
.type _Z8mAddDripPfiif, @function
_Z8mAddDripPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8mAddDripPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8mAddDripPfiif, .-_Z8mAddDripPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mAddDripPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mAddDripPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mAddDrip.hip"
.globl _Z23__device_stub__mAddDripPfiif # -- Begin function _Z23__device_stub__mAddDripPfiif
.p2align 4, 0x90
.type _Z23__device_stub__mAddDripPfiif,@function
_Z23__device_stub__mAddDripPfiif: # @_Z23__device_stub__mAddDripPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mAddDripPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mAddDripPfiif, .Lfunc_end0-_Z23__device_stub__mAddDripPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mAddDripPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mAddDripPfiif,@object # @_Z8mAddDripPfiif
.section .rodata,"a",@progbits
.globl _Z8mAddDripPfiif
.p2align 3, 0x0
_Z8mAddDripPfiif:
.quad _Z23__device_stub__mAddDripPfiif
.size _Z8mAddDripPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mAddDripPfiif"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mAddDripPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mAddDripPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<fstream>
#include<time.h>
#include<sys/time.h>
#include<string>
using namespace std;
// #define num_threads 1000
#define lli long long int
int size[5] = {100, 500, 1000, 5000, 10000};
// int edges_2[5] = {200, 447, 1969, 4991, 200001};
int edges_8[5] = {801, 20000, 79580, 1999218, 8000000};
const lli num_edges = 8000000;
const lli num_vertices1 = 10000;
const lli num_vertices2 = 10000;
__device__ int d_flat_adj_list[2*num_edges];
__device__ int d_degree[num_vertices1+num_vertices2+1]={0}; //store degree of each vertex
__device__ int d_list_ptr[num_vertices1+num_vertices2+2]; //1-indexed and extra element at the end for easy size access // Pointer to the start of adjacency list
__device__ int d_list_ptr_copy[num_vertices1+num_vertices2+2]; //
__device__ bool d_matched_edge[2*num_edges]; // Tells for every edge in the list if the edge is matched or not
__device__ bool d_is_matched_vertex[num_vertices1 + num_vertices2 + 1] = {0}; //is the vertex matched
__device__ int d_partner_vertex[num_vertices1 + num_vertices2 + 1];
__device__ int d_visited[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_bfs_parent[num_vertices1 + num_vertices2 + 1];
__device__ bool d_is_parent_change[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_frontier[num_vertices1 + num_vertices2+1] = {0};
__device__ int d_next_frontier[num_vertices1+num_vertices2+1] = {0};
__device__ int num_aug_paths = 10000000; //Any number not equal to 0 works
int *h_flat_adj_list;
int *h_degree;
int * h_list_ptr;
int *h_list_ptr_copy;
bool *h_matched_edge;
bool *h_is_matched_vertex;
int *h_partner_vertex;
int *h_visited;
int *h_bfs_parent;
bool *h_is_parent_change;
int fc = num_vertices1;
// int num_aug_paths = 0;
int *h_frontier;
int *h_next_frontier;
__device__
bool get_matched_edge(int x, int y){
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i]==y){
return d_matched_edge[i];
}
}
printf("Error! Querying for an edge which is not present \n");
return -1;
}
__device__
void set_matched_edge(int x, int y, int value){
bool edge_present = false;
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == y){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
vertex = y;
start_edge = d_list_ptr[vertex];
end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == x){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
if(!edge_present){
printf("Error! Querying for an edge which is not present \n");
}
}
void print_matchings(){
cout << "Matchings: " << endl;
for(int i=1;i<=num_vertices1+num_vertices2; i++){
cout<< i << " " << h_partner_vertex[i] << endl;
}
}
int get_matched_edge_h(int x, int y){
int vertex = x;
int start_edge = h_list_ptr[vertex];
int end_edge = h_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(h_flat_adj_list[i] == y){
return h_matched_edge[i];
}
}
cout << "Error! Querying for an edge which is not present";
exit(0);
}
__device__
void match_edges(int u, int v){
set_matched_edge(u,v,1);
set_matched_edge(v,u,1);
d_is_matched_vertex[u] = 1;
d_is_matched_vertex[v] = 1;
d_partner_vertex[u] = v;
d_partner_vertex[v] = u;
}
// Unmatching edges also unmatches the vertices since the graph is a matching
__device__
void unmatch_edges(int u, int v){
set_matched_edge(u,v,0);
set_matched_edge(v,u,0);
if(d_partner_vertex[u]==v){
d_is_matched_vertex[u] = 0;
d_partner_vertex[u] = -1;
}
if(d_partner_vertex[v]==u){
d_is_matched_vertex[v] = 0;
d_partner_vertex[v] = -1;
}
}
// Make this parallel
__global__
void update_matchings(){
int tid = blockIdx.x*1024 + threadIdx.x;
for(int i=tid; i<=num_vertices1+num_vertices2; i+=num_vertices1){
int vertex = i;
if(d_is_parent_change[vertex] == true){
// cout << "Found aug. path till " << vertex << endl;
// There should always be odd number of vertices in aug. path
int path_length = 1;
int parent = d_bfs_parent[vertex];
while(parent!=vertex){
// cout << vertex << " " <<parent << endl;
if(path_length%2==1){
match_edges(vertex, parent);
// printf("Matching %d and %d \n", vertex, parent);
}
else{
unmatch_edges(vertex, parent);
// printf("Unmatching %d and %d \n", vertex, parent);
}
vertex = d_bfs_parent[vertex];
parent = d_bfs_parent[vertex];
path_length++;
}
}
}
}
__device__
void clear_visited(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_visited[vertex1] = 0;
}
}
__device__
void clear_bfs_parent(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_bfs_parent[vertex1] = vertex1;
}
}
__device__
void initialise_partner_vertex(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_partner_vertex[vertex1] = -1;
}
}
__device__
void clear_is_parent_change(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_is_parent_change[vertex1] = -1;
}
}
__device__
void copy_frontier(int *my_frontier, int *my_next_frontier){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = my_next_frontier[i];
}
}
__device__
void clear_frontier(int *my_frontier, int *my_next_frontier ){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = 0;
my_next_frontier[i] = 0;
}
}
__device__
void vertex_disjoint_bfs(int binary_level, int vertex, int tid){
int visited_self = atomicExch(&d_visited[vertex], 1);
if(visited_self && binary_level==0){
return;
}
d_visited[vertex] = true;
bool found_path = false;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int j=start_edge;j<end_edge;j++){
if(found_path)
break;
int neighbor = d_flat_adj_list[j];
if(neighbor > num_vertices1 + num_vertices2){
printf("[%d]Error(neighbor out of range: vertex, neighbor : %d, %d \n", tid, vertex, neighbor);
}
int visited = atomicExch(&d_visited[neighbor], 1);
if(!visited){
// We want to alternate between unmatched and matched edges, otherwise we ignore
d_visited[neighbor] = true;
d_bfs_parent[neighbor] = vertex;
if( binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==1 ){
d_next_frontier[neighbor] = 1;
if(binary_level==1)
printf("Going odd %d \n", vertex);
vertex_disjoint_bfs(!binary_level, neighbor, tid);
}
// In level 1, we are only interested in matched edges
else if( binary_level==1 && get_matched_edge(vertex, neighbor)==1 ){
d_next_frontier[neighbor] = 1;
vertex_disjoint_bfs(!binary_level, neighbor, tid);
return;
}
// Changing parent change only for this node
else if(binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==0){
d_is_parent_change[neighbor] = 1;
// atomicAdd(&num_aug_paths, 1);
num_aug_paths++;
return;
}
}
}
}
__global__
void vertex_disjoint_bfs_util(){
// parallelise these functions
clear_visited();
clear_bfs_parent();
clear_is_parent_change();
// clear_frontier(my_frontier, my_next_frontier );
initialise_partner_vertex();
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex = tid+1;
if(vertex > num_vertices1)
return;
if(vertex >= num_vertices1+num_vertices2+1)
printf("[%d] Error \n");
if(!d_visited[vertex] && !d_is_matched_vertex[vertex]){
d_frontier[vertex] = 1;
vertex_disjoint_bfs(0, vertex, tid);
}
}
int check_matching(){
int total_matched = 0;
for(int i=1;i<=num_vertices1+num_vertices2;i++){
int vertex = i;
int num_matched = 0;
for(int j=h_list_ptr[i];j<h_list_ptr[i+1];j++){
int neighbor = h_flat_adj_list[j];
// cout << vertex << " " << neighbor << endl;
if(get_matched_edge_h(vertex, neighbor)){
num_matched++;
}
}
if(num_matched==1){
// cout << "Hi" << endl;
total_matched++;
}
if(num_matched>1){
cout << vertex << endl;
cout << "Error! Not a matching!";
exit(0);
}
}
return total_matched/2;
}
int main(){
struct timespec start, end;
// h_is_matched_edge = (bool *)calloc( (num_vertices1+ num_vertices2 + 1)*(num_vertices1 + num_vertices2+1), sizeof(bool));
h_matched_edge = (bool *)calloc(2*num_edges, sizeof(bool));
h_flat_adj_list = (int *)malloc(2*num_edges*sizeof(int));
h_degree = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_list_ptr = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_list_ptr_copy = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_is_matched_vertex = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_partner_vertex = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_visited = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_bfs_parent = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_is_parent_change = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_next_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
// Add a check for null memory
memset(h_degree, 0, num_vertices1 + num_vertices2 +1);
// memset(h_is_matched_edge, 0, (num_vertices1 + num_vertices2 +1)*(num_vertices1+num_vertices2+1));
memset(h_is_matched_vertex, 0, num_vertices1 + num_vertices2 +1);
memset(h_visited, 0, num_vertices1 + num_vertices2 +1);
memset(h_is_parent_change, 0, num_vertices1 + num_vertices2 +1);
memset(h_frontier, 0, num_vertices1 + num_vertices2 +1);
memset(h_next_frontier, 0, num_vertices1 + num_vertices2 +1);
// to and from of edges
// int h_edges_u[num_edges], h_edges_v[num_edges]; // Make this dynamic memory and free it once we have our 2 pass initialisation phase
int *h_edges_u, *h_edges_v;
h_edges_u = (int *)malloc((num_edges)*sizeof(int));
h_edges_v = (int *)malloc((num_edges)*sizeof(int));
ifstream fin;
fin.open("random_10000_10000_high.txt", ios::in);
int u, v;
// Vertices with 0 edges are implicitly ignored while reading the file itself
for(int i=0;i<num_edges;i++){
// cout << i << endl;
fin >> u >> v;
h_edges_u[i] = u;
h_edges_v[i] = v;
h_degree[u]++;
h_degree[v]++;
}
cout << "Done reading edges" << endl;
// Get pointer to adjacency list using prefix sum (no opti here since other parts are more complex anyway)
// Index 0 will never be used.... the last elem
h_list_ptr[1] = 0;
h_list_ptr_copy[1] = h_list_ptr[1];
for(int i=2;i<=num_vertices1+num_vertices2;i++){
h_list_ptr[i] = h_list_ptr[i-1] + h_degree[i-1];
h_list_ptr_copy[i] = h_list_ptr[i];
}
h_list_ptr[num_vertices1+num_vertices2+1] = 2*num_edges; //For easy coding
h_list_ptr_copy[num_vertices1+num_vertices2+1] = 2*num_edges; // list_ptr has the start of the adj list ; list_ptr_copy has the current position
for(int i=0;i<num_edges;i++){
h_flat_adj_list[h_list_ptr_copy[h_edges_u[i]]] = h_edges_v[i];
h_flat_adj_list[h_list_ptr_copy[h_edges_v[i]]] = h_edges_u[i];
h_list_ptr_copy[h_edges_u[i]]++;
h_list_ptr_copy[h_edges_v[i]]++;
}
clock_gettime( CLOCK_REALTIME,&start);
cudaMemcpyToSymbol(d_matched_edge, h_matched_edge, (2*num_edges)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_flat_adj_list, h_flat_adj_list, 2*num_edges*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_degree, h_degree, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_list_ptr, h_list_ptr, (num_vertices1+num_vertices2+2)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_is_matched_vertex, h_is_matched_vertex, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_visited, h_visited, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_frontier, h_frontier, (num_vertices1+num_vertices2+2)*sizeof(int),0,cudaMemcpyHostToDevice);
int h_num_aug_paths = 1000;
cudaDeviceSynchronize();
while(h_num_aug_paths>0){
h_num_aug_paths = 0;
cudaMemcpyToSymbol(num_aug_paths, &h_num_aug_paths, (1)*sizeof(int),0,cudaMemcpyHostToDevice);
vertex_disjoint_bfs_util<<<10, 1024>>>();
update_matchings<<<10, 1024>>>();
cudaDeviceSynchronize();
cudaMemcpyFromSymbol(&h_num_aug_paths, num_aug_paths, sizeof(num_aug_paths),0,cudaMemcpyDeviceToHost);
break;
}
clock_gettime( CLOCK_REALTIME,&end);
cudaMemcpyFromSymbol(h_matched_edge, d_matched_edge, sizeof(d_matched_edge),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(h_partner_vertex, d_partner_vertex, sizeof(d_partner_vertex),0,cudaMemcpyDeviceToHost);
printf("Number of augmenting paths(actual number may be higher): %d \n", h_num_aug_paths);
int num_matches = check_matching();
printf("Number of matchings: %d \n", num_matches);
double elapsed = (end.tv_sec-start.tv_sec)*1000000000 + end.tv_nsec-start.tv_nsec;
printf("Time elapsed %lf\n", elapsed/1e6);
cudaDeviceSynchronize();
} | .file "tmpxft_0013c642_00000000-6_parallel_matching.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3817:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3817:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16get_matched_edgeii
.type _Z16get_matched_edgeii, @function
_Z16get_matched_edgeii:
.LFB3800:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3800:
.size _Z16get_matched_edgeii, .-_Z16get_matched_edgeii
.globl _Z16set_matched_edgeiii
.type _Z16set_matched_edgeiii, @function
_Z16set_matched_edgeiii:
.LFB3801:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3801:
.size _Z16set_matched_edgeiii, .-_Z16set_matched_edgeiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matchings: "
.LC1:
.string " "
.text
.globl _Z15print_matchingsv
.type _Z15print_matchingsv, @function
_Z15print_matchingsv:
.LFB3802:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $11, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L17
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %eax
.L10:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4, %r12d
movl $1, %ebp
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L14
.L17:
call _ZSt16__throw_bad_castv@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L10
.L19:
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L13:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
addq $4, %r12
cmpl $20001, %ebp
je .L18
.L14:
movl %ebp, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq h_partner_vertex(%rip), %rax
movl (%rax,%r12), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L19
cmpb $0, 56(%r15)
je .L12
movzbl 67(%r15), %esi
jmp .L13
.L18:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3802:
.size _Z15print_matchingsv, .-_Z15print_matchingsv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Error! Querying for an edge which is not present"
.text
.globl _Z18get_matched_edge_hii
.type _Z18get_matched_edge_hii, @function
_Z18get_matched_edge_hii:
.LFB3803:
.cfi_startproc
endbr64
movq h_list_ptr(%rip), %rdx
movslq %edi, %rdi
movl (%rdx,%rdi,4), %eax
movl 4(%rdx,%rdi,4), %edx
cmpl %edx, %eax
jge .L21
movq h_flat_adj_list(%rip), %rcx
cltq
.L23:
cmpl %esi, (%rcx,%rax,4)
je .L26
addq $1, %rax
cmpl %eax, %edx
jg .L23
.L21:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $48, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %edi
call exit@PLT
.L26:
.cfi_def_cfa_offset 8
movq h_matched_edge(%rip), %rdx
movzbl (%rdx,%rax), %eax
ret
.cfi_endproc
.LFE3803:
.size _Z18get_matched_edge_hii, .-_Z18get_matched_edge_hii
.globl _Z11match_edgesii
.type _Z11match_edgesii, @function
_Z11match_edgesii:
.LFB3804:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3804:
.size _Z11match_edgesii, .-_Z11match_edgesii
.globl _Z13unmatch_edgesii
.type _Z13unmatch_edgesii, @function
_Z13unmatch_edgesii:
.LFB3805:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3805:
.size _Z13unmatch_edgesii, .-_Z13unmatch_edgesii
.globl _Z13clear_visitedv
.type _Z13clear_visitedv, @function
_Z13clear_visitedv:
.LFB3806:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3806:
.size _Z13clear_visitedv, .-_Z13clear_visitedv
.globl _Z16clear_bfs_parentv
.type _Z16clear_bfs_parentv, @function
_Z16clear_bfs_parentv:
.LFB3807:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3807:
.size _Z16clear_bfs_parentv, .-_Z16clear_bfs_parentv
.globl _Z25initialise_partner_vertexv
.type _Z25initialise_partner_vertexv, @function
_Z25initialise_partner_vertexv:
.LFB3808:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3808:
.size _Z25initialise_partner_vertexv, .-_Z25initialise_partner_vertexv
.globl _Z22clear_is_parent_changev
.type _Z22clear_is_parent_changev, @function
_Z22clear_is_parent_changev:
.LFB3809:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3809:
.size _Z22clear_is_parent_changev, .-_Z22clear_is_parent_changev
.globl _Z13copy_frontierPiS_
.type _Z13copy_frontierPiS_, @function
_Z13copy_frontierPiS_:
.LFB3810:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3810:
.size _Z13copy_frontierPiS_, .-_Z13copy_frontierPiS_
.globl _Z14clear_frontierPiS_
.type _Z14clear_frontierPiS_, @function
_Z14clear_frontierPiS_:
.LFB3811:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3811:
.size _Z14clear_frontierPiS_, .-_Z14clear_frontierPiS_
.globl _Z19vertex_disjoint_bfsiii
.type _Z19vertex_disjoint_bfsiii, @function
_Z19vertex_disjoint_bfsiii:
.LFB3812:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3812:
.size _Z19vertex_disjoint_bfsiii, .-_Z19vertex_disjoint_bfsiii
.section .rodata.str1.1
.LC3:
.string "Error! Not a matching!"
.text
.globl _Z14check_matchingv
.type _Z14check_matchingv, @function
_Z14check_matchingv:
.LFB3813:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $0, %r15d
movl $0, 12(%rsp)
jmp .L55
.L60:
addl $1, 12(%rsp)
.L48:
addq $1, %r15
cmpq $20000, %r15
je .L59
.L55:
leal 1(%r15), %r13d
movq h_list_ptr(%rip), %rdx
leaq 1(%r15), %rcx
leaq 0(,%rcx,4), %rax
movl (%rdx,%rcx,4), %ebx
leaq 4(%rax), %r14
cmpl 4(%rdx,%rax), %ebx
jge .L48
movslq %ebx, %rbp
salq $2, %rbp
movl $0, %r12d
.L50:
movq h_flat_adj_list(%rip), %rax
movl (%rax,%rbp), %esi
movl %r13d, %edi
call _Z18get_matched_edge_hii
cmpl $1, %eax
sbbl $-1, %r12d
addl $1, %ebx
addq $4, %rbp
movq h_list_ptr(%rip), %rax
cmpl %ebx, (%rax,%r14)
jg .L50
cmpl $1, %r12d
je .L60
jle .L48
movl %r13d, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L61
cmpb $0, 56(%rbp)
je .L53
movzbl 67(%rbp), %esi
.L54:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %edi
call exit@PLT
.L61:
call _ZSt16__throw_bad_castv@PLT
.L53:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L54
.L59:
movl 12(%rsp), %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3813:
.size _Z14check_matchingv, .-_Z14check_matchingv
.globl _Z35__device_stub__Z16update_matchingsvv
.type _Z35__device_stub__Z16update_matchingsvv, @function
_Z35__device_stub__Z16update_matchingsvv:
.LFB3839:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16update_matchingsv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3839:
.size _Z35__device_stub__Z16update_matchingsvv, .-_Z35__device_stub__Z16update_matchingsvv
.globl _Z16update_matchingsv
.type _Z16update_matchingsv, @function
_Z16update_matchingsv:
.LFB3840:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16update_matchingsvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3840:
.size _Z16update_matchingsv, .-_Z16update_matchingsv
.globl _Z43__device_stub__Z24vertex_disjoint_bfs_utilvv
.type _Z43__device_stub__Z24vertex_disjoint_bfs_utilvv, @function
_Z43__device_stub__Z24vertex_disjoint_bfs_utilvv:
.LFB3841:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L74
.L70:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L75
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z24vertex_disjoint_bfs_utilv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L70
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3841:
.size _Z43__device_stub__Z24vertex_disjoint_bfs_utilvv, .-_Z43__device_stub__Z24vertex_disjoint_bfs_utilvv
.globl _Z24vertex_disjoint_bfs_utilv
.type _Z24vertex_disjoint_bfs_utilv, @function
_Z24vertex_disjoint_bfs_utilv:
.LFB3842:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24vertex_disjoint_bfs_utilvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3842:
.size _Z24vertex_disjoint_bfs_utilv, .-_Z24vertex_disjoint_bfs_utilv
.section .rodata.str1.1
.LC4:
.string "_Z24vertex_disjoint_bfs_utilv"
.LC5:
.string "_Z16update_matchingsv"
.LC6:
.string "d_flat_adj_list"
.LC7:
.string "d_degree"
.LC8:
.string "d_list_ptr"
.LC9:
.string "d_list_ptr_copy"
.LC10:
.string "d_matched_edge"
.LC11:
.string "d_is_matched_vertex"
.LC12:
.string "d_partner_vertex"
.LC13:
.string "d_visited"
.LC14:
.string "d_bfs_parent"
.LC15:
.string "d_is_parent_change"
.LC16:
.string "d_frontier"
.LC17:
.string "d_next_frontier"
.LC18:
.string "num_aug_paths"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3844:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z24vertex_disjoint_bfs_utilv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z16update_matchingsv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $64000000, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15d_flat_adj_list(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8d_degree(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80008, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10d_list_ptr(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80008, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15d_list_ptr_copy(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $16000000, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14d_matched_edge(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $20001, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19d_is_matched_vertex(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16d_partner_vertex(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9d_visited(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12d_bfs_parent(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $20001, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL18d_is_parent_change(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10d_frontier(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $80004, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15d_next_frontier(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13num_aug_paths(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3844:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC19:
.string "random_10000_10000_high.txt"
.LC20:
.string "Done reading edges"
.section .rodata.str1.8
.align 8
.LC21:
.string "Number of augmenting paths(actual number may be higher): %d \n"
.section .rodata.str1.1
.LC22:
.string "Number of matchings: %d \n"
.LC24:
.string "Time elapsed %lf\n"
.text
.globl main
.type main, @function
main:
.LFB3814:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3814
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
movl $1, %esi
movl $16000000, %edi
call calloc@PLT
movq %rax, h_matched_edge(%rip)
movl $64000000, %edi
call malloc@PLT
movq %rax, h_flat_adj_list(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, %r15
movq %rax, h_degree(%rip)
movl $80008, %edi
call malloc@PLT
movq %rax, h_list_ptr(%rip)
movl $80008, %edi
call malloc@PLT
movq %rax, h_list_ptr_copy(%rip)
movl $20001, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, h_is_matched_vertex(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, h_partner_vertex(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, h_visited(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, h_bfs_parent(%rip)
movl $20001, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, h_is_parent_change(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, h_frontier(%rip)
movl $80004, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, h_next_frontier(%rip)
movl $20001, %edx
movl $0, %esi
movq %r15, %rdi
call memset@PLT
movl $20001, %edx
movl $0, %esi
movq %r14, %rdi
call memset@PLT
movl $20001, %edx
movl $0, %esi
movq %r13, %rdi
call memset@PLT
movl $20001, %edx
movl $0, %esi
movq %r12, %rdi
call memset@PLT
movl $20001, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
movl $20001, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
movl $32000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $32000000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 64(%rsp), %r12
movq %r12, %rdi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
movl $8, %edx
leaq .LC19(%rip), %rsi
movq %r12, %rdi
.LEHB1:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $0, %r12d
leaq 8(%rsp), %r13
jmp .L81
.L100:
movq %rax, %rdi
leaq 12(%rsp), %rsi
call _ZNSirsERi@PLT
movl 8(%rsp), %eax
movl %eax, (%rbx,%r12)
movl 12(%rsp), %edx
movl %edx, 0(%rbp,%r12)
cltq
movq h_degree(%rip), %rdx
addl $1, (%rdx,%rax,4)
movslq 12(%rsp), %rdx
movq h_degree(%rip), %rax
addl $1, (%rax,%rdx,4)
addq $4, %r12
cmpq $32000000, %r12
je .L99
.L81:
leaq 64(%rsp), %rdi
movq %r13, %rsi
call _ZNSirsERi@PLT
jmp .L100
.L99:
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq h_list_ptr(%rip), %rax
movl $0, 4(%rax)
movq h_list_ptr(%rip), %rax
movl 4(%rax), %edx
movq h_list_ptr_copy(%rip), %rax
movl %edx, 4(%rax)
movl $4, %eax
.L82:
movq h_list_ptr(%rip), %rcx
movq %rax, %rsi
addq $4, %rax
movl (%rcx,%rsi), %edx
movq h_degree(%rip), %rdi
addl (%rdi,%rsi), %edx
movl %edx, (%rcx,%rax)
movq h_list_ptr(%rip), %rdx
movl (%rdx,%rax), %ecx
movq h_list_ptr_copy(%rip), %rdx
movl %ecx, (%rdx,%rax)
cmpq $80000, %rax
jne .L82
movq h_list_ptr(%rip), %rax
movl $16000000, 80004(%rax)
movq h_list_ptr_copy(%rip), %rax
movl $16000000, 80004(%rax)
movl $0, %edx
.L83:
movl (%rbx,%rdx), %esi
movslq %esi, %rcx
movl 0(%rbp,%rdx), %eax
movq h_list_ptr_copy(%rip), %rdi
movslq (%rdi,%rcx,4), %r8
movq h_flat_adj_list(%rip), %rdi
movl %eax, (%rdi,%r8,4)
cltq
movq h_list_ptr_copy(%rip), %rdi
movslq (%rdi,%rax,4), %r8
movq h_flat_adj_list(%rip), %rdi
movl %esi, (%rdi,%r8,4)
movq h_list_ptr_copy(%rip), %rsi
addl $1, (%rsi,%rcx,4)
movq h_list_ptr_copy(%rip), %rcx
addl $1, (%rcx,%rax,4)
addq $4, %rdx
cmpq $32000000, %rdx
jne .L83
leaq 32(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %r8d
movl $0, %ecx
movl $64000000, %edx
movq h_matched_edge(%rip), %rsi
leaq _ZL14d_matched_edge(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $64000000, %edx
movq h_flat_adj_list(%rip), %rsi
leaq _ZL15d_flat_adj_list(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $80004, %edx
movq h_degree(%rip), %rsi
leaq _ZL8d_degree(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $80008, %edx
movq h_list_ptr(%rip), %rsi
leaq _ZL10d_list_ptr(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $80004, %edx
movq h_is_matched_vertex(%rip), %rsi
leaq _ZL19d_is_matched_vertex(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $80004, %edx
movq h_visited(%rip), %rsi
leaq _ZL9d_visited(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1, %r8d
movl $0, %ecx
movl $80008, %edx
movq h_frontier(%rip), %rsi
leaq _ZL10d_frontier(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $1000, 16(%rsp)
call cudaDeviceSynchronize@PLT
jmp .L101
.L102:
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L85
call _Z43__device_stub__Z24vertex_disjoint_bfs_utilvv
.L85:
movl $1024, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
call _Z35__device_stub__Z16update_matchingsvv
.L86:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL13num_aug_paths(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
jmp .L87
.L101:
cmpl $0, 16(%rsp)
jle .L87
movl $0, 16(%rsp)
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL13num_aug_paths(%rip), %rdi
call cudaMemcpyToSymbol@PLT
jmp .L102
.L87:
leaq 48(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $2, %r8d
movl $0, %ecx
movl $16000000, %edx
leaq _ZL14d_matched_edge(%rip), %rsi
movq h_matched_edge(%rip), %rdi
call cudaMemcpyFromSymbol@PLT
movl $2, %r8d
movl $0, %ecx
movl $80004, %edx
leaq _ZL16d_partner_vertex(%rip), %rsi
movq h_partner_vertex(%rip), %rdi
call cudaMemcpyFromSymbol@PLT
movl 16(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z14check_matchingv
movl %eax, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
.LEHE1:
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L103
movl $0, %eax
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 584(%rsp), %rax
subq %fs:40, %rax
je .L90
call __stack_chk_fail@PLT
.L90:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3814:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3814:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3814-.LLSDACSB3814
.LLSDACSB3814:
.uleb128 .LEHB0-.LFB3814
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3814
.uleb128 .LEHE1-.LEHB1
.uleb128 .L92-.LFB3814
.uleb128 0
.uleb128 .LEHB2-.LFB3814
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3814:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl h_next_frontier
.bss
.align 8
.type h_next_frontier, @object
.size h_next_frontier, 8
h_next_frontier:
.zero 8
.globl h_frontier
.align 8
.type h_frontier, @object
.size h_frontier, 8
h_frontier:
.zero 8
.globl fc
.data
.align 4
.type fc, @object
.size fc, 4
fc:
.long 10000
.globl h_is_parent_change
.bss
.align 8
.type h_is_parent_change, @object
.size h_is_parent_change, 8
h_is_parent_change:
.zero 8
.globl h_bfs_parent
.align 8
.type h_bfs_parent, @object
.size h_bfs_parent, 8
h_bfs_parent:
.zero 8
.globl h_visited
.align 8
.type h_visited, @object
.size h_visited, 8
h_visited:
.zero 8
.globl h_partner_vertex
.align 8
.type h_partner_vertex, @object
.size h_partner_vertex, 8
h_partner_vertex:
.zero 8
.globl h_is_matched_vertex
.align 8
.type h_is_matched_vertex, @object
.size h_is_matched_vertex, 8
h_is_matched_vertex:
.zero 8
.globl h_matched_edge
.align 8
.type h_matched_edge, @object
.size h_matched_edge, 8
h_matched_edge:
.zero 8
.globl h_list_ptr_copy
.align 8
.type h_list_ptr_copy, @object
.size h_list_ptr_copy, 8
h_list_ptr_copy:
.zero 8
.globl h_list_ptr
.align 8
.type h_list_ptr, @object
.size h_list_ptr, 8
h_list_ptr:
.zero 8
.globl h_degree
.align 8
.type h_degree, @object
.size h_degree, 8
h_degree:
.zero 8
.globl h_flat_adj_list
.align 8
.type h_flat_adj_list, @object
.size h_flat_adj_list, 8
h_flat_adj_list:
.zero 8
.local _ZL13num_aug_paths
.comm _ZL13num_aug_paths,4,4
.local _ZL15d_next_frontier
.comm _ZL15d_next_frontier,80004,32
.local _ZL10d_frontier
.comm _ZL10d_frontier,80004,32
.local _ZL18d_is_parent_change
.comm _ZL18d_is_parent_change,20001,32
.local _ZL12d_bfs_parent
.comm _ZL12d_bfs_parent,80004,32
.local _ZL9d_visited
.comm _ZL9d_visited,80004,32
.local _ZL16d_partner_vertex
.comm _ZL16d_partner_vertex,80004,32
.local _ZL19d_is_matched_vertex
.comm _ZL19d_is_matched_vertex,20001,32
.local _ZL14d_matched_edge
.comm _ZL14d_matched_edge,16000000,32
.local _ZL15d_list_ptr_copy
.comm _ZL15d_list_ptr_copy,80008,32
.local _ZL10d_list_ptr
.comm _ZL10d_list_ptr,80008,32
.local _ZL8d_degree
.comm _ZL8d_degree,80004,32
.local _ZL15d_flat_adj_list
.comm _ZL15d_flat_adj_list,64000000,32
.globl edges_8
.data
.align 16
.type edges_8, @object
.size edges_8, 20
edges_8:
.long 801
.long 20000
.long 79580
.long 1999218
.long 8000000
.globl size
.align 16
.type size, @object
.size size, 20
size:
.long 100
.long 500
.long 1000
.long 5000
.long 10000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC23:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<fstream>
#include<time.h>
#include<sys/time.h>
#include<string>
using namespace std;
// #define num_threads 1000
#define lli long long int
int size[5] = {100, 500, 1000, 5000, 10000};
// int edges_2[5] = {200, 447, 1969, 4991, 200001};
int edges_8[5] = {801, 20000, 79580, 1999218, 8000000};
const lli num_edges = 8000000;
const lli num_vertices1 = 10000;
const lli num_vertices2 = 10000;
__device__ int d_flat_adj_list[2*num_edges];
__device__ int d_degree[num_vertices1+num_vertices2+1]={0}; //store degree of each vertex
__device__ int d_list_ptr[num_vertices1+num_vertices2+2]; //1-indexed and extra element at the end for easy size access // Pointer to the start of adjacency list
__device__ int d_list_ptr_copy[num_vertices1+num_vertices2+2]; //
__device__ bool d_matched_edge[2*num_edges]; // Tells for every edge in the list if the edge is matched or not
__device__ bool d_is_matched_vertex[num_vertices1 + num_vertices2 + 1] = {0}; //is the vertex matched
__device__ int d_partner_vertex[num_vertices1 + num_vertices2 + 1];
__device__ int d_visited[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_bfs_parent[num_vertices1 + num_vertices2 + 1];
__device__ bool d_is_parent_change[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_frontier[num_vertices1 + num_vertices2+1] = {0};
__device__ int d_next_frontier[num_vertices1+num_vertices2+1] = {0};
__device__ int num_aug_paths = 10000000; //Any number not equal to 0 works
int *h_flat_adj_list;
int *h_degree;
int * h_list_ptr;
int *h_list_ptr_copy;
bool *h_matched_edge;
bool *h_is_matched_vertex;
int *h_partner_vertex;
int *h_visited;
int *h_bfs_parent;
bool *h_is_parent_change;
int fc = num_vertices1;
// int num_aug_paths = 0;
int *h_frontier;
int *h_next_frontier;
__device__
bool get_matched_edge(int x, int y){
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i]==y){
return d_matched_edge[i];
}
}
printf("Error! Querying for an edge which is not present \n");
return -1;
}
__device__
void set_matched_edge(int x, int y, int value){
bool edge_present = false;
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == y){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
vertex = y;
start_edge = d_list_ptr[vertex];
end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == x){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
if(!edge_present){
printf("Error! Querying for an edge which is not present \n");
}
}
void print_matchings(){
cout << "Matchings: " << endl;
for(int i=1;i<=num_vertices1+num_vertices2; i++){
cout<< i << " " << h_partner_vertex[i] << endl;
}
}
int get_matched_edge_h(int x, int y){
int vertex = x;
int start_edge = h_list_ptr[vertex];
int end_edge = h_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(h_flat_adj_list[i] == y){
return h_matched_edge[i];
}
}
cout << "Error! Querying for an edge which is not present";
exit(0);
}
__device__
void match_edges(int u, int v){
set_matched_edge(u,v,1);
set_matched_edge(v,u,1);
d_is_matched_vertex[u] = 1;
d_is_matched_vertex[v] = 1;
d_partner_vertex[u] = v;
d_partner_vertex[v] = u;
}
// Unmatching edges also unmatches the vertices since the graph is a matching
__device__
void unmatch_edges(int u, int v){
set_matched_edge(u,v,0);
set_matched_edge(v,u,0);
if(d_partner_vertex[u]==v){
d_is_matched_vertex[u] = 0;
d_partner_vertex[u] = -1;
}
if(d_partner_vertex[v]==u){
d_is_matched_vertex[v] = 0;
d_partner_vertex[v] = -1;
}
}
// Make this parallel
__global__
void update_matchings(){
int tid = blockIdx.x*1024 + threadIdx.x;
for(int i=tid; i<=num_vertices1+num_vertices2; i+=num_vertices1){
int vertex = i;
if(d_is_parent_change[vertex] == true){
// cout << "Found aug. path till " << vertex << endl;
// There should always be odd number of vertices in aug. path
int path_length = 1;
int parent = d_bfs_parent[vertex];
while(parent!=vertex){
// cout << vertex << " " <<parent << endl;
if(path_length%2==1){
match_edges(vertex, parent);
// printf("Matching %d and %d \n", vertex, parent);
}
else{
unmatch_edges(vertex, parent);
// printf("Unmatching %d and %d \n", vertex, parent);
}
vertex = d_bfs_parent[vertex];
parent = d_bfs_parent[vertex];
path_length++;
}
}
}
}
__device__
void clear_visited(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_visited[vertex1] = 0;
}
}
__device__
void clear_bfs_parent(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_bfs_parent[vertex1] = vertex1;
}
}
__device__
void initialise_partner_vertex(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_partner_vertex[vertex1] = -1;
}
}
__device__
void clear_is_parent_change(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_is_parent_change[vertex1] = -1;
}
}
__device__
void copy_frontier(int *my_frontier, int *my_next_frontier){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = my_next_frontier[i];
}
}
__device__
void clear_frontier(int *my_frontier, int *my_next_frontier ){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = 0;
my_next_frontier[i] = 0;
}
}
__device__
void vertex_disjoint_bfs(int binary_level, int vertex, int tid){
int visited_self = atomicExch(&d_visited[vertex], 1);
if(visited_self && binary_level==0){
return;
}
d_visited[vertex] = true;
bool found_path = false;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int j=start_edge;j<end_edge;j++){
if(found_path)
break;
int neighbor = d_flat_adj_list[j];
if(neighbor > num_vertices1 + num_vertices2){
printf("[%d]Error(neighbor out of range: vertex, neighbor : %d, %d \n", tid, vertex, neighbor);
}
int visited = atomicExch(&d_visited[neighbor], 1);
if(!visited){
// We want to alternate between unmatched and matched edges, otherwise we ignore
d_visited[neighbor] = true;
d_bfs_parent[neighbor] = vertex;
if( binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==1 ){
d_next_frontier[neighbor] = 1;
if(binary_level==1)
printf("Going odd %d \n", vertex);
vertex_disjoint_bfs(!binary_level, neighbor, tid);
}
// In level 1, we are only interested in matched edges
else if( binary_level==1 && get_matched_edge(vertex, neighbor)==1 ){
d_next_frontier[neighbor] = 1;
vertex_disjoint_bfs(!binary_level, neighbor, tid);
return;
}
// Changing parent change only for this node
else if(binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==0){
d_is_parent_change[neighbor] = 1;
// atomicAdd(&num_aug_paths, 1);
num_aug_paths++;
return;
}
}
}
}
__global__
void vertex_disjoint_bfs_util(){
// parallelise these functions
clear_visited();
clear_bfs_parent();
clear_is_parent_change();
// clear_frontier(my_frontier, my_next_frontier );
initialise_partner_vertex();
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex = tid+1;
if(vertex > num_vertices1)
return;
if(vertex >= num_vertices1+num_vertices2+1)
printf("[%d] Error \n");
if(!d_visited[vertex] && !d_is_matched_vertex[vertex]){
d_frontier[vertex] = 1;
vertex_disjoint_bfs(0, vertex, tid);
}
}
int check_matching(){
int total_matched = 0;
for(int i=1;i<=num_vertices1+num_vertices2;i++){
int vertex = i;
int num_matched = 0;
for(int j=h_list_ptr[i];j<h_list_ptr[i+1];j++){
int neighbor = h_flat_adj_list[j];
// cout << vertex << " " << neighbor << endl;
if(get_matched_edge_h(vertex, neighbor)){
num_matched++;
}
}
if(num_matched==1){
// cout << "Hi" << endl;
total_matched++;
}
if(num_matched>1){
cout << vertex << endl;
cout << "Error! Not a matching!";
exit(0);
}
}
return total_matched/2;
}
int main(){
struct timespec start, end;
// h_is_matched_edge = (bool *)calloc( (num_vertices1+ num_vertices2 + 1)*(num_vertices1 + num_vertices2+1), sizeof(bool));
h_matched_edge = (bool *)calloc(2*num_edges, sizeof(bool));
h_flat_adj_list = (int *)malloc(2*num_edges*sizeof(int));
h_degree = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_list_ptr = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_list_ptr_copy = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_is_matched_vertex = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_partner_vertex = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_visited = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_bfs_parent = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_is_parent_change = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_next_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
// Add a check for null memory
memset(h_degree, 0, num_vertices1 + num_vertices2 +1);
// memset(h_is_matched_edge, 0, (num_vertices1 + num_vertices2 +1)*(num_vertices1+num_vertices2+1));
memset(h_is_matched_vertex, 0, num_vertices1 + num_vertices2 +1);
memset(h_visited, 0, num_vertices1 + num_vertices2 +1);
memset(h_is_parent_change, 0, num_vertices1 + num_vertices2 +1);
memset(h_frontier, 0, num_vertices1 + num_vertices2 +1);
memset(h_next_frontier, 0, num_vertices1 + num_vertices2 +1);
// to and from of edges
// int h_edges_u[num_edges], h_edges_v[num_edges]; // Make this dynamic memory and free it once we have our 2 pass initialisation phase
int *h_edges_u, *h_edges_v;
h_edges_u = (int *)malloc((num_edges)*sizeof(int));
h_edges_v = (int *)malloc((num_edges)*sizeof(int));
ifstream fin;
fin.open("random_10000_10000_high.txt", ios::in);
int u, v;
// Vertices with 0 edges are implicitly ignored while reading the file itself
for(int i=0;i<num_edges;i++){
// cout << i << endl;
fin >> u >> v;
h_edges_u[i] = u;
h_edges_v[i] = v;
h_degree[u]++;
h_degree[v]++;
}
cout << "Done reading edges" << endl;
// Get pointer to adjacency list using prefix sum (no opti here since other parts are more complex anyway)
// Index 0 will never be used.... the last elem
h_list_ptr[1] = 0;
h_list_ptr_copy[1] = h_list_ptr[1];
for(int i=2;i<=num_vertices1+num_vertices2;i++){
h_list_ptr[i] = h_list_ptr[i-1] + h_degree[i-1];
h_list_ptr_copy[i] = h_list_ptr[i];
}
h_list_ptr[num_vertices1+num_vertices2+1] = 2*num_edges; //For easy coding
h_list_ptr_copy[num_vertices1+num_vertices2+1] = 2*num_edges; // list_ptr has the start of the adj list ; list_ptr_copy has the current position
for(int i=0;i<num_edges;i++){
h_flat_adj_list[h_list_ptr_copy[h_edges_u[i]]] = h_edges_v[i];
h_flat_adj_list[h_list_ptr_copy[h_edges_v[i]]] = h_edges_u[i];
h_list_ptr_copy[h_edges_u[i]]++;
h_list_ptr_copy[h_edges_v[i]]++;
}
clock_gettime( CLOCK_REALTIME,&start);
cudaMemcpyToSymbol(d_matched_edge, h_matched_edge, (2*num_edges)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_flat_adj_list, h_flat_adj_list, 2*num_edges*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_degree, h_degree, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_list_ptr, h_list_ptr, (num_vertices1+num_vertices2+2)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_is_matched_vertex, h_is_matched_vertex, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_visited, h_visited, (num_vertices1+num_vertices2+1)*sizeof(int),0,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(d_frontier, h_frontier, (num_vertices1+num_vertices2+2)*sizeof(int),0,cudaMemcpyHostToDevice);
int h_num_aug_paths = 1000;
cudaDeviceSynchronize();
while(h_num_aug_paths>0){
h_num_aug_paths = 0;
cudaMemcpyToSymbol(num_aug_paths, &h_num_aug_paths, (1)*sizeof(int),0,cudaMemcpyHostToDevice);
vertex_disjoint_bfs_util<<<10, 1024>>>();
update_matchings<<<10, 1024>>>();
cudaDeviceSynchronize();
cudaMemcpyFromSymbol(&h_num_aug_paths, num_aug_paths, sizeof(num_aug_paths),0,cudaMemcpyDeviceToHost);
break;
}
clock_gettime( CLOCK_REALTIME,&end);
cudaMemcpyFromSymbol(h_matched_edge, d_matched_edge, sizeof(d_matched_edge),0,cudaMemcpyDeviceToHost);
cudaMemcpyFromSymbol(h_partner_vertex, d_partner_vertex, sizeof(d_partner_vertex),0,cudaMemcpyDeviceToHost);
printf("Number of augmenting paths(actual number may be higher): %d \n", h_num_aug_paths);
int num_matches = check_matching();
printf("Number of matchings: %d \n", num_matches);
double elapsed = (end.tv_sec-start.tv_sec)*1000000000 + end.tv_nsec-start.tv_nsec;
printf("Time elapsed %lf\n", elapsed/1e6);
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<fstream>
#include<time.h>
#include<sys/time.h>
#include<string>
using namespace std;
// #define num_threads 1000
#define lli long long int
int size[5] = {100, 500, 1000, 5000, 10000};
// int edges_2[5] = {200, 447, 1969, 4991, 200001};
int edges_8[5] = {801, 20000, 79580, 1999218, 8000000};
const lli num_edges = 8000000;
const lli num_vertices1 = 10000;
const lli num_vertices2 = 10000;
__device__ int d_flat_adj_list[2*num_edges];
__device__ int d_degree[num_vertices1+num_vertices2+1]={0}; //store degree of each vertex
__device__ int d_list_ptr[num_vertices1+num_vertices2+2]; //1-indexed and extra element at the end for easy size access // Pointer to the start of adjacency list
__device__ int d_list_ptr_copy[num_vertices1+num_vertices2+2]; //
__device__ bool d_matched_edge[2*num_edges]; // Tells for every edge in the list if the edge is matched or not
__device__ bool d_is_matched_vertex[num_vertices1 + num_vertices2 + 1] = {0}; //is the vertex matched
__device__ int d_partner_vertex[num_vertices1 + num_vertices2 + 1];
__device__ int d_visited[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_bfs_parent[num_vertices1 + num_vertices2 + 1];
__device__ bool d_is_parent_change[num_vertices1 + num_vertices2 + 1] = {0};
__device__ int d_frontier[num_vertices1 + num_vertices2+1] = {0};
__device__ int d_next_frontier[num_vertices1+num_vertices2+1] = {0};
__device__ int num_aug_paths = 10000000; //Any number not equal to 0 works
int *h_flat_adj_list;
int *h_degree;
int * h_list_ptr;
int *h_list_ptr_copy;
bool *h_matched_edge;
bool *h_is_matched_vertex;
int *h_partner_vertex;
int *h_visited;
int *h_bfs_parent;
bool *h_is_parent_change;
int fc = num_vertices1;
// int num_aug_paths = 0;
int *h_frontier;
int *h_next_frontier;
__device__
bool get_matched_edge(int x, int y){
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i]==y){
return d_matched_edge[i];
}
}
printf("Error! Querying for an edge which is not present \n");
return -1;
}
__device__
void set_matched_edge(int x, int y, int value){
bool edge_present = false;
int vertex = x;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == y){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
vertex = y;
start_edge = d_list_ptr[vertex];
end_edge = d_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(d_flat_adj_list[i] == x){
d_matched_edge[i] = value;
edge_present = true;
break;
}
}
if(!edge_present){
printf("Error! Querying for an edge which is not present \n");
}
}
void print_matchings(){
cout << "Matchings: " << endl;
for(int i=1;i<=num_vertices1+num_vertices2; i++){
cout<< i << " " << h_partner_vertex[i] << endl;
}
}
int get_matched_edge_h(int x, int y){
int vertex = x;
int start_edge = h_list_ptr[vertex];
int end_edge = h_list_ptr[vertex + 1];
for(int i = start_edge; i<end_edge;i++){
if(h_flat_adj_list[i] == y){
return h_matched_edge[i];
}
}
cout << "Error! Querying for an edge which is not present";
exit(0);
}
__device__
void match_edges(int u, int v){
set_matched_edge(u,v,1);
set_matched_edge(v,u,1);
d_is_matched_vertex[u] = 1;
d_is_matched_vertex[v] = 1;
d_partner_vertex[u] = v;
d_partner_vertex[v] = u;
}
// Unmatching edges also unmatches the vertices since the graph is a matching
__device__
void unmatch_edges(int u, int v){
set_matched_edge(u,v,0);
set_matched_edge(v,u,0);
if(d_partner_vertex[u]==v){
d_is_matched_vertex[u] = 0;
d_partner_vertex[u] = -1;
}
if(d_partner_vertex[v]==u){
d_is_matched_vertex[v] = 0;
d_partner_vertex[v] = -1;
}
}
// Make this parallel
__global__
void update_matchings(){
int tid = blockIdx.x*1024 + threadIdx.x;
for(int i=tid; i<=num_vertices1+num_vertices2; i+=num_vertices1){
int vertex = i;
if(d_is_parent_change[vertex] == true){
// cout << "Found aug. path till " << vertex << endl;
// There should always be odd number of vertices in aug. path
int path_length = 1;
int parent = d_bfs_parent[vertex];
while(parent!=vertex){
// cout << vertex << " " <<parent << endl;
if(path_length%2==1){
match_edges(vertex, parent);
// printf("Matching %d and %d \n", vertex, parent);
}
else{
unmatch_edges(vertex, parent);
// printf("Unmatching %d and %d \n", vertex, parent);
}
vertex = d_bfs_parent[vertex];
parent = d_bfs_parent[vertex];
path_length++;
}
}
}
}
__device__
void clear_visited(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_visited[vertex1] = 0;
}
}
__device__
void clear_bfs_parent(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_bfs_parent[vertex1] = vertex1;
}
}
__device__
void initialise_partner_vertex(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_partner_vertex[vertex1] = -1;
}
}
__device__
void clear_is_parent_change(){
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex1 = tid + 1;
if(vertex1<=num_vertices1 + num_vertices2){
d_is_parent_change[vertex1] = -1;
}
}
__device__
void copy_frontier(int *my_frontier, int *my_next_frontier){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = my_next_frontier[i];
}
}
__device__
void clear_frontier(int *my_frontier, int *my_next_frontier ){
for (int i=1;i<=num_vertices1+num_vertices2;i++){
my_frontier[i] = 0;
my_next_frontier[i] = 0;
}
}
__device__
void vertex_disjoint_bfs(int binary_level, int vertex, int tid){
int visited_self = atomicExch(&d_visited[vertex], 1);
if(visited_self && binary_level==0){
return;
}
d_visited[vertex] = true;
bool found_path = false;
int start_edge = d_list_ptr[vertex];
int end_edge = d_list_ptr[vertex + 1];
for(int j=start_edge;j<end_edge;j++){
if(found_path)
break;
int neighbor = d_flat_adj_list[j];
if(neighbor > num_vertices1 + num_vertices2){
printf("[%d]Error(neighbor out of range: vertex, neighbor : %d, %d \n", tid, vertex, neighbor);
}
int visited = atomicExch(&d_visited[neighbor], 1);
if(!visited){
// We want to alternate between unmatched and matched edges, otherwise we ignore
d_visited[neighbor] = true;
d_bfs_parent[neighbor] = vertex;
if( binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==1 ){
d_next_frontier[neighbor] = 1;
if(binary_level==1)
printf("Going odd %d \n", vertex);
vertex_disjoint_bfs(!binary_level, neighbor, tid);
}
// In level 1, we are only interested in matched edges
else if( binary_level==1 && get_matched_edge(vertex, neighbor)==1 ){
d_next_frontier[neighbor] = 1;
vertex_disjoint_bfs(!binary_level, neighbor, tid);
return;
}
// Changing parent change only for this node
else if(binary_level==0 && get_matched_edge(vertex, neighbor)==0 && d_is_matched_vertex[neighbor]==0){
d_is_parent_change[neighbor] = 1;
// atomicAdd(&num_aug_paths, 1);
num_aug_paths++;
return;
}
}
}
}
__global__
void vertex_disjoint_bfs_util(){
// parallelise these functions
clear_visited();
clear_bfs_parent();
clear_is_parent_change();
// clear_frontier(my_frontier, my_next_frontier );
initialise_partner_vertex();
int tid = blockIdx.x*1024 + threadIdx.x;
int vertex = tid+1;
if(vertex > num_vertices1)
return;
if(vertex >= num_vertices1+num_vertices2+1)
printf("[%d] Error \n");
if(!d_visited[vertex] && !d_is_matched_vertex[vertex]){
d_frontier[vertex] = 1;
vertex_disjoint_bfs(0, vertex, tid);
}
}
int check_matching(){
int total_matched = 0;
for(int i=1;i<=num_vertices1+num_vertices2;i++){
int vertex = i;
int num_matched = 0;
for(int j=h_list_ptr[i];j<h_list_ptr[i+1];j++){
int neighbor = h_flat_adj_list[j];
// cout << vertex << " " << neighbor << endl;
if(get_matched_edge_h(vertex, neighbor)){
num_matched++;
}
}
if(num_matched==1){
// cout << "Hi" << endl;
total_matched++;
}
if(num_matched>1){
cout << vertex << endl;
cout << "Error! Not a matching!";
exit(0);
}
}
return total_matched/2;
}
int main(){
struct timespec start, end;
// h_is_matched_edge = (bool *)calloc( (num_vertices1+ num_vertices2 + 1)*(num_vertices1 + num_vertices2+1), sizeof(bool));
h_matched_edge = (bool *)calloc(2*num_edges, sizeof(bool));
h_flat_adj_list = (int *)malloc(2*num_edges*sizeof(int));
h_degree = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_list_ptr = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_list_ptr_copy = (int *)malloc((num_vertices1+num_vertices2+2)*sizeof(int));
h_is_matched_vertex = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_partner_vertex = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_visited = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_bfs_parent = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_is_parent_change = (bool *)malloc((num_vertices1+num_vertices2+1)*sizeof(bool));
h_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
h_next_frontier = (int *)malloc((num_vertices1+num_vertices2+1)*sizeof(int));
// Add a check for null memory
memset(h_degree, 0, num_vertices1 + num_vertices2 +1);
// memset(h_is_matched_edge, 0, (num_vertices1 + num_vertices2 +1)*(num_vertices1+num_vertices2+1));
memset(h_is_matched_vertex, 0, num_vertices1 + num_vertices2 +1);
memset(h_visited, 0, num_vertices1 + num_vertices2 +1);
memset(h_is_parent_change, 0, num_vertices1 + num_vertices2 +1);
memset(h_frontier, 0, num_vertices1 + num_vertices2 +1);
memset(h_next_frontier, 0, num_vertices1 + num_vertices2 +1);
// to and from of edges
// int h_edges_u[num_edges], h_edges_v[num_edges]; // Make this dynamic memory and free it once we have our 2 pass initialisation phase
int *h_edges_u, *h_edges_v;
h_edges_u = (int *)malloc((num_edges)*sizeof(int));
h_edges_v = (int *)malloc((num_edges)*sizeof(int));
ifstream fin;
fin.open("random_10000_10000_high.txt", ios::in);
int u, v;
// Vertices with 0 edges are implicitly ignored while reading the file itself
for(int i=0;i<num_edges;i++){
// cout << i << endl;
fin >> u >> v;
h_edges_u[i] = u;
h_edges_v[i] = v;
h_degree[u]++;
h_degree[v]++;
}
cout << "Done reading edges" << endl;
// Get pointer to adjacency list using prefix sum (no opti here since other parts are more complex anyway)
// Index 0 will never be used.... the last elem
h_list_ptr[1] = 0;
h_list_ptr_copy[1] = h_list_ptr[1];
for(int i=2;i<=num_vertices1+num_vertices2;i++){
h_list_ptr[i] = h_list_ptr[i-1] + h_degree[i-1];
h_list_ptr_copy[i] = h_list_ptr[i];
}
h_list_ptr[num_vertices1+num_vertices2+1] = 2*num_edges; //For easy coding
h_list_ptr_copy[num_vertices1+num_vertices2+1] = 2*num_edges; // list_ptr has the start of the adj list ; list_ptr_copy has the current position
for(int i=0;i<num_edges;i++){
h_flat_adj_list[h_list_ptr_copy[h_edges_u[i]]] = h_edges_v[i];
h_flat_adj_list[h_list_ptr_copy[h_edges_v[i]]] = h_edges_u[i];
h_list_ptr_copy[h_edges_u[i]]++;
h_list_ptr_copy[h_edges_v[i]]++;
}
clock_gettime( CLOCK_REALTIME,&start);
hipMemcpyToSymbol(HIP_SYMBOL(d_matched_edge), h_matched_edge, (2*num_edges)*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_flat_adj_list), h_flat_adj_list, 2*num_edges*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_degree), h_degree, (num_vertices1+num_vertices2+1)*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_list_ptr), h_list_ptr, (num_vertices1+num_vertices2+2)*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_is_matched_vertex), h_is_matched_vertex, (num_vertices1+num_vertices2+1)*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_visited), h_visited, (num_vertices1+num_vertices2+1)*sizeof(int),0,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(d_frontier), h_frontier, (num_vertices1+num_vertices2+2)*sizeof(int),0,hipMemcpyHostToDevice);
int h_num_aug_paths = 1000;
hipDeviceSynchronize();
while(h_num_aug_paths>0){
h_num_aug_paths = 0;
hipMemcpyToSymbol(HIP_SYMBOL(num_aug_paths), &h_num_aug_paths, (1)*sizeof(int),0,hipMemcpyHostToDevice);
vertex_disjoint_bfs_util<<<10, 1024>>>();
update_matchings<<<10, 1024>>>();
hipDeviceSynchronize();
hipMemcpyFromSymbol(&h_num_aug_paths, HIP_SYMBOL(num_aug_paths), sizeof(num_aug_paths),0,hipMemcpyDeviceToHost);
break;
}
clock_gettime( CLOCK_REALTIME,&end);
hipMemcpyFromSymbol(h_matched_edge, HIP_SYMBOL(d_matched_edge), sizeof(d_matched_edge),0,hipMemcpyDeviceToHost);
hipMemcpyFromSymbol(h_partner_vertex, HIP_SYMBOL(d_partner_vertex), sizeof(d_partner_vertex),0,hipMemcpyDeviceToHost);
printf("Number of augmenting paths(actual number may be higher): %d \n", h_num_aug_paths);
int num_matches = check_matching();
printf("Number of matchings: %d \n", num_matches);
double elapsed = (end.tv_sec-start.tv_sec)*1000000000 + end.tv_nsec-start.tv_nsec;
printf("Time elapsed %lf\n", elapsed/1e6);
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
cudaError_t errors;
errors = cudaSetDevice(0);
cudaDeviceProp props;
errors = cudaGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != cudaSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = cudaMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = cudaMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = cudaGetLastError();
if (errors != cudaSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", cudaGetErrorString(errors));
exit(0);
}
errors = cudaDeviceSynchronize();
if (errors != cudaSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
cudaMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToDevice);
}
cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = cudaDeviceReset();
if (errors != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | code for sm_80
Function : _Z12conwayThreadPcS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x174] ; /* 0x00005d0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe40000000000 */
/*00b0*/ I2F.RP R8, R2 ; /* 0x0000000200087306 */
/* 0x000e220000209400 */
/*00c0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*00d0*/ I2F.RP R3, R10 ; /* 0x0000000a00037306 */
/* 0x000e700000209400 */
/*00e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e300000001000 */
/*00f0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x002e620000001000 */
/*0100*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fc40007ffe0ff */
/*0110*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fca0000000000 */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000a2000021f000 */
/*0130*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x002fce0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002e2000021f000 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x004fe400078e0a07 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fe400078e00ff */
/*0180*/ IMAD R9, R9, R2, RZ ; /* 0x0000000209097224 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x008fe400078e0a05 */
/*01a0*/ IMAD.HI.U32 R6, R7, R9, R6 ; /* 0x0000000907067227 */
/* 0x000fc800078e0006 */
/*01b0*/ IMAD R3, R11, R10, RZ ; /* 0x0000000a0b037224 */
/* 0x000fe400078e02ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*01e0*/ IMAD.HI.U32 R6, R6, R7, RZ ; /* 0x0000000706067227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a06 */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a04 */
/*0220*/ IMAD R5, R2, R6, R7.reuse ; /* 0x0000000602057224 */
/* 0x100fe400078e0207 */
/*0230*/ IMAD R3, R10, R3, R7 ; /* 0x000000030a037224 */
/* 0x000fc600078e0207 */
/*0240*/ ISETP.GT.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f04070 */
/*0250*/ ISETP.GT.U32.AND P3, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fd60003f64070 */
/*0260*/ @!P0 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x0000000105058824 */
/* 0x000fe400078e0a02 */
/*0270*/ @!P3 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x000000010303b824 */
/* 0x000fe200078e0a0a */
/*0280*/ @!P3 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404b810 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.GT.U32.AND P4, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f84070 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe40003f06070 */
/*02b0*/ LOP3.LUT R3, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000037a12 */
/* 0x000fe400078e3cff */
/*02c0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc40003f65270 */
/*02d0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f26270 */
/*02e0*/ @!P4 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x000000010505c824 */
/* 0x000fe200078e0a02 */
/*02f0*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f85270 */
/*0300*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0005 */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0004 */
/*0330*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe400078e0a02 */
/*0340*/ @!P1 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff109224 */
/* 0x000fe200078e0a10 */
/*0350*/ @!P3 LOP3.LUT R16, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff10ba12 */
/* 0x000fe400078e33ff */
/*0360*/ @!P4 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff02ca12 */
/* 0x000fe400078e33ff */
/*0370*/ ISETP.GE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f26270 */
/*0380*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc40003f06270 */
/*0390*/ SEL R3, R16, c[0x0][0x170], P1 ; /* 0x00005c0010037a07 */
/* 0x000fe40000800000 */
/*03a0*/ SEL R5, R2.reuse, c[0x0][0x174], P0 ; /* 0x00005d0002057a07 */
/* 0x040fe40000000000 */
/*03b0*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD R13, R4.reuse, c[0x0][0x174], R2 ; /* 0x00005d00040d7a24 */
/* 0x040fe400078e0202 */
/*03f0*/ IMAD R9, R4, c[0x0][0x174], R5.reuse ; /* 0x00005d0004097a24 */
/* 0x100fe200078e0205 */
/*0400*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0410*/ IMAD R7, R16, c[0x0][0x174], R5 ; /* 0x00005d0010077a24 */
/* 0x000fc600078e0205 */
/*0420*/ IADD3 R8, P2, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe40007f5e0ff */
/*0430*/ SEL R15, R3, RZ, !P0 ; /* 0x000000ff030f7207 */
/* 0x000fe40004000000 */
/*0440*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P2 ; /* 0x0000590009097a11 */
/* 0x000fe400010f0eff */
/*0450*/ IADD3 R6, P1, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x040fe20007f3e0ff */
/*0460*/ IMAD R11, R4, c[0x0][0x174], R15 ; /* 0x00005d00040b7a24 */
/* 0x000fe200078e020f */
/*0470*/ IADD3 R14, R16, 0x1, RZ ; /* 0x00000001100e7810 */
/* 0x000fe20007ffe0ff */
/*0480*/ LDG.E.U8 R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000a2000c1e1100 */
/*0490*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P1 ; /* 0x0000590007077a11 */
/* 0x000fc400008f0eff */
/*04a0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fe20007f3e0ff */
/*04b0*/ IMAD R16, R16, c[0x0][0x174], R15 ; /* 0x00005d0010107a24 */
/* 0x000fe200078e020f */
/*04c0*/ ISETP.GE.AND P0, PT, R14.reuse, c[0x0][0x170], PT ; /* 0x00005c000e007a0c */
/* 0x040fe20003f06270 */
/*04d0*/ LDG.E.U8 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002e2000c1e1100 */
/*04e0*/ IADD3 R10, P2, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fe40007f5e0ff */
/*04f0*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x164], 0x1, P1 ; /* 0x000059000d0d7a11 */
/* 0x000fe400008f0eff */
/*0500*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P2 ; /* 0x000059000b0b7a11 */
/* 0x000fe400010f0eff */
/*0510*/ SEL R18, R14, RZ, !P0 ; /* 0x000000ff0e127207 */
/* 0x000fe20004000000 */
/*0520*/ LDG.E.U8 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001122000c1e1100 */
/*0530*/ IADD3 R14, P0, R16, c[0x0][0x160], RZ ; /* 0x00005800100e7a10 */
/* 0x000fc60007f1e0ff */
/*0540*/ LDG.E.U8 R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000b22000c1e1100 */
/*0550*/ IMAD R17, R18, c[0x0][0x174], R15 ; /* 0x00005d0012117a24 */
/* 0x000fe200078e020f */
/*0560*/ LEA.HI.X.SX32 R15, R16, c[0x0][0x164], 0x1, P0 ; /* 0x00005900100f7a11 */
/* 0x000fe200000f0eff */
/*0570*/ IMAD R2, R18, c[0x0][0x174], R2 ; /* 0x00005d0012027a24 */
/* 0x000fc600078e0202 */
/*0580*/ IADD3 R6, P0, R17.reuse, c[0x0][0x160], RZ ; /* 0x0000580011067a10 */
/* 0x042fe20007f1e0ff */
/*0590*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f26000c1e1100 */
/*05a0*/ LEA.HI.X.SX32 R7, R17, c[0x0][0x164], 0x1, P0 ; /* 0x0000590011077a11 */
/* 0x000fe400000f0eff */
/*05b0*/ IADD3 R16, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002107a10 */
/* 0x000fe20007f1e0ff */
/*05c0*/ IMAD R5, R18, c[0x0][0x174], R5 ; /* 0x00005d0012057a24 */
/* 0x000fe400078e0205 */
/*05d0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*05e0*/ LEA.HI.X.SX32 R17, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002117a11 */
/* 0x000fc400000f0eff */
/*05f0*/ IADD3 R10, P0, R5, c[0x0][0x160], RZ ; /* 0x00005800050a7a10 */
/* 0x020fc60007f1e0ff */
/*0600*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1100 */
/*0610*/ LEA.HI.X.SX32 R11, R5, c[0x0][0x164], 0x1, P0 ; /* 0x00005900050b7a11 */
/* 0x000fe400000f0eff */
/*0620*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0630*/ IADD3 R12, P0, R0, c[0x0][0x160], RZ ; /* 0x00005800000c7a10 */
/* 0x001fe20007f1e0ff */
/*0640*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f66000c1e1100 */
/*0650*/ IADD3.X R13, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900050d7a10 */
/* 0x000fca00007fe4ff */
/*0660*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1100 */
/*0670*/ ISETP.NE.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x004fe20003f25270 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, 0x2 ; /* 0x00000002ff037424 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x008fc80003f05270 */
/*06a0*/ SEL R2, RZ, 0x1, P0 ; /* 0x00000001ff027807 */
/* 0x000fce0000000000 */
/*06b0*/ @!P1 SEL R2, R3, 0x1, !P0 ; /* 0x0000000103029807 */
/* 0x000fe40004000000 */
/*06c0*/ ISETP.NE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x010fe40003f45270 */
/*06d0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f05270 */
/*06e0*/ SEL R3, RZ, 0x1, P2 ; /* 0x00000001ff037807 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc60003f25270 */
/*0700*/ IMAD.IADD R2, R2, 0x1, R3 ; /* 0x0000000102027824 */
/* 0x000fca00078e0203 */
/*0710*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0720*/ @P0 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0202 */
/*0730*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc80003f05270 */
/*0740*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @P1 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0203 */
/*0760*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fc80003f25270 */
/*0770*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc60007ffe0ff */
/*0780*/ @P0 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0202 */
/*0790*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*07a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ @P1 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0203 */
/*07c0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f25270 */
/*07d0*/ IADD3 R2, P2, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fe40007f5e0ff */
/*07e0*/ IADD3 R0, R4, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3.X R3, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005037a10 */
/* 0x000fe200017fe4ff */
/*0800*/ @P0 IMAD.MOV R0, RZ, RZ, R4 ; /* 0x000000ffff000224 */
/* 0x000fcc00078e0204 */
/*0810*/ @!P1 BRA 0x880 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f05270 */
/*0830*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*0840*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fca00078e00ff */
/*0860*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R0, R0, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe00007812 */
/* 0x000fc800078ec0ff */
/*0890*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f05270 */
/*08a0*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*08b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fca00078e00ff */
/*08d0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
cudaError_t errors;
errors = cudaSetDevice(0);
cudaDeviceProp props;
errors = cudaGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != cudaSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = cudaMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = cudaMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = cudaGetLastError();
if (errors != cudaSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", cudaGetErrorString(errors));
exit(0);
}
errors = cudaDeviceSynchronize();
if (errors != cudaSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
cudaMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToDevice);
}
cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = cudaDeviceReset();
if (errors != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | .file "tmpxft_000a90e4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11idxToCoordsiPiS_ii
.type _Z11idxToCoordsiPiS_ii, @function
_Z11idxToCoordsiPiS_ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11idxToCoordsiPiS_ii, .-_Z11idxToCoordsiPiS_ii
.globl _Z11coordsToIdxiiPiii
.type _Z11coordsToIdxiiPiii, @function
_Z11coordsToIdxiiPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11coordsToIdxiiPiii, .-_Z11coordsToIdxiiPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-"
.LC1:
.string "0"
.LC2:
.string "\n"
.text
.globl _Z10printBoardPcii
.type _Z10printBoardPcii, @function
_Z10printBoardPcii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, %r15d
movl $0, %r14d
movl $0, (%rsp)
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %r12
testl %esi, %esi
jg .L8
.L7:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $1, %rbx
cmpq %rbp, %rbx
je .L19
.L12:
cmpb $0, (%rbx)
jne .L10
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L19:
addl %r15d, (%rsp)
.L14:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl %r14d, 4(%rsp)
je .L7
.L8:
testl %r15d, %r15d
jle .L14
movslq (%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax), %rbx
movslq %r15d, %rbp
addq %rcx, %rbp
addq %rax, %rbp
jmp .L12
.cfi_endproc
.LFE2059:
.size _Z10printBoardPcii, .-_Z10printBoardPcii
.globl _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
.type _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii, @function
_Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12conwayThreadPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii, .-_Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
.globl _Z12conwayThreadPcS_ii
.type _Z12conwayThreadPcS_ii, @function
_Z12conwayThreadPcS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12conwayThreadPcS_ii, .-_Z12conwayThreadPcS_ii
.section .rodata.str1.1
.LC3:
.string "Beginning state:\n"
.LC4:
.string "Error setting device\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Error allocating previous state\n"
.section .rodata.str1.1
.LC6:
.string "Error allocating next state\n"
.LC7:
.string "Error copying previous state\n"
.LC8:
.string "Error copying next state\n"
.LC9:
.string "Error launching kernel\n"
.LC10:
.string "%s\n"
.LC11:
.string "Error synchronizing device\n"
.LC12:
.string "Final state\n"
.LC13:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -131072(%rsp), %r11
.cfi_def_cfa 11, 131112
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1112, %rsp
.cfi_def_cfa_offset 132224
movq %fs:40, %rax
movq %rax, 132168(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $0, %edi
call srand@PLT
leaq 1088(%rsp), %rbx
leaq 66624(%rsp), %rbp
.L29:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1088(%rsp), %rdi
movl $256, %edx
movl $256, %esi
call _Z10printBoardPcii
movl $0, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %esi
movl 368(%rsp), %ecx
movl $65536, %eax
movl $0, %edx
idivl %ecx
testl %edx, %edx
je .L30
movl %ecx, %eax
subl %edx, %eax
addl $65536, %eax
cltd
idivl %ecx
movl %eax, %ebx
.L31:
testl %esi, %esi
je .L32
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movl $65536, %eax
movl $0, %edx
idivl %ecx
movl %eax, %ebx
jmp .L31
.L32:
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L33
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L34
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
leaq 1088(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L35
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
leaq 66624(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
sall $2, %ebx
movl $100, %r12d
movl $4, %r13d
jmp .L40
.L47:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L37:
call cudaGetLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L48
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L49
movl $3, %ecx
movl $65536, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %r12d
je .L50
.L40:
movl 368(%rsp), %eax
cltd
idivl %r13d
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ebx, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movl $256, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
jmp .L37
.L48:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L49:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
leaq 66624(%rsp), %rbx
movl $2, %ecx
movl $65536, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %edx
movl $256, %esi
movq %rbx, %rdi
call _Z10printBoardPcii
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L51
.L28:
movq 132168(%rsp), %rdx
subq %fs:40, %rdx
jne .L52
addq $132184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12conwayThreadPcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12conwayThreadPcS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
cudaError_t errors;
errors = cudaSetDevice(0);
cudaDeviceProp props;
errors = cudaGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != cudaSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = cudaMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != cudaSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = cudaMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = cudaMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
if (errors != cudaSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = cudaGetLastError();
if (errors != cudaSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", cudaGetErrorString(errors));
exit(0);
}
errors = cudaDeviceSynchronize();
if (errors != cudaSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
cudaMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToDevice);
}
cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = cudaDeviceReset();
if (errors != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
hipError_t errors;
errors = hipSetDevice(0);
hipDeviceProp_t props;
errors = hipGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != hipSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = hipMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = hipMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = hipGetLastError();
if (errors != hipSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", hipGetErrorString(errors));
exit(0);
}
errors = hipDeviceSynchronize();
if (errors != hipSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
hipMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToDevice);
}
hipMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = hipDeviceReset();
if (errors != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
hipError_t errors;
errors = hipSetDevice(0);
hipDeviceProp_t props;
errors = hipGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != hipSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = hipMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = hipMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = hipGetLastError();
if (errors != hipSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", hipGetErrorString(errors));
exit(0);
}
errors = hipDeviceSynchronize();
if (errors != hipSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
hipMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToDevice);
}
hipMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = hipDeviceReset();
if (errors != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12conwayThreadPcS_ii
.globl _Z12conwayThreadPcS_ii
.p2align 8
.type _Z12conwayThreadPcS_ii,@function
_Z12conwayThreadPcS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
s_ashr_i32 s3, s4, 31
s_ashr_i32 s2, s5, 31
s_add_i32 s6, s4, s3
s_add_i32 s7, s5, s2
s_xor_b32 s6, s6, s3
s_xor_b32 s7, s7, s2
v_cvt_f32_u32_e32 v0, s6
v_cvt_f32_u32_e32 v2, s7
s_sub_i32 s2, 0, s6
s_sub_i32 s8, 0, s7
v_ashrrev_i32_e32 v5, 31, v1
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v5
v_xor_b32_e32 v6, v6, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s2, v0
v_mul_lo_u32 v4, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v6, v0
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s6
v_mul_lo_u32 v2, v2, s7
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v6, v3
v_sub_nc_u32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_subrev_nc_u32_e32 v7, s7, v2
v_cmp_le_u32_e64 s2, s7, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v3, v3, v6
v_cndmask_b32_e64 v2, v2, v7, s2
v_xor_b32_e32 v6, s3, v5
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_subrev_nc_u32_e32 v7, s7, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v0, v0, v6
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v6
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_sub_nc_u32_e32 v3, v2, v5
v_mul_lo_u32 v4, v0, s5
v_cndmask_b32_e64 v2, v0, s4, vcc_lo
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, 1, v3
v_add_nc_u32_e32 v6, 1, v3
v_add_nc_u32_e32 v2, -1, v2
v_cndmask_b32_e64 v5, v3, s5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v7, v2, s5
v_ashrrev_i32_e32 v2, 31, v1
v_dual_cndmask_b32 v0, 0, v0 :: v_dual_add_nc_u32 v5, -1, v5
v_cmp_gt_i32_e32 vcc_lo, s5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v5, v4
v_mul_lo_u32 v0, v0, s5
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_add_nc_u32_e32 v10, v7, v5
v_add_nc_u32_e32 v11, v7, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v9, v6, v4
v_ashrrev_i32_e32 v4, 31, v8
v_add_nc_u32_e32 v12, v7, v6
v_add_nc_u32_e32 v13, v0, v6
v_add_nc_u32_e32 v14, v0, v3
v_ashrrev_i32_e32 v6, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_nc_u32_e32 v0, v0, v5
v_ashrrev_i32_e32 v15, 31, v10
v_add_co_u32 v5, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_ashrrev_i32_e32 v16, 31, v11
v_add_co_u32 v7, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v15, vcc_lo
v_ashrrev_i32_e32 v17, 31, v12
v_add_co_u32 v9, vcc_lo, s0, v11
global_load_u8 v15, v[3:4], off
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v17, vcc_lo
v_ashrrev_i32_e32 v18, 31, v13
v_add_co_u32 v3, vcc_lo, s0, v13
s_clause 0x1
global_load_u8 v13, v[7:8], off
global_load_u8 v9, v[9:10], off
v_ashrrev_i32_e32 v19, 31, v14
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v18, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v14
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v19, vcc_lo
s_clause 0x3
global_load_u8 v11, v[11:12], off
global_load_u8 v12, v[5:6], off
global_load_u8 v14, v[3:4], off
global_load_u8 v7, v[7:8], off
v_ashrrev_i32_e32 v10, 31, v0
v_add_co_u32 v3, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_u8 v0, v[3:4], off
global_load_u8 v3, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(8)
v_cmp_eq_u16_e32 vcc_lo, 1, v15
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v5, 1, 2, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_eq_u16_e32 vcc_lo, 1, v9
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v13
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_eq_u16_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v11
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(2)
v_cmp_eq_u16_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v14
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v0, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 1, v3
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_7
v_cmp_ne_u32_e32 vcc_lo, 3, v0
v_add_co_u32 v0, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, s3, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_7:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v0, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, -3, v0
v_add_co_u32 v0, s0, s2, v1
v_add_co_ci_u32_e64 v1, s0, s3, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_10:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12conwayThreadPcS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12conwayThreadPcS_ii, .Lfunc_end0-_Z12conwayThreadPcS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12conwayThreadPcS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12conwayThreadPcS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
__device__ void idxToCoords(const int idx, int *row, int *col, int rows, int cols)
{
*row = idx / rows;
*col = idx % cols;
return;
}
__device__ void coordsToIdx(const int row, const int col, int *idx, int rows, int cols)
{
*idx = row * cols + col;
}
__global__ void conwayThread(char *oldState, char *newState, int rows, int cols)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("This is thread %d\n", idx);
if (idx >= rows * cols)
return;
int colIdx;
int rowIdx;
int newIdx;
idxToCoords(idx, &rowIdx, &colIdx, rows, cols);
coordsToIdx(rowIdx, colIdx, &newIdx, rows, cols);
//printf("Block: %d, Blockdim: %d, Thread: %d, Overall %d: row %d, col %d, newIdx %d\n", blockIdx.x, blockDim.x, threadIdx.x, idx, rowIdx, colIdx, newIdx);
int numLiveNeighbors = 0;
int tempRow;
int tempCol;
int tempIdx;
//__syncthreads();
//printf("Thread: %d continuing\n", idx);
// check left neighbor
tempRow = rowIdx;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx - 1;
if (tempRow < 0)
tempRow = rows - 1;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx + 1;
if (tempCol >= cols)
tempCol = 0;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
tempRow = rowIdx + 1;
if (tempRow >= rows)
tempRow = 0;
tempCol = colIdx - 1;
if (tempCol < 0)
tempCol = cols - 1;
coordsToIdx(tempRow, tempCol, &tempIdx, rows, cols);
//if(idx == 0)
//printf("Checking %d - %d, %d\n", tempIdx, tempRow, tempCol);
if (oldState[tempIdx] == 1)
numLiveNeighbors++;
if (oldState[idx] == 1)
{
if (numLiveNeighbors < 2 || numLiveNeighbors > 3)
{
newState[idx] = 0;
}
else
{
newState[idx] = 1;
}
}
else
{
if (numLiveNeighbors == 3)
{
newState[idx] = 1;
}
else
{
newState[idx] = 0;
}
}
//printf("Cell %d has %d live neighbors\n", idx, numLiveNeighbors);
}
void printBoard(char *board, int rows, int cols)
{
int counter = 0;
for (int i = 0; i < rows; i++)
{
for (int j = 0; j < cols; j++)
{
if (board[counter] == 0)
printf("-");
else
printf("0");
counter++;
}
printf("\n");
}
return;
}
int main()
{
//const int arraySize = 5;
//const int a[arraySize] = { 1, 2, 3, 4, 5 };
//const int b[arraySize] = { 10, 20, 30, 40, 50 };
//int c[arraySize] = { 0 };
const int iterations = 100;
const int rows = 256;
const int cols = 256;
const int boardSize = rows * cols;
char prevState[boardSize];
char nextState[boardSize];
char *gpu_prevState = 0;
char *gpu_nextState = 0;
srand(0);
for (int i = 0; i < boardSize; i++)
prevState[i] = rand() % 2;
printf("Beginning state:\n");
printBoard(prevState, rows, cols);
hipError_t errors;
errors = hipSetDevice(0);
hipDeviceProp_t props;
errors = hipGetDeviceProperties(&props, 0);
int nBlocks;
//printf("Max threads: %d\n", props.maxThreadsPerBlock);
int temp = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock)));
//printf("Temp: %d\n", temp);
if ((boardSize % props.maxThreadsPerBlock) != 0)
nBlocks = (boardSize + (props.maxThreadsPerBlock - (boardSize % props.maxThreadsPerBlock))) / props.maxThreadsPerBlock;
else
nBlocks = boardSize / props.maxThreadsPerBlock;
//printf("Blocks: %d\n", nBlocks);
if (errors != hipSuccess)
{
printf("Error setting device\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_prevState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating previous state\n");
exit(0);
}
errors = hipMalloc((void **)&gpu_nextState, boardSize * sizeof(char));
if (errors != hipSuccess)
{
printf("Error allocating next state\n");
exit(0);
}
errors = hipMemcpy(gpu_prevState, prevState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying previous state\n");
exit(0);
}
errors = hipMemcpy(gpu_nextState, nextState, boardSize * sizeof(char), hipMemcpyHostToDevice);
if (errors != hipSuccess)
{
printf("Error copying next state\n");
exit(0);
}
for (int i = 0; i < iterations; i++)
{
//printf("On iteration %d\n", i);
conwayThread <<<nBlocks * 4, props.maxThreadsPerBlock / 4>>>(gpu_prevState, gpu_nextState, rows, cols);
errors = hipGetLastError();
if (errors != hipSuccess)
{
printf("Error launching kernel\n");
printf("%s\n", hipGetErrorString(errors));
exit(0);
}
errors = hipDeviceSynchronize();
if (errors != hipSuccess)
{
printf("Error synchronizing device\n");
exit(0);
}
// Copy through host
//cudaMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), cudaMemcpyDeviceToHost);
//cudaMemcpy(gpu_prevState, nextState, boardSize * sizeof(char), cudaMemcpyHostToDevice);
// Copy through device
hipMemcpy(gpu_prevState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToDevice);
}
hipMemcpy(nextState, gpu_nextState, boardSize * sizeof(char), hipMemcpyDeviceToHost);
printf("Final state\n");
printBoard(nextState, rows, cols);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
errors = hipDeviceReset();
if (errors != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
return 0;
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__conwayThreadPcS_ii # -- Begin function _Z27__device_stub__conwayThreadPcS_ii
.p2align 4, 0x90
.type _Z27__device_stub__conwayThreadPcS_ii,@function
_Z27__device_stub__conwayThreadPcS_ii: # @_Z27__device_stub__conwayThreadPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12conwayThreadPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__conwayThreadPcS_ii, .Lfunc_end0-_Z27__device_stub__conwayThreadPcS_ii
.cfi_endproc
# -- End function
.globl _Z10printBoardPcii # -- Begin function _Z10printBoardPcii
.p2align 4, 0x90
.type _Z10printBoardPcii,@function
_Z10printBoardPcii: # @_Z10printBoardPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 8(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
xorl %r15d, %r15d
movl 8(%rsp), %eax # 4-byte Reload
testl %eax, %eax
movl $0, %r12d
cmovgl %eax, %r12d
movl %eax, %r13d
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r14d
addl %r12d, %r15d
cmpl 12(%rsp), %r14d # 4-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movslq %r15d, %rbp
addq 16(%rsp), %rbp # 8-byte Folded Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%rbp,%rbx)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %rbx
cmpl %ebx, %r13d
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10printBoardPcii, .Lfunc_end1-_Z10printBoardPcii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $132680, %rsp # imm = 0x20648
.cfi_def_cfa_offset 132736
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $254, %ecx
subl %ecx, %eax
movb %al, 1600(%rsp,%rbx)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 1600(%rsp), %r14
.p2align 4, 0x90
.LBB2_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%r14,%r15)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %r15
cmpl $256, %r15d # imm = 0x100
jne .LBB2_4
# %bb.5: # %._crit_edge.loopexit.i
# in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
addq $256, %r14 # imm = 0x100
cmpl $256, %ebx # imm = 0x100
jne .LBB2_3
# %bb.6: # %_Z10printBoardPcii.exit
xorl %edi, %edi
callq hipSetDevice
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl %eax, %ecx
movl 448(%rsp), %esi
movl $65536, %edi # imm = 0x10000
movl $65536, %eax # imm = 0x10000
xorl %edx, %edx
idivl %esi
movl %esi, %eax
subl %edx, %eax
addl $65536, %eax # imm = 0x10000
testl %edx, %edx
cmovel %edi, %eax
cltd
idivl %esi
testl %ecx, %ecx
jne .LBB2_7
# %bb.9:
movl %eax, %r14d
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq 16(%rsp), %rdi
leaq 1600(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 8(%rsp), %rdi
leaq 67136(%rsp), %rbx
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_21
# %bb.16: # %.preheader
movabsq $4294967296, %r13 # imm = 0x100000000
shll $2, %r14d
orq %r13, %r14
movl $100, %ebp
leaq 96(%rsp), %r15
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movl 448(%rsp), %eax
leal 3(%rax), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $2, %edx
orq %r13, %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $256, 28(%rsp) # imm = 0x100
movl $256, 24(%rsp) # imm = 0x100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z12conwayThreadPcS_ii, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.30: # in Loop: Header=BB2_17 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_31
# %bb.22: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $3, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_17
# %bb.23:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_24: # %.preheader.i40
# =>This Loop Header: Depth=1
# Child Loop BB2_25 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_25: # %.lr.ph.i43
# Parent Loop BB2_24 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%rbx,%r15)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %r15
cmpl $256, %r15d # imm = 0x100
jne .LBB2_25
# %bb.26: # %._crit_edge.loopexit.i49
# in Loop: Header=BB2_24 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r14d
addq $256, %rbx # imm = 0x100
cmpl $256, %r14d # imm = 0x100
jne .LBB2_24
# %bb.27: # %_Z10printBoardPcii.exit53
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB2_28
.LBB2_29:
addq $132680, %rsp # imm = 0x20648
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_28:
.cfi_def_cfa_offset 132736
movq stderr(%rip), %rcx
movl $.L.str.13, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB2_29
.LBB2_31:
movl $.Lstr.2, %edi
jmp .LBB2_8
.LBB2_20:
movl %eax, %r12d
movl $.Lstr.3, %edi
callq puts@PLT
movl %r12d, %edi
callq hipGetErrorString
movq %rax, %rdi
.LBB2_8:
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_7:
movl $.Lstr.8, %edi
jmp .LBB2_8
.LBB2_10:
movl $.Lstr.7, %edi
jmp .LBB2_8
.LBB2_12:
movl $.Lstr.6, %edi
jmp .LBB2_8
.LBB2_14:
movl $.Lstr.5, %edi
jmp .LBB2_8
.LBB2_21:
movl $.Lstr.4, %edi
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12conwayThreadPcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12conwayThreadPcS_ii,@object # @_Z12conwayThreadPcS_ii
.section .rodata,"a",@progbits
.globl _Z12conwayThreadPcS_ii
.p2align 3, 0x0
_Z12conwayThreadPcS_ii:
.quad _Z27__device_stub__conwayThreadPcS_ii
.size _Z12conwayThreadPcS_ii, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "hipDeviceReset failed!"
.size .L.str.13, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12conwayThreadPcS_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Beginning state:"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Final state"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error synchronizing device"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error launching kernel"
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error copying next state"
.size .Lstr.4, 25
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error copying previous state"
.size .Lstr.5, 29
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Error allocating next state"
.size .Lstr.6, 28
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Error allocating previous state"
.size .Lstr.7, 32
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Error setting device"
.size .Lstr.8, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__conwayThreadPcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12conwayThreadPcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12conwayThreadPcS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x174] ; /* 0x00005d0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, c[0x0][0x170] ; /* 0x00005c00000a7a13 */
/* 0x000fe40000000000 */
/*00b0*/ I2F.RP R8, R2 ; /* 0x0000000200087306 */
/* 0x000e220000209400 */
/*00c0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*00d0*/ I2F.RP R3, R10 ; /* 0x0000000a00037306 */
/* 0x000e700000209400 */
/*00e0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e300000001000 */
/*00f0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x002e620000001000 */
/*0100*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fc40007ffe0ff */
/*0110*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fca0000000000 */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0000a2000021f000 */
/*0130*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x002fce0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002e2000021f000 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x004fe400078e0a07 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fe400078e00ff */
/*0180*/ IMAD R9, R9, R2, RZ ; /* 0x0000000209097224 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x008fe400078e0a05 */
/*01a0*/ IMAD.HI.U32 R6, R7, R9, R6 ; /* 0x0000000907067227 */
/* 0x000fc800078e0006 */
/*01b0*/ IMAD R3, R11, R10, RZ ; /* 0x0000000a0b037224 */
/* 0x000fe400078e02ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0008 */
/*01d0*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*01e0*/ IMAD.HI.U32 R6, R6, R7, RZ ; /* 0x0000000706067227 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a06 */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a04 */
/*0220*/ IMAD R5, R2, R6, R7.reuse ; /* 0x0000000602057224 */
/* 0x100fe400078e0207 */
/*0230*/ IMAD R3, R10, R3, R7 ; /* 0x000000030a037224 */
/* 0x000fc600078e0207 */
/*0240*/ ISETP.GT.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f04070 */
/*0250*/ ISETP.GT.U32.AND P3, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fd60003f64070 */
/*0260*/ @!P0 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x0000000105058824 */
/* 0x000fe400078e0a02 */
/*0270*/ @!P3 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x000000010303b824 */
/* 0x000fe200078e0a0a */
/*0280*/ @!P3 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404b810 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.GT.U32.AND P4, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f84070 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe40003f06070 */
/*02b0*/ LOP3.LUT R3, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000037a12 */
/* 0x000fe400078e3cff */
/*02c0*/ ISETP.NE.AND P3, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc40003f65270 */
/*02d0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f26270 */
/*02e0*/ @!P4 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x000000010505c824 */
/* 0x000fe200078e0a02 */
/*02f0*/ ISETP.NE.AND P4, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f85270 */
/*0300*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R2, RZ, RZ, R5 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0005 */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0004 */
/*0330*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe400078e0a02 */
/*0340*/ @!P1 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff109224 */
/* 0x000fe200078e0a10 */
/*0350*/ @!P3 LOP3.LUT R16, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff10ba12 */
/* 0x000fe400078e33ff */
/*0360*/ @!P4 LOP3.LUT R2, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff02ca12 */
/* 0x000fe400078e33ff */
/*0370*/ ISETP.GE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f26270 */
/*0380*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc40003f06270 */
/*0390*/ SEL R3, R16, c[0x0][0x170], P1 ; /* 0x00005c0010037a07 */
/* 0x000fe40000800000 */
/*03a0*/ SEL R5, R2.reuse, c[0x0][0x174], P0 ; /* 0x00005d0002057a07 */
/* 0x040fe40000000000 */
/*03b0*/ IADD3 R4, R3, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD R13, R4.reuse, c[0x0][0x174], R2 ; /* 0x00005d00040d7a24 */
/* 0x040fe400078e0202 */
/*03f0*/ IMAD R9, R4, c[0x0][0x174], R5.reuse ; /* 0x00005d0004097a24 */
/* 0x100fe200078e0205 */
/*0400*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0410*/ IMAD R7, R16, c[0x0][0x174], R5 ; /* 0x00005d0010077a24 */
/* 0x000fc600078e0205 */
/*0420*/ IADD3 R8, P2, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe40007f5e0ff */
/*0430*/ SEL R15, R3, RZ, !P0 ; /* 0x000000ff030f7207 */
/* 0x000fe40004000000 */
/*0440*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P2 ; /* 0x0000590009097a11 */
/* 0x000fe400010f0eff */
/*0450*/ IADD3 R6, P1, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x040fe20007f3e0ff */
/*0460*/ IMAD R11, R4, c[0x0][0x174], R15 ; /* 0x00005d00040b7a24 */
/* 0x000fe200078e020f */
/*0470*/ IADD3 R14, R16, 0x1, RZ ; /* 0x00000001100e7810 */
/* 0x000fe20007ffe0ff */
/*0480*/ LDG.E.U8 R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000a2000c1e1100 */
/*0490*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P1 ; /* 0x0000590007077a11 */
/* 0x000fc400008f0eff */
/*04a0*/ IADD3 R12, P1, R13, c[0x0][0x160], RZ ; /* 0x000058000d0c7a10 */
/* 0x000fe20007f3e0ff */
/*04b0*/ IMAD R16, R16, c[0x0][0x174], R15 ; /* 0x00005d0010107a24 */
/* 0x000fe200078e020f */
/*04c0*/ ISETP.GE.AND P0, PT, R14.reuse, c[0x0][0x170], PT ; /* 0x00005c000e007a0c */
/* 0x040fe20003f06270 */
/*04d0*/ LDG.E.U8 R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002e2000c1e1100 */
/*04e0*/ IADD3 R10, P2, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fe40007f5e0ff */
/*04f0*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x164], 0x1, P1 ; /* 0x000059000d0d7a11 */
/* 0x000fe400008f0eff */
/*0500*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P2 ; /* 0x000059000b0b7a11 */
/* 0x000fe400010f0eff */
/*0510*/ SEL R18, R14, RZ, !P0 ; /* 0x000000ff0e127207 */
/* 0x000fe20004000000 */
/*0520*/ LDG.E.U8 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001122000c1e1100 */
/*0530*/ IADD3 R14, P0, R16, c[0x0][0x160], RZ ; /* 0x00005800100e7a10 */
/* 0x000fc60007f1e0ff */
/*0540*/ LDG.E.U8 R9, [R10.64] ; /* 0x000000040a097981 */
/* 0x000b22000c1e1100 */
/*0550*/ IMAD R17, R18, c[0x0][0x174], R15 ; /* 0x00005d0012117a24 */
/* 0x000fe200078e020f */
/*0560*/ LEA.HI.X.SX32 R15, R16, c[0x0][0x164], 0x1, P0 ; /* 0x00005900100f7a11 */
/* 0x000fe200000f0eff */
/*0570*/ IMAD R2, R18, c[0x0][0x174], R2 ; /* 0x00005d0012027a24 */
/* 0x000fc600078e0202 */
/*0580*/ IADD3 R6, P0, R17.reuse, c[0x0][0x160], RZ ; /* 0x0000580011067a10 */
/* 0x042fe20007f1e0ff */
/*0590*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f26000c1e1100 */
/*05a0*/ LEA.HI.X.SX32 R7, R17, c[0x0][0x164], 0x1, P0 ; /* 0x0000590011077a11 */
/* 0x000fe400000f0eff */
/*05b0*/ IADD3 R16, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002107a10 */
/* 0x000fe20007f1e0ff */
/*05c0*/ IMAD R5, R18, c[0x0][0x174], R5 ; /* 0x00005d0012057a24 */
/* 0x000fe400078e0205 */
/*05d0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*05e0*/ LEA.HI.X.SX32 R17, R2, c[0x0][0x164], 0x1, P0 ; /* 0x0000590002117a11 */
/* 0x000fc400000f0eff */
/*05f0*/ IADD3 R10, P0, R5, c[0x0][0x160], RZ ; /* 0x00005800050a7a10 */
/* 0x020fc60007f1e0ff */
/*0600*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1100 */
/*0610*/ LEA.HI.X.SX32 R11, R5, c[0x0][0x164], 0x1, P0 ; /* 0x00005900050b7a11 */
/* 0x000fe400000f0eff */
/*0620*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0630*/ IADD3 R12, P0, R0, c[0x0][0x160], RZ ; /* 0x00005800000c7a10 */
/* 0x001fe20007f1e0ff */
/*0640*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f66000c1e1100 */
/*0650*/ IADD3.X R13, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900050d7a10 */
/* 0x000fca00007fe4ff */
/*0660*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1100 */
/*0670*/ ISETP.NE.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x004fe20003f25270 */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, 0x2 ; /* 0x00000002ff037424 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x008fc80003f05270 */
/*06a0*/ SEL R2, RZ, 0x1, P0 ; /* 0x00000001ff027807 */
/* 0x000fce0000000000 */
/*06b0*/ @!P1 SEL R2, R3, 0x1, !P0 ; /* 0x0000000103029807 */
/* 0x000fe40004000000 */
/*06c0*/ ISETP.NE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x010fe40003f45270 */
/*06d0*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f05270 */
/*06e0*/ SEL R3, RZ, 0x1, P2 ; /* 0x00000001ff037807 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc60003f25270 */
/*0700*/ IMAD.IADD R2, R2, 0x1, R3 ; /* 0x0000000102027824 */
/* 0x000fca00078e0203 */
/*0710*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0720*/ @P0 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0202 */
/*0730*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc80003f05270 */
/*0740*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @P1 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff021224 */
/* 0x000fe200078e0203 */
/*0760*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fc80003f25270 */
/*0770*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc60007ffe0ff */
/*0780*/ @P0 IMAD.MOV R3, RZ, RZ, R2 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0202 */
/*0790*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f05270 */
/*07a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ @P1 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff041224 */
/* 0x000fe200078e0203 */
/*07c0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f25270 */
/*07d0*/ IADD3 R2, P2, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fe40007f5e0ff */
/*07e0*/ IADD3 R0, R4, 0x1, RZ ; /* 0x0000000104007810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3.X R3, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005037a10 */
/* 0x000fe200017fe4ff */
/*0800*/ @P0 IMAD.MOV R0, RZ, RZ, R4 ; /* 0x000000ffff000224 */
/* 0x000fcc00078e0204 */
/*0810*/ @!P1 BRA 0x880 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f05270 */
/*0830*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*0840*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fca00078e00ff */
/*0860*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ LOP3.LUT R0, R0, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe00007812 */
/* 0x000fc800078ec0ff */
/*0890*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f05270 */
/*08a0*/ @P0 STG.E.U8 [R2.64], RZ ; /* 0x000000ff02000986 */
/* 0x0001e2000c101104 */
/*08b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fca00078e00ff */
/*08d0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12conwayThreadPcS_ii
.globl _Z12conwayThreadPcS_ii
.p2align 8
.type _Z12conwayThreadPcS_ii,@function
_Z12conwayThreadPcS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
s_ashr_i32 s3, s4, 31
s_ashr_i32 s2, s5, 31
s_add_i32 s6, s4, s3
s_add_i32 s7, s5, s2
s_xor_b32 s6, s6, s3
s_xor_b32 s7, s7, s2
v_cvt_f32_u32_e32 v0, s6
v_cvt_f32_u32_e32 v2, s7
s_sub_i32 s2, 0, s6
s_sub_i32 s8, 0, s7
v_ashrrev_i32_e32 v5, 31, v1
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v5
v_xor_b32_e32 v6, v6, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s2, v0
v_mul_lo_u32 v4, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v6, v0
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s6
v_mul_lo_u32 v2, v2, s7
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v6, v3
v_sub_nc_u32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_subrev_nc_u32_e32 v7, s7, v2
v_cmp_le_u32_e64 s2, s7, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v3, v3, v6
v_cndmask_b32_e64 v2, v2, v7, s2
v_xor_b32_e32 v6, s3, v5
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_subrev_nc_u32_e32 v7, s7, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v0, v0, v6
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v6
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 1, v0
v_sub_nc_u32_e32 v3, v2, v5
v_mul_lo_u32 v4, v0, s5
v_cndmask_b32_e64 v2, v0, s4, vcc_lo
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_i32_e32 vcc_lo, 1, v3
v_add_nc_u32_e32 v6, 1, v3
v_add_nc_u32_e32 v2, -1, v2
v_cndmask_b32_e64 v5, v3, s5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v7, v2, s5
v_ashrrev_i32_e32 v2, 31, v1
v_dual_cndmask_b32 v0, 0, v0 :: v_dual_add_nc_u32 v5, -1, v5
v_cmp_gt_i32_e32 vcc_lo, s5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, v5, v4
v_mul_lo_u32 v0, v0, s5
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_add_nc_u32_e32 v10, v7, v5
v_add_nc_u32_e32 v11, v7, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v9, v6, v4
v_ashrrev_i32_e32 v4, 31, v8
v_add_nc_u32_e32 v12, v7, v6
v_add_nc_u32_e32 v13, v0, v6
v_add_nc_u32_e32 v14, v0, v3
v_ashrrev_i32_e32 v6, 31, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_nc_u32_e32 v0, v0, v5
v_ashrrev_i32_e32 v15, 31, v10
v_add_co_u32 v5, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_ashrrev_i32_e32 v16, 31, v11
v_add_co_u32 v7, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v15, vcc_lo
v_ashrrev_i32_e32 v17, 31, v12
v_add_co_u32 v9, vcc_lo, s0, v11
global_load_u8 v15, v[3:4], off
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v17, vcc_lo
v_ashrrev_i32_e32 v18, 31, v13
v_add_co_u32 v3, vcc_lo, s0, v13
s_clause 0x1
global_load_u8 v13, v[7:8], off
global_load_u8 v9, v[9:10], off
v_ashrrev_i32_e32 v19, 31, v14
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v18, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v14
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v19, vcc_lo
s_clause 0x3
global_load_u8 v11, v[11:12], off
global_load_u8 v12, v[5:6], off
global_load_u8 v14, v[3:4], off
global_load_u8 v7, v[7:8], off
v_ashrrev_i32_e32 v10, 31, v0
v_add_co_u32 v3, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_u8 v0, v[3:4], off
global_load_u8 v3, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(8)
v_cmp_eq_u16_e32 vcc_lo, 1, v15
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_cndmask_b32_e64 v5, 1, 2, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_eq_u16_e32 vcc_lo, 1, v9
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v13
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_eq_u16_e32 vcc_lo, 1, v12
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v11
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(2)
v_cmp_eq_u16_e32 vcc_lo, 1, v7
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_eq_u16_e32 vcc_lo, 1, v14
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_eq_u16_e32 vcc_lo, 1, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v0, vcc_lo, v4, v6, vcc_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 1, v3
s_xor_b32 s1, exec_lo, s0
s_cbranch_execz .LBB0_7
v_cmp_ne_u32_e32 vcc_lo, 3, v0
v_add_co_u32 v0, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v1, s0, s3, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_7:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v0, -4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e32 vcc_lo, -3, v0
v_add_co_u32 v0, s0, s2, v1
v_add_co_ci_u32_e64 v1, s0, s3, v2, s0
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_10:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v2, 0
global_store_b8 v[0:1], v2, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12conwayThreadPcS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12conwayThreadPcS_ii, .Lfunc_end0-_Z12conwayThreadPcS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12conwayThreadPcS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12conwayThreadPcS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a90e4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11idxToCoordsiPiS_ii
.type _Z11idxToCoordsiPiS_ii, @function
_Z11idxToCoordsiPiS_ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11idxToCoordsiPiS_ii, .-_Z11idxToCoordsiPiS_ii
.globl _Z11coordsToIdxiiPiii
.type _Z11coordsToIdxiiPiii, @function
_Z11coordsToIdxiiPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11coordsToIdxiiPiii, .-_Z11coordsToIdxiiPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-"
.LC1:
.string "0"
.LC2:
.string "\n"
.text
.globl _Z10printBoardPcii
.type _Z10printBoardPcii, @function
_Z10printBoardPcii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, %r15d
movl $0, %r14d
movl $0, (%rsp)
leaq .LC1(%rip), %r13
leaq .LC0(%rip), %r12
testl %esi, %esi
jg .L8
.L7:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $1, %rbx
cmpq %rbp, %rbx
je .L19
.L12:
cmpb $0, (%rbx)
jne .L10
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L19:
addl %r15d, (%rsp)
.L14:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl %r14d, 4(%rsp)
je .L7
.L8:
testl %r15d, %r15d
jle .L14
movslq (%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax), %rbx
movslq %r15d, %rbp
addq %rcx, %rbp
addq %rax, %rbp
jmp .L12
.cfi_endproc
.LFE2059:
.size _Z10printBoardPcii, .-_Z10printBoardPcii
.globl _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
.type _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii, @function
_Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12conwayThreadPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii, .-_Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
.globl _Z12conwayThreadPcS_ii
.type _Z12conwayThreadPcS_ii, @function
_Z12conwayThreadPcS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12conwayThreadPcS_ii, .-_Z12conwayThreadPcS_ii
.section .rodata.str1.1
.LC3:
.string "Beginning state:\n"
.LC4:
.string "Error setting device\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Error allocating previous state\n"
.section .rodata.str1.1
.LC6:
.string "Error allocating next state\n"
.LC7:
.string "Error copying previous state\n"
.LC8:
.string "Error copying next state\n"
.LC9:
.string "Error launching kernel\n"
.LC10:
.string "%s\n"
.LC11:
.string "Error synchronizing device\n"
.LC12:
.string "Final state\n"
.LC13:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -131072(%rsp), %r11
.cfi_def_cfa 11, 131112
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1112, %rsp
.cfi_def_cfa_offset 132224
movq %fs:40, %rax
movq %rax, 132168(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $0, %edi
call srand@PLT
leaq 1088(%rsp), %rbx
leaq 66624(%rsp), %rbp
.L29:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1088(%rsp), %rdi
movl $256, %edx
movl $256, %esi
call _Z10printBoardPcii
movl $0, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %esi
movl 368(%rsp), %ecx
movl $65536, %eax
movl $0, %edx
idivl %ecx
testl %edx, %edx
je .L30
movl %ecx, %eax
subl %edx, %eax
addl $65536, %eax
cltd
idivl %ecx
movl %eax, %ebx
.L31:
testl %esi, %esi
je .L32
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L30:
movl $65536, %eax
movl $0, %edx
idivl %ecx
movl %eax, %ebx
jmp .L31
.L32:
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L33
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L33:
leaq 16(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
je .L34
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L34:
leaq 1088(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L35
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
leaq 66624(%rsp), %rsi
movl $1, %ecx
movl $65536, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
sall $2, %ebx
movl $100, %r12d
movl $4, %r13d
jmp .L40
.L47:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L37:
call cudaGetLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L48
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L49
movl $3, %ecx
movl $65536, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %r12d
je .L50
.L40:
movl 368(%rsp), %eax
cltd
idivl %r13d
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ebx, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movl $256, %ecx
movl $256, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z12conwayThreadPcS_iiPcS_ii
jmp .L37
.L48:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L49:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L50:
leaq 66624(%rsp), %rbx
movl $2, %ecx
movl $65536, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, %edx
movl $256, %esi
movq %rbx, %rdi
call _Z10printBoardPcii
call cudaDeviceReset@PLT
movl %eax, %edx
movl $0, %eax
testl %edx, %edx
jne .L51
.L28:
movq 132168(%rsp), %rdx
subq %fs:40, %rdx
jne .L52
addq $132184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z12conwayThreadPcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12conwayThreadPcS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z27__device_stub__conwayThreadPcS_ii # -- Begin function _Z27__device_stub__conwayThreadPcS_ii
.p2align 4, 0x90
.type _Z27__device_stub__conwayThreadPcS_ii,@function
_Z27__device_stub__conwayThreadPcS_ii: # @_Z27__device_stub__conwayThreadPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12conwayThreadPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__conwayThreadPcS_ii, .Lfunc_end0-_Z27__device_stub__conwayThreadPcS_ii
.cfi_endproc
# -- End function
.globl _Z10printBoardPcii # -- Begin function _Z10printBoardPcii
.p2align 4, 0x90
.type _Z10printBoardPcii,@function
_Z10printBoardPcii: # @_Z10printBoardPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 8(%rsp) # 4-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
xorl %r15d, %r15d
movl 8(%rsp), %eax # 4-byte Reload
testl %eax, %eax
movl $0, %r12d
cmovgl %eax, %r12d
movl %eax, %r13d
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r14d
addl %r12d, %r15d
cmpl 12(%rsp), %r14d # 4-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movslq %r15d, %rbp
addq 16(%rsp), %rbp # 8-byte Folded Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%rbp,%rbx)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %rbx
cmpl %ebx, %r13d
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10printBoardPcii, .Lfunc_end1-_Z10printBoardPcii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $132680, %rsp # imm = 0x20648
.cfi_def_cfa_offset 132736
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 16(%rsp)
movq $0, 8(%rsp)
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $254, %ecx
subl %ecx, %eax
movb %al, 1600(%rsp,%rbx)
incq %rbx
cmpq $65536, %rbx # imm = 0x10000
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
leaq 1600(%rsp), %r14
.p2align 4, 0x90
.LBB2_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%r14,%r15)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %r15
cmpl $256, %r15d # imm = 0x100
jne .LBB2_4
# %bb.5: # %._crit_edge.loopexit.i
# in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
addq $256, %r14 # imm = 0x100
cmpl $256, %ebx # imm = 0x100
jne .LBB2_3
# %bb.6: # %_Z10printBoardPcii.exit
xorl %edi, %edi
callq hipSetDevice
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl %eax, %ecx
movl 448(%rsp), %esi
movl $65536, %edi # imm = 0x10000
movl $65536, %eax # imm = 0x10000
xorl %edx, %edx
idivl %esi
movl %esi, %eax
subl %edx, %eax
addl $65536, %eax # imm = 0x10000
testl %edx, %edx
cmovel %edi, %eax
cltd
idivl %esi
testl %ecx, %ecx
jne .LBB2_7
# %bb.9:
movl %eax, %r14d
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq 16(%rsp), %rdi
leaq 1600(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 8(%rsp), %rdi
leaq 67136(%rsp), %rbx
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_21
# %bb.16: # %.preheader
movabsq $4294967296, %r13 # imm = 0x100000000
shll $2, %r14d
orq %r13, %r14
movl $100, %ebp
leaq 96(%rsp), %r15
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movl 448(%rsp), %eax
leal 3(%rax), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $2, %edx
orq %r13, %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $256, 28(%rsp) # imm = 0x100
movl $256, 24(%rsp) # imm = 0x100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z12conwayThreadPcS_ii, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB2_20
# %bb.30: # in Loop: Header=BB2_17 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_31
# %bb.22: # in Loop: Header=BB2_17 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movl $3, %ecx
callq hipMemcpy
decl %ebp
jne .LBB2_17
# %bb.23:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_24: # %.preheader.i40
# =>This Loop Header: Depth=1
# Child Loop BB2_25 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_25: # %.lr.ph.i43
# Parent Loop BB2_24 Depth=1
# => This Inner Loop Header: Depth=2
xorl %eax, %eax
cmpb $0, (%rbx,%r15)
setne %al
leal (%rax,%rax,2), %edi
addl $45, %edi
callq putchar@PLT
incq %r15
cmpl $256, %r15d # imm = 0x100
jne .LBB2_25
# %bb.26: # %._crit_edge.loopexit.i49
# in Loop: Header=BB2_24 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r14d
addq $256, %rbx # imm = 0x100
cmpl $256, %r14d # imm = 0x100
jne .LBB2_24
# %bb.27: # %_Z10printBoardPcii.exit53
callq hipDeviceReset
movl %eax, %ecx
xorl %eax, %eax
testl %ecx, %ecx
jne .LBB2_28
.LBB2_29:
addq $132680, %rsp # imm = 0x20648
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_28:
.cfi_def_cfa_offset 132736
movq stderr(%rip), %rcx
movl $.L.str.13, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB2_29
.LBB2_31:
movl $.Lstr.2, %edi
jmp .LBB2_8
.LBB2_20:
movl %eax, %r12d
movl $.Lstr.3, %edi
callq puts@PLT
movl %r12d, %edi
callq hipGetErrorString
movq %rax, %rdi
.LBB2_8:
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB2_7:
movl $.Lstr.8, %edi
jmp .LBB2_8
.LBB2_10:
movl $.Lstr.7, %edi
jmp .LBB2_8
.LBB2_12:
movl $.Lstr.6, %edi
jmp .LBB2_8
.LBB2_14:
movl $.Lstr.5, %edi
jmp .LBB2_8
.LBB2_21:
movl $.Lstr.4, %edi
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12conwayThreadPcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12conwayThreadPcS_ii,@object # @_Z12conwayThreadPcS_ii
.section .rodata,"a",@progbits
.globl _Z12conwayThreadPcS_ii
.p2align 3, 0x0
_Z12conwayThreadPcS_ii:
.quad _Z27__device_stub__conwayThreadPcS_ii
.size _Z12conwayThreadPcS_ii, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "hipDeviceReset failed!"
.size .L.str.13, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12conwayThreadPcS_ii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Beginning state:"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Final state"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error synchronizing device"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error launching kernel"
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error copying next state"
.size .Lstr.4, 25
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error copying previous state"
.size .Lstr.5, 29
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Error allocating next state"
.size .Lstr.6, 28
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Error allocating previous state"
.size .Lstr.7, 32
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Error setting device"
.size .Lstr.8, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__conwayThreadPcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12conwayThreadPcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(int),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | code for sm_80
Function : _Z15my_first_kernelILi3EEvPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff097435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R11, 0x437c0000 ; /* 0x437c0000000b7802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*0080*/ FFMA.SAT R4, R2, R9, 0.5 ; /* 0x3f00000002047423 */
/* 0x001fe40000002009 */
/*0090*/ FMUL R3, RZ, R2 ; /* 0x00000002ff037220 */
/* 0x000fe40000400000 */
/*00a0*/ FFMA.RM R5, R4, R11, 12582913 ; /* 0x4b40000104057423 */
/* 0x000fe4000000400b */
/*00b0*/ FFMA.SAT R4, R3, R9, 0.5 ; /* 0x3f00000003047423 */
/* 0x000fe40000002009 */
/*00c0*/ FADD R8, R2, R2 ; /* 0x0000000202087221 */
/* 0x000fc40000000000 */
/*00d0*/ FFMA.RM R4, R4, R11, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fe4000000400b */
/*00e0*/ FFMA.SAT R9, R8, R9, 0.5 ; /* 0x3f00000008097423 */
/* 0x000fe40000002009 */
/*00f0*/ FADD R6, R4.reuse, -12583039 ; /* 0xcb40007f04067421 */
/* 0x040fe20000000000 */
/*0100*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fe200000006ff */
/*0110*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe20000000000 */
/*0120*/ SHF.L.U32 R5, R5, 0x17, RZ ; /* 0x0000001705057819 */
/* 0x000fe200000006ff */
/*0130*/ FFMA.RM R9, R9, R11, 12582913 ; /* 0x4b40000109097423 */
/* 0x000fe4000000400b */
/*0140*/ FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03067823 */
/* 0x000fc40000000806 */
/*0150*/ FFMA R7, R2.reuse, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b02077823 */
/* 0x040fe40000000807 */
/*0160*/ FADD R11, R9.reuse, -12583039 ; /* 0xcb40007f090b7421 */
/* 0x040fe20000000000 */
/*0170*/ SHF.L.U32 R9, R9, 0x17, RZ ; /* 0x0000001709097819 */
/* 0x000fe200000006ff */
/*0180*/ FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003067823 */
/* 0x000fe40000000006 */
/*0190*/ FFMA R7, R2, 1.925963033500011079e-08, R7 ; /* 0x32a5706002077823 */
/* 0x000fe40000000007 */
/*01a0*/ FFMA R11, R8.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b080b7823 */
/* 0x040fe2000000080b */
/*01b0*/ MUFU.EX2 R3, R6 ; /* 0x0000000600037308 */
/* 0x000e260000000800 */
/*01c0*/ FFMA R11, R8, 1.925963033500011079e-08, R11 ; /* 0x32a57060080b7823 */
/* 0x000fca000000000b */
/*01d0*/ MUFU.EX2 R2, R7 ; /* 0x0000000700027308 */
/* 0x000e700000000800 */
/*01e0*/ MUFU.EX2 R8, R11 ; /* 0x0000000b00087308 */
/* 0x000ea20000000800 */
/*01f0*/ FMUL R3, R4, R3 ; /* 0x0000000304037220 */
/* 0x001fc80000400000 */
/*0200*/ FFMA R4, R3, R3, RZ ; /* 0x0000000303047223 */
/* 0x000fe400000000ff */
/*0210*/ FMUL R2, R5, R2 ; /* 0x0000000205027220 */
/* 0x002fc80000400000 */
/*0220*/ FFMA R4, R3, R2, R4 ; /* 0x0000000203047223 */
/* 0x000fe40000000004 */
/*0230*/ FMUL R8, R9, R8 ; /* 0x0000000809087220 */
/* 0x004fc80000400000 */
/*0240*/ FFMA R4, R3, R8, R4 ; /* 0x0000000803047223 */
/* 0x000fc80000000004 */
/*0250*/ FFMA R5, R3, R2, R4 ; /* 0x0000000203057223 */
/* 0x000fc80000000004 */
/*0260*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x000fc80000000005 */
/*0270*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x000fc80000000005 */
/*0280*/ FFMA R5, R3, R8, R5 ; /* 0x0000000803057223 */
/* 0x000fe20000000005 */
/*0290*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*02a0*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x000fc80000000005 */
/*02b0*/ FFMA R5, R8, R8, R5 ; /* 0x0000000808057223 */
/* 0x000fc60000000005 */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15my_first_kernelILi2EEvPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x437c0000 ; /* 0x437c000000077802 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0202 */
/*0080*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x000e240000201400 */
/*0090*/ FMUL R3, RZ, R0 ; /* 0x00000000ff037220 */
/* 0x001fc80000400000 */
/*00a0*/ FFMA.SAT R4, R3, R5.reuse, 0.5 ; /* 0x3f00000003047423 */
/* 0x080fe40000002005 */
/*00b0*/ FFMA.SAT R5, R0, R5, 0.5 ; /* 0x3f00000000057423 */
/* 0x000fe40000002005 */
/*00c0*/ FFMA.RM R4, R4, R7.reuse, 12582913 ; /* 0x4b40000104047423 */
/* 0x080fe40000004007 */
/*00d0*/ FFMA.RM R5, R5, R7, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fe40000004007 */
/*00e0*/ FADD R6, R4.reuse, -12583039 ; /* 0xcb40007f04067421 */
/* 0x040fe20000000000 */
/*00f0*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fe200000006ff */
/*0100*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe20000000000 */
/*0110*/ SHF.L.U32 R5, R5, 0x17, RZ ; /* 0x0000001705057819 */
/* 0x000fe200000006ff */
/*0120*/ FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03067823 */
/* 0x000fc40000000806 */
/*0130*/ FFMA R7, R0.reuse, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b00077823 */
/* 0x040fe40000000807 */
/*0140*/ FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003067823 */
/* 0x000fe40000000006 */
/*0150*/ FFMA R7, R0, 1.925963033500011079e-08, R7 ; /* 0x32a5706000077823 */
/* 0x000fe40000000007 */
/*0160*/ MUFU.EX2 R3, R6 ; /* 0x0000000600037308 */
/* 0x000e300000000800 */
/*0170*/ MUFU.EX2 R0, R7 ; /* 0x0000000700007308 */
/* 0x000e620000000800 */
/*0180*/ FMUL R3, R4, R3 ; /* 0x0000000304037220 */
/* 0x001fc80000400000 */
/*0190*/ FFMA R4, R3, R3, RZ ; /* 0x0000000303047223 */
/* 0x000fe400000000ff */
/*01a0*/ FMUL R0, R5, R0 ; /* 0x0000000005007220 */
/* 0x002fc80000400000 */
/*01b0*/ FFMA R4, R3, R0, R4 ; /* 0x0000000003047223 */
/* 0x000fc80000000004 */
/*01c0*/ FFMA R5, R3, R0, R4 ; /* 0x0000000003057223 */
/* 0x000fe40000000004 */
/*01d0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*01e0*/ FFMA R5, R0, R0, R5 ; /* 0x0000000000057223 */
/* 0x000fca0000000005 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(int),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | .file "tmpxft_001a6f8b_00000000-6_prac6c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf, @function
_ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf:
.LFB2084:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelILi2EEvPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf, .-_ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.weak _Z15my_first_kernelILi2EEvPf
.type _Z15my_first_kernelILi2EEvPf, @function
_Z15my_first_kernelILi2EEvPf:
.LFB2135:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2135:
.size _Z15my_first_kernelILi2EEvPf, .-_Z15my_first_kernelILi2EEvPf
.text
.type _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf, @function
_ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf:
.LFB2086:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelILi3EEvPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf, .-_ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.weak _Z15my_first_kernelILi3EEvPf
.type _Z15my_first_kernelILi3EEvPf, @function
_Z15my_first_kernelILi3EEvPf:
.LFB2136:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2136:
.size _Z15my_first_kernelILi3EEvPf, .-_Z15my_first_kernelILi3EEvPf
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " n, x = %d %g \n"
.LC1:
.string " n, i = %d %g \n"
.text
.globl _Z5prac6ii
.type _Z5prac6ii, @function
_Z5prac6ii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %edi, 8(%rsp)
movl %esi, %r13d
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %r15d
imull %esi, %r15d
movslq %r15d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L21
movl $0, %ebx
leaq .LC0(%rip), %r13
.L22:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L22
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
.L28:
movl $0, %ebx
leaq .LC1(%rip), %r13
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L25
.L24:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 24(%rsp), %rdi
call _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
jmp .L20
.L27:
movq 24(%rsp), %rdi
call _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jg .L28
jmp .L24
.L21:
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5prac6ii, .-_Z5prac6ii
.section .rodata.str1.1
.LC2:
.string "_Z15my_first_kernelILi3EEvPf"
.LC3:
.string "_Z15my_first_kernelILi2EEvPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelILi3EEvPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelILi2EEvPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
cudaMemcpy(h_x,d_x,nsize*sizeof(int),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(int),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(int),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.protected _Z15my_first_kernelILi2EEvPf
.globl _Z15my_first_kernelILi2EEvPf
.p2align 8
.type _Z15my_first_kernelILi2EEvPf,@function
_Z15my_first_kernelILi2EEvPf:
s_load_b32 s2, s[0:1], 0x14
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_i32_e32 v3, v1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_cvt_f32_i32_e32 v4, s4
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v4
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v6, v4, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v7, v5
v_sub_f32_e32 v5, v5, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0x32a5705f, v4
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 0
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cndmask_b32_e64 v0, v0, v4, s2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 1
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 1
s_mov_b64 s[2:3], 0
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v4, v0, v2, vcc_lo
.LBB0_4:
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v5, v0, v2, vcc_lo
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 1
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v5
s_cbranch_scc0 .LBB0_4
s_add_i32 s2, s4, 1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_7
s_mov_b32 s4, s2
s_branch .LBB0_3
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelILi2EEvPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.Lfunc_end0:
.size _Z15my_first_kernelILi2EEvPf, .Lfunc_end0-_Z15my_first_kernelILi2EEvPf
.section .AMDGPU.csdata,"",@progbits
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.protected _Z15my_first_kernelILi3EEvPf
.globl _Z15my_first_kernelILi3EEvPf
.p2align 8
.type _Z15my_first_kernelILi3EEvPf,@function
_Z15my_first_kernelILi3EEvPf:
s_load_b32 s2, s[0:1], 0x14
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_i32_e32 v4, v1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_1:
v_cvt_f32_i32_e32 v5, s4
s_cmp_eq_u32 s4, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v5
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_sub_f32_e32 v6, v6, v8
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, 0x32a5705f, v5
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 1
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_cmp_eq_u32 s4, 0
v_cndmask_b32_e64 v2, v2, v5, s2
s_cselect_b32 s3, -1, 0
s_add_u32 s4, s4, 1
v_cndmask_b32_e64 v0, v0, v5, s3
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 3
s_cbranch_scc1 .LBB1_1
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v4, 0
s_mov_b32 s4, 0
.p2align 6
.LBB1_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 1
s_mov_b64 s[2:3], 0
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 2
v_cndmask_b32_e32 v5, v0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v3, vcc_lo
.LBB1_4:
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v6, v0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
v_cndmask_b32_e32 v6, v6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v6
s_cbranch_scc0 .LBB1_4
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 3
s_cbranch_scc0 .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelILi3EEvPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.Lfunc_end1:
.size _Z15my_first_kernelILi3EEvPf, .Lfunc_end1-_Z15my_first_kernelILi3EEvPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelILi2EEvPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelILi2EEvPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelILi3EEvPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelILi3EEvPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// template kernel routine
//
template <int size>
__global__ void my_first_kernel(float *x)
{
float xl[size];
int tid = threadIdx.x + blockDim.x*blockIdx.x;
for (int i=0; i<size; i++) {
xl[i] = expf((float) i*tid);
}
float sum = 0.0f;
for (int i=0; i<size; i++) {
for (int j=0; j<size; j++) {
sum += xl[i]*xl[j];
}
}
x[tid] = sum;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel for size=2
my_first_kernel<2><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %g \n",n,h_x[n]);
// execute kernel for size=3
my_first_kernel<3><<<nblocks,nthreads>>>(d_x);
hipMemcpy(h_x,d_x,nsize*sizeof(int),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, i = %d %g \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} | .text
.file "prac6c.hip"
.globl _Z5prac6ii # -- Begin function _Z5prac6ii
.p2align 4, 0x90
.type _Z5prac6ii,@function
_Z5prac6ii: # @_Z5prac6ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %r13d
imull %edi, %r13d
movslq %r13d, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %ebp, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelILi2EEvPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r13d, %ebp
movl %r13d, 84(%rsp) # 4-byte Spill
testl %r13d, %r13d
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
jne .LBB0_4
.LBB0_5: # %._crit_edge
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelILi3EEvPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 84(%rsp) # 4-byte Folded Reload
jle .LBB0_10
# %bb.8: # %.lr.ph50.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB0_9
.LBB0_10: # %._crit_edge51
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5prac6ii, .Lfunc_end0-_Z5prac6ii
.cfi_endproc
# -- End function
.section .text._Z30__device_stub__my_first_kernelILi2EEvPf,"axG",@progbits,_Z30__device_stub__my_first_kernelILi2EEvPf,comdat
.weak _Z30__device_stub__my_first_kernelILi2EEvPf # -- Begin function _Z30__device_stub__my_first_kernelILi2EEvPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelILi2EEvPf,@function
_Z30__device_stub__my_first_kernelILi2EEvPf: # @_Z30__device_stub__my_first_kernelILi2EEvPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelILi2EEvPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__my_first_kernelILi2EEvPf, .Lfunc_end1-_Z30__device_stub__my_first_kernelILi2EEvPf
.cfi_endproc
# -- End function
.section .text._Z30__device_stub__my_first_kernelILi3EEvPf,"axG",@progbits,_Z30__device_stub__my_first_kernelILi3EEvPf,comdat
.weak _Z30__device_stub__my_first_kernelILi3EEvPf # -- Begin function _Z30__device_stub__my_first_kernelILi3EEvPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelILi3EEvPf,@function
_Z30__device_stub__my_first_kernelILi3EEvPf: # @_Z30__device_stub__my_first_kernelILi3EEvPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelILi3EEvPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__my_first_kernelILi3EEvPf, .Lfunc_end2-_Z30__device_stub__my_first_kernelILi3EEvPf
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelILi2EEvPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelILi3EEvPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelILi2EEvPf,@object # @_Z15my_first_kernelILi2EEvPf
.section .rodata._Z15my_first_kernelILi2EEvPf,"aG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.weak _Z15my_first_kernelILi2EEvPf
.p2align 3, 0x0
_Z15my_first_kernelILi2EEvPf:
.quad _Z30__device_stub__my_first_kernelILi2EEvPf
.size _Z15my_first_kernelILi2EEvPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " n, x = %d %g \n"
.size .L.str, 20
.type _Z15my_first_kernelILi3EEvPf,@object # @_Z15my_first_kernelILi3EEvPf
.section .rodata._Z15my_first_kernelILi3EEvPf,"aG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.weak _Z15my_first_kernelILi3EEvPf
.p2align 3, 0x0
_Z15my_first_kernelILi3EEvPf:
.quad _Z30__device_stub__my_first_kernelILi3EEvPf
.size _Z15my_first_kernelILi3EEvPf, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " n, i = %d %g \n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelILi2EEvPf"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15my_first_kernelILi3EEvPf"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelILi2EEvPf
.addrsig_sym _Z30__device_stub__my_first_kernelILi3EEvPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelILi2EEvPf
.addrsig_sym _Z15my_first_kernelILi3EEvPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15my_first_kernelILi3EEvPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff097435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R11, 0x437c0000 ; /* 0x437c0000000b7802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*0080*/ FFMA.SAT R4, R2, R9, 0.5 ; /* 0x3f00000002047423 */
/* 0x001fe40000002009 */
/*0090*/ FMUL R3, RZ, R2 ; /* 0x00000002ff037220 */
/* 0x000fe40000400000 */
/*00a0*/ FFMA.RM R5, R4, R11, 12582913 ; /* 0x4b40000104057423 */
/* 0x000fe4000000400b */
/*00b0*/ FFMA.SAT R4, R3, R9, 0.5 ; /* 0x3f00000003047423 */
/* 0x000fe40000002009 */
/*00c0*/ FADD R8, R2, R2 ; /* 0x0000000202087221 */
/* 0x000fc40000000000 */
/*00d0*/ FFMA.RM R4, R4, R11, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fe4000000400b */
/*00e0*/ FFMA.SAT R9, R8, R9, 0.5 ; /* 0x3f00000008097423 */
/* 0x000fe40000002009 */
/*00f0*/ FADD R6, R4.reuse, -12583039 ; /* 0xcb40007f04067421 */
/* 0x040fe20000000000 */
/*0100*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fe200000006ff */
/*0110*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe20000000000 */
/*0120*/ SHF.L.U32 R5, R5, 0x17, RZ ; /* 0x0000001705057819 */
/* 0x000fe200000006ff */
/*0130*/ FFMA.RM R9, R9, R11, 12582913 ; /* 0x4b40000109097423 */
/* 0x000fe4000000400b */
/*0140*/ FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03067823 */
/* 0x000fc40000000806 */
/*0150*/ FFMA R7, R2.reuse, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b02077823 */
/* 0x040fe40000000807 */
/*0160*/ FADD R11, R9.reuse, -12583039 ; /* 0xcb40007f090b7421 */
/* 0x040fe20000000000 */
/*0170*/ SHF.L.U32 R9, R9, 0x17, RZ ; /* 0x0000001709097819 */
/* 0x000fe200000006ff */
/*0180*/ FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003067823 */
/* 0x000fe40000000006 */
/*0190*/ FFMA R7, R2, 1.925963033500011079e-08, R7 ; /* 0x32a5706002077823 */
/* 0x000fe40000000007 */
/*01a0*/ FFMA R11, R8.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b080b7823 */
/* 0x040fe2000000080b */
/*01b0*/ MUFU.EX2 R3, R6 ; /* 0x0000000600037308 */
/* 0x000e260000000800 */
/*01c0*/ FFMA R11, R8, 1.925963033500011079e-08, R11 ; /* 0x32a57060080b7823 */
/* 0x000fca000000000b */
/*01d0*/ MUFU.EX2 R2, R7 ; /* 0x0000000700027308 */
/* 0x000e700000000800 */
/*01e0*/ MUFU.EX2 R8, R11 ; /* 0x0000000b00087308 */
/* 0x000ea20000000800 */
/*01f0*/ FMUL R3, R4, R3 ; /* 0x0000000304037220 */
/* 0x001fc80000400000 */
/*0200*/ FFMA R4, R3, R3, RZ ; /* 0x0000000303047223 */
/* 0x000fe400000000ff */
/*0210*/ FMUL R2, R5, R2 ; /* 0x0000000205027220 */
/* 0x002fc80000400000 */
/*0220*/ FFMA R4, R3, R2, R4 ; /* 0x0000000203047223 */
/* 0x000fe40000000004 */
/*0230*/ FMUL R8, R9, R8 ; /* 0x0000000809087220 */
/* 0x004fc80000400000 */
/*0240*/ FFMA R4, R3, R8, R4 ; /* 0x0000000803047223 */
/* 0x000fc80000000004 */
/*0250*/ FFMA R5, R3, R2, R4 ; /* 0x0000000203057223 */
/* 0x000fc80000000004 */
/*0260*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x000fc80000000005 */
/*0270*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x000fc80000000005 */
/*0280*/ FFMA R5, R3, R8, R5 ; /* 0x0000000803057223 */
/* 0x000fe20000000005 */
/*0290*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*02a0*/ FFMA R5, R2, R8, R5 ; /* 0x0000000802057223 */
/* 0x000fc80000000005 */
/*02b0*/ FFMA R5, R8, R8, R5 ; /* 0x0000000808057223 */
/* 0x000fc60000000005 */
/*02c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*02d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15my_first_kernelILi2EEvPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x437c0000 ; /* 0x437c000000077802 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0202 */
/*0080*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x000e240000201400 */
/*0090*/ FMUL R3, RZ, R0 ; /* 0x00000000ff037220 */
/* 0x001fc80000400000 */
/*00a0*/ FFMA.SAT R4, R3, R5.reuse, 0.5 ; /* 0x3f00000003047423 */
/* 0x080fe40000002005 */
/*00b0*/ FFMA.SAT R5, R0, R5, 0.5 ; /* 0x3f00000000057423 */
/* 0x000fe40000002005 */
/*00c0*/ FFMA.RM R4, R4, R7.reuse, 12582913 ; /* 0x4b40000104047423 */
/* 0x080fe40000004007 */
/*00d0*/ FFMA.RM R5, R5, R7, 12582913 ; /* 0x4b40000105057423 */
/* 0x000fe40000004007 */
/*00e0*/ FADD R6, R4.reuse, -12583039 ; /* 0xcb40007f04067421 */
/* 0x040fe20000000000 */
/*00f0*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fe200000006ff */
/*0100*/ FADD R7, R5.reuse, -12583039 ; /* 0xcb40007f05077421 */
/* 0x040fe20000000000 */
/*0110*/ SHF.L.U32 R5, R5, 0x17, RZ ; /* 0x0000001705057819 */
/* 0x000fe200000006ff */
/*0120*/ FFMA R6, R3, 1.4426950216293334961, -R6 ; /* 0x3fb8aa3b03067823 */
/* 0x000fc40000000806 */
/*0130*/ FFMA R7, R0.reuse, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b00077823 */
/* 0x040fe40000000807 */
/*0140*/ FFMA R6, R3, 1.925963033500011079e-08, R6 ; /* 0x32a5706003067823 */
/* 0x000fe40000000006 */
/*0150*/ FFMA R7, R0, 1.925963033500011079e-08, R7 ; /* 0x32a5706000077823 */
/* 0x000fe40000000007 */
/*0160*/ MUFU.EX2 R3, R6 ; /* 0x0000000600037308 */
/* 0x000e300000000800 */
/*0170*/ MUFU.EX2 R0, R7 ; /* 0x0000000700007308 */
/* 0x000e620000000800 */
/*0180*/ FMUL R3, R4, R3 ; /* 0x0000000304037220 */
/* 0x001fc80000400000 */
/*0190*/ FFMA R4, R3, R3, RZ ; /* 0x0000000303047223 */
/* 0x000fe400000000ff */
/*01a0*/ FMUL R0, R5, R0 ; /* 0x0000000005007220 */
/* 0x002fc80000400000 */
/*01b0*/ FFMA R4, R3, R0, R4 ; /* 0x0000000003047223 */
/* 0x000fc80000000004 */
/*01c0*/ FFMA R5, R3, R0, R4 ; /* 0x0000000003057223 */
/* 0x000fe40000000004 */
/*01d0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*01e0*/ FFMA R5, R0, R0, R5 ; /* 0x0000000000057223 */
/* 0x000fca0000000005 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.protected _Z15my_first_kernelILi2EEvPf
.globl _Z15my_first_kernelILi2EEvPf
.p2align 8
.type _Z15my_first_kernelILi2EEvPf,@function
_Z15my_first_kernelILi2EEvPf:
s_load_b32 s2, s[0:1], 0x14
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_i32_e32 v3, v1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_cvt_f32_i32_e32 v4, s4
s_cmp_eq_u32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v4
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v6, v4, 0x3fb8aa3b, -v5
v_rndne_f32_e32 v7, v5
v_sub_f32_e32 v5, v5, v7
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0x32a5705f, v4
v_add_f32_e32 v5, v5, v6
v_cvt_i32_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 0
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_cndmask_b32_e64 v0, v0, v4, s2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 1
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 1
s_mov_b64 s[2:3], 0
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v4, v0, v2, vcc_lo
.LBB0_4:
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v5, v0, v2, vcc_lo
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 1
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v5
s_cbranch_scc0 .LBB0_4
s_add_i32 s2, s4, 1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_7
s_mov_b32 s4, s2
s_branch .LBB0_3
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelILi2EEvPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.Lfunc_end0:
.size _Z15my_first_kernelILi2EEvPf, .Lfunc_end0-_Z15my_first_kernelILi2EEvPf
.section .AMDGPU.csdata,"",@progbits
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.protected _Z15my_first_kernelILi3EEvPf
.globl _Z15my_first_kernelILi3EEvPf
.p2align 8
.type _Z15my_first_kernelILi3EEvPf,@function
_Z15my_first_kernelILi3EEvPf:
s_load_b32 s2, s[0:1], 0x14
s_mov_b64 s[4:5], 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_i32_e32 v4, v1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_1:
v_cvt_f32_i32_e32 v5, s4
s_cmp_eq_u32 s4, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v4, v5
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_sub_f32_e32 v6, v6, v8
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, 0x32a5705f, v5
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 1
s_cselect_b32 s2, -1, 0
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_cmp_eq_u32 s4, 0
v_cndmask_b32_e64 v2, v2, v5, s2
s_cselect_b32 s3, -1, 0
s_add_u32 s4, s4, 1
v_cndmask_b32_e64 v0, v0, v5, s3
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 3
s_cbranch_scc1 .LBB1_1
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v4, 0
s_mov_b32 s4, 0
.p2align 6
.LBB1_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 1
s_mov_b64 s[2:3], 0
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s4, 2
v_cndmask_b32_e32 v5, v0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v3, vcc_lo
.LBB1_4:
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v6, v0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
v_cndmask_b32_e32 v6, v6, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v6
s_cbranch_scc0 .LBB1_4
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 3
s_cbranch_scc0 .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelILi3EEvPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.Lfunc_end1:
.size _Z15my_first_kernelILi3EEvPf, .Lfunc_end1-_Z15my_first_kernelILi3EEvPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelILi2EEvPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelILi2EEvPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelILi3EEvPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelILi3EEvPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6f8b_00000000-6_prac6c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf, @function
_ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf:
.LFB2084:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelILi2EEvPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf, .-_ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
.section .text._Z15my_first_kernelILi2EEvPf,"axG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.weak _Z15my_first_kernelILi2EEvPf
.type _Z15my_first_kernelILi2EEvPf, @function
_Z15my_first_kernelILi2EEvPf:
.LFB2135:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2135:
.size _Z15my_first_kernelILi2EEvPf, .-_Z15my_first_kernelILi2EEvPf
.text
.type _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf, @function
_ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf:
.LFB2086:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelILi3EEvPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf, .-_ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
.section .text._Z15my_first_kernelILi3EEvPf,"axG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.weak _Z15my_first_kernelILi3EEvPf
.type _Z15my_first_kernelILi3EEvPf, @function
_Z15my_first_kernelILi3EEvPf:
.LFB2136:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2136:
.size _Z15my_first_kernelILi3EEvPf, .-_Z15my_first_kernelILi3EEvPf
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " n, x = %d %g \n"
.LC1:
.string " n, i = %d %g \n"
.text
.globl _Z5prac6ii
.type _Z5prac6ii, @function
_Z5prac6ii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movl %edi, 8(%rsp)
movl %esi, %r13d
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %r15d
imull %esi, %r15d
movslq %r15d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L20:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L21
movl $0, %ebx
leaq .LC0(%rip), %r13
.L22:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L22
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
.L28:
movl $0, %ebx
leaq .LC1(%rip), %r13
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L25
.L24:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 24(%rsp), %rdi
call _ZL42__device_stub__Z15my_first_kernelILi2EEvPfPf
jmp .L20
.L27:
movq 24(%rsp), %rdi
call _ZL42__device_stub__Z15my_first_kernelILi3EEvPfPf
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jg .L28
jmp .L24
.L21:
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
jmp .L24
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z5prac6ii, .-_Z5prac6ii
.section .rodata.str1.1
.LC2:
.string "_Z15my_first_kernelILi3EEvPf"
.LC3:
.string "_Z15my_first_kernelILi2EEvPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelILi3EEvPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelILi2EEvPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prac6c.hip"
.globl _Z5prac6ii # -- Begin function _Z5prac6ii
.p2align 4, 0x90
.type _Z5prac6ii,@function
_Z5prac6ii: # @_Z5prac6ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %r13d
imull %edi, %r13d
movslq %r13d, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
movl %ebp, %r12d
orq %rax, %r12
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelILi2EEvPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %r13d, %ebp
movl %r13d, 84(%rsp) # 4-byte Spill
testl %r13d, %r13d
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbp
jne .LBB0_4
.LBB0_5: # %._crit_edge
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_7
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelILi3EEvPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_7:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 84(%rsp) # 4-byte Folded Reload
jle .LBB0_10
# %bb.8: # %.lr.ph50.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_9: # %.lr.ph50
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %rbp
jne .LBB0_9
.LBB0_10: # %._crit_edge51
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5prac6ii, .Lfunc_end0-_Z5prac6ii
.cfi_endproc
# -- End function
.section .text._Z30__device_stub__my_first_kernelILi2EEvPf,"axG",@progbits,_Z30__device_stub__my_first_kernelILi2EEvPf,comdat
.weak _Z30__device_stub__my_first_kernelILi2EEvPf # -- Begin function _Z30__device_stub__my_first_kernelILi2EEvPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelILi2EEvPf,@function
_Z30__device_stub__my_first_kernelILi2EEvPf: # @_Z30__device_stub__my_first_kernelILi2EEvPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelILi2EEvPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__my_first_kernelILi2EEvPf, .Lfunc_end1-_Z30__device_stub__my_first_kernelILi2EEvPf
.cfi_endproc
# -- End function
.section .text._Z30__device_stub__my_first_kernelILi3EEvPf,"axG",@progbits,_Z30__device_stub__my_first_kernelILi3EEvPf,comdat
.weak _Z30__device_stub__my_first_kernelILi3EEvPf # -- Begin function _Z30__device_stub__my_first_kernelILi3EEvPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelILi3EEvPf,@function
_Z30__device_stub__my_first_kernelILi3EEvPf: # @_Z30__device_stub__my_first_kernelILi3EEvPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelILi3EEvPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z30__device_stub__my_first_kernelILi3EEvPf, .Lfunc_end2-_Z30__device_stub__my_first_kernelILi3EEvPf
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelILi2EEvPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelILi3EEvPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelILi2EEvPf,@object # @_Z15my_first_kernelILi2EEvPf
.section .rodata._Z15my_first_kernelILi2EEvPf,"aG",@progbits,_Z15my_first_kernelILi2EEvPf,comdat
.weak _Z15my_first_kernelILi2EEvPf
.p2align 3, 0x0
_Z15my_first_kernelILi2EEvPf:
.quad _Z30__device_stub__my_first_kernelILi2EEvPf
.size _Z15my_first_kernelILi2EEvPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " n, x = %d %g \n"
.size .L.str, 20
.type _Z15my_first_kernelILi3EEvPf,@object # @_Z15my_first_kernelILi3EEvPf
.section .rodata._Z15my_first_kernelILi3EEvPf,"aG",@progbits,_Z15my_first_kernelILi3EEvPf,comdat
.weak _Z15my_first_kernelILi3EEvPf
.p2align 3, 0x0
_Z15my_first_kernelILi3EEvPf:
.quad _Z30__device_stub__my_first_kernelILi3EEvPf
.size _Z15my_first_kernelILi3EEvPf, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " n, i = %d %g \n"
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelILi2EEvPf"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15my_first_kernelILi3EEvPf"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelILi2EEvPf
.addrsig_sym _Z30__device_stub__my_first_kernelILi3EEvPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelILi2EEvPf
.addrsig_sym _Z15my_first_kernelILi3EEvPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#define uint uint32_t
#define WST 8
#define WSU 8
#define WSV 8
#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)
#define WS_MASK (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)
#include <stdint.h>
#define uint uint32_t
__device__ uint Rng4(uint4* state){
uint b;
b = ((((*state).x << 6)^(*state).x) >> 13);
(*state).x = ((((*state).x & 4294967294) << 18) ^b);
b = ((((*state).y << 2)^(*state).y) >> 27);
(*state).y = ((((*state).y & 4294967288) << 2) ^b);
b = ((((*state).z << 13)^(*state).z) >> 21);
(*state).z = ((((*state).z & 4294967280) << 7) ^b);
b = ((((*state).w << 3)^(*state).w) >> 12);
(*state).w = ((((*state).w & 4294967168) << 13)^b);
return ((*state).x^(*state).y^(*state).z^(*state).w);
}
__device__ int TUVToIndex(int t, int u, int v){
int index=0;
index += (t%3)<<9;
index += ((u%3)*3)<<9;
index += ((v%3)*9)<<9;
index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
return index;
}
__device__ int AddUnitToIndex(int unit, int index, int& OOB){
int dw = (unit>>3)&0x1;
int dt = ((unit>>0)&0x1)-dw;
int du = ((unit>>1)&0x1)-dw;
int dv = ((unit>>2)&0x1)-dw;
int tr=(index>>9)%3;
int ur=((index>>9)/3)%3;
int vr=((index>>9)/9);
tr += dt;
ur += du;
vr += dv;
// And now for a new bag of tricks! The idea is to find out whether it is out of bounds after
// adding a combination of +/- t,u,v. We don't check for overflow, since that is actually useful for
// the subtraction itself (without the out-of-bounds). We know that we either go
// from 111 -> 000 or 111 -> 000 in case of out-of bounds.
int mask = (tr+1)/4*(0x001); //+t
mask += (3-tr)/4*(0x007); //-t
mask += (ur+1)/4*(0x008); //+u
mask += (3-ur)/4*(0x038); //-u
mask += (vr+1)/4*(0x040); //+v
mask += (3-vr)/4*(0x1c0); //-v
int newIndex = ((index&WS_MASK)+mask)&WS_MASK;
int oldIndex = index&WS_MASK;
int a = oldIndex|(oldIndex>>1)|(oldIndex>>2);
int b = newIndex|(newIndex>>1)|(newIndex>>2);
int c = oldIndex&(oldIndex>>1)&(oldIndex>>2);
int d = newIndex&(newIndex>>1)&(newIndex>>2);
OOB= (((~a)&d)|((~b)&c))&0x49;
newIndex += (tr+ur*3+vr*9)*WS;
return newIndex;
}
__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
int valid;
if((a|b) != 0xf && (a&b))
return 0;
c = (((a|b)==0xf)?(a&b):(a|b));
valid = (c==0x3||c==0xc)?0:1;
return valid;
}
__device__ uint GPUAddUnitVectors(uint a, uint b){
return (((a|b)==0xf)?(a&b):(a|b));
}
__device__ void TransForw(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
if(!latSiteComplete) return;
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
int newIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSl=newSiteComp&0x40;
if(sl+newSl==0) return;
uint rand = Rng4(rngState);
int newBond1 = (trans[next/4]>>(4*(2*next%4)+(next&0x1)))&0xf;
int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
int temp = newBond1;
newBond1 = (rand&0x2)?newBond1:newBond2;
newBond2 = (rand&0x2)?newBond2:temp;
int destIndex = AddUnitToIndex(index,newBond1,OOB);
if(OOB) return;
int destSiteComp = lattice[destIndex];
if(destSiteComp) return;
int moveFirst;
if(sl+newSl==0x80){
moveFirst = (rand&0x4)>>2;
}
else if(sl)
moveFirst = 1;
else
moveFirst = 0;
destSiteComp = newBond2;
if(moveFirst){
latSiteComplete = newBond1|((label>>1)&0x10);
destSiteComp |= label&0x10;
}
else{
latSiteComplete = newBond1|label|sl;
destSiteComp |= (newSiteComp&0x20)>>1;
newSiteComp = newSiteComp&0x5f;
}
lattice[index] = latSiteComplete;
lattice[destIndex] = destSiteComp;
if(!moveFirst)
lattice[newIndex] = newSiteComp;
}
__device__ void TransBack(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int srcIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int srcSiteComp = lattice[srcIndex];
int srcNext = srcSiteComp&0xf;
int srcLabel= srcSiteComp&0x30;
int srcSl = srcSiteComp&0x40;
int newNext;
if(srcSl) return;
if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
int newIndex = AddUnitToIndex(newNext, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSiteSl = newSiteComp&0x40;
if(sl+newSiteSl == 0x80) return;
uint rand = Rng4(rngState);
int moveFirst;
if(sl+newSiteSl == 0x0){
moveFirst = rand&0x1;
}
else if(sl == 0x40)
moveFirst = 0;
else
moveFirst = 1;
if(moveFirst){
latSiteComplete = newNext|(label<<1)|0x40;
}
else{
latSiteComplete = newNext|label|sl;
newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
}
lattice[srcIndex]=0;
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__device__ void DiffuseSL(char* lattice, int index){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int newIndex = AddUnitToIndex(next, index, OOB);
int newSiteComp = lattice[newIndex];
int newSiteLabel = newSiteComp&0x30;
int newSiteSl = newSiteComp&0x40;
if(OOB) return;
if(newSiteSl + sl != 0x40) return;
if(sl){
newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
latSiteComplete = next|((label>>1)&0x10);
}
else{
latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
newSiteComp = newSiteComp&0x1f;
}
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__global__ void polmove(int nStep, uint4* seeds, char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
__shared__ char lattice[BLOCK_SIZE];
uint trans[4];
int lid = threadIdx.x;
int wid = blockIdx.x;
int gid = wid * blockDim.x + lid;
uint4 rngl;
uint4 rngp;
uint site;
int dt = dtuv%WLT;
int du = (dtuv/WLT)%(WLU);
int dv = dtuv/(WLT*WLU);
int p=0;
int pSwitchNext=dt*du*dv;
int dtBlock=dt;
int duBlock=du;
int dvBlock=dv;
int memOffSet=0;
for(int src=wid*BLOCK_SIZE+lid*4; src<(wid+1)*BLOCK_SIZE; src += 4*WS){
for(int i=0; i<4 && i+src<4*WS; i++){
while(i+src>=pSwitchNext){
memOffSet += pSwitchNext;
dtBlock = (p&0x1)?(WLT-dt):dt;
duBlock = (p&0x2)?(WLU-du):du;
dvBlock = (p&0x4)?(WLV-dv):dv;
pSwitchNext += dtBlock*duBlock*dvBlock;
p++;
}
int offSet = src+i-memOffSet;
int t = ((p&0x1)?dt:0) + (offSet%dtBlock);
int u = ((p&0x2)?du:0) + ((offSet/dtBlock)%duBlock);
int v = ((p&0x4)?dv:0) + (offSet/(dtBlock*duBlock));
int index = TUVToIndex(t,u,v);
lattice[index]=srcLattice[src+i];
}
}
for(int i=0; i<4; i++) trans[i] = gTrans[i];
int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
rngp = seeds[gid*2];
rngl = seeds[gid*2+1];
__syncthreads();
for(int i=0; i<nStep; i++){
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransForw(lattice, site, trans, &rngp); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransBack(lattice, site, trans, &rngp); __syncthreads();
}
dt = dtuv_next%WLT;
du = (dtuv_next/WLT)%(WLU);
dv = dtuv_next/(WLT*WLU);
memOffSet=0;
for(int p=0; p<8; p++){
int dtBlock = (p^0x1)?(WLT-dt):dt;
int duBlock = (p^0x2)?(WLU-du):du;
int dvBlock = (p^0x4)?(WLV-dv):dv;
int dstWid = ((wid%NWT)+NWT-(((p>>0)&0x1)^0x1))%NWT;
dstWid += (((wid%NWU)+NWU-(((p>>1)&0x1)^0x1))%NWU)*NWT;
dstWid += (((wid%NWU)+NWU-(((p>>2)&0x1)^0x1))%NWU)*NWT*NWU;
for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
int t = i%dtBlock;
int u = (i/dtBlock)%duBlock;
int v = (i/(dtBlock*duBlock));
int dst = dstWid*BLOCK_SIZE+memOffSet+i;
int index = TUVToIndex(t, u, v);
dstLattice[dst] = lattice[index];
}
memOffSet += dtBlock*duBlock*dvBlock;
}
__syncthreads();
} | .file "tmpxft_00059b24_00000000-6_ringpol2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4Rng4P5uint4
.type _Z4Rng4P5uint4, @function
_Z4Rng4P5uint4:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4Rng4P5uint4, .-_Z4Rng4P5uint4
.globl _Z10TUVToIndexiii
.type _Z10TUVToIndexiii, @function
_Z10TUVToIndexiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z10TUVToIndexiii, .-_Z10TUVToIndexiii
.globl _Z14AddUnitToIndexiiRi
.type _Z14AddUnitToIndexiiRi, @function
_Z14AddUnitToIndexiiRi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14AddUnitToIndexiiRi, .-_Z14AddUnitToIndexiiRi
.globl _Z25GPUValidateAddUnitVectorsiiRi
.type _Z25GPUValidateAddUnitVectorsiiRi, @function
_Z25GPUValidateAddUnitVectorsiiRi:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z25GPUValidateAddUnitVectorsiiRi, .-_Z25GPUValidateAddUnitVectorsiiRi
.globl _Z17GPUAddUnitVectorsjj
.type _Z17GPUAddUnitVectorsjj, @function
_Z17GPUAddUnitVectorsjj:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z17GPUAddUnitVectorsjj, .-_Z17GPUAddUnitVectorsjj
.globl _Z9TransForwPciPjP5uint4
.type _Z9TransForwPciPjP5uint4, @function
_Z9TransForwPciPjP5uint4:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z9TransForwPciPjP5uint4, .-_Z9TransForwPciPjP5uint4
.globl _Z9TransBackPciPjP5uint4
.type _Z9TransBackPciPjP5uint4, @function
_Z9TransBackPciPjP5uint4:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z9TransBackPciPjP5uint4, .-_Z9TransBackPciPjP5uint4
.globl _Z9DiffuseSLPci
.type _Z9DiffuseSLPci, @function
_Z9DiffuseSLPci:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z9DiffuseSLPci, .-_Z9DiffuseSLPci
.globl _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
.type _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, @function
_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj:
.LFB2059:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 40(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, .-_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
.globl _Z7polmoveiP5uint4PcS1_Pjiijjj
.type _Z7polmoveiP5uint4PcS1_Pjiijjj, @function
_Z7polmoveiP5uint4PcS1_Pjiijjj:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7polmoveiP5uint4PcS1_Pjiijjj, .-_Z7polmoveiP5uint4PcS1_Pjiijjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7polmoveiP5uint4PcS1_Pjiijjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#define uint uint32_t
#define WST 8
#define WSU 8
#define WSV 8
#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)
#define WS_MASK (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)
#include <stdint.h>
#define uint uint32_t
__device__ uint Rng4(uint4* state){
uint b;
b = ((((*state).x << 6)^(*state).x) >> 13);
(*state).x = ((((*state).x & 4294967294) << 18) ^b);
b = ((((*state).y << 2)^(*state).y) >> 27);
(*state).y = ((((*state).y & 4294967288) << 2) ^b);
b = ((((*state).z << 13)^(*state).z) >> 21);
(*state).z = ((((*state).z & 4294967280) << 7) ^b);
b = ((((*state).w << 3)^(*state).w) >> 12);
(*state).w = ((((*state).w & 4294967168) << 13)^b);
return ((*state).x^(*state).y^(*state).z^(*state).w);
}
__device__ int TUVToIndex(int t, int u, int v){
int index=0;
index += (t%3)<<9;
index += ((u%3)*3)<<9;
index += ((v%3)*9)<<9;
index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
return index;
}
__device__ int AddUnitToIndex(int unit, int index, int& OOB){
int dw = (unit>>3)&0x1;
int dt = ((unit>>0)&0x1)-dw;
int du = ((unit>>1)&0x1)-dw;
int dv = ((unit>>2)&0x1)-dw;
int tr=(index>>9)%3;
int ur=((index>>9)/3)%3;
int vr=((index>>9)/9);
tr += dt;
ur += du;
vr += dv;
// And now for a new bag of tricks! The idea is to find out whether it is out of bounds after
// adding a combination of +/- t,u,v. We don't check for overflow, since that is actually useful for
// the subtraction itself (without the out-of-bounds). We know that we either go
// from 111 -> 000 or 111 -> 000 in case of out-of bounds.
int mask = (tr+1)/4*(0x001); //+t
mask += (3-tr)/4*(0x007); //-t
mask += (ur+1)/4*(0x008); //+u
mask += (3-ur)/4*(0x038); //-u
mask += (vr+1)/4*(0x040); //+v
mask += (3-vr)/4*(0x1c0); //-v
int newIndex = ((index&WS_MASK)+mask)&WS_MASK;
int oldIndex = index&WS_MASK;
int a = oldIndex|(oldIndex>>1)|(oldIndex>>2);
int b = newIndex|(newIndex>>1)|(newIndex>>2);
int c = oldIndex&(oldIndex>>1)&(oldIndex>>2);
int d = newIndex&(newIndex>>1)&(newIndex>>2);
OOB= (((~a)&d)|((~b)&c))&0x49;
newIndex += (tr+ur*3+vr*9)*WS;
return newIndex;
}
__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
int valid;
if((a|b) != 0xf && (a&b))
return 0;
c = (((a|b)==0xf)?(a&b):(a|b));
valid = (c==0x3||c==0xc)?0:1;
return valid;
}
__device__ uint GPUAddUnitVectors(uint a, uint b){
return (((a|b)==0xf)?(a&b):(a|b));
}
__device__ void TransForw(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
if(!latSiteComplete) return;
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
int newIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSl=newSiteComp&0x40;
if(sl+newSl==0) return;
uint rand = Rng4(rngState);
int newBond1 = (trans[next/4]>>(4*(2*next%4)+(next&0x1)))&0xf;
int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
int temp = newBond1;
newBond1 = (rand&0x2)?newBond1:newBond2;
newBond2 = (rand&0x2)?newBond2:temp;
int destIndex = AddUnitToIndex(index,newBond1,OOB);
if(OOB) return;
int destSiteComp = lattice[destIndex];
if(destSiteComp) return;
int moveFirst;
if(sl+newSl==0x80){
moveFirst = (rand&0x4)>>2;
}
else if(sl)
moveFirst = 1;
else
moveFirst = 0;
destSiteComp = newBond2;
if(moveFirst){
latSiteComplete = newBond1|((label>>1)&0x10);
destSiteComp |= label&0x10;
}
else{
latSiteComplete = newBond1|label|sl;
destSiteComp |= (newSiteComp&0x20)>>1;
newSiteComp = newSiteComp&0x5f;
}
lattice[index] = latSiteComplete;
lattice[destIndex] = destSiteComp;
if(!moveFirst)
lattice[newIndex] = newSiteComp;
}
__device__ void TransBack(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int srcIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int srcSiteComp = lattice[srcIndex];
int srcNext = srcSiteComp&0xf;
int srcLabel= srcSiteComp&0x30;
int srcSl = srcSiteComp&0x40;
int newNext;
if(srcSl) return;
if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
int newIndex = AddUnitToIndex(newNext, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSiteSl = newSiteComp&0x40;
if(sl+newSiteSl == 0x80) return;
uint rand = Rng4(rngState);
int moveFirst;
if(sl+newSiteSl == 0x0){
moveFirst = rand&0x1;
}
else if(sl == 0x40)
moveFirst = 0;
else
moveFirst = 1;
if(moveFirst){
latSiteComplete = newNext|(label<<1)|0x40;
}
else{
latSiteComplete = newNext|label|sl;
newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
}
lattice[srcIndex]=0;
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__device__ void DiffuseSL(char* lattice, int index){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int newIndex = AddUnitToIndex(next, index, OOB);
int newSiteComp = lattice[newIndex];
int newSiteLabel = newSiteComp&0x30;
int newSiteSl = newSiteComp&0x40;
if(OOB) return;
if(newSiteSl + sl != 0x40) return;
if(sl){
newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
latSiteComplete = next|((label>>1)&0x10);
}
else{
latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
newSiteComp = newSiteComp&0x1f;
}
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__global__ void polmove(int nStep, uint4* seeds, char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
__shared__ char lattice[BLOCK_SIZE];
uint trans[4];
int lid = threadIdx.x;
int wid = blockIdx.x;
int gid = wid * blockDim.x + lid;
uint4 rngl;
uint4 rngp;
uint site;
int dt = dtuv%WLT;
int du = (dtuv/WLT)%(WLU);
int dv = dtuv/(WLT*WLU);
int p=0;
int pSwitchNext=dt*du*dv;
int dtBlock=dt;
int duBlock=du;
int dvBlock=dv;
int memOffSet=0;
for(int src=wid*BLOCK_SIZE+lid*4; src<(wid+1)*BLOCK_SIZE; src += 4*WS){
for(int i=0; i<4 && i+src<4*WS; i++){
while(i+src>=pSwitchNext){
memOffSet += pSwitchNext;
dtBlock = (p&0x1)?(WLT-dt):dt;
duBlock = (p&0x2)?(WLU-du):du;
dvBlock = (p&0x4)?(WLV-dv):dv;
pSwitchNext += dtBlock*duBlock*dvBlock;
p++;
}
int offSet = src+i-memOffSet;
int t = ((p&0x1)?dt:0) + (offSet%dtBlock);
int u = ((p&0x2)?du:0) + ((offSet/dtBlock)%duBlock);
int v = ((p&0x4)?dv:0) + (offSet/(dtBlock*duBlock));
int index = TUVToIndex(t,u,v);
lattice[index]=srcLattice[src+i];
}
}
for(int i=0; i<4; i++) trans[i] = gTrans[i];
int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
rngp = seeds[gid*2];
rngl = seeds[gid*2+1];
__syncthreads();
for(int i=0; i<nStep; i++){
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransForw(lattice, site, trans, &rngp); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransBack(lattice, site, trans, &rngp); __syncthreads();
}
dt = dtuv_next%WLT;
du = (dtuv_next/WLT)%(WLU);
dv = dtuv_next/(WLT*WLU);
memOffSet=0;
for(int p=0; p<8; p++){
int dtBlock = (p^0x1)?(WLT-dt):dt;
int duBlock = (p^0x2)?(WLU-du):du;
int dvBlock = (p^0x4)?(WLV-dv):dv;
int dstWid = ((wid%NWT)+NWT-(((p>>0)&0x1)^0x1))%NWT;
dstWid += (((wid%NWU)+NWU-(((p>>1)&0x1)^0x1))%NWU)*NWT;
dstWid += (((wid%NWU)+NWU-(((p>>2)&0x1)^0x1))%NWU)*NWT*NWU;
for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
int t = i%dtBlock;
int u = (i/dtBlock)%duBlock;
int v = (i/(dtBlock*duBlock));
int dst = dstWid*BLOCK_SIZE+memOffSet+i;
int index = TUVToIndex(t, u, v);
dstLattice[dst] = lattice[index];
}
memOffSet += dtBlock*duBlock*dvBlock;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#define uint uint32_t
#define WST 8
#define WSU 8
#define WSV 8
#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)
#define WS_MASK (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)
#include <stdint.h>
#define uint uint32_t
__device__ uint Rng4(uint4* state){
uint b;
b = ((((*state).x << 6)^(*state).x) >> 13);
(*state).x = ((((*state).x & 4294967294) << 18) ^b);
b = ((((*state).y << 2)^(*state).y) >> 27);
(*state).y = ((((*state).y & 4294967288) << 2) ^b);
b = ((((*state).z << 13)^(*state).z) >> 21);
(*state).z = ((((*state).z & 4294967280) << 7) ^b);
b = ((((*state).w << 3)^(*state).w) >> 12);
(*state).w = ((((*state).w & 4294967168) << 13)^b);
return ((*state).x^(*state).y^(*state).z^(*state).w);
}
__device__ int TUVToIndex(int t, int u, int v){
int index=0;
index += (t%3)<<9;
index += ((u%3)*3)<<9;
index += ((v%3)*9)<<9;
index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
return index;
}
__device__ int AddUnitToIndex(int unit, int index, int& OOB){
int dw = (unit>>3)&0x1;
int dt = ((unit>>0)&0x1)-dw;
int du = ((unit>>1)&0x1)-dw;
int dv = ((unit>>2)&0x1)-dw;
int tr=(index>>9)%3;
int ur=((index>>9)/3)%3;
int vr=((index>>9)/9);
tr += dt;
ur += du;
vr += dv;
// And now for a new bag of tricks! The idea is to find out whether it is out of bounds after
// adding a combination of +/- t,u,v. We don't check for overflow, since that is actually useful for
// the subtraction itself (without the out-of-bounds). We know that we either go
// from 111 -> 000 or 111 -> 000 in case of out-of bounds.
int mask = (tr+1)/4*(0x001); //+t
mask += (3-tr)/4*(0x007); //-t
mask += (ur+1)/4*(0x008); //+u
mask += (3-ur)/4*(0x038); //-u
mask += (vr+1)/4*(0x040); //+v
mask += (3-vr)/4*(0x1c0); //-v
int newIndex = ((index&WS_MASK)+mask)&WS_MASK;
int oldIndex = index&WS_MASK;
int a = oldIndex|(oldIndex>>1)|(oldIndex>>2);
int b = newIndex|(newIndex>>1)|(newIndex>>2);
int c = oldIndex&(oldIndex>>1)&(oldIndex>>2);
int d = newIndex&(newIndex>>1)&(newIndex>>2);
OOB= (((~a)&d)|((~b)&c))&0x49;
newIndex += (tr+ur*3+vr*9)*WS;
return newIndex;
}
__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
int valid;
if((a|b) != 0xf && (a&b))
return 0;
c = (((a|b)==0xf)?(a&b):(a|b));
valid = (c==0x3||c==0xc)?0:1;
return valid;
}
__device__ uint GPUAddUnitVectors(uint a, uint b){
return (((a|b)==0xf)?(a&b):(a|b));
}
__device__ void TransForw(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
if(!latSiteComplete) return;
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
int newIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSl=newSiteComp&0x40;
if(sl+newSl==0) return;
uint rand = Rng4(rngState);
int newBond1 = (trans[next/4]>>(4*(2*next%4)+(next&0x1)))&0xf;
int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
int temp = newBond1;
newBond1 = (rand&0x2)?newBond1:newBond2;
newBond2 = (rand&0x2)?newBond2:temp;
int destIndex = AddUnitToIndex(index,newBond1,OOB);
if(OOB) return;
int destSiteComp = lattice[destIndex];
if(destSiteComp) return;
int moveFirst;
if(sl+newSl==0x80){
moveFirst = (rand&0x4)>>2;
}
else if(sl)
moveFirst = 1;
else
moveFirst = 0;
destSiteComp = newBond2;
if(moveFirst){
latSiteComplete = newBond1|((label>>1)&0x10);
destSiteComp |= label&0x10;
}
else{
latSiteComplete = newBond1|label|sl;
destSiteComp |= (newSiteComp&0x20)>>1;
newSiteComp = newSiteComp&0x5f;
}
lattice[index] = latSiteComplete;
lattice[destIndex] = destSiteComp;
if(!moveFirst)
lattice[newIndex] = newSiteComp;
}
__device__ void TransBack(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int srcIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int srcSiteComp = lattice[srcIndex];
int srcNext = srcSiteComp&0xf;
int srcLabel= srcSiteComp&0x30;
int srcSl = srcSiteComp&0x40;
int newNext;
if(srcSl) return;
if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
int newIndex = AddUnitToIndex(newNext, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSiteSl = newSiteComp&0x40;
if(sl+newSiteSl == 0x80) return;
uint rand = Rng4(rngState);
int moveFirst;
if(sl+newSiteSl == 0x0){
moveFirst = rand&0x1;
}
else if(sl == 0x40)
moveFirst = 0;
else
moveFirst = 1;
if(moveFirst){
latSiteComplete = newNext|(label<<1)|0x40;
}
else{
latSiteComplete = newNext|label|sl;
newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
}
lattice[srcIndex]=0;
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__device__ void DiffuseSL(char* lattice, int index){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int newIndex = AddUnitToIndex(next, index, OOB);
int newSiteComp = lattice[newIndex];
int newSiteLabel = newSiteComp&0x30;
int newSiteSl = newSiteComp&0x40;
if(OOB) return;
if(newSiteSl + sl != 0x40) return;
if(sl){
newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
latSiteComplete = next|((label>>1)&0x10);
}
else{
latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
newSiteComp = newSiteComp&0x1f;
}
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__global__ void polmove(int nStep, uint4* seeds, char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
__shared__ char lattice[BLOCK_SIZE];
uint trans[4];
int lid = threadIdx.x;
int wid = blockIdx.x;
int gid = wid * blockDim.x + lid;
uint4 rngl;
uint4 rngp;
uint site;
int dt = dtuv%WLT;
int du = (dtuv/WLT)%(WLU);
int dv = dtuv/(WLT*WLU);
int p=0;
int pSwitchNext=dt*du*dv;
int dtBlock=dt;
int duBlock=du;
int dvBlock=dv;
int memOffSet=0;
for(int src=wid*BLOCK_SIZE+lid*4; src<(wid+1)*BLOCK_SIZE; src += 4*WS){
for(int i=0; i<4 && i+src<4*WS; i++){
while(i+src>=pSwitchNext){
memOffSet += pSwitchNext;
dtBlock = (p&0x1)?(WLT-dt):dt;
duBlock = (p&0x2)?(WLU-du):du;
dvBlock = (p&0x4)?(WLV-dv):dv;
pSwitchNext += dtBlock*duBlock*dvBlock;
p++;
}
int offSet = src+i-memOffSet;
int t = ((p&0x1)?dt:0) + (offSet%dtBlock);
int u = ((p&0x2)?du:0) + ((offSet/dtBlock)%duBlock);
int v = ((p&0x4)?dv:0) + (offSet/(dtBlock*duBlock));
int index = TUVToIndex(t,u,v);
lattice[index]=srcLattice[src+i];
}
}
for(int i=0; i<4; i++) trans[i] = gTrans[i];
int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
rngp = seeds[gid*2];
rngl = seeds[gid*2+1];
__syncthreads();
for(int i=0; i<nStep; i++){
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransForw(lattice, site, trans, &rngp); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransBack(lattice, site, trans, &rngp); __syncthreads();
}
dt = dtuv_next%WLT;
du = (dtuv_next/WLT)%(WLU);
dv = dtuv_next/(WLT*WLU);
memOffSet=0;
for(int p=0; p<8; p++){
int dtBlock = (p^0x1)?(WLT-dt):dt;
int duBlock = (p^0x2)?(WLU-du):du;
int dvBlock = (p^0x4)?(WLV-dv):dv;
int dstWid = ((wid%NWT)+NWT-(((p>>0)&0x1)^0x1))%NWT;
dstWid += (((wid%NWU)+NWU-(((p>>1)&0x1)^0x1))%NWU)*NWT;
dstWid += (((wid%NWU)+NWU-(((p>>2)&0x1)^0x1))%NWU)*NWT*NWU;
for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
int t = i%dtBlock;
int u = (i/dtBlock)%duBlock;
int v = (i/(dtBlock*duBlock));
int dst = dstWid*BLOCK_SIZE+memOffSet+i;
int index = TUVToIndex(t, u, v);
dstLattice[dst] = lattice[index];
}
memOffSet += dtBlock*duBlock*dvBlock;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#define uint uint32_t
#define WST 8
#define WSU 8
#define WSV 8
#define WS (WST*WSU*WSV)
#define CELL_LENGTH 3
#define CELL_SIZE (CELL_LENGTH*CELL_LENGTH*CELL_LENGTH)
#define BLOCK_SIZE (WS*CELL_SIZE)
#define WLT (WST*CELL_LENGTH)
#define WLU (WSU*CELL_LENGTH)
#define WLV (WSV*CELL_LENGTH)
#define WS_MASK (WS-1)
#define TID_MASK (WST-1)
#define UID_MASK (WSU-1)
#define VID_MASK (WSV-1)
#include <stdint.h>
#define uint uint32_t
__device__ uint Rng4(uint4* state){
uint b;
b = ((((*state).x << 6)^(*state).x) >> 13);
(*state).x = ((((*state).x & 4294967294) << 18) ^b);
b = ((((*state).y << 2)^(*state).y) >> 27);
(*state).y = ((((*state).y & 4294967288) << 2) ^b);
b = ((((*state).z << 13)^(*state).z) >> 21);
(*state).z = ((((*state).z & 4294967280) << 7) ^b);
b = ((((*state).w << 3)^(*state).w) >> 12);
(*state).w = ((((*state).w & 4294967168) << 13)^b);
return ((*state).x^(*state).y^(*state).z^(*state).w);
}
__device__ int TUVToIndex(int t, int u, int v){
int index=0;
index += (t%3)<<9;
index += ((u%3)*3)<<9;
index += ((v%3)*9)<<9;
index += (t/3)+(u/3)*WST+(v/3)*WST*WSU;
return index;
}
__device__ int AddUnitToIndex(int unit, int index, int& OOB){
int dw = (unit>>3)&0x1;
int dt = ((unit>>0)&0x1)-dw;
int du = ((unit>>1)&0x1)-dw;
int dv = ((unit>>2)&0x1)-dw;
int tr=(index>>9)%3;
int ur=((index>>9)/3)%3;
int vr=((index>>9)/9);
tr += dt;
ur += du;
vr += dv;
// And now for a new bag of tricks! The idea is to find out whether it is out of bounds after
// adding a combination of +/- t,u,v. We don't check for overflow, since that is actually useful for
// the subtraction itself (without the out-of-bounds). We know that we either go
// from 111 -> 000 or 111 -> 000 in case of out-of bounds.
int mask = (tr+1)/4*(0x001); //+t
mask += (3-tr)/4*(0x007); //-t
mask += (ur+1)/4*(0x008); //+u
mask += (3-ur)/4*(0x038); //-u
mask += (vr+1)/4*(0x040); //+v
mask += (3-vr)/4*(0x1c0); //-v
int newIndex = ((index&WS_MASK)+mask)&WS_MASK;
int oldIndex = index&WS_MASK;
int a = oldIndex|(oldIndex>>1)|(oldIndex>>2);
int b = newIndex|(newIndex>>1)|(newIndex>>2);
int c = oldIndex&(oldIndex>>1)&(oldIndex>>2);
int d = newIndex&(newIndex>>1)&(newIndex>>2);
OOB= (((~a)&d)|((~b)&c))&0x49;
newIndex += (tr+ur*3+vr*9)*WS;
return newIndex;
}
__device__ uint GPUValidateAddUnitVectors(int a, int b, int& c){
int valid;
if((a|b) != 0xf && (a&b))
return 0;
c = (((a|b)==0xf)?(a&b):(a|b));
valid = (c==0x3||c==0xc)?0:1;
return valid;
}
__device__ uint GPUAddUnitVectors(uint a, uint b){
return (((a|b)==0xf)?(a&b):(a|b));
}
__device__ void TransForw(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
if(!latSiteComplete) return;
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
int newIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSl=newSiteComp&0x40;
if(sl+newSl==0) return;
uint rand = Rng4(rngState);
int newBond1 = (trans[next/4]>>(4*(2*next%4)+(next&0x1)))&0xf;
int newBond2 = GPUAddUnitVectors((~newBond1)&0xf, next);
int temp = newBond1;
newBond1 = (rand&0x2)?newBond1:newBond2;
newBond2 = (rand&0x2)?newBond2:temp;
int destIndex = AddUnitToIndex(index,newBond1,OOB);
if(OOB) return;
int destSiteComp = lattice[destIndex];
if(destSiteComp) return;
int moveFirst;
if(sl+newSl==0x80){
moveFirst = (rand&0x4)>>2;
}
else if(sl)
moveFirst = 1;
else
moveFirst = 0;
destSiteComp = newBond2;
if(moveFirst){
latSiteComplete = newBond1|((label>>1)&0x10);
destSiteComp |= label&0x10;
}
else{
latSiteComplete = newBond1|label|sl;
destSiteComp |= (newSiteComp&0x20)>>1;
newSiteComp = newSiteComp&0x5f;
}
lattice[index] = latSiteComplete;
lattice[destIndex] = destSiteComp;
if(!moveFirst)
lattice[newIndex] = newSiteComp;
}
__device__ void TransBack(char* lattice, int index, uint* trans, uint4* rngState){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int srcIndex = AddUnitToIndex(next, index, OOB);
if(OOB) return;
int srcSiteComp = lattice[srcIndex];
int srcNext = srcSiteComp&0xf;
int srcLabel= srcSiteComp&0x30;
int srcSl = srcSiteComp&0x40;
int newNext;
if(srcSl) return;
if(!GPUValidateAddUnitVectors(next, srcNext, newNext)) return;
int newIndex = AddUnitToIndex(newNext, index, OOB);
if(OOB) return;
int newSiteComp = lattice[newIndex];
int newSiteSl = newSiteComp&0x40;
if(sl+newSiteSl == 0x80) return;
uint rand = Rng4(rngState);
int moveFirst;
if(sl+newSiteSl == 0x0){
moveFirst = rand&0x1;
}
else if(sl == 0x40)
moveFirst = 0;
else
moveFirst = 1;
if(moveFirst){
latSiteComplete = newNext|(label<<1)|0x40;
}
else{
latSiteComplete = newNext|label|sl;
newSiteComp = (newSiteComp&0x3f)|(srcLabel<<1)|0x40;
}
lattice[srcIndex]=0;
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__device__ void DiffuseSL(char* lattice, int index){
int OOB;
int latSiteComplete = lattice[index];
int next = latSiteComplete&0xf;
int label = latSiteComplete&0x30;
int sl = latSiteComplete&0x40;
if(!latSiteComplete) return;
int newIndex = AddUnitToIndex(next, index, OOB);
int newSiteComp = lattice[newIndex];
int newSiteLabel = newSiteComp&0x30;
int newSiteSl = newSiteComp&0x40;
if(OOB) return;
if(newSiteSl + sl != 0x40) return;
if(sl){
newSiteComp = newSiteComp | ((label&0x10)<<1) | 0x40;
latSiteComplete = next|((label>>1)&0x10);
}
else{
latSiteComplete = next|(label<<1)|((newSiteLabel>>1)&0x10)|0x40;
newSiteComp = newSiteComp&0x1f;
}
lattice[index] = latSiteComplete;
lattice[newIndex] = newSiteComp;
}
__global__ void polmove(int nStep, uint4* seeds, char* srcLattice, char* dstLattice, uint* gTrans, int dtuv, int dtuv_next, uint NWT, uint NWU, uint NWV){
__shared__ char lattice[BLOCK_SIZE];
uint trans[4];
int lid = threadIdx.x;
int wid = blockIdx.x;
int gid = wid * blockDim.x + lid;
uint4 rngl;
uint4 rngp;
uint site;
int dt = dtuv%WLT;
int du = (dtuv/WLT)%(WLU);
int dv = dtuv/(WLT*WLU);
int p=0;
int pSwitchNext=dt*du*dv;
int dtBlock=dt;
int duBlock=du;
int dvBlock=dv;
int memOffSet=0;
for(int src=wid*BLOCK_SIZE+lid*4; src<(wid+1)*BLOCK_SIZE; src += 4*WS){
for(int i=0; i<4 && i+src<4*WS; i++){
while(i+src>=pSwitchNext){
memOffSet += pSwitchNext;
dtBlock = (p&0x1)?(WLT-dt):dt;
duBlock = (p&0x2)?(WLU-du):du;
dvBlock = (p&0x4)?(WLV-dv):dv;
pSwitchNext += dtBlock*duBlock*dvBlock;
p++;
}
int offSet = src+i-memOffSet;
int t = ((p&0x1)?dt:0) + (offSet%dtBlock);
int u = ((p&0x2)?du:0) + ((offSet/dtBlock)%duBlock);
int v = ((p&0x4)?dv:0) + (offSet/(dtBlock*duBlock));
int index = TUVToIndex(t,u,v);
lattice[index]=srcLattice[src+i];
}
}
for(int i=0; i<4; i++) trans[i] = gTrans[i];
int indexStart = ((lid&0x1f)<<2)|((lid&0x60)>>5)|(lid&0x180);
rngp = seeds[gid*2];
rngl = seeds[gid*2+1];
__syncthreads();
for(int i=0; i<nStep; i++){
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransForw(lattice, site, trans, &rngp); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
DiffuseSL(lattice, site); __syncthreads();
site = indexStart | ((Rng4(&rngl)%27)<<9);
TransBack(lattice, site, trans, &rngp); __syncthreads();
}
dt = dtuv_next%WLT;
du = (dtuv_next/WLT)%(WLU);
dv = dtuv_next/(WLT*WLU);
memOffSet=0;
for(int p=0; p<8; p++){
int dtBlock = (p^0x1)?(WLT-dt):dt;
int duBlock = (p^0x2)?(WLU-du):du;
int dvBlock = (p^0x4)?(WLV-dv):dv;
int dstWid = ((wid%NWT)+NWT-(((p>>0)&0x1)^0x1))%NWT;
dstWid += (((wid%NWU)+NWU-(((p>>1)&0x1)^0x1))%NWU)*NWT;
dstWid += (((wid%NWU)+NWU-(((p>>2)&0x1)^0x1))%NWU)*NWT*NWU;
for(int i=lid; i<dtBlock*duBlock*dvBlock; i+=WS){
int t = i%dtBlock;
int u = (i/dtBlock)%duBlock;
int v = (i/(dtBlock*duBlock));
int dst = dstWid*BLOCK_SIZE+memOffSet+i;
int index = TUVToIndex(t, u, v);
dstLattice[dst] = lattice[index];
}
memOffSet += dtBlock*duBlock*dvBlock;
}
__syncthreads();
} | .text
.file "ringpol2.hip"
.globl _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj # -- Begin function _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.p2align 4, 0x90
.type _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@function
_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj: # @_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, .Lfunc_end0-_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@object # @_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.section .rodata,"a",@progbits
.globl _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.p2align 3, 0x0
_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj:
.quad _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.size _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059b24_00000000-6_ringpol2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4Rng4P5uint4
.type _Z4Rng4P5uint4, @function
_Z4Rng4P5uint4:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z4Rng4P5uint4, .-_Z4Rng4P5uint4
.globl _Z10TUVToIndexiii
.type _Z10TUVToIndexiii, @function
_Z10TUVToIndexiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z10TUVToIndexiii, .-_Z10TUVToIndexiii
.globl _Z14AddUnitToIndexiiRi
.type _Z14AddUnitToIndexiiRi, @function
_Z14AddUnitToIndexiiRi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z14AddUnitToIndexiiRi, .-_Z14AddUnitToIndexiiRi
.globl _Z25GPUValidateAddUnitVectorsiiRi
.type _Z25GPUValidateAddUnitVectorsiiRi, @function
_Z25GPUValidateAddUnitVectorsiiRi:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z25GPUValidateAddUnitVectorsiiRi, .-_Z25GPUValidateAddUnitVectorsiiRi
.globl _Z17GPUAddUnitVectorsjj
.type _Z17GPUAddUnitVectorsjj, @function
_Z17GPUAddUnitVectorsjj:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z17GPUAddUnitVectorsjj, .-_Z17GPUAddUnitVectorsjj
.globl _Z9TransForwPciPjP5uint4
.type _Z9TransForwPciPjP5uint4, @function
_Z9TransForwPciPjP5uint4:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z9TransForwPciPjP5uint4, .-_Z9TransForwPciPjP5uint4
.globl _Z9TransBackPciPjP5uint4
.type _Z9TransBackPciPjP5uint4, @function
_Z9TransBackPciPjP5uint4:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z9TransBackPciPjP5uint4, .-_Z9TransBackPciPjP5uint4
.globl _Z9DiffuseSLPci
.type _Z9DiffuseSLPci, @function
_Z9DiffuseSLPci:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z9DiffuseSLPci, .-_Z9DiffuseSLPci
.globl _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
.type _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, @function
_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj:
.LFB2059:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 40(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj, .-_Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
.globl _Z7polmoveiP5uint4PcS1_Pjiijjj
.type _Z7polmoveiP5uint4PcS1_Pjiijjj, @function
_Z7polmoveiP5uint4PcS1_Pjiijjj:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z44__device_stub__Z7polmoveiP5uint4PcS1_PjiijjjiP5uint4PcS1_Pjiijjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z7polmoveiP5uint4PcS1_Pjiijjj, .-_Z7polmoveiP5uint4PcS1_Pjiijjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7polmoveiP5uint4PcS1_Pjiijjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7polmoveiP5uint4PcS1_Pjiijjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ringpol2.hip"
.globl _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj # -- Begin function _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.p2align 4, 0x90
.type _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@function
_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj: # @_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, .Lfunc_end0-_Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj,@object # @_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.section .rodata,"a",@progbits
.globl _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.p2align 3, 0x0
_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj:
.quad _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.size _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7polmoveiP15HIP_vector_typeIjLj4EEPcS2_Pjiijjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | code for sm_80
Function : _Z7addvecsPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x004e0e0000000006 */
/*0090*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7addnumsPdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0050*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*0060*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .file "tmpxft_0015b5b8_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7addnumsPddPdd
.type _Z27__device_stub__Z7addnumsPddPdd, @function
_Z27__device_stub__Z7addnumsPddPdd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addnumsPdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7addnumsPddPdd, .-_Z27__device_stub__Z7addnumsPddPdd
.globl _Z7addnumsPdd
.type _Z7addnumsPdd, @function
_Z7addnumsPdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7addnumsPddPdd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7addnumsPdd, .-_Z7addnumsPdd
.globl _Z28__device_stub__Z7addvecsPdS_PdS_
.type _Z28__device_stub__Z7addvecsPdS_PdS_, @function
_Z28__device_stub__Z7addvecsPdS_PdS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addvecsPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z7addvecsPdS_PdS_, .-_Z28__device_stub__Z7addvecsPdS_PdS_
.globl _Z7addvecsPdS_
.type _Z7addvecsPdS_, @function
_Z7addvecsPdS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7addvecsPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7addvecsPdS_, .-_Z7addvecsPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7addvecsPdS_"
.LC1:
.string "_Z7addnumsPdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addvecsPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addnumsPdd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | #include <hip/hip_runtime.h>
// cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7addnumsPdd
.globl _Z7addnumsPdd
.p2align 8
.type _Z7addnumsPdd,@function
_Z7addnumsPdd:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[2:3]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addnumsPdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7addnumsPdd, .Lfunc_end0-_Z7addnumsPdd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7addvecsPdS_
.globl _Z7addvecsPdS_
.p2align 8
.type _Z7addvecsPdS_,@function
_Z7addvecsPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[2:3]
global_load_b64 v[2:3], v4, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addvecsPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7addvecsPdS_, .Lfunc_end1-_Z7addvecsPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addnumsPdd
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z7addnumsPdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addvecsPdS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7addvecsPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// cuda-kernel: add 2 numbers
__global__ void addnums (double *pi, double c){
*pi += c;
}
// cuda-kernel: add 2 vectors
__global__ void addvecs (double *v1, double *v2){
int idx = threadIdx.x;
v1[idx] += v2[idx];
} | .text
.file "add.hip"
.globl _Z22__device_stub__addnumsPdd # -- Begin function _Z22__device_stub__addnumsPdd
.p2align 4, 0x90
.type _Z22__device_stub__addnumsPdd,@function
_Z22__device_stub__addnumsPdd: # @_Z22__device_stub__addnumsPdd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addnumsPdd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__addnumsPdd, .Lfunc_end0-_Z22__device_stub__addnumsPdd
.cfi_endproc
# -- End function
.globl _Z22__device_stub__addvecsPdS_ # -- Begin function _Z22__device_stub__addvecsPdS_
.p2align 4, 0x90
.type _Z22__device_stub__addvecsPdS_,@function
_Z22__device_stub__addvecsPdS_: # @_Z22__device_stub__addvecsPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addvecsPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__addvecsPdS_, .Lfunc_end1-_Z22__device_stub__addvecsPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addnumsPdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addvecsPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7addnumsPdd,@object # @_Z7addnumsPdd
.section .rodata,"a",@progbits
.globl _Z7addnumsPdd
.p2align 3, 0x0
_Z7addnumsPdd:
.quad _Z22__device_stub__addnumsPdd
.size _Z7addnumsPdd, 8
.type _Z7addvecsPdS_,@object # @_Z7addvecsPdS_
.globl _Z7addvecsPdS_
.p2align 3, 0x0
_Z7addvecsPdS_:
.quad _Z22__device_stub__addvecsPdS_
.size _Z7addvecsPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7addnumsPdd"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7addvecsPdS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__addnumsPdd
.addrsig_sym _Z22__device_stub__addvecsPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7addnumsPdd
.addrsig_sym _Z7addvecsPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7addvecsPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R6, R2, R6 ; /* 0x0000000002067229 */
/* 0x004e0e0000000006 */
/*0090*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7addnumsPdd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*0050*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*0060*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7addnumsPdd
.globl _Z7addnumsPdd
.p2align 8
.type _Z7addnumsPdd,@function
_Z7addnumsPdd:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[2:3]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addnumsPdd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7addnumsPdd, .Lfunc_end0-_Z7addnumsPdd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7addvecsPdS_
.globl _Z7addvecsPdS_
.p2align 8
.type _Z7addvecsPdS_,@function
_Z7addvecsPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 3, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[0:1], v4, s[2:3]
global_load_b64 v[2:3], v4, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v4, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7addvecsPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7addvecsPdS_, .Lfunc_end1-_Z7addvecsPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addnumsPdd
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z7addnumsPdd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7addvecsPdS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z7addvecsPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015b5b8_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7addnumsPddPdd
.type _Z27__device_stub__Z7addnumsPddPdd, @function
_Z27__device_stub__Z7addnumsPddPdd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addnumsPdd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7addnumsPddPdd, .-_Z27__device_stub__Z7addnumsPddPdd
.globl _Z7addnumsPdd
.type _Z7addnumsPdd, @function
_Z7addnumsPdd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7addnumsPddPdd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7addnumsPdd, .-_Z7addnumsPdd
.globl _Z28__device_stub__Z7addvecsPdS_PdS_
.type _Z28__device_stub__Z7addvecsPdS_PdS_, @function
_Z28__device_stub__Z7addvecsPdS_PdS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7addvecsPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z7addvecsPdS_PdS_, .-_Z28__device_stub__Z7addvecsPdS_PdS_
.globl _Z7addvecsPdS_
.type _Z7addvecsPdS_, @function
_Z7addvecsPdS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7addvecsPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7addvecsPdS_, .-_Z7addvecsPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7addvecsPdS_"
.LC1:
.string "_Z7addnumsPdd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addvecsPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7addnumsPdd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z22__device_stub__addnumsPdd # -- Begin function _Z22__device_stub__addnumsPdd
.p2align 4, 0x90
.type _Z22__device_stub__addnumsPdd,@function
_Z22__device_stub__addnumsPdd: # @_Z22__device_stub__addnumsPdd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addnumsPdd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__addnumsPdd, .Lfunc_end0-_Z22__device_stub__addnumsPdd
.cfi_endproc
# -- End function
.globl _Z22__device_stub__addvecsPdS_ # -- Begin function _Z22__device_stub__addvecsPdS_
.p2align 4, 0x90
.type _Z22__device_stub__addvecsPdS_,@function
_Z22__device_stub__addvecsPdS_: # @_Z22__device_stub__addvecsPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7addvecsPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__addvecsPdS_, .Lfunc_end1-_Z22__device_stub__addvecsPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addnumsPdd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7addvecsPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7addnumsPdd,@object # @_Z7addnumsPdd
.section .rodata,"a",@progbits
.globl _Z7addnumsPdd
.p2align 3, 0x0
_Z7addnumsPdd:
.quad _Z22__device_stub__addnumsPdd
.size _Z7addnumsPdd, 8
.type _Z7addvecsPdS_,@object # @_Z7addvecsPdS_
.globl _Z7addvecsPdS_
.p2align 3, 0x0
_Z7addvecsPdS_:
.quad _Z22__device_stub__addvecsPdS_
.size _Z7addvecsPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7addnumsPdd"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7addvecsPdS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__addnumsPdd
.addrsig_sym _Z22__device_stub__addvecsPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7addnumsPdd
.addrsig_sym _Z7addvecsPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
cudaMalloc(&devPtr, mem_size ); // MB
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", cudaGetErrorString(cudaGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
cudaFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
cudaMalloc(&devPtr, mem_size ); // MB
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", cudaGetErrorString(cudaGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
cudaFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} | .file "tmpxft_00187077_00000000-6_malloc_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n"
.align 8
.LC2:
.string "\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\ncurrent free memory is %.1f\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "------------------------------------------------------------------\n"
.align 8
.LC5:
.string "\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n"
.align 8
.LC6:
.string "0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n"
.align 8
.LC7:
.string "%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n"
.section .rodata.str1.1
.LC8:
.string "couldn't allocate %.1f MB "
.LC9:
.string "Err : %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMemGetInfo@PLT
movq 24(%rsp), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rsp)
movq 32(%rsp), %rax
cmpl $2, %ebx
jg .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L7:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L6:
testq %rax, %rax
js .L8
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L9:
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
shrq $2, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm5
movaps %xmm5, %xmm0
movss (%rsp), %xmm6
subss %xmm6, %xmm0
pxor %xmm2, %xmm2
cvtss2sd %xmm0, %xmm2
movsd %xmm2, (%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm6, %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movl $0, %r12d
leaq .LC7(%rip), %r14
jmp .L17
.L8:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L9
.L10:
shrq %r15
pxor %xmm0, %xmm0
cvtsi2ssq %r15, %xmm0
addss %xmm0, %xmm0
jmp .L11
.L12:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
addss %xmm1, %xmm1
jmp .L13
.L14:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L15:
mulss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r15, %xmm3
movsd (%rsp), %xmm2
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
addq %r13, %rbp
testq %rdi, %rdi
je .L21
call cudaFree@PLT
addq %r13, %rbx
shrq $2, %rbx
addl $1, %r12d
.L17:
salq $2, %rbx
leaq (%rbx,%rbp), %r15
salq $20, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMemGetInfo@PLT
testq %r15, %r15
js .L10
pxor %xmm0, %xmm0
cvtsi2ssq %r15, %xmm0
.L11:
mulss .LC0(%rip), %xmm0
pxor %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movq %xmm4, %r15
movq 24(%rsp), %rax
testq %rax, %rax
js .L12
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
.L13:
mulss .LC0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 32(%rsp), %rax
testq %rax, %rax
js .L14
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L15
.L21:
movq %r15, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
cudaMalloc(&devPtr, mem_size ); // MB
cudaMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", cudaGetErrorString(cudaGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
cudaFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
hipMalloc(&devPtr, mem_size ); // MB
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", hipGetErrorString(hipGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
hipFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
hipMalloc(&devPtr, mem_size ); // MB
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", hipGetErrorString(hipGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
hipFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
compile : nvcc malloc_test.cu -o malloc_test
exec : ./malloc_test 512 1
starting 512MB , increase 1MB
if you have multiple GPU, use below
export CUDA_VISIBLE_DEVICES=3;./malloc_test 512 1
MB convert table would be :
GB MB
1 1024
2 2048
3 3072
4 4096
5 5120
6 6144
7 7168
8 8192
9 9216
10 10240
11 11264
12 12288
13 13312
14 14336
15 15360
16 16384
17 17408
18 18432
19 19456
20 20480
21 21504
22 22528
23 23552
24 24576
25 25600
26 26624
27 27648
28 28672
29 29696
30 30720
31 31744
32 32768
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
int main(int argc, char* argv[]) {
int *devPtr= NULL;
size_t mem_size, free, total , start, inc, size ;
float free_f, total_f, used_f, used_start_f, used_now_f;
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_start_f = used_f;
if(argc<3){
printf(" plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n");
printf("\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n");
printf("\ncurrent free memory is %.1f\n", free_f);
return 0;
}
start = atoi(argv[1]) / sizeof(int) ;
inc = atoi(argv[2]) ;
size = start;
printf("------------------------------------------------------------------\n");
printf("\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n");
printf("0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n", total_f,free_f, used_f );
printf("------------------------------------------------------------------\n");
int i = 0;
do {
mem_size = sizeof(int) * size * (1024*1024) + (inc*i) * (1024*1024) ;
hipMalloc(&devPtr, mem_size ); // MB
hipMemGetInfo(&free,&total);
free_f = float(free) / (1024*1024) ;
total_f = float(total) / (1024*1024) ;
used_f = total_f-free_f ;
used_now_f = (float)mem_size/(1024*1024) ;
printf("%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n", i, total_f, free_f, used_start_f, used_now_f);
if(devPtr == NULL) {
printf("couldn't allocate %.1f MB ", used_now_f);
printf("Err : %s\n", hipGetErrorString(hipGetLastError()) );
return 0;
} else {
//printf("Allocated %d int's.\n", int(size));
}
hipFree(devPtr);
size = (size* sizeof(int) + inc )/sizeof(int) ;
mem_size = sizeof(int) * size ;
i=i+1;
} while(1);
} | .text
.file "malloc_test.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
movq $0, 48(%rsp)
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
callq hipMemGetInfo
movq 32(%rsp), %rax
testq %rax, %rax
js .LBB0_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB0_3
.LBB0_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_3:
mulss .LCPI0_0(%rip), %xmm0
cmpl $2, %ebx
movss %xmm0, 8(%rsp) # 4-byte Spill
jg .LBB0_5
# %bb.4:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
jmp .LBB0_20
.LBB0_5:
movq 24(%rsp), %rax
testq %rax, %rax
js .LBB0_6
# %bb.7:
cvtsi2ss %rax, %xmm1
jmp .LBB0_8
.LBB0_6:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB0_8:
mulss .LCPI0_0(%rip), %xmm1
movss %xmm1, 44(%rsp) # 4-byte Spill
movaps %xmm1, %xmm2
subss %xmm0, %xmm2
movss %xmm2, 16(%rsp) # 4-byte Spill
movq 8(%r14), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rbp
shrq $2, %rbp
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %r15
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movsd %xmm2, 8(%rsp) # 8-byte Spill
movb $3, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %r15, %r14
shlq $20, %r14
shrq $2, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movq %rbp, %r13
shlq $22, %r13
addq %r12, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
callq hipMemGetInfo
movq 32(%rsp), %rax
testq %rax, %rax
js .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_9 Depth=1
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB0_12: # in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rax
testq %rax, %rax
js .LBB0_13
# %bb.14: # in Loop: Header=BB0_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
testq %r13, %r13
jns .LBB0_17
.LBB0_16: # in Loop: Header=BB0_9 Depth=1
movq %r13, %rax
shrq %rax
andl $1, %r13d
orq %rax, %r13
xorps %xmm2, %xmm2
cvtsi2ss %r13, %xmm2
addss %xmm2, %xmm2
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
testq %r13, %r13
js .LBB0_16
.LBB0_17: # in Loop: Header=BB0_9 Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r13, %xmm2
.LBB0_18: # in Loop: Header=BB0_9 Depth=1
movss .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm3, %xmm1
mulss %xmm3, %xmm0
mulss %xmm3, %xmm2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
xorps %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
movl $.L.str.6, %edi
movl %ebx, %esi
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd %xmm3, 16(%rsp) # 8-byte Spill
movb $4, %al
callq printf
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_19
# %bb.21: # in Loop: Header=BB0_9 Depth=1
callq hipFree
addq %r15, %rbp
movabsq $4611686018427387903, %rax # imm = 0x3FFFFFFFFFFFFFFF
andq %rax, %rbp
addq %r14, %r12
incl %ebx
jmp .LBB0_9
.LBB0_19:
movl $.L.str.7, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB0_20:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "\ncurrent free memory is %.1f\n"
.size .L.str.2, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n"
.size .L.str.6, 40
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "couldn't allocate %.1f MB "
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Err : %s\n"
.size .L.str.8, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)"
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "------------------------------------------------------------------"
.size .Lstr.2, 67
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB "
.size .Lstr.3, 97
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB"
.size .Lstr.4, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187077_00000000-6_malloc_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string " plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB \n"
.align 8
.LC2:
.string "\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\ncurrent free memory is %.1f\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "------------------------------------------------------------------\n"
.align 8
.LC5:
.string "\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)\n"
.align 8
.LC6:
.string "0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n"
.align 8
.LC7:
.string "%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n"
.section .rodata.str1.1
.LC8:
.string "couldn't allocate %.1f MB "
.LC9:
.string "Err : %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMemGetInfo@PLT
movq 24(%rsp), %rax
testq %rax, %rax
js .L4
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L5:
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rsp)
movq 32(%rsp), %rax
cmpl $2, %ebx
jg .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L7:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L5
.L6:
testq %rax, %rax
js .L8
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L9:
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rsp)
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
shrq $2, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
leaq .LC4(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm5
movaps %xmm5, %xmm0
movss (%rsp), %xmm6
subss %xmm6, %xmm0
pxor %xmm2, %xmm2
cvtss2sd %xmm0, %xmm2
movsd %xmm2, (%rsp)
pxor %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm6, %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movl $0, %r12d
leaq .LC7(%rip), %r14
jmp .L17
.L8:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L9
.L10:
shrq %r15
pxor %xmm0, %xmm0
cvtsi2ssq %r15, %xmm0
addss %xmm0, %xmm0
jmp .L11
.L12:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
addss %xmm1, %xmm1
jmp .L13
.L14:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L15:
mulss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r15, %xmm3
movsd (%rsp), %xmm2
movl %r12d, %edx
movq %r14, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
addq %r13, %rbp
testq %rdi, %rdi
je .L21
call cudaFree@PLT
addq %r13, %rbx
shrq $2, %rbx
addl $1, %r12d
.L17:
salq $2, %rbx
leaq (%rbx,%rbp), %r15
salq $20, %r15
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdi
call cudaMemGetInfo@PLT
testq %r15, %r15
js .L10
pxor %xmm0, %xmm0
cvtsi2ssq %r15, %xmm0
.L11:
mulss .LC0(%rip), %xmm0
pxor %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movq %xmm4, %r15
movq 24(%rsp), %rax
testq %rax, %rax
js .L12
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
.L13:
mulss .LC0(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movq 32(%rsp), %rax
testq %rax, %rax
js .L14
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L15
.L21:
movq %r15, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 897581056
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "malloc_test.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x35800000 # float 9.53674316E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebx
movq $0, 48(%rsp)
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
callq hipMemGetInfo
movq 32(%rsp), %rax
testq %rax, %rax
js .LBB0_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB0_3
.LBB0_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_3:
mulss .LCPI0_0(%rip), %xmm0
cmpl $2, %ebx
movss %xmm0, 8(%rsp) # 4-byte Spill
jg .LBB0_5
# %bb.4:
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
jmp .LBB0_20
.LBB0_5:
movq 24(%rsp), %rax
testq %rax, %rax
js .LBB0_6
# %bb.7:
cvtsi2ss %rax, %xmm1
jmp .LBB0_8
.LBB0_6:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB0_8:
mulss .LCPI0_0(%rip), %xmm1
movss %xmm1, 44(%rsp) # 4-byte Spill
movaps %xmm1, %xmm2
subss %xmm0, %xmm2
movss %xmm2, 16(%rsp) # 4-byte Spill
movq 8(%r14), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %rbp
shrq $2, %rbp
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movslq %eax, %r15
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 8(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movsd %xmm2, 8(%rsp) # 8-byte Spill
movb $3, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq %r15, %r14
shlq $20, %r14
shrq $2, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movq %rbp, %r13
shlq $22, %r13
addq %r12, %r13
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
leaq 24(%rsp), %rsi
callq hipMemGetInfo
movq 32(%rsp), %rax
testq %rax, %rax
js .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_9 Depth=1
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB0_12: # in Loop: Header=BB0_9 Depth=1
movq 24(%rsp), %rax
testq %rax, %rax
js .LBB0_13
# %bb.14: # in Loop: Header=BB0_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
testq %r13, %r13
jns .LBB0_17
.LBB0_16: # in Loop: Header=BB0_9 Depth=1
movq %r13, %rax
shrq %rax
andl $1, %r13d
orq %rax, %r13
xorps %xmm2, %xmm2
cvtsi2ss %r13, %xmm2
addss %xmm2, %xmm2
jmp .LBB0_18
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_9 Depth=1
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
testq %r13, %r13
js .LBB0_16
.LBB0_17: # in Loop: Header=BB0_9 Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %r13, %xmm2
.LBB0_18: # in Loop: Header=BB0_9 Depth=1
movss .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm3, %xmm1
mulss %xmm3, %xmm0
mulss %xmm3, %xmm2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
xorps %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
movl $.L.str.6, %edi
movl %ebx, %esi
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd %xmm3, 16(%rsp) # 8-byte Spill
movb $4, %al
callq printf
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_19
# %bb.21: # in Loop: Header=BB0_9 Depth=1
callq hipFree
addq %r15, %rbp
movabsq $4611686018427387903, %rax # imm = 0x3FFFFFFFFFFFFFFF
andq %rax, %rbp
addq %r14, %r12
incl %ebx
jmp .LBB0_9
.LBB0_19:
movl $.L.str.7, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB0_20:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "\ncurrent free memory is %.1f\n"
.size .L.str.2, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "0\t%.1f =\t%.1f+ \t%.1f \t <------ initial used memory \n"
.size .L.str.5, 64
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\t%.1f =\t%.1f+ \t%.1f+ \t%.1f \n"
.size .L.str.6, 40
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "couldn't allocate %.1f MB "
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Err : %s\n"
.size .L.str.8, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\tTotal(MB)=\tFree(MB)+\tinit(MB)+\tAlloc(MB)"
.size .Lstr.1, 42
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "------------------------------------------------------------------"
.size .Lstr.2, 67
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " plz use below command \n ./malloc_test 1024 10 \n to malloc 1024MB and increment would be 10MB "
.size .Lstr.3, 97
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n11GB 11264MB\n15GB 15360MB \n23GB 23552MB\n31GB 31744MB"
.size .Lstr.4, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <float.h>
#ifndef M_PI
# define M_PI 3.14159265358979323846
#endif
# define N 192
__device__ int count;
__device__ void sum(double *partial_sum, int dummy) {
if(threadIdx.x == 0) {
count = dummy;
if(count %2 != 0) {
count++;
partial_sum[count-1] = 0;
}
}
__syncthreads();
for(int i = count/2; i > 0; i = i/2) {
if(threadIdx.x < i)
partial_sum[threadIdx.x] += partial_sum[threadIdx.x + i];
__syncthreads();
if(threadIdx.x == 0) {
if(i%2 != 0 && i != 1) {
partial_sum[0] += partial_sum[--i];
}
}
__syncthreads();
}
__syncthreads();
return;
}
void init_grid_points(double * x, double * y, int m)
{
double h = (double)1/(m + 1);
for (int i = 0; i < m; i ++)
{
for (int j = 0; j < m; j ++)
{
x[i*m+j] = (i + 1)*h;
y[i*m+j] = (j + 1)*h;
}
}
}
void init_observed_data_vector(double * f, double * x, double * y, int m)
{
double l[2] = {(double)2/m, (double)2/m};
int n = m * m;
//kernel(f, x, y, l, n);
for (int i = 0; i < n; i ++)
{
f[i] = 0.02 * ((double)rand() / (double)RAND_MAX - 0.5);
double d = pow((x[i] - 0.25)/l[0], 2) + pow((y[i] - 0.25)/l[1],2);
f[i] += 1.0/sqrt(2.0*M_PI) *exp(-d/2);
f[i] += x[i] * 0.2 + y[i] * 0.1;
}
}
void randperm(int * r, int n){
for(int i = 0; i < n; i ++){
r[i] = i;
}
for (int i = n - 1; i >= 0; i --){
int j = rand() % (i + 1);
int temp = r[i];
r[i] = r[j];
r[j] = temp;
}
}
void init_data_set_indices(int * itest, int * itrain, int ntest, int ntrain){
int n = ntest + ntrain;
int * r = (int *) malloc(n * sizeof(int));
randperm(r, n);
for (int i = 0; i < ntest; i ++){
itest[i] = r[i];
}
for (int i = 0; i < ntrain; i ++){
itrain[i] = r[ntest + i];
}
free(r);
}
void compute_A(double * A, double t, int n)//tI + K
{
//Compute A = tI+K
for (int i = 0; i < n; i ++)
{
A[i*n + i] += t;
}
}
__device__ void compute_A_gpu(double * A, double t, int n)//tI + K
{
//Compute A = tI+K
for (int i = threadIdx.x; i < n; i += N)
{
A[i*n + i] += t;
}
}
void compute_k(double * k, double * x, double * y, double * rstar, int n)
{
int i;
double d;
for (i = 0; i < n; i ++)
{
d = pow(rstar[0]-x[i], 2) + pow(rstar[1]-y[i], 2);
k[i] = exp(-d);
}
}
void compute_LU_factors(double * A, int n)
{
int k, i, j;
double m;
for (k = 0; k < n - 1; k ++)
{
for (i = k + 1; i < n; i ++)
{
m = A[i*n + k] / A[k*n + k];
for (j = k + 1; j < n; j ++)
{
A[i*n + j] = A[i*n + j] - m * A[k*n + j];
}
A[i*n + k] = m;
}
}
}
void solve_triangular_systems(double * z, double * A, double * f, int * itrain, int n)
{
int i, j;
double m;
//Solve Az = f by LUz = f
//1. Solve Ly = f for y
for (i = 0; i < n; i ++)
{
m = 0;
for (j = 0; j < i; j ++)
{
m += A[i*n + j] * z[j];
}
z[i] = (f[itrain[i]] - m)/A[i*n + i];
}
//2. Solve Uz = y for z
for (i = n - 1; i >= 0; i --)
{
m = 0;
for (j = i + 1; j < n; j ++)
{
m += A[i*n + j] * z[j];
}
z[i] = (z[i]-m)/A[i*n + i];
}
}
double compute_fstar(double * k, double * z, int n)
{
int i;
double fstar = 0.0;
// Compute predicted value fstar at rstar: k'*z
for (i = 0; i < n; i ++)
{
fstar += k[i] * z[i];
}
return fstar;
}
void compute_ftest(double * ftest, double * k, double * z, int ntrain, int ntest)
{
// Compute predicted value ftest at itest array: kT*z
for (int i = 0; i < ntest; i ++)
{
ftest[i] = 0;
for (int j = 0; j < ntrain; j ++){
ftest[i] += k[i * ntrain + j] * z[j];
}
}
}
void compute_kernel(double * K, double * x, double * y, double * l, int n)
{
for (int i = 0; i < n; i ++)
{
for (int j = 0; j < n; j++)
{
double d = pow((x[i] - x[j])/l[0], 2) + pow((y[i] - y[j])/l[1],2);
K[i*n + j] = 1.0/sqrt(2.0*M_PI) * exp(-d/2);
}
}
}
__device__ void compute_kernel_gpu(double * K, double * x, double * y, double * l, int n)
{
for (int m = threadIdx.x; m < n*n; m += N )
{
int i = m / n;
int j = m % n;
if (i < j){
continue;
}
double d = pow((x[i] - x[j])/l[0], 2) + pow((y[i] - y[j])/l[1],2);
K[i*n + j] = 1.0/sqrt(2.0*M_PI) * exp(-d/2);
K[j*n + i] = K[i*n + j];
}
return;
}
void extract_K(double * K0, double * K, int * i1, int * i2, int n, int n1, int n2){
for (int i = 0; i < n1; i ++)
{
for (int j = 0; j < n2; j++)
{
K[i * n2 + j] = K0[i1[i] * n + i2[j]];
}
}
}
__device__ void extract_K_gpu(double * K0, double * K, int * i1, int * i2, int n, int n1, int n2){
for (int m = threadIdx.x; m < n1*n2; m += N )
{
int i = m / n2;
int j = m % n2;
K[i * n2 + j] = K0[i1[i] * n + i2[j]];
}
return;
}
__device__ void print_array(double * array, int n)
{
for (int i = 0; i < n; i++)
{
printf("%.4f ", array[i]);
}
printf("\n");
}
__device__ void print_matrix(double * matrix, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
printf("%.4f ", matrix[i*n + j]);
}
printf("\n");
}
}
void GPR(double * ftest, double * x, double * y, double * f, int * itest, int * itrain, double t, double * l, int n, int ntest)
{
int ntrain = n - ntest;
double * K0;
double * LU;
double * kT;
double * z;
// Allocate host memory
K0 = (double *) malloc(n * n * sizeof(double));
LU = (double *) malloc(ntrain * ntrain * sizeof(double));
kT = (double *) malloc(ntest * ntrain * sizeof(double));
z = (double *) malloc(ntrain * sizeof(double));
printf("CPU\n");
compute_kernel(K0, x, y, l, n);
extract_K(K0, LU, itrain, itrain, n, ntrain, ntrain);
compute_A(LU, t, ntrain);//tI + K
compute_LU_factors(LU, ntrain);
extract_K(K0, kT, itest, itrain, n, ntest, ntrain);
solve_triangular_systems(z, LU, f, itrain, ntrain);
compute_ftest(ftest, kT, z, ntrain, ntest);
free(K0);
free(LU);
free(kT);
free(z);
}
__global__ void GPR_gpu(double * ftest, double * x, double * y, double * f, int * itest, int * itrain, double t, double * l, int n, int ntest)
{
extern __shared__ double partial_sum[];
__shared__ double * K0;
__shared__ double * A;
__shared__ double * kT;
__shared__ double * z;
int ntrain = n - ntest;
if (threadIdx.x == 0) {
K0 = (double *) malloc(n * n * sizeof(double));
A = (double *) malloc(ntrain * ntrain * sizeof(double));
kT = (double *) malloc(ntest * ntrain * sizeof(double));
}
__syncthreads();
compute_kernel_gpu(K0, x, y, l, n);
__syncthreads();
extract_K_gpu(K0, A, itrain, itrain, n, ntrain, ntrain);
__syncthreads();
extract_K_gpu(K0, kT, itest, itrain, n, ntest, ntrain);
__syncthreads();
if (threadIdx.x == 0) {
free(K0);
z = (double *) malloc(ntrain * sizeof(double));
}
__syncthreads();
compute_A_gpu(A, t, ntrain); //tI + K
n = ntrain;
__syncthreads();
// compute LU factors
for (int k = 0; k < n - 1; k ++)
{
for (int i = k + 1 + threadIdx.x; i < n; i += N)
{
A[i*n + k] = A[i*n + k] / A[k*n + k];
}
__syncthreads();
for (int m = threadIdx.x; m < (n - k - 1)*(n - k - 1); m += N )
{
int i = k + 1 + m / (n - k - 1);
int j = k + 1 + m % (n - k - 1);
A[i*n + j] -= A[i*n + k] * A[k*n + j];
}
__syncthreads();
}
__syncthreads();
//Solve Az = f by LUz = f
// 1. Solve Ly = f for y
for (int i = 0; i < n; i ++)
{
partial_sum[threadIdx.x] = 0;
for (int j = threadIdx.x; j < i; j += N)
{
partial_sum[threadIdx.x] += A[i*n + j] * z[j];
}
__syncthreads();
sum (partial_sum, (N<i)?N:i);
if (threadIdx.x == 0){
z[i] = (f[itrain[i]] - partial_sum[0])/A[i*n + i];
}
__syncthreads();
}
__syncthreads();
//2. Solve Uz = y for z
for (int i = n - 1; i >= 0; i --)
{
partial_sum[threadIdx.x] = 0;
for (int j = i + 1 + threadIdx.x; j < n; j += N)
{
partial_sum[threadIdx.x] += A[i*n + j] * z[j];
}
__syncthreads();
sum(partial_sum, (N < (n-1-i))? N:(n-1-i));
if(threadIdx.x == 0) {
z[i] = (z[i]-partial_sum[0])/A[i*n + i];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == 0) {
free(A);
// cudaFree(A);
}
__syncthreads();
// compute ftest
for (int i = 0; i < ntest; i ++)
{
partial_sum[threadIdx.x] = 0;
for (int j = threadIdx.x; j < ntrain; j += N){
partial_sum[threadIdx.x] += kT[i * ntrain + j] * z[j];
}
__syncthreads();
sum(partial_sum, (N < ntrain)? N : ntrain);
if(threadIdx.x == 0) {
ftest[i] = partial_sum[0];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == 0) {
free(kT);
free(z);
}
__syncthreads();
return;
}
double compute_MSE(double * f, int * itest, double * ftest, int ntest) // compute the mean square error
{
double squareError = 0;
for (int i = 0; i < ntest; i ++){
squareError += pow(f[itest[i]] - ftest[i], 2);
}
return squareError / ntest;
}
int main(int argc, char** argv)
{
// Host Data
double * hGx; // host grid x-coordinate array
double * hGy; // host grid y-coordinate array
double * hf;// host observed data vector f
int * hitest; // Indices of test points (randomly chosen)
int * hitrain; //Indices of training points
// Device Data
double * dx;
double * dy;
double * dl;
double * df;
double * dftest;
int * ditest;
int * ditrain;
// Grid size m, grid points n, size of test data and training data,
int m = 4, n, ntest, ntrain;
// Coordinate of hyper-parameter l(l1, l2)
double l[2], bestL[2];
// predicted value of test
double * ftest;
// Timing variables
cudaEvent_t start, stop; // GPU timing variables
float total_time;
// Other variables
// double fstar;
double Lparam[20];
double MSE[20][20];
int size;
double minMSE = DBL_MAX;
// Timing initializations
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Check input
if (argc > 1){
m = atoi(argv[1]);
}else{
printf("Please indicate grid size m\n");
return -1;
}
// Allocate host coordinate arrays
n = m * m;
size = n * sizeof(double);
hGx = (double *) malloc(size);
hGy = (double *) malloc(size);
hf = (double *) malloc(size);
ntest = (n + 9) / 10;
ntrain = n - ntest;
printf("testing data: %d, training data: %d\n", ntest, ntrain);
size = sizeof(int);
hitest = (int *) malloc(ntest * size);
hitrain = (int *) malloc(ntrain * size);
size = sizeof(double);
ftest = (double *) malloc(ntest * size);
for (int i = 0; i < 20; i++){
Lparam[i] = (i + 1) * 0.5/ m;
}
init_grid_points(hGx, hGy, m);
srand(time(0));
init_observed_data_vector(hf, hGx, hGy, m);
init_data_set_indices(hitest, hitrain, ntest, ntrain);
printf("Number of threads %d\n", N);
cudaMalloc(&dx, n * sizeof(double));
cudaMalloc(&dy, n * sizeof(double));
cudaMalloc(&dl, 2 * sizeof(double));
cudaMalloc(&dftest, ntest * sizeof(double));
cudaMalloc(&df, n * sizeof(double));
cudaMalloc(&ditest, ntest * sizeof(int));
cudaMalloc(&ditrain, ntrain * sizeof(int));
cudaMemcpy(dx, hGx, n * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(dy, hGy, n * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(df, hf, n * sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(ditest, hitest, ntest * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(ditrain, hitrain, ntrain * sizeof(int), cudaMemcpyHostToDevice);
double t = 0.5;// Parameter t
// printf("20*20 values of Parameter L[2]\n");
for (int il1 = 0; il1 < 20; il1 ++){
l[0] = Lparam[il1];
for (int il2 = 0; il2 < 20; il2 ++){
l[1] = Lparam[il2];
// printf("(%d,%d)\t",il1, il2);
// GPR(ftest, hGx, hGy, hf, hitest, hitrain, t, l, n, ntest);
cudaMemcpy(dl, l, 2 * sizeof(double), cudaMemcpyHostToDevice);
if(il1 == 0 && il2 == 0){
cudaEventRecord(start, 0);
GPR_gpu<<<1, N, N * sizeof(double)>>>(dftest, dx, dy, df, ditest, ditrain, t, dl, n, ntest);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&total_time, start, stop);
printf("One round time = %f ms\n", total_time);
}else{
GPR_gpu<<<1, N, N * sizeof(double)>>>(dftest, dx, dy, df, ditest, ditrain, t, dl, n, ntest);
}
cudaMemcpy(ftest, dftest, ntest * sizeof(double), cudaMemcpyDeviceToHost);
// print_array(ftest, ntest);
MSE[il1][il2] = compute_MSE(hf, hitest, ftest, ntest);
printf("\rFinished (l1,l2) = %f, %f, mse = %e", Lparam[il1], Lparam[il2], MSE[il1][il2]);
if (MSE[il1][il2] < minMSE){
bestL[0] = l[0];
bestL[1] = l[1];
minMSE = MSE[il1][il2];
}
printf("\t progress: %d/400", il1*20 + il2+1);
}
}
printf("\nBest (l1,l2) = %f, %f, mse = %e\n", bestL[0], bestL[1], minMSE);
free(hGx);
free(hGy);
free(hf);
free(hitest);
free(hitrain);
free(ftest);
cudaFree(dx);
cudaFree(dy);
cudaFree(dl);
cudaFree(df);
cudaFree(dftest);
cudaFree(ditest);
cudaFree(ditrain);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <float.h>
#ifndef M_PI
# define M_PI 3.14159265358979323846
#endif
# define N 192
__device__ int count;
__device__ void sum(double *partial_sum, int dummy) {
if(threadIdx.x == 0) {
count = dummy;
if(count %2 != 0) {
count++;
partial_sum[count-1] = 0;
}
}
__syncthreads();
for(int i = count/2; i > 0; i = i/2) {
if(threadIdx.x < i)
partial_sum[threadIdx.x] += partial_sum[threadIdx.x + i];
__syncthreads();
if(threadIdx.x == 0) {
if(i%2 != 0 && i != 1) {
partial_sum[0] += partial_sum[--i];
}
}
__syncthreads();
}
__syncthreads();
return;
}
void init_grid_points(double * x, double * y, int m)
{
double h = (double)1/(m + 1);
for (int i = 0; i < m; i ++)
{
for (int j = 0; j < m; j ++)
{
x[i*m+j] = (i + 1)*h;
y[i*m+j] = (j + 1)*h;
}
}
}
void init_observed_data_vector(double * f, double * x, double * y, int m)
{
double l[2] = {(double)2/m, (double)2/m};
int n = m * m;
//kernel(f, x, y, l, n);
for (int i = 0; i < n; i ++)
{
f[i] = 0.02 * ((double)rand() / (double)RAND_MAX - 0.5);
double d = pow((x[i] - 0.25)/l[0], 2) + pow((y[i] - 0.25)/l[1],2);
f[i] += 1.0/sqrt(2.0*M_PI) *exp(-d/2);
f[i] += x[i] * 0.2 + y[i] * 0.1;
}
}
void randperm(int * r, int n){
for(int i = 0; i < n; i ++){
r[i] = i;
}
for (int i = n - 1; i >= 0; i --){
int j = rand() % (i + 1);
int temp = r[i];
r[i] = r[j];
r[j] = temp;
}
}
void init_data_set_indices(int * itest, int * itrain, int ntest, int ntrain){
int n = ntest + ntrain;
int * r = (int *) malloc(n * sizeof(int));
randperm(r, n);
for (int i = 0; i < ntest; i ++){
itest[i] = r[i];
}
for (int i = 0; i < ntrain; i ++){
itrain[i] = r[ntest + i];
}
free(r);
}
void compute_A(double * A, double t, int n)//tI + K
{
//Compute A = tI+K
for (int i = 0; i < n; i ++)
{
A[i*n + i] += t;
}
}
__device__ void compute_A_gpu(double * A, double t, int n)//tI + K
{
//Compute A = tI+K
for (int i = threadIdx.x; i < n; i += N)
{
A[i*n + i] += t;
}
}
void compute_k(double * k, double * x, double * y, double * rstar, int n)
{
int i;
double d;
for (i = 0; i < n; i ++)
{
d = pow(rstar[0]-x[i], 2) + pow(rstar[1]-y[i], 2);
k[i] = exp(-d);
}
}
void compute_LU_factors(double * A, int n)
{
int k, i, j;
double m;
for (k = 0; k < n - 1; k ++)
{
for (i = k + 1; i < n; i ++)
{
m = A[i*n + k] / A[k*n + k];
for (j = k + 1; j < n; j ++)
{
A[i*n + j] = A[i*n + j] - m * A[k*n + j];
}
A[i*n + k] = m;
}
}
}
void solve_triangular_systems(double * z, double * A, double * f, int * itrain, int n)
{
int i, j;
double m;
//Solve Az = f by LUz = f
//1. Solve Ly = f for y
for (i = 0; i < n; i ++)
{
m = 0;
for (j = 0; j < i; j ++)
{
m += A[i*n + j] * z[j];
}
z[i] = (f[itrain[i]] - m)/A[i*n + i];
}
//2. Solve Uz = y for z
for (i = n - 1; i >= 0; i --)
{
m = 0;
for (j = i + 1; j < n; j ++)
{
m += A[i*n + j] * z[j];
}
z[i] = (z[i]-m)/A[i*n + i];
}
}
double compute_fstar(double * k, double * z, int n)
{
int i;
double fstar = 0.0;
// Compute predicted value fstar at rstar: k'*z
for (i = 0; i < n; i ++)
{
fstar += k[i] * z[i];
}
return fstar;
}
void compute_ftest(double * ftest, double * k, double * z, int ntrain, int ntest)
{
// Compute predicted value ftest at itest array: kT*z
for (int i = 0; i < ntest; i ++)
{
ftest[i] = 0;
for (int j = 0; j < ntrain; j ++){
ftest[i] += k[i * ntrain + j] * z[j];
}
}
}
void compute_kernel(double * K, double * x, double * y, double * l, int n)
{
for (int i = 0; i < n; i ++)
{
for (int j = 0; j < n; j++)
{
double d = pow((x[i] - x[j])/l[0], 2) + pow((y[i] - y[j])/l[1],2);
K[i*n + j] = 1.0/sqrt(2.0*M_PI) * exp(-d/2);
}
}
}
__device__ void compute_kernel_gpu(double * K, double * x, double * y, double * l, int n)
{
for (int m = threadIdx.x; m < n*n; m += N )
{
int i = m / n;
int j = m % n;
if (i < j){
continue;
}
double d = pow((x[i] - x[j])/l[0], 2) + pow((y[i] - y[j])/l[1],2);
K[i*n + j] = 1.0/sqrt(2.0*M_PI) * exp(-d/2);
K[j*n + i] = K[i*n + j];
}
return;
}
void extract_K(double * K0, double * K, int * i1, int * i2, int n, int n1, int n2){
for (int i = 0; i < n1; i ++)
{
for (int j = 0; j < n2; j++)
{
K[i * n2 + j] = K0[i1[i] * n + i2[j]];
}
}
}
__device__ void extract_K_gpu(double * K0, double * K, int * i1, int * i2, int n, int n1, int n2){
for (int m = threadIdx.x; m < n1*n2; m += N )
{
int i = m / n2;
int j = m % n2;
K[i * n2 + j] = K0[i1[i] * n + i2[j]];
}
return;
}
__device__ void print_array(double * array, int n)
{
for (int i = 0; i < n; i++)
{
printf("%.4f ", array[i]);
}
printf("\n");
}
__device__ void print_matrix(double * matrix, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
printf("%.4f ", matrix[i*n + j]);
}
printf("\n");
}
}
void GPR(double * ftest, double * x, double * y, double * f, int * itest, int * itrain, double t, double * l, int n, int ntest)
{
int ntrain = n - ntest;
double * K0;
double * LU;
double * kT;
double * z;
// Allocate host memory
K0 = (double *) malloc(n * n * sizeof(double));
LU = (double *) malloc(ntrain * ntrain * sizeof(double));
kT = (double *) malloc(ntest * ntrain * sizeof(double));
z = (double *) malloc(ntrain * sizeof(double));
printf("CPU\n");
compute_kernel(K0, x, y, l, n);
extract_K(K0, LU, itrain, itrain, n, ntrain, ntrain);
compute_A(LU, t, ntrain);//tI + K
compute_LU_factors(LU, ntrain);
extract_K(K0, kT, itest, itrain, n, ntest, ntrain);
solve_triangular_systems(z, LU, f, itrain, ntrain);
compute_ftest(ftest, kT, z, ntrain, ntest);
free(K0);
free(LU);
free(kT);
free(z);
}
__global__ void GPR_gpu(double * ftest, double * x, double * y, double * f, int * itest, int * itrain, double t, double * l, int n, int ntest)
{
extern __shared__ double partial_sum[];
__shared__ double * K0;
__shared__ double * A;
__shared__ double * kT;
__shared__ double * z;
int ntrain = n - ntest;
if (threadIdx.x == 0) {
K0 = (double *) malloc(n * n * sizeof(double));
A = (double *) malloc(ntrain * ntrain * sizeof(double));
kT = (double *) malloc(ntest * ntrain * sizeof(double));
}
__syncthreads();
compute_kernel_gpu(K0, x, y, l, n);
__syncthreads();
extract_K_gpu(K0, A, itrain, itrain, n, ntrain, ntrain);
__syncthreads();
extract_K_gpu(K0, kT, itest, itrain, n, ntest, ntrain);
__syncthreads();
if (threadIdx.x == 0) {
free(K0);
z = (double *) malloc(ntrain * sizeof(double));
}
__syncthreads();
compute_A_gpu(A, t, ntrain); //tI + K
n = ntrain;
__syncthreads();
// compute LU factors
for (int k = 0; k < n - 1; k ++)
{
for (int i = k + 1 + threadIdx.x; i < n; i += N)
{
A[i*n + k] = A[i*n + k] / A[k*n + k];
}
__syncthreads();
for (int m = threadIdx.x; m < (n - k - 1)*(n - k - 1); m += N )
{
int i = k + 1 + m / (n - k - 1);
int j = k + 1 + m % (n - k - 1);
A[i*n + j] -= A[i*n + k] * A[k*n + j];
}
__syncthreads();
}
__syncthreads();
//Solve Az = f by LUz = f
// 1. Solve Ly = f for y
for (int i = 0; i < n; i ++)
{
partial_sum[threadIdx.x] = 0;
for (int j = threadIdx.x; j < i; j += N)
{
partial_sum[threadIdx.x] += A[i*n + j] * z[j];
}
__syncthreads();
sum (partial_sum, (N<i)?N:i);
if (threadIdx.x == 0){
z[i] = (f[itrain[i]] - partial_sum[0])/A[i*n + i];
}
__syncthreads();
}
__syncthreads();
//2. Solve Uz = y for z
for (int i = n - 1; i >= 0; i --)
{
partial_sum[threadIdx.x] = 0;
for (int j = i + 1 + threadIdx.x; j < n; j += N)
{
partial_sum[threadIdx.x] += A[i*n + j] * z[j];
}
__syncthreads();
sum(partial_sum, (N < (n-1-i))? N:(n-1-i));
if(threadIdx.x == 0) {
z[i] = (z[i]-partial_sum[0])/A[i*n + i];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == 0) {
free(A);
// cudaFree(A);
}
__syncthreads();
// compute ftest
for (int i = 0; i < ntest; i ++)
{
partial_sum[threadIdx.x] = 0;
for (int j = threadIdx.x; j < ntrain; j += N){
partial_sum[threadIdx.x] += kT[i * ntrain + j] * z[j];
}
__syncthreads();
sum(partial_sum, (N < ntrain)? N : ntrain);
if(threadIdx.x == 0) {
ftest[i] = partial_sum[0];
}
__syncthreads();
}
__syncthreads();
if (threadIdx.x == 0) {
free(kT);
free(z);
}
__syncthreads();
return;
}
double compute_MSE(double * f, int * itest, double * ftest, int ntest) // compute the mean square error
{
double squareError = 0;
for (int i = 0; i < ntest; i ++){
squareError += pow(f[itest[i]] - ftest[i], 2);
}
return squareError / ntest;
}
int main(int argc, char** argv)
{
// Host Data
double * hGx; // host grid x-coordinate array
double * hGy; // host grid y-coordinate array
double * hf;// host observed data vector f
int * hitest; // Indices of test points (randomly chosen)
int * hitrain; //Indices of training points
// Device Data
double * dx;
double * dy;
double * dl;
double * df;
double * dftest;
int * ditest;
int * ditrain;
// Grid size m, grid points n, size of test data and training data,
int m = 4, n, ntest, ntrain;
// Coordinate of hyper-parameter l(l1, l2)
double l[2], bestL[2];
// predicted value of test
double * ftest;
// Timing variables
hipEvent_t start, stop; // GPU timing variables
float total_time;
// Other variables
// double fstar;
double Lparam[20];
double MSE[20][20];
int size;
double minMSE = DBL_MAX;
// Timing initializations
hipEventCreate(&start);
hipEventCreate(&stop);
// Check input
if (argc > 1){
m = atoi(argv[1]);
}else{
printf("Please indicate grid size m\n");
return -1;
}
// Allocate host coordinate arrays
n = m * m;
size = n * sizeof(double);
hGx = (double *) malloc(size);
hGy = (double *) malloc(size);
hf = (double *) malloc(size);
ntest = (n + 9) / 10;
ntrain = n - ntest;
printf("testing data: %d, training data: %d\n", ntest, ntrain);
size = sizeof(int);
hitest = (int *) malloc(ntest * size);
hitrain = (int *) malloc(ntrain * size);
size = sizeof(double);
ftest = (double *) malloc(ntest * size);
for (int i = 0; i < 20; i++){
Lparam[i] = (i + 1) * 0.5/ m;
}
init_grid_points(hGx, hGy, m);
srand(time(0));
init_observed_data_vector(hf, hGx, hGy, m);
init_data_set_indices(hitest, hitrain, ntest, ntrain);
printf("Number of threads %d\n", N);
hipMalloc(&dx, n * sizeof(double));
hipMalloc(&dy, n * sizeof(double));
hipMalloc(&dl, 2 * sizeof(double));
hipMalloc(&dftest, ntest * sizeof(double));
hipMalloc(&df, n * sizeof(double));
hipMalloc(&ditest, ntest * sizeof(int));
hipMalloc(&ditrain, ntrain * sizeof(int));
hipMemcpy(dx, hGx, n * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(dy, hGy, n * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(df, hf, n * sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(ditest, hitest, ntest * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(ditrain, hitrain, ntrain * sizeof(int), hipMemcpyHostToDevice);
double t = 0.5;// Parameter t
// printf("20*20 values of Parameter L[2]\n");
for (int il1 = 0; il1 < 20; il1 ++){
l[0] = Lparam[il1];
for (int il2 = 0; il2 < 20; il2 ++){
l[1] = Lparam[il2];
// printf("(%d,%d)\t",il1, il2);
// GPR(ftest, hGx, hGy, hf, hitest, hitrain, t, l, n, ntest);
hipMemcpy(dl, l, 2 * sizeof(double), hipMemcpyHostToDevice);
if(il1 == 0 && il2 == 0){
hipEventRecord(start, 0);
GPR_gpu<<<1, N, N * sizeof(double)>>>(dftest, dx, dy, df, ditest, ditrain, t, dl, n, ntest);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&total_time, start, stop);
printf("One round time = %f ms\n", total_time);
}else{
GPR_gpu<<<1, N, N * sizeof(double)>>>(dftest, dx, dy, df, ditest, ditrain, t, dl, n, ntest);
}
hipMemcpy(ftest, dftest, ntest * sizeof(double), hipMemcpyDeviceToHost);
// print_array(ftest, ntest);
MSE[il1][il2] = compute_MSE(hf, hitest, ftest, ntest);
printf("\rFinished (l1,l2) = %f, %f, mse = %e", Lparam[il1], Lparam[il2], MSE[il1][il2]);
if (MSE[il1][il2] < minMSE){
bestL[0] = l[0];
bestL[1] = l[1];
minMSE = MSE[il1][il2];
}
printf("\t progress: %d/400", il1*20 + il2+1);
}
}
printf("\nBest (l1,l2) = %f, %f, mse = %e\n", bestL[0], bestL[1], minMSE);
free(hGx);
free(hGy);
free(hf);
free(hitest);
free(hitrain);
free(ftest);
hipFree(dx);
hipFree(dy);
hipFree(dl);
hipFree(df);
hipFree(dftest);
hipFree(ditest);
hipFree(ditrain);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
cudaMalloc((void**)&d_in, size);
cudaMalloc((void**)&d_exp, size);
cudaMalloc((void**)&d_sum, sizeof(double));
cudaMalloc((void**)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
cudaMemcpy(h_out, d_exp, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_exp);
cudaFree(d_sum);
cudaFree(d_out);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z7softmaxPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fcc00078e00ff */
/*00a0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x652b82fe ; /* 0x652b82feff047424 */
/* 0x000fe200078e00ff */
/*00c0*/ BSSY B0, 0x370 ; /* 0x000002a000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff057424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe400078e00ff */
/*0100*/ DFMA R4, R2, R4, 6.75539944105574400000e+15 ; /* 0x433800000204742b */
/* 0x004e220000000004 */
/*0110*/ FSETP.GEU.AND P0, PT, |R3|, 4.1917929649353027344, PT ; /* 0x4086232b0300780b */
/* 0x000fca0003f0e200 */
/*0120*/ DADD R8, R4, -6.75539944105574400000e+15 ; /* 0xc338000004087429 */
/* 0x001e0c0000000000 */
/*0130*/ DFMA R10, R8, c[0x2][0x0], R2 ; /* 0x00800000080a7a2b */
/* 0x001e0c0000000002 */
/*0140*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000000a */
/*0150*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x001624000000000c */
/*0160*/ MUFU.RCP64H R13, R7 ; /* 0x00000007000d7308 */
/* 0x008e620000001800 */
/*0170*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fc600078e00ff */
/*0180*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x001e0c000000000a */
/*0190*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x001e0c000000000a */
/*01a0*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x001e08000000000a */
/*01b0*/ DFMA R14, -R6, R12, 1 ; /* 0x3ff00000060e742b */
/* 0x002e48000000010c */
/*01c0*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x001e08000000000a */
/*01d0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x002e48000000000e */
/*01e0*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x001e08000000000a */
/*01f0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x002fc8000000000c */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x001e0c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x001e0c000000000a */
/*0230*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000000a */
/*0240*/ DFMA R12, R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001fc8000000000a */
/*0250*/ DFMA R8, -R6, R14, 1 ; /* 0x3ff000000608742b */
/* 0x000e0c000000010e */
/*0260*/ DFMA R8, R14, R8, R14 ; /* 0x000000080e08722b */
/* 0x001062000000000e */
/*0270*/ IMAD R11, R4, 0x100000, R13 ; /* 0x00100000040b7824 */
/* 0x000fe400078e020d */
/*0280*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0290*/ @!P0 BRA 0x360 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GEU.AND P1, PT, |R3|, 4.2275390625, PT ; /* 0x408748000300780b */
/* 0x003fe20003f2e200 */
/*02b0*/ DADD R10, R2, +INF ; /* 0x7ff00000020a7429 */
/* 0x000fc80000000000 */
/*02c0*/ DSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e0c0003f0e000 */
/*02d0*/ FSEL R10, R10, RZ, P0 ; /* 0x000000ff0a0a7208 */
/* 0x001fe40000000000 */
/*02e0*/ @!P1 LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404059211 */
/* 0x000fe400078f08ff */
/*02f0*/ FSEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7208 */
/* 0x000fe40000000000 */
/*0300*/ @!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff059819 */
/* 0x000fca0000011405 */
/*0310*/ @!P1 IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104029824 */
/* 0x000fe400078e0a05 */
/*0320*/ @!P1 IMAD R13, R5, 0x100000, R13 ; /* 0x00100000050d9824 */
/* 0x000fc600078e020d */
/*0330*/ @!P1 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff0000002039811 */
/* 0x000fe200078ea0ff */
/*0340*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff029224 */
/* 0x000fcc00078e00ff */
/*0350*/ @!P1 DMUL R10, R12, R2 ; /* 0x000000020c0a9228 */
/* 0x00004c0000000000 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*0370*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*0380*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fe20003f2e200 */
/*0390*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*03a0*/ BSSY B0, 0x460 ; /* 0x000000b000007945 */
/* 0x000fea0003800000 */
/*03b0*/ DMUL R2, R8, R4 ; /* 0x0000000408027228 */
/* 0x000e0c0000000000 */
/*03c0*/ DFMA R4, -R6, R2, R4 ; /* 0x000000020604722b */
/* 0x001e0c0000000104 */
/*03d0*/ DFMA R2, R8, R4, R2 ; /* 0x000000040802722b */
/* 0x001e140000000002 */
/*03e0*/ FFMA R4, RZ, R7, R3 ; /* 0x00000007ff047223 */
/* 0x001fca0000000003 */
/*03f0*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0400*/ @P0 BRA P1, 0x450 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0420*/ MOV R10, 0x450 ; /* 0x00000450000a7802 */
/* 0x000fe20000000f00 */
/*0430*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0440*/ CALL.REL.NOINC 0x4a0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ LEA R4, P0, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000047a11 */
/* 0x000fc800078018ff */
/*0470*/ LEA.HI.X R5, R0, c[0x0][0x174], RZ, 0x3, P0 ; /* 0x00005d0000057a11 */
/* 0x000fca00000f1cff */
/*0480*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*04b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*04c0*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*04e0*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*04f0*/ BSSY B1, 0xa30 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0500*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0510*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0520*/ LOP3.LUT R11, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030b7812 */
/* 0x000fe400078ec0ff */
/*0530*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*0540*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*0550*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0560*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0570*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0580*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0590*/ MUFU.RCP64H R15, R5 ; /* 0x00000005000f7308 */
/* 0x001e220000001800 */
/*05a0*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*05b0*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*05c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*05d0*/ LOP3.LUT R9, R9, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef803 */
/*05e0*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*05f0*/ @!P0 LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005108812 */
/* 0x000fe400078ec0ff */
/*0600*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R3, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef803 */
/*0610*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0620*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*0630*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000804 */
/*0640*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0650*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0660*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0670*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0680*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0690*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000804 */
/*06a0*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*06b0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*06c0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*06d0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*06e0*/ DFMA R20, R18, -R4, R8 ; /* 0x800000041214722b */
/* 0x001e0c0000000008 */
/*06f0*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0700*/ @P0 BRA 0x8d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0720*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0730*/ IMAD.IADD R2, R11, 0x1, -R16 ; /* 0x000000010b027824 */
/* 0x000fc600078e0a10 */
/*0740*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0750*/ IMNMX R2, R2, -0x46a00000, !PT ; /* 0xb960000002027817 */
/* 0x000fc80007800200 */
/*0760*/ IMNMX R2, R2, 0x46a00000, PT ; /* 0x46a0000002027817 */
/* 0x000fca0003800200 */
/*0770*/ IMAD.IADD R11, R2, 0x1, -R11 ; /* 0x00000001020b7824 */
/* 0x000fe400078e0a0b */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0790*/ IADD3 R3, R11, 0x7fe00000, RZ ; /* 0x7fe000000b037810 */
/* 0x000fcc0007ffe0ff */
/*07a0*/ DMUL R12, R14, R2 ; /* 0x000000020e0c7228 */
/* 0x002e540000000000 */
/*07b0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*07c0*/ @P0 BRA 0xa20 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*07d0*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e620000000008 */
/*07e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*07f0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x042fe40003f0d000 */
/*0800*/ LOP3.LUT R7, R5, 0x80000000, R7, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4807 */
/*0810*/ LOP3.LUT R3, R7, R3, RZ, 0xfc, !PT ; /* 0x0000000307037212 */
/* 0x000fce00078efcff */
/*0820*/ @!P0 BRA 0xa20 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV R5, RZ, RZ, -R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a0b */
/*0840*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e620000008000 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0860*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e86000000000e */
/*0870*/ LOP3.LUT R7, R3, R7, RZ, 0x3c, !PT ; /* 0x0000000703077212 */
/* 0x002fc600078e3cff */
/*0880*/ IADD3 R4, -R11, -0x43300000, RZ ; /* 0xbcd000000b047810 */
/* 0x004fc80007ffe1ff */
/*0890*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*08a0*/ FSEL R12, R2, R12, !P0 ; /* 0x0000000c020c7208 */
/* 0x000fe40004000000 */
/*08b0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*08c0*/ BRA 0xa20 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*08d0*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*08e0*/ @P0 BRA 0xa00 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*08f0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0900*/ @P0 BRA 0x9d0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0910*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0920*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0930*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0940*/ @!P0 BRA 0xa20 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0960*/ LOP3.LUT R13, R3, 0x80000000, R7, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fe400078e4807 */
/*0970*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0980*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0990*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*09a0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*09b0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*09c0*/ BRA 0xa20 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*09e0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*09f0*/ BRA 0xa20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a00*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x000fe200078efcff */
/*0a10*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*0a20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0a40*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fc400078e000c */
/*0a50*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0a60*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff5900a007950 */
/* 0x000fec0003c3ffff */
/*0a70*/ BRA 0xa70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3sumPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fe40000000f00 */
/*0090*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe20003f26070 */
/*00b0*/ STS.64 [R0.X8], R2 ; /* 0x0000000200007388 */
/* 0x0041e80000008a00 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P1 BRA 0x2c0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD.SHL.U32 R6, R0, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x000fd200078e00ff */
/*0100*/ IMAD.SHL.U32 R8, R5, 0x2, RZ ; /* 0x0000000205087824 */
/* 0x000fc800078e00ff */
/*0110*/ I2F.U32.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x000e620000209000 */
/*0120*/ IADD3 R7, RZ, -R8, RZ ; /* 0x80000008ff077210 */
/* 0x000fe40007ffe0ff */
/*0130*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fca0003f45070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x003fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x002fc800078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R3, R8, R3, R0 ; /* 0x0000000308037224 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103031824 */
/* 0x000fca00078e0a08 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IADD3 R3, -R8, R3, RZ ; /* 0x0000000308031210 */
/* 0x000fe40007ffe1ff */
/*0210*/ @!P2 LOP3.LUT R3, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff03a212 */
/* 0x000fc800078e33ff */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @!P1 IMAD R4, R5, 0x8, R6 ; /* 0x0000000805049824 */
/* 0x000fe200078e0206 */
/*0240*/ @!P1 LDS.64 R2, [R0.X8] ; /* 0x0000000000029984 */
/* 0x000fea0000008a00 */
/*0250*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0260*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x0010640000000004 */
/*0270*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x001fca0000000f00 */
/*0280*/ @!P1 STS.64 [R0.X8], R2 ; /* 0x0000000200009388 */
/* 0x0021e80000008a00 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f26070 */
/*02b0*/ @!P1 BRA 0x100 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ LDS.64 R2, [RZ] ; /* 0x00000000ff027984 */
/* 0x001e220000000a00 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*02f0*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*0300*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3expPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x652b82fe ; /* 0x652b82feff047424 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 1.9912109375, 0.00128841400146484375 ; /* 0x3ff71547ff057435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0a7424 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x2f0 ; /* 0x0000023000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0b7424 */
/* 0x000fc600078e00ff */
/*00d0*/ DFMA R4, R2, R4, 6.75539944105574400000e+15 ; /* 0x433800000204742b */
/* 0x004e220000000004 */
/*00e0*/ FSETP.GEU.AND P0, PT, |R3|, 4.1917929649353027344, PT ; /* 0x4086232b0300780b */
/* 0x000fca0003f0e200 */
/*00f0*/ DADD R6, R4, -6.75539944105574400000e+15 ; /* 0xc338000004067429 */
/* 0x001e0c0000000000 */
/*0100*/ DFMA R8, R6, c[0x2][0x0], R2 ; /* 0x0080000006087a2b */
/* 0x001e0c0000000002 */
/*0110*/ DFMA R6, R6, c[0x2][0x8], R8 ; /* 0x0080020006067a2b */
/* 0x001e0c0000000008 */
/*0120*/ DFMA R8, R6, R10, c[0x2][0x10] ; /* 0x008004000608762b */
/* 0x001064000000000a */
/*0130*/ LEA R10, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a00000a7a11 */
/* 0x001fc800078218ff */
/*0140*/ DFMA R8, R6, R8, c[0x2][0x18] ; /* 0x008006000608762b */
/* 0x002e220000000008 */
/*0150*/ LEA.HI.X R11, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b00000b7a11 */
/* 0x000fca00008f1cff */
/*0160*/ DFMA R8, R6, R8, c[0x2][0x20] ; /* 0x008008000608762b */
/* 0x001e0c0000000008 */
/*0170*/ DFMA R8, R6, R8, c[0x2][0x28] ; /* 0x00800a000608762b */
/* 0x001e0c0000000008 */
/*0180*/ DFMA R8, R6, R8, c[0x2][0x30] ; /* 0x00800c000608762b */
/* 0x001e0c0000000008 */
/*0190*/ DFMA R8, R6, R8, c[0x2][0x38] ; /* 0x00800e000608762b */
/* 0x001e0c0000000008 */
/*01a0*/ DFMA R8, R6, R8, c[0x2][0x40] ; /* 0x008010000608762b */
/* 0x001e0c0000000008 */
/*01b0*/ DFMA R8, R6, R8, c[0x2][0x48] ; /* 0x008012000608762b */
/* 0x001e0c0000000008 */
/*01c0*/ DFMA R8, R6, R8, c[0x2][0x50] ; /* 0x008014000608762b */
/* 0x001e0c0000000008 */
/*01d0*/ DFMA R8, R6, R8, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000008 */
/*01e0*/ DFMA R8, R6, R8, 1 ; /* 0x3ff000000608742b */
/* 0x001e140000000008 */
/*01f0*/ LEA R7, R4, R9, 0x14 ; /* 0x0000000904077211 */
/* 0x001fe200078ea0ff */
/*0200*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0210*/ @!P0 BRA 0x2e0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.AND P1, PT, |R3|, 4.2275390625, PT ; /* 0x408748000300780b */
/* 0x000fe20003f2e200 */
/*0230*/ DADD R6, R2, +INF ; /* 0x7ff0000002067429 */
/* 0x000fc80000000000 */
/*0240*/ DSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e0c0003f0e000 */
/*0250*/ FSEL R6, R6, RZ, P0 ; /* 0x000000ff06067208 */
/* 0x001fe40000000000 */
/*0260*/ @!P1 LEA.HI R0, R4, R4, RZ, 0x1 ; /* 0x0000000404009211 */
/* 0x000fe400078f08ff */
/*0270*/ FSEL R7, R7, RZ, P0 ; /* 0x000000ff07077208 */
/* 0x000fe40000000000 */
/*0280*/ @!P1 SHF.R.S32.HI R3, RZ, 0x1, R0 ; /* 0x00000001ff039819 */
/* 0x000fc80000011400 */
/*0290*/ @!P1 LEA R9, R3, R9, 0x14 ; /* 0x0000000903099211 */
/* 0x000fe200078ea0ff */
/*02a0*/ @!P1 IMAD.IADD R2, R4, 0x1, -R3 ; /* 0x0000000104029824 */
/* 0x000fca00078e0a03 */
/*02b0*/ @!P1 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff0000002039811 */
/* 0x000fe200078ea0ff */
/*02c0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff029224 */
/* 0x000fcc00078e00ff */
/*02d0*/ @!P1 DMUL R6, R8, R2 ; /* 0x0000000208069228 */
/* 0x00004c0000000000 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ STG.E.64 [R10.64], R6 ; /* 0x000000060a007986 */
/* 0x002fe2000c101b04 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
cudaMalloc((void**)&d_in, size);
cudaMalloc((void**)&d_exp, size);
cudaMalloc((void**)&d_sum, sizeof(double));
cudaMalloc((void**)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
cudaMemcpy(h_out, d_exp, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_exp);
cudaFree(d_sum);
cudaFree(d_out);
return EXIT_SUCCESS;
} | .file "tmpxft_001b3e8d_00000000-6_softmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3expPdS_PdS_
.type _Z24__device_stub__Z3expPdS_PdS_, @function
_Z24__device_stub__Z3expPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3expPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3expPdS_PdS_, .-_Z24__device_stub__Z3expPdS_PdS_
.globl _Z3expPdS_
.type _Z3expPdS_, @function
_Z3expPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3expPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3expPdS_, .-_Z3expPdS_
.globl _Z24__device_stub__Z3sumPdS_PdS_
.type _Z24__device_stub__Z3sumPdS_PdS_, @function
_Z24__device_stub__Z3sumPdS_PdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z3sumPdS_PdS_, .-_Z24__device_stub__Z3sumPdS_PdS_
.globl _Z3sumPdS_
.type _Z3sumPdS_, @function
_Z3sumPdS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3sumPdS_, .-_Z3sumPdS_
.globl _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
.type _Z30__device_stub__Z7softmaxPdS_S_PdS_S_, @function
_Z30__device_stub__Z7softmaxPdS_S_PdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7softmaxPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z7softmaxPdS_S_PdS_S_, .-_Z30__device_stub__Z7softmaxPdS_S_PdS_S_
.globl _Z7softmaxPdS_S_
.type _Z7softmaxPdS_S_, @function
_Z7softmaxPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7softmaxPdS_S_, .-_Z7softmaxPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "h_in[%d] = %f"
.LC2:
.string "exp[%d]=%f"
.LC3:
.string "softmax[%d]=%f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L28:
movl %ebx, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, (%r12,%rbx,8)
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L28
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L29:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r13
.L30:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L30
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L31:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L32:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %r13
.L33:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L33
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z24__device_stub__Z3expPdS_PdS_
jmp .L29
.L40:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3sumPdS_PdS_
jmp .L31
.L41:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
jmp .L32
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7softmaxPdS_S_"
.LC5:
.string "_Z3sumPdS_"
.LC6:
.string "_Z3expPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7softmaxPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3expPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1068498944
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
cudaMalloc((void**)&d_in, size);
cudaMalloc((void**)&d_exp, size);
cudaMalloc((void**)&d_sum, sizeof(double));
cudaMalloc((void**)&d_out, size);
cudaMemcpy(d_in, h_in, size, cudaMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
cudaMemcpy(h_out, d_exp, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
cudaMemcpy(h_out, d_out, size, cudaMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_exp);
cudaFree(d_sum);
cudaFree(d_out);
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
hipMalloc((void**)&d_in, size);
hipMalloc((void**)&d_exp, size);
hipMalloc((void**)&d_sum, sizeof(double));
hipMalloc((void**)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
hipMemcpy(h_out, d_exp, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_exp);
hipFree(d_sum);
hipFree(d_out);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
hipMalloc((void**)&d_in, size);
hipMalloc((void**)&d_exp, size);
hipMalloc((void**)&d_sum, sizeof(double));
hipMalloc((void**)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
hipMemcpy(h_out, d_exp, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_exp);
hipFree(d_sum);
hipFree(d_out);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3expPdS_
.globl _Z3expPdS_
.p2align 8
.type _Z3expPdS_,@function
_Z3expPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s5, 0x3e5ade15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, 0x6a5dcb37
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[4:5], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_cndmask_b32_e64 v3, 0, v5, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3expPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3expPdS_, .Lfunc_end0-_Z3expPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPdS_
.globl _Z3sumPdS_
.p2align 8
.type _Z3sumPdS_,@function
_Z3sumPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s2, 2
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[2:3], v[1:2], off
v_lshl_add_u32 v1, v0, 3, 0
s_waitcnt vmcnt(0)
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_mov_b32 s4, 1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_ge_u32 s3, s2
s_mov_b32 s4, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
.LBB1_3:
s_lshl_b32 s3, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s3, -1
v_and_b32_e32 v2, s5, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 3, 0
ds_load_b64 v[2:3], v2
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_branch .LBB1_2
.LBB1_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3sumPdS_, .Lfunc_end1-_Z3sumPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7softmaxPdS_S_
.globl _Z7softmaxPdS_S_
.p2align 8
.type _Z7softmaxPdS_S_,@function
_Z7softmaxPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[4:5], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_load_b64 s[4:5], s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_cndmask_b32_e64 v3, 0, v5, s0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[4:5], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7softmaxPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7softmaxPdS_S_, .Lfunc_end2-_Z7softmaxPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3expPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3expPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7softmaxPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7softmaxPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
const double N = 16;
__global__
void exp(double* d_in, double *d_exp)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: exp(xi)
d_exp[idx] = exp(d_in[idx]);
}
__global__
void sum(double *d_exp, double *d_sum)
{
// reduction function: sum(exp(x))
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned tid = threadIdx.x;
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = d_exp[idx];
__syncthreads();
// do reduction in shared mem
for (unsigned s=1; s < blockDim.x; s *= 2) {
if (tid % (2*s) == 0) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result to global mem
if (tid == 0) *d_sum = sdata[0];
}
__global__
void softmax(double* d_in, double *d_sum, double *d_out)
{
unsigned idx = blockIdx.x * blockDim.x + threadIdx.x;
// map function: softmax(xi) = exp(xi)/sum
d_out[idx] = exp(d_in[idx])/(*d_sum);
}
int main()
{
double *h_in;
double *d_in, *d_exp, *d_sum, *d_out, *h_out;
const int size = N*sizeof(double);
h_in = (double*)malloc(size);
h_out = (double*)malloc(size);
for (int ii = 0; ii < N; ii++) {
h_in[ii] = ii/N;
printf("h_in[%d] = %f", ii, h_in[ii]);
}
hipMalloc((void**)&d_in, size);
hipMalloc((void**)&d_exp, size);
hipMalloc((void**)&d_sum, sizeof(double));
hipMalloc((void**)&d_out, size);
hipMemcpy(d_in, h_in, size, hipMemcpyHostToDevice);
// softmax: f(xi) = exp(xi)/sum(exp(x))
dim3 dimBlock(N, 1);
dim3 dimGrid(N, 1);
exp<<<dimGrid, dimBlock>>>(d_in, d_exp);
hipMemcpy(h_out, d_exp, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("exp[%d]=%f", ii, h_out[ii]);
sum<<<dimGrid, dimBlock>>>(d_exp, d_sum);
softmax<<<dimGrid, dimBlock>>>(d_in, d_sum, d_out);
hipMemcpy(h_out, d_out, size, hipMemcpyDeviceToHost);
for (int ii = 0; ii < N; ii++)
printf("softmax[%d]=%f", ii, h_out[ii]);
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_exp);
hipFree(d_sum);
hipFree(d_out);
return EXIT_SUCCESS;
} | .text
.file "softmax.hip"
.globl _Z18__device_stub__expPdS_ # -- Begin function _Z18__device_stub__expPdS_
.p2align 4, 0x90
.type _Z18__device_stub__expPdS_,@function
_Z18__device_stub__expPdS_: # @_Z18__device_stub__expPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3expPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__expPdS_, .Lfunc_end0-_Z18__device_stub__expPdS_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPdS_ # -- Begin function _Z18__device_stub__sumPdS_
.p2align 4, 0x90
.type _Z18__device_stub__sumPdS_,@function
_Z18__device_stub__sumPdS_: # @_Z18__device_stub__sumPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__sumPdS_, .Lfunc_end1-_Z18__device_stub__sumPdS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__softmaxPdS_S_ # -- Begin function _Z22__device_stub__softmaxPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__softmaxPdS_S_,@function
_Z22__device_stub__softmaxPdS_S_: # @_Z22__device_stub__softmaxPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7softmaxPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__softmaxPdS_S_, .Lfunc_end2-_Z22__device_stub__softmaxPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_1
# %bb.2:
movabsq $4294967312, %r15 # imm = 0x100000010
leaq 72(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 88(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 72(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3expPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 64(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movl %r12d, %esi
movb $1, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB3_5
# %bb.6:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 64(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 72(%rsp), %rax
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rsp, %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7softmaxPdS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 80(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_11: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_11
# %bb.12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3expPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7softmaxPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3expPdS_,@object # @_Z3expPdS_
.section .rodata,"a",@progbits
.globl _Z3expPdS_
.p2align 3, 0x0
_Z3expPdS_:
.quad _Z18__device_stub__expPdS_
.size _Z3expPdS_, 8
.type _Z3sumPdS_,@object # @_Z3sumPdS_
.globl _Z3sumPdS_
.p2align 3, 0x0
_Z3sumPdS_:
.quad _Z18__device_stub__sumPdS_
.size _Z3sumPdS_, 8
.type _Z7softmaxPdS_S_,@object # @_Z7softmaxPdS_S_
.globl _Z7softmaxPdS_S_
.p2align 3, 0x0
_Z7softmaxPdS_S_:
.quad _Z22__device_stub__softmaxPdS_S_
.size _Z7softmaxPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_in[%d] = %f"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "exp[%d]=%f"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "softmax[%d]=%f"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3expPdS_"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3sumPdS_"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7softmaxPdS_S_"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__expPdS_
.addrsig_sym _Z18__device_stub__sumPdS_
.addrsig_sym _Z22__device_stub__softmaxPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3expPdS_
.addrsig_sym _Z3sumPdS_
.addrsig_sym _Z7softmaxPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b3e8d_00000000-6_softmax.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3expPdS_PdS_
.type _Z24__device_stub__Z3expPdS_PdS_, @function
_Z24__device_stub__Z3expPdS_PdS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3expPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3expPdS_PdS_, .-_Z24__device_stub__Z3expPdS_PdS_
.globl _Z3expPdS_
.type _Z3expPdS_, @function
_Z3expPdS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3expPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3expPdS_, .-_Z3expPdS_
.globl _Z24__device_stub__Z3sumPdS_PdS_
.type _Z24__device_stub__Z3sumPdS_PdS_, @function
_Z24__device_stub__Z3sumPdS_PdS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z3sumPdS_PdS_, .-_Z24__device_stub__Z3sumPdS_PdS_
.globl _Z3sumPdS_
.type _Z3sumPdS_, @function
_Z3sumPdS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3sumPdS_, .-_Z3sumPdS_
.globl _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
.type _Z30__device_stub__Z7softmaxPdS_S_PdS_S_, @function
_Z30__device_stub__Z7softmaxPdS_S_PdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7softmaxPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z7softmaxPdS_S_PdS_S_, .-_Z30__device_stub__Z7softmaxPdS_S_PdS_S_
.globl _Z7softmaxPdS_S_
.type _Z7softmaxPdS_S_, @function
_Z7softmaxPdS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7softmaxPdS_S_, .-_Z7softmaxPdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "h_in[%d] = %f"
.LC2:
.string "exp[%d]=%f"
.LC3:
.string "softmax[%d]=%f"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %r12
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L28:
movl %ebx, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, (%r12,%rbx,8)
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L28
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L29:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r13
.L30:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L30
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L31:
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L32:
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %r13
.L33:
movsd 0(%rbp,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L33
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z24__device_stub__Z3expPdS_PdS_
jmp .L29
.L40:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3sumPdS_PdS_
jmp .L31
.L41:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z7softmaxPdS_S_PdS_S_
jmp .L32
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7softmaxPdS_S_"
.LC5:
.string "_Z3sumPdS_"
.LC6:
.string "_Z3expPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7softmaxPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3expPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1068498944
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "softmax.hip"
.globl _Z18__device_stub__expPdS_ # -- Begin function _Z18__device_stub__expPdS_
.p2align 4, 0x90
.type _Z18__device_stub__expPdS_,@function
_Z18__device_stub__expPdS_: # @_Z18__device_stub__expPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3expPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__expPdS_, .Lfunc_end0-_Z18__device_stub__expPdS_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPdS_ # -- Begin function _Z18__device_stub__sumPdS_
.p2align 4, 0x90
.type _Z18__device_stub__sumPdS_,@function
_Z18__device_stub__sumPdS_: # @_Z18__device_stub__sumPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z18__device_stub__sumPdS_, .Lfunc_end1-_Z18__device_stub__sumPdS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__softmaxPdS_S_ # -- Begin function _Z22__device_stub__softmaxPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__softmaxPdS_S_,@function
_Z22__device_stub__softmaxPdS_S_: # @_Z22__device_stub__softmaxPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7softmaxPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__softmaxPdS_S_, .Lfunc_end2-_Z22__device_stub__softmaxPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3fb0000000000000 # double 0.0625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
movl $.L.str, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_1
# %bb.2:
movabsq $4294967312, %r15 # imm = 0x100000010
leaq 72(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 88(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 72(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3expPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 64(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movl %r12d, %esi
movb $1, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB3_5
# %bb.6:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 64(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 72(%rsp), %rax
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 40(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %rsp, %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7softmaxPdS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 80(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_11: # =>This Inner Loop Header: Depth=1
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $16, %r15
jne .LBB3_11
# %bb.12:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3expPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7softmaxPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3expPdS_,@object # @_Z3expPdS_
.section .rodata,"a",@progbits
.globl _Z3expPdS_
.p2align 3, 0x0
_Z3expPdS_:
.quad _Z18__device_stub__expPdS_
.size _Z3expPdS_, 8
.type _Z3sumPdS_,@object # @_Z3sumPdS_
.globl _Z3sumPdS_
.p2align 3, 0x0
_Z3sumPdS_:
.quad _Z18__device_stub__sumPdS_
.size _Z3sumPdS_, 8
.type _Z7softmaxPdS_S_,@object # @_Z7softmaxPdS_S_
.globl _Z7softmaxPdS_S_
.p2align 3, 0x0
_Z7softmaxPdS_S_:
.quad _Z22__device_stub__softmaxPdS_S_
.size _Z7softmaxPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "h_in[%d] = %f"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "exp[%d]=%f"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "softmax[%d]=%f"
.size .L.str.2, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3expPdS_"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3sumPdS_"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7softmaxPdS_S_"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__expPdS_
.addrsig_sym _Z18__device_stub__sumPdS_
.addrsig_sym _Z22__device_stub__softmaxPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3expPdS_
.addrsig_sym _Z3sumPdS_
.addrsig_sym _Z7softmaxPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} | code for sm_80
Function : _Z12matmulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0xc], R2 ; /* 0x0000030009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R9, c[0x0][0x180], R0 ; /* 0x0000600009027a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fce0003f06270 */
/*00f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e020b */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0150*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fd20000000f00 */
/*0170*/ @!P0 BRA 0xcc0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R10, -R8, c[0x0][0x17c], RZ ; /* 0x00005f00080a7a10 */
/* 0x000fe20007ffe1ff */
/*0190*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD R14, R9, c[0x0][0x17c], RZ ; /* 0x00005f00090e7a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020b */
/*01d0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f04270 */
/*01e0*/ MOV R12, c[0x0][0x160] ; /* 0x00005800000c7a02 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R13, c[0x0][0x164] ; /* 0x00005900000d7a02 */
/* 0x000fd20000000f00 */
/*0200*/ @!P0 BRA 0xb00 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0210*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0230*/ @!P1 BRA 0x7d0 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0260*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea2000c1e1900 */
/*0280*/ MOV R17, c[0x0][0x180] ; /* 0x0000600000117a02 */
/* 0x000fe20000000f00 */
/*0290*/ FFMA R23, R16, R18, R19 ; /* 0x0000001210177223 */
/* 0x004fc80000000013 */
/*02a0*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x008fe200078e0204 */
/*02b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*02f0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*0300*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FFMA R27, R4, R5, R25 ; /* 0x00000005041b7223 */
/* 0x008fc40000000019 */
/*0340*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0350*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R22, [R6.64+0xc] ; /* 0x00000c0406167981 */
/* 0x000e62000c1e1900 */
/*0380*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc800078e0204 */
/*0390*/ FFMA R23, R16, R22, R27 ; /* 0x0000001610177223 */
/* 0x002fca000000001b */
/*03a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100406147981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*03e0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*03f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0430*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0440*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R23, R16, R18, R27 ; /* 0x0000001210177223 */
/* 0x002fc4000000001b */
/*0480*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0490*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R20, [R6.64+0x1c] ; /* 0x00001c0406147981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*04d0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*04e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ee4000c1e1900 */
/*0510*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0520*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0530*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R18, [R6.64+0x24] ; /* 0x0000240406127981 */
/* 0x000e64000c1e1900 */
/*0560*/ FFMA R23, R16, R18, R27 ; /* 0x0000001210177223 */
/* 0x002fc4000000001b */
/*0570*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0580*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R20, [R6.64+0x28] ; /* 0x0000280406147981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*05c0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*05d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0610*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0620*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0630*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0640*/ LDG.E R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x000ee4000c1e1900 */
/*0650*/ FFMA R29, R16, R18, R27 ; /* 0x00000012101d7223 */
/* 0x008fc4000000001b */
/*0660*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0670*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R20, [R6.64+0x34] ; /* 0x0000340406147981 */
/* 0x000e64000c1e1900 */
/*06a0*/ FFMA R25, R16, R20, R29 ; /* 0x0000001410197223 */
/* 0x002fc4000000001d */
/*06b0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*06c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IMAD.WIDE R22, R17, 0x4, R20 ; /* 0x0000000411167825 */
/* 0x000fe200078e0214 */
/*0700*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fc60007ffe0ff */
/*0710*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x004fca0000000019 */
/*0720*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0730*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ea2000c1e1900 */
/*0750*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0760*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007f5e0ff */
/*0770*/ IADD3 R15, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0790*/ FFMA R19, R4, R5, R27 ; /* 0x0000000504137223 */
/* 0x004fe4000000001b */
/*07a0*/ IMAD.WIDE R4, R17, 0x4, R22 ; /* 0x0000000411047825 */
/* 0x000fc600078e0216 */
/*07b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e2000c101904 */
/*07c0*/ @P1 BRA 0x250 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07e0*/ @!P1 BRA 0xae0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0800*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea2000c1e1900 */
/*0820*/ MOV R17, c[0x0][0x180] ; /* 0x0000600000117a02 */
/* 0x000fe20000000f00 */
/*0830*/ FFMA R23, R16, R18, R19 ; /* 0x0000001210177223 */
/* 0x004fc80000000013 */
/*0840*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x008fe200078e0204 */
/*0850*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0860*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*0890*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*08a0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*08b0*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee4000c1e1900 */
/*08d0*/ FFMA R27, R4, R5, R25 ; /* 0x00000005041b7223 */
/* 0x008fc40000000019 */
/*08e0*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*08f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0900*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0910*/ LDG.E R22, [R6.64+0xc] ; /* 0x00000c0406167981 */
/* 0x000e62000c1e1900 */
/*0920*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc800078e0204 */
/*0930*/ FFMA R23, R16, R22, R27 ; /* 0x0000001610177223 */
/* 0x002fca000000001b */
/*0940*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100406147981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*0980*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*0990*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*09a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ee4000c1e1900 */
/*09c0*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*09d0*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*09e0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000ee2000c1e1900 */
/*0a10*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x002fc800078e0204 */
/*0a20*/ FFMA R29, R16, R18, R27 ; /* 0x00000012101d7223 */
/* 0x008fca000000001b */
/*0a30*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0005e8000c101904 */
/*0a40*/ LDG.E R19, [R6.64+0x1c] ; /* 0x00001c0406137981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe20007f3e0ff */
/*0a70*/ IMAD.WIDE R4, R17, 0x4, R22 ; /* 0x0000000411047825 */
/* 0x000fe200078e0216 */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a90*/ IADD3 R15, R15, 0x8, RZ ; /* 0x000000080f0f7810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0ac0*/ FFMA R19, R16, R19, R29 ; /* 0x0000001310137223 */
/* 0x008fca000000001d */
/*0ad0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e4000c101904 */
/*0ae0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0af0*/ @!P0 BRA 0xcc0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b00*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0b10*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f28000c1e1900 */
/*0b20*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000f22000c1e1900 */
/*0b30*/ MOV R21, c[0x0][0x180] ; /* 0x0000600000157a02 */
/* 0x000fe20000000f00 */
/*0b40*/ FFMA R19, R16, R17, R19 ; /* 0x0000001110137223 */
/* 0x01cfc80000000013 */
/*0b50*/ IMAD.WIDE R16, R21.reuse, 0x4, R4 ; /* 0x0000000415107825 */
/* 0x040fe200078e0204 */
/*0b60*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ IMAD.WIDE R22, R21, 0x4, R16 ; /* 0x0000000415167825 */
/* 0x000fc800078e0210 */
/*0ba0*/ FFMA R27, R18, R20, R19 ; /* 0x00000014121b7223 */
/* 0x004fca0000000013 */
/*0bb0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0bc0*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ee8000c1e1900 */
/*0bd0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee2000c1e1900 */
/*0be0*/ IMAD.WIDE R24, R21, 0x4, R22 ; /* 0x0000000415187825 */
/* 0x000fe200078e0216 */
/*0bf0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c00*/ FFMA R29, R4, R5, R27 ; /* 0x00000005041d7223 */
/* 0x008fca000000001b */
/*0c10*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0005e8000c101904 */
/*0c20*/ LDG.E R19, [R6.64+0xc] ; /* 0x00000c0406137981 */
/* 0x002ee8000c1e1900 */
/*0c30*/ LDG.E R4, [R24.64] ; /* 0x0000000418047981 */
/* 0x000ee2000c1e1900 */
/*0c40*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0c50*/ IADD3 R12, P1, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007f3e0ff */
/*0c60*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe40007ffe0ff */
/*0c70*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0c80*/ FFMA R19, R4, R19, R29 ; /* 0x0000001304137223 */
/* 0x008fe4000000001d */
/*0c90*/ IMAD.WIDE R4, R21, 0x4, R24 ; /* 0x0000000415047825 */
/* 0x000fc600078e0218 */
/*0ca0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e4000c101904 */
/*0cb0*/ @P0 BRA 0xb00 ; /* 0xfffffe4000000947 */
/* 0x005fea000383ffff */
/*0cc0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cd0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ce0*/ IMAD R4, R9, c[0x0][0x17c], R15 ; /* 0x00005f0009047a24 */
/* 0x000fe400078e020f */
/*0cf0*/ IMAD R0, R15, c[0x0][0x180], R0 ; /* 0x000060000f007a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0d10*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e020b */
/*0d20*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fc80000000f00 */
/*0d30*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0d40*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x00232a000c1e1900 */
/*0d50*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000b22000c1e1900 */
/*0d60*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fc40000000f00 */
/*0d80*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0d90*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0da0*/ IMAD.WIDE R6, R11, 0x4, R6 ; /* 0x000000040b067825 */
/* 0x002fc600078e0206 */
/*0db0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x020fe20000ffe4ff */
/*0dc0*/ FFMA R19, R0, R4, R19 ; /* 0x0000000400137223 */
/* 0x01cfca0000000013 */
/*0dd0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101904 */
/*0de0*/ @P0 BRA 0xd30 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} | .file "tmpxft_0013e47f_00000000-6_matmulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12matmulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
.globl _Z12matmulKernelPfS_S_iii
.type _Z12matmulKernelPfS_S_iii, @function
_Z12matmulKernelPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matmulKernelPfS_S_iii, .-_Z12matmulKernelPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matmulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matmulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matmulKernelPfS_S_iii
.globl _Z12matmulKernelPfS_S_iii
.p2align 8
.type _Z12matmulKernelPfS_S_iii,@function
_Z12matmulKernelPfS_S_iii:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s6, s3, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s2, v1
s_add_i32 s6, s6, s14
s_cmp_lt_i32 s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_cselect_b32 s2, -1, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
v_mad_u64_u32 v[1:2], null, s6, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_cmp_lt_i32 s5, 1
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v5, v[2:3], off
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v4, s[0:1]
global_load_b32 v6, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v1, v6
global_store_b32 v[2:3], v5, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matmulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matmulKernelPfS_S_iii, .Lfunc_end0-_Z12matmulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matmulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matmulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmulKernel(float *A, float *B, float *C, int rA, int cA, int cB){
int i = blockIdx.y*gridDim.x + blockIdx.x, j = threadIdx.y*blockDim.x + threadIdx.x;
if(i < rA && j < cB){
C[i*cB + j] = 0.;
for(int k=0;k<cA;++k) C[i*cB + j] += A[i*cA + k] * B[k*cB + j];
}
return;
} | .text
.file "matmulKernel.hip"
.globl _Z27__device_stub__matmulKernelPfS_S_iii # -- Begin function _Z27__device_stub__matmulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__matmulKernelPfS_S_iii,@function
_Z27__device_stub__matmulKernelPfS_S_iii: # @_Z27__device_stub__matmulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12matmulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__matmulKernelPfS_S_iii, .Lfunc_end0-_Z27__device_stub__matmulKernelPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matmulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matmulKernelPfS_S_iii,@object # @_Z12matmulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12matmulKernelPfS_S_iii
.p2align 3, 0x0
_Z12matmulKernelPfS_S_iii:
.quad _Z27__device_stub__matmulKernelPfS_S_iii
.size _Z12matmulKernelPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matmulKernelPfS_S_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matmulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matmulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matmulKernelPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0xc], R2 ; /* 0x0000030009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R9, c[0x0][0x180], R0 ; /* 0x0000600009027a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fce0003f06270 */
/*00f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e020b */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe40007ffe0ff */
/*0130*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0150*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fd20000000f00 */
/*0170*/ @!P0 BRA 0xcc0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R10, -R8, c[0x0][0x17c], RZ ; /* 0x00005f00080a7a10 */
/* 0x000fe20007ffe1ff */
/*0190*/ HFMA2.MMA R15, -RZ, RZ, 0, 0 ; /* 0x00000000ff0f7435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD R14, R9, c[0x0][0x17c], RZ ; /* 0x00005f00090e7a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020b */
/*01d0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f04270 */
/*01e0*/ MOV R12, c[0x0][0x160] ; /* 0x00005800000c7a02 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R13, c[0x0][0x164] ; /* 0x00005900000d7a02 */
/* 0x000fd20000000f00 */
/*0200*/ @!P0 BRA 0xb00 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*0210*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0230*/ @!P1 BRA 0x7d0 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0250*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0260*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea2000c1e1900 */
/*0280*/ MOV R17, c[0x0][0x180] ; /* 0x0000600000117a02 */
/* 0x000fe20000000f00 */
/*0290*/ FFMA R23, R16, R18, R19 ; /* 0x0000001210177223 */
/* 0x004fc80000000013 */
/*02a0*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x008fe200078e0204 */
/*02b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*02f0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*0300*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FFMA R27, R4, R5, R25 ; /* 0x00000005041b7223 */
/* 0x008fc40000000019 */
/*0340*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0350*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R22, [R6.64+0xc] ; /* 0x00000c0406167981 */
/* 0x000e62000c1e1900 */
/*0380*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc800078e0204 */
/*0390*/ FFMA R23, R16, R22, R27 ; /* 0x0000001610177223 */
/* 0x002fca000000001b */
/*03a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100406147981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*03e0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*03f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0430*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0440*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R23, R16, R18, R27 ; /* 0x0000001210177223 */
/* 0x002fc4000000001b */
/*0480*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0490*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R20, [R6.64+0x1c] ; /* 0x00001c0406147981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*04d0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*04e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ee4000c1e1900 */
/*0510*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0520*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0530*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R18, [R6.64+0x24] ; /* 0x0000240406127981 */
/* 0x000e64000c1e1900 */
/*0560*/ FFMA R23, R16, R18, R27 ; /* 0x0000001210177223 */
/* 0x002fc4000000001b */
/*0570*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0580*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R20, [R6.64+0x28] ; /* 0x0000280406147981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*05c0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*05d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*0610*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*0620*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0630*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0640*/ LDG.E R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x000ee4000c1e1900 */
/*0650*/ FFMA R29, R16, R18, R27 ; /* 0x00000012101d7223 */
/* 0x008fc4000000001b */
/*0660*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc600078e0204 */
/*0670*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R20, [R6.64+0x34] ; /* 0x0000340406147981 */
/* 0x000e64000c1e1900 */
/*06a0*/ FFMA R25, R16, R20, R29 ; /* 0x0000001410197223 */
/* 0x002fc4000000001d */
/*06b0*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*06c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IMAD.WIDE R22, R17, 0x4, R20 ; /* 0x0000000411167825 */
/* 0x000fe200078e0214 */
/*0700*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fc60007ffe0ff */
/*0710*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x004fca0000000019 */
/*0720*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0730*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ea2000c1e1900 */
/*0750*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0760*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x000fc40007f5e0ff */
/*0770*/ IADD3 R15, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0790*/ FFMA R19, R4, R5, R27 ; /* 0x0000000504137223 */
/* 0x004fe4000000001b */
/*07a0*/ IMAD.WIDE R4, R17, 0x4, R22 ; /* 0x0000000411047825 */
/* 0x000fc600078e0216 */
/*07b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0007e2000c101904 */
/*07c0*/ @P1 BRA 0x250 ; /* 0xfffffa8000001947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07e0*/ @!P1 BRA 0xae0 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0800*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea2000c1e1900 */
/*0820*/ MOV R17, c[0x0][0x180] ; /* 0x0000600000117a02 */
/* 0x000fe20000000f00 */
/*0830*/ FFMA R23, R16, R18, R19 ; /* 0x0000001210177223 */
/* 0x004fc80000000013 */
/*0840*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x008fe200078e0204 */
/*0850*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0860*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*0890*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*08a0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*08b0*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee8000c1e1900 */
/*08c0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee4000c1e1900 */
/*08d0*/ FFMA R27, R4, R5, R25 ; /* 0x00000005041b7223 */
/* 0x008fc40000000019 */
/*08e0*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*08f0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0007e8000c101904 */
/*0900*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000e68000c1e1900 */
/*0910*/ LDG.E R22, [R6.64+0xc] ; /* 0x00000c0406167981 */
/* 0x000e62000c1e1900 */
/*0920*/ IMAD.WIDE R18, R17, 0x4, R4 ; /* 0x0000000411127825 */
/* 0x000fc800078e0204 */
/*0930*/ FFMA R23, R16, R22, R27 ; /* 0x0000001610177223 */
/* 0x002fca000000001b */
/*0940*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R20, [R6.64+0x10] ; /* 0x0000100406147981 */
/* 0x000ea4000c1e1900 */
/*0970*/ FFMA R25, R16, R20, R23 ; /* 0x0000001410197223 */
/* 0x004fc40000000017 */
/*0980*/ IMAD.WIDE R20, R17, 0x4, R18 ; /* 0x0000000411147825 */
/* 0x000fc600078e0212 */
/*0990*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*09a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ee4000c1e1900 */
/*09c0*/ FFMA R27, R16, R4, R25 ; /* 0x00000004101b7223 */
/* 0x008fc40000000019 */
/*09d0*/ IMAD.WIDE R4, R17, 0x4, R20 ; /* 0x0000000411047825 */
/* 0x000fc600078e0214 */
/*09e0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x000ee2000c1e1900 */
/*0a10*/ IMAD.WIDE R22, R17, 0x4, R4 ; /* 0x0000000411167825 */
/* 0x002fc800078e0204 */
/*0a20*/ FFMA R29, R16, R18, R27 ; /* 0x00000012101d7223 */
/* 0x008fca000000001b */
/*0a30*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0005e8000c101904 */
/*0a40*/ LDG.E R19, [R6.64+0x1c] ; /* 0x00001c0406137981 */
/* 0x000ee8000c1e1900 */
/*0a50*/ LDG.E R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ee2000c1e1900 */
/*0a60*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe20007f3e0ff */
/*0a70*/ IMAD.WIDE R4, R17, 0x4, R22 ; /* 0x0000000411047825 */
/* 0x000fe200078e0216 */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a90*/ IADD3 R15, R15, 0x8, RZ ; /* 0x000000080f0f7810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0ac0*/ FFMA R19, R16, R19, R29 ; /* 0x0000001310137223 */
/* 0x008fca000000001d */
/*0ad0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e4000c101904 */
/*0ae0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0af0*/ @!P0 BRA 0xcc0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0b00*/ IMAD.WIDE R6, R14, 0x4, R12 ; /* 0x000000040e067825 */
/* 0x000fe200078e020c */
/*0b10*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f28000c1e1900 */
/*0b20*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000f22000c1e1900 */
/*0b30*/ MOV R21, c[0x0][0x180] ; /* 0x0000600000157a02 */
/* 0x000fe20000000f00 */
/*0b40*/ FFMA R19, R16, R17, R19 ; /* 0x0000001110137223 */
/* 0x01cfc80000000013 */
/*0b50*/ IMAD.WIDE R16, R21.reuse, 0x4, R4 ; /* 0x0000000415107825 */
/* 0x040fe200078e0204 */
/*0b60*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ IMAD.WIDE R22, R21, 0x4, R16 ; /* 0x0000000415167825 */
/* 0x000fc800078e0210 */
/*0ba0*/ FFMA R27, R18, R20, R19 ; /* 0x00000014121b7223 */
/* 0x004fca0000000013 */
/*0bb0*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0bc0*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ee8000c1e1900 */
/*0bd0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ee2000c1e1900 */
/*0be0*/ IMAD.WIDE R24, R21, 0x4, R22 ; /* 0x0000000415187825 */
/* 0x000fe200078e0216 */
/*0bf0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c00*/ FFMA R29, R4, R5, R27 ; /* 0x00000005041d7223 */
/* 0x008fca000000001b */
/*0c10*/ STG.E [R2.64], R29 ; /* 0x0000001d02007986 */
/* 0x0005e8000c101904 */
/*0c20*/ LDG.E R19, [R6.64+0xc] ; /* 0x00000c0406137981 */
/* 0x002ee8000c1e1900 */
/*0c30*/ LDG.E R4, [R24.64] ; /* 0x0000000418047981 */
/* 0x000ee2000c1e1900 */
/*0c40*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0c50*/ IADD3 R12, P1, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007f3e0ff */
/*0c60*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe40007ffe0ff */
/*0c70*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe20000ffe4ff */
/*0c80*/ FFMA R19, R4, R19, R29 ; /* 0x0000001304137223 */
/* 0x008fe4000000001d */
/*0c90*/ IMAD.WIDE R4, R21, 0x4, R24 ; /* 0x0000000415047825 */
/* 0x000fc600078e0218 */
/*0ca0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e4000c101904 */
/*0cb0*/ @P0 BRA 0xb00 ; /* 0xfffffe4000000947 */
/* 0x005fea000383ffff */
/*0cc0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cd0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ce0*/ IMAD R4, R9, c[0x0][0x17c], R15 ; /* 0x00005f0009047a24 */
/* 0x000fe400078e020f */
/*0cf0*/ IMAD R0, R15, c[0x0][0x180], R0 ; /* 0x000060000f007a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0d10*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e020b */
/*0d20*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fc80000000f00 */
/*0d30*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0d40*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x00232a000c1e1900 */
/*0d50*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000b22000c1e1900 */
/*0d60*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fc40000000f00 */
/*0d80*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0d90*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0da0*/ IMAD.WIDE R6, R11, 0x4, R6 ; /* 0x000000040b067825 */
/* 0x002fc600078e0206 */
/*0db0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x020fe20000ffe4ff */
/*0dc0*/ FFMA R19, R0, R4, R19 ; /* 0x0000000400137223 */
/* 0x01cfca0000000013 */
/*0dd0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e2000c101904 */
/*0de0*/ @P0 BRA 0xd30 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matmulKernelPfS_S_iii
.globl _Z12matmulKernelPfS_S_iii
.p2align 8
.type _Z12matmulKernelPfS_S_iii,@function
_Z12matmulKernelPfS_S_iii:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s6, s3, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s2, v1
s_add_i32 s6, s6, s14
s_cmp_lt_i32 s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_cselect_b32 s2, -1, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x1c
v_mad_u64_u32 v[1:2], null, s6, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_cmp_lt_i32 s5, 1
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v5, v[2:3], off
s_load_b128 s[0:3], s[0:1], 0x0
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v4, s[0:1]
global_load_b32 v6, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, v1, v6
global_store_b32 v[2:3], v5, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matmulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matmulKernelPfS_S_iii, .Lfunc_end0-_Z12matmulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matmulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matmulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e47f_00000000-6_matmulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
.type _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii, @function
_Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12matmulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii, .-_Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
.globl _Z12matmulKernelPfS_S_iii
.type _Z12matmulKernelPfS_S_iii, @function
_Z12matmulKernelPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12matmulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matmulKernelPfS_S_iii, .-_Z12matmulKernelPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matmulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matmulKernelPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmulKernel.hip"
.globl _Z27__device_stub__matmulKernelPfS_S_iii # -- Begin function _Z27__device_stub__matmulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z27__device_stub__matmulKernelPfS_S_iii,@function
_Z27__device_stub__matmulKernelPfS_S_iii: # @_Z27__device_stub__matmulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12matmulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__matmulKernelPfS_S_iii, .Lfunc_end0-_Z27__device_stub__matmulKernelPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matmulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matmulKernelPfS_S_iii,@object # @_Z12matmulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z12matmulKernelPfS_S_iii
.p2align 3, 0x0
_Z12matmulKernelPfS_S_iii:
.quad _Z27__device_stub__matmulKernelPfS_S_iii
.size _Z12matmulKernelPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matmulKernelPfS_S_iii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matmulKernelPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matmulKernelPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <error.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <cuda_runtime.h>
#define DEVICE_NUMBER (0)
typedef struct {
int nofThreads;
int nofBlocks;
int32_t nof_repetitions;
int data_size;
int buffer_length;
unsigned int *targetMeasOH;
unsigned int hostMeasOH;
int *hostBuffer;
int *targetBuffer;
uint64_t *target_realSum;
uint64_t host_realSum;
unsigned int *target_times;
unsigned int *host_times;
FILE *fd;
} param_t;
// Prints a message and returns zero if the given value is not cudaSuccess
#define CheckCUDAError(val) (InternalCheckCUDAError((val), #val, __FILE__, __LINE__))
// Called internally by CheckCUDAError
static int InternalCheckCUDAError(cudaError_t result, const char *fn,
const char *file, int line) {
if (result == cudaSuccess) return 0;
printf("CUDA error %d in %s, line %d (%s): %s\n", (int) result, file, line,
fn, cudaGetErrorString(result));
return -1;
}
static void createSequentialArrayHost(param_t params){
// Link sequentially
for(int i = 0; i < params.buffer_length; i++){
params.hostBuffer[i]=(i+params.nofThreads*params.nofBlocks)%params.buffer_length;
}
}
static __global__ void getMeasurementOverhead(param_t params) {
unsigned int start, stop;
uint64_t sum = 0;
start = clock();
for (int j = 0; j < params.buffer_length; j++){
sum +=j;
}
stop = clock();
*params.targetMeasOH = (stop-start)/params.buffer_length;
*params.target_realSum = sum;
}
static __global__ void sequentialWalk(param_t params) {
int current;
unsigned int time_start, time_end, time_acc;
uint64_t sum;
int tindex = blockDim.x*blockIdx.x*params.nof_repetitions + params.nof_repetitions *threadIdx.x;
// Warm up data cache
for(int i = 0; i < params.buffer_length; i++){
sum += params.targetBuffer[i%params.buffer_length];
}
// Run experiment multiple times. First iteration (-1) is to warm up icache
for (int i = -2; i < params.nof_repetitions; i++){
sum = 0;
time_acc = 0;
current = (blockDim.x*blockIdx.x + threadIdx.x)%params.buffer_length;
__syncthreads();
time_start = clock();
// Strided access to array
for(int j = 0; j < params.buffer_length; j++){
current = params.targetBuffer[current];
sum += current;
}
time_end = clock();
time_acc += (time_end - time_start);
__syncthreads();
*params.target_realSum = sum;
// Do not write time for warm up iteration
if (i>=0){
// Write element access time with measurement overhead
params.target_times[tindex+i] = time_acc/params.buffer_length-(*params.targetMeasOH);
}
}
}
#if 0
static void printArray(int* buffer, int size){
printf("%d\n",size);
for( int row = 0; row <= ceil(size/10); row++){
for(int i = row*10; i< row*10+10 && i<size; i++)
printf("[%4d] ",i);
printf("\n");
for(int i = row*10; i< row*10+10 && i<size; i++)
printf(" %4d, ",buffer[i]);
printf("\n");
}
}
#endif
static int initializeTest(param_t *params){
//allocate buffer
params->hostBuffer = NULL;
params->hostBuffer = (int *) malloc(params->buffer_length*sizeof(int));
if (!params->hostBuffer) {
perror("Failed allocating host buffer: ");
return -1;
}
createSequentialArrayHost(*params);
//allocate device random buffer
if (CheckCUDAError(cudaMalloc(¶ms->targetBuffer, \
params->buffer_length*sizeof(int)))) return -1;
/*
createSequentialArray<<<params->nofBlocks,params->nofThreads>>>(*params);
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
if (CheckCUDAError(cudaMemcpy(params->hostBuffer, \
params->targetBuffer, \
params->buffer_length*sizeof(int), \
cudaMemcpyDeviceToHost))) return -1;
*/
#if 0
printArray(params->hostBuffer, params->buffer_length);
#endif
//allocate device times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(cudaMalloc(¶ms->target_times, \
size_time))) return -1;
//allocate host times
params->host_times = NULL;
params->host_times = (unsigned int *) malloc(size_time);
if (!params->host_times) {
perror("Failed allocating host_times buffer: ");
return -1;
}
memset(params->host_times,1, size_time);
// Allocate device accumulator
if (CheckCUDAError(cudaMalloc(¶ms->target_realSum, \
sizeof(uint64_t)))) return -1;
// Allocate device measOH
if (CheckCUDAError(cudaMalloc(¶ms->targetMeasOH, \
sizeof(unsigned int)))) return -1;
return 0;
}
static int runTest(param_t *params){
// Get measurement overhead
getMeasurementOverhead<<<1,1>>>(*params);
// Launch kernel
sequentialWalk<<<params->nofBlocks,params->nofThreads>>>(*params);
// Synchronize with device
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
// Copyback times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(cudaMemcpy(params->host_times, \
params->target_times, \
size_time, \
cudaMemcpyDeviceToHost))) return -1;
// Copyback sum
params->host_realSum=0;
if (CheckCUDAError(cudaMemcpy(¶ms->host_realSum, \
params->target_realSum, \
sizeof(uint64_t), \
cudaMemcpyDeviceToHost))) return -1;
// Copyback target meas oh
params->hostMeasOH=0;
if (CheckCUDAError(cudaMemcpy(¶ms->hostMeasOH, \
params->targetMeasOH, \
sizeof(unsigned int), \
cudaMemcpyDeviceToHost))) return -1;
return 0;
}
static int writeResults(param_t *params){
if (fprintf(params->fd,"{\n") < 0 ) return -1;
// Write device info
cudaDeviceProp deviceProp;
if (CheckCUDAError(cudaGetDeviceProperties(&deviceProp, DEVICE_NUMBER))) return -1;
int driverVersion = 0;
if (CheckCUDAError(cudaDriverGetVersion(&driverVersion))) return -1;
int runtimeVersion = 0;
if (CheckCUDAError(cudaRuntimeGetVersion(&runtimeVersion))) return -1;
if (fprintf(params->fd,"\"driverVer\": \"%d\",\n", driverVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"runTimeVer\": \"%d\",\n", runtimeVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"clockRate\": \"%d\",\n", deviceProp.clockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"globalL1CacheSupported\": \"%d\",\n", deviceProp.globalL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"localL1CacheSupported\": \"%d\",\n", deviceProp.localL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"l2CacheSize\": \"%d\",\n", deviceProp.l2CacheSize) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryBusWidth\": \"%d\",\n", deviceProp.memoryBusWidth) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryClockRate\": \"%d\",\n", deviceProp.memoryClockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"multiProcessorCount\": \"%d\",\n", deviceProp.multiProcessorCount) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerBlock\": \"%d\",\n", deviceProp.regsPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerMultiprocessor\": \"%d\",\n", deviceProp.regsPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerBlock\": \"%zu\",\n", deviceProp.sharedMemPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerMultiprocessor\": \"%zu\",\n", deviceProp.sharedMemPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"warpSize\": \"%d\",\n", deviceProp.warpSize) < 0 ) return -1;
cudaFuncCache config;
if (CheckCUDAError(cudaDeviceGetCacheConfig ( &config ) )) return -1;
if (fprintf(params->fd,"\"cacheConfig\": \"%d\",\n", config) < 0 ) return -1;
// Write header
if (fprintf(params->fd,"\"nofThreads\": \"%u\",\n", params->nofThreads) < 0 ) return -1;
if (fprintf(params->fd,"\"nofBlocks\": \"%u\",\n", params->nofBlocks) < 0 ) return -1;
if (fprintf(params->fd,"\"nof_repetitions\": \"%d\",\n", params->nof_repetitions) < 0 ) return -1;
if (fprintf(params->fd,"\"data_size\": \"%d\",\n", params->data_size) < 0 ) return -1;
if (fprintf(params->fd,"\"buffer_length\": \"%d\",\n", params->buffer_length) < 0 ) return -1;
if (fprintf(params->fd,"\"real_sum\": \"%llu\",\n", (unsigned long long)params->host_realSum) < 0 ) return -1;
if (fprintf(params->fd,"\"exp_sum\": \"%llu\",\n", ((unsigned long long)(params->buffer_length-1)*(unsigned long long)params->buffer_length)/2) < 0 ) return -1;
if (fprintf(params->fd,"\"measOH\": \"%u\",\n", params->hostMeasOH) < 0 ) return -1;
// Write times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks;
if (fprintf(params->fd,"\"times\":[\n") < 0 ) return -1;
for (int i = 0; i < size_time-1; i++){
if (fprintf(params->fd,"\"%u\",\n",params->host_times[i]) < 0 ) return -1;
}
if (fprintf(params->fd,"\"%u\"]\n}", params->host_times[size_time-1]) < 0 ) return -1;
if (fclose(params->fd) < 0) return -1;
return 0;
}
static int cleanUp(param_t *params){
// Free target buffers
cudaFree(params->targetBuffer);
cudaFree(params->target_times);
// Free host buffers
free(params->hostBuffer);
free(params->host_times);
return 0;
}
static void PrintUsage(const char *name) {
printf("Usage: %s <#threads> <#blocks> <# of intervals> <size in KB>"
"<output JSON file name>\n", name);
}
int main(int argc, char **argv) {
if (argc != 6) {
PrintUsage(argv[0]);
return 1;
}
param_t params;
// Parse input parameter
int nof_threads = atoi(argv[1]);
if (nof_threads <= 0) {
printf("Min one thread. Got %s threads\n", argv[1]);
return EXIT_FAILURE;
}
int nof_blocks = atoi(argv[2]);
if (nof_blocks <= 0) {
printf("Min 1 block. Got %s blocks\n", argv[2]);
return EXIT_FAILURE;
}
params.nofThreads = nof_threads;
params.nofBlocks = nof_blocks;
int nof_repetitions = atoi(argv[3]);
if (nof_repetitions <= 0) {
printf("More than 0 repetitions need to be used. Got %s repetitions\n", argv[3]);
return EXIT_FAILURE;
}
int data_size = atoi(argv[4]);
if (data_size <= 0) {
printf("The buffer must be 1 or more KB. Got %s KB\n", argv[4]);
return EXIT_FAILURE;
}
params.nof_repetitions = nof_repetitions;
params.data_size = data_size*1024;
params.buffer_length = data_size*1024/sizeof(int);
params.fd = NULL;
params.fd = fopen(argv[5],"w");
if (params.fd == NULL) {
perror("Error opening output file:");
return EXIT_FAILURE;
}
// Set CUDA device
if (CheckCUDAError(cudaSetDevice(DEVICE_NUMBER))) {
return EXIT_FAILURE;
}
// Initialize parameters
if (initializeTest(¶ms) < 0) return EXIT_FAILURE;
// Run test
if (runTest(¶ms) < 0) return EXIT_FAILURE;
// Write results
if (writeResults(¶ms) < 0){
perror("Error while writing outpufile: ");
return EXIT_FAILURE;
}
// Clean up
if (cleanUp(¶ms) < 0) return EXIT_FAILURE;
printf("Finished testrun\n");
cudaDeviceReset();
return 0;
} | .file "tmpxft_00003120_00000000-6_sequential-walk.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL22getMeasurementOverhead7param_t, @function
_ZL22getMeasurementOverhead7param_t:
.LFB2092:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _ZL22getMeasurementOverhead7param_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _ZL22getMeasurementOverhead7param_t, .-_ZL22getMeasurementOverhead7param_t
.type _ZL14sequentialWalk7param_t, @function
_ZL14sequentialWalk7param_t:
.LFB2094:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _ZL14sequentialWalk7param_t(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _ZL14sequentialWalk7param_t, .-_ZL14sequentialWalk7param_t
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA error %d in %s, line %d (%s): %s\n"
.text
.type _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i, @function
_ZL22InternalCheckCUDAError9cudaErrorPKcS1_i:
.LFB2059:
.cfi_startproc
testl %edi, %edi
jne .L20
movl $0, %eax
ret
.L20:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %rbp
movl %ecx, %r12d
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
movq %r13, %r9
movl %r12d, %r8d
movq %rbp, %rcx
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i, .-_ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "{\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/realentertain/tt-gpu/master/experiments/sequential-walk-multithread/sequential-walk.cu"
.align 8
.LC3:
.string "cudaGetDeviceProperties(&deviceProp, DEVICE_NUMBER)"
.align 8
.LC4:
.string "cudaDriverGetVersion(&driverVersion)"
.align 8
.LC5:
.string "cudaRuntimeGetVersion(&runtimeVersion)"
.section .rodata.str1.1
.LC6:
.string "\"driverVer\": \"%d\",\n"
.LC7:
.string "\"runTimeVer\": \"%d\",\n"
.LC8:
.string "\"clockRate\": \"%d\",\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "\"globalL1CacheSupported\": \"%d\",\n"
.align 8
.LC10:
.string "\"localL1CacheSupported\": \"%d\",\n"
.section .rodata.str1.1
.LC11:
.string "\"l2CacheSize\": \"%d\",\n"
.LC12:
.string "\"memoryBusWidth\": \"%d\",\n"
.LC13:
.string "\"memoryClockRate\": \"%d\",\n"
.LC14:
.string "\"multiProcessorCount\": \"%d\",\n"
.LC15:
.string "\"regsPerBlock\": \"%d\",\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "\"regsPerMultiprocessor\": \"%d\",\n"
.section .rodata.str1.1
.LC17:
.string "\"sharedMemPerBlock\": \"%zu\",\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "\"sharedMemPerMultiprocessor\": \"%zu\",\n"
.section .rodata.str1.1
.LC19:
.string "\"warpSize\": \"%d\",\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "cudaDeviceGetCacheConfig ( &config )"
.section .rodata.str1.1
.LC21:
.string "\"cacheConfig\": \"%d\",\n"
.LC22:
.string "\"nofThreads\": \"%u\",\n"
.LC23:
.string "\"nofBlocks\": \"%u\",\n"
.LC24:
.string "\"nof_repetitions\": \"%d\",\n"
.LC25:
.string "\"data_size\": \"%d\",\n"
.LC26:
.string "\"buffer_length\": \"%d\",\n"
.LC27:
.string "\"real_sum\": \"%llu\",\n"
.LC28:
.string "\"exp_sum\": \"%llu\",\n"
.LC29:
.string "\"measOH\": \"%u\",\n"
.LC30:
.string "\"times\":[\n"
.LC31:
.string "\"%u\",\n"
.LC32:
.string "\"%u\"]\n}"
.text
.type _ZL12writeResultsP7param_t, @function
_ZL12writeResultsP7param_t:
.LFB2063:
.cfi_startproc
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movq 88(%rdi), %rdi
leaq .LC1(%rip), %rdx
movl $2, %esi
call __fprintf_chk@PLT
testl %eax, %eax
js .L26
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %edi
movl $209, %ecx
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L27
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaDriverGetVersion@PLT
movl %eax, %edi
movl $211, %ecx
leaq .LC2(%rip), %rdx
leaq .LC4(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L28
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
call cudaRuntimeGetVersion@PLT
movl %eax, %edi
movl $213, %ecx
leaq .LC2(%rip), %rdx
leaq .LC5(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L29
movq 88(%rbx), %rdi
movl 4(%rsp), %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
call __fprintf_chk@PLT
testl %eax, %eax
js .L30
movq 88(%rbx), %rdi
movl 8(%rsp), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L31
movq 88(%rbx), %rdi
movl 364(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L32
movq 88(%rbx), %rdi
movl 648(%rsp), %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L33
movq 88(%rbx), %rdi
movl 652(%rsp), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L34
movq 88(%rbx), %rdi
movl 632(%rsp), %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L35
movq 88(%rbx), %rdi
movl 628(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L36
movq 88(%rbx), %rdi
movl 624(%rsp), %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L37
movq 88(%rbx), %rdi
movl 404(%rsp), %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L38
movq 88(%rbx), %rdi
movl 320(%rsp), %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L39
movq 88(%rbx), %rdi
movl 664(%rsp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L40
movq 88(%rbx), %rdi
movq 312(%rsp), %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L41
movq 88(%rbx), %rdi
movq 656(%rsp), %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L42
movq 88(%rbx), %rdi
movl 324(%rsp), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L43
leaq 12(%rsp), %rdi
call cudaDeviceGetCacheConfig@PLT
movl %eax, %edi
movl $230, %ecx
leaq .LC2(%rip), %rdx
leaq .LC20(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L44
movq 88(%rbx), %rdi
movl 12(%rsp), %ecx
leaq .LC21(%rip), %rdx
movl $2, %esi
call __fprintf_chk@PLT
testl %eax, %eax
js .L45
movl (%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC22(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L46
movl 4(%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC23(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L47
movl 8(%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC24(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L48
movl 12(%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC25(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L49
movl 16(%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC26(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L50
movq 64(%rbx), %rcx
movq 88(%rbx), %rdi
leaq .LC27(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L51
movl 16(%rbx), %eax
leal -1(%rax), %ecx
movslq %ecx, %rcx
cltq
imulq %rax, %rcx
shrq %rcx
movq 88(%rbx), %rdi
leaq .LC28(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L52
movl 32(%rbx), %ecx
movq 88(%rbx), %rdi
leaq .LC29(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L53
movl 8(%rbx), %r14d
imull (%rbx), %r14d
imull 4(%rbx), %r14d
movq 88(%rbx), %rdi
leaq .LC30(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L54
cmpl $1, %r14d
jle .L23
leal -1(%r14), %r12d
salq $2, %r12
movl $0, %ebp
leaq .LC31(%rip), %r13
.L24:
movq 80(%rbx), %rax
movl (%rax,%rbp), %ecx
movq 88(%rbx), %rdi
movq %r13, %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L55
addq $4, %rbp
cmpq %r12, %rbp
jne .L24
.L23:
movslq %r14d, %r14
movq 80(%rbx), %rax
movl -4(%rax,%r14,4), %ecx
movq 88(%rbx), %rdi
leaq .LC32(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
testl %eax, %eax
js .L56
movq 88(%rbx), %rdi
call fclose@PLT
sarl $31, %eax
.L21:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L59
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl $-1, %eax
jmp .L21
.L27:
movl $-1, %eax
jmp .L21
.L28:
movl $-1, %eax
jmp .L21
.L29:
movl $-1, %eax
jmp .L21
.L30:
movl $-1, %eax
jmp .L21
.L31:
movl $-1, %eax
jmp .L21
.L32:
movl $-1, %eax
jmp .L21
.L33:
movl $-1, %eax
jmp .L21
.L34:
movl $-1, %eax
jmp .L21
.L35:
movl $-1, %eax
jmp .L21
.L36:
movl $-1, %eax
jmp .L21
.L37:
movl $-1, %eax
jmp .L21
.L38:
movl $-1, %eax
jmp .L21
.L39:
movl $-1, %eax
jmp .L21
.L40:
movl $-1, %eax
jmp .L21
.L41:
movl $-1, %eax
jmp .L21
.L42:
movl $-1, %eax
jmp .L21
.L43:
movl $-1, %eax
jmp .L21
.L44:
movl $-1, %eax
jmp .L21
.L45:
movl $-1, %eax
jmp .L21
.L46:
movl $-1, %eax
jmp .L21
.L47:
movl $-1, %eax
jmp .L21
.L48:
movl $-1, %eax
jmp .L21
.L49:
movl $-1, %eax
jmp .L21
.L50:
movl $-1, %eax
jmp .L21
.L51:
movl $-1, %eax
jmp .L21
.L52:
movl $-1, %eax
jmp .L21
.L53:
movl $-1, %eax
jmp .L21
.L54:
movl $-1, %eax
jmp .L21
.L55:
movl $-1, %eax
jmp .L21
.L56:
movl $-1, %eax
jmp .L21
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _ZL12writeResultsP7param_t, .-_ZL12writeResultsP7param_t
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8
.align 8
.LC33:
.string "Usage: %s <#threads> <#blocks> <# of intervals> <size in KB><output JSON file name>\n"
.align 8
.LC34:
.string "Min one thread. Got %s threads\n"
.section .rodata.str1.1
.LC35:
.string "Min 1 block. Got %s blocks\n"
.section .rodata.str1.8
.align 8
.LC36:
.string "More than 0 repetitions need to be used. Got %s repetitions\n"
.align 8
.LC37:
.string "The buffer must be 1 or more KB. Got %s KB\n"
.section .rodata.str1.1
.LC38:
.string "w"
.LC39:
.string "Error opening output file:"
.LC40:
.string "cudaSetDevice(DEVICE_NUMBER)"
.section .rodata.str1.8
.align 8
.LC41:
.string "Failed allocating host buffer: "
.align 8
.LC42:
.string "cudaMalloc(¶ms->targetBuffer, params->buffer_length*sizeof(int))"
.align 8
.LC43:
.string "cudaMalloc(¶ms->target_times, size_time)"
.align 8
.LC44:
.string "Failed allocating host_times buffer: "
.align 8
.LC45:
.string "cudaMalloc(¶ms->target_realSum, sizeof(uint64_t))"
.align 8
.LC46:
.string "cudaMalloc(¶ms->targetMeasOH, sizeof(unsigned int))"
.section .rodata.str1.1
.LC47:
.string "cudaDeviceSynchronize()"
.section .rodata.str1.8
.align 8
.LC48:
.string "cudaMemcpy(params->host_times, params->target_times, size_time, cudaMemcpyDeviceToHost)"
.align 8
.LC49:
.string "cudaMemcpy(¶ms->host_realSum, params->target_realSum, sizeof(uint64_t), cudaMemcpyDeviceToHost)"
.align 8
.LC50:
.string "cudaMemcpy(¶ms->hostMeasOH, params->targetMeasOH, sizeof(unsigned int), cudaMemcpyDeviceToHost)"
.align 8
.LC51:
.string "Error while writing outpufile: "
.section .rodata.str1.1
.LC52:
.string "Finished testrun\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $6, %edi
je .L63
movq (%rsi), %rdx
leaq .LC33(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %ebx
.L62:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl %ebx, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
testl %eax, %eax
jle .L85
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L86
movl %ebp, 32(%rsp)
movl %eax, 36(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
testl %eax, %eax
jle .L87
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L88
movl %ebp, 40(%rsp)
sall $10, %eax
movl %eax, 44(%rsp)
cltq
shrq $2, %rax
movl %eax, 48(%rsp)
movq $0, 120(%rsp)
movq 40(%rbx), %rdi
leaq .LC38(%rip), %rsi
call fopen@PLT
movq %rax, 120(%rsp)
testq %rax, %rax
je .L89
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $323, %ecx
leaq .LC2(%rip), %rdx
leaq .LC40(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
movl $1, %ebx
testl %eax, %eax
jne .L62
movl 48(%rsp), %ebx
movslq %ebx, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rsi
movq %rax, 72(%rsp)
testq %rax, %rax
je .L90
movl 36(%rsp), %edi
imull 32(%rsp), %edi
movl $0, %ecx
jmp .L72
.L85:
movq 8(%rbx), %rdx
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L62
.L86:
movq 16(%rbx), %rdx
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L62
.L87:
movq 24(%rbx), %rdx
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L62
.L88:
movq 32(%rbx), %rdx
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L62
.L89:
leaq .LC39(%rip), %rdi
call perror@PLT
movl $1, %ebx
jmp .L62
.L90:
leaq .LC41(%rip), %rdi
call perror@PLT
.L71:
movl $1, %ebx
jmp .L62
.L73:
leal (%rdi,%rcx), %eax
cltd
idivl %ebx
movl %edx, (%rsi,%rcx,4)
addq $1, %rcx
.L72:
cmpl %ecx, %ebx
jg .L73
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $125, %ecx
leaq .LC2(%rip), %rdx
leaq .LC42(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L71
movl 40(%rsp), %ebx
imull 32(%rsp), %ebx
imull 36(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $145, %ecx
leaq .LC2(%rip), %rdx
leaq .LC43(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L71
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 112(%rsp)
testq %rax, %rax
je .L91
movq %rbx, %rcx
movq %rbx, %rdx
movl $1, %esi
call __memset_chk@PLT
leaq 88(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $158, %ecx
leaq .LC2(%rip), %rdx
leaq .LC45(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L71
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $162, %ecx
leaq .LC2(%rip), %rdx
leaq .LC46(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
movl $1, %ebx
testl %eax, %eax
jne .L62
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L75:
movl 32(%rsp), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl 36(%rsp), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L93
.L76:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $175, %ecx
leaq .LC2(%rip), %rdx
leaq .LC47(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L77
movl 40(%rsp), %edx
imull 32(%rsp), %edx
imull 36(%rsp), %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq 104(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $183, %ecx
leaq .LC2(%rip), %rdx
leaq .LC48(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L77
movq $0, 96(%rsp)
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $190, %ecx
leaq .LC2(%rip), %rdx
leaq .LC49(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
testl %eax, %eax
jne .L77
movl $0, 64(%rsp)
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $197, %ecx
leaq .LC2(%rip), %rdx
leaq .LC50(%rip), %rsi
call _ZL22InternalCheckCUDAError9cudaErrorPKcS1_i
movl %eax, %ebx
testl %eax, %eax
jne .L82
leaq 32(%rsp), %rdi
call _ZL12writeResultsP7param_t
testl %eax, %eax
js .L94
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call free@PLT
movq 112(%rsp), %rdi
call free@PLT
leaq .LC52(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L62
.L91:
leaq .LC44(%rip), %rdi
call perror@PLT
jmp .L71
.L92:
subq $96, %rsp
.cfi_def_cfa_offset 272
leaq 128(%rsp), %rsi
movl $24, %ecx
movq %rsp, %rdi
rep movsl
call _ZL22getMeasurementOverhead7param_t
addq $96, %rsp
.cfi_def_cfa_offset 176
jmp .L75
.L93:
subq $96, %rsp
.cfi_def_cfa_offset 272
leaq 128(%rsp), %rsi
movl $24, %ecx
movq %rsp, %rdi
rep movsl
call _ZL14sequentialWalk7param_t
addq $96, %rsp
.cfi_def_cfa_offset 176
jmp .L76
.L94:
leaq .LC51(%rip), %rdi
call perror@PLT
movl $1, %ebx
jmp .L62
.L82:
movl $1, %ebx
jmp .L62
.L77:
movl $1, %ebx
jmp .L62
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.1
.LC53:
.string "_Z14sequentialWalk7param_t"
.section .rodata.str1.8
.align 8
.LC54:
.string "_Z22getMeasurementOverhead7param_t"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC53(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14sequentialWalk7param_t(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC54(%rip), %rdx
movq %rdx, %rcx
leaq _ZL22getMeasurementOverhead7param_t(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <error.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <cuda_runtime.h>
#define DEVICE_NUMBER (0)
typedef struct {
int nofThreads;
int nofBlocks;
int32_t nof_repetitions;
int data_size;
int buffer_length;
unsigned int *targetMeasOH;
unsigned int hostMeasOH;
int *hostBuffer;
int *targetBuffer;
uint64_t *target_realSum;
uint64_t host_realSum;
unsigned int *target_times;
unsigned int *host_times;
FILE *fd;
} param_t;
// Prints a message and returns zero if the given value is not cudaSuccess
#define CheckCUDAError(val) (InternalCheckCUDAError((val), #val, __FILE__, __LINE__))
// Called internally by CheckCUDAError
static int InternalCheckCUDAError(cudaError_t result, const char *fn,
const char *file, int line) {
if (result == cudaSuccess) return 0;
printf("CUDA error %d in %s, line %d (%s): %s\n", (int) result, file, line,
fn, cudaGetErrorString(result));
return -1;
}
static void createSequentialArrayHost(param_t params){
// Link sequentially
for(int i = 0; i < params.buffer_length; i++){
params.hostBuffer[i]=(i+params.nofThreads*params.nofBlocks)%params.buffer_length;
}
}
static __global__ void getMeasurementOverhead(param_t params) {
unsigned int start, stop;
uint64_t sum = 0;
start = clock();
for (int j = 0; j < params.buffer_length; j++){
sum +=j;
}
stop = clock();
*params.targetMeasOH = (stop-start)/params.buffer_length;
*params.target_realSum = sum;
}
static __global__ void sequentialWalk(param_t params) {
int current;
unsigned int time_start, time_end, time_acc;
uint64_t sum;
int tindex = blockDim.x*blockIdx.x*params.nof_repetitions + params.nof_repetitions *threadIdx.x;
// Warm up data cache
for(int i = 0; i < params.buffer_length; i++){
sum += params.targetBuffer[i%params.buffer_length];
}
// Run experiment multiple times. First iteration (-1) is to warm up icache
for (int i = -2; i < params.nof_repetitions; i++){
sum = 0;
time_acc = 0;
current = (blockDim.x*blockIdx.x + threadIdx.x)%params.buffer_length;
__syncthreads();
time_start = clock();
// Strided access to array
for(int j = 0; j < params.buffer_length; j++){
current = params.targetBuffer[current];
sum += current;
}
time_end = clock();
time_acc += (time_end - time_start);
__syncthreads();
*params.target_realSum = sum;
// Do not write time for warm up iteration
if (i>=0){
// Write element access time with measurement overhead
params.target_times[tindex+i] = time_acc/params.buffer_length-(*params.targetMeasOH);
}
}
}
#if 0
static void printArray(int* buffer, int size){
printf("%d\n",size);
for( int row = 0; row <= ceil(size/10); row++){
for(int i = row*10; i< row*10+10 && i<size; i++)
printf("[%4d] ",i);
printf("\n");
for(int i = row*10; i< row*10+10 && i<size; i++)
printf(" %4d, ",buffer[i]);
printf("\n");
}
}
#endif
static int initializeTest(param_t *params){
//allocate buffer
params->hostBuffer = NULL;
params->hostBuffer = (int *) malloc(params->buffer_length*sizeof(int));
if (!params->hostBuffer) {
perror("Failed allocating host buffer: ");
return -1;
}
createSequentialArrayHost(*params);
//allocate device random buffer
if (CheckCUDAError(cudaMalloc(¶ms->targetBuffer, \
params->buffer_length*sizeof(int)))) return -1;
/*
createSequentialArray<<<params->nofBlocks,params->nofThreads>>>(*params);
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
if (CheckCUDAError(cudaMemcpy(params->hostBuffer, \
params->targetBuffer, \
params->buffer_length*sizeof(int), \
cudaMemcpyDeviceToHost))) return -1;
*/
#if 0
printArray(params->hostBuffer, params->buffer_length);
#endif
//allocate device times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(cudaMalloc(¶ms->target_times, \
size_time))) return -1;
//allocate host times
params->host_times = NULL;
params->host_times = (unsigned int *) malloc(size_time);
if (!params->host_times) {
perror("Failed allocating host_times buffer: ");
return -1;
}
memset(params->host_times,1, size_time);
// Allocate device accumulator
if (CheckCUDAError(cudaMalloc(¶ms->target_realSum, \
sizeof(uint64_t)))) return -1;
// Allocate device measOH
if (CheckCUDAError(cudaMalloc(¶ms->targetMeasOH, \
sizeof(unsigned int)))) return -1;
return 0;
}
static int runTest(param_t *params){
// Get measurement overhead
getMeasurementOverhead<<<1,1>>>(*params);
// Launch kernel
sequentialWalk<<<params->nofBlocks,params->nofThreads>>>(*params);
// Synchronize with device
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
// Copyback times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(cudaMemcpy(params->host_times, \
params->target_times, \
size_time, \
cudaMemcpyDeviceToHost))) return -1;
// Copyback sum
params->host_realSum=0;
if (CheckCUDAError(cudaMemcpy(¶ms->host_realSum, \
params->target_realSum, \
sizeof(uint64_t), \
cudaMemcpyDeviceToHost))) return -1;
// Copyback target meas oh
params->hostMeasOH=0;
if (CheckCUDAError(cudaMemcpy(¶ms->hostMeasOH, \
params->targetMeasOH, \
sizeof(unsigned int), \
cudaMemcpyDeviceToHost))) return -1;
return 0;
}
static int writeResults(param_t *params){
if (fprintf(params->fd,"{\n") < 0 ) return -1;
// Write device info
cudaDeviceProp deviceProp;
if (CheckCUDAError(cudaGetDeviceProperties(&deviceProp, DEVICE_NUMBER))) return -1;
int driverVersion = 0;
if (CheckCUDAError(cudaDriverGetVersion(&driverVersion))) return -1;
int runtimeVersion = 0;
if (CheckCUDAError(cudaRuntimeGetVersion(&runtimeVersion))) return -1;
if (fprintf(params->fd,"\"driverVer\": \"%d\",\n", driverVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"runTimeVer\": \"%d\",\n", runtimeVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"clockRate\": \"%d\",\n", deviceProp.clockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"globalL1CacheSupported\": \"%d\",\n", deviceProp.globalL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"localL1CacheSupported\": \"%d\",\n", deviceProp.localL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"l2CacheSize\": \"%d\",\n", deviceProp.l2CacheSize) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryBusWidth\": \"%d\",\n", deviceProp.memoryBusWidth) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryClockRate\": \"%d\",\n", deviceProp.memoryClockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"multiProcessorCount\": \"%d\",\n", deviceProp.multiProcessorCount) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerBlock\": \"%d\",\n", deviceProp.regsPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerMultiprocessor\": \"%d\",\n", deviceProp.regsPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerBlock\": \"%zu\",\n", deviceProp.sharedMemPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerMultiprocessor\": \"%zu\",\n", deviceProp.sharedMemPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"warpSize\": \"%d\",\n", deviceProp.warpSize) < 0 ) return -1;
cudaFuncCache config;
if (CheckCUDAError(cudaDeviceGetCacheConfig ( &config ) )) return -1;
if (fprintf(params->fd,"\"cacheConfig\": \"%d\",\n", config) < 0 ) return -1;
// Write header
if (fprintf(params->fd,"\"nofThreads\": \"%u\",\n", params->nofThreads) < 0 ) return -1;
if (fprintf(params->fd,"\"nofBlocks\": \"%u\",\n", params->nofBlocks) < 0 ) return -1;
if (fprintf(params->fd,"\"nof_repetitions\": \"%d\",\n", params->nof_repetitions) < 0 ) return -1;
if (fprintf(params->fd,"\"data_size\": \"%d\",\n", params->data_size) < 0 ) return -1;
if (fprintf(params->fd,"\"buffer_length\": \"%d\",\n", params->buffer_length) < 0 ) return -1;
if (fprintf(params->fd,"\"real_sum\": \"%llu\",\n", (unsigned long long)params->host_realSum) < 0 ) return -1;
if (fprintf(params->fd,"\"exp_sum\": \"%llu\",\n", ((unsigned long long)(params->buffer_length-1)*(unsigned long long)params->buffer_length)/2) < 0 ) return -1;
if (fprintf(params->fd,"\"measOH\": \"%u\",\n", params->hostMeasOH) < 0 ) return -1;
// Write times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks;
if (fprintf(params->fd,"\"times\":[\n") < 0 ) return -1;
for (int i = 0; i < size_time-1; i++){
if (fprintf(params->fd,"\"%u\",\n",params->host_times[i]) < 0 ) return -1;
}
if (fprintf(params->fd,"\"%u\"]\n}", params->host_times[size_time-1]) < 0 ) return -1;
if (fclose(params->fd) < 0) return -1;
return 0;
}
static int cleanUp(param_t *params){
// Free target buffers
cudaFree(params->targetBuffer);
cudaFree(params->target_times);
// Free host buffers
free(params->hostBuffer);
free(params->host_times);
return 0;
}
static void PrintUsage(const char *name) {
printf("Usage: %s <#threads> <#blocks> <# of intervals> <size in KB>"
"<output JSON file name>\n", name);
}
int main(int argc, char **argv) {
if (argc != 6) {
PrintUsage(argv[0]);
return 1;
}
param_t params;
// Parse input parameter
int nof_threads = atoi(argv[1]);
if (nof_threads <= 0) {
printf("Min one thread. Got %s threads\n", argv[1]);
return EXIT_FAILURE;
}
int nof_blocks = atoi(argv[2]);
if (nof_blocks <= 0) {
printf("Min 1 block. Got %s blocks\n", argv[2]);
return EXIT_FAILURE;
}
params.nofThreads = nof_threads;
params.nofBlocks = nof_blocks;
int nof_repetitions = atoi(argv[3]);
if (nof_repetitions <= 0) {
printf("More than 0 repetitions need to be used. Got %s repetitions\n", argv[3]);
return EXIT_FAILURE;
}
int data_size = atoi(argv[4]);
if (data_size <= 0) {
printf("The buffer must be 1 or more KB. Got %s KB\n", argv[4]);
return EXIT_FAILURE;
}
params.nof_repetitions = nof_repetitions;
params.data_size = data_size*1024;
params.buffer_length = data_size*1024/sizeof(int);
params.fd = NULL;
params.fd = fopen(argv[5],"w");
if (params.fd == NULL) {
perror("Error opening output file:");
return EXIT_FAILURE;
}
// Set CUDA device
if (CheckCUDAError(cudaSetDevice(DEVICE_NUMBER))) {
return EXIT_FAILURE;
}
// Initialize parameters
if (initializeTest(¶ms) < 0) return EXIT_FAILURE;
// Run test
if (runTest(¶ms) < 0) return EXIT_FAILURE;
// Write results
if (writeResults(¶ms) < 0){
perror("Error while writing outpufile: ");
return EXIT_FAILURE;
}
// Clean up
if (cleanUp(¶ms) < 0) return EXIT_FAILURE;
printf("Finished testrun\n");
cudaDeviceReset();
return 0;
} | #include <error.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define DEVICE_NUMBER (0)
typedef struct {
int nofThreads;
int nofBlocks;
int32_t nof_repetitions;
int data_size;
int buffer_length;
unsigned int *targetMeasOH;
unsigned int hostMeasOH;
int *hostBuffer;
int *targetBuffer;
uint64_t *target_realSum;
uint64_t host_realSum;
unsigned int *target_times;
unsigned int *host_times;
FILE *fd;
} param_t;
// Prints a message and returns zero if the given value is not cudaSuccess
#define CheckCUDAError(val) (InternalCheckCUDAError((val), #val, __FILE__, __LINE__))
// Called internally by CheckCUDAError
static int InternalCheckCUDAError(hipError_t result, const char *fn,
const char *file, int line) {
if (result == hipSuccess) return 0;
printf("CUDA error %d in %s, line %d (%s): %s\n", (int) result, file, line,
fn, hipGetErrorString(result));
return -1;
}
static void createSequentialArrayHost(param_t params){
// Link sequentially
for(int i = 0; i < params.buffer_length; i++){
params.hostBuffer[i]=(i+params.nofThreads*params.nofBlocks)%params.buffer_length;
}
}
static __global__ void getMeasurementOverhead(param_t params) {
unsigned int start, stop;
uint64_t sum = 0;
start = clock();
for (int j = 0; j < params.buffer_length; j++){
sum +=j;
}
stop = clock();
*params.targetMeasOH = (stop-start)/params.buffer_length;
*params.target_realSum = sum;
}
static __global__ void sequentialWalk(param_t params) {
int current;
unsigned int time_start, time_end, time_acc;
uint64_t sum;
int tindex = blockDim.x*blockIdx.x*params.nof_repetitions + params.nof_repetitions *threadIdx.x;
// Warm up data cache
for(int i = 0; i < params.buffer_length; i++){
sum += params.targetBuffer[i%params.buffer_length];
}
// Run experiment multiple times. First iteration (-1) is to warm up icache
for (int i = -2; i < params.nof_repetitions; i++){
sum = 0;
time_acc = 0;
current = (blockDim.x*blockIdx.x + threadIdx.x)%params.buffer_length;
__syncthreads();
time_start = clock();
// Strided access to array
for(int j = 0; j < params.buffer_length; j++){
current = params.targetBuffer[current];
sum += current;
}
time_end = clock();
time_acc += (time_end - time_start);
__syncthreads();
*params.target_realSum = sum;
// Do not write time for warm up iteration
if (i>=0){
// Write element access time with measurement overhead
params.target_times[tindex+i] = time_acc/params.buffer_length-(*params.targetMeasOH);
}
}
}
#if 0
static void printArray(int* buffer, int size){
printf("%d\n",size);
for( int row = 0; row <= ceil(size/10); row++){
for(int i = row*10; i< row*10+10 && i<size; i++)
printf("[%4d] ",i);
printf("\n");
for(int i = row*10; i< row*10+10 && i<size; i++)
printf(" %4d, ",buffer[i]);
printf("\n");
}
}
#endif
static int initializeTest(param_t *params){
//allocate buffer
params->hostBuffer = NULL;
params->hostBuffer = (int *) malloc(params->buffer_length*sizeof(int));
if (!params->hostBuffer) {
perror("Failed allocating host buffer: ");
return -1;
}
createSequentialArrayHost(*params);
//allocate device random buffer
if (CheckCUDAError(hipMalloc(¶ms->targetBuffer, \
params->buffer_length*sizeof(int)))) return -1;
/*
createSequentialArray<<<params->nofBlocks,params->nofThreads>>>(*params);
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
if (CheckCUDAError(cudaMemcpy(params->hostBuffer, \
params->targetBuffer, \
params->buffer_length*sizeof(int), \
cudaMemcpyDeviceToHost))) return -1;
*/
#if 0
printArray(params->hostBuffer, params->buffer_length);
#endif
//allocate device times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMalloc(¶ms->target_times, \
size_time))) return -1;
//allocate host times
params->host_times = NULL;
params->host_times = (unsigned int *) malloc(size_time);
if (!params->host_times) {
perror("Failed allocating host_times buffer: ");
return -1;
}
memset(params->host_times,1, size_time);
// Allocate device accumulator
if (CheckCUDAError(hipMalloc(¶ms->target_realSum, \
sizeof(uint64_t)))) return -1;
// Allocate device measOH
if (CheckCUDAError(hipMalloc(¶ms->targetMeasOH, \
sizeof(unsigned int)))) return -1;
return 0;
}
static int runTest(param_t *params){
// Get measurement overhead
getMeasurementOverhead<<<1,1>>>(*params);
// Launch kernel
sequentialWalk<<<params->nofBlocks,params->nofThreads>>>(*params);
// Synchronize with device
if (CheckCUDAError(hipDeviceSynchronize())) return -1;
// Copyback times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMemcpy(params->host_times, \
params->target_times, \
size_time, \
hipMemcpyDeviceToHost))) return -1;
// Copyback sum
params->host_realSum=0;
if (CheckCUDAError(hipMemcpy(¶ms->host_realSum, \
params->target_realSum, \
sizeof(uint64_t), \
hipMemcpyDeviceToHost))) return -1;
// Copyback target meas oh
params->hostMeasOH=0;
if (CheckCUDAError(hipMemcpy(¶ms->hostMeasOH, \
params->targetMeasOH, \
sizeof(unsigned int), \
hipMemcpyDeviceToHost))) return -1;
return 0;
}
static int writeResults(param_t *params){
if (fprintf(params->fd,"{\n") < 0 ) return -1;
// Write device info
hipDeviceProp_t deviceProp;
if (CheckCUDAError(hipGetDeviceProperties(&deviceProp, DEVICE_NUMBER))) return -1;
int driverVersion = 0;
if (CheckCUDAError(hipDriverGetVersion(&driverVersion))) return -1;
int runtimeVersion = 0;
if (CheckCUDAError(hipRuntimeGetVersion(&runtimeVersion))) return -1;
if (fprintf(params->fd,"\"driverVer\": \"%d\",\n", driverVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"runTimeVer\": \"%d\",\n", runtimeVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"clockRate\": \"%d\",\n", deviceProp.clockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"globalL1CacheSupported\": \"%d\",\n", deviceProp.globalL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"localL1CacheSupported\": \"%d\",\n", deviceProp.localL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"l2CacheSize\": \"%d\",\n", deviceProp.l2CacheSize) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryBusWidth\": \"%d\",\n", deviceProp.memoryBusWidth) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryClockRate\": \"%d\",\n", deviceProp.memoryClockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"multiProcessorCount\": \"%d\",\n", deviceProp.multiProcessorCount) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerBlock\": \"%d\",\n", deviceProp.regsPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerMultiprocessor\": \"%d\",\n", deviceProp.regsPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerBlock\": \"%zu\",\n", deviceProp.sharedMemPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerMultiprocessor\": \"%zu\",\n", deviceProp.sharedMemPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"warpSize\": \"%d\",\n", deviceProp.warpSize) < 0 ) return -1;
hipFuncCache_t config;
if (CheckCUDAError(hipDeviceGetCacheConfig ( &config ) )) return -1;
if (fprintf(params->fd,"\"cacheConfig\": \"%d\",\n", config) < 0 ) return -1;
// Write header
if (fprintf(params->fd,"\"nofThreads\": \"%u\",\n", params->nofThreads) < 0 ) return -1;
if (fprintf(params->fd,"\"nofBlocks\": \"%u\",\n", params->nofBlocks) < 0 ) return -1;
if (fprintf(params->fd,"\"nof_repetitions\": \"%d\",\n", params->nof_repetitions) < 0 ) return -1;
if (fprintf(params->fd,"\"data_size\": \"%d\",\n", params->data_size) < 0 ) return -1;
if (fprintf(params->fd,"\"buffer_length\": \"%d\",\n", params->buffer_length) < 0 ) return -1;
if (fprintf(params->fd,"\"real_sum\": \"%llu\",\n", (unsigned long long)params->host_realSum) < 0 ) return -1;
if (fprintf(params->fd,"\"exp_sum\": \"%llu\",\n", ((unsigned long long)(params->buffer_length-1)*(unsigned long long)params->buffer_length)/2) < 0 ) return -1;
if (fprintf(params->fd,"\"measOH\": \"%u\",\n", params->hostMeasOH) < 0 ) return -1;
// Write times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks;
if (fprintf(params->fd,"\"times\":[\n") < 0 ) return -1;
for (int i = 0; i < size_time-1; i++){
if (fprintf(params->fd,"\"%u\",\n",params->host_times[i]) < 0 ) return -1;
}
if (fprintf(params->fd,"\"%u\"]\n}", params->host_times[size_time-1]) < 0 ) return -1;
if (fclose(params->fd) < 0) return -1;
return 0;
}
static int cleanUp(param_t *params){
// Free target buffers
hipFree(params->targetBuffer);
hipFree(params->target_times);
// Free host buffers
free(params->hostBuffer);
free(params->host_times);
return 0;
}
static void PrintUsage(const char *name) {
printf("Usage: %s <#threads> <#blocks> <# of intervals> <size in KB>"
"<output JSON file name>\n", name);
}
int main(int argc, char **argv) {
if (argc != 6) {
PrintUsage(argv[0]);
return 1;
}
param_t params;
// Parse input parameter
int nof_threads = atoi(argv[1]);
if (nof_threads <= 0) {
printf("Min one thread. Got %s threads\n", argv[1]);
return EXIT_FAILURE;
}
int nof_blocks = atoi(argv[2]);
if (nof_blocks <= 0) {
printf("Min 1 block. Got %s blocks\n", argv[2]);
return EXIT_FAILURE;
}
params.nofThreads = nof_threads;
params.nofBlocks = nof_blocks;
int nof_repetitions = atoi(argv[3]);
if (nof_repetitions <= 0) {
printf("More than 0 repetitions need to be used. Got %s repetitions\n", argv[3]);
return EXIT_FAILURE;
}
int data_size = atoi(argv[4]);
if (data_size <= 0) {
printf("The buffer must be 1 or more KB. Got %s KB\n", argv[4]);
return EXIT_FAILURE;
}
params.nof_repetitions = nof_repetitions;
params.data_size = data_size*1024;
params.buffer_length = data_size*1024/sizeof(int);
params.fd = NULL;
params.fd = fopen(argv[5],"w");
if (params.fd == NULL) {
perror("Error opening output file:");
return EXIT_FAILURE;
}
// Set CUDA device
if (CheckCUDAError(hipSetDevice(DEVICE_NUMBER))) {
return EXIT_FAILURE;
}
// Initialize parameters
if (initializeTest(¶ms) < 0) return EXIT_FAILURE;
// Run test
if (runTest(¶ms) < 0) return EXIT_FAILURE;
// Write results
if (writeResults(¶ms) < 0){
perror("Error while writing outpufile: ");
return EXIT_FAILURE;
}
// Clean up
if (cleanUp(¶ms) < 0) return EXIT_FAILURE;
printf("Finished testrun\n");
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <error.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define DEVICE_NUMBER (0)
typedef struct {
int nofThreads;
int nofBlocks;
int32_t nof_repetitions;
int data_size;
int buffer_length;
unsigned int *targetMeasOH;
unsigned int hostMeasOH;
int *hostBuffer;
int *targetBuffer;
uint64_t *target_realSum;
uint64_t host_realSum;
unsigned int *target_times;
unsigned int *host_times;
FILE *fd;
} param_t;
// Prints a message and returns zero if the given value is not cudaSuccess
#define CheckCUDAError(val) (InternalCheckCUDAError((val), #val, __FILE__, __LINE__))
// Called internally by CheckCUDAError
static int InternalCheckCUDAError(hipError_t result, const char *fn,
const char *file, int line) {
if (result == hipSuccess) return 0;
printf("CUDA error %d in %s, line %d (%s): %s\n", (int) result, file, line,
fn, hipGetErrorString(result));
return -1;
}
static void createSequentialArrayHost(param_t params){
// Link sequentially
for(int i = 0; i < params.buffer_length; i++){
params.hostBuffer[i]=(i+params.nofThreads*params.nofBlocks)%params.buffer_length;
}
}
static __global__ void getMeasurementOverhead(param_t params) {
unsigned int start, stop;
uint64_t sum = 0;
start = clock();
for (int j = 0; j < params.buffer_length; j++){
sum +=j;
}
stop = clock();
*params.targetMeasOH = (stop-start)/params.buffer_length;
*params.target_realSum = sum;
}
static __global__ void sequentialWalk(param_t params) {
int current;
unsigned int time_start, time_end, time_acc;
uint64_t sum;
int tindex = blockDim.x*blockIdx.x*params.nof_repetitions + params.nof_repetitions *threadIdx.x;
// Warm up data cache
for(int i = 0; i < params.buffer_length; i++){
sum += params.targetBuffer[i%params.buffer_length];
}
// Run experiment multiple times. First iteration (-1) is to warm up icache
for (int i = -2; i < params.nof_repetitions; i++){
sum = 0;
time_acc = 0;
current = (blockDim.x*blockIdx.x + threadIdx.x)%params.buffer_length;
__syncthreads();
time_start = clock();
// Strided access to array
for(int j = 0; j < params.buffer_length; j++){
current = params.targetBuffer[current];
sum += current;
}
time_end = clock();
time_acc += (time_end - time_start);
__syncthreads();
*params.target_realSum = sum;
// Do not write time for warm up iteration
if (i>=0){
// Write element access time with measurement overhead
params.target_times[tindex+i] = time_acc/params.buffer_length-(*params.targetMeasOH);
}
}
}
#if 0
static void printArray(int* buffer, int size){
printf("%d\n",size);
for( int row = 0; row <= ceil(size/10); row++){
for(int i = row*10; i< row*10+10 && i<size; i++)
printf("[%4d] ",i);
printf("\n");
for(int i = row*10; i< row*10+10 && i<size; i++)
printf(" %4d, ",buffer[i]);
printf("\n");
}
}
#endif
static int initializeTest(param_t *params){
//allocate buffer
params->hostBuffer = NULL;
params->hostBuffer = (int *) malloc(params->buffer_length*sizeof(int));
if (!params->hostBuffer) {
perror("Failed allocating host buffer: ");
return -1;
}
createSequentialArrayHost(*params);
//allocate device random buffer
if (CheckCUDAError(hipMalloc(¶ms->targetBuffer, \
params->buffer_length*sizeof(int)))) return -1;
/*
createSequentialArray<<<params->nofBlocks,params->nofThreads>>>(*params);
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
if (CheckCUDAError(cudaMemcpy(params->hostBuffer, \
params->targetBuffer, \
params->buffer_length*sizeof(int), \
cudaMemcpyDeviceToHost))) return -1;
*/
#if 0
printArray(params->hostBuffer, params->buffer_length);
#endif
//allocate device times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMalloc(¶ms->target_times, \
size_time))) return -1;
//allocate host times
params->host_times = NULL;
params->host_times = (unsigned int *) malloc(size_time);
if (!params->host_times) {
perror("Failed allocating host_times buffer: ");
return -1;
}
memset(params->host_times,1, size_time);
// Allocate device accumulator
if (CheckCUDAError(hipMalloc(¶ms->target_realSum, \
sizeof(uint64_t)))) return -1;
// Allocate device measOH
if (CheckCUDAError(hipMalloc(¶ms->targetMeasOH, \
sizeof(unsigned int)))) return -1;
return 0;
}
static int runTest(param_t *params){
// Get measurement overhead
getMeasurementOverhead<<<1,1>>>(*params);
// Launch kernel
sequentialWalk<<<params->nofBlocks,params->nofThreads>>>(*params);
// Synchronize with device
if (CheckCUDAError(hipDeviceSynchronize())) return -1;
// Copyback times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMemcpy(params->host_times, \
params->target_times, \
size_time, \
hipMemcpyDeviceToHost))) return -1;
// Copyback sum
params->host_realSum=0;
if (CheckCUDAError(hipMemcpy(¶ms->host_realSum, \
params->target_realSum, \
sizeof(uint64_t), \
hipMemcpyDeviceToHost))) return -1;
// Copyback target meas oh
params->hostMeasOH=0;
if (CheckCUDAError(hipMemcpy(¶ms->hostMeasOH, \
params->targetMeasOH, \
sizeof(unsigned int), \
hipMemcpyDeviceToHost))) return -1;
return 0;
}
static int writeResults(param_t *params){
if (fprintf(params->fd,"{\n") < 0 ) return -1;
// Write device info
hipDeviceProp_t deviceProp;
if (CheckCUDAError(hipGetDeviceProperties(&deviceProp, DEVICE_NUMBER))) return -1;
int driverVersion = 0;
if (CheckCUDAError(hipDriverGetVersion(&driverVersion))) return -1;
int runtimeVersion = 0;
if (CheckCUDAError(hipRuntimeGetVersion(&runtimeVersion))) return -1;
if (fprintf(params->fd,"\"driverVer\": \"%d\",\n", driverVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"runTimeVer\": \"%d\",\n", runtimeVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"clockRate\": \"%d\",\n", deviceProp.clockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"globalL1CacheSupported\": \"%d\",\n", deviceProp.globalL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"localL1CacheSupported\": \"%d\",\n", deviceProp.localL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"l2CacheSize\": \"%d\",\n", deviceProp.l2CacheSize) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryBusWidth\": \"%d\",\n", deviceProp.memoryBusWidth) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryClockRate\": \"%d\",\n", deviceProp.memoryClockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"multiProcessorCount\": \"%d\",\n", deviceProp.multiProcessorCount) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerBlock\": \"%d\",\n", deviceProp.regsPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerMultiprocessor\": \"%d\",\n", deviceProp.regsPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerBlock\": \"%zu\",\n", deviceProp.sharedMemPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerMultiprocessor\": \"%zu\",\n", deviceProp.sharedMemPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"warpSize\": \"%d\",\n", deviceProp.warpSize) < 0 ) return -1;
hipFuncCache_t config;
if (CheckCUDAError(hipDeviceGetCacheConfig ( &config ) )) return -1;
if (fprintf(params->fd,"\"cacheConfig\": \"%d\",\n", config) < 0 ) return -1;
// Write header
if (fprintf(params->fd,"\"nofThreads\": \"%u\",\n", params->nofThreads) < 0 ) return -1;
if (fprintf(params->fd,"\"nofBlocks\": \"%u\",\n", params->nofBlocks) < 0 ) return -1;
if (fprintf(params->fd,"\"nof_repetitions\": \"%d\",\n", params->nof_repetitions) < 0 ) return -1;
if (fprintf(params->fd,"\"data_size\": \"%d\",\n", params->data_size) < 0 ) return -1;
if (fprintf(params->fd,"\"buffer_length\": \"%d\",\n", params->buffer_length) < 0 ) return -1;
if (fprintf(params->fd,"\"real_sum\": \"%llu\",\n", (unsigned long long)params->host_realSum) < 0 ) return -1;
if (fprintf(params->fd,"\"exp_sum\": \"%llu\",\n", ((unsigned long long)(params->buffer_length-1)*(unsigned long long)params->buffer_length)/2) < 0 ) return -1;
if (fprintf(params->fd,"\"measOH\": \"%u\",\n", params->hostMeasOH) < 0 ) return -1;
// Write times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks;
if (fprintf(params->fd,"\"times\":[\n") < 0 ) return -1;
for (int i = 0; i < size_time-1; i++){
if (fprintf(params->fd,"\"%u\",\n",params->host_times[i]) < 0 ) return -1;
}
if (fprintf(params->fd,"\"%u\"]\n}", params->host_times[size_time-1]) < 0 ) return -1;
if (fclose(params->fd) < 0) return -1;
return 0;
}
static int cleanUp(param_t *params){
// Free target buffers
hipFree(params->targetBuffer);
hipFree(params->target_times);
// Free host buffers
free(params->hostBuffer);
free(params->host_times);
return 0;
}
static void PrintUsage(const char *name) {
printf("Usage: %s <#threads> <#blocks> <# of intervals> <size in KB>"
"<output JSON file name>\n", name);
}
int main(int argc, char **argv) {
if (argc != 6) {
PrintUsage(argv[0]);
return 1;
}
param_t params;
// Parse input parameter
int nof_threads = atoi(argv[1]);
if (nof_threads <= 0) {
printf("Min one thread. Got %s threads\n", argv[1]);
return EXIT_FAILURE;
}
int nof_blocks = atoi(argv[2]);
if (nof_blocks <= 0) {
printf("Min 1 block. Got %s blocks\n", argv[2]);
return EXIT_FAILURE;
}
params.nofThreads = nof_threads;
params.nofBlocks = nof_blocks;
int nof_repetitions = atoi(argv[3]);
if (nof_repetitions <= 0) {
printf("More than 0 repetitions need to be used. Got %s repetitions\n", argv[3]);
return EXIT_FAILURE;
}
int data_size = atoi(argv[4]);
if (data_size <= 0) {
printf("The buffer must be 1 or more KB. Got %s KB\n", argv[4]);
return EXIT_FAILURE;
}
params.nof_repetitions = nof_repetitions;
params.data_size = data_size*1024;
params.buffer_length = data_size*1024/sizeof(int);
params.fd = NULL;
params.fd = fopen(argv[5],"w");
if (params.fd == NULL) {
perror("Error opening output file:");
return EXIT_FAILURE;
}
// Set CUDA device
if (CheckCUDAError(hipSetDevice(DEVICE_NUMBER))) {
return EXIT_FAILURE;
}
// Initialize parameters
if (initializeTest(¶ms) < 0) return EXIT_FAILURE;
// Run test
if (runTest(¶ms) < 0) return EXIT_FAILURE;
// Write results
if (writeResults(¶ms) < 0){
perror("Error while writing outpufile: ");
return EXIT_FAILURE;
}
// Clean up
if (cleanUp(¶ms) < 0) return EXIT_FAILURE;
printf("Finished testrun\n");
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL22getMeasurementOverhead7param_t,"axG",@progbits,_ZL22getMeasurementOverhead7param_t,comdat
.globl _ZL22getMeasurementOverhead7param_t
.p2align 8
.type _ZL22getMeasurementOverhead7param_t,@function
_ZL22getMeasurementOverhead7param_t:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x38
s_getreg_b32 s7, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_2
s_add_i32 s4, s6, -2
s_add_i32 s8, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s8, s4
s_mul_i32 s4, s8, s4
s_lshr_b64 s[4:5], s[4:5], 1
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, 0
s_branch .LBB0_3
.LBB0_2:
s_mov_b64 s[4:5], 0
.LBB0_3:
v_cvt_f32_u32_e32 v0, s6
s_sub_i32 s9, 0, s6
s_getreg_b32 s10, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
v_mov_b32_e32 v2, 0
s_sub_i32 s7, s10, s7
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s8, v0
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s7, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s6
s_sub_i32 s7, s7, s9
s_add_i32 s9, s8, 1
s_sub_i32 s10, s7, s6
s_cmp_ge_u32 s7, s6
s_cselect_b32 s8, s9, s8
s_cselect_b32 s7, s10, s7
s_add_i32 s9, s8, 1
s_cmp_ge_u32 s7, s6
s_cselect_b32 s6, s9, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s6
s_clause 0x1
global_store_b32 v2, v3, s[2:3]
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL22getMeasurementOverhead7param_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 96
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL22getMeasurementOverhead7param_t,"axG",@progbits,_ZL22getMeasurementOverhead7param_t,comdat
.Lfunc_end0:
.size _ZL22getMeasurementOverhead7param_t, .Lfunc_end0-_ZL22getMeasurementOverhead7param_t
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL14sequentialWalk7param_t,"axG",@progbits,_ZL14sequentialWalk7param_t,comdat
.globl _ZL14sequentialWalk7param_t
.p2align 8
.type _ZL14sequentialWalk7param_t,@function
_ZL14sequentialWalk7param_t:
s_load_b32 s10, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, -1
s_cbranch_scc1 .LBB1_8
s_clause 0x2
s_load_b32 s11, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x6c
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s11
s_sub_i32 s12, 0, s11
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s12, v4
v_mul_hi_u32 v3, v4, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x30
s_load_b64 s[8:9], s[0:1], 0x48
s_cselect_b32 s0, -1, 0
s_mov_b32 s1, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v4, v3
v_mul_lo_u32 v5, v1, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v1, v0
v_mul_lo_u32 v0, v0, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_subrev_nc_u32_e32 v2, s11, v0
v_cmp_le_u32_e32 vcc_lo, s11, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_cndmask_b32_e64 v2, 0, 1, s0
v_subrev_nc_u32_e32 v3, s11, v0
v_cmp_le_u32_e32 vcc_lo, s11, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s0, 1, v2
v_cndmask_b32_e32 v6, v0, v3, vcc_lo
s_branch .LBB1_3
.LBB1_2:
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s1, s10
s_cbranch_scc1 .LBB1_8
.LBB1_3:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s0
s_getreg_b32 s13, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_cbranch_vccnz .LBB1_6
v_mov_b32_e32 v2, v6
s_mov_b32 s14, s11
.LBB1_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_cbranch_scc0 .LBB1_5
.LBB1_6:
s_getreg_b32 s14, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_cmp_gt_i32 s1, -1
s_barrier
buffer_gl0_inv
global_store_b64 v7, v[0:1], s[6:7]
s_cbranch_scc0 .LBB1_2
global_load_b32 v2, v7, s[2:3]
v_readfirstlane_b32 s15, v4
s_sub_i32 s13, s14, s13
v_add_nc_u32_e32 v0, s1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s16, s12, s15
s_mul_hi_u32 s14, s15, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s15, s15, s14
s_mul_hi_u32 s14, s13, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s15, s14, s11
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_sub_i32 s13, s13, s15
s_add_i32 s15, s14, 1
s_sub_i32 s16, s13, s11
s_cmp_ge_u32 s13, s11
s_cselect_b32 s14, s15, s14
s_cselect_b32 s13, s16, s13
s_add_i32 s15, s14, 1
s_cmp_ge_u32 s13, s11
v_add_co_u32 v0, vcc_lo, s8, v0
s_cselect_b32 s13, s15, s14
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, s13, v2
global_store_b32 v[0:1], v2, off
s_branch .LBB1_2
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL14sequentialWalk7param_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL14sequentialWalk7param_t,"axG",@progbits,_ZL14sequentialWalk7param_t,comdat
.Lfunc_end1:
.size _ZL14sequentialWalk7param_t, .Lfunc_end1-_ZL14sequentialWalk7param_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 96
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 96
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL22getMeasurementOverhead7param_t
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _ZL22getMeasurementOverhead7param_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 96
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL14sequentialWalk7param_t
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _ZL14sequentialWalk7param_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <error.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define DEVICE_NUMBER (0)
typedef struct {
int nofThreads;
int nofBlocks;
int32_t nof_repetitions;
int data_size;
int buffer_length;
unsigned int *targetMeasOH;
unsigned int hostMeasOH;
int *hostBuffer;
int *targetBuffer;
uint64_t *target_realSum;
uint64_t host_realSum;
unsigned int *target_times;
unsigned int *host_times;
FILE *fd;
} param_t;
// Prints a message and returns zero if the given value is not cudaSuccess
#define CheckCUDAError(val) (InternalCheckCUDAError((val), #val, __FILE__, __LINE__))
// Called internally by CheckCUDAError
static int InternalCheckCUDAError(hipError_t result, const char *fn,
const char *file, int line) {
if (result == hipSuccess) return 0;
printf("CUDA error %d in %s, line %d (%s): %s\n", (int) result, file, line,
fn, hipGetErrorString(result));
return -1;
}
static void createSequentialArrayHost(param_t params){
// Link sequentially
for(int i = 0; i < params.buffer_length; i++){
params.hostBuffer[i]=(i+params.nofThreads*params.nofBlocks)%params.buffer_length;
}
}
static __global__ void getMeasurementOverhead(param_t params) {
unsigned int start, stop;
uint64_t sum = 0;
start = clock();
for (int j = 0; j < params.buffer_length; j++){
sum +=j;
}
stop = clock();
*params.targetMeasOH = (stop-start)/params.buffer_length;
*params.target_realSum = sum;
}
static __global__ void sequentialWalk(param_t params) {
int current;
unsigned int time_start, time_end, time_acc;
uint64_t sum;
int tindex = blockDim.x*blockIdx.x*params.nof_repetitions + params.nof_repetitions *threadIdx.x;
// Warm up data cache
for(int i = 0; i < params.buffer_length; i++){
sum += params.targetBuffer[i%params.buffer_length];
}
// Run experiment multiple times. First iteration (-1) is to warm up icache
for (int i = -2; i < params.nof_repetitions; i++){
sum = 0;
time_acc = 0;
current = (blockDim.x*blockIdx.x + threadIdx.x)%params.buffer_length;
__syncthreads();
time_start = clock();
// Strided access to array
for(int j = 0; j < params.buffer_length; j++){
current = params.targetBuffer[current];
sum += current;
}
time_end = clock();
time_acc += (time_end - time_start);
__syncthreads();
*params.target_realSum = sum;
// Do not write time for warm up iteration
if (i>=0){
// Write element access time with measurement overhead
params.target_times[tindex+i] = time_acc/params.buffer_length-(*params.targetMeasOH);
}
}
}
#if 0
static void printArray(int* buffer, int size){
printf("%d\n",size);
for( int row = 0; row <= ceil(size/10); row++){
for(int i = row*10; i< row*10+10 && i<size; i++)
printf("[%4d] ",i);
printf("\n");
for(int i = row*10; i< row*10+10 && i<size; i++)
printf(" %4d, ",buffer[i]);
printf("\n");
}
}
#endif
static int initializeTest(param_t *params){
//allocate buffer
params->hostBuffer = NULL;
params->hostBuffer = (int *) malloc(params->buffer_length*sizeof(int));
if (!params->hostBuffer) {
perror("Failed allocating host buffer: ");
return -1;
}
createSequentialArrayHost(*params);
//allocate device random buffer
if (CheckCUDAError(hipMalloc(¶ms->targetBuffer, \
params->buffer_length*sizeof(int)))) return -1;
/*
createSequentialArray<<<params->nofBlocks,params->nofThreads>>>(*params);
if (CheckCUDAError(cudaDeviceSynchronize())) return -1;
if (CheckCUDAError(cudaMemcpy(params->hostBuffer, \
params->targetBuffer, \
params->buffer_length*sizeof(int), \
cudaMemcpyDeviceToHost))) return -1;
*/
#if 0
printArray(params->hostBuffer, params->buffer_length);
#endif
//allocate device times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMalloc(¶ms->target_times, \
size_time))) return -1;
//allocate host times
params->host_times = NULL;
params->host_times = (unsigned int *) malloc(size_time);
if (!params->host_times) {
perror("Failed allocating host_times buffer: ");
return -1;
}
memset(params->host_times,1, size_time);
// Allocate device accumulator
if (CheckCUDAError(hipMalloc(¶ms->target_realSum, \
sizeof(uint64_t)))) return -1;
// Allocate device measOH
if (CheckCUDAError(hipMalloc(¶ms->targetMeasOH, \
sizeof(unsigned int)))) return -1;
return 0;
}
static int runTest(param_t *params){
// Get measurement overhead
getMeasurementOverhead<<<1,1>>>(*params);
// Launch kernel
sequentialWalk<<<params->nofBlocks,params->nofThreads>>>(*params);
// Synchronize with device
if (CheckCUDAError(hipDeviceSynchronize())) return -1;
// Copyback times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks \
* sizeof(unsigned int);
if (CheckCUDAError(hipMemcpy(params->host_times, \
params->target_times, \
size_time, \
hipMemcpyDeviceToHost))) return -1;
// Copyback sum
params->host_realSum=0;
if (CheckCUDAError(hipMemcpy(¶ms->host_realSum, \
params->target_realSum, \
sizeof(uint64_t), \
hipMemcpyDeviceToHost))) return -1;
// Copyback target meas oh
params->hostMeasOH=0;
if (CheckCUDAError(hipMemcpy(¶ms->hostMeasOH, \
params->targetMeasOH, \
sizeof(unsigned int), \
hipMemcpyDeviceToHost))) return -1;
return 0;
}
static int writeResults(param_t *params){
if (fprintf(params->fd,"{\n") < 0 ) return -1;
// Write device info
hipDeviceProp_t deviceProp;
if (CheckCUDAError(hipGetDeviceProperties(&deviceProp, DEVICE_NUMBER))) return -1;
int driverVersion = 0;
if (CheckCUDAError(hipDriverGetVersion(&driverVersion))) return -1;
int runtimeVersion = 0;
if (CheckCUDAError(hipRuntimeGetVersion(&runtimeVersion))) return -1;
if (fprintf(params->fd,"\"driverVer\": \"%d\",\n", driverVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"runTimeVer\": \"%d\",\n", runtimeVersion) < 0 ) return -1;
if (fprintf(params->fd,"\"clockRate\": \"%d\",\n", deviceProp.clockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"globalL1CacheSupported\": \"%d\",\n", deviceProp.globalL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"localL1CacheSupported\": \"%d\",\n", deviceProp.localL1CacheSupported) < 0 ) return -1;
if (fprintf(params->fd,"\"l2CacheSize\": \"%d\",\n", deviceProp.l2CacheSize) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryBusWidth\": \"%d\",\n", deviceProp.memoryBusWidth) < 0 ) return -1;
if (fprintf(params->fd,"\"memoryClockRate\": \"%d\",\n", deviceProp.memoryClockRate) < 0 ) return -1;
if (fprintf(params->fd,"\"multiProcessorCount\": \"%d\",\n", deviceProp.multiProcessorCount) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerBlock\": \"%d\",\n", deviceProp.regsPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"regsPerMultiprocessor\": \"%d\",\n", deviceProp.regsPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerBlock\": \"%zu\",\n", deviceProp.sharedMemPerBlock) < 0 ) return -1;
if (fprintf(params->fd,"\"sharedMemPerMultiprocessor\": \"%zu\",\n", deviceProp.sharedMemPerMultiprocessor) < 0 ) return -1;
if (fprintf(params->fd,"\"warpSize\": \"%d\",\n", deviceProp.warpSize) < 0 ) return -1;
hipFuncCache_t config;
if (CheckCUDAError(hipDeviceGetCacheConfig ( &config ) )) return -1;
if (fprintf(params->fd,"\"cacheConfig\": \"%d\",\n", config) < 0 ) return -1;
// Write header
if (fprintf(params->fd,"\"nofThreads\": \"%u\",\n", params->nofThreads) < 0 ) return -1;
if (fprintf(params->fd,"\"nofBlocks\": \"%u\",\n", params->nofBlocks) < 0 ) return -1;
if (fprintf(params->fd,"\"nof_repetitions\": \"%d\",\n", params->nof_repetitions) < 0 ) return -1;
if (fprintf(params->fd,"\"data_size\": \"%d\",\n", params->data_size) < 0 ) return -1;
if (fprintf(params->fd,"\"buffer_length\": \"%d\",\n", params->buffer_length) < 0 ) return -1;
if (fprintf(params->fd,"\"real_sum\": \"%llu\",\n", (unsigned long long)params->host_realSum) < 0 ) return -1;
if (fprintf(params->fd,"\"exp_sum\": \"%llu\",\n", ((unsigned long long)(params->buffer_length-1)*(unsigned long long)params->buffer_length)/2) < 0 ) return -1;
if (fprintf(params->fd,"\"measOH\": \"%u\",\n", params->hostMeasOH) < 0 ) return -1;
// Write times
int size_time = params->nof_repetitions \
* params->nofThreads \
* params->nofBlocks;
if (fprintf(params->fd,"\"times\":[\n") < 0 ) return -1;
for (int i = 0; i < size_time-1; i++){
if (fprintf(params->fd,"\"%u\",\n",params->host_times[i]) < 0 ) return -1;
}
if (fprintf(params->fd,"\"%u\"]\n}", params->host_times[size_time-1]) < 0 ) return -1;
if (fclose(params->fd) < 0) return -1;
return 0;
}
static int cleanUp(param_t *params){
// Free target buffers
hipFree(params->targetBuffer);
hipFree(params->target_times);
// Free host buffers
free(params->hostBuffer);
free(params->host_times);
return 0;
}
static void PrintUsage(const char *name) {
printf("Usage: %s <#threads> <#blocks> <# of intervals> <size in KB>"
"<output JSON file name>\n", name);
}
int main(int argc, char **argv) {
if (argc != 6) {
PrintUsage(argv[0]);
return 1;
}
param_t params;
// Parse input parameter
int nof_threads = atoi(argv[1]);
if (nof_threads <= 0) {
printf("Min one thread. Got %s threads\n", argv[1]);
return EXIT_FAILURE;
}
int nof_blocks = atoi(argv[2]);
if (nof_blocks <= 0) {
printf("Min 1 block. Got %s blocks\n", argv[2]);
return EXIT_FAILURE;
}
params.nofThreads = nof_threads;
params.nofBlocks = nof_blocks;
int nof_repetitions = atoi(argv[3]);
if (nof_repetitions <= 0) {
printf("More than 0 repetitions need to be used. Got %s repetitions\n", argv[3]);
return EXIT_FAILURE;
}
int data_size = atoi(argv[4]);
if (data_size <= 0) {
printf("The buffer must be 1 or more KB. Got %s KB\n", argv[4]);
return EXIT_FAILURE;
}
params.nof_repetitions = nof_repetitions;
params.data_size = data_size*1024;
params.buffer_length = data_size*1024/sizeof(int);
params.fd = NULL;
params.fd = fopen(argv[5],"w");
if (params.fd == NULL) {
perror("Error opening output file:");
return EXIT_FAILURE;
}
// Set CUDA device
if (CheckCUDAError(hipSetDevice(DEVICE_NUMBER))) {
return EXIT_FAILURE;
}
// Initialize parameters
if (initializeTest(¶ms) < 0) return EXIT_FAILURE;
// Run test
if (runTest(¶ms) < 0) return EXIT_FAILURE;
// Write results
if (writeResults(¶ms) < 0){
perror("Error while writing outpufile: ");
return EXIT_FAILURE;
}
// Clean up
if (cleanUp(¶ms) < 0) return EXIT_FAILURE;
printf("Finished testrun\n");
hipDeviceReset();
return 0;
} | .text
.file "sequential-walk.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $6, %edi
jne .LBB0_8
# %bb.1:
movq 8(%rbx), %r15
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB0_9
# %bb.2:
movq 16(%rbx), %r15
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB0_10
# %bb.3:
movl %r14d, (%rsp)
movl %eax, 4(%rsp)
movq 24(%rbx), %r15
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB0_11
# %bb.4:
movq 32(%rbx), %r15
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB0_12
# %bb.5:
movl %r14d, 8(%rsp)
shll $10, %eax
movl %eax, 12(%rsp)
shrl $2, %eax
movl %eax, 16(%rsp)
movq $0, 88(%rsp)
movq 40(%rbx), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, 88(%rsp)
testq %rax, %rax
je .LBB0_25
# %bb.6:
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB0_17
# %bb.7: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.6, %r8d
movl %ebx, %esi
movl $323, %ecx # imm = 0x143
jmp .LBB0_33
.LBB0_8:
movq (%rbx), %rsi
movl $.L.str.10, %edi
jmp .LBB0_14
.LBB0_9:
movl $.L.str, %edi
jmp .LBB0_13
.LBB0_10:
movl $.L.str.1, %edi
jmp .LBB0_13
.LBB0_11:
movl $.L.str.2, %edi
jmp .LBB0_13
.LBB0_12:
movl $.L.str.3, %edi
.LBB0_13: # %.critedge25
movq %r15, %rsi
.LBB0_14:
xorl %eax, %eax
callq printf
.LBB0_15:
movl $1, %eax
.LBB0_16:
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_17: # %.critedge
.cfi_def_cfa_offset 128
movq $0, 40(%rsp)
movslq 16(%rsp), %r14
leaq (,%r14,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 40(%rsp)
testq %rax, %rax
je .LBB0_29
# %bb.18:
movl %r14d, %esi
leaq 48(%rsp), %rdi
testl %esi, %esi
jle .LBB0_21
# %bb.19: # %.lr.ph.i.i
movq %rax, %rcx
movl (%rsp), %r8d
imull 4(%rsp), %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_20: # =>This Inner Loop Header: Depth=1
leal (%r8,%r9), %eax
cltd
idivl %esi
movl %edx, (%rcx,%r9,4)
incq %r9
cmpq %r9, %rsi
jne .LBB0_20
.LBB0_21: # %_ZL25createSequentialArrayHost7param_t.exit.i
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_23
# %bb.22: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit.i
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.13, %r8d
movl %ebx, %esi
movl $126, %ecx
jmp .LBB0_33
.LBB0_23: # %.critedge.i
movl 8(%rsp), %eax
imull (%rsp), %eax
imull 4(%rsp), %eax
shll $2, %eax
leaq 72(%rsp), %rdi
movslq %eax, %rbx
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_26
# %bb.24: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit27.i
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.14, %r8d
movl %ebx, %esi
movl $146, %ecx
jmp .LBB0_33
.LBB0_25:
movl $.L.str.5, %edi
jmp .LBB0_30
.LBB0_26: # %.critedge39.i
movq $0, 80(%rsp)
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp)
testq %rax, %rax
je .LBB0_37
# %bb.27:
movq %rax, %rdi
movl $1, %esi
movq %rbx, %rdx
callq memset@PLT
leaq 56(%rsp), %rdi
movl $8, %esi
callq hipMalloc
testl %eax, %eax
je .LBB0_31
# %bb.28: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit29.i
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.16, %r8d
movl %ebx, %esi
movl $159, %ecx
jmp .LBB0_33
.LBB0_29:
movl $.L.str.12, %edi
.LBB0_30: # %.critedge25
callq perror
jmp .LBB0_15
.LBB0_31: # %.critedge40.i
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
je .LBB0_34
# %bb.32: # %_ZL14initializeTestP7param_t.exit
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.17, %r8d
movl %ebx, %esi
movl $163, %ecx
.LBB0_33: # %.critedge25
movq %rax, %r9
xorl %eax, %eax
callq printf
jmp .LBB0_15
.LBB0_34: # %.critedge26
movq %rsp, %rdi
callq _ZL7runTestP7param_t
testl %eax, %eax
js .LBB0_15
# %bb.35:
movq %rsp, %rdi
callq _ZL12writeResultsP7param_t
testl %eax, %eax
js .LBB0_39
# %bb.36:
movq %rsp, %rdi
callq _ZL7cleanUpP7param_t
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
jmp .LBB0_16
.LBB0_37:
movl $.L.str.15, %edi
jmp .LBB0_30
.LBB0_39:
movl $.L.str.8, %edi
jmp .LBB0_30
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL22InternalCheckCUDAError10hipError_tPKcS1_i
.type _ZL22InternalCheckCUDAError10hipError_tPKcS1_i,@function
_ZL22InternalCheckCUDAError10hipError_tPKcS1_i: # @_ZL22InternalCheckCUDAError10hipError_tPKcS1_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB1_1
# %bb.2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movl %edi, %r14d
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl %r14d, %esi
movl %ebp, %ecx
movq %rbx, %r8
movq %rax, %r9
xorl %eax, %eax
callq printf
movl $-1, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
retq
.LBB1_1:
xorl %eax, %eax
retq
.Lfunc_end1:
.size _ZL22InternalCheckCUDAError10hipError_tPKcS1_i, .Lfunc_end1-_ZL22InternalCheckCUDAError10hipError_tPKcS1_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7runTestP7param_t
.type _ZL7runTestP7param_t,@function
_ZL7runTestP7param_t: # @_ZL7runTestP7param_t
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 1(%r14), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movups 80(%rbx), %xmm0
movaps %xmm0, 144(%rsp)
movups 64(%rbx), %xmm0
movaps %xmm0, 128(%rsp)
movups (%rbx), %xmm0
movups 16(%rbx), %xmm1
movups 32(%rbx), %xmm2
movups 48(%rbx), %xmm3
movaps %xmm3, 112(%rsp)
movaps %xmm2, 96(%rsp)
movaps %xmm1, 80(%rsp)
movaps %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_ZL22getMeasurementOverhead7param_t, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl (%rbx), %edx
movl 4(%rbx), %edi
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movups 80(%rbx), %xmm0
movaps %xmm0, 144(%rsp)
movups 64(%rbx), %xmm0
movaps %xmm0, 128(%rsp)
movups (%rbx), %xmm0
movups 16(%rbx), %xmm1
movups 32(%rbx), %xmm2
movups 48(%rbx), %xmm3
movaps %xmm3, 112(%rsp)
movaps %xmm2, 96(%rsp)
movaps %xmm1, 80(%rsp)
movaps %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_ZL14sequentialWalk7param_t, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_7
# %bb.5: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.18, %r8d
movl %ebx, %esi
movl $175, %ecx
jmp .LBB2_6
.LBB2_7: # %.critedge
movl 8(%rbx), %eax
imull (%rbx), %eax
imull 4(%rbx), %eax
shll $2, %eax
movq 80(%rbx), %rdi
movq 72(%rbx), %rsi
movslq %eax, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_9
# %bb.8: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit34
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.19, %r8d
movl %ebx, %esi
movl $186, %ecx
jmp .LBB2_6
.LBB2_9: # %.critedge48
leaq 64(%rbx), %rdi
movq $0, 64(%rbx)
movq 56(%rbx), %rsi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_11
# %bb.10: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit36
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.20, %r8d
movl %ebx, %esi
movl $193, %ecx
.LBB2_6:
movq %rax, %r9
xorl %eax, %eax
callq printf
movl $-1, %eax
.LBB2_14:
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11: # %.critedge49
.cfi_def_cfa_offset 192
leaq 32(%rbx), %rdi
movl $0, 32(%rbx)
movq 24(%rbx), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %ebx
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.21, %r8d
movl %ebx, %esi
movl $200, %ecx
movq %rax, %r9
xorl %eax, %eax
callq printf
.LBB2_13: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit38
xorl %eax, %eax
negl %ebx
sbbl %eax, %eax
jmp .LBB2_14
.Lfunc_end2:
.size _ZL7runTestP7param_t, .Lfunc_end2-_ZL7runTestP7param_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL12writeResultsP7param_t
.type _ZL12writeResultsP7param_t,@function
_ZL12writeResultsP7param_t: # @_ZL12writeResultsP7param_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq 88(%rdi), %rdi
movl $.L.str.22, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.1:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB3_4
# %bb.2: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.23, %r8d
movl %ebx, %esi
movl $209, %ecx
jmp .LBB3_8
.LBB3_4: # %.critedge58
movl $0, 8(%rsp)
leaq 8(%rsp), %rdi
callq hipDriverGetVersion
testl %eax, %eax
je .LBB3_6
# %bb.5: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit55
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.24, %r8d
movl %ebx, %esi
movl $211, %ecx
jmp .LBB3_8
.LBB3_6: # %.critedge59
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipRuntimeGetVersion
testl %eax, %eax
je .LBB3_11
# %bb.7: # %_ZL22InternalCheckCUDAError10hipError_tPKcS1_i.exit57
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.11, %edi
movl $.L.str.7, %edx
movl $.L.str.25, %r8d
movl %ebx, %esi
movl $213, %ecx
.LBB3_8:
movq %rax, %r9
xorl %eax, %eax
callq printf
.LBB3_9:
movl $-1, %eax
.LBB3_10:
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_11: # %.critedge60
.cfi_def_cfa_offset 1536
movq 88(%rbx), %rdi
movl 8(%rsp), %edx
movl $.L.str.26, %esi
xorl %eax, %eax
callq fprintf
movl %eax, %ecx
movl $-1, %eax
testl %ecx, %ecx
js .LBB3_10
# %bb.12:
movq 88(%rbx), %rdi
movl 4(%rsp), %edx
movl $.L.str.27, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.13:
movq 88(%rbx), %rdi
movl 364(%rsp), %edx
movl $.L.str.28, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.14:
movq 88(%rbx), %rdi
movl 648(%rsp), %edx
movl $.L.str.29, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.15:
movq 88(%rbx), %rdi
movl 652(%rsp), %edx
movl $.L.str.30, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.16:
movq 88(%rbx), %rdi
movl 632(%rsp), %edx
movl $.L.str.31, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.17:
movq 88(%rbx), %rdi
movl 628(%rsp), %edx
movl $.L.str.32, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.18:
movq 88(%rbx), %rdi
movl 624(%rsp), %edx
movl $.L.str.33, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.19:
movq 88(%rbx), %rdi
movl 404(%rsp), %edx
movl $.L.str.34, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.20:
movq 88(%rbx), %rdi
movl 320(%rsp), %edx
movl $.L.str.35, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.21:
movq 88(%rbx), %rdi
movl 664(%rsp), %edx
movl $.L.str.36, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.22:
movq 88(%rbx), %rdi
movq 312(%rsp), %rdx
movl $.L.str.37, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.23:
movq 88(%rbx), %rdi
movq 656(%rsp), %rdx
movl $.L.str.38, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_9
# %bb.24:
movq 88(%rbx), %rdi
movl 324(%rsp), %edx
movl $.L.str.39, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
movl $-1, %eax
js .LBB3_10
# %bb.25:
leaq 12(%rsp), %rdi
callq hipDeviceGetCacheConfig
movl $.L.str.40, %esi
movl %eax, %edi
movl $230, %edx
callq _ZL22InternalCheckCUDAError10hipError_tPKcS1_i
movl $-1, %ebp
testl %eax, %eax
je .LBB3_39
.LBB3_26: # %.loopexit
movl %ebp, %eax
jmp .LBB3_10
.LBB3_39:
movq 88(%rbx), %rdi
movl 12(%rsp), %edx
movl $.L.str.41, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.40:
movq 88(%rbx), %rdi
movl (%rbx), %edx
movl $.L.str.42, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.41:
movq 88(%rbx), %rdi
movl 4(%rbx), %edx
movl $.L.str.43, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.42:
movq 88(%rbx), %rdi
movl 8(%rbx), %edx
movl $.L.str.44, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.43:
movq 88(%rbx), %rdi
movl 12(%rbx), %edx
movl $.L.str.45, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.44:
movq 88(%rbx), %rdi
movl 16(%rbx), %edx
movl $.L.str.46, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.45:
movq 64(%rbx), %rdx
movq 88(%rbx), %rdi
movl $.L.str.47, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.46:
movq 88(%rbx), %rdi
movslq 16(%rbx), %rax
leaq -1(%rax), %rdx
imulq %rax, %rdx
shrq %rdx
movl $.L.str.48, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.47:
movq 88(%rbx), %rdi
movl 32(%rbx), %edx
movl $.L.str.49, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.48:
movl 8(%rbx), %r14d
movl (%rbx), %r15d
movl 4(%rbx), %r12d
movq 88(%rbx), %rdi
movl $.L.str.50, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.49: # %.preheader
imull %r14d, %r15d
imull %r12d, %r15d
leal -1(%r15), %r14d
cmpl $2, %r15d
jl .LBB3_53
# %bb.50: # %.lr.ph
movl %r14d, %r15d
xorl %r12d, %r12d
.LBB3_51: # =>This Inner Loop Header: Depth=1
movq 80(%rbx), %rax
movq 88(%rbx), %rdi
movl (%rax,%r12,4), %edx
movl $.L.str.51, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.52: # in Loop: Header=BB3_51 Depth=1
incq %r12
cmpq %r12, %r15
jne .LBB3_51
.LBB3_53: # %.critedge
movq 80(%rbx), %rax
movq 88(%rbx), %rdi
movslq %r14d, %rcx
movl (%rax,%rcx,4), %edx
movl $.L.str.52, %esi
xorl %eax, %eax
callq fprintf
testl %eax, %eax
js .LBB3_26
# %bb.54:
movq 88(%rbx), %rdi
callq fclose
sarl $31, %eax
movl %eax, %ebp
jmp .LBB3_26
.Lfunc_end3:
.size _ZL12writeResultsP7param_t, .Lfunc_end3-_ZL12writeResultsP7param_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL7cleanUpP7param_t
.type _ZL7cleanUpP7param_t,@function
_ZL7cleanUpP7param_t: # @_ZL7cleanUpP7param_t
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 48(%rdi), %rdi
callq hipFree
movq 72(%rbx), %rdi
callq hipFree
movq 40(%rbx), %rdi
callq free
movq 80(%rbx), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end4:
.size _ZL7cleanUpP7param_t, .Lfunc_end4-_ZL7cleanUpP7param_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL37__device_stub__getMeasurementOverhead7param_t
.type _ZL37__device_stub__getMeasurementOverhead7param_t,@function
_ZL37__device_stub__getMeasurementOverhead7param_t: # @_ZL37__device_stub__getMeasurementOverhead7param_t
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_ZL22getMeasurementOverhead7param_t, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _ZL37__device_stub__getMeasurementOverhead7param_t, .Lfunc_end5-_ZL37__device_stub__getMeasurementOverhead7param_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL29__device_stub__sequentialWalk7param_t
.type _ZL29__device_stub__sequentialWalk7param_t,@function
_ZL29__device_stub__sequentialWalk7param_t: # @_ZL29__device_stub__sequentialWalk7param_t
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_ZL14sequentialWalk7param_t, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end6:
.size _ZL29__device_stub__sequentialWalk7param_t, .Lfunc_end6-_ZL29__device_stub__sequentialWalk7param_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL22getMeasurementOverhead7param_t, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL14sequentialWalk7param_t, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Min one thread. Got %s threads\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Min 1 block. Got %s blocks\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "More than 0 repetitions need to be used. Got %s repetitions\n"
.size .L.str.2, 61
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The buffer must be 1 or more KB. Got %s KB\n"
.size .L.str.3, 44
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "w"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error opening output file:"
.size .L.str.5, 27
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipSetDevice(DEVICE_NUMBER)"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/realentertain/tt-gpu/master/experiments/sequential-walk-multithread/sequential-walk.hip"
.size .L.str.7, 145
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error while writing outpufile: "
.size .L.str.8, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Usage: %s <#threads> <#blocks> <# of intervals> <size in KB><output JSON file name>\n"
.size .L.str.10, 85
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CUDA error %d in %s, line %d (%s): %s\n"
.size .L.str.11, 39
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed allocating host buffer: "
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMalloc(¶ms->targetBuffer, params->buffer_length*sizeof(int))"
.size .L.str.13, 68
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hipMalloc(¶ms->target_times, size_time)"
.size .L.str.14, 44
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed allocating host_times buffer: "
.size .L.str.15, 38
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "hipMalloc(¶ms->target_realSum, sizeof(uint64_t))"
.size .L.str.16, 53
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "hipMalloc(¶ms->targetMeasOH, sizeof(unsigned int))"
.size .L.str.17, 55
.type _ZL22getMeasurementOverhead7param_t,@object # @_ZL22getMeasurementOverhead7param_t
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL22getMeasurementOverhead7param_t:
.quad _ZL37__device_stub__getMeasurementOverhead7param_t
.size _ZL22getMeasurementOverhead7param_t, 8
.type _ZL14sequentialWalk7param_t,@object # @_ZL14sequentialWalk7param_t
.p2align 3, 0x0
_ZL14sequentialWalk7param_t:
.quad _ZL29__device_stub__sequentialWalk7param_t
.size _ZL14sequentialWalk7param_t, 8
.type .L.str.18,@object # @.str.18
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.18:
.asciz "hipDeviceSynchronize()"
.size .L.str.18, 23
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "hipMemcpy(params->host_times, params->target_times, size_time, hipMemcpyDeviceToHost)"
.size .L.str.19, 86
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "hipMemcpy(¶ms->host_realSum, params->target_realSum, sizeof(uint64_t), hipMemcpyDeviceToHost)"
.size .L.str.20, 98
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "hipMemcpy(¶ms->hostMeasOH, params->targetMeasOH, sizeof(unsigned int), hipMemcpyDeviceToHost)"
.size .L.str.21, 98
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "{\n"
.size .L.str.22, 3
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "hipGetDeviceProperties(&deviceProp, DEVICE_NUMBER)"
.size .L.str.23, 51
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "hipDriverGetVersion(&driverVersion)"
.size .L.str.24, 36
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "hipRuntimeGetVersion(&runtimeVersion)"
.size .L.str.25, 38
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "\"driverVer\": \"%d\",\n"
.size .L.str.26, 20
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "\"runTimeVer\": \"%d\",\n"
.size .L.str.27, 21
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "\"clockRate\": \"%d\",\n"
.size .L.str.28, 20
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "\"globalL1CacheSupported\": \"%d\",\n"
.size .L.str.29, 33
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "\"localL1CacheSupported\": \"%d\",\n"
.size .L.str.30, 32
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "\"l2CacheSize\": \"%d\",\n"
.size .L.str.31, 22
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "\"memoryBusWidth\": \"%d\",\n"
.size .L.str.32, 25
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "\"memoryClockRate\": \"%d\",\n"
.size .L.str.33, 26
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz "\"multiProcessorCount\": \"%d\",\n"
.size .L.str.34, 30
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz "\"regsPerBlock\": \"%d\",\n"
.size .L.str.35, 23
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz "\"regsPerMultiprocessor\": \"%d\",\n"
.size .L.str.36, 32
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz "\"sharedMemPerBlock\": \"%zu\",\n"
.size .L.str.37, 29
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz "\"sharedMemPerMultiprocessor\": \"%zu\",\n"
.size .L.str.38, 38
.type .L.str.39,@object # @.str.39
.L.str.39:
.asciz "\"warpSize\": \"%d\",\n"
.size .L.str.39, 19
.type .L.str.40,@object # @.str.40
.L.str.40:
.asciz "hipDeviceGetCacheConfig ( &config )"
.size .L.str.40, 36
.type .L.str.41,@object # @.str.41
.L.str.41:
.asciz "\"cacheConfig\": \"%d\",\n"
.size .L.str.41, 22
.type .L.str.42,@object # @.str.42
.L.str.42:
.asciz "\"nofThreads\": \"%u\",\n"
.size .L.str.42, 21
.type .L.str.43,@object # @.str.43
.L.str.43:
.asciz "\"nofBlocks\": \"%u\",\n"
.size .L.str.43, 20
.type .L.str.44,@object # @.str.44
.L.str.44:
.asciz "\"nof_repetitions\": \"%d\",\n"
.size .L.str.44, 26
.type .L.str.45,@object # @.str.45
.L.str.45:
.asciz "\"data_size\": \"%d\",\n"
.size .L.str.45, 20
.type .L.str.46,@object # @.str.46
.L.str.46:
.asciz "\"buffer_length\": \"%d\",\n"
.size .L.str.46, 24
.type .L.str.47,@object # @.str.47
.L.str.47:
.asciz "\"real_sum\": \"%llu\",\n"
.size .L.str.47, 21
.type .L.str.48,@object # @.str.48
.L.str.48:
.asciz "\"exp_sum\": \"%llu\",\n"
.size .L.str.48, 20
.type .L.str.49,@object # @.str.49
.L.str.49:
.asciz "\"measOH\": \"%u\",\n"
.size .L.str.49, 17
.type .L.str.50,@object # @.str.50
.L.str.50:
.asciz "\"times\":[\n"
.size .L.str.50, 11
.type .L.str.51,@object # @.str.51
.L.str.51:
.asciz "\"%u\",\n"
.size .L.str.51, 7
.type .L.str.52,@object # @.str.52
.L.str.52:
.asciz "\"%u\"]\n}"
.size .L.str.52, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL22getMeasurementOverhead7param_t"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL14sequentialWalk7param_t"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finished testrun"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL37__device_stub__getMeasurementOverhead7param_t
.addrsig_sym _ZL29__device_stub__sequentialWalk7param_t
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL22getMeasurementOverhead7param_t
.addrsig_sym _ZL14sequentialWalk7param_t
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} | code for sm_80
Function : _Z7gAddRowPfPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00a0*/ IADD3 R5, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x001fe20007ffe0ff */
/*00b0*/ IMAD R7, R8, c[0x0][0xc], R7 ; /* 0x0000030008077a24 */
/* 0x000fe200078e0207 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*00d0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc40003f06270 */
/*00e0*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fd60003f26270 */
/*00f0*/ @P0 BRA 0x170 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R5, R4, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R9, R6, R3 ; /* 0x0000000306097221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ @!P1 BRA 0xa0 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} | .file "tmpxft_0014d184_00000000-6_gAddRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
.type _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi, @function
_Z30__device_stub__Z7gAddRowPfPKfiPfPKfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7gAddRowPfPKfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi, .-_Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
.globl _Z7gAddRowPfPKfi
.type _Z7gAddRowPfPKfi, @function
_Z7gAddRowPfPKfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7gAddRowPfPKfi, .-_Z7gAddRowPfPKfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7gAddRowPfPKfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gAddRowPfPKfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gAddRowPfPKfi
.globl _Z7gAddRowPfPKfi
.p2align 8
.type _Z7gAddRowPfPKfi,@function
_Z7gAddRowPfPKfi:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s6, s4
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s6, v1
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gAddRowPfPKfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gAddRowPfPKfi, .Lfunc_end0-_Z7gAddRowPfPKfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gAddRowPfPKfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gAddRowPfPKfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gAddRow(float* out, const float* in, int length) {
for(int bid = 0; bid < length; bid += blockDim.x * gridDim.x) {
int index = bid + blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
out[index] = in[index] + out[index];
}
}
} | .text
.file "gAddRow.hip"
.globl _Z22__device_stub__gAddRowPfPKfi # -- Begin function _Z22__device_stub__gAddRowPfPKfi
.p2align 4, 0x90
.type _Z22__device_stub__gAddRowPfPKfi,@function
_Z22__device_stub__gAddRowPfPKfi: # @_Z22__device_stub__gAddRowPfPKfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7gAddRowPfPKfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__gAddRowPfPKfi, .Lfunc_end0-_Z22__device_stub__gAddRowPfPKfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gAddRowPfPKfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gAddRowPfPKfi,@object # @_Z7gAddRowPfPKfi
.section .rodata,"a",@progbits
.globl _Z7gAddRowPfPKfi
.p2align 3, 0x0
_Z7gAddRowPfPKfi:
.quad _Z22__device_stub__gAddRowPfPKfi
.size _Z7gAddRowPfPKfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7gAddRowPfPKfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gAddRowPfPKfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gAddRowPfPKfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7gAddRowPfPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x170] ; /* 0x00005c0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00a0*/ IADD3 R5, R0, R7, RZ ; /* 0x0000000700057210 */
/* 0x001fe20007ffe0ff */
/*00b0*/ IMAD R7, R8, c[0x0][0xc], R7 ; /* 0x0000030008077a24 */
/* 0x000fe200078e0207 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*00d0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc40003f06270 */
/*00e0*/ ISETP.GE.AND P1, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fd60003f26270 */
/*00f0*/ @P0 BRA 0x170 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.WIDE R2, R5, R4, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0204 */
/*0120*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FADD R9, R6, R3 ; /* 0x0000000306097221 */
/* 0x004fca0000000000 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ @!P1 BRA 0xa0 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gAddRowPfPKfi
.globl _Z7gAddRowPfPKfi
.p2align 8
.type _Z7gAddRowPfPKfi,@function
_Z7gAddRowPfPKfi:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s6, s4
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s6, v1
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gAddRowPfPKfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gAddRowPfPKfi, .Lfunc_end0-_Z7gAddRowPfPKfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gAddRowPfPKfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gAddRowPfPKfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d184_00000000-6_gAddRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
.type _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi, @function
_Z30__device_stub__Z7gAddRowPfPKfiPfPKfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7gAddRowPfPKfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi, .-_Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
.globl _Z7gAddRowPfPKfi
.type _Z7gAddRowPfPKfi, @function
_Z7gAddRowPfPKfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7gAddRowPfPKfiPfPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7gAddRowPfPKfi, .-_Z7gAddRowPfPKfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7gAddRowPfPKfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gAddRowPfPKfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gAddRow.hip"
.globl _Z22__device_stub__gAddRowPfPKfi # -- Begin function _Z22__device_stub__gAddRowPfPKfi
.p2align 4, 0x90
.type _Z22__device_stub__gAddRowPfPKfi,@function
_Z22__device_stub__gAddRowPfPKfi: # @_Z22__device_stub__gAddRowPfPKfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7gAddRowPfPKfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__gAddRowPfPKfi, .Lfunc_end0-_Z22__device_stub__gAddRowPfPKfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gAddRowPfPKfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gAddRowPfPKfi,@object # @_Z7gAddRowPfPKfi
.section .rodata,"a",@progbits
.globl _Z7gAddRowPfPKfi
.p2align 3, 0x0
_Z7gAddRowPfPKfi:
.quad _Z22__device_stub__gAddRowPfPKfi
.size _Z7gAddRowPfPKfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7gAddRowPfPKfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gAddRowPfPKfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gAddRowPfPKfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define TILE_WIDTH 16
__global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns)
{
int i = TILE_WIDTH * blockIdx.y + threadIdx.y;
int j = TILE_WIDTH * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
c[i * columns + j] = a[i * columns + j] + b[i * columns + j];
}
int m_add(int *a, int *b, int *c, int rows, int columns)
{
int *da,
*db,
*dc,
size = rows * columns * sizeof(int);
cudaMalloc((void **)&da, size);
cudaMalloc((void **)&db, size);
cudaMalloc((void **)&dc, size);
cudaMemcpy(da, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(db, b, size, cudaMemcpyHostToDevice);
dim3 dimGrid(ceil((float)columns / TILE_WIDTH),
ceil((float)rows / TILE_WIDTH),
1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
_gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns);
cudaMemcpy(c, dc, size, cudaMemcpyDeviceToHost);
cudaFree(da); cudaFree(db); cudaFree(dc);
return 0;
}
int main()
{
int *A, *B, *C;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
//Alocando memória na CPU
A = (int *)malloc(sizeof(int)*linhas*colunas);
B = (int *)malloc(sizeof(int)*linhas*colunas);
C = (int *)malloc(sizeof(int)*linhas*colunas);
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
m_add(A, B, C, linhas, colunas);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
} | code for sm_80
Function : _Z10_gpu_m_addPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x001fc800078e20ff */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R0, R0, R5, 0x4 ; /* 0x0000000500007211 */
/* 0x002fc800078e20ff */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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