system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <cstdlib>
// 2 GB of data
#define BYTES 2147483648
#define MAX_STRIDE 4194304
#define MAX_INDEX (BYTES/MAX_STRIDE)
static void __global__
Set(const int Seed, const int Stride, char *data) {
// Everyone set some data
for(int i = threadIdx.x; i < BYTES ; i+= blockDim.x ) {
data[i] = (char)(i * threadIdx.x + Seed);
}
}
static void __global__
CacheTest(const int Seed , const int Stride , char *data, int *result ) {
if(threadIdx.x == 0 ) {
int local_result = 0;
for(int i = 0 ; i < MAX_INDEX; ++i) {
local_result += data[i *(Stride+1)];
}
*result = local_result; // Here to make sure we don't optimize the loop away
}
}
static void Validate(bool cond, std::string msg) {
if(!cond) {
std::cout << msg << std::endl;
hipDeviceReset();
std::exit(EXIT_FAILURE);
}
}
static void CudaCheck(std::string msg, hipError_t err) {
Validate(err==hipSuccess, hipGetErrorString(err) + std::string("\n") + msg);
}
void sort(float *durations, int size) {
for(int i = 1 ; i < size; ++i) {
float cand = durations[i];
int j = i;
while( j > 0 && cand < durations[j-1]) {
if(durations[j] < durations[j-1]) {
durations[j] = durations[j-1];
}
--j;
}
durations[j] = cand;
}
}
float Run(const int Seed, const int Stride) {
const int Blocks = 1;
const int Threads = 1024;
float time;
hipEvent_t start,end;
char *d_data;
int *d_result;
CudaCheck("Malloc Result", hipMalloc(&d_result, sizeof(int) ) );
CudaCheck("Malloc Data", hipMalloc(&d_data, BYTES ) );
CudaCheck("Memset Result", hipMemset(d_result, 0, sizeof(int) ) );
CudaCheck("Memset Data", hipMemset(d_data, 0, BYTES ) );
Set<<<Blocks,Threads>>>(Seed, Stride, d_data);
CudaCheck("Set",hipDeviceSynchronize());
CudaCheck("Create start",hipEventCreate(&start));
CudaCheck("Create end",hipEventCreate(&end));
CudaCheck("Record start",hipEventRecord(start,0));
CacheTest<<<Blocks,Threads>>>(Seed, Stride, d_data, d_result);
CudaCheck("Record end",hipEventRecord(end,0));
CudaCheck("Device Sync",hipDeviceSynchronize());
CudaCheck("Event sync", hipEventSynchronize(end) );
CudaCheck("Get elapsed time",hipEventElapsedTime(&time,start,end));
CudaCheck("Destroy start",hipEventDestroy(start));
CudaCheck("Destroy end",hipEventDestroy(end));
CudaCheck("Free result", hipFree(d_result));
CudaCheck("Free data", hipFree(d_data));
CudaCheck("Reset",hipDeviceReset());
return time;
}
int main(int argc, char* argv[]) {
const int Runs = 50;
float durations[Runs];
Validate(argc==2,"Usage: " + std::string(argv[0]) + " stride");
const int Stride = atoi(argv[1]);
Validate(Stride <= MAX_STRIDE,"Decrease Stride");
std::cout << "Stride: " << Stride << std::endl;
for(int i = 0 ; i < Runs ; ++i ) {
durations[i] = Run(i+1, Stride);
}
sort(durations,Runs);
float time = 0;
int count = 0;
for(int i = 0; i < Runs; ++i) {
time += durations[i];
++count;
}
time /= count;
std::cout << "Elapsed Time: " << time << "ms" << std::endl;
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL3SetiiPc,"axG",@progbits,_ZL3SetiiPc,comdat
.globl _ZL3SetiiPc
.p2align 8
.type _ZL3SetiiPc,@function
_ZL3SetiiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mad_u32_u24 v1, v0, v0, s3
v_mul_u32_u24_e32 v2, s2, v0
.LBB0_1:
v_ashrrev_i32_e32 v4, 31, v0
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 vcc_lo, exec_lo
global_store_b8 v[3:4], v1, off
v_add_nc_u32_e32 v1, v1, v2
s_cbranch_vccnz .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL3SetiiPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL3SetiiPc,"axG",@progbits,_ZL3SetiiPc,comdat
.Lfunc_end0:
.size _ZL3SetiiPc, .Lfunc_end0-_ZL3SetiiPc
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL9CacheTestiiPcPi,"axG",@progbits,_ZL9CacheTestiiPcPi,comdat
.globl _ZL9CacheTestiiPcPi
.p2align 8
.type _ZL9CacheTestiiPcPi,@function
_ZL9CacheTestiiPcPi:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_movk_i32 s6, 0x200
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
.LBB1_2:
global_load_i8 v2, v1, s[2:3]
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
s_cbranch_scc0 .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9CacheTestiiPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9CacheTestiiPcPi,"axG",@progbits,_ZL9CacheTestiiPcPi,comdat
.Lfunc_end1:
.size _ZL9CacheTestiiPcPi, .Lfunc_end1-_ZL9CacheTestiiPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL3SetiiPc
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _ZL3SetiiPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9CacheTestiiPcPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _ZL9CacheTestiiPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9CacheTestiiPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R36, -RZ, RZ, 0, 0 ; /* 0x00000000ff247435 */
/* 0x000fe200000001ff */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULEA UR10, UR5, 0x20, 0x5 ; /* 0x00000020050a7891 */
/* 0x000fe4000f8e283f */
/*0080*/ USHF.L.U32 UR11, UR5, 0x1, URZ ; /* 0x00000001050b7899 */
/* 0x000fe4000800063f */
/*0090*/ UIMAD UR12, UR5, 0x3, URZ ; /* 0x00000003050c78a4 */
/* 0x000fe4000f8e023f */
/*00a0*/ USHF.L.U32 UR13, UR5, 0x2, URZ ; /* 0x00000002050d7899 */
/* 0x000fc4000800063f */
/*00b0*/ UIMAD UR14, UR5, 0x5, URZ ; /* 0x00000005050e78a4 */
/* 0x000fe4000f8e023f */
/*00c0*/ UIMAD UR15, UR5, 0x6, URZ ; /* 0x00000006050f78a4 */
/* 0x000fe4000f8e023f */
/*00d0*/ UIMAD UR16, UR5, 0x7, URZ ; /* 0x00000007051078a4 */
/* 0x000fe4000f8e023f */
/*00e0*/ USHF.L.U32 UR17, UR5, 0x3, URZ ; /* 0x0000000305117899 */
/* 0x000fe4000800063f */
/*00f0*/ UIMAD UR18, UR5, 0x9, URZ ; /* 0x00000009051278a4 */
/* 0x000fe4000f8e023f */
/*0100*/ UIMAD UR19, UR5, 0xa, URZ ; /* 0x0000000a051378a4 */
/* 0x000fc4000f8e023f */
/*0110*/ UIMAD UR20, UR5, 0xb, URZ ; /* 0x0000000b051478a4 */
/* 0x000fe4000f8e023f */
/*0120*/ UIMAD UR21, UR5, 0xc, URZ ; /* 0x0000000c051578a4 */
/* 0x000fe4000f8e023f */
/*0130*/ UIMAD UR22, UR5, 0xd, URZ ; /* 0x0000000d051678a4 */
/* 0x000fe4000f8e023f */
/*0140*/ UIMAD UR23, UR5, 0xe, URZ ; /* 0x0000000e051778a4 */
/* 0x000fe4000f8e023f */
/*0150*/ UIMAD UR24, UR5, 0xf, URZ ; /* 0x0000000f051878a4 */
/* 0x000fe4000f8e023f */
/*0160*/ USHF.L.U32 UR25, UR5, 0x4, URZ ; /* 0x0000000405197899 */
/* 0x000fc4000800063f */
/*0170*/ UIMAD UR26, UR5, 0x11, URZ ; /* 0x00000011051a78a4 */
/* 0x000fe4000f8e023f */
/*0180*/ UIMAD UR27, UR5, 0x12, URZ ; /* 0x00000012051b78a4 */
/* 0x000fe4000f8e023f */
/*0190*/ UIMAD UR28, UR5, 0x13, URZ ; /* 0x00000013051c78a4 */
/* 0x000fe4000f8e023f */
/*01a0*/ UIMAD UR29, UR5, 0x14, URZ ; /* 0x00000014051d78a4 */
/* 0x000fe4000f8e023f */
/*01b0*/ UIMAD UR30, UR5, 0x15, URZ ; /* 0x00000015051e78a4 */
/* 0x000fe4000f8e023f */
/*01c0*/ UIMAD UR31, UR5, 0x16, URZ ; /* 0x00000016051f78a4 */
/* 0x000fc4000f8e023f */
/*01d0*/ UIMAD UR32, UR5, 0x17, URZ ; /* 0x00000017052078a4 */
/* 0x000fe4000f8e023f */
/*01e0*/ UIMAD UR33, UR5, 0x18, URZ ; /* 0x00000018052178a4 */
/* 0x000fe4000f8e023f */
/*01f0*/ UIMAD UR34, UR5, 0x19, URZ ; /* 0x00000019052278a4 */
/* 0x000fe4000f8e023f */
/*0200*/ UIMAD UR35, UR5, 0x1a, URZ ; /* 0x0000001a052378a4 */
/* 0x000fe4000f8e023f */
/*0210*/ UIMAD UR36, UR5, 0x1b, URZ ; /* 0x0000001b052478a4 */
/* 0x000fe4000f8e023f */
/*0220*/ UIMAD UR37, UR5, 0x1c, URZ ; /* 0x0000001c052578a4 */
/* 0x000fc4000f8e023f */
/*0230*/ UIMAD UR38, UR5, 0x1d, URZ ; /* 0x0000001d052678a4 */
/* 0x000fe4000f8e023f */
/*0240*/ UIMAD UR39, UR5, 0x1e, URZ ; /* 0x0000001e052778a4 */
/* 0x000fe4000f8e023f */
/*0250*/ UIMAD UR40, UR5, 0x1f, URZ ; /* 0x0000001f052878a4 */
/* 0x000fe4000f8e023f */
/*0260*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0270*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0280*/ UIADD3 UR50, UP0, UR12, UR8, URZ ; /* 0x000000080c327290 */
/* 0x000fe4000ff1e03f */
/*0290*/ UIADD3 UR49, UP1, UR11, UR8, URZ ; /* 0x000000080b317290 */
/* 0x000fc4000ff3e03f */
/*02a0*/ ULEA.HI.X.SX32 UR51, UR12, UR9, 0x1, UP0 ; /* 0x000000090c337291 */
/* 0x000fe400080f0e3f */
/*02b0*/ UIADD3 UR54, UP6, UR14, UR8, URZ ; /* 0x000000080e367290 */
/* 0x000fe2000ffde03f */
/*02c0*/ MOV R6, UR50 ; /* 0x0000003200067c02 */
/* 0x000fe20008000f00 */
/*02d0*/ ULEA.HI.X.SX32 UR52, UR11, UR9, 0x1, UP1 ; /* 0x000000090b347291 */
/* 0x000fe200088f0e3f */
/*02e0*/ IMAD.U32 R2, RZ, RZ, UR49 ; /* 0x00000031ff027e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ UIADD3 UR58, UP3, UR16, UR8, URZ ; /* 0x00000008103a7290 */
/* 0x000fe2000ff7e03f */
/*0300*/ IMAD.U32 R7, RZ, RZ, UR51 ; /* 0x00000033ff077e24 */
/* 0x000fe2000f8e00ff */
/*0310*/ UIADD3 UR53, UP4, UR13, UR8, URZ ; /* 0x000000080d357290 */
/* 0x000fe4000ff9e03f */
/*0320*/ UIADD3 UR57, UP5, UR15, UR8, URZ ; /* 0x000000080f397290 */
/* 0x000fe2000ffbe03f */
/*0330*/ IMAD.U32 R3, RZ, RZ, UR52 ; /* 0x00000034ff037e24 */
/* 0x000fe2000f8e00ff */
/*0340*/ ULEA.HI.X.SX32 UR55, UR14, UR9, 0x1, UP6 ; /* 0x000000090e377291 */
/* 0x000fe2000b0f0e3f */
/*0350*/ LDG.E.S8 R34, [R6.64+0x3] ; /* 0x0000030606227981 */
/* 0x0000a2000c1e1300 */
/*0360*/ ULEA.HI.X.SX32 UR59, UR16, UR9, 0x1, UP3 ; /* 0x00000009103b7291 */
/* 0x000fc400098f0e3f */
/*0370*/ UIADD3 UR4, UP1, UR18, UR8, URZ ; /* 0x0000000812047290 */
/* 0x000fe4000ff3e03f */
/*0380*/ UIADD3 UR61, UP2, UR17, UR8, URZ ; /* 0x00000008113d7290 */
/* 0x000fe4000ff5e03f */
/*0390*/ ULEA.HI.X.SX32 UR56, UR13, UR9, 0x1, UP4 ; /* 0x000000090d387291 */
/* 0x000fe4000a0f0e3f */
/*03a0*/ UIADD3 UR41, UP0, UR19, UR8, URZ ; /* 0x0000000813297290 */
/* 0x000fe2000ff1e03f */
/*03b0*/ IMAD.U32 R10, RZ, RZ, UR54 ; /* 0x00000036ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*03c0*/ ULEA.HI.X.SX32 UR60, UR15, UR9, 0x1, UP5 ; /* 0x000000090f3c7291 */
/* 0x000fe2000a8f0e3f */
/*03d0*/ LDG.E.S8 R35, [R2.64+0x2] ; /* 0x0000020602237981 */
/* 0x0002a2000c1e1300 */
/*03e0*/ UIADD3 UR42, UP4, UR20, UR8, URZ ; /* 0x00000008142a7290 */
/* 0x000fe2000ff9e03f */
/*03f0*/ IMAD.U32 R11, RZ, RZ, UR55 ; /* 0x00000037ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0400*/ UIADD3 UR43, UP6, UR21, UR8, URZ ; /* 0x00000008152b7290 */
/* 0x000fe2000ffde03f */
/*0410*/ IMAD.U32 R6, RZ, RZ, UR58 ; /* 0x0000003aff067e24 */
/* 0x001fe2000f8e00ff */
/*0420*/ ULEA.HI.X.SX32 UR48, UR18, UR9, 0x1, UP1 ; /* 0x0000000912307291 */
/* 0x000fe200088f0e3f */
/*0430*/ MOV R7, UR59 ; /* 0x0000003b00077c02 */
/* 0x000fe20008000f00 */
/*0440*/ ULEA.HI.X.SX32 UR52, UR20, UR9, 0x1, UP4 ; /* 0x0000000914347291 */
/* 0x000fc4000a0f0e3f */
/*0450*/ ULEA.HI.X.SX32 UR46, UR17, UR9, 0x1, UP2 ; /* 0x00000009112e7291 */
/* 0x000fe200090f0e3f */
/*0460*/ MOV R2, UR57 ; /* 0x0000003900027c02 */
/* 0x002fe20008000f00 */
/*0470*/ ULEA.HI.X.SX32 UR50, UR19, UR9, 0x1, UP0 ; /* 0x0000000913327291 */
/* 0x000fe200080f0e3f */
/*0480*/ IMAD.U32 R3, RZ, RZ, UR60 ; /* 0x0000003cff037e24 */
/* 0x000fe2000f8e00ff */
/*0490*/ UIADD3 UR47, UP2, UR24, UR8, URZ ; /* 0x00000008182f7290 */
/* 0x000fe2000ff5e03f */
/*04a0*/ IMAD.U32 R8, RZ, RZ, UR53 ; /* 0x00000035ff087e24 */
/* 0x000fe2000f8e00ff */
/*04b0*/ UIADD3 UR51, UP0, UR26, UR8, URZ ; /* 0x000000081a337290 */
/* 0x000fe2000ff1e03f */
/*04c0*/ MOV R9, UR56 ; /* 0x0000003800097c02 */
/* 0x000fe20008000f00 */
/*04d0*/ UIADD3 UR45, UP3, UR23, UR8, URZ ; /* 0x00000008172d7290 */
/* 0x000fe2000ff7e03f */
/*04e0*/ LDG.E.S8 R32, [R10.64+0x5] ; /* 0x000005060a207981 */
/* 0x0000e2000c1e1300 */
/*04f0*/ ULEA.HI.X.SX32 UR54, UR21, UR9, 0x1, UP6 ; /* 0x0000000915367291 */
/* 0x000fc4000b0f0e3f */
/*0500*/ UIADD3 UR44, UP5, UR22, UR8, URZ ; /* 0x00000008162c7290 */
/* 0x000fe2000ffbe03f */
/*0510*/ LDG.E.S8 R30, [R6.64+0x7] ; /* 0x00000706061e7981 */
/* 0x000322000c1e1300 */
/*0520*/ UIADD3 UR55, UP6, UR28, UR8, URZ ; /* 0x000000081c377290 */
/* 0x000fe4000ffde03f */
/*0530*/ ULEA.HI.X.SX32 UR60, UR24, UR9, 0x1, UP2 ; /* 0x00000009183c7291 */
/* 0x000fe200090f0e3f */
/*0540*/ LDG.E.S8 R31, [R2.64+0x6] ; /* 0x00000606021f7981 */
/* 0x000b22000c1e1300 */
/*0550*/ UIADD3 UR49, UP1, UR25, UR8, URZ ; /* 0x0000000819317290 */
/* 0x000fe2000ff3e03f */
/*0560*/ IMAD.U32 R11, RZ, RZ, UR48 ; /* 0x00000030ff0b7e24 */
/* 0x001fe2000f8e00ff */
/*0570*/ ULEA.HI.X.SX32 UR48, UR26, UR9, 0x1, UP0 ; /* 0x000000091a307291 */
/* 0x000fe200080f0e3f */
/*0580*/ LDG.E.S8 R33, [R8.64+0x4] ; /* 0x0000040608217981 */
/* 0x0000e2000c1e1300 */
/*0590*/ ULEA.HI.X.SX32 UR58, UR23, UR9, 0x1, UP3 ; /* 0x00000009173a7291 */
/* 0x000fe200098f0e3f */
/*05a0*/ IMAD.U32 R6, RZ, RZ, UR42 ; /* 0x0000002aff067e24 */
/* 0x002fc4000f8e00ff */
/*05b0*/ IMAD.U32 R7, RZ, RZ, UR52 ; /* 0x00000034ff077e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ ULEA.HI.X.SX32 UR56, UR22, UR9, 0x1, UP5 ; /* 0x0000000916387291 */
/* 0x000fe2000a8f0e3f */
/*05d0*/ MOV R3, UR50 ; /* 0x0000003200037c02 */
/* 0x020fe20008000f00 */
/*05e0*/ IMAD.U32 R2, RZ, RZ, UR41 ; /* 0x00000029ff027e24 */
/* 0x000fe2000f8e00ff */
/*05f0*/ ULEA.HI.X.SX32 UR50, UR28, UR9, 0x1, UP6 ; /* 0x000000091c327291 */
/* 0x000fe2000b0f0e3f */
/*0600*/ MOV R10, UR4 ; /* 0x00000004000a7c02 */
/* 0x000fe20008000f00 */
/*0610*/ UIADD3 UR57, UP5, UR29, UR8, URZ ; /* 0x000000081d397290 */
/* 0x000fe2000ffbe03f */
/*0620*/ IMAD.U32 R8, RZ, RZ, UR61 ; /* 0x0000003dff087e24 */
/* 0x001fe2000f8e00ff */
/*0630*/ UIADD3 UR59, UP3, UR30, UR8, URZ ; /* 0x000000081e3b7290 */
/* 0x000fe2000ff7e03f */
/*0640*/ IMAD.U32 R9, RZ, RZ, UR46 ; /* 0x0000002eff097e24 */
/* 0x000fe2000f8e00ff */
/*0650*/ UIADD3 UR53, UP4, UR27, UR8, URZ ; /* 0x000000081b357290 */
/* 0x000fe2000ff9e03f */
/*0660*/ LDG.E.S8 R26, [R6.64+0xb] ; /* 0x00000b06061a7981 */
/* 0x000162000c1e1300 */
/*0670*/ UIADD3 UR61, UP2, UR31, UR8, URZ ; /* 0x000000081f3d7290 */
/* 0x000fe2000ff5e03f */
/*0680*/ MOV R20, UR47 ; /* 0x0000002f00147c02 */
/* 0x000fe20008000f00 */
/*0690*/ ULEA.HI.X.SX32 UR46, UR25, UR9, 0x1, UP1 ; /* 0x00000009192e7291 */
/* 0x000fe200088f0e3f */
/*06a0*/ IMAD.U32 R21, RZ, RZ, UR60 ; /* 0x0000003cff157e24 */
/* 0x000fe2000f8e00ff */
/*06b0*/ UIADD3 UR4, UP1, UR32, UR8, URZ ; /* 0x0000000820047290 */
/* 0x000fe2000ff3e03f */
/*06c0*/ LDG.E.S8 R27, [R2.64+0xa] ; /* 0x00000a06021b7981 */
/* 0x000362000c1e1300 */
/*06d0*/ MOV R12, UR43 ; /* 0x0000002b000c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ IMAD.U32 R13, RZ, RZ, UR54 ; /* 0x00000036ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*06f0*/ ULEA.HI.X.SX32 UR52, UR29, UR9, 0x1, UP5 ; /* 0x000000091d347291 */
/* 0x000fe2000a8f0e3f */
/*0700*/ IMAD.U32 R7, RZ, RZ, UR48 ; /* 0x00000030ff077e24 */
/* 0x001fe2000f8e00ff */
/*0710*/ ULEA.HI.X.SX32 UR48, UR30, UR9, 0x1, UP3 ; /* 0x000000091e307291 */
/* 0x000fe200098f0e3f */
/*0720*/ IMAD.U32 R18, RZ, RZ, UR45 ; /* 0x0000002dff127e24 */
/* 0x000fe2000f8e00ff */
/*0730*/ UIADD3 UR41, UP0, UR33, UR8, URZ ; /* 0x0000000821297290 */
/* 0x000fe2000ff1e03f */
/*0740*/ IMAD.U32 R19, RZ, RZ, UR58 ; /* 0x0000003aff137e24 */
/* 0x000fe2000f8e00ff */
/*0750*/ ULEA.HI.X.SX32 UR42, UR27, UR9, 0x1, UP4 ; /* 0x000000091b2a7291 */
/* 0x000fe2000a0f0e3f */
/*0760*/ IMAD.U32 R2, RZ, RZ, UR55 ; /* 0x00000037ff027e24 */
/* 0x002fe2000f8e00ff */
/*0770*/ MOV R3, UR50 ; /* 0x0000003200037c02 */
/* 0x000fe20008000f00 */
/*0780*/ LDG.E.S8 R29, [R8.64+0x8] ; /* 0x00000806081d7981 */
/* 0x0000a2000c1e1300 */
/*0790*/ UIADD3 UR43, UP4, UR34, UR8, URZ ; /* 0x00000008222b7290 */
/* 0x000fe2000ff9e03f */
/*07a0*/ IMAD.U32 R6, RZ, RZ, UR51 ; /* 0x00000033ff067e24 */
/* 0x000fe2000f8e00ff */
/*07b0*/ ULEA.HI.X.SX32 UR47, UR31, UR9, 0x1, UP2 ; /* 0x000000091f2f7291 */
/* 0x000fe200090f0e3f */
/*07c0*/ LDG.E.S8 R28, [R10.64+0x9] ; /* 0x000009060a1c7981 */
/* 0x0002a2000c1e1300 */
/*07d0*/ IMAD.U32 R22, RZ, RZ, UR57 ; /* 0x00000039ff167e24 */
/* 0x000fc6000f8e00ff */
/*07e0*/ LDG.E.S8 R16, [R20.64+0xf] ; /* 0x00000f0614107981 */
/* 0x0002a2000c1e1300 */
/*07f0*/ IMAD.U32 R8, RZ, RZ, UR44 ; /* 0x0000002cff087e24 */
/* 0x001fe2000f8e00ff */
/*0800*/ UIADD3 UR44, UP6, UR35, UR8, URZ ; /* 0x00000008232c7290 */
/* 0x000fe4000ffde03f */
/*0810*/ LDG.E.S8 R25, [R12.64+0xc] ; /* 0x00000c060c197981 */
/* 0x0000a2000c1e1300 */
/*0820*/ MOV R9, UR56 ; /* 0x0000003800097c02 */
/* 0x000fe20008000f00 */
/*0830*/ IMAD.U32 R10, RZ, RZ, UR49 ; /* 0x00000031ff0a7e24 */
/* 0x002fe2000f8e00ff */
/*0840*/ MOV R11, UR46 ; /* 0x0000002e000b7c02 */
/* 0x000fe20008000f00 */
/*0850*/ LDG.E.S8 R17, [R18.64+0xe] ; /* 0x00000e0612117981 */
/* 0x0002a2000c1e1300 */
/*0860*/ IMAD.U32 R23, RZ, RZ, UR52 ; /* 0x00000034ff177e24 */
/* 0x000fe4000f8e00ff */
/*0870*/ IMAD.U32 R20, RZ, RZ, UR4 ; /* 0x00000004ff147e24 */
/* 0x000fe2000f8e00ff */
/*0880*/ ULEA.HI.X.SX32 UR4, UR34, UR9, 0x1, UP4 ; /* 0x0000000922047291 */
/* 0x000fe2000a0f0e3f */
/*0890*/ LDG.E.S8 R14, [R6.64+0x11] ; /* 0x00001106060e7981 */
/* 0x0002a2000c1e1300 */
/*08a0*/ UIADD3 UR45, UP5, UR36, UR8, URZ ; /* 0x00000008242d7290 */
/* 0x000fc6000ffbe03f */
/*08b0*/ LDG.E.S8 R12, [R2.64+0x13] ; /* 0x00001306020c7981 */
/* 0x0010a2000c1e1300 */
/*08c0*/ IMAD.U32 R19, RZ, RZ, UR48 ; /* 0x00000030ff137e24 */
/* 0x002fe2000f8e00ff */
/*08d0*/ ULEA.HI.X.SX32 UR48, UR32, UR9, 0x1, UP1 ; /* 0x0000000920307291 */
/* 0x000fe200088f0e3f */
/*08e0*/ MOV R18, UR59 ; /* 0x0000003b00127c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E.S8 R15, [R10.64+0x10] ; /* 0x000010060a0f7981 */
/* 0x0002a2000c1e1300 */
/*0900*/ MOV R7, UR47 ; /* 0x0000002f00077c02 */
/* 0x000fe20008000f00 */
/*0910*/ ULEA.HI.X.SX32 UR47, UR33, UR9, 0x1, UP0 ; /* 0x00000009212f7291 */
/* 0x000fe400080f0e3f */
/*0920*/ LDG.E.S8 R24, [R8.64+0xd] ; /* 0x00000d0608187981 */
/* 0x0002a2000c1e1300 */
/*0930*/ MOV R2, UR41 ; /* 0x0000002900027c02 */
/* 0x001fe20008000f00 */
/*0940*/ ULEA.HI.X.SX32 UR41, UR35, UR9, 0x1, UP6 ; /* 0x0000000923297291 */
/* 0x000fc4000b0f0e3f */
/*0950*/ UIADD3 UR46, UP3, UR37, UR8, URZ ; /* 0x00000008252e7290 */
/* 0x000fe2000ff7e03f */
/*0960*/ LDG.E.S8 R11, [R22.64+0x14] ; /* 0x00001406160b7981 */
/* 0x0020a2000c1e1300 */
/*0970*/ IMAD.U32 R21, RZ, RZ, UR48 ; /* 0x00000030ff157e24 */
/* 0x000fe2000f8e00ff */
/*0980*/ MOV R8, UR53 ; /* 0x0000003500087c02 */
/* 0x000fe20008000f00 */
/*0990*/ IMAD.U32 R9, RZ, RZ, UR42 ; /* 0x0000002aff097e24 */
/* 0x000fe2000f8e00ff */
/*09a0*/ LDG.E.S8 R10, [R18.64+0x15] ; /* 0x00001506120a7981 */
/* 0x0002a2000c1e1300 */
/*09b0*/ IMAD.U32 R6, RZ, RZ, UR61 ; /* 0x0000003dff067e24 */
/* 0x000fe2000f8e00ff */
/*09c0*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x001fe20008000f00 */
/*09d0*/ ULEA.HI.X.SX32 UR4, UR36, UR9, 0x1, UP5 ; /* 0x0000000924047291 */
/* 0x000fe2000a8f0e3f */
/*09e0*/ IMAD.U32 R3, RZ, RZ, UR47 ; /* 0x0000002fff037e24 */
/* 0x000fe2000f8e00ff */
/*09f0*/ UIADD3 UR42, UP2, UR38, UR8, URZ ; /* 0x00000008262a7290 */
/* 0x000fe2000ff5e03f */
/*0a00*/ LDG.E.S8 R13, [R8.64+0x12] ; /* 0x00001206080d7981 */
/* 0x0000a2000c1e1300 */
/*0a10*/ MOV R19, UR41 ; /* 0x0000002900137c02 */
/* 0x002fe20008000f00 */
/*0a20*/ ULEA.HI.X.SX32 UR41, UR37, UR9, 0x1, UP3 ; /* 0x0000000925297291 */
/* 0x000fe200098f0e3f */
/*0a30*/ IMAD.U32 R22, RZ, RZ, UR43 ; /* 0x0000002bff167e24 */
/* 0x000fe2000f8e00ff */
/*0a40*/ LDG.E.S8 R8, [R20.64+0x17] ; /* 0x0000170614087981 */
/* 0x0010a8000c1e1300 */
/*0a50*/ LDG.E.S8 R9, [R6.64+0x16] ; /* 0x0000160606097981 */
/* 0x0002a2000c1e1300 */
/*0a60*/ MOV R21, UR4 ; /* 0x0000000400157c02 */
/* 0x001fe20008000f00 */
/*0a70*/ ULEA.HI.X.SX32 UR4, UR38, UR9, 0x1, UP2 ; /* 0x0000000926047291 */
/* 0x000fc400090f0e3f */
/*0a80*/ LDG.E.S8 R7, [R2.64+0x18] ; /* 0x0000180602077981 */
/* 0x0020a2000c1e1300 */
/*0a90*/ IMAD.U32 R18, RZ, RZ, UR44 ; /* 0x0000002cff127e24 */
/* 0x000fc6000f8e00ff */
/*0aa0*/ LDG.E.S8 R6, [R22.64+0x19] ; /* 0x0000190616067981 */
/* 0x0002a2000c1e1300 */
/*0ab0*/ IMAD.U32 R20, RZ, RZ, UR45 ; /* 0x0000002dff147e24 */
/* 0x000fc6000f8e00ff */
/*0ac0*/ LDG.E.S8 R0, [R18.64+0x1a] ; /* 0x00001a0612007981 */
/* 0x0002a2000c1e1300 */
/*0ad0*/ MOV R3, UR41 ; /* 0x0000002900037c02 */
/* 0x001fe20008000f00 */
/*0ae0*/ UIADD3 UR41, UP0, UR39, UR8, URZ ; /* 0x0000000827297290 */
/* 0x000fe4000ff1e03f */
/*0af0*/ LDG.E.S8 R5, [R20.64+0x1b] ; /* 0x00001b0614057981 */
/* 0x0000a2000c1e1300 */
/*0b00*/ IMAD.U32 R22, RZ, RZ, UR42 ; /* 0x0000002aff167e24 */
/* 0x002fe2000f8e00ff */
/*0b10*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x000fe20008000f00 */
/*0b20*/ ULEA.HI.X.SX32 UR42, UR39, UR9, 0x1, UP0 ; /* 0x00000009272a7291 */
/* 0x000fe400080f0e3f */
/*0b30*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe40000000800 */
/*0b40*/ UIADD3 UR4, UP0, UR8, UR4, URZ ; /* 0x0000000408047290 */
/* 0x000fe2000ff1e03f */
/*0b50*/ IMAD.U32 R18, RZ, RZ, UR41 ; /* 0x00000029ff127e24 */
/* 0x000fe2000f8e00ff */
/*0b60*/ MOV R19, UR42 ; /* 0x0000002a00137c02 */
/* 0x000fc40008000f00 */
/*0b70*/ ULEA.HI.X.SX32 UR42, UR5, UR9, 0x1, UP0 ; /* 0x00000009052a7291 */
/* 0x000fc600080f0e3f */
/*0b80*/ LDG.E.S8 R37, [R18.64+0x1e] ; /* 0x00001e0612257981 */
/* 0x0002a2000c1e1300 */
/*0b90*/ IMAD.U32 R20, RZ, RZ, UR4 ; /* 0x00000004ff147e24 */
/* 0x001fe4000f8e00ff */
/*0ba0*/ MOV R21, UR42 ; /* 0x0000002a00157c02 */
/* 0x000fcc0008000f00 */
/*0bb0*/ LDG.E.S8 R21, [R20.64+0x1] ; /* 0x0000010614157981 */
/* 0x000ea2000c1e1300 */
/*0bc0*/ MOV R18, UR8 ; /* 0x0000000800127c02 */
/* 0x002fe20008000f00 */
/*0bd0*/ IMAD.U32 R19, RZ, RZ, UR9 ; /* 0x00000009ff137e24 */
/* 0x000fca000f8e00ff */
/*0be0*/ LDG.E.S8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1300 */
/*0bf0*/ UIADD3 UR41, UP0, UR40, UR8, URZ ; /* 0x0000000828297290 */
/* 0x000fe2000ff1e03f */
/*0c00*/ IMAD.U32 R2, RZ, RZ, UR46 ; /* 0x0000002eff027e24 */
/* 0x000fc6000f8e00ff */
/*0c10*/ ULEA.HI.X.SX32 UR4, UR40, UR9, 0x1, UP0 ; /* 0x0000000928047291 */
/* 0x000fe400080f0e3f */
/*0c20*/ LDG.E.S8 R3, [R2.64+0x1c] ; /* 0x00001c0602037981 */
/* 0x0000e8000c1e1300 */
/*0c30*/ LDG.E.S8 R2, [R22.64+0x1d] ; /* 0x00001d0616027981 */
/* 0x001164000c1e1300 */
/*0c40*/ IMAD.U32 R22, RZ, RZ, UR41 ; /* 0x00000029ff167e24 */
/* 0x001fe2000f8e00ff */
/*0c50*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x000fca0008000f00 */
/*0c60*/ LDG.E.S8 R22, [R22.64+0x1f] ; /* 0x00001f0616167981 */
/* 0x000f62000c1e1300 */
/*0c70*/ IADD3 R4, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R4, 0x200, PT ; /* 0x000002000400780c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP0, UR10, UR8, URZ ; /* 0x000000080a087290 */
/* 0x000fc8000ff1e03f */
/*0ca0*/ ULEA.HI.X.SX32 UR9, UR10, UR9, 0x1, UP0 ; /* 0x000000090a097291 */
/* 0x000fe200080f0e3f */
/*0cb0*/ IADD3 R36, R21, R36, R18 ; /* 0x0000002415247210 */
/* 0x004fc80007ffe012 */
/*0cc0*/ IADD3 R34, R34, R36, R35 ; /* 0x0000002422227210 */
/* 0x000fc80007ffe023 */
/*0cd0*/ IADD3 R32, R32, R34, R33 ; /* 0x0000002220207210 */
/* 0x008fc80007ffe021 */
/*0ce0*/ IADD3 R30, R30, R32, R31 ; /* 0x000000201e1e7210 */
/* 0x010fc80007ffe01f */
/*0cf0*/ IADD3 R28, R28, R30, R29 ; /* 0x0000001e1c1c7210 */
/* 0x000fc80007ffe01d */
/*0d00*/ IADD3 R26, R26, R28, R27 ; /* 0x0000001c1a1a7210 */
/* 0x020fc80007ffe01b */
/*0d10*/ IADD3 R24, R24, R26, R25 ; /* 0x0000001a18187210 */
/* 0x000fc80007ffe019 */
/*0d20*/ IADD3 R16, R16, R24, R17 ; /* 0x0000001810107210 */
/* 0x000fc80007ffe011 */
/*0d30*/ IADD3 R14, R14, R16, R15 ; /* 0x000000100e0e7210 */
/* 0x000fc80007ffe00f */
/*0d40*/ IADD3 R12, R12, R14, R13 ; /* 0x0000000e0c0c7210 */
/* 0x000fc80007ffe00d */
/*0d50*/ IADD3 R10, R10, R12, R11 ; /* 0x0000000c0a0a7210 */
/* 0x000fc80007ffe00b */
/*0d60*/ IADD3 R8, R8, R10, R9 ; /* 0x0000000a08087210 */
/* 0x000fc80007ffe009 */
/*0d70*/ IADD3 R6, R6, R8, R7 ; /* 0x0000000806067210 */
/* 0x000fc80007ffe007 */
/*0d80*/ IADD3 R0, R5, R6, R0 ; /* 0x0000000605007210 */
/* 0x000fc80007ffe000 */
/*0d90*/ IADD3 R0, R2, R0, R3 ; /* 0x0000000002007210 */
/* 0x000fc80007ffe003 */
/*0da0*/ IADD3 R36, R22, R0, R37 ; /* 0x0000000016247210 */
/* 0x000fe20007ffe025 */
/*0db0*/ @P0 BRA 0x280 ; /* 0xfffff4c000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0dd0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0de0*/ STG.E [R2.64], R36 ; /* 0x0000002402007986 */
/* 0x000fe2000c101906 */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3SetiiPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD R5, R4, R4.reuse, c[0x0][0x160] ; /* 0x0000580004057624 */
/* 0x081fe200078e0204 */
/*0040*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fc80000000f00 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0.reuse, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x040fe400000f0eff */
/*0070*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*0080*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101104 */
/*0090*/ IMAD R5, R4, c[0x0][0x0], R5 ; /* 0x0000000004057a24 */
/* 0x001fe200078e0205 */
/*00a0*/ BRA 0x50 ; /* 0xffffffa000007947 */
/* 0x000fea000383ffff */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL3SetiiPc,"axG",@progbits,_ZL3SetiiPc,comdat
.globl _ZL3SetiiPc
.p2align 8
.type _ZL3SetiiPc,@function
_ZL3SetiiPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mad_u32_u24 v1, v0, v0, s3
v_mul_u32_u24_e32 v2, s2, v0
.LBB0_1:
v_ashrrev_i32_e32 v4, 31, v0
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 vcc_lo, exec_lo
global_store_b8 v[3:4], v1, off
v_add_nc_u32_e32 v1, v1, v2
s_cbranch_vccnz .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL3SetiiPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL3SetiiPc,"axG",@progbits,_ZL3SetiiPc,comdat
.Lfunc_end0:
.size _ZL3SetiiPc, .Lfunc_end0-_ZL3SetiiPc
.section .AMDGPU.csdata,"",@progbits
.section .text._ZL9CacheTestiiPcPi,"axG",@progbits,_ZL9CacheTestiiPcPi,comdat
.globl _ZL9CacheTestiiPcPi
.p2align 8
.type _ZL9CacheTestiiPcPi,@function
_ZL9CacheTestiiPcPi:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_movk_i32 s6, 0x200
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
.LBB1_2:
global_load_i8 v2, v1, s[2:3]
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
s_cbranch_scc0 .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9CacheTestiiPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9CacheTestiiPcPi,"axG",@progbits,_ZL9CacheTestiiPcPi,comdat
.Lfunc_end1:
.size _ZL9CacheTestiiPcPi, .Lfunc_end1-_ZL9CacheTestiiPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL3SetiiPc
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _ZL3SetiiPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9CacheTestiiPcPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _ZL9CacheTestiiPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} | code for sm_80
Function : _Z4move4View
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R19, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff137435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R19, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fc800078e0213 */
/*0090*/ IMAD.WIDE R2, R0.reuse, R19.reuse, c[0x0][0x198] ; /* 0x0000660000027625 */
/* 0x0c0fe400078e0213 */
/*00a0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R19.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0213 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.WIDE R10, R0, R19, c[0x0][0x188] ; /* 0x00006200000a7625 */
/* 0x000fe200078e0213 */
/*00f0*/ DFMA R14, R8, R2, R6 ; /* 0x00000002080e722b */
/* 0x0040460000000006 */
/*0100*/ IMAD.WIDE R6, R0, R19, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x001fc800078e0213 */
/*0110*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x002fe8000c101b04 */
/*0120*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R8, R0, R19, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0213 */
/*0150*/ DFMA R16, R2, R10, R12 ; /* 0x0000000a0210722b */
/* 0x004046000000000c */
/*0160*/ IMAD.WIDE R12, R0, R19, c[0x0][0x190] ; /* 0x00006400000c7625 */
/* 0x001fc800078e0213 */
/*0170*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x002fe8000c101b04 */
/*0180*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*0190*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea4000c1e1b00 */
/*01a0*/ DFMA R18, R2, R12, R18 ; /* 0x0000000c0212722b */
/* 0x004e0e0000000012 */
/*01b0*/ STG.E.64 [R8.64], R18 ; /* 0x0000001208007986 */
/* 0x001fe2000c101b04 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} | .file "tmpxft_000bd492_00000000-6_soa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4move4ViewR4View
.type _Z26__device_stub__Z4move4ViewR4View, @function
_Z26__device_stub__Z4move4ViewR4View:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4move4View(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z26__device_stub__Z4move4ViewR4View, .-_Z26__device_stub__Z4move4ViewR4View
.globl _Z4move4View
.type _Z4move4View, @function
_Z4move4View:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z26__device_stub__Z4move4ViewR4View
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4move4View, .-_Z4move4View
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4move4View"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4move4View(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} | #include <hip/hip_runtime.h>
struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4move4View
.globl _Z4move4View
.p2align 8
.type _Z4move4View,@function
_Z4move4View:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[8:9], v[6:7], off
s_load_b128 s[0:3], s[0:1], 0x28
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
global_store_b64 v[6:7], v[2:3], off
global_load_b64 v[2:3], v[8:9], off
global_load_b64 v[6:7], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[10:11], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4move4View
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4move4View, .Lfunc_end0-_Z4move4View
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 64
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4move4View
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4move4View.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
struct Point {
double* x;
double* y;
double* z;
};
struct Ref {
Point pos;
Point dir;
double* distance;
};
struct View {
int size;
Point pos;
Point dir;
double* distance;
__device__ Ref operator[](int i) const {
return {{pos.x + i, pos.y + i, pos.z + i},
{dir.x + i, dir.y + i, dir.z + i},
distance + i};
}
};
__device__ inline void move_impl(const Ref& ref) {
const double nextdist = *ref.distance;
*ref.pos.x += *ref.dir.x * nextdist;
*ref.pos.y += *ref.dir.y * nextdist;
*ref.pos.z += *ref.dir.z * nextdist;
}
__global__ void move(View view) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < view.size) {
move_impl(view[idx]);
}
} | .text
.file "soa.hip"
.globl _Z19__device_stub__move4View # -- Begin function _Z19__device_stub__move4View
.p2align 4, 0x90
.type _Z19__device_stub__move4View,@function
_Z19__device_stub__move4View: # @_Z19__device_stub__move4View
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z4move4View, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__move4View, .Lfunc_end0-_Z19__device_stub__move4View
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4move4View, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4move4View,@object # @_Z4move4View
.section .rodata,"a",@progbits
.globl _Z4move4View
.p2align 3, 0x0
_Z4move4View:
.quad _Z19__device_stub__move4View
.size _Z4move4View, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4move4View"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__move4View
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4move4View
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4move4View
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R19, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff137435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R8, R0, R19, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fc800078e0213 */
/*0090*/ IMAD.WIDE R2, R0.reuse, R19.reuse, c[0x0][0x198] ; /* 0x0000660000027625 */
/* 0x0c0fe400078e0213 */
/*00a0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R19.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0213 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.WIDE R10, R0, R19, c[0x0][0x188] ; /* 0x00006200000a7625 */
/* 0x000fe200078e0213 */
/*00f0*/ DFMA R14, R8, R2, R6 ; /* 0x00000002080e722b */
/* 0x0040460000000006 */
/*0100*/ IMAD.WIDE R6, R0, R19, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x001fc800078e0213 */
/*0110*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x002fe8000c101b04 */
/*0120*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R8, R0, R19, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fe200078e0213 */
/*0150*/ DFMA R16, R2, R10, R12 ; /* 0x0000000a0210722b */
/* 0x004046000000000c */
/*0160*/ IMAD.WIDE R12, R0, R19, c[0x0][0x190] ; /* 0x00006400000c7625 */
/* 0x001fc800078e0213 */
/*0170*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x002fe8000c101b04 */
/*0180*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*0190*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea4000c1e1b00 */
/*01a0*/ DFMA R18, R2, R12, R18 ; /* 0x0000000c0212722b */
/* 0x004e0e0000000012 */
/*01b0*/ STG.E.64 [R8.64], R18 ; /* 0x0000001208007986 */
/* 0x001fe2000c101b04 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4move4View
.globl _Z4move4View
.p2align 8
.type _Z4move4View,@function
_Z4move4View:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x38
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[8:9], v[6:7], off
s_load_b128 s[0:3], s[0:1], 0x28
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v10, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v1, vcc_lo
global_store_b64 v[6:7], v[2:3], off
global_load_b64 v[2:3], v[8:9], off
global_load_b64 v[6:7], v[10:11], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
v_add_co_u32 v6, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[10:11], v[2:3], off
global_load_b64 v[2:3], v[6:7], off
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4move4View
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4move4View, .Lfunc_end0-_Z4move4View
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 64
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4move4View
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4move4View.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bd492_00000000-6_soa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4move4ViewR4View
.type _Z26__device_stub__Z4move4ViewR4View, @function
_Z26__device_stub__Z4move4ViewR4View:
.LFB2053:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4move4View(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z26__device_stub__Z4move4ViewR4View, .-_Z26__device_stub__Z4move4ViewR4View
.globl _Z4move4View
.type _Z4move4View, @function
_Z4move4View:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z26__device_stub__Z4move4ViewR4View
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4move4View, .-_Z4move4View
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4move4View"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4move4View(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "soa.hip"
.globl _Z19__device_stub__move4View # -- Begin function _Z19__device_stub__move4View
.p2align 4, 0x90
.type _Z19__device_stub__move4View,@function
_Z19__device_stub__move4View: # @_Z19__device_stub__move4View
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z4move4View, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__move4View, .Lfunc_end0-_Z19__device_stub__move4View
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4move4View, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4move4View,@object # @_Z4move4View
.section .rodata,"a",@progbits
.globl _Z4move4View
.p2align 3, 0x0
_Z4move4View:
.quad _Z19__device_stub__move4View
.size _Z4move4View, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4move4View"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__move4View
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4move4View
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} | .file "tmpxft_000d4683_00000000-6_bfs_cpu_array_multi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3193:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3bfsi
.type _Z3bfsi, @function
_Z3bfsi:
.LFB3189:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movl %edi, %esi
leaq visit(%rip), %rdx
movl $512, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movl %esi, q(%rip)
movl $0, %edx
movl $0, %r12d
movl $1, %r8d
leaq q(%rip), %rbp
leaq edge(%rip), %r13
leaq visit(%rip), %r9
leaq dist(%rip), %r11
movslq %esi, %rbx
salq $10, %rbx
jmp .L9
.L7:
movslq %edx, %rsi
movl %eax, 0(%rbp,%rsi,4)
cltq
movl $1, (%r9,%rax,4)
addl $1, %r8d
.L6:
addq $4, %rcx
movl -4(%rcx), %eax
testl %eax, %eax
je .L5
.L8:
movslq %eax, %rsi
cmpl $0, (%r9,%rsi,4)
jne .L6
addq %rbx, %rsi
movl (%r11,%r10,4), %edi
addl $1, %edi
movl %edi, (%r11,%rsi,4)
addl $1, %edx
cmpl $1023, %edx
jle .L7
movl %edx, %esi
sarl $31, %esi
shrl $22, %esi
addl %esi, %edx
andl $1023, %edx
subl %esi, %edx
jmp .L7
.L5:
testl %r8d, %r8d
jle .L14
.L9:
movslq %r12d, %rax
movl 0(%rbp,%rax,4), %r10d
addl $1, %r12d
subl $1, %r8d
cmpl $1024, %r12d
movl $0, %eax
cmovge %eax, %r12d
movslq %r10d, %rax
salq $12, %rax
movl 0(%r13,%rax), %eax
testl %eax, %eax
je .L5
movslq %r10d, %rcx
salq $12, %rcx
leaq 4(%r13,%rcx), %rcx
movslq %r10d, %r10
addq %rbx, %r10
jmp .L8
.L14:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3189:
.size _Z3bfsi, .-_Z3bfsi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC2:
.string "%d %d"
.LC3:
.string "w"
.LC4:
.string " %d"
.LC5:
.string "\n"
.LC6:
.string "Finished!\n"
.text
.globl main
.type main, @function
main:
.LFB3190:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq filein(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $4194304, %edx
movl $0, %esi
leaq edge(%rip), %rdi
call memset@PLT
leaq visit(%rip), %rdx
movl $512, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movl $4194304, %edx
movl $0, %esi
leaq dist(%rip), %rdi
call memset@PLT
movl $0, 12(%rsp)
leaq 48(%rsp), %r15
leaq .LC1(%rip), %r14
leaq edge(%rip), %r13
.L16:
leaq 44(%rsp), %rdx
movq %r15, %rcx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L32
addl $1, 12(%rsp)
cmpl $0, 48(%rsp)
jle .L16
movl $0, %ebx
leaq 52(%rsp), %r12
.L18:
movq %r12, %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %ebx, %rdx
movslq 44(%rsp), %rax
salq $10, %rax
addq %rdx, %rax
movl 52(%rsp), %edx
movl %edx, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, 48(%rsp)
jg .L18
jmp .L16
.L32:
movq %rbp, %rdi
call fclose@PLT
movl 12(%rsp), %ebp
testl %ebp, %ebp
jle .L20
movl $0, %ebx
.L21:
movl %ebx, %edi
call _Z3bfsi
addl $1, %ebx
cmpl %ebx, %ebp
jne .L21
leaq .LC3(%rip), %rsi
leaq fileout(%rip), %rdi
call fopen@PLT
movq %rax, %r13
leaq dist(%rip), %rax
movslq 12(%rsp), %rdx
movq %rdx, %r12
salq $12, %r12
addq %rax, %r12
negq %rdx
salq $12, %rdx
movq %rdx, 24(%rsp)
movl $0, %r15d
leaq .LC4(%rip), %r14
movq %rax, 16(%rsp)
.L23:
movl %r15d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
leaq (%r12,%rax), %rbx
movq 16(%rsp), %rbp
.L22:
movl 0(%rbp), %ecx
movl (%rbx), %eax
cmpl %eax, %ecx
cmovl %eax, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbp
addq $4096, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r15d
addq $4096, 16(%rsp)
addq $4, %r12
cmpl %r15d, 12(%rsp)
jne .L23
.L24:
movq %r13, %rdi
call fclose@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq fileout(%rip), %rdi
call fopen@PLT
movq %rax, %r13
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3190:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3216:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3216:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dist
.bss
.align 32
.type dist, @object
.size dist, 4194304
dist:
.zero 4194304
.globl visit
.align 32
.type visit, @object
.size visit, 4096
visit:
.zero 4096
.globl edge
.align 32
.type edge, @object
.size edge, 4194304
edge:
.zero 4194304
.globl q
.align 32
.type q, @object
.size q, 4096
q:
.zero 4096
.globl fileout
.data
.align 32
.type fileout, @object
.size fileout, 35
fileout:
.string "/home/yuede/dataset/edge.cpu_multi"
.globl filein
.align 16
.type filein, @object
.size filein, 29
filein:
.string "/home/yuede/dataset/edge.dat"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
File name: bfs_cpu_array_multi.cu
Author: Yuede Ji
Last update: 21:54 10-02-2015
Description: Using array to implent CPU version of bfs.
Calculate the shortest distance between each other
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <queue>
#include <stdlib.h>
#include <string.h>
using namespace std;
#define N 1024 // vertex number
//Using arrays to implement queue
#define imax(a, b) (a>b?a:b)
char filein[] = "/home/yuede/dataset/edge.dat";
char fileout[] = "/home/yuede/dataset/edge.cpu_multi";
//Using arrays to implement queue
int q[N];
int edge[N][N];
int visit[N];
int dist[N][N];
int bfs(int root)
{
//memset(dist, 0, sizeof(int) * N * N);
memset(visit, 0, sizeof(int) * N);
q[0] = root;
int l = 1; // record the size of the queue
int front = 0; // identify the front element
int end = 0; // identify the end element
while(l>0)
{
int cur = q[front];
++front;
--l;
if(front >= N)
front %= N;
for(int i=0; edge[cur][i]!=0; ++i)
{
int v = edge[cur][i];
if(visit[v])
continue;
dist[root][v] = dist[root][cur] + 1;
++end;
if(end >= N)
end %= N;
q[end] = v;
visit[v] = 1;
++l;
}
}
return 0;
}
int main()
{
FILE *fp_in = fopen(filein, "r");
int v, e;
int num_v=0;
memset(edge, 0, N*N*sizeof(int));
memset(visit, 0, N*sizeof(int));
memset(dist, 0, N*N*sizeof(int));
while(fscanf(fp_in, "%d %d", &v, &e)!=EOF)
{
++num_v;
for(int i=0; i<e; ++i)
{
int v1;
fscanf(fp_in, "%d", &v1);
edge[v][i] = v1;//v->v1
}
}
fclose(fp_in);
for(int i=0; i<num_v; ++i)
bfs(i);
FILE *fp_out = fopen(fileout, "w");
//fprintf("num_v = %d\n", num_v);
for(int i=0; i<num_v; ++i)
{
fprintf(fp_out, "%d", i);
for(int j=0; j<num_v; ++j)
fprintf(fp_out, " %d", imax(dist[i][j], dist[j][i]));
fprintf(fp_out, "\n");
}
fclose(fp_out);
printf("Finished!\n");
return 0;
} | .text
.file "bfs_cpu_array_multi.hip"
.globl _Z3bfsi # -- Begin function _Z3bfsi
.p2align 4, 0x90
.type _Z3bfsi,@function
_Z3bfsi: # @_Z3bfsi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl %ebx, q(%rip)
movslq %ebx, %rax
movl $1, %ecx
shlq $12, %rax
xorl %edx, %edx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_1: # %.loopexit
# in Loop: Header=BB0_2 Depth=1
testl %ecx, %ecx
jle .LBB0_7
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movslq %ebp, %rdi
movslq q(,%rdi,4), %rsi
leal 1(%rdi), %r8d
decl %ecx
movl %r8d, %ebp
andl $1023, %ebp # imm = 0x3FF
cmpl $1023, %edi # imm = 0x3FF
cmovll %r8d, %ebp
movq %rsi, %rdi
shlq $12, %rdi
movl edge(%rdi), %r8d
testl %r8d, %r8d
je .LBB0_1
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
leaq (%rax,%rsi,4), %rsi
addq $dist, %rsi
leaq edge+4(%rdi), %rdi
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
movl (%rdi), %r8d
addq $4, %rdi
testl %r8d, %r8d
je .LBB0_1
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq %r8d, %r8
cmpl $0, visit(,%r8,4)
jne .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movl (%rsi), %r9d
incl %r9d
movl %r9d, dist(%rax,%r8,4)
leal 1(%rdx), %r9d
movl %r9d, %r10d
andl $1023, %r10d # imm = 0x3FF
cmpl $1023, %edx # imm = 0x3FF
cmovll %r9d, %r10d
movslq %r10d, %rdx
movl %r8d, q(,%rdx,4)
movl $1, visit(,%r8,4)
incl %ecx
movl %r10d, %edx
jmp .LBB0_6
.LBB0_7:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z3bfsi, .Lfunc_end0-_Z3bfsi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $filein, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
xorl %ebp, %ebp
movl $edge, %edi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq memset@PLT
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl $dist, %edi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.1, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_6
# %bb.1: # %.lr.ph39.preheader
leaq 12(%rsp), %r14
leaq 8(%rsp), %r15
leaq 4(%rsp), %r12
xorl %ebp, %ebp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_2: # %.loopexit
# in Loop: Header=BB1_3 Depth=1
incl %ebp
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r15, %rdx
movq %r12, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_6
.LBB1_3: # %.lr.ph39
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_2
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB1_3 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movslq 8(%rsp), %rcx
shlq $12, %rcx
movl %eax, edge(%rcx,%r13,4)
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_5
jmp .LBB1_2
.LBB1_6: # %._crit_edge
movq %rbx, %rdi
callq fclose
movl %ebp, %r15d
testl %ebp, %ebp
je .LBB1_10
# %bb.7: # %.lr.ph42.preheader
xorl %ebx, %ebx
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_9: # %_Z3bfsi.exit
# in Loop: Header=BB1_8 Depth=1
incq %rbx
cmpq %r15, %rbx
je .LBB1_10
.LBB1_8: # %.lr.ph42
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
# Child Loop BB1_19 Depth 3
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl %ebx, q(%rip)
movl $1, %eax
movq %rbx, %rcx
shlq $12, %rcx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_16: # %.loopexit.i
# in Loop: Header=BB1_17 Depth=2
testl %eax, %eax
jle .LBB1_9
.LBB1_17: # Parent Loop BB1_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_19 Depth 3
movslq %edx, %r8
movslq q(,%r8,4), %rdi
leal 1(%r8), %r9d
decl %eax
movl %r9d, %edx
andl $1023, %edx # imm = 0x3FF
cmpl $1023, %r8d # imm = 0x3FF
cmovll %r9d, %edx
movq %rdi, %r8
shlq $12, %r8
movl edge(%r8), %r9d
testl %r9d, %r9d
je .LBB1_16
# %bb.18: # %.lr.ph.i
# in Loop: Header=BB1_17 Depth=2
leaq (%rcx,%rdi,4), %rdi
addq $dist, %rdi
leaq edge+4(%r8), %r8
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_19 Depth=3
movl (%r8), %r9d
addq $4, %r8
testl %r9d, %r9d
je .LBB1_16
.LBB1_19: # Parent Loop BB1_8 Depth=1
# Parent Loop BB1_17 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r9d, %r9
cmpl $0, visit(,%r9,4)
jne .LBB1_21
# %bb.20: # in Loop: Header=BB1_19 Depth=3
movl (%rdi), %r10d
incl %r10d
movl %r10d, dist(%rcx,%r9,4)
leal 1(%rsi), %r10d
movl %r10d, %r11d
andl $1023, %r11d # imm = 0x3FF
cmpl $1023, %esi # imm = 0x3FF
cmovll %r10d, %r11d
movslq %r11d, %rsi
movl %r9d, q(,%rsi,4)
movl $1, visit(,%r9,4)
incl %eax
movl %r11d, %esi
jmp .LBB1_21
.LBB1_10: # %._crit_edge43
movl $fileout, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testl %ebp, %ebp
je .LBB1_15
# %bb.11: # %.lr.ph47.preheader
movl $dist, %ebp
movl $dist, %r13d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph47
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
movq %rbp, 16(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r12,4), %eax
movl (%rbp), %edx
cmpl %edx, %eax
cmovgl %eax, %edx
movl $.L.str.4, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
addq $4096, %rbp # imm = 0x1000
cmpq %r12, %r15
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $4096, %r13 # imm = 0x1000
movq 16(%rsp), %rbp # 8-byte Reload
addq $4, %rbp
cmpq %r15, %r14
jne .LBB1_12
.LBB1_15: # %._crit_edge48
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type filein,@object # @filein
.data
.globl filein
.p2align 4, 0x0
filein:
.asciz "/home/yuede/dataset/edge.dat"
.size filein, 29
.type fileout,@object # @fileout
.globl fileout
.p2align 4, 0x0
fileout:
.asciz "/home/yuede/dataset/edge.cpu_multi"
.size fileout, 35
.type q,@object # @q
.bss
.globl q
.p2align 4, 0x0
q:
.zero 4096
.size q, 4096
.type edge,@object # @edge
.globl edge
.p2align 4, 0x0
edge:
.zero 4194304
.size edge, 4194304
.type visit,@object # @visit
.globl visit
.p2align 4, 0x0
visit:
.zero 4096
.size visit, 4096
.type dist,@object # @dist
.globl dist
.p2align 4, 0x0
dist:
.zero 4194304
.size dist, 4194304
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %d"
.size .L.str.4, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finished!"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filein
.addrsig_sym fileout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d4683_00000000-6_bfs_cpu_array_multi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3193:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3193:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3bfsi
.type _Z3bfsi, @function
_Z3bfsi:
.LFB3189:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movl %edi, %esi
leaq visit(%rip), %rdx
movl $512, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movl %esi, q(%rip)
movl $0, %edx
movl $0, %r12d
movl $1, %r8d
leaq q(%rip), %rbp
leaq edge(%rip), %r13
leaq visit(%rip), %r9
leaq dist(%rip), %r11
movslq %esi, %rbx
salq $10, %rbx
jmp .L9
.L7:
movslq %edx, %rsi
movl %eax, 0(%rbp,%rsi,4)
cltq
movl $1, (%r9,%rax,4)
addl $1, %r8d
.L6:
addq $4, %rcx
movl -4(%rcx), %eax
testl %eax, %eax
je .L5
.L8:
movslq %eax, %rsi
cmpl $0, (%r9,%rsi,4)
jne .L6
addq %rbx, %rsi
movl (%r11,%r10,4), %edi
addl $1, %edi
movl %edi, (%r11,%rsi,4)
addl $1, %edx
cmpl $1023, %edx
jle .L7
movl %edx, %esi
sarl $31, %esi
shrl $22, %esi
addl %esi, %edx
andl $1023, %edx
subl %esi, %edx
jmp .L7
.L5:
testl %r8d, %r8d
jle .L14
.L9:
movslq %r12d, %rax
movl 0(%rbp,%rax,4), %r10d
addl $1, %r12d
subl $1, %r8d
cmpl $1024, %r12d
movl $0, %eax
cmovge %eax, %r12d
movslq %r10d, %rax
salq $12, %rax
movl 0(%r13,%rax), %eax
testl %eax, %eax
je .L5
movslq %r10d, %rcx
salq $12, %rcx
leaq 4(%r13,%rcx), %rcx
movslq %r10d, %r10
addq %rbx, %r10
jmp .L8
.L14:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3189:
.size _Z3bfsi, .-_Z3bfsi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d"
.LC2:
.string "%d %d"
.LC3:
.string "w"
.LC4:
.string " %d"
.LC5:
.string "\n"
.LC6:
.string "Finished!\n"
.text
.globl main
.type main, @function
main:
.LFB3190:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq filein(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $4194304, %edx
movl $0, %esi
leaq edge(%rip), %rdi
call memset@PLT
leaq visit(%rip), %rdx
movl $512, %ecx
movl $0, %eax
movq %rdx, %rdi
rep stosq
movl $4194304, %edx
movl $0, %esi
leaq dist(%rip), %rdi
call memset@PLT
movl $0, 12(%rsp)
leaq 48(%rsp), %r15
leaq .LC1(%rip), %r14
leaq edge(%rip), %r13
.L16:
leaq 44(%rsp), %rdx
movq %r15, %rcx
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L32
addl $1, 12(%rsp)
cmpl $0, 48(%rsp)
jle .L16
movl $0, %ebx
leaq 52(%rsp), %r12
.L18:
movq %r12, %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %ebx, %rdx
movslq 44(%rsp), %rax
salq $10, %rax
addq %rdx, %rax
movl 52(%rsp), %edx
movl %edx, 0(%r13,%rax,4)
addl $1, %ebx
cmpl %ebx, 48(%rsp)
jg .L18
jmp .L16
.L32:
movq %rbp, %rdi
call fclose@PLT
movl 12(%rsp), %ebp
testl %ebp, %ebp
jle .L20
movl $0, %ebx
.L21:
movl %ebx, %edi
call _Z3bfsi
addl $1, %ebx
cmpl %ebx, %ebp
jne .L21
leaq .LC3(%rip), %rsi
leaq fileout(%rip), %rdi
call fopen@PLT
movq %rax, %r13
leaq dist(%rip), %rax
movslq 12(%rsp), %rdx
movq %rdx, %r12
salq $12, %r12
addq %rax, %r12
negq %rdx
salq $12, %rdx
movq %rdx, 24(%rsp)
movl $0, %r15d
leaq .LC4(%rip), %r14
movq %rax, 16(%rsp)
.L23:
movl %r15d, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 24(%rsp), %rax
leaq (%r12,%rax), %rbx
movq 16(%rsp), %rbp
.L22:
movl 0(%rbp), %ecx
movl (%rbx), %eax
cmpl %eax, %ecx
cmovl %eax, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbp
addq $4096, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r15d
addq $4096, 16(%rsp)
addq $4, %r12
cmpl %r15d, 12(%rsp)
jne .L23
.L24:
movq %r13, %rdi
call fclose@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq fileout(%rip), %rdi
call fopen@PLT
movq %rax, %r13
jmp .L24
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3190:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3216:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3216:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dist
.bss
.align 32
.type dist, @object
.size dist, 4194304
dist:
.zero 4194304
.globl visit
.align 32
.type visit, @object
.size visit, 4096
visit:
.zero 4096
.globl edge
.align 32
.type edge, @object
.size edge, 4194304
edge:
.zero 4194304
.globl q
.align 32
.type q, @object
.size q, 4096
q:
.zero 4096
.globl fileout
.data
.align 32
.type fileout, @object
.size fileout, 35
fileout:
.string "/home/yuede/dataset/edge.cpu_multi"
.globl filein
.align 16
.type filein, @object
.size filein, 29
filein:
.string "/home/yuede/dataset/edge.dat"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bfs_cpu_array_multi.hip"
.globl _Z3bfsi # -- Begin function _Z3bfsi
.p2align 4, 0x90
.type _Z3bfsi,@function
_Z3bfsi: # @_Z3bfsi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl %ebx, q(%rip)
movslq %ebx, %rax
movl $1, %ecx
shlq $12, %rax
xorl %edx, %edx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_1: # %.loopexit
# in Loop: Header=BB0_2 Depth=1
testl %ecx, %ecx
jle .LBB0_7
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movslq %ebp, %rdi
movslq q(,%rdi,4), %rsi
leal 1(%rdi), %r8d
decl %ecx
movl %r8d, %ebp
andl $1023, %ebp # imm = 0x3FF
cmpl $1023, %edi # imm = 0x3FF
cmovll %r8d, %ebp
movq %rsi, %rdi
shlq $12, %rdi
movl edge(%rdi), %r8d
testl %r8d, %r8d
je .LBB0_1
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
leaq (%rax,%rsi,4), %rsi
addq $dist, %rsi
leaq edge+4(%rdi), %rdi
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=2
movl (%rdi), %r8d
addq $4, %rdi
testl %r8d, %r8d
je .LBB0_1
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq %r8d, %r8
cmpl $0, visit(,%r8,4)
jne .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=2
movl (%rsi), %r9d
incl %r9d
movl %r9d, dist(%rax,%r8,4)
leal 1(%rdx), %r9d
movl %r9d, %r10d
andl $1023, %r10d # imm = 0x3FF
cmpl $1023, %edx # imm = 0x3FF
cmovll %r9d, %r10d
movslq %r10d, %rdx
movl %r8d, q(,%rdx,4)
movl $1, visit(,%r8,4)
incl %ecx
movl %r10d, %edx
jmp .LBB0_6
.LBB0_7:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z3bfsi, .Lfunc_end0-_Z3bfsi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $filein, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
xorl %ebp, %ebp
movl $edge, %edi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq memset@PLT
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl $dist, %edi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdx
leaq 4(%rsp), %rcx
movl $.L.str.1, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_6
# %bb.1: # %.lr.ph39.preheader
leaq 12(%rsp), %r14
leaq 8(%rsp), %r15
leaq 4(%rsp), %r12
xorl %ebp, %ebp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_2: # %.loopexit
# in Loop: Header=BB1_3 Depth=1
incl %ebp
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r15, %rdx
movq %r12, %rcx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB1_6
.LBB1_3: # %.lr.ph39
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_2
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB1_3 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movslq 8(%rsp), %rcx
shlq $12, %rcx
movl %eax, edge(%rcx,%r13,4)
incq %r13
movslq 4(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_5
jmp .LBB1_2
.LBB1_6: # %._crit_edge
movq %rbx, %rdi
callq fclose
movl %ebp, %r15d
testl %ebp, %ebp
je .LBB1_10
# %bb.7: # %.lr.ph42.preheader
xorl %ebx, %ebx
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_9: # %_Z3bfsi.exit
# in Loop: Header=BB1_8 Depth=1
incq %rbx
cmpq %r15, %rbx
je .LBB1_10
.LBB1_8: # %.lr.ph42
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
# Child Loop BB1_19 Depth 3
movl $visit, %edi
movl $4096, %edx # imm = 0x1000
xorl %esi, %esi
callq memset@PLT
movl %ebx, q(%rip)
movl $1, %eax
movq %rbx, %rcx
shlq $12, %rcx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_16: # %.loopexit.i
# in Loop: Header=BB1_17 Depth=2
testl %eax, %eax
jle .LBB1_9
.LBB1_17: # Parent Loop BB1_8 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_19 Depth 3
movslq %edx, %r8
movslq q(,%r8,4), %rdi
leal 1(%r8), %r9d
decl %eax
movl %r9d, %edx
andl $1023, %edx # imm = 0x3FF
cmpl $1023, %r8d # imm = 0x3FF
cmovll %r9d, %edx
movq %rdi, %r8
shlq $12, %r8
movl edge(%r8), %r9d
testl %r9d, %r9d
je .LBB1_16
# %bb.18: # %.lr.ph.i
# in Loop: Header=BB1_17 Depth=2
leaq (%rcx,%rdi,4), %rdi
addq $dist, %rdi
leaq edge+4(%r8), %r8
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_19 Depth=3
movl (%r8), %r9d
addq $4, %r8
testl %r9d, %r9d
je .LBB1_16
.LBB1_19: # Parent Loop BB1_8 Depth=1
# Parent Loop BB1_17 Depth=2
# => This Inner Loop Header: Depth=3
movslq %r9d, %r9
cmpl $0, visit(,%r9,4)
jne .LBB1_21
# %bb.20: # in Loop: Header=BB1_19 Depth=3
movl (%rdi), %r10d
incl %r10d
movl %r10d, dist(%rcx,%r9,4)
leal 1(%rsi), %r10d
movl %r10d, %r11d
andl $1023, %r11d # imm = 0x3FF
cmpl $1023, %esi # imm = 0x3FF
cmovll %r10d, %r11d
movslq %r11d, %rsi
movl %r9d, q(,%rsi,4)
movl $1, visit(,%r9,4)
incl %eax
movl %r11d, %esi
jmp .LBB1_21
.LBB1_10: # %._crit_edge43
movl $fileout, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testl %ebp, %ebp
je .LBB1_15
# %bb.11: # %.lr.ph47.preheader
movl $dist, %ebp
movl $dist, %r13d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph47
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
movl $.L.str.2, %esi
movq %rbx, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq fprintf
movq %rbp, 16(%rsp) # 8-byte Spill
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_12 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%r12,4), %eax
movl (%rbp), %edx
cmpl %edx, %eax
cmovgl %eax, %edx
movl $.L.str.4, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r12
addq $4096, %rbp # imm = 0x1000
cmpq %r12, %r15
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r14
addq $4096, %r13 # imm = 0x1000
movq 16(%rsp), %rbp # 8-byte Reload
addq $4, %rbp
cmpq %r15, %r14
jne .LBB1_12
.LBB1_15: # %._crit_edge48
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type filein,@object # @filein
.data
.globl filein
.p2align 4, 0x0
filein:
.asciz "/home/yuede/dataset/edge.dat"
.size filein, 29
.type fileout,@object # @fileout
.globl fileout
.p2align 4, 0x0
fileout:
.asciz "/home/yuede/dataset/edge.cpu_multi"
.size fileout, 35
.type q,@object # @q
.bss
.globl q
.p2align 4, 0x0
q:
.zero 4096
.size q, 4096
.type edge,@object # @edge
.globl edge
.p2align 4, 0x0
edge:
.zero 4194304
.size edge, 4194304
.type visit,@object # @visit
.globl visit
.p2align 4, 0x0
visit:
.zero 4096
.size visit, 4096
.type dist,@object # @dist
.globl dist
.p2align 4, 0x0
dist:
.zero 4194304
.size dist, 4194304
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %d"
.size .L.str.4, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finished!"
.size .Lstr, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym filein
.addrsig_sym fileout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define max(a, b) ((a) > (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
static __device__ float E = 2.718281828;
static __device__ int getIndex(int *ids, int ndim, int *dims)
{
int i, id;
for (i = 0, id = ids[0]; i < ndim-1; i++)
id = dims[i+1] * id + ids[i+1];
return id;
}
static __device__ void getIndexes(int id, int *ids, int ndim, int *dims)
{
for (int i = ndim-1; i >=0; i--) {
ids[i] = id % dims[i];
id = id / dims[i];
}
}
/* __global__ void sliceTensorKernel(float *src, float *dst, int sdim, int ddim, int start, int block_size) */
/* { */
/* int di = blockIdx.x * block_size + threadIdx.x; */
/* /\* si is the index of src elements to be copied. */
/* The "block index" of src[si] is (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) *\/ */
/* int si = (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) * block_size + threadIdx.x; */
/* dst[di] = src[si]; */
/* } */
__global__ void sliceTensorKernel(float *src, float *dst, int start, int s_vol, int d_vol, int vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = di / d_vol * s_vol + di % d_vol + start * vol;
dst[di] = src[si];
}
__global__ void reduceArgMaxKernel(float *src, float *dst, float *arg, int dim_size, int reduce_vol, int batch_vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* src[si] is the first element in this thread to be compared, then
si = batch_vol * batch + (di - reduce_vol * batch),
where batch = di / reduce_vol,
which is the same as the following code: */
int si = (batch_vol - reduce_vol) * (di / reduce_vol) + di;
float now = src[si], max = now;
int maxi = 0;
for (int i = 1; i < dim_size; i++) {
now = src[si+i*reduce_vol];
if (now > max) {
max = now;
maxi = i;
}
}
dst[di] = max;
arg[di] = maxi;
}
__global__ void multiplyElementKernel(float *src1, float *src2, float *dst, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
dst[di] = src1[di] * src2[di];
}
__global__ void transposeTensorKernel(float *src, float *dst, int ndim, int *s_dims, int *d_dims, int *s_ids, int *d_ids, int *axes, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int *t_s_ids = s_ids + di * ndim;
int *t_d_ids = d_ids + di * ndim;
getIndexes(di, t_d_ids, ndim, d_dims);
for (int i = 0; i < ndim; i++)
t_s_ids[axes[i]] = t_d_ids[i];
int si = getIndex(t_s_ids, ndim, s_dims);
dst[di] = src[si];
}
__global__ void transformBboxSQDKernel(float *delta, float *anchor, float *res, float width, float height, float img_width, float img_height, int x_shift, int y_shift, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* int batch_idx = di / anchor_num; */
/* now only support batch_size = 1 */
float x_scale = 1.0 * width / img_width;
float y_scale = 1.0 * height / img_height;
/* (not used) si is the index of the first elements to be computed in the thread, then
si = 4 * anchor_num * batch_idx + (di - anchor_num * batch_idx),
which is the same as the following code: */
/* int si = 3 * anchor_num * batch_idx + di; */
/* take 4 elements from each of delta and anchor */
int si = di * 4;
float d[4] = {delta[si], delta[si+1], delta[si+2], delta[si+3]};
float a[4] = {anchor[si], anchor[si+1], anchor[si+2], anchor[si+3]};
/* compute and put 4 result elements to res, according to SqueezeDet's source code */
/* TODO: don't know why (maybe the resize), always has some shift compared to groundtruth*/
float cx = (a[0] + d[0] * a[2]) / x_scale + x_shift;
float cy = (a[1] + d[1] * a[3]) / y_scale + y_shift;
float w = (a[2] * (d[2] < 1 ? expf(d[2]) : d[2] * E)) / x_scale;
float h = (a[3] * (d[3] < 1 ? expf(d[3]) : d[3] * E)) / y_scale;
res[si] = min(max(cx - w * 0.5, 0), img_width - 1);
res[si+1] = min(max(cy - h * 0.5, 0), img_height - 1);
res[si+2] = max(min(cx + w * 0.5, img_width - 1), 0);
res[si+3] = max(min(cy + h * 0.5, img_height - 1), 0);
}
__global__ void pickElementsKernel(float *src, float *dst, int *idx, int stride, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = idx[di];
for (int i = 0; i < stride; i++)
dst[di*stride+i] = src[si*stride+i];
} | .file "tmpxft_0013776b_00000000-6_tensorCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
.type _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii, @function
_Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sliceTensorKernelPfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii, .-_Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
.globl _Z17sliceTensorKernelPfS_iiiiii
.type _Z17sliceTensorKernelPfS_iiiiii, @function
_Z17sliceTensorKernelPfS_iiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17sliceTensorKernelPfS_iiiiii, .-_Z17sliceTensorKernelPfS_iiiiii
.globl _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
.type _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii, @function
_Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18reduceArgMaxKernelPfS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii, .-_Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
.globl _Z18reduceArgMaxKernelPfS_S_iiiii
.type _Z18reduceArgMaxKernelPfS_S_iiiii, @function
_Z18reduceArgMaxKernelPfS_S_iiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18reduceArgMaxKernelPfS_S_iiiii, .-_Z18reduceArgMaxKernelPfS_S_iiiii
.globl _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
.type _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii, @function
_Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21multiplyElementKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii, .-_Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
.globl _Z21multiplyElementKernelPfS_S_ii
.type _Z21multiplyElementKernelPfS_S_ii, @function
_Z21multiplyElementKernelPfS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z21multiplyElementKernelPfS_S_ii, .-_Z21multiplyElementKernelPfS_S_ii
.globl _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
.type _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii, @function
_Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 248(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii, .-_Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
.globl _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.type _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, @function
_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, .-_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.globl _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
.type _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii, @function
_Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii:
.LFB2091:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 240(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22transformBboxSQDKernelPfS_S_ffffiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii, .-_Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
.globl _Z22transformBboxSQDKernelPfS_S_ffffiiii
.type _Z22transformBboxSQDKernelPfS_S_ffffiiii, @function
_Z22transformBboxSQDKernelPfS_S_ffffiiii:
.LFB2092:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z22transformBboxSQDKernelPfS_S_ffffiiii, .-_Z22transformBboxSQDKernelPfS_S_ffffiiii
.globl _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
.type _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii, @function
_Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii:
.LFB2093:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18pickElementsKernelPfS_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii, .-_Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
.globl _Z18pickElementsKernelPfS_Piiii
.type _Z18pickElementsKernelPfS_Piiii, @function
_Z18pickElementsKernelPfS_Piiii:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z18pickElementsKernelPfS_Piiii, .-_Z18pickElementsKernelPfS_Piiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18pickElementsKernelPfS_Piiii"
.align 8
.LC1:
.string "_Z22transformBboxSQDKernelPfS_S_ffffiiii"
.align 8
.LC2:
.string "_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii"
.align 8
.LC3:
.string "_Z21multiplyElementKernelPfS_S_ii"
.align 8
.LC4:
.string "_Z18reduceArgMaxKernelPfS_S_iiiii"
.align 8
.LC5:
.string "_Z17sliceTensorKernelPfS_iiiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "E"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18pickElementsKernelPfS_Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22transformBboxSQDKernelPfS_S_ffffiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21multiplyElementKernelPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18reduceArgMaxKernelPfS_S_iiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sliceTensorKernelPfS_iiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1E(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1E
.comm _ZL1E,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define max(a, b) ((a) > (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
static __device__ float E = 2.718281828;
static __device__ int getIndex(int *ids, int ndim, int *dims)
{
int i, id;
for (i = 0, id = ids[0]; i < ndim-1; i++)
id = dims[i+1] * id + ids[i+1];
return id;
}
static __device__ void getIndexes(int id, int *ids, int ndim, int *dims)
{
for (int i = ndim-1; i >=0; i--) {
ids[i] = id % dims[i];
id = id / dims[i];
}
}
/* __global__ void sliceTensorKernel(float *src, float *dst, int sdim, int ddim, int start, int block_size) */
/* { */
/* int di = blockIdx.x * block_size + threadIdx.x; */
/* /\* si is the index of src elements to be copied. */
/* The "block index" of src[si] is (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) *\/ */
/* int si = (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) * block_size + threadIdx.x; */
/* dst[di] = src[si]; */
/* } */
__global__ void sliceTensorKernel(float *src, float *dst, int start, int s_vol, int d_vol, int vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = di / d_vol * s_vol + di % d_vol + start * vol;
dst[di] = src[si];
}
__global__ void reduceArgMaxKernel(float *src, float *dst, float *arg, int dim_size, int reduce_vol, int batch_vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* src[si] is the first element in this thread to be compared, then
si = batch_vol * batch + (di - reduce_vol * batch),
where batch = di / reduce_vol,
which is the same as the following code: */
int si = (batch_vol - reduce_vol) * (di / reduce_vol) + di;
float now = src[si], max = now;
int maxi = 0;
for (int i = 1; i < dim_size; i++) {
now = src[si+i*reduce_vol];
if (now > max) {
max = now;
maxi = i;
}
}
dst[di] = max;
arg[di] = maxi;
}
__global__ void multiplyElementKernel(float *src1, float *src2, float *dst, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
dst[di] = src1[di] * src2[di];
}
__global__ void transposeTensorKernel(float *src, float *dst, int ndim, int *s_dims, int *d_dims, int *s_ids, int *d_ids, int *axes, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int *t_s_ids = s_ids + di * ndim;
int *t_d_ids = d_ids + di * ndim;
getIndexes(di, t_d_ids, ndim, d_dims);
for (int i = 0; i < ndim; i++)
t_s_ids[axes[i]] = t_d_ids[i];
int si = getIndex(t_s_ids, ndim, s_dims);
dst[di] = src[si];
}
__global__ void transformBboxSQDKernel(float *delta, float *anchor, float *res, float width, float height, float img_width, float img_height, int x_shift, int y_shift, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* int batch_idx = di / anchor_num; */
/* now only support batch_size = 1 */
float x_scale = 1.0 * width / img_width;
float y_scale = 1.0 * height / img_height;
/* (not used) si is the index of the first elements to be computed in the thread, then
si = 4 * anchor_num * batch_idx + (di - anchor_num * batch_idx),
which is the same as the following code: */
/* int si = 3 * anchor_num * batch_idx + di; */
/* take 4 elements from each of delta and anchor */
int si = di * 4;
float d[4] = {delta[si], delta[si+1], delta[si+2], delta[si+3]};
float a[4] = {anchor[si], anchor[si+1], anchor[si+2], anchor[si+3]};
/* compute and put 4 result elements to res, according to SqueezeDet's source code */
/* TODO: don't know why (maybe the resize), always has some shift compared to groundtruth*/
float cx = (a[0] + d[0] * a[2]) / x_scale + x_shift;
float cy = (a[1] + d[1] * a[3]) / y_scale + y_shift;
float w = (a[2] * (d[2] < 1 ? expf(d[2]) : d[2] * E)) / x_scale;
float h = (a[3] * (d[3] < 1 ? expf(d[3]) : d[3] * E)) / y_scale;
res[si] = min(max(cx - w * 0.5, 0), img_width - 1);
res[si+1] = min(max(cy - h * 0.5, 0), img_height - 1);
res[si+2] = max(min(cx + w * 0.5, img_width - 1), 0);
res[si+3] = max(min(cy + h * 0.5, img_height - 1), 0);
}
__global__ void pickElementsKernel(float *src, float *dst, int *idx, int stride, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = idx[di];
for (int i = 0; i < stride; i++)
dst[di*stride+i] = src[si*stride+i];
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define max(a, b) ((a) > (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
static __device__ float E = 2.718281828;
static __device__ int getIndex(int *ids, int ndim, int *dims)
{
int i, id;
for (i = 0, id = ids[0]; i < ndim-1; i++)
id = dims[i+1] * id + ids[i+1];
return id;
}
static __device__ void getIndexes(int id, int *ids, int ndim, int *dims)
{
for (int i = ndim-1; i >=0; i--) {
ids[i] = id % dims[i];
id = id / dims[i];
}
}
/* __global__ void sliceTensorKernel(float *src, float *dst, int sdim, int ddim, int start, int block_size) */
/* { */
/* int di = blockIdx.x * block_size + threadIdx.x; */
/* /\* si is the index of src elements to be copied. */
/* The "block index" of src[si] is (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) *\/ */
/* int si = (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) * block_size + threadIdx.x; */
/* dst[di] = src[si]; */
/* } */
__global__ void sliceTensorKernel(float *src, float *dst, int start, int s_vol, int d_vol, int vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = di / d_vol * s_vol + di % d_vol + start * vol;
dst[di] = src[si];
}
__global__ void reduceArgMaxKernel(float *src, float *dst, float *arg, int dim_size, int reduce_vol, int batch_vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* src[si] is the first element in this thread to be compared, then
si = batch_vol * batch + (di - reduce_vol * batch),
where batch = di / reduce_vol,
which is the same as the following code: */
int si = (batch_vol - reduce_vol) * (di / reduce_vol) + di;
float now = src[si], max = now;
int maxi = 0;
for (int i = 1; i < dim_size; i++) {
now = src[si+i*reduce_vol];
if (now > max) {
max = now;
maxi = i;
}
}
dst[di] = max;
arg[di] = maxi;
}
__global__ void multiplyElementKernel(float *src1, float *src2, float *dst, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
dst[di] = src1[di] * src2[di];
}
__global__ void transposeTensorKernel(float *src, float *dst, int ndim, int *s_dims, int *d_dims, int *s_ids, int *d_ids, int *axes, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int *t_s_ids = s_ids + di * ndim;
int *t_d_ids = d_ids + di * ndim;
getIndexes(di, t_d_ids, ndim, d_dims);
for (int i = 0; i < ndim; i++)
t_s_ids[axes[i]] = t_d_ids[i];
int si = getIndex(t_s_ids, ndim, s_dims);
dst[di] = src[si];
}
__global__ void transformBboxSQDKernel(float *delta, float *anchor, float *res, float width, float height, float img_width, float img_height, int x_shift, int y_shift, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* int batch_idx = di / anchor_num; */
/* now only support batch_size = 1 */
float x_scale = 1.0 * width / img_width;
float y_scale = 1.0 * height / img_height;
/* (not used) si is the index of the first elements to be computed in the thread, then
si = 4 * anchor_num * batch_idx + (di - anchor_num * batch_idx),
which is the same as the following code: */
/* int si = 3 * anchor_num * batch_idx + di; */
/* take 4 elements from each of delta and anchor */
int si = di * 4;
float d[4] = {delta[si], delta[si+1], delta[si+2], delta[si+3]};
float a[4] = {anchor[si], anchor[si+1], anchor[si+2], anchor[si+3]};
/* compute and put 4 result elements to res, according to SqueezeDet's source code */
/* TODO: don't know why (maybe the resize), always has some shift compared to groundtruth*/
float cx = (a[0] + d[0] * a[2]) / x_scale + x_shift;
float cy = (a[1] + d[1] * a[3]) / y_scale + y_shift;
float w = (a[2] * (d[2] < 1 ? expf(d[2]) : d[2] * E)) / x_scale;
float h = (a[3] * (d[3] < 1 ? expf(d[3]) : d[3] * E)) / y_scale;
res[si] = min(max(cx - w * 0.5, 0), img_width - 1);
res[si+1] = min(max(cy - h * 0.5, 0), img_height - 1);
res[si+2] = max(min(cx + w * 0.5, img_width - 1), 0);
res[si+3] = max(min(cy + h * 0.5, img_height - 1), 0);
}
__global__ void pickElementsKernel(float *src, float *dst, int *idx, int stride, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = idx[di];
for (int i = 0; i < stride; i++)
dst[di*stride+i] = src[si*stride+i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define max(a, b) ((a) > (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
static __device__ float E = 2.718281828;
static __device__ int getIndex(int *ids, int ndim, int *dims)
{
int i, id;
for (i = 0, id = ids[0]; i < ndim-1; i++)
id = dims[i+1] * id + ids[i+1];
return id;
}
static __device__ void getIndexes(int id, int *ids, int ndim, int *dims)
{
for (int i = ndim-1; i >=0; i--) {
ids[i] = id % dims[i];
id = id / dims[i];
}
}
/* __global__ void sliceTensorKernel(float *src, float *dst, int sdim, int ddim, int start, int block_size) */
/* { */
/* int di = blockIdx.x * block_size + threadIdx.x; */
/* /\* si is the index of src elements to be copied. */
/* The "block index" of src[si] is (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) *\/ */
/* int si = (blockIdx.x / ddim * sdim + blockIdx.x % ddim + start) * block_size + threadIdx.x; */
/* dst[di] = src[si]; */
/* } */
__global__ void sliceTensorKernel(float *src, float *dst, int start, int s_vol, int d_vol, int vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = di / d_vol * s_vol + di % d_vol + start * vol;
dst[di] = src[si];
}
__global__ void reduceArgMaxKernel(float *src, float *dst, float *arg, int dim_size, int reduce_vol, int batch_vol, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* src[si] is the first element in this thread to be compared, then
si = batch_vol * batch + (di - reduce_vol * batch),
where batch = di / reduce_vol,
which is the same as the following code: */
int si = (batch_vol - reduce_vol) * (di / reduce_vol) + di;
float now = src[si], max = now;
int maxi = 0;
for (int i = 1; i < dim_size; i++) {
now = src[si+i*reduce_vol];
if (now > max) {
max = now;
maxi = i;
}
}
dst[di] = max;
arg[di] = maxi;
}
__global__ void multiplyElementKernel(float *src1, float *src2, float *dst, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
dst[di] = src1[di] * src2[di];
}
__global__ void transposeTensorKernel(float *src, float *dst, int ndim, int *s_dims, int *d_dims, int *s_ids, int *d_ids, int *axes, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int *t_s_ids = s_ids + di * ndim;
int *t_d_ids = d_ids + di * ndim;
getIndexes(di, t_d_ids, ndim, d_dims);
for (int i = 0; i < ndim; i++)
t_s_ids[axes[i]] = t_d_ids[i];
int si = getIndex(t_s_ids, ndim, s_dims);
dst[di] = src[si];
}
__global__ void transformBboxSQDKernel(float *delta, float *anchor, float *res, float width, float height, float img_width, float img_height, int x_shift, int y_shift, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
/* int batch_idx = di / anchor_num; */
/* now only support batch_size = 1 */
float x_scale = 1.0 * width / img_width;
float y_scale = 1.0 * height / img_height;
/* (not used) si is the index of the first elements to be computed in the thread, then
si = 4 * anchor_num * batch_idx + (di - anchor_num * batch_idx),
which is the same as the following code: */
/* int si = 3 * anchor_num * batch_idx + di; */
/* take 4 elements from each of delta and anchor */
int si = di * 4;
float d[4] = {delta[si], delta[si+1], delta[si+2], delta[si+3]};
float a[4] = {anchor[si], anchor[si+1], anchor[si+2], anchor[si+3]};
/* compute and put 4 result elements to res, according to SqueezeDet's source code */
/* TODO: don't know why (maybe the resize), always has some shift compared to groundtruth*/
float cx = (a[0] + d[0] * a[2]) / x_scale + x_shift;
float cy = (a[1] + d[1] * a[3]) / y_scale + y_shift;
float w = (a[2] * (d[2] < 1 ? expf(d[2]) : d[2] * E)) / x_scale;
float h = (a[3] * (d[3] < 1 ? expf(d[3]) : d[3] * E)) / y_scale;
res[si] = min(max(cx - w * 0.5, 0), img_width - 1);
res[si+1] = min(max(cy - h * 0.5, 0), img_height - 1);
res[si+2] = max(min(cx + w * 0.5, img_width - 1), 0);
res[si+3] = max(min(cy + h * 0.5, img_height - 1), 0);
}
__global__ void pickElementsKernel(float *src, float *dst, int *idx, int stride, int block_size, int total)
{
int di = blockIdx.x * block_size + threadIdx.x;
if (di >= total)
return;
int si = idx[di];
for (int i = 0; i < stride; i++)
dst[di*stride+i] = src[si*stride+i];
} | .text
.file "tensorCuda.hip"
.globl _Z32__device_stub__sliceTensorKernelPfS_iiiiii # -- Begin function _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.p2align 4, 0x90
.type _Z32__device_stub__sliceTensorKernelPfS_iiiiii,@function
_Z32__device_stub__sliceTensorKernelPfS_iiiiii: # @_Z32__device_stub__sliceTensorKernelPfS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sliceTensorKernelPfS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__sliceTensorKernelPfS_iiiiii, .Lfunc_end0-_Z32__device_stub__sliceTensorKernelPfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii # -- Begin function _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.p2align 4, 0x90
.type _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii,@function
_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii: # @_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18reduceArgMaxKernelPfS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii, .Lfunc_end1-_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__multiplyElementKernelPfS_S_ii # -- Begin function _Z36__device_stub__multiplyElementKernelPfS_S_ii
.p2align 4, 0x90
.type _Z36__device_stub__multiplyElementKernelPfS_S_ii,@function
_Z36__device_stub__multiplyElementKernelPfS_S_ii: # @_Z36__device_stub__multiplyElementKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21multiplyElementKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z36__device_stub__multiplyElementKernelPfS_S_ii, .Lfunc_end2-_Z36__device_stub__multiplyElementKernelPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii # -- Begin function _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.p2align 4, 0x90
.type _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii,@function
_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii: # @_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, .Lfunc_end3-_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii # -- Begin function _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.p2align 4, 0x90
.type _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii,@function
_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii: # @_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 208(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22transformBboxSQDKernelPfS_S_ffffiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end4:
.size _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii, .Lfunc_end4-_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__pickElementsKernelPfS_Piiii # -- Begin function _Z33__device_stub__pickElementsKernelPfS_Piiii
.p2align 4, 0x90
.type _Z33__device_stub__pickElementsKernelPfS_Piiii,@function
_Z33__device_stub__pickElementsKernelPfS_Piiii: # @_Z33__device_stub__pickElementsKernelPfS_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18pickElementsKernelPfS_Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z33__device_stub__pickElementsKernelPfS_Piiii, .Lfunc_end5-_Z33__device_stub__pickElementsKernelPfS_Piiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sliceTensorKernelPfS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18reduceArgMaxKernelPfS_S_iiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21multiplyElementKernelPfS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22transformBboxSQDKernelPfS_S_ffffiiii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18pickElementsKernelPfS_Piiii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sliceTensorKernelPfS_iiiiii,@object # @_Z17sliceTensorKernelPfS_iiiiii
.section .rodata,"a",@progbits
.globl _Z17sliceTensorKernelPfS_iiiiii
.p2align 3, 0x0
_Z17sliceTensorKernelPfS_iiiiii:
.quad _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.size _Z17sliceTensorKernelPfS_iiiiii, 8
.type _Z18reduceArgMaxKernelPfS_S_iiiii,@object # @_Z18reduceArgMaxKernelPfS_S_iiiii
.globl _Z18reduceArgMaxKernelPfS_S_iiiii
.p2align 3, 0x0
_Z18reduceArgMaxKernelPfS_S_iiiii:
.quad _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.size _Z18reduceArgMaxKernelPfS_S_iiiii, 8
.type _Z21multiplyElementKernelPfS_S_ii,@object # @_Z21multiplyElementKernelPfS_S_ii
.globl _Z21multiplyElementKernelPfS_S_ii
.p2align 3, 0x0
_Z21multiplyElementKernelPfS_S_ii:
.quad _Z36__device_stub__multiplyElementKernelPfS_S_ii
.size _Z21multiplyElementKernelPfS_S_ii, 8
.type _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii,@object # @_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.globl _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.p2align 3, 0x0
_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii:
.quad _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.size _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, 8
.type _Z22transformBboxSQDKernelPfS_S_ffffiiii,@object # @_Z22transformBboxSQDKernelPfS_S_ffffiiii
.globl _Z22transformBboxSQDKernelPfS_S_ffffiiii
.p2align 3, 0x0
_Z22transformBboxSQDKernelPfS_S_ffffiiii:
.quad _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.size _Z22transformBboxSQDKernelPfS_S_ffffiiii, 8
.type _Z18pickElementsKernelPfS_Piiii,@object # @_Z18pickElementsKernelPfS_Piiii
.globl _Z18pickElementsKernelPfS_Piiii
.p2align 3, 0x0
_Z18pickElementsKernelPfS_Piiii:
.quad _Z33__device_stub__pickElementsKernelPfS_Piiii
.size _Z18pickElementsKernelPfS_Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sliceTensorKernelPfS_iiiiii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18reduceArgMaxKernelPfS_S_iiiii"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21multiplyElementKernelPfS_S_ii"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii"
.size .L__unnamed_4, 47
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z22transformBboxSQDKernelPfS_S_ffffiiii"
.size .L__unnamed_5, 41
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z18pickElementsKernelPfS_Piiii"
.size .L__unnamed_6, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.addrsig_sym _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.addrsig_sym _Z36__device_stub__multiplyElementKernelPfS_S_ii
.addrsig_sym _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.addrsig_sym _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.addrsig_sym _Z33__device_stub__pickElementsKernelPfS_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sliceTensorKernelPfS_iiiiii
.addrsig_sym _Z18reduceArgMaxKernelPfS_S_iiiii
.addrsig_sym _Z21multiplyElementKernelPfS_S_ii
.addrsig_sym _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.addrsig_sym _Z22transformBboxSQDKernelPfS_S_ffffiiii
.addrsig_sym _Z18pickElementsKernelPfS_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013776b_00000000-6_tensorCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
.type _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii, @function
_Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sliceTensorKernelPfS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii, .-_Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
.globl _Z17sliceTensorKernelPfS_iiiiii
.type _Z17sliceTensorKernelPfS_iiiiii, @function
_Z17sliceTensorKernelPfS_iiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17sliceTensorKernelPfS_iiiiiiPfS_iiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17sliceTensorKernelPfS_iiiiii, .-_Z17sliceTensorKernelPfS_iiiiii
.globl _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
.type _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii, @function
_Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18reduceArgMaxKernelPfS_S_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii, .-_Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
.globl _Z18reduceArgMaxKernelPfS_S_iiiii
.type _Z18reduceArgMaxKernelPfS_S_iiiii, @function
_Z18reduceArgMaxKernelPfS_S_iiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z18reduceArgMaxKernelPfS_S_iiiiiPfS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18reduceArgMaxKernelPfS_S_iiiii, .-_Z18reduceArgMaxKernelPfS_S_iiiii
.globl _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
.type _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii, @function
_Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21multiplyElementKernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii, .-_Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
.globl _Z21multiplyElementKernelPfS_S_ii
.type _Z21multiplyElementKernelPfS_S_ii, @function
_Z21multiplyElementKernelPfS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21multiplyElementKernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z21multiplyElementKernelPfS_S_ii, .-_Z21multiplyElementKernelPfS_S_ii
.globl _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
.type _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii, @function
_Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 248(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii, .-_Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
.globl _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.type _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, @function
_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z60__device_stub__Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_iiPfS_iPiS0_S0_S0_S0_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, .-_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.globl _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
.type _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii, @function
_Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii:
.LFB2091:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 240(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z22transformBboxSQDKernelPfS_S_ffffiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii, .-_Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
.globl _Z22transformBboxSQDKernelPfS_S_ffffiiii
.type _Z22transformBboxSQDKernelPfS_S_ffffiiii, @function
_Z22transformBboxSQDKernelPfS_S_ffffiiii:
.LFB2092:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z22transformBboxSQDKernelPfS_S_ffffiiiiPfS_S_ffffiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z22transformBboxSQDKernelPfS_S_ffffiiii, .-_Z22transformBboxSQDKernelPfS_S_ffffiiii
.globl _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
.type _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii, @function
_Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii:
.LFB2093:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18pickElementsKernelPfS_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii, .-_Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
.globl _Z18pickElementsKernelPfS_Piiii
.type _Z18pickElementsKernelPfS_Piiii, @function
_Z18pickElementsKernelPfS_Piiii:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z18pickElementsKernelPfS_PiiiiPfS_Piiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z18pickElementsKernelPfS_Piiii, .-_Z18pickElementsKernelPfS_Piiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18pickElementsKernelPfS_Piiii"
.align 8
.LC1:
.string "_Z22transformBboxSQDKernelPfS_S_ffffiiii"
.align 8
.LC2:
.string "_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii"
.align 8
.LC3:
.string "_Z21multiplyElementKernelPfS_S_ii"
.align 8
.LC4:
.string "_Z18reduceArgMaxKernelPfS_S_iiiii"
.align 8
.LC5:
.string "_Z17sliceTensorKernelPfS_iiiiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "E"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18pickElementsKernelPfS_Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22transformBboxSQDKernelPfS_S_ffffiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21multiplyElementKernelPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18reduceArgMaxKernelPfS_S_iiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sliceTensorKernelPfS_iiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1E(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1E
.comm _ZL1E,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tensorCuda.hip"
.globl _Z32__device_stub__sliceTensorKernelPfS_iiiiii # -- Begin function _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.p2align 4, 0x90
.type _Z32__device_stub__sliceTensorKernelPfS_iiiiii,@function
_Z32__device_stub__sliceTensorKernelPfS_iiiiii: # @_Z32__device_stub__sliceTensorKernelPfS_iiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sliceTensorKernelPfS_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__sliceTensorKernelPfS_iiiiii, .Lfunc_end0-_Z32__device_stub__sliceTensorKernelPfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii # -- Begin function _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.p2align 4, 0x90
.type _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii,@function
_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii: # @_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18reduceArgMaxKernelPfS_S_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii, .Lfunc_end1-_Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__multiplyElementKernelPfS_S_ii # -- Begin function _Z36__device_stub__multiplyElementKernelPfS_S_ii
.p2align 4, 0x90
.type _Z36__device_stub__multiplyElementKernelPfS_S_ii,@function
_Z36__device_stub__multiplyElementKernelPfS_S_ii: # @_Z36__device_stub__multiplyElementKernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21multiplyElementKernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z36__device_stub__multiplyElementKernelPfS_S_ii, .Lfunc_end2-_Z36__device_stub__multiplyElementKernelPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii # -- Begin function _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.p2align 4, 0x90
.type _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii,@function
_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii: # @_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end3:
.size _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, .Lfunc_end3-_Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii # -- Begin function _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.p2align 4, 0x90
.type _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii,@function
_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii: # @_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 208(%rsp), %rax
movq %rax, 192(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z22transformBboxSQDKernelPfS_S_ffffiiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end4:
.size _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii, .Lfunc_end4-_Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__pickElementsKernelPfS_Piiii # -- Begin function _Z33__device_stub__pickElementsKernelPfS_Piiii
.p2align 4, 0x90
.type _Z33__device_stub__pickElementsKernelPfS_Piiii,@function
_Z33__device_stub__pickElementsKernelPfS_Piiii: # @_Z33__device_stub__pickElementsKernelPfS_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18pickElementsKernelPfS_Piiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z33__device_stub__pickElementsKernelPfS_Piiii, .Lfunc_end5-_Z33__device_stub__pickElementsKernelPfS_Piiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sliceTensorKernelPfS_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18reduceArgMaxKernelPfS_S_iiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21multiplyElementKernelPfS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22transformBboxSQDKernelPfS_S_ffffiiii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18pickElementsKernelPfS_Piiii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sliceTensorKernelPfS_iiiiii,@object # @_Z17sliceTensorKernelPfS_iiiiii
.section .rodata,"a",@progbits
.globl _Z17sliceTensorKernelPfS_iiiiii
.p2align 3, 0x0
_Z17sliceTensorKernelPfS_iiiiii:
.quad _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.size _Z17sliceTensorKernelPfS_iiiiii, 8
.type _Z18reduceArgMaxKernelPfS_S_iiiii,@object # @_Z18reduceArgMaxKernelPfS_S_iiiii
.globl _Z18reduceArgMaxKernelPfS_S_iiiii
.p2align 3, 0x0
_Z18reduceArgMaxKernelPfS_S_iiiii:
.quad _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.size _Z18reduceArgMaxKernelPfS_S_iiiii, 8
.type _Z21multiplyElementKernelPfS_S_ii,@object # @_Z21multiplyElementKernelPfS_S_ii
.globl _Z21multiplyElementKernelPfS_S_ii
.p2align 3, 0x0
_Z21multiplyElementKernelPfS_S_ii:
.quad _Z36__device_stub__multiplyElementKernelPfS_S_ii
.size _Z21multiplyElementKernelPfS_S_ii, 8
.type _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii,@object # @_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.globl _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.p2align 3, 0x0
_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii:
.quad _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.size _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii, 8
.type _Z22transformBboxSQDKernelPfS_S_ffffiiii,@object # @_Z22transformBboxSQDKernelPfS_S_ffffiiii
.globl _Z22transformBboxSQDKernelPfS_S_ffffiiii
.p2align 3, 0x0
_Z22transformBboxSQDKernelPfS_S_ffffiiii:
.quad _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.size _Z22transformBboxSQDKernelPfS_S_ffffiiii, 8
.type _Z18pickElementsKernelPfS_Piiii,@object # @_Z18pickElementsKernelPfS_Piiii
.globl _Z18pickElementsKernelPfS_Piiii
.p2align 3, 0x0
_Z18pickElementsKernelPfS_Piiii:
.quad _Z33__device_stub__pickElementsKernelPfS_Piiii
.size _Z18pickElementsKernelPfS_Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sliceTensorKernelPfS_iiiiii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z18reduceArgMaxKernelPfS_S_iiiii"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21multiplyElementKernelPfS_S_ii"
.size .L__unnamed_3, 34
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii"
.size .L__unnamed_4, 47
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z22transformBboxSQDKernelPfS_S_ffffiiii"
.size .L__unnamed_5, 41
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z18pickElementsKernelPfS_Piiii"
.size .L__unnamed_6, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sliceTensorKernelPfS_iiiiii
.addrsig_sym _Z33__device_stub__reduceArgMaxKernelPfS_S_iiiii
.addrsig_sym _Z36__device_stub__multiplyElementKernelPfS_S_ii
.addrsig_sym _Z36__device_stub__transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.addrsig_sym _Z37__device_stub__transformBboxSQDKernelPfS_S_ffffiiii
.addrsig_sym _Z33__device_stub__pickElementsKernelPfS_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sliceTensorKernelPfS_iiiiii
.addrsig_sym _Z18reduceArgMaxKernelPfS_S_iiiii
.addrsig_sym _Z21multiplyElementKernelPfS_S_ii
.addrsig_sym _Z21transposeTensorKernelPfS_iPiS0_S0_S0_S0_ii
.addrsig_sym _Z22transformBboxSQDKernelPfS_S_ffffiiii
.addrsig_sym _Z18pickElementsKernelPfS_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
cudaMalloc(&d_grid, bytes);
cudaMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaFuncSetCacheConfig(GOL, cudaFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
cudaMemcpy(d_grid, h_grid, bytes, cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
cudaEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
cudaEventRecord(stop);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
printf("CUDA error %s\n", cudaGetErrorString(error));
// Copy back results and sum
cudaMemcpy(h_grid, d_grid, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
cudaFree(d_grid);
cudaFree(d_newGrid);
free(h_grid);
return 0;
} | code for sm_80
Function : _Z3GOLiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x1d0 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0070*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0080*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00c0*/ UIADD3 UR7, UR6, 0x1, URZ ; /* 0x0000000106077890 */
/* 0x000fe2000fffe03f */
/*00d0*/ IMAD R0, R0, UR4, R5 ; /* 0x0000000400007c24 */
/* 0x001fe2000f8e0205 */
/*00e0*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fc40000000000 */
/*00f0*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe4000fffe03f */
/*0100*/ ISETP.GT.AND P1, PT, R0.reuse, UR7, PT ; /* 0x0000000700007c0c */
/* 0x040fe4000bf24270 */
/*0110*/ ISETP.GT.AND P0, PT, R0.reuse, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x040fe20003f04270 */
/*0120*/ IMAD R3, R3, UR5, R4.reuse ; /* 0x0000000503037c24 */
/* 0x102fe4000f8e0204 */
/*0130*/ IMAD R13, R5, 0x20, R4 ; /* 0x00000020050d7824 */
/* 0x000fe400078e0204 */
/*0140*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*0150*/ ISETP.GT.OR P1, PT, R3, UR7, P1 ; /* 0x0000000703007c0c */
/* 0x000fc40008f24670 */
/*0160*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fd60000704670 */
/*0170*/ @P1 BRA 0x1c0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*01a0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000004800 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0200*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fc40000000a00 */
/*0210*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fcc000fffe13f */
/*0220*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf05270 */
/*0230*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0240*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fc80004702670 */
/*0250*/ ISETP.EQ.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80000702670 */
/*0260*/ ISETP.EQ.OR P0, PT, R4, UR4, P0 ; /* 0x0000000404007c0c */
/* 0x000fda0008702670 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R2, [R13.X4+-0x80] ; /* 0xffff80000d027984 */
/* 0x001fe80000004800 */
/*0290*/ LDS R3, [R13.X4+0x80] ; /* 0x000080000d037984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS R4, [R13.X4+0x4] ; /* 0x000004000d047984 */
/* 0x000e280000004800 */
/*02b0*/ LDS R5, [R13.X4+-0x4] ; /* 0xfffffc000d057984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R6, [R13.X4+0x84] ; /* 0x000084000d067984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R7, [R13.X4+-0x84] ; /* 0xffff7c000d077984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R8, [R13.X4+-0x7c] ; /* 0xffff84000d087984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R9, [R13.X4+0x7c] ; /* 0x00007c000d097984 */
/* 0x000ee80000004800 */
/*0300*/ LDS R11, [R13.X4] ; /* 0x000000000d0b7984 */
/* 0x000f220000004800 */
/*0310*/ IADD3 R2, R4, R2, R3 ; /* 0x0000000204027210 */
/* 0x001fe20007ffe003 */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0330*/ IADD3 R2, R6, R2, R5 ; /* 0x0000000206027210 */
/* 0x002fc80007ffe005 */
/*0340*/ IADD3 R2, R8, R2, R7 ; /* 0x0000000208027210 */
/* 0x004fca0007ffe007 */
/*0350*/ IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102097824 */
/* 0x008fe400078e0209 */
/*0360*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e0203 */
/*0370*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x010fe40003f05270 */
/*0380*/ ISETP.LT.AND P1, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fda0003f21270 */
/*0390*/ @!P0 BRA P1, 0x4b0 ; /* 0x0000011000008947 */
/* 0x000fea0000800000 */
/*03a0*/ LOP3.LUT R0, R9, 0x1, RZ, 0xfc, !PT ; /* 0x0000000109007812 */
/* 0x000fc800078efcff */
/*03b0*/ ISETP.EQ.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f22270 */
/*03c0*/ @!P0 BRA P1, 0x480 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*03d0*/ ISETP.GT.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f24270 */
/*03e0*/ @!P0 BRA P1, 0x460 ; /* 0x0000007000008947 */
/* 0x000fea0000800000 */
/*03f0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fc80003f05270 */
/*0400*/ ISETP.EQ.AND P0, PT, R11, RZ, !P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0004702270 */
/*0410*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e2000c101908 */
/*0420*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0440*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0490*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9ghostColsiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR6, 0x1, URZ ; /* 0x0000000106047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UIADD3 UR4, UR6, 0x2, URZ ; /* 0x0000000206047890 */
/* 0x000fe2000fffe03f */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fca00000001ff */
/*00a0*/ IMAD R0, R0, UR4, RZ ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0110*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x004fe8000c101904 */
/*0120*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x008fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9ghostRowsiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R2, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R3, [R2.64+0xc] ; /* 0x00000c0402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fc80000000f00 */
/*00d0*/ IADD3 R5, R4.reuse, 0x2, RZ ; /* 0x0000000204057810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*00f0*/ IMAD R6, R5.reuse, c[0x0][0x160], R0.reuse ; /* 0x0000580005067a24 */
/* 0x140fe400078e0200 */
/*0100*/ IMAD R4, R5, R4, R0 ; /* 0x0000000405047224 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0209 */
/*0130*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040406077981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*0160*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
cudaMalloc(&d_grid, bytes);
cudaMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaFuncSetCacheConfig(GOL, cudaFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
cudaMemcpy(d_grid, h_grid, bytes, cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
cudaEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
cudaEventRecord(stop);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
printf("CUDA error %s\n", cudaGetErrorString(error));
// Copy back results and sum
cudaMemcpy(h_grid, d_grid, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
cudaFree(d_grid);
cudaFree(d_newGrid);
free(h_grid);
return 0;
} | .file "tmpxft_00142eca_00000000-6_GOL_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9ghostRowsiPiiPi
.type _Z29__device_stub__Z9ghostRowsiPiiPi, @function
_Z29__device_stub__Z9ghostRowsiPiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9ghostRowsiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z9ghostRowsiPiiPi, .-_Z29__device_stub__Z9ghostRowsiPiiPi
.globl _Z9ghostRowsiPi
.type _Z9ghostRowsiPi, @function
_Z9ghostRowsiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9ghostRowsiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9ghostRowsiPi, .-_Z9ghostRowsiPi
.globl _Z29__device_stub__Z9ghostColsiPiiPi
.type _Z29__device_stub__Z9ghostColsiPiiPi, @function
_Z29__device_stub__Z9ghostColsiPiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9ghostColsiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9ghostColsiPiiPi, .-_Z29__device_stub__Z9ghostColsiPiiPi
.globl _Z9ghostColsiPi
.type _Z9ghostColsiPi, @function
_Z9ghostColsiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9ghostColsiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9ghostColsiPi, .-_Z9ghostColsiPi
.globl _Z25__device_stub__Z3GOLiPiS_iPiS_
.type _Z25__device_stub__Z3GOLiPiS_iPiS_, @function
_Z25__device_stub__Z3GOLiPiS_iPiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3GOLiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z3GOLiPiS_iPiS_, .-_Z25__device_stub__Z3GOLiPiS_iPiS_
.globl _Z3GOLiPiS_
.type _Z3GOLiPiS_, @function
_Z3GOLiPiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3GOLiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3GOLiPiS_, .-_Z3GOLiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error %s\n"
.LC1:
.string "Total Alive: %d\n"
.LC3:
.string "ElapsedTime: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $268566544, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $268566544, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268566544, %esi
call cudaMalloc@PLT
movl $1985, %edi
call srand@PLT
leaq 65548(%r14), %rbp
leaq 268566540(%r14), %r13
movq %rbp, %r12
.L28:
leaq -32768(%r12), %rbx
.L29:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L29
addq $32776, %r12
cmpq %r13, %r12
jne .L28
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %esi
leaq _Z3GOLiPiS_(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $1, %ecx
movl $268566544, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $274, 56(%rsp)
movl $586, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $257, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
jmp .L34
.L45:
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z29__device_stub__Z9ghostRowsiPiiPi
jmp .L31
.L46:
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z29__device_stub__Z9ghostColsiPiiPi
jmp .L32
.L33:
movq 8(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 8(%rsp)
movq %rax, 16(%rsp)
subl $1, %ebx
je .L44
.L34:
movl $32, 68(%rsp)
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L31:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L32:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z25__device_stub__Z3GOLiPiS_iPiS_
jmp .L33
.L44:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L47
.L35:
movl $2, %ecx
movl $268566544, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
movl $0, %ecx
.L36:
leaq -32768(%rbp), %rax
.L37:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rbp, %rax
jne .L37
addq $32776, %rbp
cmpq %r13, %rbp
jne .L36
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L35
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3GOLiPiS_"
.LC5:
.string "_Z9ghostColsiPi"
.LC6:
.string "_Z9ghostRowsiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3GOLiPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ghostColsiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ghostRowsiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
cudaMalloc(&d_grid, bytes);
cudaMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaFuncSetCacheConfig(GOL, cudaFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
cudaMemcpy(d_grid, h_grid, bytes, cudaMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
cudaEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
cudaEventRecord(stop);
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
printf("CUDA error %s\n", cudaGetErrorString(error));
// Copy back results and sum
cudaMemcpy(h_grid, d_grid, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
cudaFree(d_grid);
cudaFree(d_newGrid);
free(h_grid);
return 0;
} | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
hipMalloc(&d_grid, bytes);
hipMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(GOL), hipFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
hipMemcpy(d_grid, h_grid, bytes, hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
hipEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
hipEventRecord(stop);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
printf("CUDA error %s\n", hipGetErrorString(error));
// Copy back results and sum
hipMemcpy(h_grid, d_grid, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
hipFree(d_grid);
hipFree(d_newGrid);
free(h_grid);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
hipMalloc(&d_grid, bytes);
hipMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(GOL), hipFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
hipMemcpy(d_grid, h_grid, bytes, hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
hipEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
hipEventRecord(stop);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
printf("CUDA error %s\n", hipGetErrorString(error));
// Copy back results and sum
hipMemcpy(h_grid, d_grid, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
hipFree(d_grid);
hipFree(d_newGrid);
free(h_grid);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ghostRowsiPi
.globl _Z9ghostRowsiPi
.p2align 8
.type _Z9ghostRowsiPi,@function
_Z9ghostRowsiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_mov_b32 s3, exec_lo
v_add3_u32 v0, v0, s15, 1
v_cmpx_ge_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s3, s2, 2
s_add_i32 s4, s2, 1
v_add_nc_u32_e32 v1, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v5, v[1:2], off
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v5, off
global_load_b32 v2, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ghostRowsiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ghostRowsiPi, .Lfunc_end0-_Z9ghostRowsiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9ghostColsiPi
.globl _Z9ghostColsiPi
.p2align 8
.type _Z9ghostColsiPi,@function
_Z9ghostColsiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_add_i32 s3, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s3, s2, 2
s_load_b64 s[0:1], s[0:1], 0x8
v_mul_lo_u32 v0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off offset:4
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v4, off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ghostColsiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9ghostColsiPi, .Lfunc_end1-_Z9ghostColsiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3GOLiPiS_
.globl _Z3GOLiPiS_
.p2align 8
.type _Z3GOLiPiS_,@function
_Z3GOLiPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s4, -2
s_add_i32 s6, s3, -2
v_mad_u64_u32 v[6:7], null, s5, s15, v[2:3]
v_mad_u64_u32 v[4:5], null, s6, s14, v[3:4]
s_add_i32 s5, s2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v5, v4, v6
v_mad_u64_u32 v[0:1], null, v6, s5, v[4:5]
s_add_i32 s5, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, v2, 7, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s5, exec_lo
v_cmpx_ge_i32_e64 s2, v6
s_cbranch_execz .LBB2_21
v_cmp_ge_i32_e32 vcc_lo, s2, v4
v_cmp_ne_u32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB2_21
s_add_i32 s4, s4, -1
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cmp_ne_u32_e64 s2, s4, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, s3, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB2_21
v_lshlrev_b32_e32 v1, 7, v2
v_lshlrev_b32_e32 v2, 2, v3
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x80, v1
v_add_nc_u32_e32 v4, 0xffffff80, v1
v_add_nc_u32_e32 v5, 4, v2
v_add_nc_u32_e32 v6, -4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v3, v2
v_add_nc_u32_e32 v8, v4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v9, v1, v5
v_add_nc_u32_e32 v10, v1, v6
v_add_nc_u32_e32 v11, v3, v5
ds_load_b32 v7, v7
ds_load_b32 v8, v8
ds_load_b32 v9, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v12, v4, v6
v_add_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v3, v3, v6
ds_load_b32 v5, v11
ds_load_b32 v6, v12
v_add_nc_u32_e32 v1, v1, v2
ds_load_b32 v4, v4
ds_load_b32 v3, v3
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v9, v10
v_add3_u32 v1, v1, v5, v6
v_cmp_ne_u32_e64 s0, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v1, v4, v3
v_cmp_lt_i32_e64 s1, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s1
s_cbranch_execz .LBB2_19
v_and_b32_e32 v1, -2, v3
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 2, v1
s_or_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB2_16
v_cmp_gt_i32_e32 vcc_lo, 4, v3
s_or_b32 s0, s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s6, exec_lo, s1
s_cbranch_execz .LBB2_13
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_ne_u32_e64 s0, 3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s1, s2, v0
v_add_co_ci_u32_e64 v1, s1, s3, v1, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB2_10
global_store_b32 v[0:1], v2, off
.LBB2_10:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB2_12
v_mov_b32_e32 v2, 1
global_store_b32 v[0:1], v2, off
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_13:
s_and_not1_saveexec_b32 s0, s6
s_cbranch_execz .LBB2_15
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_15:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_16:
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB2_18
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_19:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB2_21
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3GOLiPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3GOLiPiS_, .Lfunc_end2-_Z3GOLiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ghostRowsiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ghostRowsiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ghostColsiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ghostColsiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3GOLiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3GOLiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* THE FOLLOWING CODE IS AUTHORED BY ADAM SIMPSON FROM
* OAK RIDGE NATIONAL LABORATORY, WITH MODIFICATIONS
* DONE BY NICOLAS BARRIOS AND MUHANNED IBRAHIM. WE DO
* NOT CLAIM OWNERSHIP NOR COPYRIGHT OVER THIS MATERIAL.
* THE ORIGINAL PUBLICATION AND REPOSITORY CAN BE FOUND HERE:
* https://www.olcf.ornl.gov/tutorials/cuda-game-of-life/
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SRAND_VALUE 1985
#define BLOCK_SIZE_x 32
#define BLOCK_SIZE_y 16
__global__ void ghostRows(int dim, int *grid) {
// We want id ∈ [1,dim]
int id = blockDim.x * blockIdx.x + threadIdx.x + 1;
if (id <= dim) {
// Copy first real row to bottom ghost row
grid[(dim + 2) * (dim + 1) + id] = grid[(dim + 2) + id];
// Copy last real row to top ghost row
grid[id] = grid[(dim + 2) * dim + id];
}
}
__global__ void ghostCols(int dim, int *grid) {
// We want id ∈ [0,dim+1]
int id = blockDim.x * blockIdx.x + threadIdx.x;
if (id <= dim + 1) {
// Copy first real column to right most ghost column
grid[id * (dim + 2) + dim + 1] = grid[id * (dim + 2) + 1];
// Copy last real column to left most ghost column
grid[id * (dim + 2)] = grid[id * (dim + 2) + dim];
}
}
__global__ void GOL(int dim, int *grid, int *newGrid) {
int iy = (blockDim.y - 2) * blockIdx.y + threadIdx.y;
int ix = (blockDim.x - 2) * blockIdx.x + threadIdx.x;
int id = iy * (dim + 2) + ix;
int i = threadIdx.y;
int j = threadIdx.x;
int numNeighbors;
// Declare the shared memory on a per block level
__shared__ int s_grid[BLOCK_SIZE_y][BLOCK_SIZE_x];
// Copy cells into shared memory
if (ix <= dim + 1 && iy <= dim + 1)
s_grid[i][j] = grid[id];
// Sync all threads in block
__syncthreads();
if (iy <= dim && ix <= dim) {
if (i != 0 && i != blockDim.y - 1 && j != 0 && j != blockDim.x - 1) {
// Get the number of neighbors for a given grid point
numNeighbors = s_grid[i + 1][j] + s_grid[i - 1][j] // upper lower
+ s_grid[i][j + 1] + s_grid[i][j - 1] // right left
+ s_grid[i + 1][j + 1] +
s_grid[i - 1][j - 1] // diagonals
+ s_grid[i - 1][j + 1] + s_grid[i + 1][j - 1];
int cell = s_grid[i][j];
// Here we have explicitly all of the game rules
if (cell == 1 && numNeighbors < 2)
newGrid[id] = 0;
else if (cell == 1 && (numNeighbors == 2 || numNeighbors == 3))
newGrid[id] = 1;
else if (cell == 1 && numNeighbors > 3)
newGrid[id] = 0;
else if (cell == 0 && numNeighbors == 3)
newGrid[id] = 1;
else
newGrid[id] = cell;
}
}
}
int main() {
int i, j, iter;
int *h_grid; // Grid on host
int *d_grid; // Grid on device
int *d_newGrid; // Second grid used on device only
int *d_tmpGrid; // tmp grid pointer used to switch between grid and newGrid
int dim = 1 << 13; // Linear dimension of our grid - not counting ghost cells
int maxIter = 100; // Number of game steps
size_t bytes = sizeof(int) * (dim + 2) * (dim + 2);
// Allocate host Grid used for initial setup and read back from device
h_grid = (int *)malloc(bytes);
// Allocate device grids
hipMalloc(&d_grid, bytes);
hipMalloc(&d_newGrid, bytes);
// Assign initial population randomly
srand(SRAND_VALUE);
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
h_grid[i * (dim + 2) + j] = rand() % 2;
}
}
// See
// https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipFuncSetCacheConfig(reinterpret_cast<const void*>(GOL), hipFuncCachePreferShared);
// Copy over initial game grid (Dim-1 threads)
hipMemcpy(d_grid, h_grid, bytes, hipMemcpyHostToDevice);
dim3 blockSize(BLOCK_SIZE_x, BLOCK_SIZE_y, 1);
int linGrid_x = (int)ceil(dim / (float)(BLOCK_SIZE_x - 2));
int linGrid_y = (int)ceil(dim / (float)(BLOCK_SIZE_y - 2));
dim3 gridSize(linGrid_x, linGrid_y, 1);
dim3 cpyBlockSize(BLOCK_SIZE_x, 1, 1);
dim3 cpyGridRowsGridSize((int)ceil(dim / (float)cpyBlockSize.x), 1, 1);
dim3 cpyGridColsGridSize((int)ceil((dim + 2) / (float)cpyBlockSize.x), 1,
1);
// Added this myself -N
#ifdef DEBUG
printf("blockSize: { %d %d %d }\n", blockSize.x, blockSize.y, blockSize.z);
printf("gridSize: { %d %d %d }\n", gridSize.x, gridSize.y, gridSize.z);
printf("cpyBlockSize: { %d %d %d }\n", cpyBlockSize.x, cpyBlockSize.y,
cpyBlockSize.z);
printf("cpyGridRowsGridSize: { %d %d %d }\n", cpyGridRowsGridSize.x,
cpyGridRowsGridSize.y, cpyGridRowsGridSize.z);
printf("cpyGridColsGridSize: { %d %d %d }\n", cpyGridColsGridSize.x,
cpyGridColsGridSize.y, cpyGridColsGridSize.z);
#endif
hipEventRecord(start);
// Main game loop
for (iter = 0; iter < maxIter; iter++) {
ghostRows<<<cpyGridRowsGridSize, cpyBlockSize>>>(dim, d_grid);
ghostCols<<<cpyGridColsGridSize, cpyBlockSize>>>(dim, d_grid);
GOL<<<gridSize, blockSize>>>(dim, d_grid, d_newGrid);
// Swap our grids and iterate again
d_tmpGrid = d_grid;
d_grid = d_newGrid;
d_newGrid = d_tmpGrid;
} // iter loop
hipEventRecord(stop);
hipError_t error = hipGetLastError();
if (error != hipSuccess)
printf("CUDA error %s\n", hipGetErrorString(error));
// Copy back results and sum
hipMemcpy(h_grid, d_grid, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipDeviceSynchronize();
// Sum up alive cells and print results
int total = 0;
for (i = 1; i <= dim; i++) {
for (j = 1; j <= dim; j++) {
#ifdef DEBUG
printf("%d", h_grid[i * (dim + 2) + j]);
#endif
total += h_grid[i * (dim + 2) + j];
}
#ifdef DEBUG
printf("\n");
#endif
}
printf("Total Alive: %d\n", total);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
printf("ElapsedTime: %f ms\n", ms);
hipFree(d_grid);
hipFree(d_newGrid);
free(h_grid);
return 0;
} | .text
.file "GOL_shared.hip"
.globl _Z24__device_stub__ghostRowsiPi # -- Begin function _Z24__device_stub__ghostRowsiPi
.p2align 4, 0x90
.type _Z24__device_stub__ghostRowsiPi,@function
_Z24__device_stub__ghostRowsiPi: # @_Z24__device_stub__ghostRowsiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9ghostRowsiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__ghostRowsiPi, .Lfunc_end0-_Z24__device_stub__ghostRowsiPi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__ghostColsiPi # -- Begin function _Z24__device_stub__ghostColsiPi
.p2align 4, 0x90
.type _Z24__device_stub__ghostColsiPi,@function
_Z24__device_stub__ghostColsiPi: # @_Z24__device_stub__ghostColsiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9ghostColsiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__ghostColsiPi, .Lfunc_end1-_Z24__device_stub__ghostColsiPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__GOLiPiS_ # -- Begin function _Z18__device_stub__GOLiPiS_
.p2align 4, 0x90
.type _Z18__device_stub__GOLiPiS_,@function
_Z18__device_stub__GOLiPiS_: # @_Z18__device_stub__GOLiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3GOLiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__GOLiPiS_, .Lfunc_end2-_Z18__device_stub__GOLiPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $268566544, %edi # imm = 0x10020010
callq malloc
movq %rax, %r12
movq %rsp, %rdi
movl $268566544, %esi # imm = 0x10020010
callq hipMalloc
leaq 64(%rsp), %rdi
movl $268566544, %esi # imm = 0x10020010
callq hipMalloc
movl $1985, %edi # imm = 0x7C1
callq srand
leaq 32780(%r12), %rbx
movl $1, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r14
addq $32776, %rbx # imm = 0x8008
cmpq $8193, %r14 # imm = 0x2001
jne .LBB3_1
# %bb.4:
movabsq $4294967328, %r14 # imm = 0x100000020
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movl $_Z3GOLiPiS_, %edi
movl $1, %esi
callq hipFuncSetCacheConfig
movq (%rsp), %rdi
movl $268566544, %edx # imm = 0x10020010
movq %r12, 128(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 224(%r14), %r15
leaq 80(%rsp), %r12
leaq 96(%rsp), %r13
leaq 225(%r14), %rbp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movq 64(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 64(%rsp)
decl %ebx
je .LBB3_12
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movl $8192, 8(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9ghostRowsiPi, %edi
movq %r13, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7: # in Loop: Header=BB3_5 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movl $8192, 8(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9ghostColsiPi, %edi
movq %r13, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_5 Depth=1
movabsq $2516850835730, %rdi # imm = 0x24A00000112
movl $1, %esi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movq 64(%rsp), %rcx
movl $8192, 92(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 92(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z3GOLiPiS_, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipGetLastError
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_14:
movq (%rsp), %rsi
movl $268566544, %edx # imm = 0x10020010
movq 128(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
movq %r14, %rax
addq $32780, %rax # imm = 0x800C
movl $1, %ecx
.p2align 4, 0x90
.LBB3_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_16 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_15 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rax,%rdx,4), %ebx
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_15 Depth=1
incq %rcx
addq $32776, %rax # imm = 0x8008
cmpq $8193, %rcx # imm = 0x2001
jne .LBB3_15
# %bb.18:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $0, 96(%rsp)
movq 120(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ghostRowsiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ghostColsiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3GOLiPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ghostRowsiPi,@object # @_Z9ghostRowsiPi
.section .rodata,"a",@progbits
.globl _Z9ghostRowsiPi
.p2align 3, 0x0
_Z9ghostRowsiPi:
.quad _Z24__device_stub__ghostRowsiPi
.size _Z9ghostRowsiPi, 8
.type _Z9ghostColsiPi,@object # @_Z9ghostColsiPi
.globl _Z9ghostColsiPi
.p2align 3, 0x0
_Z9ghostColsiPi:
.quad _Z24__device_stub__ghostColsiPi
.size _Z9ghostColsiPi, 8
.type _Z3GOLiPiS_,@object # @_Z3GOLiPiS_
.globl _Z3GOLiPiS_
.p2align 3, 0x0
_Z3GOLiPiS_:
.quad _Z18__device_stub__GOLiPiS_
.size _Z3GOLiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error %s\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total Alive: %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ElapsedTime: %f ms\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9ghostRowsiPi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9ghostColsiPi"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3GOLiPiS_"
.size .L__unnamed_3, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ghostRowsiPi
.addrsig_sym _Z24__device_stub__ghostColsiPi
.addrsig_sym _Z18__device_stub__GOLiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ghostRowsiPi
.addrsig_sym _Z9ghostColsiPi
.addrsig_sym _Z3GOLiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3GOLiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR5, 0x2 ; /* 0x0000000200057882 */
/* 0x000fe20000000000 */
/*0030*/ BSSY B0, 0x1d0 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0070*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0080*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000800 */
/*00b0*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*00c0*/ UIADD3 UR7, UR6, 0x1, URZ ; /* 0x0000000106077890 */
/* 0x000fe2000fffe03f */
/*00d0*/ IMAD R0, R0, UR4, R5 ; /* 0x0000000400007c24 */
/* 0x001fe2000f8e0205 */
/*00e0*/ UMOV UR4, 0x2 ; /* 0x0000000200047882 */
/* 0x000fc40000000000 */
/*00f0*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fe4000fffe03f */
/*0100*/ ISETP.GT.AND P1, PT, R0.reuse, UR7, PT ; /* 0x0000000700007c0c */
/* 0x040fe4000bf24270 */
/*0110*/ ISETP.GT.AND P0, PT, R0.reuse, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x040fe20003f04270 */
/*0120*/ IMAD R3, R3, UR5, R4.reuse ; /* 0x0000000503037c24 */
/* 0x102fe4000f8e0204 */
/*0130*/ IMAD R13, R5, 0x20, R4 ; /* 0x00000020050d7824 */
/* 0x000fe400078e0204 */
/*0140*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*0150*/ ISETP.GT.OR P1, PT, R3, UR7, P1 ; /* 0x0000000703007c0c */
/* 0x000fc40008f24670 */
/*0160*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fd60000704670 */
/*0170*/ @P1 BRA 0x1c0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*01a0*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ STS [R13.X4], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000004800 */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0200*/ ULDC.64 UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fc40000000a00 */
/*0210*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fcc000fffe13f */
/*0220*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf05270 */
/*0230*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0240*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fc80004702670 */
/*0250*/ ISETP.EQ.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80000702670 */
/*0260*/ ISETP.EQ.OR P0, PT, R4, UR4, P0 ; /* 0x0000000404007c0c */
/* 0x000fda0008702670 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R2, [R13.X4+-0x80] ; /* 0xffff80000d027984 */
/* 0x001fe80000004800 */
/*0290*/ LDS R3, [R13.X4+0x80] ; /* 0x000080000d037984 */
/* 0x000fe80000004800 */
/*02a0*/ LDS R4, [R13.X4+0x4] ; /* 0x000004000d047984 */
/* 0x000e280000004800 */
/*02b0*/ LDS R5, [R13.X4+-0x4] ; /* 0xfffffc000d057984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R6, [R13.X4+0x84] ; /* 0x000084000d067984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R7, [R13.X4+-0x84] ; /* 0xffff7c000d077984 */
/* 0x000fe80000004800 */
/*02e0*/ LDS R8, [R13.X4+-0x7c] ; /* 0xffff84000d087984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R9, [R13.X4+0x7c] ; /* 0x00007c000d097984 */
/* 0x000ee80000004800 */
/*0300*/ LDS R11, [R13.X4] ; /* 0x000000000d0b7984 */
/* 0x000f220000004800 */
/*0310*/ IADD3 R2, R4, R2, R3 ; /* 0x0000000204027210 */
/* 0x001fe20007ffe003 */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0330*/ IADD3 R2, R6, R2, R5 ; /* 0x0000000206027210 */
/* 0x002fc80007ffe005 */
/*0340*/ IADD3 R2, R8, R2, R7 ; /* 0x0000000208027210 */
/* 0x004fca0007ffe007 */
/*0350*/ IMAD.IADD R9, R2, 0x1, R9 ; /* 0x0000000102097824 */
/* 0x008fe400078e0209 */
/*0360*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e0203 */
/*0370*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x010fe40003f05270 */
/*0380*/ ISETP.LT.AND P1, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fda0003f21270 */
/*0390*/ @!P0 BRA P1, 0x4b0 ; /* 0x0000011000008947 */
/* 0x000fea0000800000 */
/*03a0*/ LOP3.LUT R0, R9, 0x1, RZ, 0xfc, !PT ; /* 0x0000000109007812 */
/* 0x000fc800078efcff */
/*03b0*/ ISETP.EQ.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f22270 */
/*03c0*/ @!P0 BRA P1, 0x480 ; /* 0x000000b000008947 */
/* 0x000fea0000800000 */
/*03d0*/ ISETP.GT.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f24270 */
/*03e0*/ @!P0 BRA P1, 0x460 ; /* 0x0000007000008947 */
/* 0x000fea0000800000 */
/*03f0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fc80003f05270 */
/*0400*/ ISETP.EQ.AND P0, PT, R11, RZ, !P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0004702270 */
/*0410*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e2000c101908 */
/*0420*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0440*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*0470*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0490*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101908 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9ghostColsiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR6, 0x1, URZ ; /* 0x0000000106047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ UIADD3 UR4, UR6, 0x2, URZ ; /* 0x0000000206047890 */
/* 0x000fe2000fffe03f */
/*0090*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fca00000001ff */
/*00a0*/ IMAD R0, R0, UR4, RZ ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e02ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R4, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee8000c1e1900 */
/*0110*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x004fe8000c101904 */
/*0120*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x008fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9ghostRowsiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fc80007ffe0ff */
/*0050*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R2, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00a0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R3, [R2.64+0xc] ; /* 0x00000c0402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fc80000000f00 */
/*00d0*/ IADD3 R5, R4.reuse, 0x2, RZ ; /* 0x0000000204057810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007ffe0ff */
/*00f0*/ IMAD R6, R5.reuse, c[0x0][0x160], R0.reuse ; /* 0x0000580005067a24 */
/* 0x140fe400078e0200 */
/*0100*/ IMAD R4, R5, R4, R0 ; /* 0x0000000405047224 */
/* 0x000fe400078e0200 */
/*0110*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0209 */
/*0130*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x004fe8000c101904 */
/*0140*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040406077981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*0160*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ghostRowsiPi
.globl _Z9ghostRowsiPi
.p2align 8
.type _Z9ghostRowsiPi,@function
_Z9ghostRowsiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_mov_b32 s3, exec_lo
v_add3_u32 v0, v0, s15, 1
v_cmpx_ge_i32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s3, s2, 2
s_add_i32 s4, s2, 1
v_add_nc_u32_e32 v1, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v5, v[1:2], off
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v5, off
global_load_b32 v2, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ghostRowsiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ghostRowsiPi, .Lfunc_end0-_Z9ghostRowsiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9ghostColsiPi
.globl _Z9ghostColsiPi
.p2align 8
.type _Z9ghostColsiPi,@function
_Z9ghostColsiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_add_i32 s3, s2, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
s_add_i32 s3, s2, 2
s_load_b64 s[0:1], s[0:1], 0x8
v_mul_lo_u32 v0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off offset:4
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v4, off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ghostColsiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9ghostColsiPi, .Lfunc_end1-_Z9ghostColsiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3GOLiPiS_
.globl _Z3GOLiPiS_
.p2align 8
.type _Z3GOLiPiS_,@function
_Z3GOLiPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s4, -2
s_add_i32 s6, s3, -2
v_mad_u64_u32 v[6:7], null, s5, s15, v[2:3]
v_mad_u64_u32 v[4:5], null, s6, s14, v[3:4]
s_add_i32 s5, s2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v5, v4, v6
v_mad_u64_u32 v[0:1], null, v6, s5, v[4:5]
s_add_i32 s5, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b64 s[6:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b64 v[7:8], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, v2, 7, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s5, exec_lo
v_cmpx_ge_i32_e64 s2, v6
s_cbranch_execz .LBB2_21
v_cmp_ge_i32_e32 vcc_lo, s2, v4
v_cmp_ne_u32_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB2_21
s_add_i32 s4, s4, -1
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_cmp_ne_u32_e64 s2, s4, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, s3, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB2_21
v_lshlrev_b32_e32 v1, 7, v2
v_lshlrev_b32_e32 v2, 2, v3
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x80, v1
v_add_nc_u32_e32 v4, 0xffffff80, v1
v_add_nc_u32_e32 v5, 4, v2
v_add_nc_u32_e32 v6, -4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v7, v3, v2
v_add_nc_u32_e32 v8, v4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v9, v1, v5
v_add_nc_u32_e32 v10, v1, v6
v_add_nc_u32_e32 v11, v3, v5
ds_load_b32 v7, v7
ds_load_b32 v8, v8
ds_load_b32 v9, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v12, v4, v6
v_add_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v3, v3, v6
ds_load_b32 v5, v11
ds_load_b32 v6, v12
v_add_nc_u32_e32 v1, v1, v2
ds_load_b32 v4, v4
ds_load_b32 v3, v3
ds_load_b32 v2, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v9, v10
v_add3_u32 v1, v1, v5, v6
v_cmp_ne_u32_e64 s0, 1, v2
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v1, v4, v3
v_cmp_lt_i32_e64 s1, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s1
s_cbranch_execz .LBB2_19
v_and_b32_e32 v1, -2, v3
s_xor_b32 s1, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 2, v1
s_or_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB2_16
v_cmp_gt_i32_e32 vcc_lo, 4, v3
s_or_b32 s0, s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s6, exec_lo, s1
s_cbranch_execz .LBB2_13
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_ne_u32_e64 s0, 3, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s1, s2, v0
v_add_co_ci_u32_e64 v1, s1, s3, v1, s1
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB2_10
global_store_b32 v[0:1], v2, off
.LBB2_10:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB2_12
v_mov_b32_e32 v2, 1
global_store_b32 v[0:1], v2, off
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_13:
s_and_not1_saveexec_b32 s0, s6
s_cbranch_execz .LBB2_15
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_15:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_16:
s_and_not1_saveexec_b32 s0, s5
s_cbranch_execz .LBB2_18
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s0
.LBB2_19:
s_and_not1_saveexec_b32 s0, s4
s_cbranch_execz .LBB2_21
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3GOLiPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3GOLiPiS_, .Lfunc_end2-_Z3GOLiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ghostRowsiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ghostRowsiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ghostColsiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ghostColsiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3GOLiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3GOLiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142eca_00000000-6_GOL_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9ghostRowsiPiiPi
.type _Z29__device_stub__Z9ghostRowsiPiiPi, @function
_Z29__device_stub__Z9ghostRowsiPiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9ghostRowsiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z9ghostRowsiPiiPi, .-_Z29__device_stub__Z9ghostRowsiPiiPi
.globl _Z9ghostRowsiPi
.type _Z9ghostRowsiPi, @function
_Z9ghostRowsiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9ghostRowsiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9ghostRowsiPi, .-_Z9ghostRowsiPi
.globl _Z29__device_stub__Z9ghostColsiPiiPi
.type _Z29__device_stub__Z9ghostColsiPiiPi, @function
_Z29__device_stub__Z9ghostColsiPiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9ghostColsiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z9ghostColsiPiiPi, .-_Z29__device_stub__Z9ghostColsiPiiPi
.globl _Z9ghostColsiPi
.type _Z9ghostColsiPi, @function
_Z9ghostColsiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9ghostColsiPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9ghostColsiPi, .-_Z9ghostColsiPi
.globl _Z25__device_stub__Z3GOLiPiS_iPiS_
.type _Z25__device_stub__Z3GOLiPiS_iPiS_, @function
_Z25__device_stub__Z3GOLiPiS_iPiS_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3GOLiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z3GOLiPiS_iPiS_, .-_Z25__device_stub__Z3GOLiPiS_iPiS_
.globl _Z3GOLiPiS_
.type _Z3GOLiPiS_, @function
_Z3GOLiPiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3GOLiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3GOLiPiS_, .-_Z3GOLiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error %s\n"
.LC1:
.string "Total Alive: %d\n"
.LC3:
.string "ElapsedTime: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $268566544, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $268566544, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $268566544, %esi
call cudaMalloc@PLT
movl $1985, %edi
call srand@PLT
leaq 65548(%r14), %rbp
leaq 268566540(%r14), %r13
movq %rbp, %r12
.L28:
leaq -32768(%r12), %rbx
.L29:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L29
addq $32776, %r12
cmpq %r13, %r12
jne .L28
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %esi
leaq _Z3GOLiPiS_(%rip), %rdi
call cudaFuncSetCacheConfig@PLT
movl $1, %ecx
movl $268566544, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $274, 56(%rsp)
movl $586, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $257, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
jmp .L34
.L45:
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z29__device_stub__Z9ghostRowsiPiiPi
jmp .L31
.L46:
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z29__device_stub__Z9ghostColsiPiiPi
jmp .L32
.L33:
movq 8(%rsp), %rax
movq 16(%rsp), %rdx
movq %rdx, 8(%rsp)
movq %rax, 16(%rsp)
subl $1, %ebx
je .L44
.L34:
movl $32, 68(%rsp)
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 80(%rsp), %rdi
movl 88(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L31:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L32:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $8192, %edi
call _Z25__device_stub__Z3GOLiPiS_iPiS_
jmp .L33
.L44:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L47
.L35:
movl $2, %ecx
movl $268566544, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
call cudaDeviceSynchronize@PLT
movl $0, %ecx
.L36:
leaq -32768(%rbp), %rax
.L37:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rbp, %rax
jne .L37
addq $32776, %rbp
cmpq %r13, %rbp
jne .L36
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L35
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3GOLiPiS_"
.LC5:
.string "_Z9ghostColsiPi"
.LC6:
.string "_Z9ghostRowsiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3GOLiPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ghostColsiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ghostRowsiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GOL_shared.hip"
.globl _Z24__device_stub__ghostRowsiPi # -- Begin function _Z24__device_stub__ghostRowsiPi
.p2align 4, 0x90
.type _Z24__device_stub__ghostRowsiPi,@function
_Z24__device_stub__ghostRowsiPi: # @_Z24__device_stub__ghostRowsiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9ghostRowsiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__ghostRowsiPi, .Lfunc_end0-_Z24__device_stub__ghostRowsiPi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__ghostColsiPi # -- Begin function _Z24__device_stub__ghostColsiPi
.p2align 4, 0x90
.type _Z24__device_stub__ghostColsiPi,@function
_Z24__device_stub__ghostColsiPi: # @_Z24__device_stub__ghostColsiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9ghostColsiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__ghostColsiPi, .Lfunc_end1-_Z24__device_stub__ghostColsiPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__GOLiPiS_ # -- Begin function _Z18__device_stub__GOLiPiS_
.p2align 4, 0x90
.type _Z18__device_stub__GOLiPiS_,@function
_Z18__device_stub__GOLiPiS_: # @_Z18__device_stub__GOLiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3GOLiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z18__device_stub__GOLiPiS_, .Lfunc_end2-_Z18__device_stub__GOLiPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $268566544, %edi # imm = 0x10020010
callq malloc
movq %rax, %r12
movq %rsp, %rdi
movl $268566544, %esi # imm = 0x10020010
callq hipMalloc
leaq 64(%rsp), %rdi
movl $268566544, %esi # imm = 0x10020010
callq hipMalloc
movl $1985, %edi # imm = 0x7C1
callq srand
leaq 32780(%r12), %rbx
movl $1, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader101
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $8192, %r15 # imm = 0x2000
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r14
addq $32776, %rbx # imm = 0x8008
cmpq $8193, %r14 # imm = 0x2001
jne .LBB3_1
# %bb.4:
movabsq $4294967328, %r14 # imm = 0x100000020
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movl $_Z3GOLiPiS_, %edi
movl $1, %esi
callq hipFuncSetCacheConfig
movq (%rsp), %rdi
movl $268566544, %edx # imm = 0x10020010
movq %r12, 128(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
leaq 224(%r14), %r15
leaq 80(%rsp), %r12
leaq 96(%rsp), %r13
leaq 225(%r14), %rbp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movq 64(%rsp), %rcx
movq %rcx, (%rsp)
movq %rax, 64(%rsp)
decl %ebx
je .LBB3_12
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movl $8192, 8(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9ghostRowsiPi, %edi
movq %r13, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7: # in Loop: Header=BB3_5 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movl $8192, 8(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9ghostColsiPi, %edi
movq %r13, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_5 Depth=1
movabsq $2516850835730, %rdi # imm = 0x24A00000112
movl $1, %esi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_5 Depth=1
movq (%rsp), %rax
movq 64(%rsp), %rcx
movl $8192, 92(%rsp) # imm = 0x2000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 92(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z3GOLiPiS_, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 72(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
callq hipGetLastError
testl %eax, %eax
je .LBB3_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_14:
movq (%rsp), %rsi
movl $268566544, %edx # imm = 0x10020010
movq 128(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipEventSynchronize
callq hipDeviceSynchronize
movq %r14, %rax
addq $32780, %rax # imm = 0x800C
movl $1, %ecx
.p2align 4, 0x90
.LBB3_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_16 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_16: # Parent Loop BB3_15 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rax,%rdx,4), %ebx
incq %rdx
cmpq $8192, %rdx # imm = 0x2000
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_15 Depth=1
incq %rcx
addq $32776, %rax # imm = 0x8008
cmpq $8193, %rcx # imm = 0x2001
jne .LBB3_15
# %bb.18:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $0, 96(%rsp)
movq 120(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 96(%rsp), %rdi
callq hipEventElapsedTime
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ghostRowsiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ghostColsiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3GOLiPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ghostRowsiPi,@object # @_Z9ghostRowsiPi
.section .rodata,"a",@progbits
.globl _Z9ghostRowsiPi
.p2align 3, 0x0
_Z9ghostRowsiPi:
.quad _Z24__device_stub__ghostRowsiPi
.size _Z9ghostRowsiPi, 8
.type _Z9ghostColsiPi,@object # @_Z9ghostColsiPi
.globl _Z9ghostColsiPi
.p2align 3, 0x0
_Z9ghostColsiPi:
.quad _Z24__device_stub__ghostColsiPi
.size _Z9ghostColsiPi, 8
.type _Z3GOLiPiS_,@object # @_Z3GOLiPiS_
.globl _Z3GOLiPiS_
.p2align 3, 0x0
_Z3GOLiPiS_:
.quad _Z18__device_stub__GOLiPiS_
.size _Z3GOLiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error %s\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Total Alive: %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ElapsedTime: %f ms\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9ghostRowsiPi"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9ghostColsiPi"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3GOLiPiS_"
.size .L__unnamed_3, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ghostRowsiPi
.addrsig_sym _Z24__device_stub__ghostColsiPi
.addrsig_sym _Z18__device_stub__GOLiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ghostRowsiPi
.addrsig_sym _Z9ghostColsiPi
.addrsig_sym _Z3GOLiPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
cudaMalloc(&nelements, N * sizeof(unsigned));
cudaMemcpy(nelements, hnelements, N * sizeof(unsigned), cudaMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
cudaDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z2k1Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe20003f05270 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0003 */
/*0080*/ @!P0 STS [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe80000000800 */
/*0090*/ @!P0 STS [0x8], RZ ; /* 0x000008ffff008388 */
/* 0x000fe80000000800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00d0*/ @!P0 I2F.U32.RP R7, c[0x0][0x0] ; /* 0x0000000000078b06 */
/* 0x000e220000209000 */
/*00e0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00f0*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e6c0000000000 */
/*0100*/ @!P0 MUFU.RCP R7, R7 ; /* 0x0000000700078308 */
/* 0x001e220000001000 */
/*0110*/ ISETP.EQ.U32.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x002fc4000bf22070 */
/*0120*/ @!P0 IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07048810 */
/* 0x001fca0007ffe0ff */
/*0130*/ @!P0 F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400058305 */
/* 0x000064000021f000 */
/*0140*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*0160*/ @!P0 IMAD R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b8a24 */
/* 0x000fc800078e02ff */
/*0170*/ @!P0 IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05058227 */
/* 0x000fe200078e0004 */
/*0180*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x004e26000000c000 */
/*0190*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */
/* 0x001fca000f8e00ff */
/*01a0*/ @P1 ATOMS.ADD RZ, [RZ], R8 ; /* 0x00000008ffff138c */
/* 0x000fe80000000000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f2e170 */
/*01d0*/ @!P0 LDS R6, [RZ] ; /* 0x00000000ff068984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605058227 */
/* 0x001fc800078e00ff */
/*01f0*/ @!P0 IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff078224 */
/* 0x000fc800078e0a05 */
/*0200*/ @!P0 IMAD R6, R7, c[0x0][0x0], R6 ; /* 0x0000000007068a24 */
/* 0x000fca00078e0206 */
/*0210*/ @!P0 ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006008a0c */
/* 0x000fc80003f46070 */
/*0220*/ @!P0 PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ; /* 0x000000000000881c */
/* 0x000fe4000172f070 */
/*0230*/ PLOP3.LUT P2, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f4e170 */
/*0240*/ @P1 IADD3 R6, R6, -c[0x0][0x0], RZ ; /* 0x8000000006061a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0260*/ @!P0 ISETP.GE.U32.AND P3, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006008a0c */
/* 0x000fc80003f66070 */
/*0270*/ @!P0 PLOP3.LUT P2, PT, P3, PT, PT, 0x80, 0x0 ; /* 0x000000000000881c */
/* 0x000fe40001f4f070 */
/*0280*/ ISETP.NE.U32.OR P3, PT, RZ, c[0x0][0x0], P0 ; /* 0x00000000ff007a0c */
/* 0x000fd60000765470 */
/*0290*/ @P2 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105052810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P3 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05ba12 */
/* 0x000fca00078e33ff */
/*02b0*/ @!P0 STS [0x4], R5 ; /* 0x00000405ff008388 */
/* 0x000fe80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ BSSY B0, 0x3a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*02f0*/ LDS R0, [0x4] ; /* 0x00000400ff007984 */
/* 0x000ea40000000800 */
/*0300*/ IMAD.IADD R0, R3, 0x1, -R0 ; /* 0x0000000103007824 */
/* 0x004fca00078e0a00 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x000fda0003f06070 */
/*0320*/ @!P0 BRA 0x390 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0330*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e22000000c000 */
/*0340*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0350*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0360*/ ISETP.EQ.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf02070 */
/*0370*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x001fd8000f8e00ff */
/*0380*/ @P0 ATOMS.ADD RZ, [0x8], R2 ; /* 0x00000802ffff038c */
/* 0x0001e40000000000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ LDS R0, [0x8] ; /* 0x00000800ff007984 */
/* 0x000e640000000800 */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x270f, PT ; /* 0x0000270f0000780c */
/* 0x002fda0003f04070 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*03e0*/ IADD3 R0, R0, 0x2710, RZ ; /* 0x0000271000007810 */
/* 0x000fca0007ffe0ff */
/*03f0*/ ATOMS.DEC RZ, [0x8], R0 ; /* 0x00000800ffff738c */
/* 0x000fe80002000000 */
/*0400*/ LDS R2, [0x8] ; /* 0x00000800ff027984 */
/* 0x001e240000000800 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R2, 0x2710, PT ; /* 0x000027100200780c */
/* 0x001fda0003f06070 */
/*0420*/ @!P0 BRA 0x3f0 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
cudaMalloc(&nelements, N * sizeof(unsigned));
cudaMemcpy(nelements, hnelements, N * sizeof(unsigned), cudaMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
cudaDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000c5686_00000000-6_donate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z2k1PjPj
.type _Z21__device_stub__Z2k1PjPj, @function
_Z21__device_stub__Z2k1PjPj:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2k1Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z21__device_stub__Z2k1PjPj, .-_Z21__device_stub__Z2k1PjPj
.globl _Z2k1Pj
.type _Z2k1Pj, @function
_Z2k1Pj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z2k1PjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2k1Pj, .-_Z2k1Pj
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2056, %rsp
.cfi_def_cfa_offset 2080
movq %fs:40, %rax
movq %rax, 2040(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 2032(%rsp), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movq %rsp, %rdi
movl $2000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 2040(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $2056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z21__device_stub__Z2k1PjPj
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k1Pj"
.LC1:
.string "delta"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k1Pj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5delta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL5delta, @object
.size _ZL5delta, 4
_ZL5delta:
.long 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
cudaMalloc(&nelements, N * sizeof(unsigned));
cudaMemcpy(nelements, hnelements, N * sizeof(unsigned), cudaMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
cudaDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
hipMalloc(&nelements, N * sizeof(unsigned));
hipMemcpy(nelements, hnelements, N * sizeof(unsigned), hipMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
hipDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
hipMalloc(&nelements, N * sizeof(unsigned));
hipMemcpy(nelements, hnelements, N * sizeof(unsigned), hipMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
hipDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k1Pj
.globl _Z2k1Pj
.p2align 8
.type _Z2k1Pj,@function
_Z2k1Pj:
s_load_b32 s2, s[0:1], 0x14
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
ds_store_2addr_b32 v0, v0, v0 offset1:2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, v1, s0
global_load_b32 v2, v[0:1], off
.LBB0_3:
s_ctz_i32_b32 s0, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s1, v2, s0
s_lshl_b32 s0, 1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s4, s4, s0
s_add_i32 s3, s3, s1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_3
v_mbcnt_lo_u32_b32 v2, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v2
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s3
ds_add_u32 v2, v3 offset:8
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
ds_load_b32 v4, v3 offset:8
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s1
s_mul_hi_u32 s3, s1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s4, v4
s_mul_hi_u32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s1, s2
s_sub_i32 s3, s4, s3
s_add_i32 s4, s1, 1
s_sub_i32 s5, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s1, s4, s1
s_cselect_b32 s3, s5, s3
s_add_i32 s4, s1, 1
s_cmp_ge_u32 s3, s2
s_cselect_b32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s1
ds_store_b32 v3, v2 offset:4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_mov_b32 s0, exec_lo
ds_load_b32 v1, v1 offset:4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e32 4, v0
s_cbranch_execz .LBB0_13
s_mov_b32 s3, exec_lo
s_mov_b32 s1, 0
.LBB0_10:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s1, s1, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_10
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s1
ds_add_u32 v0, v1
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v0, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, 0x270f, v1
s_cbranch_vccnz .LBB0_16
s_add_i32 s0, s2, 0x2710
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s0
.LBB0_15:
ds_dec_u32 v0, v1
ds_load_b32 v2, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, 0x2710, v2
s_cbranch_vccnz .LBB0_15
.LBB0_16:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k1Pj
.amdhsa_group_segment_fixed_size 12
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k1Pj, .Lfunc_end0-_Z2k1Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 12
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k1Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2k1Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define N 500
#define BLOCKSIZE 64
#define ELEPERTHREAD 20
__device__ const unsigned delta = ELEPERTHREAD / 5;
__global__ void k1(unsigned *nelements) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ unsigned sum;
__shared__ unsigned avg;
__shared__ unsigned donationbox[N], donationboxindex;
if (id == 0) {
sum = 0;
donationboxindex = 0;
}
__syncthreads();
// compute sum.
atomicAdd(&sum, nelements[id]);
__syncthreads();
// compute average.
if (id == 0) avg = sum / blockDim.x;
__syncthreads();
// check if I need to donate.
unsigned surplus = nelements[id] - avg;
if (surplus > delta) {
// donate.
unsigned index = atomicAdd(&donationboxindex, surplus);
for (unsigned ii = 0; ii < surplus; ++ii) {
donationbox[index + ii] = id; // some work.
}
}
// process.
// some processing here.
//__syncthreads(); // this is wrong.
// empty donation box.
while (donationboxindex < N * ELEPERTHREAD) {
unsigned index = atomicDec(&donationboxindex, N * ELEPERTHREAD + blockDim.x); // to ensure that wrap-around does not cause confusion.
if (index < N * ELEPERTHREAD) {
unsigned work = donationbox[index];
// process with work.
}
}
}
int main() {
unsigned hnelements[N];
for (unsigned ii = 0; ii < N; ++ii) {
hnelements[ii] = rand() % ELEPERTHREAD;
}
unsigned *nelements;
hipMalloc(&nelements, N * sizeof(unsigned));
hipMemcpy(nelements, hnelements, N * sizeof(unsigned), hipMemcpyHostToDevice);
unsigned nblocks = (N + BLOCKSIZE - 1) / BLOCKSIZE;
k1<<<nblocks, BLOCKSIZE>>>(nelements);
hipDeviceSynchronize();
//k2<<<1, 1>>>();
//cudaDeviceSynchronize();
return 0;
} | .text
.file "donate.hip"
.globl _Z17__device_stub__k1Pj # -- Begin function _Z17__device_stub__k1Pj
.p2align 4, 0x90
.type _Z17__device_stub__k1Pj,@function
_Z17__device_stub__k1Pj: # @_Z17__device_stub__k1Pj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z2k1Pj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z17__device_stub__k1Pj, .Lfunc_end0-_Z17__device_stub__k1Pj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2080, %rsp # imm = 0x820
.cfi_def_cfa_offset 2096
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 80(%rsp,%rbx,4)
incq %rbx
cmpq $500, %rbx # imm = 0x1F4
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2000, %edx # imm = 0x7D0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 56(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z2k1Pj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $2080, %rsp # imm = 0x820
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k1Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k1Pj,@object # @_Z2k1Pj
.section .rodata,"a",@progbits
.globl _Z2k1Pj
.p2align 3, 0x0
_Z2k1Pj:
.quad _Z17__device_stub__k1Pj
.size _Z2k1Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k1Pj"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k1Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k1Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2k1Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.NE.AND P0, PT, R2.reuse, RZ, PT ; /* 0x000000ff0200720c */
/* 0x040fe20003f05270 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0003 */
/*0080*/ @!P0 STS [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe80000000800 */
/*0090*/ @!P0 STS [0x8], RZ ; /* 0x000008ffff008388 */
/* 0x000fe80000000800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00d0*/ @!P0 I2F.U32.RP R7, c[0x0][0x0] ; /* 0x0000000000078b06 */
/* 0x000e220000209000 */
/*00e0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*00f0*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e6c0000000000 */
/*0100*/ @!P0 MUFU.RCP R7, R7 ; /* 0x0000000700078308 */
/* 0x001e220000001000 */
/*0110*/ ISETP.EQ.U32.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x002fc4000bf22070 */
/*0120*/ @!P0 IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07048810 */
/* 0x001fca0007ffe0ff */
/*0130*/ @!P0 F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400058305 */
/* 0x000064000021f000 */
/*0140*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a05 */
/*0160*/ @!P0 IMAD R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b8a24 */
/* 0x000fc800078e02ff */
/*0170*/ @!P0 IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05058227 */
/* 0x000fe200078e0004 */
/*0180*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x004e26000000c000 */
/*0190*/ IMAD.U32 R8, RZ, RZ, UR5 ; /* 0x00000005ff087e24 */
/* 0x001fca000f8e00ff */
/*01a0*/ @P1 ATOMS.ADD RZ, [RZ], R8 ; /* 0x00000008ffff138c */
/* 0x000fe80000000000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f2e170 */
/*01d0*/ @!P0 LDS R6, [RZ] ; /* 0x00000000ff068984 */
/* 0x000e240000000800 */
/*01e0*/ @!P0 IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605058227 */
/* 0x001fc800078e00ff */
/*01f0*/ @!P0 IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff078224 */
/* 0x000fc800078e0a05 */
/*0200*/ @!P0 IMAD R6, R7, c[0x0][0x0], R6 ; /* 0x0000000007068a24 */
/* 0x000fca00078e0206 */
/*0210*/ @!P0 ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006008a0c */
/* 0x000fc80003f46070 */
/*0220*/ @!P0 PLOP3.LUT P1, PT, P2, PT, PT, 0x80, 0x0 ; /* 0x000000000000881c */
/* 0x000fe4000172f070 */
/*0230*/ PLOP3.LUT P2, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f4e170 */
/*0240*/ @P1 IADD3 R6, R6, -c[0x0][0x0], RZ ; /* 0x8000000006061a10 */
/* 0x000fe40007ffe0ff */
/*0250*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0260*/ @!P0 ISETP.GE.U32.AND P3, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006008a0c */
/* 0x000fc80003f66070 */
/*0270*/ @!P0 PLOP3.LUT P2, PT, P3, PT, PT, 0x80, 0x0 ; /* 0x000000000000881c */
/* 0x000fe40001f4f070 */
/*0280*/ ISETP.NE.U32.OR P3, PT, RZ, c[0x0][0x0], P0 ; /* 0x00000000ff007a0c */
/* 0x000fd60000765470 */
/*0290*/ @P2 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105052810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ @!P3 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05ba12 */
/* 0x000fca00078e33ff */
/*02b0*/ @!P0 STS [0x4], R5 ; /* 0x00000405ff008388 */
/* 0x000fe80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ BSSY B0, 0x3a0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*02f0*/ LDS R0, [0x4] ; /* 0x00000400ff007984 */
/* 0x000ea40000000800 */
/*0300*/ IMAD.IADD R0, R3, 0x1, -R0 ; /* 0x0000000103007824 */
/* 0x004fca00078e0a00 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x000fda0003f06070 */
/*0320*/ @!P0 BRA 0x390 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0330*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e22000000c000 */
/*0340*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0350*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0360*/ ISETP.EQ.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf02070 */
/*0370*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x001fd8000f8e00ff */
/*0380*/ @P0 ATOMS.ADD RZ, [0x8], R2 ; /* 0x00000802ffff038c */
/* 0x0001e40000000000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ LDS R0, [0x8] ; /* 0x00000800ff007984 */
/* 0x000e640000000800 */
/*03b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x270f, PT ; /* 0x0000270f0000780c */
/* 0x002fda0003f04070 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fca00078e00ff */
/*03e0*/ IADD3 R0, R0, 0x2710, RZ ; /* 0x0000271000007810 */
/* 0x000fca0007ffe0ff */
/*03f0*/ ATOMS.DEC RZ, [0x8], R0 ; /* 0x00000800ffff738c */
/* 0x000fe80002000000 */
/*0400*/ LDS R2, [0x8] ; /* 0x00000800ff027984 */
/* 0x001e240000000800 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R2, 0x2710, PT ; /* 0x000027100200780c */
/* 0x001fda0003f06070 */
/*0420*/ @!P0 BRA 0x3f0 ; /* 0xffffffc000008947 */
/* 0x000fea000383ffff */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k1Pj
.globl _Z2k1Pj
.p2align 8
.type _Z2k1Pj,@function
_Z2k1Pj:
s_load_b32 s2, s[0:1], 0x14
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
ds_store_2addr_b32 v0, v0, v0 offset1:2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s0, v0
v_add_co_ci_u32_e64 v1, s0, s1, v1, s0
global_load_b32 v2, v[0:1], off
.LBB0_3:
s_ctz_i32_b32 s0, s4
s_waitcnt vmcnt(0)
v_readlane_b32 s1, v2, s0
s_lshl_b32 s0, 1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s4, s4, s0
s_add_i32 s3, s3, s1
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_3
v_mbcnt_lo_u32_b32 v2, exec_lo, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, 0, v2
s_and_saveexec_b32 s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s3
ds_add_u32 v2, v3 offset:8
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
ds_load_b32 v4, v3 offset:8
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s1
s_mul_hi_u32 s3, s1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s4, v4
s_mul_hi_u32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s1, s2
s_sub_i32 s3, s4, s3
s_add_i32 s4, s1, 1
s_sub_i32 s5, s3, s2
s_cmp_ge_u32 s3, s2
s_cselect_b32 s1, s4, s1
s_cselect_b32 s3, s5, s3
s_add_i32 s4, s1, 1
s_cmp_ge_u32 s3, s2
s_cselect_b32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s1
ds_store_b32 v3, v2 offset:4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_mov_b32 s0, exec_lo
ds_load_b32 v1, v1 offset:4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e32 4, v0
s_cbranch_execz .LBB0_13
s_mov_b32 s3, exec_lo
s_mov_b32 s1, 0
.LBB0_10:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s1, s1, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_10
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_13
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s1
ds_add_u32 v0, v1
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v0, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, 0x270f, v1
s_cbranch_vccnz .LBB0_16
s_add_i32 s0, s2, 0x2710
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s0
.LBB0_15:
ds_dec_u32 v0, v1
ds_load_b32 v2, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, 0x2710, v2
s_cbranch_vccnz .LBB0_15
.LBB0_16:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k1Pj
.amdhsa_group_segment_fixed_size 12
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k1Pj, .Lfunc_end0-_Z2k1Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 12
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k1Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2k1Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5686_00000000-6_donate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z2k1PjPj
.type _Z21__device_stub__Z2k1PjPj, @function
_Z21__device_stub__Z2k1PjPj:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2k1Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z21__device_stub__Z2k1PjPj, .-_Z21__device_stub__Z2k1PjPj
.globl _Z2k1Pj
.type _Z2k1Pj, @function
_Z2k1Pj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z2k1PjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2k1Pj, .-_Z2k1Pj
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2056, %rsp
.cfi_def_cfa_offset 2080
movq %fs:40, %rax
movq %rax, 2040(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbx
leaq 2032(%rsp), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
sall $2, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movq %rsp, %rdi
movl $2000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 2040(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $2056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z21__device_stub__Z2k1PjPj
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k1Pj"
.LC1:
.string "delta"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k1Pj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5delta(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 4
.type _ZL5delta, @object
.size _ZL5delta, 4
_ZL5delta:
.long 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "donate.hip"
.globl _Z17__device_stub__k1Pj # -- Begin function _Z17__device_stub__k1Pj
.p2align 4, 0x90
.type _Z17__device_stub__k1Pj,@function
_Z17__device_stub__k1Pj: # @_Z17__device_stub__k1Pj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z2k1Pj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z17__device_stub__k1Pj, .Lfunc_end0-_Z17__device_stub__k1Pj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2080, %rsp # imm = 0x820
.cfi_def_cfa_offset 2096
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
shll $2, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, 80(%rsp,%rbx,4)
incq %rbx
cmpq $500, %rbx # imm = 0x1F4
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2000, %esi # imm = 0x7D0
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2000, %edx # imm = 0x7D0
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 56(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z2k1Pj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $2080, %rsp # imm = 0x820
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k1Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k1Pj,@object # @_Z2k1Pj
.section .rodata,"a",@progbits
.globl _Z2k1Pj
.p2align 3, 0x0
_Z2k1Pj:
.quad _Z17__device_stub__k1Pj
.size _Z2k1Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k1Pj"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k1Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k1Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /////////////////////////
#include <stdio.h> /* Enables printing output to console */
#define N 64 /* Speficy array length value */
#define TPB 32 /* Threads per block used in kernel */
__device__
float scale(int i, int n){ return ((float)i)/(n-1); }
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float ref, int len){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const float x=scale(i,len);
d_out[i]=distance(x,ref);
printf("i = %2d: dist from %f to %f is %f.\n",i,ref,x,d_out[i]);
}
int main(){
const float ref=0.5f;
//Declare a pointer for an array of floats
float *d_out=0;
//Allocate device memory to store the output array
cudaMalloc(&d_out, N*sizeof(float));
//Launch kernel to compute and store distance values
distanceKernel<<<N/TPB,TPB>>>(d_out,ref,N);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fce0007ffe0ff */
/*0070*/ I2F R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e620008201400 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fce00078e0203 */
/*0090*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e300000001000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00b0*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*00c0*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc60000000005 */
/*00d0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*00e0*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0100*/ FFMA R5, R2, R6, R5 ; /* 0x0000000602057223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x570 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ FADD R2, -R5, c[0x0][0x168] ; /* 0x00005a0005027621 */
/* 0x000fe20000000100 */
/*0160*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ BSSY B0, 0x2a0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0190*/ FMUL R3, R2, R2 ; /* 0x0000000202037220 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*01b0*/ MUFU.RSQ R4, R3 ; /* 0x0000000300047308 */
/* 0x0000620000001400 */
/*01c0*/ IADD3 R2, R3, -0xd000000, RZ ; /* 0xf300000003027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 BRA 0x250 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B1, 0x230 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0200*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x400 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0240*/ BRA 0x290 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0250*/ FMUL.FTZ R2, R3, R4 ; /* 0x0000000403027220 */
/* 0x003fe40000410000 */
/*0260*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*0270*/ FFMA R3, -R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000103 */
/*0280*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe40000000002 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ F2F.F64.F32 R8, R5 ; /* 0x0000000500087310 */
/* 0x0001e20000201800 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*02d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fe200078e020d */
/*0300*/ LDC.64 R16, c[0x4][R3] ; /* 0x0100000003107b82 */
/* 0x0002a20000000a00 */
/*0310*/ F2F.F64.F32 R10, R2 ; /* 0x00000002000a7310 */
/* 0x000ee40000201800 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x001fe200078e00ff */
/*0330*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0003ea000c101904 */
/*0340*/ F2F.F64.F32 R14, c[0x0][0x168] ; /* 0x00005a00000e7b10 */
/* 0x000e220000201800 */
/*0350*/ STL.128 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0083e80000100c00 */
/*0360*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0013e40000100a00 */
/*0370*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0380*/ MOV R9, 0x3f0 ; /* 0x000003f000097802 */
/* 0x000fc40000000f00 */
/*0390*/ MOV R20, 0x370 ; /* 0x0000037000147802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03c0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*03d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*03e0*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x000fea0003c00000 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BRA 0x530 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f1e000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0003 */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff038424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x530 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04a0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04b0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04c0*/ @P0 FMUL.FTZ R9, R4, R3 ; /* 0x0000000304090220 */
/* 0x001fe40000410000 */
/*04d0*/ @P0 FMUL.FTZ R10, R3, 0.5 ; /* 0x3f000000030a0820 */
/* 0x000fe40000410000 */
/*04e0*/ @P0 FADD.FTZ R8, -R9.reuse, -RZ ; /* 0x800000ff09080221 */
/* 0x040fe40000010100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0500*/ @P0 FFMA R8, R9, R8, R4 ; /* 0x0000000809080223 */
/* 0x000fc80000000004 */
/*0510*/ @P0 FFMA R8, R8, R10, R9 ; /* 0x0000000a08080223 */
/* 0x000fc80000000009 */
/*0520*/ @P0 FMUL.FTZ R3, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008030820 */
/* 0x000fc80000410000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa9002007950 */
/* 0x000fea0003c3ffff */
/*0570*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0580*/ BSSY B1, 0xbd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0590*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*05b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*05d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*07f0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0800*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0810*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0820*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0830*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0840*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0850*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0880*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0890*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*08b0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*08c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0990*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*09a0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*09b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*09c0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*09e0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0a00*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0a80*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0aa0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0ac0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0b50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0be0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff40002007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /////////////////////////
#include <stdio.h> /* Enables printing output to console */
#define N 64 /* Speficy array length value */
#define TPB 32 /* Threads per block used in kernel */
__device__
float scale(int i, int n){ return ((float)i)/(n-1); }
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float ref, int len){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const float x=scale(i,len);
d_out[i]=distance(x,ref);
printf("i = %2d: dist from %f to %f is %f.\n",i,ref,x,d_out[i]);
}
int main(){
const float ref=0.5f;
//Declare a pointer for an array of floats
float *d_out=0;
//Allocate device memory to store the output array
cudaMalloc(&d_out, N*sizeof(float));
//Launch kernel to compute and store distance values
distanceKernel<<<N/TPB,TPB>>>(d_out,ref,N);
cudaFree(d_out);
return 0;
} | .file "tmpxft_00104e77_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /////////////////////////
#include <stdio.h> /* Enables printing output to console */
#define N 64 /* Speficy array length value */
#define TPB 32 /* Threads per block used in kernel */
__device__
float scale(int i, int n){ return ((float)i)/(n-1); }
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float ref, int len){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const float x=scale(i,len);
d_out[i]=distance(x,ref);
printf("i = %2d: dist from %f to %f is %f.\n",i,ref,x,d_out[i]);
}
int main(){
const float ref=0.5f;
//Declare a pointer for an array of floats
float *d_out=0;
//Allocate device memory to store the output array
cudaMalloc(&d_out, N*sizeof(float));
//Launch kernel to compute and store distance values
distanceKernel<<<N/TPB,TPB>>>(d_out,ref,N);
cudaFree(d_out);
return 0;
} | /////////////////////////
#include <hip/hip_runtime.h>
#include <stdio.h> /* Enables printing output to console */
#define N 64 /* Speficy array length value */
#define TPB 32 /* Threads per block used in kernel */
__device__
float scale(int i, int n){ return ((float)i)/(n-1); }
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float ref, int len){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const float x=scale(i,len);
d_out[i]=distance(x,ref);
printf("i = %2d: dist from %f to %f is %f.\n",i,ref,x,d_out[i]);
}
int main(){
const float ref=0.5f;
//Declare a pointer for an array of floats
float *d_out=0;
//Allocate device memory to store the output array
hipMalloc(&d_out, N*sizeof(float));
//Launch kernel to compute and store distance values
distanceKernel<<<N/TPB,TPB>>>(d_out,ref,N);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /////////////////////////
#include <hip/hip_runtime.h>
#include <stdio.h> /* Enables printing output to console */
#define N 64 /* Speficy array length value */
#define TPB 32 /* Threads per block used in kernel */
__device__
float scale(int i, int n){ return ((float)i)/(n-1); }
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float ref, int len){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
const float x=scale(i,len);
d_out[i]=distance(x,ref);
printf("i = %2d: dist from %f to %f is %f.\n",i,ref,x,d_out[i]);
}
int main(){
const float ref=0.5f;
//Declare a pointer for an array of floats
float *d_out=0;
//Allocate device memory to store the output array
hipMalloc(&d_out, N*sizeof(float));
//Launch kernel to compute and store distance values
distanceKernel<<<N/TPB,TPB>>>(d_out,ref,N);
hipFree(d_out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00104e77_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(cudaMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(cudaMemcpy(v_device, v, sizeV, cudaMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(cudaMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(cudaMemcpy(h, h_device, sizeH, cudaMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(cudaFree(v_device));
CUDA_CHECK_RETURN(cudaFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
cudaEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} | code for sm_80
Function : _Z19calcular_histogramaPjS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00b0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05070 */
/*00c0*/ @!P0 BRA 0x120 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R2, 0xf0 ; /* 0x000000f000027802 */
/* 0x001fe40000000f00 */
/*00e0*/ CALL.REL.NOINC 0x2a0 ; /* 0x000001b000007944 */
/* 0x020fea0003c00000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0110*/ BRA 0x250 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x001e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0190*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fca00078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x020fc800078e00ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe400078e0200 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R0, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000000a10 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @P0 IADD3 R0, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000000a10 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff009a12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*0250*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0260*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fe400000f1403 */
/*0270*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*0280*/ RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400798e */
/* 0x000fe2000c10e184 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ I2F.U64.RP R3, c[0x0][0x178] ; /* 0x00005e0000037b12 */
/* 0x000e300000309000 */
/*02b0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*02c0*/ IADD3 R4, R3, 0x1ffffffe, RZ ; /* 0x1ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*02d0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*02e0*/ IMAD.WIDE.U32 R6, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a25 */
/* 0x001fc800078e00ff */
/*02f0*/ IMAD R7, R4, c[0x0][0x17c], R7 ; /* 0x00005f0004077a24 */
/* 0x000fe200078e0207 */
/*0300*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fc60007f1e0ff */
/*0310*/ IMAD R7, R5, c[0x0][0x178], R7 ; /* 0x00005e0005077a24 */
/* 0x000fe400078e0207 */
/*0320*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0330*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0350*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0360*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0370*/ IMAD.HI.U32 R3, R5, R11, RZ ; /* 0x0000000b05037227 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fc80007820006 */
/*0390*/ IMAD.X R3, R3, 0x1, R5, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0605 */
/*03a0*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fc80007f5e0ff */
/*03b0*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*03c0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], RZ ; /* 0x00005e0007047a25 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD R6, R7, c[0x0][0x17c], R5 ; /* 0x00005f0007067a24 */
/* 0x000fe200078e0205 */
/*03e0*/ IADD3 R5, P0, RZ, -R4, RZ ; /* 0x80000004ff057210 */
/* 0x000fc60007f1e0ff */
/*03f0*/ IMAD R4, R3, c[0x0][0x178], R6 ; /* 0x00005e0003047a24 */
/* 0x000fe400078e0206 */
/*0400*/ IMAD.HI.U32 R6, R7, R5, RZ ; /* 0x0000000507067227 */
/* 0x000fc600078e00ff */
/*0410*/ IADD3.X R4, RZ, ~R4, RZ, P0, !PT ; /* 0x80000004ff047210 */
/* 0x000fca00007fe4ff */
/*0420*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0430*/ IMAD R8, R3.reuse, R4, RZ ; /* 0x0000000403087224 */
/* 0x040fe400078e02ff */
/*0440*/ IMAD.HI.U32 R7, P1, R3, R5, R6 ; /* 0x0000000503077227 */
/* 0x000fc80007820006 */
/*0450*/ IMAD.HI.U32 R6, R3, R4, RZ ; /* 0x0000000403067227 */
/* 0x000fe200078e00ff */
/*0460*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0470*/ IMAD.X R3, R6, 0x1, R3, P0 ; /* 0x0000000106037824 */
/* 0x000fe400000e0603 */
/*0480*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0490*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE.U32 R4, RZ, R7, R4 ; /* 0x00000007ff047225 */
/* 0x000fcc00078e0004 */
/*04c0*/ IMAD.HI.U32 R3, P0, R3, R0, R4 ; /* 0x0000000003037227 */
/* 0x000fca0007800004 */
/*04d0*/ IADD3 R7, P1, RZ, R3, RZ ; /* 0x00000003ff077210 */
/* 0x000fe20007f3e0ff */
/*04e0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*04f0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], RZ ; /* 0x00005e0007047a25 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0510*/ IMAD R6, R7, c[0x0][0x17c], R5 ; /* 0x00005f0007067a24 */
/* 0x000fe200078e0205 */
/*0520*/ IADD3 R0, P1, -R4, R0, RZ ; /* 0x0000000004007210 */
/* 0x000fc60007f3e1ff */
/*0530*/ IMAD R3, R3, c[0x0][0x178], R6 ; /* 0x00005e0003037a24 */
/* 0x000fe200078e0206 */
/*0540*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc60003f06070 */
/*0550*/ IMAD.X R5, RZ, RZ, ~R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0e03 */
/*0560*/ IADD3 R3, P1, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000037a10 */
/* 0x000fc80007f3e0ff */
/*0570*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0005007a0c */
/* 0x040fe40003f06100 */
/*0580*/ IADD3.X R4, R5, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0005047a10 */
/* 0x000fe40000ffe4ff */
/*0590*/ SEL R3, R3, R0, P0 ; /* 0x0000000003037207 */
/* 0x000fe40000000000 */
/*05a0*/ SEL R4, R4, R5, P0 ; /* 0x0000000504047207 */
/* 0x000fe40000000000 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x040fe40003f06070 */
/*05c0*/ IADD3 R0, P2, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003007a10 */
/* 0x000fc40007f5e0ff */
/*05d0*/ ISETP.GE.U32.AND.EX P0, PT, R4.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0004007a0c */
/* 0x040fe40003f06100 */
/*05e0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25070 */
/*05f0*/ IADD3.X R5, R4, ~c[0x0][0x17c], RZ, P2, !PT ; /* 0x80005f0004057a10 */
/* 0x000fe400017fe4ff */
/*0600*/ SEL R0, R0, R3, P0 ; /* 0x0000000300007207 */
/* 0x000fe20000000000 */
/*0610*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0620*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25310 */
/*0630*/ SEL R5, R5, R4, P0 ; /* 0x0000000405057207 */
/* 0x000fc40000000000 */
/*0640*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe40000800000 */
/*0650*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0660*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff99002007950 */
/* 0x000fec0003c3ffff */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z22inicializar_histogramaPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(cudaMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(cudaMemcpy(v_device, v, sizeV, cudaMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(cudaMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(cudaMemcpy(h, h_device, sizeH, cudaMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(cudaFree(v_device));
CUDA_CHECK_RETURN(cudaFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
cudaEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} | .file "tmpxft_0013d202_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB6905:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE6905:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6910:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6910:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z22inicializar_histogramaPjmPjm
.type _Z43__device_stub__Z22inicializar_histogramaPjmPjm, @function
_Z43__device_stub__Z22inicializar_histogramaPjmPjm:
.LFB6932:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22inicializar_histogramaPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6932:
.size _Z43__device_stub__Z22inicializar_histogramaPjmPjm, .-_Z43__device_stub__Z22inicializar_histogramaPjmPjm
.globl _Z22inicializar_histogramaPjm
.type _Z22inicializar_histogramaPjm, @function
_Z22inicializar_histogramaPjm:
.LFB6933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z22inicializar_histogramaPjmPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6933:
.size _Z22inicializar_histogramaPjm, .-_Z22inicializar_histogramaPjm
.globl _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
.type _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm, @function
_Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm:
.LFB6934:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19calcular_histogramaPjS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6934:
.size _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm, .-_Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.type _Z19calcular_histogramaPjS_mm, @function
_Z19calcular_histogramaPjS_mm:
.LFB6935:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6935:
.size _Z19calcular_histogramaPjS_mm, .-_Z19calcular_histogramaPjS_mm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "inicializar_histograma<<<%lu, %lu>>> falla.\n"
.align 8
.LC6:
.string "calcular_histograma<<<%lu, %lu>>> falla.\n"
.align 8
.LC7:
.string "Cuidado! No se selecciona ning\303\272n kernel\n"
.text
.globl _Z13tiempo_kernelPjS_j
.type _Z13tiempo_kernelPjS_j, @function
_Z13tiempo_kernelPjS_j:
.LFB6907:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, 8(%rsp)
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %ebx
movq $0x000000000, (%rsp)
leaq .LC7(%rip), %r13
leaq .LC6(%rip), %r15
leaq 44(%rsp), %r12
jmp .L34
.L44:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L28:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L40
.L29:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $98, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L30:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L42
.L31:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaEventElapsedTime@PLT
cmpl $5, %ebx
jle .L32
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addl $1, %ebx
cmpl $106, %ebx
je .L43
.L34:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $1, %ebp
je .L44
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L39:
movl $8, %esi
movq %r14, %rdi
call _Z43__device_stub__Z22inicializar_histogramaPjmPjm
jmp .L28
.L40:
movl $1024, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L41:
movl $8, %ecx
movl $100000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
jmp .L30
.L42:
movl $1024, %ecx
movl $98, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L43:
divsd .LC8(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
addl $1, %ebx
jmp .L34
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6907:
.size _Z13tiempo_kernelPjS_j, .-_Z13tiempo_kernelPjS_j
.section .rodata.str1.1
.LC9:
.string "cudaMalloc(&v_device, sizeV)"
.section .rodata.str1.8
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mbdaso/cuda/master/histograma-primera-implementacion/main.cu"
.align 8
.LC11:
.string "cudaMemcpy(v_device, v, sizeV, cudaMemcpyHostToDevice)"
.section .rodata.str1.1
.LC12:
.string "cudaMalloc(&h_device, sizeH)"
.section .rodata.str1.8
.align 8
.LC13:
.string "Llamando kernel con M = %i N = %i y P = %i\n"
.align 8
.LC14:
.string "cudaMemcpy(h, h_device, sizeH, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC15:
.string "Tiempo transcurrido: %f ms\n"
.LC16:
.string "Histograma: "
.LC17:
.string "%u "
.LC18:
.string "\n"
.LC19:
.string "Elementos del vector: %i\n"
.LC20:
.string "Suma de elementos : %lu\n"
.LC21:
.string "cudaFree(v_device)"
.LC22:
.string "cudaFree(h_device)"
.text
.globl main
.type main, @function
main:
.LFB6906:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 400000(%rax), %rbp
.L47:
call rand@PLT
cltd
shrl $29, %edx
addl %edx, %eax
andl $7, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $57, %esi
leaq .LC10(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $58, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $32, %edi
call malloc@PLT
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $64, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %r8d
movl $100000, %ecx
movl $8, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z13tiempo_kernelPjS_j
movss %xmm0, 12(%rsp)
movl $2, %ecx
movl $32, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC14(%rip), %rdx
movl $70, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbx
leaq 32(%r15), %r14
movl $0, %ebp
leaq .LC17(%rip), %r13
.L48:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %eax
addq %rax, %rbp
addq $4, %rbx
cmpq %r14, %rbx
jne .L48
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100000, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC21(%rip), %rdx
movl $85, %esi
leaq .LC10(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC22(%rip), %rdx
movl $86, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6906:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z19calcular_histogramaPjS_mm"
.LC24:
.string "_Z22inicializar_histogramaPjm"
.section .rodata.str1.8
.align 8
.LC25:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std3__419piecewise_constructE"
.align 8
.LC26:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC27:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6937:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcular_histogramaPjS_mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z22inicializar_histogramaPjm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6937:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(cudaMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(cudaMemcpy(v_device, v, sizeV, cudaMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(cudaMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(cudaMemcpy(h, h_device, sizeH, cudaMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(cudaFree(v_device));
CUDA_CHECK_RETURN(cudaFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
cudaEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(cudaPeekAtLastError() != cudaSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(hipMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(hipMemcpy(v_device, v, sizeV, hipMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(hipMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(hipMemcpy(h, h_device, sizeH, hipMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(hipFree(v_device));
CUDA_CHECK_RETURN(hipFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
hipEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(hipPeekAtLastError() != hipSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(hipPeekAtLastError() != hipSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(hipMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(hipMemcpy(v_device, v, sizeV, hipMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(hipMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(hipMemcpy(h, h_device, sizeH, hipMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(hipFree(v_device));
CUDA_CHECK_RETURN(hipFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
hipEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(hipPeekAtLastError() != hipSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(hipPeekAtLastError() != hipSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22inicializar_histogramaPjm
.globl _Z22inicializar_histogramaPjm
.p2align 8
.type _Z22inicializar_histogramaPjm,@function
_Z22inicializar_histogramaPjm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22inicializar_histogramaPjm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22inicializar_histogramaPjm, .Lfunc_end0-_Z22inicializar_histogramaPjm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19calcular_histogramaPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.p2align 8
.type _Z19calcular_histogramaPjS_mm,@function
_Z19calcular_histogramaPjS_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v1, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_3
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 0
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v1, v0, v1, vcc_lo
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcular_histogramaPjS_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19calcular_histogramaPjS_mm, .Lfunc_end1-_Z19calcular_histogramaPjS_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22inicializar_histogramaPjm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22inicializar_histogramaPjm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcular_histogramaPjS_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcular_histogramaPjS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <numeric>
#include <stdlib.h>
#include <stdio.h>
#include <limits.h>
#include <hip/hip_runtime.h>
#include <hip/hip_cooperative_groups.h>
/* INT_MAX < LONG_MAX < ULONG_MAX < LLONG_MAX < ULLONG_MAX*/
typedef unsigned vector_t;
typedef unsigned int histogram_t;
typedef int atomic_t;
#define MIL 1000
#define MILLON MIL*MIL
#define N 100*MIL
#define M 8 //Tamaño histograma
#define SIZE_BYTES sizeof(vector_t);
#define R 106 //Repeticiones
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
}
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
__global__ void inicializar_histograma(histogram_t * h, size_t n){
size_t thread_id = threadIdx.x + blockDim.x * blockIdx.x;
if(thread_id >= n) return;
h[thread_id] = 0;
}
__global__ void calcular_histograma(vector_t* v, histogram_t* h,
size_t n, size_t m){
size_t id = threadIdx.x + blockDim.x * blockIdx.x;
if(id >= n) return;
atomicAdd(&h[v[id]%m], 1);
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel);
int main(void){
srand(time(NULL));
size_t sizeV = N * sizeof(vector_t);
vector_t * v = (vector_t *)malloc(sizeV);
for (size_t i = 0; i < N; i++)
v[i] = rand()%M;
vector_t * v_device;
CUDA_CHECK_RETURN(hipMalloc(&v_device, sizeV));
CUDA_CHECK_RETURN(hipMemcpy(v_device, v, sizeV, hipMemcpyHostToDevice));
size_t sizeH = M * sizeof(histogram_t);
histogram_t * h = (histogram_t *)malloc(sizeH);
histogram_t * h_device;
CUDA_CHECK_RETURN(hipMalloc(&h_device, sizeH));
printf("Llamando kernel con M = %i N = %i y P = %i\n", M, N, 1);
float totalTime = tiempo_kernel(h_device, v_device, 1);
CUDA_CHECK_RETURN(hipMemcpy(h, h_device, sizeH, hipMemcpyDeviceToHost));
printf("Tiempo transcurrido: %f ms\n", totalTime);
printf("Histograma: ");
size_t suma = 0;
for (int i = 0; i < M; i++){
printf("%u ", h[i]);
suma += h[i];
}
printf("\n");
printf("Elementos del vector: %i\n", N);
printf("Suma de elementos : %lu\n", suma);
free(v);
free(h);
CUDA_CHECK_RETURN(hipFree(v_device));
CUDA_CHECK_RETURN(hipFree(h_device));
}
float tiempo_kernel(histogram_t * h_device, vector_t * v_device, unsigned kernel){
size_t threadsPerBlock = 1024;
size_t blocksPerGridM = ((unsigned)M + threadsPerBlock - 1) / threadsPerBlock;
size_t blocksPerGridN = ((unsigned)N + threadsPerBlock - 1) / threadsPerBlock;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
double totalTime = 0;
for(int i = 0; i < R; i++){
hipEventRecord(start, 0);
switch(kernel){
case 1:
inicializar_histograma<<<blocksPerGridM, threadsPerBlock>>>(h_device, M);
if(hipPeekAtLastError() != hipSuccess) printf("inicializar_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridM, threadsPerBlock);
calcular_histograma <<<blocksPerGridN, threadsPerBlock>>>(v_device, h_device, N, M);
if(hipPeekAtLastError() != hipSuccess) printf("calcular_histograma<<<%lu, %lu>>> falla.\n", blocksPerGridN, threadsPerBlock);
break;
default:
printf("Cuidado! No se selecciona ningún kernel\n");
break;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
if(i > 5) totalTime += (double)elapsedTime;
}
return totalTime / (R-6);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__inicializar_histogramaPjm # -- Begin function _Z37__device_stub__inicializar_histogramaPjm
.p2align 4, 0x90
.type _Z37__device_stub__inicializar_histogramaPjm,@function
_Z37__device_stub__inicializar_histogramaPjm: # @_Z37__device_stub__inicializar_histogramaPjm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22inicializar_histogramaPjm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z37__device_stub__inicializar_histogramaPjm, .Lfunc_end0-_Z37__device_stub__inicializar_histogramaPjm
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcular_histogramaPjS_mm # -- Begin function _Z34__device_stub__calcular_histogramaPjS_mm
.p2align 4, 0x90
.type _Z34__device_stub__calcular_histogramaPjS_mm,@function
_Z34__device_stub__calcular_histogramaPjS_mm: # @_Z34__device_stub__calcular_histogramaPjS_mm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19calcular_histogramaPjS_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__calcular_histogramaPjS_mm, .Lfunc_end1-_Z34__device_stub__calcular_histogramaPjS_mm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-8, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movl $.L.str.1, %esi
movl $57, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.2, %esi
movl $58, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $32, %edi
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movl $.L.str.3, %esi
movl $64, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $.L.str.4, %edi
movl $8, %esi
movl $100000, %edx # imm = 0x186A0
movl $1, %ecx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $1, %edx
callq _Z13tiempo_kernelPjS_j
movss %xmm0, 20(%rsp) # 4-byte Spill
movq (%rsp), %rsi
movl $32, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl $70, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl (%r14,%r12,4), %eax
addq %rax, %r15
incq %r12
cmpq $8, %r12
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movl $.L.str.10, %edi
movl $100000, %esi # imm = 0x186A0
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.12, %esi
movl $85, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq (%rsp), %rdi
callq hipFree
movl $.L.str.13, %esi
movl $86, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.17, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.18, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.19, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.20, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end3-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13tiempo_kernelPjS_j
.LCPI4_0:
.quad 0x8000000000000000 # double -0
.LCPI4_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z13tiempo_kernelPjS_j
.p2align 4, 0x90
.type _Z13tiempo_kernelPjS_j,@function
_Z13tiempo_kernelPjS_j: # @_Z13tiempo_kernelPjS_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, 136(%rsp) # 8-byte Spill
movq %rdi, 80(%rsp) # 8-byte Spill
movabsq $4294968320, %r12 # imm = 0x100000400
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorpd %xmm0, %xmm0
leaq -1023(%r12), %r13
leaq 96(%rsp), %rbp
leaq -926(%r12), %r14
xorl %r15d, %r15d
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_1 Depth=1
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB4_14: # in Loop: Header=BB4_1 Depth=1
movsd 144(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movapd %xmm1, %xmm0
incl %r15d
cmpl $106, %r15d
je .LBB4_15
.LBB4_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $1, %ebx
jne .LBB4_10
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_1 Depth=1
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq $8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z22inicializar_histogramaPjm, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4: # in Loop: Header=BB4_1 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
je .LBB4_6
# %bb.5: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.14, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
.LBB4_6: # in Loop: Header=BB4_1 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_1 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq $100000, 56(%rsp) # imm = 0x186A0
movq $8, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z19calcular_histogramaPjS_mm, %edi
movq %rbp, %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8: # in Loop: Header=BB4_1 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
je .LBB4_11
# %bb.9: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.15, %edi
movl $98, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_1 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB4_11: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbp, %rdi
callq hipEventElapsedTime
cmpl $6, %r15d
jb .LBB4_13
# %bb.12: # in Loop: Header=BB4_1 Depth=1
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
jmp .LBB4_14
.LBB4_15:
divsd .LCPI4_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z13tiempo_kernelPjS_j, .Lfunc_end4-_Z13tiempo_kernelPjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22inicializar_histogramaPjm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcular_histogramaPjS_mm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22inicializar_histogramaPjm,@object # @_Z22inicializar_histogramaPjm
.section .rodata,"a",@progbits
.globl _Z22inicializar_histogramaPjm
.p2align 3, 0x0
_Z22inicializar_histogramaPjm:
.quad _Z37__device_stub__inicializar_histogramaPjm
.size _Z22inicializar_histogramaPjm, 8
.type _Z19calcular_histogramaPjS_mm,@object # @_Z19calcular_histogramaPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.p2align 3, 0x0
_Z19calcular_histogramaPjS_mm:
.quad _Z34__device_stub__calcular_histogramaPjS_mm
.size _Z19calcular_histogramaPjS_mm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mbdaso/cuda/master/histograma-primera-implementacion/main.hip"
.size .L.str, 119
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc(&v_device, sizeV)"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy(v_device, v, sizeV, hipMemcpyHostToDevice)"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc(&h_device, sizeH)"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Llamando kernel con M = %i N = %i y P = %i\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(h, h_device, sizeH, hipMemcpyDeviceToHost)"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo transcurrido: %f ms\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Histograma: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%u "
.size .L.str.8, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Elementos del vector: %i\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Suma de elementos : %lu\n"
.size .L.str.11, 25
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipFree(v_device)"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipFree(h_device)"
.size .L.str.13, 18
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "inicializar_histograma<<<%lu, %lu>>> falla.\n"
.size .L.str.14, 45
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "calcular_histograma<<<%lu, %lu>>> falla.\n"
.size .L.str.15, 42
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " returned "
.size .L.str.17, 11
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "("
.size .L.str.18, 2
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz ") at "
.size .L.str.19, 6
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz ":"
.size .L.str.20, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22inicializar_histogramaPjm"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcular_histogramaPjS_mm"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Cuidado! No se selecciona ning\303\272n kernel"
.size .Lstr, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__inicializar_histogramaPjm
.addrsig_sym _Z34__device_stub__calcular_histogramaPjS_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22inicializar_histogramaPjm
.addrsig_sym _Z19calcular_histogramaPjS_mm
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19calcular_histogramaPjS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000162000c1e1900 */
/*00b0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05070 */
/*00c0*/ @!P0 BRA 0x120 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00d0*/ MOV R2, 0xf0 ; /* 0x000000f000027802 */
/* 0x001fe40000000f00 */
/*00e0*/ CALL.REL.NOINC 0x2a0 ; /* 0x000001b000007944 */
/* 0x020fea0003c00000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0110*/ BRA 0x250 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0120*/ I2F.U32.RP R4, c[0x0][0x178] ; /* 0x00005e0000047b06 */
/* 0x001e220000209000 */
/*0130*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fce0003f25070 */
/*0140*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0150*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0160*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0170*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0180*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0190*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fca00078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x020fc800078e00ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe400078e0200 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R0, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000000a10 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0220*/ @P0 IADD3 R0, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000000a10 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff009a12 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0000 */
/*0250*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0260*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fe400000f1403 */
/*0270*/ MOV R3, 0x1 ; /* 0x0000000100037802 */
/* 0x000fca0000000f00 */
/*0280*/ RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400798e */
/* 0x000fe2000c10e184 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ I2F.U64.RP R3, c[0x0][0x178] ; /* 0x00005e0000037b12 */
/* 0x000e300000309000 */
/*02b0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*02c0*/ IADD3 R4, R3, 0x1ffffffe, RZ ; /* 0x1ffffffe03047810 */
/* 0x001fcc0007ffe0ff */
/*02d0*/ F2I.U64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x000e24000020d800 */
/*02e0*/ IMAD.WIDE.U32 R6, R4, c[0x0][0x178], RZ ; /* 0x00005e0004067a25 */
/* 0x001fc800078e00ff */
/*02f0*/ IMAD R7, R4, c[0x0][0x17c], R7 ; /* 0x00005f0004077a24 */
/* 0x000fe200078e0207 */
/*0300*/ IADD3 R9, P0, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fc60007f1e0ff */
/*0310*/ IMAD R7, R5, c[0x0][0x178], R7 ; /* 0x00005e0005077a24 */
/* 0x000fe400078e0207 */
/*0320*/ IMAD.HI.U32 R6, R4, R9, RZ ; /* 0x0000000904067227 */
/* 0x000fc800078e00ff */
/*0330*/ IMAD.X R11, RZ, RZ, ~R7, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fe400000e0e07 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0004 */
/*0350*/ IMAD R13, R5, R11.reuse, RZ ; /* 0x0000000b050d7224 */
/* 0x080fe400078e02ff */
/*0360*/ IMAD.WIDE.U32 R6, P0, R4, R11, R6 ; /* 0x0000000b04067225 */
/* 0x000fc80007800006 */
/*0370*/ IMAD.HI.U32 R3, R5, R11, RZ ; /* 0x0000000b05037227 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.HI.U32 R6, P1, R5, R9, R6 ; /* 0x0000000905067227 */
/* 0x000fc80007820006 */
/*0390*/ IMAD.X R3, R3, 0x1, R5, P0 ; /* 0x0000000103037824 */
/* 0x000fe200000e0605 */
/*03a0*/ IADD3 R7, P2, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x000fc80007f5e0ff */
/*03b0*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*03c0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], RZ ; /* 0x00005e0007047a25 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD R6, R7, c[0x0][0x17c], R5 ; /* 0x00005f0007067a24 */
/* 0x000fe200078e0205 */
/*03e0*/ IADD3 R5, P0, RZ, -R4, RZ ; /* 0x80000004ff057210 */
/* 0x000fc60007f1e0ff */
/*03f0*/ IMAD R4, R3, c[0x0][0x178], R6 ; /* 0x00005e0003047a24 */
/* 0x000fe400078e0206 */
/*0400*/ IMAD.HI.U32 R6, R7, R5, RZ ; /* 0x0000000507067227 */
/* 0x000fc600078e00ff */
/*0410*/ IADD3.X R4, RZ, ~R4, RZ, P0, !PT ; /* 0x80000004ff047210 */
/* 0x000fca00007fe4ff */
/*0420*/ IMAD.WIDE.U32 R6, P0, R7, R4, R6 ; /* 0x0000000407067225 */
/* 0x000fc80007800006 */
/*0430*/ IMAD R8, R3.reuse, R4, RZ ; /* 0x0000000403087224 */
/* 0x040fe400078e02ff */
/*0440*/ IMAD.HI.U32 R7, P1, R3, R5, R6 ; /* 0x0000000503077227 */
/* 0x000fc80007820006 */
/*0450*/ IMAD.HI.U32 R6, R3, R4, RZ ; /* 0x0000000403067227 */
/* 0x000fe200078e00ff */
/*0460*/ IADD3 R7, P2, R8, R7, RZ ; /* 0x0000000708077210 */
/* 0x000fc60007f5e0ff */
/*0470*/ IMAD.X R3, R6, 0x1, R3, P0 ; /* 0x0000000106037824 */
/* 0x000fe400000e0603 */
/*0480*/ IMAD.HI.U32 R4, R7, R0, RZ ; /* 0x0000000007047227 */
/* 0x000fc600078e00ff */
/*0490*/ IADD3.X R3, RZ, RZ, R3, P2, P1 ; /* 0x000000ffff037210 */
/* 0x000fe200017e2403 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE.U32 R4, RZ, R7, R4 ; /* 0x00000007ff047225 */
/* 0x000fcc00078e0004 */
/*04c0*/ IMAD.HI.U32 R3, P0, R3, R0, R4 ; /* 0x0000000003037227 */
/* 0x000fca0007800004 */
/*04d0*/ IADD3 R7, P1, RZ, R3, RZ ; /* 0x00000003ff077210 */
/* 0x000fe20007f3e0ff */
/*04e0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fc800000e06ff */
/*04f0*/ IMAD.WIDE.U32 R4, R7, c[0x0][0x178], RZ ; /* 0x00005e0007047a25 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fc60000ffe4ff */
/*0510*/ IMAD R6, R7, c[0x0][0x17c], R5 ; /* 0x00005f0007067a24 */
/* 0x000fe200078e0205 */
/*0520*/ IADD3 R0, P1, -R4, R0, RZ ; /* 0x0000000004007210 */
/* 0x000fc60007f3e1ff */
/*0530*/ IMAD R3, R3, c[0x0][0x178], R6 ; /* 0x00005e0003037a24 */
/* 0x000fe200078e0206 */
/*0540*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc60003f06070 */
/*0550*/ IMAD.X R5, RZ, RZ, ~R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0e03 */
/*0560*/ IADD3 R3, P1, R0, -c[0x0][0x178], RZ ; /* 0x80005e0000037a10 */
/* 0x000fc80007f3e0ff */
/*0570*/ ISETP.GE.U32.AND.EX P0, PT, R5.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0005007a0c */
/* 0x040fe40003f06100 */
/*0580*/ IADD3.X R4, R5, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0005047a10 */
/* 0x000fe40000ffe4ff */
/*0590*/ SEL R3, R3, R0, P0 ; /* 0x0000000003037207 */
/* 0x000fe40000000000 */
/*05a0*/ SEL R4, R4, R5, P0 ; /* 0x0000000504047207 */
/* 0x000fe40000000000 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x040fe40003f06070 */
/*05c0*/ IADD3 R0, P2, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003007a10 */
/* 0x000fc40007f5e0ff */
/*05d0*/ ISETP.GE.U32.AND.EX P0, PT, R4.reuse, c[0x0][0x17c], PT, P0 ; /* 0x00005f0004007a0c */
/* 0x040fe40003f06100 */
/*05e0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25070 */
/*05f0*/ IADD3.X R5, R4, ~c[0x0][0x17c], RZ, P2, !PT ; /* 0x80005f0004057a10 */
/* 0x000fe400017fe4ff */
/*0600*/ SEL R0, R0, R3, P0 ; /* 0x0000000300007207 */
/* 0x000fe20000000000 */
/*0610*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fe200078e00ff */
/*0620*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25310 */
/*0630*/ SEL R5, R5, R4, P0 ; /* 0x0000000405057207 */
/* 0x000fc40000000000 */
/*0640*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe40000800000 */
/*0650*/ SEL R5, R5, 0xffffffff, P1 ; /* 0xffffffff05057807 */
/* 0x000fe20000800000 */
/*0660*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff99002007950 */
/* 0x000fec0003c3ffff */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z22inicializar_histogramaPjm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22inicializar_histogramaPjm
.globl _Z22inicializar_histogramaPjm
.p2align 8
.type _Z22inicializar_histogramaPjm,@function
_Z22inicializar_histogramaPjm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22inicializar_histogramaPjm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22inicializar_histogramaPjm, .Lfunc_end0-_Z22inicializar_histogramaPjm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19calcular_histogramaPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.p2align 8
.type _Z19calcular_histogramaPjS_mm,@function
_Z19calcular_histogramaPjS_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v1, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_3
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s4, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 0
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s2
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v0
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v1, v0, v1, vcc_lo
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcular_histogramaPjS_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19calcular_histogramaPjS_mm, .Lfunc_end1-_Z19calcular_histogramaPjS_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22inicializar_histogramaPjm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22inicializar_histogramaPjm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcular_histogramaPjS_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcular_histogramaPjS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013d202_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB6905:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE6905:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB6910:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6910:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z22inicializar_histogramaPjmPjm
.type _Z43__device_stub__Z22inicializar_histogramaPjmPjm, @function
_Z43__device_stub__Z22inicializar_histogramaPjmPjm:
.LFB6932:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22inicializar_histogramaPjm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6932:
.size _Z43__device_stub__Z22inicializar_histogramaPjmPjm, .-_Z43__device_stub__Z22inicializar_histogramaPjmPjm
.globl _Z22inicializar_histogramaPjm
.type _Z22inicializar_histogramaPjm, @function
_Z22inicializar_histogramaPjm:
.LFB6933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z22inicializar_histogramaPjmPjm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6933:
.size _Z22inicializar_histogramaPjm, .-_Z22inicializar_histogramaPjm
.globl _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
.type _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm, @function
_Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm:
.LFB6934:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19calcular_histogramaPjS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6934:
.size _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm, .-_Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.type _Z19calcular_histogramaPjS_mm, @function
_Z19calcular_histogramaPjS_mm:
.LFB6935:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6935:
.size _Z19calcular_histogramaPjS_mm, .-_Z19calcular_histogramaPjS_mm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "inicializar_histograma<<<%lu, %lu>>> falla.\n"
.align 8
.LC6:
.string "calcular_histograma<<<%lu, %lu>>> falla.\n"
.align 8
.LC7:
.string "Cuidado! No se selecciona ning\303\272n kernel\n"
.text
.globl _Z13tiempo_kernelPjS_j
.type _Z13tiempo_kernelPjS_j, @function
_Z13tiempo_kernelPjS_j:
.LFB6907:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, 8(%rsp)
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %ebx
movq $0x000000000, (%rsp)
leaq .LC7(%rip), %r13
leaq .LC6(%rip), %r15
leaq 44(%rsp), %r12
jmp .L34
.L44:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L28:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L40
.L29:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $98, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L30:
call cudaPeekAtLastError@PLT
testl %eax, %eax
jne .L42
.L31:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaEventElapsedTime@PLT
cmpl $5, %ebx
jle .L32
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addl $1, %ebx
cmpl $106, %ebx
je .L43
.L34:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
cmpl $1, %ebp
je .L44
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L39:
movl $8, %esi
movq %r14, %rdi
call _Z43__device_stub__Z22inicializar_histogramaPjmPjm
jmp .L28
.L40:
movl $1024, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L29
.L41:
movl $8, %ecx
movl $100000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z19calcular_histogramaPjS_mmPjS_mm
jmp .L30
.L42:
movl $1024, %ecx
movl $98, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L43:
divsd .LC8(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
addl $1, %ebx
jmp .L34
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6907:
.size _Z13tiempo_kernelPjS_j, .-_Z13tiempo_kernelPjS_j
.section .rodata.str1.1
.LC9:
.string "cudaMalloc(&v_device, sizeV)"
.section .rodata.str1.8
.align 8
.LC10:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mbdaso/cuda/master/histograma-primera-implementacion/main.cu"
.align 8
.LC11:
.string "cudaMemcpy(v_device, v, sizeV, cudaMemcpyHostToDevice)"
.section .rodata.str1.1
.LC12:
.string "cudaMalloc(&h_device, sizeH)"
.section .rodata.str1.8
.align 8
.LC13:
.string "Llamando kernel con M = %i N = %i y P = %i\n"
.align 8
.LC14:
.string "cudaMemcpy(h, h_device, sizeH, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC15:
.string "Tiempo transcurrido: %f ms\n"
.LC16:
.string "Histograma: "
.LC17:
.string "%u "
.LC18:
.string "\n"
.LC19:
.string "Elementos del vector: %i\n"
.LC20:
.string "Suma de elementos : %lu\n"
.LC21:
.string "cudaFree(v_device)"
.LC22:
.string "cudaFree(h_device)"
.text
.globl main
.type main, @function
main:
.LFB6906:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 400000(%rax), %rbp
.L47:
call rand@PLT
cltd
shrl $29, %edx
addl %edx, %eax
andl $7, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $57, %esi
leaq .LC10(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $58, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $32, %edi
call malloc@PLT
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $64, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %r8d
movl $100000, %ecx
movl $8, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z13tiempo_kernelPjS_j
movss %xmm0, 12(%rsp)
movl $2, %ecx
movl $32, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC14(%rip), %rdx
movl $70, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rbx
leaq 32(%r15), %r14
movl $0, %ebp
leaq .LC17(%rip), %r13
.L48:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %eax
addq %rax, %rbp
addq $4, %rbx
cmpq %r14, %rbx
jne .L48
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100000, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC21(%rip), %rdx
movl $85, %esi
leaq .LC10(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC22(%rip), %rdx
movl $86, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6906:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z19calcular_histogramaPjS_mm"
.LC24:
.string "_Z22inicializar_histogramaPjm"
.section .rodata.str1.8
.align 8
.LC25:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std3__419piecewise_constructE"
.align 8
.LC26:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC27:
.string "_ZN37_INTERNAL_df3990d6_7_main_cu_ac8204b54cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6937:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcular_histogramaPjS_mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z22inicializar_histogramaPjm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6937:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z37__device_stub__inicializar_histogramaPjm # -- Begin function _Z37__device_stub__inicializar_histogramaPjm
.p2align 4, 0x90
.type _Z37__device_stub__inicializar_histogramaPjm,@function
_Z37__device_stub__inicializar_histogramaPjm: # @_Z37__device_stub__inicializar_histogramaPjm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22inicializar_histogramaPjm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z37__device_stub__inicializar_histogramaPjm, .Lfunc_end0-_Z37__device_stub__inicializar_histogramaPjm
.cfi_endproc
# -- End function
.globl _Z34__device_stub__calcular_histogramaPjS_mm # -- Begin function _Z34__device_stub__calcular_histogramaPjS_mm
.p2align 4, 0x90
.type _Z34__device_stub__calcular_histogramaPjS_mm,@function
_Z34__device_stub__calcular_histogramaPjS_mm: # @_Z34__device_stub__calcular_histogramaPjS_mm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19calcular_histogramaPjS_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__calcular_histogramaPjS_mm, .Lfunc_end1-_Z34__device_stub__calcular_histogramaPjS_mm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-8, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movl $.L.str.1, %esi
movl $57, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.L.str.2, %esi
movl $58, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $32, %edi
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movl $.L.str.3, %esi
movl $64, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movl $.L.str.4, %edi
movl $8, %esi
movl $100000, %edx # imm = 0x186A0
movl $1, %ecx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $1, %edx
callq _Z13tiempo_kernelPjS_j
movss %xmm0, 20(%rsp) # 4-byte Spill
movq (%rsp), %rsi
movl $32, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl $70, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl (%r14,%r12,4), %eax
addq %rax, %r15
incq %r12
cmpq $8, %r12
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movl $.L.str.10, %edi
movl $100000, %esi # imm = 0x186A0
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movl $.L.str.12, %esi
movl $85, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq (%rsp), %rdi
callq hipFree
movl $.L.str.13, %esi
movl $86, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB3_2
# %bb.1:
retq
.LBB3_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.17, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.18, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.19, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.20, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end3:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end3-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13tiempo_kernelPjS_j
.LCPI4_0:
.quad 0x8000000000000000 # double -0
.LCPI4_1:
.quad 0x4059000000000000 # double 100
.text
.globl _Z13tiempo_kernelPjS_j
.p2align 4, 0x90
.type _Z13tiempo_kernelPjS_j,@function
_Z13tiempo_kernelPjS_j: # @_Z13tiempo_kernelPjS_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, 136(%rsp) # 8-byte Spill
movq %rdi, 80(%rsp) # 8-byte Spill
movabsq $4294968320, %r12 # imm = 0x100000400
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorpd %xmm0, %xmm0
leaq -1023(%r12), %r13
leaq 96(%rsp), %rbp
leaq -926(%r12), %r14
xorl %r15d, %r15d
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_13: # in Loop: Header=BB4_1 Depth=1
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
.LBB4_14: # in Loop: Header=BB4_1 Depth=1
movsd 144(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movapd %xmm1, %xmm0
incl %r15d
cmpl $106, %r15d
je .LBB4_15
.LBB4_1: # =>This Inner Loop Header: Depth=1
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $1, %ebx
jne .LBB4_10
# %bb.2: # in Loop: Header=BB4_1 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_1 Depth=1
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq $8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z22inicializar_histogramaPjm, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4: # in Loop: Header=BB4_1 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
je .LBB4_6
# %bb.5: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.14, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
.LBB4_6: # in Loop: Header=BB4_1 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7: # in Loop: Header=BB4_1 Depth=1
movq 136(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq $100000, 56(%rsp) # imm = 0x186A0
movq $8, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z19calcular_histogramaPjS_mm, %edi
movq %rbp, %r9
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8: # in Loop: Header=BB4_1 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
je .LBB4_11
# %bb.9: # in Loop: Header=BB4_1 Depth=1
movl $.L.str.15, %edi
movl $98, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_1 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB4_11: # in Loop: Header=BB4_1 Depth=1
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rbp, %rdi
callq hipEventElapsedTime
cmpl $6, %r15d
jb .LBB4_13
# %bb.12: # in Loop: Header=BB4_1 Depth=1
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
jmp .LBB4_14
.LBB4_15:
divsd .LCPI4_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z13tiempo_kernelPjS_j, .Lfunc_end4-_Z13tiempo_kernelPjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22inicializar_histogramaPjm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcular_histogramaPjS_mm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22inicializar_histogramaPjm,@object # @_Z22inicializar_histogramaPjm
.section .rodata,"a",@progbits
.globl _Z22inicializar_histogramaPjm
.p2align 3, 0x0
_Z22inicializar_histogramaPjm:
.quad _Z37__device_stub__inicializar_histogramaPjm
.size _Z22inicializar_histogramaPjm, 8
.type _Z19calcular_histogramaPjS_mm,@object # @_Z19calcular_histogramaPjS_mm
.globl _Z19calcular_histogramaPjS_mm
.p2align 3, 0x0
_Z19calcular_histogramaPjS_mm:
.quad _Z34__device_stub__calcular_histogramaPjS_mm
.size _Z19calcular_histogramaPjS_mm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mbdaso/cuda/master/histograma-primera-implementacion/main.hip"
.size .L.str, 119
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc(&v_device, sizeV)"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy(v_device, v, sizeV, hipMemcpyHostToDevice)"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc(&h_device, sizeH)"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Llamando kernel con M = %i N = %i y P = %i\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(h, h_device, sizeH, hipMemcpyDeviceToHost)"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo transcurrido: %f ms\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Histograma: "
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%u "
.size .L.str.8, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Elementos del vector: %i\n"
.size .L.str.10, 26
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Suma de elementos : %lu\n"
.size .L.str.11, 25
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipFree(v_device)"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipFree(h_device)"
.size .L.str.13, 18
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "inicializar_histograma<<<%lu, %lu>>> falla.\n"
.size .L.str.14, 45
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "calcular_histograma<<<%lu, %lu>>> falla.\n"
.size .L.str.15, 42
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " returned "
.size .L.str.17, 11
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "("
.size .L.str.18, 2
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz ") at "
.size .L.str.19, 6
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz ":"
.size .L.str.20, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22inicializar_histogramaPjm"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19calcular_histogramaPjS_mm"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Cuidado! No se selecciona ning\303\272n kernel"
.size .Lstr, 41
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__inicializar_histogramaPjm
.addrsig_sym _Z34__device_stub__calcular_histogramaPjS_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22inicializar_histogramaPjm
.addrsig_sym _Z19calcular_histogramaPjS_mm
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} | code for sm_80
Function : _Z12simpleKernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} | .file "tmpxft_00182aa3_00000000-6_simpleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12simpleKernelPfS_PfS_
.type _Z34__device_stub__Z12simpleKernelPfS_PfS_, @function
_Z34__device_stub__Z12simpleKernelPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12simpleKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12simpleKernelPfS_PfS_, .-_Z34__device_stub__Z12simpleKernelPfS_PfS_
.globl _Z12simpleKernelPfS_
.type _Z12simpleKernelPfS_, @function
_Z12simpleKernelPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12simpleKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12simpleKernelPfS_, .-_Z12simpleKernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12simpleKernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simpleKernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simpleKernelPfS_
.globl _Z12simpleKernelPfS_
.p2align 8
.type _Z12simpleKernelPfS_,@function
_Z12simpleKernelPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simpleKernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simpleKernelPfS_, .Lfunc_end0-_Z12simpleKernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simpleKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simpleKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simpleKernel(float *dst, float *src)
{
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
float temp = src[idx];
dst[idx] = temp * temp;
} | .text
.file "simpleKernel.hip"
.globl _Z27__device_stub__simpleKernelPfS_ # -- Begin function _Z27__device_stub__simpleKernelPfS_
.p2align 4, 0x90
.type _Z27__device_stub__simpleKernelPfS_,@function
_Z27__device_stub__simpleKernelPfS_: # @_Z27__device_stub__simpleKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12simpleKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__simpleKernelPfS_, .Lfunc_end0-_Z27__device_stub__simpleKernelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simpleKernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simpleKernelPfS_,@object # @_Z12simpleKernelPfS_
.section .rodata,"a",@progbits
.globl _Z12simpleKernelPfS_
.p2align 3, 0x0
_Z12simpleKernelPfS_:
.quad _Z27__device_stub__simpleKernelPfS_
.size _Z12simpleKernelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12simpleKernelPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simpleKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simpleKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12simpleKernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fca0000400000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simpleKernelPfS_
.globl _Z12simpleKernelPfS_
.p2align 8
.type _Z12simpleKernelPfS_,@function
_Z12simpleKernelPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simpleKernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simpleKernelPfS_, .Lfunc_end0-_Z12simpleKernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simpleKernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simpleKernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00182aa3_00000000-6_simpleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12simpleKernelPfS_PfS_
.type _Z34__device_stub__Z12simpleKernelPfS_PfS_, @function
_Z34__device_stub__Z12simpleKernelPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12simpleKernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12simpleKernelPfS_PfS_, .-_Z34__device_stub__Z12simpleKernelPfS_PfS_
.globl _Z12simpleKernelPfS_
.type _Z12simpleKernelPfS_, @function
_Z12simpleKernelPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12simpleKernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12simpleKernelPfS_, .-_Z12simpleKernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12simpleKernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simpleKernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleKernel.hip"
.globl _Z27__device_stub__simpleKernelPfS_ # -- Begin function _Z27__device_stub__simpleKernelPfS_
.p2align 4, 0x90
.type _Z27__device_stub__simpleKernelPfS_,@function
_Z27__device_stub__simpleKernelPfS_: # @_Z27__device_stub__simpleKernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12simpleKernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__simpleKernelPfS_, .Lfunc_end0-_Z27__device_stub__simpleKernelPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simpleKernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simpleKernelPfS_,@object # @_Z12simpleKernelPfS_
.section .rodata,"a",@progbits
.globl _Z12simpleKernelPfS_
.p2align 3, 0x0
_Z12simpleKernelPfS_:
.quad _Z27__device_stub__simpleKernelPfS_
.size _Z12simpleKernelPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12simpleKernelPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simpleKernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simpleKernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
other things we should test:
- struct pointer, with offset
- multiple struct pointers, cut from same buffer
- getting values from various types of structs passed in
*/
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <cuda.h>
struct Struct_fp_fp_f_f {
float *p1;
float *p2;
float f1;
float f2;
};
struct Struct_fp {
float *p1;
};
struct Struct_1float {
float f1;
};
struct Struct_2floats {
float f1;
float f2;
};
__global__ void struct_byvalue(struct Struct_fp_fp_f_f mystruct, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct_byvalue<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, (float *)gpuOut);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
cudaFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void struct_aspointer(struct Struct_2floats *mystruct, float *out) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
}
void testaspointerstruct() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
struct Struct_2floats mystruct = { 5, 7 };
struct Struct_2floats *gpu_mystruct;
cudaMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
cudaMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), cudaMemcpyHostToDevice);
struct_aspointer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void kernel_twostructs(struct Struct_fp_fp_f_f mystruct, struct Struct_fp mystruct2) {
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
mystruct2.p1[0] = 11.0f;
}
void testtwostructs() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2};
struct Struct_fp mystruct2 = {(float *)gpuFloats3};
kernel_twostructs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, mystruct2);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats3, gpuFloats3, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostFloats3[0] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostFloats3[0] == 11);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
cuStreamDestroy(stream);
}
__global__ void kernel_structbyval_noptrs(struct Struct_1float mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = 5;
}
}
void teststructbyvalNoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_1float mystruct1 = {8.0f};
kernel_structbyval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 5);
delete[] hostFloats1;
cudaFree(gpuFloats1);
cuStreamDestroy(stream);
}
__global__ void kernel_twostructs_noptrs(struct Struct_2floats *mystruct, struct Struct_1float *mystruct2, struct Struct_1float mystruct3, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
out[2] = mystruct2->f1;
out[3] = mystruct3.f1;
}
}
void test_twostructs_byptr_NoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct = {5.0f, 6.0f};
struct Struct_1float mystruct2 = {7.0f};
struct Struct_1float mystruct3 = {8.0f};
struct Struct_2floats *gpu_mystruct;
cudaMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
cudaMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), cudaMemcpyHostToDevice);
struct Struct_1float *gpu_mystruct2;
cudaMalloc((void**)(&gpu_mystruct2), sizeof(mystruct2));
cudaMemcpy(gpu_mystruct2, &mystruct2, sizeof(mystruct2), cudaMemcpyHostToDevice);
kernel_twostructs_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpu_mystruct2, mystruct3, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
cout << hostFloats1[2] << endl;
cout << hostFloats1[3] << endl;
assert(hostFloats1[0] == 5);
assert(hostFloats1[1] == 6);
assert(hostFloats1[2] == 7);
assert(hostFloats1[3] == 8);
cudaFree(gpuFloats1);
cudaFree(gpu_mystruct);
cudaFree(gpu_mystruct2);
// cudaFree(gpu_mystruct3);
delete[] hostFloats1;
cuStreamDestroy(stream);
}
__global__ void kernel_struct2byval_noptrs(struct Struct_2floats mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = mystruct1.f2;
}
}
void teststruct2byvalNoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct1 = {8.0f, 9.0f};
kernel_struct2byval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 9);
delete[] hostFloats1;
cudaFree(gpuFloats1);
cuStreamDestroy(stream);
}
struct struct_f_c_f_c {
float f1;
char c1;
float f2;
char c2;
};
__global__ void kernel_twostructs_gpuside_singlebuffer(struct struct_f_c_f_c *mystruct1, struct struct_f_c_f_c *mystruct2, float *out) {
out[0] = mystruct1->f1;
out[1] = mystruct1->f2;
out[2] = mystruct2->f1;
out[3] = mystruct2->f2;
}
void test_twostructs_gpuside_singlebuffer() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
char *gpubuf;
cudaMalloc((void **)&gpubuf, 1024);
int offset1 = 24;
int offset2 = 40;
struct struct_f_c_f_c mystruct1 = { 5, 0, 7, 0 };
cudaMemcpy(gpubuf + offset1, &mystruct1, sizeof(mystruct1), cudaMemcpyHostToDevice);
struct struct_f_c_f_c mystruct2 = { 9, 0, 3, 0 };
cudaMemcpy(gpubuf + offset2, &mystruct2, sizeof(mystruct2), cudaMemcpyHostToDevice);
kernel_twostructs_gpuside_singlebuffer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(
(struct struct_f_c_f_c *)(gpubuf + offset1),
(struct struct_f_c_f_c *)(gpubuf + offset2),
gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
cout << hostOut[2] << endl;
cout << hostOut[3] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
assert(hostOut[2] == 9);
assert(hostOut[3] == 3);
delete[]hostOut;
cuStreamDestroy(stream);
}
struct NestL2 {
float floats[10];
};
struct NestL1 {
struct NestL2 n1;
struct NestL2 n2;
};
struct NestTop {
struct NestL1 n1;
struct NestL1 n2;
};
__global__ void kernelUseNestTop(NestTop nest, float *out) {
out[0] = nest.n1.n1.floats[0];
out[1] = nest.n1.n1.floats[1];
}
void testKernelUsesNestTop() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostOut = new float[N];
struct NestTop nestTop;
nestTop.n1.n1.floats[0] = 5;
nestTop.n1.n1.floats[1] = 7;
kernelUseNestTop<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(nestTop, (float *)gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
cudaFree(gpuOut);
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void struct_byvalue_withreadnone(struct Struct_fp_fp_f_f mystruct, struct Struct_fp_fp_f_f donothing, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct_withreadnone() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct Struct_fp_fp_f_f donothing = {(float *)0, (float *)0, 0.0f, 0.0f};
struct_byvalue_withreadnone<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, donothing, (float *)gpuOut);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
cudaFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
cuStreamDestroy(stream);
}
int main(int argc, char *argv[]) {
cout << "\ntestvaluestruct" << endl;
testbyvaluestruct();
cout << "\ntestaspointersstruct" << endl;
testaspointerstruct();
cout << "\ntesttwostructs" << endl;
testtwostructs();
cout << "\teststructbyvalNoPtr" << endl;
teststructbyvalNoPtr();
cout << "\ntest_twostructs_byptr_NoPtr" << endl;
test_twostructs_byptr_NoPtr();
cout << "\teststruct2byvalNoPtr" << endl;
teststruct2byvalNoPtr();
cout << "\test_twostructs_gpuside_singlebuffer" << endl;
test_twostructs_gpuside_singlebuffer();
cout << "\ntestKernelUsesNestTop" << endl;
testKernelUsesNestTop();
cout << "\ntestvaluestruct_withreadnone" << endl;
testbyvaluestruct_withreadnone();
return 0;
} | code for sm_80
Function : _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R13, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0d7435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R9, c[0x0][0x170] ; /* 0x00005c0000097a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x194] ; /* 0x0000650000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R15, RZ, RZ, 0x41200000 ; /* 0x41200000ff0f7424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*00f0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16kernelUseNestTop7NestTopPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x200] ; /* 0x00008000ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R3, c[0x0][0x204] ; /* 0x0000810000037a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0070*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fc80000000f00 */
/*0080*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101904 */
/*0090*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fc600078e00ff */
/*00b0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x004fe8000c101904 */
/*00c0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x004fe8000c101904 */
/*00e0*/ LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0070*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101904 */
/*00d0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R13, c[0x0][0x170] ; /* 0x00005c00000d7a02 */
/* 0x000fc60000000f00 */
/*00f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x004fe8000c101904 */
/*0100*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*0110*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R4.64+0x8], R7 ; /* 0x0000080704007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25kernel_structbyval_noptrs13Struct_1floatPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40a00000 ; /* 0x40a00000ff077424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*00a0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R11, -RZ, RZ, 2.5625, 0 ; /* 0x41200000ff0b7435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x41100000 ; /* 0x41100000ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R13, RZ, RZ, 0x41300000 ; /* 0x41300000ff0d7424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16struct_aspointerP14Struct_2floatsPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*0080*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0090*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x004fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14struct_byvalue16Struct_fp_fp_f_fPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R13, -RZ, RZ, 2.53125, 0 ; /* 0x41100000ff0d7435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R9, c[0x0][0x170] ; /* 0x00005c0000097a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R15, RZ, RZ, 0x41200000 ; /* 0x41200000ff0f7424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R2.64+0x4], R11 ; /* 0x0000040b02007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*00f0*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
other things we should test:
- struct pointer, with offset
- multiple struct pointers, cut from same buffer
- getting values from various types of structs passed in
*/
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <cuda.h>
struct Struct_fp_fp_f_f {
float *p1;
float *p2;
float f1;
float f2;
};
struct Struct_fp {
float *p1;
};
struct Struct_1float {
float f1;
};
struct Struct_2floats {
float f1;
float f2;
};
__global__ void struct_byvalue(struct Struct_fp_fp_f_f mystruct, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct_byvalue<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, (float *)gpuOut);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
cudaFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void struct_aspointer(struct Struct_2floats *mystruct, float *out) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
}
void testaspointerstruct() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
struct Struct_2floats mystruct = { 5, 7 };
struct Struct_2floats *gpu_mystruct;
cudaMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
cudaMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), cudaMemcpyHostToDevice);
struct_aspointer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void kernel_twostructs(struct Struct_fp_fp_f_f mystruct, struct Struct_fp mystruct2) {
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
mystruct2.p1[0] = 11.0f;
}
void testtwostructs() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2};
struct Struct_fp mystruct2 = {(float *)gpuFloats3};
kernel_twostructs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, mystruct2);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats3, gpuFloats3, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostFloats3[0] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostFloats3[0] == 11);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
cuStreamDestroy(stream);
}
__global__ void kernel_structbyval_noptrs(struct Struct_1float mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = 5;
}
}
void teststructbyvalNoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_1float mystruct1 = {8.0f};
kernel_structbyval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 5);
delete[] hostFloats1;
cudaFree(gpuFloats1);
cuStreamDestroy(stream);
}
__global__ void kernel_twostructs_noptrs(struct Struct_2floats *mystruct, struct Struct_1float *mystruct2, struct Struct_1float mystruct3, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
out[2] = mystruct2->f1;
out[3] = mystruct3.f1;
}
}
void test_twostructs_byptr_NoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct = {5.0f, 6.0f};
struct Struct_1float mystruct2 = {7.0f};
struct Struct_1float mystruct3 = {8.0f};
struct Struct_2floats *gpu_mystruct;
cudaMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
cudaMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), cudaMemcpyHostToDevice);
struct Struct_1float *gpu_mystruct2;
cudaMalloc((void**)(&gpu_mystruct2), sizeof(mystruct2));
cudaMemcpy(gpu_mystruct2, &mystruct2, sizeof(mystruct2), cudaMemcpyHostToDevice);
kernel_twostructs_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpu_mystruct2, mystruct3, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
cout << hostFloats1[2] << endl;
cout << hostFloats1[3] << endl;
assert(hostFloats1[0] == 5);
assert(hostFloats1[1] == 6);
assert(hostFloats1[2] == 7);
assert(hostFloats1[3] == 8);
cudaFree(gpuFloats1);
cudaFree(gpu_mystruct);
cudaFree(gpu_mystruct2);
// cudaFree(gpu_mystruct3);
delete[] hostFloats1;
cuStreamDestroy(stream);
}
__global__ void kernel_struct2byval_noptrs(struct Struct_2floats mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = mystruct1.f2;
}
}
void teststruct2byvalNoPtr() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct1 = {8.0f, 9.0f};
kernel_struct2byval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 9);
delete[] hostFloats1;
cudaFree(gpuFloats1);
cuStreamDestroy(stream);
}
struct struct_f_c_f_c {
float f1;
char c1;
float f2;
char c2;
};
__global__ void kernel_twostructs_gpuside_singlebuffer(struct struct_f_c_f_c *mystruct1, struct struct_f_c_f_c *mystruct2, float *out) {
out[0] = mystruct1->f1;
out[1] = mystruct1->f2;
out[2] = mystruct2->f1;
out[3] = mystruct2->f2;
}
void test_twostructs_gpuside_singlebuffer() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
char *gpubuf;
cudaMalloc((void **)&gpubuf, 1024);
int offset1 = 24;
int offset2 = 40;
struct struct_f_c_f_c mystruct1 = { 5, 0, 7, 0 };
cudaMemcpy(gpubuf + offset1, &mystruct1, sizeof(mystruct1), cudaMemcpyHostToDevice);
struct struct_f_c_f_c mystruct2 = { 9, 0, 3, 0 };
cudaMemcpy(gpubuf + offset2, &mystruct2, sizeof(mystruct2), cudaMemcpyHostToDevice);
kernel_twostructs_gpuside_singlebuffer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(
(struct struct_f_c_f_c *)(gpubuf + offset1),
(struct struct_f_c_f_c *)(gpubuf + offset2),
gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
cout << hostOut[2] << endl;
cout << hostOut[3] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
assert(hostOut[2] == 9);
assert(hostOut[3] == 3);
delete[]hostOut;
cuStreamDestroy(stream);
}
struct NestL2 {
float floats[10];
};
struct NestL1 {
struct NestL2 n1;
struct NestL2 n2;
};
struct NestTop {
struct NestL1 n1;
struct NestL1 n2;
};
__global__ void kernelUseNestTop(NestTop nest, float *out) {
out[0] = nest.n1.n1.floats[0];
out[1] = nest.n1.n1.floats[1];
}
void testKernelUsesNestTop() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostOut = new float[N];
struct NestTop nestTop;
nestTop.n1.n1.floats[0] = 5;
nestTop.n1.n1.floats[1] = 7;
kernelUseNestTop<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(nestTop, (float *)gpuOut);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
cudaFree(gpuOut);
delete[]hostOut;
cuStreamDestroy(stream);
}
__global__ void struct_byvalue_withreadnone(struct Struct_fp_fp_f_f mystruct, struct Struct_fp_fp_f_f donothing, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct_withreadnone() {
int N = 1024;
CUstream stream;
cuStreamCreate(&stream, 0);
float *gpuFloats1;
cudaMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
cudaMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
cudaMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
cudaMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct Struct_fp_fp_f_f donothing = {(float *)0, (float *)0, 0.0f, 0.0f};
struct_byvalue_withreadnone<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, donothing, (float *)gpuOut);
cudaMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(hostOut, gpuOut, 4 * sizeof(float), cudaMemcpyDeviceToHost);
cuStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
cudaFree(gpuFloats1);
cudaFree(gpuFloats2);
cudaFree(gpuFloats3);
cudaFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
cuStreamDestroy(stream);
}
int main(int argc, char *argv[]) {
cout << "\ntestvaluestruct" << endl;
testbyvaluestruct();
cout << "\ntestaspointersstruct" << endl;
testaspointerstruct();
cout << "\ntesttwostructs" << endl;
testtwostructs();
cout << "\teststructbyvalNoPtr" << endl;
teststructbyvalNoPtr();
cout << "\ntest_twostructs_byptr_NoPtr" << endl;
test_twostructs_byptr_NoPtr();
cout << "\teststruct2byvalNoPtr" << endl;
teststruct2byvalNoPtr();
cout << "\test_twostructs_gpuside_singlebuffer" << endl;
test_twostructs_gpuside_singlebuffer();
cout << "\ntestKernelUsesNestTop" << endl;
testKernelUsesNestTop();
cout << "\ntestvaluestruct_withreadnone" << endl;
testbyvaluestruct_withreadnone();
return 0;
} | /*
other things we should test:
- struct pointer, with offset
- multiple struct pointers, cut from same buffer
- getting values from various types of structs passed in
*/
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <hip/hip_runtime.h>
struct Struct_fp_fp_f_f {
float *p1;
float *p2;
float f1;
float f2;
};
struct Struct_fp {
float *p1;
};
struct Struct_1float {
float f1;
};
struct Struct_2floats {
float f1;
float f2;
};
__global__ void struct_byvalue(struct Struct_fp_fp_f_f mystruct, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct_byvalue<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, (float *)gpuOut);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
hipFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void struct_aspointer(struct Struct_2floats *mystruct, float *out) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
}
void testaspointerstruct() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
struct Struct_2floats mystruct = { 5, 7 };
struct Struct_2floats *gpu_mystruct;
hipMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
hipMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), hipMemcpyHostToDevice);
struct_aspointer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void kernel_twostructs(struct Struct_fp_fp_f_f mystruct, struct Struct_fp mystruct2) {
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
mystruct2.p1[0] = 11.0f;
}
void testtwostructs() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2};
struct Struct_fp mystruct2 = {(float *)gpuFloats3};
kernel_twostructs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, mystruct2);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats3, gpuFloats3, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostFloats3[0] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostFloats3[0] == 11);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
hipStreamDestroy(stream);
}
__global__ void kernel_structbyval_noptrs(struct Struct_1float mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = 5;
}
}
void teststructbyvalNoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_1float mystruct1 = {8.0f};
kernel_structbyval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 5);
delete[] hostFloats1;
hipFree(gpuFloats1);
hipStreamDestroy(stream);
}
__global__ void kernel_twostructs_noptrs(struct Struct_2floats *mystruct, struct Struct_1float *mystruct2, struct Struct_1float mystruct3, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
out[2] = mystruct2->f1;
out[3] = mystruct3.f1;
}
}
void test_twostructs_byptr_NoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct = {5.0f, 6.0f};
struct Struct_1float mystruct2 = {7.0f};
struct Struct_1float mystruct3 = {8.0f};
struct Struct_2floats *gpu_mystruct;
hipMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
hipMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), hipMemcpyHostToDevice);
struct Struct_1float *gpu_mystruct2;
hipMalloc((void**)(&gpu_mystruct2), sizeof(mystruct2));
hipMemcpy(gpu_mystruct2, &mystruct2, sizeof(mystruct2), hipMemcpyHostToDevice);
kernel_twostructs_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpu_mystruct2, mystruct3, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
cout << hostFloats1[2] << endl;
cout << hostFloats1[3] << endl;
assert(hostFloats1[0] == 5);
assert(hostFloats1[1] == 6);
assert(hostFloats1[2] == 7);
assert(hostFloats1[3] == 8);
hipFree(gpuFloats1);
hipFree(gpu_mystruct);
hipFree(gpu_mystruct2);
// cudaFree(gpu_mystruct3);
delete[] hostFloats1;
hipStreamDestroy(stream);
}
__global__ void kernel_struct2byval_noptrs(struct Struct_2floats mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = mystruct1.f2;
}
}
void teststruct2byvalNoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct1 = {8.0f, 9.0f};
kernel_struct2byval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 9);
delete[] hostFloats1;
hipFree(gpuFloats1);
hipStreamDestroy(stream);
}
struct struct_f_c_f_c {
float f1;
char c1;
float f2;
char c2;
};
__global__ void kernel_twostructs_gpuside_singlebuffer(struct struct_f_c_f_c *mystruct1, struct struct_f_c_f_c *mystruct2, float *out) {
out[0] = mystruct1->f1;
out[1] = mystruct1->f2;
out[2] = mystruct2->f1;
out[3] = mystruct2->f2;
}
void test_twostructs_gpuside_singlebuffer() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
char *gpubuf;
hipMalloc((void **)&gpubuf, 1024);
int offset1 = 24;
int offset2 = 40;
struct struct_f_c_f_c mystruct1 = { 5, 0, 7, 0 };
hipMemcpy(gpubuf + offset1, &mystruct1, sizeof(mystruct1), hipMemcpyHostToDevice);
struct struct_f_c_f_c mystruct2 = { 9, 0, 3, 0 };
hipMemcpy(gpubuf + offset2, &mystruct2, sizeof(mystruct2), hipMemcpyHostToDevice);
kernel_twostructs_gpuside_singlebuffer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(
(struct struct_f_c_f_c *)(gpubuf + offset1),
(struct struct_f_c_f_c *)(gpubuf + offset2),
gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
cout << hostOut[2] << endl;
cout << hostOut[3] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
assert(hostOut[2] == 9);
assert(hostOut[3] == 3);
delete[]hostOut;
hipStreamDestroy(stream);
}
struct NestL2 {
float floats[10];
};
struct NestL1 {
struct NestL2 n1;
struct NestL2 n2;
};
struct NestTop {
struct NestL1 n1;
struct NestL1 n2;
};
__global__ void kernelUseNestTop(NestTop nest, float *out) {
out[0] = nest.n1.n1.floats[0];
out[1] = nest.n1.n1.floats[1];
}
void testKernelUsesNestTop() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostOut = new float[N];
struct NestTop nestTop;
nestTop.n1.n1.floats[0] = 5;
nestTop.n1.n1.floats[1] = 7;
kernelUseNestTop<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(nestTop, (float *)gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
hipFree(gpuOut);
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void struct_byvalue_withreadnone(struct Struct_fp_fp_f_f mystruct, struct Struct_fp_fp_f_f donothing, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct_withreadnone() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct Struct_fp_fp_f_f donothing = {(float *)0, (float *)0, 0.0f, 0.0f};
struct_byvalue_withreadnone<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, donothing, (float *)gpuOut);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
hipFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
hipStreamDestroy(stream);
}
int main(int argc, char *argv[]) {
cout << "\ntestvaluestruct" << endl;
testbyvaluestruct();
cout << "\ntestaspointersstruct" << endl;
testaspointerstruct();
cout << "\ntesttwostructs" << endl;
testtwostructs();
cout << "\teststructbyvalNoPtr" << endl;
teststructbyvalNoPtr();
cout << "\ntest_twostructs_byptr_NoPtr" << endl;
test_twostructs_byptr_NoPtr();
cout << "\teststruct2byvalNoPtr" << endl;
teststruct2byvalNoPtr();
cout << "\test_twostructs_gpuside_singlebuffer" << endl;
test_twostructs_gpuside_singlebuffer();
cout << "\ntestKernelUsesNestTop" << endl;
testKernelUsesNestTop();
cout << "\ntestvaluestruct_withreadnone" << endl;
testbyvaluestruct_withreadnone();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
other things we should test:
- struct pointer, with offset
- multiple struct pointers, cut from same buffer
- getting values from various types of structs passed in
*/
#include <iostream>
#include <memory>
#include <cassert>
using namespace std;
#include <hip/hip_runtime.h>
struct Struct_fp_fp_f_f {
float *p1;
float *p2;
float f1;
float f2;
};
struct Struct_fp {
float *p1;
};
struct Struct_1float {
float f1;
};
struct Struct_2floats {
float f1;
float f2;
};
__global__ void struct_byvalue(struct Struct_fp_fp_f_f mystruct, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct_byvalue<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, (float *)gpuOut);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
hipFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void struct_aspointer(struct Struct_2floats *mystruct, float *out) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
}
void testaspointerstruct() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
struct Struct_2floats mystruct = { 5, 7 };
struct Struct_2floats *gpu_mystruct;
hipMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
hipMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), hipMemcpyHostToDevice);
struct_aspointer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void kernel_twostructs(struct Struct_fp_fp_f_f mystruct, struct Struct_fp mystruct2) {
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
mystruct2.p1[0] = 11.0f;
}
void testtwostructs() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2};
struct Struct_fp mystruct2 = {(float *)gpuFloats3};
kernel_twostructs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, mystruct2);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats3, gpuFloats3, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostFloats3[0] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostFloats3[0] == 11);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
hipStreamDestroy(stream);
}
__global__ void kernel_structbyval_noptrs(struct Struct_1float mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = 5;
}
}
void teststructbyvalNoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_1float mystruct1 = {8.0f};
kernel_structbyval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 5);
delete[] hostFloats1;
hipFree(gpuFloats1);
hipStreamDestroy(stream);
}
__global__ void kernel_twostructs_noptrs(struct Struct_2floats *mystruct, struct Struct_1float *mystruct2, struct Struct_1float mystruct3, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct->f1;
out[1] = mystruct->f2;
out[2] = mystruct2->f1;
out[3] = mystruct3.f1;
}
}
void test_twostructs_byptr_NoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct = {5.0f, 6.0f};
struct Struct_1float mystruct2 = {7.0f};
struct Struct_1float mystruct3 = {8.0f};
struct Struct_2floats *gpu_mystruct;
hipMalloc((void**)(&gpu_mystruct), sizeof(mystruct));
hipMemcpy(gpu_mystruct, &mystruct, sizeof(mystruct), hipMemcpyHostToDevice);
struct Struct_1float *gpu_mystruct2;
hipMalloc((void**)(&gpu_mystruct2), sizeof(mystruct2));
hipMemcpy(gpu_mystruct2, &mystruct2, sizeof(mystruct2), hipMemcpyHostToDevice);
kernel_twostructs_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(gpu_mystruct, gpu_mystruct2, mystruct3, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
cout << hostFloats1[2] << endl;
cout << hostFloats1[3] << endl;
assert(hostFloats1[0] == 5);
assert(hostFloats1[1] == 6);
assert(hostFloats1[2] == 7);
assert(hostFloats1[3] == 8);
hipFree(gpuFloats1);
hipFree(gpu_mystruct);
hipFree(gpu_mystruct2);
// cudaFree(gpu_mystruct3);
delete[] hostFloats1;
hipStreamDestroy(stream);
}
__global__ void kernel_struct2byval_noptrs(struct Struct_2floats mystruct1, float *out) {
if(threadIdx.x == 0) {
out[0] = mystruct1.f1;
out[1] = mystruct1.f2;
}
}
void teststruct2byvalNoPtr() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostFloats1 = new float[N];
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
struct Struct_2floats mystruct1 = {8.0f, 9.0f};
kernel_struct2byval_noptrs<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct1, (float *)gpuFloats1);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats1[1] << endl;
assert(hostFloats1[0] == 8);
assert(hostFloats1[1] == 9);
delete[] hostFloats1;
hipFree(gpuFloats1);
hipStreamDestroy(stream);
}
struct struct_f_c_f_c {
float f1;
char c1;
float f2;
char c2;
};
__global__ void kernel_twostructs_gpuside_singlebuffer(struct struct_f_c_f_c *mystruct1, struct struct_f_c_f_c *mystruct2, float *out) {
out[0] = mystruct1->f1;
out[1] = mystruct1->f2;
out[2] = mystruct2->f1;
out[3] = mystruct2->f2;
}
void test_twostructs_gpuside_singlebuffer() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *hostOut = new float[N];
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
char *gpubuf;
hipMalloc((void **)&gpubuf, 1024);
int offset1 = 24;
int offset2 = 40;
struct struct_f_c_f_c mystruct1 = { 5, 0, 7, 0 };
hipMemcpy(gpubuf + offset1, &mystruct1, sizeof(mystruct1), hipMemcpyHostToDevice);
struct struct_f_c_f_c mystruct2 = { 9, 0, 3, 0 };
hipMemcpy(gpubuf + offset2, &mystruct2, sizeof(mystruct2), hipMemcpyHostToDevice);
kernel_twostructs_gpuside_singlebuffer<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(
(struct struct_f_c_f_c *)(gpubuf + offset1),
(struct struct_f_c_f_c *)(gpubuf + offset2),
gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
cout << hostOut[2] << endl;
cout << hostOut[3] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
assert(hostOut[2] == 9);
assert(hostOut[3] == 3);
delete[]hostOut;
hipStreamDestroy(stream);
}
struct NestL2 {
float floats[10];
};
struct NestL1 {
struct NestL2 n1;
struct NestL2 n2;
};
struct NestTop {
struct NestL1 n1;
struct NestL1 n2;
};
__global__ void kernelUseNestTop(NestTop nest, float *out) {
out[0] = nest.n1.n1.floats[0];
out[1] = nest.n1.n1.floats[1];
}
void testKernelUsesNestTop() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostOut = new float[N];
struct NestTop nestTop;
nestTop.n1.n1.floats[0] = 5;
nestTop.n1.n1.floats[1] = 7;
kernelUseNestTop<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(nestTop, (float *)gpuOut);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostOut[0] == 5);
assert(hostOut[1] == 7);
hipFree(gpuOut);
delete[]hostOut;
hipStreamDestroy(stream);
}
__global__ void struct_byvalue_withreadnone(struct Struct_fp_fp_f_f mystruct, struct Struct_fp_fp_f_f donothing, float *out) {
out[0] = mystruct.f1;
out[1] = mystruct.f2;
mystruct.p1[0] = 9.0f;
mystruct.p2[0] = 10.0f;
}
void testbyvaluestruct_withreadnone() {
int N = 1024;
hipStream_t stream;
hipStreamCreateWithFlags(&stream, 0);
float *gpuFloats1;
hipMalloc((void**)(&gpuFloats1), N * sizeof(float));
float *gpuFloats2;
hipMalloc((void**)(&gpuFloats2), N * sizeof(float));
float *gpuFloats3;
hipMalloc((void**)(&gpuFloats3), N * sizeof(float));
float *gpuOut;
hipMalloc((void**)(&gpuOut), N * sizeof(float));
float *hostFloats1 = new float[N];
float *hostFloats2 = new float[N];
float *hostFloats3 = new float[N];
float *hostOut = new float[N];
struct Struct_fp_fp_f_f mystruct = {(float *)gpuFloats1, (float *)gpuFloats2, 3.0f, 8.0f};
struct Struct_fp_fp_f_f donothing = {(float *)0, (float *)0, 0.0f, 0.0f};
struct_byvalue_withreadnone<<<dim3(1,1,1), dim3(32,1,1), 0, stream>>>(mystruct, donothing, (float *)gpuOut);
hipMemcpy(hostFloats1, gpuFloats1, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostFloats2, gpuFloats2, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(hostOut, gpuOut, 4 * sizeof(float), hipMemcpyDeviceToHost);
hipStreamSynchronize(stream);
cout << hostFloats1[0] << endl;
cout << hostFloats2[0] << endl;
cout << hostOut[0] << endl;
cout << hostOut[1] << endl;
assert(hostFloats1[0] == 9);
assert(hostFloats2[0] == 10);
assert(hostOut[0] == 3);
assert(hostOut[1] == 8);
hipFree(gpuFloats1);
hipFree(gpuFloats2);
hipFree(gpuFloats3);
hipFree(gpuOut);
delete[]hostFloats1;
delete[]hostFloats2;
delete[]hostFloats3;
delete[]hostOut;
hipStreamDestroy(stream);
}
int main(int argc, char *argv[]) {
cout << "\ntestvaluestruct" << endl;
testbyvaluestruct();
cout << "\ntestaspointersstruct" << endl;
testaspointerstruct();
cout << "\ntesttwostructs" << endl;
testtwostructs();
cout << "\teststructbyvalNoPtr" << endl;
teststructbyvalNoPtr();
cout << "\ntest_twostructs_byptr_NoPtr" << endl;
test_twostructs_byptr_NoPtr();
cout << "\teststruct2byvalNoPtr" << endl;
teststruct2byvalNoPtr();
cout << "\test_twostructs_gpuside_singlebuffer" << endl;
test_twostructs_gpuside_singlebuffer();
cout << "\ntestKernelUsesNestTop" << endl;
testKernelUsesNestTop();
cout << "\ntestvaluestruct_withreadnone" << endl;
testbyvaluestruct_withreadnone();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14struct_byvalue16Struct_fp_fp_f_fPf
.globl _Z14struct_byvalue16Struct_fp_fp_f_fPf
.p2align 8
.type _Z14struct_byvalue16Struct_fp_fp_f_fPf,@function
_Z14struct_byvalue16Struct_fp_fp_f_fPf:
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0x41200000
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, 0x41100000 :: v_dual_mov_b32 v0, s4
v_mov_b32_e32 v1, s5
s_clause 0x2
global_store_b64 v2, v[0:1], s[6:7]
global_store_b32 v2, v3, s[0:1]
global_store_b32 v2, v4, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14struct_byvalue16Struct_fp_fp_f_fPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14struct_byvalue16Struct_fp_fp_f_fPf, .Lfunc_end0-_Z14struct_byvalue16Struct_fp_fp_f_fPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16struct_aspointerP14Struct_2floatsPf
.globl _Z16struct_aspointerP14Struct_2floatsPf
.p2align 8
.type _Z16struct_aspointerP14Struct_2floatsPf,@function
_Z16struct_aspointerP14Struct_2floatsPf:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
global_store_b32 v0, v1, s[2:3]
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3] offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16struct_aspointerP14Struct_2floatsPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16struct_aspointerP14Struct_2floatsPf, .Lfunc_end1-_Z16struct_aspointerP14Struct_2floatsPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.globl _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.p2align 8
.type _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp,@function
_Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x41100000
v_mov_b32_e32 v2, 0x41200000
v_mov_b32_e32 v3, 0x41300000
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v2, s[6:7]
global_store_b32 v0, v3, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp, .Lfunc_end2-_Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25kernel_structbyval_noptrs13Struct_1floatPf
.globl _Z25kernel_structbyval_noptrs13Struct_1floatPf
.p2align 8
.type _Z25kernel_structbyval_noptrs13Struct_1floatPf,@function
_Z25kernel_structbyval_noptrs13Struct_1floatPf:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_2
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x40a00000
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s2
global_store_b64 v2, v[0:1], s[0:1]
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_structbyval_noptrs13Struct_1floatPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z25kernel_structbyval_noptrs13Struct_1floatPf, .Lfunc_end3-_Z25kernel_structbyval_noptrs13Struct_1floatPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.globl _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.p2align 8
.type _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf,@function
_Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v0, s3
global_store_b32 v2, v0, s[0:1]
global_load_b32 v0, v2, s[4:5] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v2, v0, s[0:1] offset:4
global_load_b32 v0, v2, s[6:7]
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[0:1] offset:8
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf, .Lfunc_end4-_Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.globl _Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.p2align 8
.type _Z26kernel_struct2byval_noptrs14Struct_2floatsPf,@function
_Z26kernel_struct2byval_noptrs14Struct_2floatsPf:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB5_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
global_store_b64 v2, v[0:1], s[2:3]
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z26kernel_struct2byval_noptrs14Struct_2floatsPf, .Lfunc_end5-_Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.globl _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.p2align 8
.type _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf,@function
_Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
global_load_b32 v1, v0, s[4:5] offset:8
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1] offset:4
global_load_b32 v1, v0, s[6:7]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1] offset:8
global_load_b32 v1, v0, s[6:7] offset:8
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1] offset:12
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf, .Lfunc_end6-_Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16kernelUseNestTop7NestTopPf
.globl _Z16kernelUseNestTop7NestTopPf
.p2align 8
.type _Z16kernelUseNestTop7NestTopPf,@function
_Z16kernelUseNestTop7NestTopPf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0xa0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernelUseNestTop7NestTopPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 168
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end7:
.size _Z16kernelUseNestTop7NestTopPf, .Lfunc_end7-_Z16kernelUseNestTop7NestTopPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.globl _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.p2align 8
.type _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf,@function
_Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x30
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0x41200000
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, 0x41100000 :: v_dual_mov_b32 v0, s4
v_mov_b32_e32 v1, s5
s_clause 0x2
global_store_b64 v2, v[0:1], s[6:7]
global_store_b32 v2, v3, s[0:1]
global_store_b32 v2, v4, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end8:
.size _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf, .Lfunc_end8-_Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14struct_byvalue16Struct_fp_fp_f_fPf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14struct_byvalue16Struct_fp_fp_f_fPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16struct_aspointerP14Struct_2floatsPf
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z16struct_aspointerP14Struct_2floatsPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z17kernel_twostructs16Struct_fp_fp_f_f9Struct_fp.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_structbyval_noptrs13Struct_1floatPf
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z25kernel_structbyval_noptrs13Struct_1floatPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z24kernel_twostructs_noptrsP14Struct_2floatsP13Struct_1floatS1_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26kernel_struct2byval_noptrs14Struct_2floatsPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z26kernel_struct2byval_noptrs14Struct_2floatsPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z38kernel_twostructs_gpuside_singlebufferP14struct_f_c_f_cS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 160
.value_kind: by_value
- .address_space: global
.offset: 160
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 168
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernelUseNestTop7NestTopPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z16kernelUseNestTop7NestTopPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z27struct_byvalue_withreadnone16Struct_fp_fp_f_fS_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z11evaluate_2bPK7double4P7double3Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*0050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0060*/ BRA 0x60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
cudaDeviceSynchronize();
} | .file "tmpxft_001870ef_00000000-6_twobodyForceNN.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl computeInteraction
.type computeInteraction, @function
computeInteraction:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size computeInteraction, .-computeInteraction
.globl _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
.type _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd, @function
_Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11evaluate_2bPK7double4P7double3Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd, .-_Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
.globl _Z11evaluate_2bPK7double4P7double3Pd
.type _Z11evaluate_2bPK7double4P7double3Pd, @function
_Z11evaluate_2bPK7double4P7double3Pd:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11evaluate_2bPK7double4P7double3Pd, .-_Z11evaluate_2bPK7double4P7double3Pd
.globl _Z18launch_evaluate_2bPK7double4P7double3Pd
.type _Z18launch_evaluate_2bPK7double4P7double3Pd, @function
_Z18launch_evaluate_2bPK7double4P7double3Pd:
.LFB2028:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
jmp .L14
.cfi_endproc
.LFE2028:
.size _Z18launch_evaluate_2bPK7double4P7double3Pd, .-_Z18launch_evaluate_2bPK7double4P7double3Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11evaluate_2bPK7double4P7double3Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11evaluate_2bPK7double4P7double3Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
hipDeviceSynchronize();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.globl _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 8
.type _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end0-_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __device__ double computeInteraction(
const unsigned int atom1,
const unsigned int atom2,
const double4* __restrict__ posq,
double3 * forces) {
// CUDA COMPUTATIONAL KERNEL
return 0;
}
__global__ void evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function will parallelize computeInteraction to run in parallel with all the pairs of molecules,
// for now just computing the interaction between the 2 molecules (identified by their Oxygen atom)
energy[0] = computeInteraction(0, 3, posq, forces);
}
void launch_evaluate_2b(
const double4* __restrict__ posq,
double3 * forces,
double * energy) {
// This function is useful to configure the number of device threads, just one for now:
evaluate_2b<<<1,1>>>(posq, forces, energy);
hipDeviceSynchronize();
} | .text
.file "twobodyForceNN.hip"
.globl _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd # -- Begin function _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 4, 0x90
.type _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd: # @_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end0-_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_endproc
# -- End function
.globl _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd # -- Begin function _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 4, 0x90
.type _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd: # @_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end1-_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@object # @_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.section .rodata,"a",@progbits
.globl _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 3, 0x0
_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd:
.quad _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.size _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11evaluate_2bPK7double4P7double3Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*0050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0060*/ BRA 0x60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.globl _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 8
.type _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd:
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end0-_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001870ef_00000000-6_twobodyForceNN.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl computeInteraction
.type computeInteraction, @function
computeInteraction:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size computeInteraction, .-computeInteraction
.globl _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
.type _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd, @function
_Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11evaluate_2bPK7double4P7double3Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd, .-_Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
.globl _Z11evaluate_2bPK7double4P7double3Pd
.type _Z11evaluate_2bPK7double4P7double3Pd, @function
_Z11evaluate_2bPK7double4P7double3Pd:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11evaluate_2bPK7double4P7double3Pd, .-_Z11evaluate_2bPK7double4P7double3Pd
.globl _Z18launch_evaluate_2bPK7double4P7double3Pd
.type _Z18launch_evaluate_2bPK7double4P7double3Pd, @function
_Z18launch_evaluate_2bPK7double4P7double3Pd:
.LFB2028:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z50__device_stub__Z11evaluate_2bPK7double4P7double3PdPK7double4P7double3Pd
jmp .L14
.cfi_endproc
.LFE2028:
.size _Z18launch_evaluate_2bPK7double4P7double3Pd, .-_Z18launch_evaluate_2bPK7double4P7double3Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11evaluate_2bPK7double4P7double3Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11evaluate_2bPK7double4P7double3Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "twobodyForceNN.hip"
.globl _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd # -- Begin function _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 4, 0x90
.type _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd: # @_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end0-_Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_endproc
# -- End function
.globl _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd # -- Begin function _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 4, 0x90
.type _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@function
_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd: # @_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, .Lfunc_end1-_Z18launch_evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd,@object # @_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.section .rodata,"a",@progbits
.globl _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.p2align 3, 0x0
_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd:
.quad _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.size _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11evaluate_2bPK15HIP_vector_typeIdLj4EEPS_IdLj3EEPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
cudaGetDeviceCount(&devCount);
if (deviceid<devCount) {
cudaSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
cudaDeviceReset();
return (0);
} | code for sm_80
Function : _Z14helloWorld_GPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
cudaGetDeviceCount(&devCount);
if (deviceid<devCount) {
cudaSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
cudaDeviceReset();
return (0);
} | .file "tmpxft_00193bd6_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14helloWorld_GPUvv
.type _Z33__device_stub__Z14helloWorld_GPUvv, @function
_Z33__device_stub__Z14helloWorld_GPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14helloWorld_GPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14helloWorld_GPUvv, .-_Z33__device_stub__Z14helloWorld_GPUvv
.globl _Z14helloWorld_GPUv
.type _Z14helloWorld_GPUv, @function
_Z14helloWorld_GPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14helloWorld_GPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14helloWorld_GPUv, .-_Z14helloWorld_GPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl $1, %eax
cmpl $0, 12(%rsp)
jle .L11
movl $0, %edi
call cudaSetDevice@PLT
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceReset@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call _Z33__device_stub__Z14helloWorld_GPUvv
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14helloWorld_GPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14helloWorld_GPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
cudaGetDeviceCount(&devCount);
if (deviceid<devCount) {
cudaSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
cudaDeviceReset();
return (0);
} | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
hipGetDeviceCount(&devCount);
if (deviceid<devCount) {
hipSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
hipDeviceReset();
return (0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
hipGetDeviceCount(&devCount);
if (deviceid<devCount) {
hipSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
hipDeviceReset();
return (0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14helloWorld_GPUv
.globl _Z14helloWorld_GPUv
.p2align 8
.type _Z14helloWorld_GPUv,@function
_Z14helloWorld_GPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14helloWorld_GPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14helloWorld_GPUv, .Lfunc_end0-_Z14helloWorld_GPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world!\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14helloWorld_GPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z14helloWorld_GPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // In this assignment you will write a basic kernel where every thread
// will write out to console string "Hello world!".
// You will also initialize GPU using cudaSetDevice() and also launch
// your "Hello world" kernel.
#include <stdio.h>
#include <stdlib.h>
// we have to include few more things
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
//----------------------------------------------------------------------
// TASK 2: Write a "Hello world" kernel
//
// Remember that kernel is defined by __global__ and inside it looks like
// a serial code for CPU. For printing out to console you can use printf().
// write your kernel here
__global__ void helloWorld_GPU(void) {
printf("hello world!\n");
}
//----------------------------------------------------------------------
int main(void) {
//----------------------------------------------------------------------
// TASK 1: Initiate GPU using cudaSetDevice()
//
// You can also try to write a check if there is a device with that id,
// so the code behaves nicely when it fails
// write you GPU initialization here
int deviceid = 0;
int devCount;
hipGetDeviceCount(&devCount);
if (deviceid<devCount) {
hipSetDevice(deviceid);
}
else return(1);
//----------------------------------------------------------------------
//----------------------------------------------------------------------
// TASK 3: execute your "Hello world" kernel on 1 block with 5 threads
// using execution configuration syntax.
//
// You may use whatever syntax version you prefer, a simplified one
// dimensional or full three dimensional call using dim3 data type.
// execute your "Hello world" kernel here
int nBlocks = 1;
int nThreads = 5;
helloWorld_GPU<<< nBlocks, nThreads >>>();
//----------------------------------------------------------------------
hipDeviceReset();
return (0);
} | .text
.file "helloworld.hip"
.globl _Z29__device_stub__helloWorld_GPUv # -- Begin function _Z29__device_stub__helloWorld_GPUv
.p2align 4, 0x90
.type _Z29__device_stub__helloWorld_GPUv,@function
_Z29__device_stub__helloWorld_GPUv: # @_Z29__device_stub__helloWorld_GPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14helloWorld_GPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__helloWorld_GPUv, .Lfunc_end0-_Z29__device_stub__helloWorld_GPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB1_1
# %bb.2:
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14helloWorld_GPUv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceReset
jmp .LBB1_5
.LBB1_1:
movl $1, %ebx
.LBB1_5:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14helloWorld_GPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14helloWorld_GPUv,@object # @_Z14helloWorld_GPUv
.section .rodata,"a",@progbits
.globl _Z14helloWorld_GPUv
.p2align 3, 0x0
_Z14helloWorld_GPUv:
.quad _Z29__device_stub__helloWorld_GPUv
.size _Z14helloWorld_GPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14helloWorld_GPUv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__helloWorld_GPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14helloWorld_GPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14helloWorld_GPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14helloWorld_GPUv
.globl _Z14helloWorld_GPUv
.p2align 8
.type _Z14helloWorld_GPUv,@function
_Z14helloWorld_GPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14helloWorld_GPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14helloWorld_GPUv, .Lfunc_end0-_Z14helloWorld_GPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello world!\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14helloWorld_GPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z14helloWorld_GPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193bd6_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14helloWorld_GPUvv
.type _Z33__device_stub__Z14helloWorld_GPUvv, @function
_Z33__device_stub__Z14helloWorld_GPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14helloWorld_GPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14helloWorld_GPUvv, .-_Z33__device_stub__Z14helloWorld_GPUvv
.globl _Z14helloWorld_GPUv
.type _Z14helloWorld_GPUv, @function
_Z14helloWorld_GPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14helloWorld_GPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14helloWorld_GPUv, .-_Z14helloWorld_GPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl $1, %eax
cmpl $0, 12(%rsp)
jle .L11
movl $0, %edi
call cudaSetDevice@PLT
movl $5, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceReset@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call _Z33__device_stub__Z14helloWorld_GPUvv
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14helloWorld_GPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14helloWorld_GPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld.hip"
.globl _Z29__device_stub__helloWorld_GPUv # -- Begin function _Z29__device_stub__helloWorld_GPUv
.p2align 4, 0x90
.type _Z29__device_stub__helloWorld_GPUv,@function
_Z29__device_stub__helloWorld_GPUv: # @_Z29__device_stub__helloWorld_GPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14helloWorld_GPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__helloWorld_GPUv, .Lfunc_end0-_Z29__device_stub__helloWorld_GPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB1_1
# %bb.2:
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14helloWorld_GPUv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceReset
jmp .LBB1_5
.LBB1_1:
movl $1, %ebx
.LBB1_5:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14helloWorld_GPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14helloWorld_GPUv,@object # @_Z14helloWorld_GPUv
.section .rodata,"a",@progbits
.globl _Z14helloWorld_GPUv
.p2align 3, 0x0
_Z14helloWorld_GPUv:
.quad _Z29__device_stub__helloWorld_GPUv
.size _Z14helloWorld_GPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14helloWorld_GPUv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__helloWorld_GPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14helloWorld_GPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} | code for sm_80
Function : add_two_vector_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} | .file "tmpxft_0004d243_00000000-6_kernel_functions_for_template.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
.type _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_, @function
_Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add_two_vector_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_, .-_Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
.globl add_two_vector_kernel
.type add_two_vector_kernel, @function
add_two_vector_kernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size add_two_vector_kernel, .-add_two_vector_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add_two_vector_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add_two_vector_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} | #include <hip/hip_runtime.h>
template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add_two_vector_kernel
.globl add_two_vector_kernel
.p2align 8
.type add_two_vector_kernel,@function
add_two_vector_kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_two_vector_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add_two_vector_kernel, .Lfunc_end0-add_two_vector_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_two_vector_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add_two_vector_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
template <class T>
__device__ T add_two_vector(T x, T y){
return (x + y);
}
extern "C" {
__global__ void add_two_vector_kernel(int nx, int *a, int *b, int *res){
const int x = threadIdx.x + blockDim.x * blockIdx.x;
if (x < nx){
res[x] = add_two_vector<int>(a[x], b[x]);
}
}
} | .text
.file "kernel_functions_for_template.hip"
.globl __device_stub__add_two_vector_kernel # -- Begin function __device_stub__add_two_vector_kernel
.p2align 4, 0x90
.type __device_stub__add_two_vector_kernel,@function
__device_stub__add_two_vector_kernel: # @__device_stub__add_two_vector_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add_two_vector_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add_two_vector_kernel, .Lfunc_end0-__device_stub__add_two_vector_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_two_vector_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add_two_vector_kernel,@object # @add_two_vector_kernel
.section .rodata,"a",@progbits
.globl add_two_vector_kernel
.p2align 3, 0x0
add_two_vector_kernel:
.quad __device_stub__add_two_vector_kernel
.size add_two_vector_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add_two_vector_kernel"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add_two_vector_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add_two_vector_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add_two_vector_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add_two_vector_kernel
.globl add_two_vector_kernel
.p2align 8
.type add_two_vector_kernel,@function
add_two_vector_kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_two_vector_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add_two_vector_kernel, .Lfunc_end0-add_two_vector_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_two_vector_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add_two_vector_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d243_00000000-6_kernel_functions_for_template.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
.type _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_, @function
_Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add_two_vector_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_, .-_Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
.globl add_two_vector_kernel
.type add_two_vector_kernel, @function
add_two_vector_kernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21add_two_vector_kerneliPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size add_two_vector_kernel, .-add_two_vector_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add_two_vector_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add_two_vector_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_functions_for_template.hip"
.globl __device_stub__add_two_vector_kernel # -- Begin function __device_stub__add_two_vector_kernel
.p2align 4, 0x90
.type __device_stub__add_two_vector_kernel,@function
__device_stub__add_two_vector_kernel: # @__device_stub__add_two_vector_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add_two_vector_kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add_two_vector_kernel, .Lfunc_end0-__device_stub__add_two_vector_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_two_vector_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add_two_vector_kernel,@object # @add_two_vector_kernel
.section .rodata,"a",@progbits
.globl add_two_vector_kernel
.p2align 3, 0x0
add_two_vector_kernel:
.quad __device_stub__add_two_vector_kernel
.size add_two_vector_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add_two_vector_kernel"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add_two_vector_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add_two_vector_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} | code for sm_80
Function : _Z14inclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.EQ.OR P2, PT, R0.reuse, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x040fe40000742670 */
/*0080*/ ISETP.LT.U32.OR P1, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fe20000721470 */
/*0090*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*00c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*00d0*/ @!P2 LDS R7, [R0.X4+-0x4] ; /* 0xfffffc000007a984 */
/* 0x000e240000004800 */
/*00e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fc400078e0207 */
/*00f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0100*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.LT.U32.OR P2, PT, R0, 0x4, P0 ; /* 0x000000040000780c */
/* 0x000fca0000741470 */
/*0130*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0140*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0150*/ @!P1 LDS R5, [R0.X4+-0x8] ; /* 0xfffff80000059984 */
/* 0x000e240000004800 */
/*0160*/ @!P1 IMAD.IADD R5, R4, 0x1, R5 ; /* 0x0000000104059824 */
/* 0x001fe400078e0205 */
/*0170*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x8, P0 ; /* 0x000000080000780c */
/* 0x000fca0000721470 */
/*01b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*01c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*01d0*/ @!P2 LDS R7, [R0.X4+-0x10] ; /* 0xfffff0000007a984 */
/* 0x000e240000004800 */
/*01e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*01f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0200*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.LT.U32.OR P2, PT, R0, 0x10, P0 ; /* 0x000000100000780c */
/* 0x000fca0000741470 */
/*0230*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0240*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0250*/ @!P1 LDS R5, [R0.X4+-0x20] ; /* 0xffffe00000059984 */
/* 0x000e240000004800 */
/*0260*/ @!P1 IADD3 R5, R4, R5, RZ ; /* 0x0000000504059210 */
/* 0x001fe40007ffe0ff */
/*0270*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0280*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x20, P0 ; /* 0x000000200000780c */
/* 0x000fca0000721470 */
/*02b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*02c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*02d0*/ @!P2 LDS R7, [R0.X4+-0x40] ; /* 0xffffc0000007a984 */
/* 0x000e240000004800 */
/*02e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*02f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0300*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.LT.U32.OR P2, PT, R0, 0x40, P0 ; /* 0x000000400000780c */
/* 0x000fca0000741470 */
/*0330*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0340*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0350*/ @!P1 LDS R5, [R0.X4+-0x80] ; /* 0xffff800000059984 */
/* 0x000e240000004800 */
/*0360*/ @!P1 IMAD.IADD R5, R4, 0x1, R5 ; /* 0x0000000104059824 */
/* 0x001fe400078e0205 */
/*0370*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0380*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x80, P0 ; /* 0x000000800000780c */
/* 0x000fc40000721470 */
/*03b0*/ ISETP.LT.U32.OR P0, PT, R0, 0x100, P0 ; /* 0x000001000000780c */
/* 0x000fc60000701470 */
/*03c0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*03d0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*03e0*/ @!P2 LDS R7, [R0.X4+-0x100] ; /* 0xffff00000007a984 */
/* 0x000e240000004800 */
/*03f0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*0400*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0410*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0440*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R5, [R0.X4+-0x200] ; /* 0xfffe000000059984 */
/* 0x000e240000004800 */
/*0460*/ @!P1 IADD3 R5, R4, R5, RZ ; /* 0x0000000504059210 */
/* 0x001fc40007ffe0ff */
/*0470*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0480*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*04b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ @!P0 LDS R4, [R0.X4] ; /* 0x0000000000048984 */
/* 0x000fe80000004800 */
/*04d0*/ @!P0 LDS R7, [R0.X4+-0x400] ; /* 0xfffc000000078984 */
/* 0x000e240000004800 */
/*04e0*/ @!P0 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104078824 */
/* 0x001fc400078e0207 */
/*04f0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0500*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0520*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*0530*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} | .file "tmpxft_00070ce8_00000000-6_inclusive_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14inclusive_scanPiPi
.type _Z34__device_stub__Z14inclusive_scanPiPi, @function
_Z34__device_stub__Z14inclusive_scanPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14inclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14inclusive_scanPiPi, .-_Z34__device_stub__Z14inclusive_scanPiPi
.globl _Z14inclusive_scanPi
.type _Z14inclusive_scanPi, @function
_Z14inclusive_scanPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14inclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14inclusive_scanPi, .-_Z14inclusive_scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "out[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
leaq 2080(%rsp), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 2080(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 2080(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $-1, %eax
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z34__device_stub__Z14inclusive_scanPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14inclusive_scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14inclusive_scanPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 8
.type _Z14inclusive_scanPi,@function
_Z14inclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s1, 1
s_cmpk_gt_u32 s1, 0xff
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_cmp_le_u32_e64 s0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_1
v_subrev_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
s_branch .LBB0_1
.LBB0_4:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14inclusive_scanPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14inclusive_scanPi, .Lfunc_end0-_Z14inclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14inclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14inclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 512
__global__ void inclusive_scan(int *d_in){
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1){
if((i >= s) && (i < N)) {
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main(){
int h_in[N];
int h_out[N];
for(int i=0; i < N; i++)
h_in[i] = 1;
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
inclusive_scan<<<1, N>>>(d_in);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
return -1;
} | .text
.file "inclusive_scan.hip"
.globl _Z29__device_stub__inclusive_scanPi # -- Begin function _Z29__device_stub__inclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__inclusive_scanPi,@function
_Z29__device_stub__inclusive_scanPi: # @_Z29__device_stub__inclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14inclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__inclusive_scanPi, .Lfunc_end0-_Z29__device_stub__inclusive_scanPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 2112(%rsp,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
leaq 2112(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14inclusive_scanPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $512, %rbx # imm = 0x200
jne .LBB1_5
# %bb.6:
movl $-1, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14inclusive_scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14inclusive_scanPi,@object # @_Z14inclusive_scanPi
.section .rodata,"a",@progbits
.globl _Z14inclusive_scanPi
.p2align 3, 0x0
_Z14inclusive_scanPi:
.quad _Z29__device_stub__inclusive_scanPi
.size _Z14inclusive_scanPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[%d] = %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14inclusive_scanPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__inclusive_scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14inclusive_scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14inclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.EQ.OR P2, PT, R0.reuse, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x040fe40000742670 */
/*0080*/ ISETP.LT.U32.OR P1, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fe20000721470 */
/*0090*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*00c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*00d0*/ @!P2 LDS R7, [R0.X4+-0x4] ; /* 0xfffffc000007a984 */
/* 0x000e240000004800 */
/*00e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fc400078e0207 */
/*00f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0100*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.LT.U32.OR P2, PT, R0, 0x4, P0 ; /* 0x000000040000780c */
/* 0x000fca0000741470 */
/*0130*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0140*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0150*/ @!P1 LDS R5, [R0.X4+-0x8] ; /* 0xfffff80000059984 */
/* 0x000e240000004800 */
/*0160*/ @!P1 IMAD.IADD R5, R4, 0x1, R5 ; /* 0x0000000104059824 */
/* 0x001fe400078e0205 */
/*0170*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x8, P0 ; /* 0x000000080000780c */
/* 0x000fca0000721470 */
/*01b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*01c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*01d0*/ @!P2 LDS R7, [R0.X4+-0x10] ; /* 0xfffff0000007a984 */
/* 0x000e240000004800 */
/*01e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*01f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0200*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.LT.U32.OR P2, PT, R0, 0x10, P0 ; /* 0x000000100000780c */
/* 0x000fca0000741470 */
/*0230*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0240*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0250*/ @!P1 LDS R5, [R0.X4+-0x20] ; /* 0xffffe00000059984 */
/* 0x000e240000004800 */
/*0260*/ @!P1 IADD3 R5, R4, R5, RZ ; /* 0x0000000504059210 */
/* 0x001fe40007ffe0ff */
/*0270*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0280*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x20, P0 ; /* 0x000000200000780c */
/* 0x000fca0000721470 */
/*02b0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*02c0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*02d0*/ @!P2 LDS R7, [R0.X4+-0x40] ; /* 0xffffc0000007a984 */
/* 0x000e240000004800 */
/*02e0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*02f0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0300*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.LT.U32.OR P2, PT, R0, 0x40, P0 ; /* 0x000000400000780c */
/* 0x000fca0000741470 */
/*0330*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0340*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0350*/ @!P1 LDS R5, [R0.X4+-0x80] ; /* 0xffff800000059984 */
/* 0x000e240000004800 */
/*0360*/ @!P1 IMAD.IADD R5, R4, 0x1, R5 ; /* 0x0000000104059824 */
/* 0x001fe400078e0205 */
/*0370*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0380*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.LT.U32.OR P1, PT, R0, 0x80, P0 ; /* 0x000000800000780c */
/* 0x000fc40000721470 */
/*03b0*/ ISETP.LT.U32.OR P0, PT, R0, 0x100, P0 ; /* 0x000001000000780c */
/* 0x000fc60000701470 */
/*03c0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*03d0*/ @!P2 LDS R4, [R0.X4] ; /* 0x000000000004a984 */
/* 0x000fe80000004800 */
/*03e0*/ @!P2 LDS R7, [R0.X4+-0x100] ; /* 0xffff00000007a984 */
/* 0x000e240000004800 */
/*03f0*/ @!P2 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x000000010407a824 */
/* 0x001fe400078e0207 */
/*0400*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0410*/ @!P2 STS [R0.X4], R7 ; /* 0x000000070000a388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0440*/ @!P1 LDS R4, [R0.X4] ; /* 0x0000000000049984 */
/* 0x000fe80000004800 */
/*0450*/ @!P1 LDS R5, [R0.X4+-0x200] ; /* 0xfffe000000059984 */
/* 0x000e240000004800 */
/*0460*/ @!P1 IADD3 R5, R4, R5, RZ ; /* 0x0000000504059210 */
/* 0x001fc40007ffe0ff */
/*0470*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0480*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x000fe80000004800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04a0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*04b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*04c0*/ @!P0 LDS R4, [R0.X4] ; /* 0x0000000000048984 */
/* 0x000fe80000004800 */
/*04d0*/ @!P0 LDS R7, [R0.X4+-0x400] ; /* 0xfffc000000078984 */
/* 0x000e240000004800 */
/*04e0*/ @!P0 IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104078824 */
/* 0x001fc400078e0207 */
/*04f0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0500*/ @!P0 STS [R0.X4], R7 ; /* 0x0000000700008388 */
/* 0x000fe80000004800 */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0520*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*0530*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ BRA 0x550; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 8
.type _Z14inclusive_scanPi,@function
_Z14inclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s1, 1
s_cmpk_gt_u32 s1, 0xff
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_cmp_le_u32_e64 s0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_1
v_subrev_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
s_branch .LBB0_1
.LBB0_4:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14inclusive_scanPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14inclusive_scanPi, .Lfunc_end0-_Z14inclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14inclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14inclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070ce8_00000000-6_inclusive_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14inclusive_scanPiPi
.type _Z34__device_stub__Z14inclusive_scanPiPi, @function
_Z34__device_stub__Z14inclusive_scanPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14inclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14inclusive_scanPiPi, .-_Z34__device_stub__Z14inclusive_scanPiPi
.globl _Z14inclusive_scanPi
.type _Z14inclusive_scanPi, @function
_Z14inclusive_scanPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14inclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14inclusive_scanPi, .-_Z14inclusive_scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "out[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $4096, %rsp
.cfi_def_cfa_offset 4120
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
leaq 2080(%rsp), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 2080(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 2080(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $512, %rbx
jne .L14
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $-1, %eax
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z34__device_stub__Z14inclusive_scanPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14inclusive_scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14inclusive_scanPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "inclusive_scan.hip"
.globl _Z29__device_stub__inclusive_scanPi # -- Begin function _Z29__device_stub__inclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__inclusive_scanPi,@function
_Z29__device_stub__inclusive_scanPi: # @_Z29__device_stub__inclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14inclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__inclusive_scanPi, .Lfunc_end0-_Z29__device_stub__inclusive_scanPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 2112(%rsp,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
leaq 2112(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14inclusive_scanPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $512, %rbx # imm = 0x200
jne .LBB1_5
# %bb.6:
movl $-1, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14inclusive_scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14inclusive_scanPi,@object # @_Z14inclusive_scanPi
.section .rodata,"a",@progbits
.globl _Z14inclusive_scanPi
.p2align 3, 0x0
_Z14inclusive_scanPi:
.quad _Z29__device_stub__inclusive_scanPi
.size _Z14inclusive_scanPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[%d] = %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14inclusive_scanPi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__inclusive_scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14inclusive_scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
#include<stdio.h>
#include<iostream>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int pattern_length, int patHash, int* result, unsigned long long* runtime)
{
unsigned long long start_time = clock64();
int loc_in_input = threadIdx.x;
int input_hash,i;
for(input_hash=0,i=loc_in_input;i<pattern_length+loc_in_input;i++) {
input_hash=((input_hash << 8) + input[i]) % 997;
}
int j;
bool match = true;
if (input_hash == patHash) {
for(j=loc_in_input;j<loc_in_input+pattern_length;j++) {
//printf("Thread %d [%d] pattern char %c input char %c\n",threadIdx.x,j,pattern[j-loc_in_input],input[j]);
match &= (pattern[j-loc_in_input] == input[j]);
}
result[loc_in_input]= match?1:0;
}
unsigned long long stop_time = clock64();
runtime[loc_in_input] = (unsigned long long)(stop_time-start_time);
}
int main()
{
// host variables
char input[] = "HEABAL"; /*Sample Input*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int pattern_length = 2; /*Pattern Length*/
int input_length = 6; /*Input Length*/
// device variables
char* d_input;
char* d_pattern;
int* d_result;
unsigned long long* d_runtime;
// measure the execution time by using clock() api in the kernel as we did in Lab3
int runtime_size = input_length-pattern_length+1;
result = (int *) malloc((input_length-pattern_length+1)*sizeof(int));
runtime = (int *) malloc(runtime_size);
memset(runtime,0,input_length-pattern_length+1);
cudaMalloc((void **)&d_runtime,input_length-pattern_length+1);
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_length; i++)
{
patHash = (patHash * 256 + pattern[i]) % 997;
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&d_input,input_length);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&d_pattern,pattern_length);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&d_result,(input_length-pattern_length+1)*sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr,"Failer to allocate result (error code %s)!\n",cudaGetErrorString(err));
}
err = cudaMemcpy(d_pattern,pattern,pattern_length,cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy pattern (error code %s)!\n",cudaGetErrorString(err));
}
err = cudaMemcpy(d_input,input,input_length,cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy input (error code %s)!\n",cudaGetErrorString(err));
}
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocks = 1;
int threads = input_length-pattern_length+1;
findIfExistsCu<<<blocks,threads>>>(d_input,input_length,d_pattern,pattern_length,patHash,d_result,d_runtime);
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr,"Failed to launch kernel (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(result,d_result,(input_length-pattern_length+1)*sizeof(int),cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy result (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
cudaMemcpy(runtime, d_runtime, runtime_size, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
unsigned long long elapsed_time = 0;
for(int i = 0; i < input_length-pattern_length+1; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
printf("Total cycles: %d \n", (int)elapsed_time);
printf("Searching for a single pattern in a single string\n");
printf("Print at which position the pattern was found\n");
printf("Input string = %s\n",input);
printf("pattern=%s\n",pattern);
for (int i = 0;i < input_length-pattern_length+1;i++) {
printf("Pos:%d Result: %d\n",i,result[i]);
}
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
return 0;
} | .file "tmpxft_000ec200_00000000-6_cmpe297_hw2_rabin_karp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
.type _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy, @function
_Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14findIfExistsCuPciS_iiPiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy, .-_Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
.globl _Z14findIfExistsCuPciS_iiPiPy
.type _Z14findIfExistsCuPciS_iiPiPy, @function
_Z14findIfExistsCuPciS_iiPiPy:
.LFB3695:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14findIfExistsCuPciS_iiPiPy, .-_Z14findIfExistsCuPciS_iiPiPy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocated input (error code %s)!\n"
.align 8
.LC1:
.string "Failer to allocate result (error code %s)!\n"
.align 8
.LC2:
.string "Failed to copy pattern (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy input (error code %s)!\n"
.align 8
.LC4:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy result (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Total cycles: %d \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Searching for a single pattern in a single string\n"
.align 8
.LC8:
.string "Print at which position the pattern was found\n"
.section .rodata.str1.1
.LC9:
.string "Input string = %s\n"
.LC10:
.string "pattern=%s\n"
.LC11:
.string "Pos:%d Result: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1111573832, 65(%rsp)
movl $4997442, 68(%rsp)
movw $16961, 62(%rsp)
movb $0, 64(%rsp)
movl $20, %edi
call malloc@PLT
movq %rax, %rbp
movl $5, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movb $0, 4(%rax)
leaq 24(%rsp), %rdi
movl $5, %esi
call cudaMalloc@PLT
movzbl 62(%rsp), %r12d
movzbl 63(%rsp), %r13d
movq %rsp, %rdi
movl $6, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L14:
leaq 62(%rsp), %rsi
movl $1, %ecx
movl $2, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L15:
leaq 65(%rsp), %rsi
movl $1, %ecx
movl $6, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
.L16:
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $5, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movq %rbx, %rax
addq $20, %rbx
movl $0, %edx
.L20:
movslq (%rax), %rcx
cmpq %rcx, %rdx
cmovb %rcx, %rdx
addq $4, %rax
cmpq %rbx, %rax
jne .L20
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 65(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 62(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %r12
.L21:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L21
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L14
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L31:
movsbl %r12b, %eax
movl $997, %ecx
cltd
idivl %ecx
sall $8, %edx
movsbl %r13b, %r13d
leal (%rdx,%r13), %eax
cltd
idivl %ecx
movl %edx, %r8d
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 32(%rsp), %r9
movl $2, %ecx
movq 24(%rsp), %rdx
movl $6, %esi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z14findIfExistsCuPciS_iiPiPy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findIfExistsCuPciS_iiPiPy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
#include<stdio.h>
#include<iostream>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int pattern_length, int patHash, int* result, unsigned long long* runtime)
{
unsigned long long start_time = clock64();
int loc_in_input = threadIdx.x;
int input_hash,i;
for(input_hash=0,i=loc_in_input;i<pattern_length+loc_in_input;i++) {
input_hash=((input_hash << 8) + input[i]) % 997;
}
int j;
bool match = true;
if (input_hash == patHash) {
for(j=loc_in_input;j<loc_in_input+pattern_length;j++) {
//printf("Thread %d [%d] pattern char %c input char %c\n",threadIdx.x,j,pattern[j-loc_in_input],input[j]);
match &= (pattern[j-loc_in_input] == input[j]);
}
result[loc_in_input]= match?1:0;
}
unsigned long long stop_time = clock64();
runtime[loc_in_input] = (unsigned long long)(stop_time-start_time);
}
int main()
{
// host variables
char input[] = "HEABAL"; /*Sample Input*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int pattern_length = 2; /*Pattern Length*/
int input_length = 6; /*Input Length*/
// device variables
char* d_input;
char* d_pattern;
int* d_result;
unsigned long long* d_runtime;
// measure the execution time by using clock() api in the kernel as we did in Lab3
int runtime_size = input_length-pattern_length+1;
result = (int *) malloc((input_length-pattern_length+1)*sizeof(int));
runtime = (int *) malloc(runtime_size);
memset(runtime,0,input_length-pattern_length+1);
cudaMalloc((void **)&d_runtime,input_length-pattern_length+1);
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_length; i++)
{
patHash = (patHash * 256 + pattern[i]) % 997;
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&d_input,input_length);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&d_pattern,pattern_length);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&d_result,(input_length-pattern_length+1)*sizeof(int));
if (err != cudaSuccess) {
fprintf(stderr,"Failer to allocate result (error code %s)!\n",cudaGetErrorString(err));
}
err = cudaMemcpy(d_pattern,pattern,pattern_length,cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy pattern (error code %s)!\n",cudaGetErrorString(err));
}
err = cudaMemcpy(d_input,input,input_length,cudaMemcpyHostToDevice);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy input (error code %s)!\n",cudaGetErrorString(err));
}
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocks = 1;
int threads = input_length-pattern_length+1;
findIfExistsCu<<<blocks,threads>>>(d_input,input_length,d_pattern,pattern_length,patHash,d_result,d_runtime);
err = cudaGetLastError();
if (err != cudaSuccess) {
fprintf(stderr,"Failed to launch kernel (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(result,d_result,(input_length-pattern_length+1)*sizeof(int),cudaMemcpyDeviceToHost);
if (err != cudaSuccess) {
fprintf(stderr,"Failed to copy result (error code %s)!\n",cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
cudaMemcpy(runtime, d_runtime, runtime_size, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
unsigned long long elapsed_time = 0;
for(int i = 0; i < input_length-pattern_length+1; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
printf("Total cycles: %d \n", (int)elapsed_time);
printf("Searching for a single pattern in a single string\n");
printf("Print at which position the pattern was found\n");
printf("Input string = %s\n",input);
printf("pattern=%s\n",pattern);
for (int i = 0;i < input_length-pattern_length+1;i++) {
printf("Pos:%d Result: %d\n",i,result[i]);
}
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
return 0;
} | // CMPE297-6 HW2
// CUDA version Rabin-Karp
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int pattern_length, int patHash, int* result, unsigned long long* runtime)
{
unsigned long long start_time = clock64();
int loc_in_input = threadIdx.x;
int input_hash,i;
for(input_hash=0,i=loc_in_input;i<pattern_length+loc_in_input;i++) {
input_hash=((input_hash << 8) + input[i]) % 997;
}
int j;
bool match = true;
if (input_hash == patHash) {
for(j=loc_in_input;j<loc_in_input+pattern_length;j++) {
//printf("Thread %d [%d] pattern char %c input char %c\n",threadIdx.x,j,pattern[j-loc_in_input],input[j]);
match &= (pattern[j-loc_in_input] == input[j]);
}
result[loc_in_input]= match?1:0;
}
unsigned long long stop_time = clock64();
runtime[loc_in_input] = (unsigned long long)(stop_time-start_time);
}
int main()
{
// host variables
char input[] = "HEABAL"; /*Sample Input*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int pattern_length = 2; /*Pattern Length*/
int input_length = 6; /*Input Length*/
// device variables
char* d_input;
char* d_pattern;
int* d_result;
unsigned long long* d_runtime;
// measure the execution time by using clock() api in the kernel as we did in Lab3
int runtime_size = input_length-pattern_length+1;
result = (int *) malloc((input_length-pattern_length+1)*sizeof(int));
runtime = (int *) malloc(runtime_size);
memset(runtime,0,input_length-pattern_length+1);
hipMalloc((void **)&d_runtime,input_length-pattern_length+1);
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_length; i++)
{
patHash = (patHash * 256 + pattern[i]) % 997;
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **)&d_input,input_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_pattern,pattern_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_result,(input_length-pattern_length+1)*sizeof(int));
if (err != hipSuccess) {
fprintf(stderr,"Failer to allocate result (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_pattern,pattern,pattern_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy pattern (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_input,input,input_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy input (error code %s)!\n",hipGetErrorString(err));
}
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocks = 1;
int threads = input_length-pattern_length+1;
findIfExistsCu<<<blocks,threads>>>(d_input,input_length,d_pattern,pattern_length,patHash,d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr,"Failed to launch kernel (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(result,d_result,(input_length-pattern_length+1)*sizeof(int),hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy result (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
unsigned long long elapsed_time = 0;
for(int i = 0; i < input_length-pattern_length+1; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
printf("Total cycles: %d \n", (int)elapsed_time);
printf("Searching for a single pattern in a single string\n");
printf("Print at which position the pattern was found\n");
printf("Input string = %s\n",input);
printf("pattern=%s\n",pattern);
for (int i = 0;i < input_length-pattern_length+1;i++) {
printf("Pos:%d Result: %d\n",i,result[i]);
}
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int pattern_length, int patHash, int* result, unsigned long long* runtime)
{
unsigned long long start_time = clock64();
int loc_in_input = threadIdx.x;
int input_hash,i;
for(input_hash=0,i=loc_in_input;i<pattern_length+loc_in_input;i++) {
input_hash=((input_hash << 8) + input[i]) % 997;
}
int j;
bool match = true;
if (input_hash == patHash) {
for(j=loc_in_input;j<loc_in_input+pattern_length;j++) {
//printf("Thread %d [%d] pattern char %c input char %c\n",threadIdx.x,j,pattern[j-loc_in_input],input[j]);
match &= (pattern[j-loc_in_input] == input[j]);
}
result[loc_in_input]= match?1:0;
}
unsigned long long stop_time = clock64();
runtime[loc_in_input] = (unsigned long long)(stop_time-start_time);
}
int main()
{
// host variables
char input[] = "HEABAL"; /*Sample Input*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int pattern_length = 2; /*Pattern Length*/
int input_length = 6; /*Input Length*/
// device variables
char* d_input;
char* d_pattern;
int* d_result;
unsigned long long* d_runtime;
// measure the execution time by using clock() api in the kernel as we did in Lab3
int runtime_size = input_length-pattern_length+1;
result = (int *) malloc((input_length-pattern_length+1)*sizeof(int));
runtime = (int *) malloc(runtime_size);
memset(runtime,0,input_length-pattern_length+1);
hipMalloc((void **)&d_runtime,input_length-pattern_length+1);
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_length; i++)
{
patHash = (patHash * 256 + pattern[i]) % 997;
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **)&d_input,input_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_pattern,pattern_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_result,(input_length-pattern_length+1)*sizeof(int));
if (err != hipSuccess) {
fprintf(stderr,"Failer to allocate result (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_pattern,pattern,pattern_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy pattern (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_input,input,input_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy input (error code %s)!\n",hipGetErrorString(err));
}
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocks = 1;
int threads = input_length-pattern_length+1;
findIfExistsCu<<<blocks,threads>>>(d_input,input_length,d_pattern,pattern_length,patHash,d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr,"Failed to launch kernel (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(result,d_result,(input_length-pattern_length+1)*sizeof(int),hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy result (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
unsigned long long elapsed_time = 0;
for(int i = 0; i < input_length-pattern_length+1; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
printf("Total cycles: %d \n", (int)elapsed_time);
printf("Searching for a single pattern in a single string\n");
printf("Print at which position the pattern was found\n");
printf("Input string = %s\n",input);
printf("pattern=%s\n",pattern);
for (int i = 0;i < input_length-pattern_length+1;i++) {
printf("Pos:%d Result: %d\n",i,result[i]);
}
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14findIfExistsCuPciS_iiPiPy
.globl _Z14findIfExistsCuPciS_iiPiPy
.p2align 8
.type _Z14findIfExistsCuPciS_iiPiPy,@function
_Z14findIfExistsCuPciS_iiPiPy:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_getreg_b32 s3, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s2, v0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
v_mov_b32_e32 v1, v0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_load_i8 v5, v[5:6], off
v_cmp_ge_i32_e32 vcc_lo, v1, v4
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_lshl_add_u32 v3, v3, 8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v5, v3, 0x837765f1
v_add_nc_u32_e32 v5, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v6, 31, v5
v_ashrrev_i32_e32 v5, 9, v5
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v5, 0x3e5, v5
v_sub_nc_u32_e32 v3, v3, v5
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b32 s6, s[0:1], 0x1c
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 s6, v3
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v1, 1
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_10
s_load_b64 s[6:7], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s10, -1
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
s_waitcnt lgkmcnt(0)
global_load_u8 v7, v1, s[6:7]
global_load_u8 v5, v[5:6], off
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v2, v4
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s2, v7, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s10, s10, s2
s_add_u32 s6, s6, 1
s_addc_u32 s7, s7, 0
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 s2, s11, exec_lo
s_and_b32 s11, s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s11, s2, s11
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s9
v_cndmask_b32_e64 v1, 0, 1, s11
.LBB0_10:
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[4:5]
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[0:1], s[0:1], 0x28
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_u32 s2, s2, s3
s_subb_u32 s3, 0, 0
v_lshlrev_b32_e32 v2, 3, v0
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14findIfExistsCuPciS_iiPiPy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14findIfExistsCuPciS_iiPiPy, .Lfunc_end0-_Z14findIfExistsCuPciS_iiPiPy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14findIfExistsCuPciS_iiPiPy
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z14findIfExistsCuPciS_iiPiPy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int pattern_length, int patHash, int* result, unsigned long long* runtime)
{
unsigned long long start_time = clock64();
int loc_in_input = threadIdx.x;
int input_hash,i;
for(input_hash=0,i=loc_in_input;i<pattern_length+loc_in_input;i++) {
input_hash=((input_hash << 8) + input[i]) % 997;
}
int j;
bool match = true;
if (input_hash == patHash) {
for(j=loc_in_input;j<loc_in_input+pattern_length;j++) {
//printf("Thread %d [%d] pattern char %c input char %c\n",threadIdx.x,j,pattern[j-loc_in_input],input[j]);
match &= (pattern[j-loc_in_input] == input[j]);
}
result[loc_in_input]= match?1:0;
}
unsigned long long stop_time = clock64();
runtime[loc_in_input] = (unsigned long long)(stop_time-start_time);
}
int main()
{
// host variables
char input[] = "HEABAL"; /*Sample Input*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int pattern_length = 2; /*Pattern Length*/
int input_length = 6; /*Input Length*/
// device variables
char* d_input;
char* d_pattern;
int* d_result;
unsigned long long* d_runtime;
// measure the execution time by using clock() api in the kernel as we did in Lab3
int runtime_size = input_length-pattern_length+1;
result = (int *) malloc((input_length-pattern_length+1)*sizeof(int));
runtime = (int *) malloc(runtime_size);
memset(runtime,0,input_length-pattern_length+1);
hipMalloc((void **)&d_runtime,input_length-pattern_length+1);
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_length; i++)
{
patHash = (patHash * 256 + pattern[i]) % 997;
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
err = hipMalloc((void **)&d_input,input_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_pattern,pattern_length);
if (err != hipSuccess) {
fprintf(stderr,"Failed to allocated input (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&d_result,(input_length-pattern_length+1)*sizeof(int));
if (err != hipSuccess) {
fprintf(stderr,"Failer to allocate result (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_pattern,pattern,pattern_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy pattern (error code %s)!\n",hipGetErrorString(err));
}
err = hipMemcpy(d_input,input,input_length,hipMemcpyHostToDevice);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy input (error code %s)!\n",hipGetErrorString(err));
}
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocks = 1;
int threads = input_length-pattern_length+1;
findIfExistsCu<<<blocks,threads>>>(d_input,input_length,d_pattern,pattern_length,patHash,d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess) {
fprintf(stderr,"Failed to launch kernel (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(result,d_result,(input_length-pattern_length+1)*sizeof(int),hipMemcpyDeviceToHost);
if (err != hipSuccess) {
fprintf(stderr,"Failed to copy result (error code %s)!\n",hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
unsigned long long elapsed_time = 0;
for(int i = 0; i < input_length-pattern_length+1; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
printf("Total cycles: %d \n", (int)elapsed_time);
printf("Searching for a single pattern in a single string\n");
printf("Print at which position the pattern was found\n");
printf("Input string = %s\n",input);
printf("pattern=%s\n",pattern);
for (int i = 0;i < input_length-pattern_length+1;i++) {
printf("Pos:%d Result: %d\n",i,result[i]);
}
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
return 0;
} | .text
.file "cmpe297_hw2_rabin_karp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__findIfExistsCuPciS_iiPiPy # -- Begin function _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.p2align 4, 0x90
.type _Z29__device_stub__findIfExistsCuPciS_iiPiPy,@function
_Z29__device_stub__findIfExistsCuPciS_iiPiPy: # @_Z29__device_stub__findIfExistsCuPciS_iiPiPy
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14findIfExistsCuPciS_iiPiPy, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__findIfExistsCuPciS_iiPiPy, .Lfunc_end0-_Z29__device_stub__findIfExistsCuPciS_iiPiPy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1111573832, 13(%rsp) # imm = 0x42414548
movw $19521, 17(%rsp) # imm = 0x4C41
movb $0, 19(%rsp)
movw $16961, 10(%rsp) # imm = 0x4241
movb $0, 12(%rsp)
movl $20, %edi
callq malloc
movq %rax, %rbx
movl $5, %edi
callq malloc
movq %rax, %r14
movl $0, (%rax)
movb $0, 4(%rax)
leaq 32(%rsp), %rdi
movl $5, %esi
callq hipMalloc
xorl %eax, %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
shll $8, %r12d
movsbl 10(%rsp,%rax), %ecx
addl %r12d, %ecx
movslq %ecx, %r12
imulq $-2089327119, %r12, %rcx # imm = 0x837765F1
shrq $32, %rcx
addl %r12d, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $9, %ecx
addl %edx, %ecx
imull $997, %ecx, %ecx # imm = 0x3E5
subl %ecx, %r12d
incq %rax
cmpq $1, %rax
je .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
movl $6, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 48(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.6:
leaq 40(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
movq 48(%rsp), %rdi
leaq 10(%rsp), %rsi
movl $2, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
movq 56(%rsp), %rdi
leaq 13(%rsp), %rsi
movl $6, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
.LBB1_12:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 136(%rsp)
movl $6, 28(%rsp)
movq %rcx, 128(%rsp)
movl $2, 24(%rsp)
movl %r12d, 20(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z14findIfExistsCuPciS_iiPiPy, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 40(%rsp), %rsi
movl $20, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_17
# %bb.18:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movl $5, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq %rsi, %rcx
movslq (%r14,%rax,4), %rsi
cmpq %rsi, %rcx
cmovaq %rcx, %rsi
incq %rax
cmpq $5, %rax
jne .LBB1_19
# %bb.20:
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 13(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 10(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_21: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.11, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB1_21
# %bb.22:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 240
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_4
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_4
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findIfExistsCuPciS_iiPiPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findIfExistsCuPciS_iiPiPy,@object # @_Z14findIfExistsCuPciS_iiPiPy
.section .rodata,"a",@progbits
.globl _Z14findIfExistsCuPciS_iiPiPy
.p2align 3, 0x0
_Z14findIfExistsCuPciS_iiPiPy:
.quad _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.size _Z14findIfExistsCuPciS_iiPiPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocated input (error code %s)!\n"
.size .L.str, 44
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failer to allocate result (error code %s)!\n"
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to copy pattern (error code %s)!\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy input (error code %s)!\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy result (error code %s)!\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total cycles: %d \n"
.size .L.str.6, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Input string = %s\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "pattern=%s\n"
.size .L.str.10, 12
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Pos:%d Result: %d\n"
.size .L.str.11, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findIfExistsCuPciS_iiPiPy"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Searching for a single pattern in a single string"
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Print at which position the pattern was found"
.size .Lstr.1, 46
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findIfExistsCuPciS_iiPiPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ec200_00000000-6_cmpe297_hw2_rabin_karp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
.type _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy, @function
_Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14findIfExistsCuPciS_iiPiPy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy, .-_Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
.globl _Z14findIfExistsCuPciS_iiPiPy
.type _Z14findIfExistsCuPciS_iiPiPy, @function
_Z14findIfExistsCuPciS_iiPiPy:
.LFB3695:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14findIfExistsCuPciS_iiPiPy, .-_Z14findIfExistsCuPciS_iiPiPy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocated input (error code %s)!\n"
.align 8
.LC1:
.string "Failer to allocate result (error code %s)!\n"
.align 8
.LC2:
.string "Failed to copy pattern (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy input (error code %s)!\n"
.align 8
.LC4:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC5:
.string "Failed to copy result (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Total cycles: %d \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "Searching for a single pattern in a single string\n"
.align 8
.LC8:
.string "Print at which position the pattern was found\n"
.section .rodata.str1.1
.LC9:
.string "Input string = %s\n"
.LC10:
.string "pattern=%s\n"
.LC11:
.string "Pos:%d Result: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1111573832, 65(%rsp)
movl $4997442, 68(%rsp)
movw $16961, 62(%rsp)
movb $0, 64(%rsp)
movl $20, %edi
call malloc@PLT
movq %rax, %rbp
movl $5, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movb $0, 4(%rax)
leaq 24(%rsp), %rdi
movl $5, %esi
call cudaMalloc@PLT
movzbl 62(%rsp), %r12d
movzbl 63(%rsp), %r13d
movq %rsp, %rdi
movl $6, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 8(%rsp), %rdi
movl $2, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L14:
leaq 62(%rsp), %rsi
movl $1, %ecx
movl $2, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L15:
leaq 65(%rsp), %rsi
movl $1, %ecx
movl $6, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
.L16:
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L17:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $5, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movq %rbx, %rax
addq $20, %rbx
movl $0, %edx
.L20:
movslq (%rax), %rcx
cmpq %rcx, %rdx
cmovb %rcx, %rdx
addq $4, %rax
cmpq %rbx, %rax
jne .L20
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 65(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 62(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %r12
.L21:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L21
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L14
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L31:
movsbl %r12b, %eax
movl $997, %ecx
cltd
idivl %ecx
sall $8, %edx
movsbl %r13b, %r13d
leal (%rdx,%r13), %eax
cltd
idivl %ecx
movl %edx, %r8d
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 32(%rsp)
.cfi_def_cfa_offset 144
movq 32(%rsp), %r9
movl $2, %ecx
movq 24(%rsp), %rdx
movl $6, %esi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z14findIfExistsCuPciS_iiPiPyPciS_iiPiPy
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z14findIfExistsCuPciS_iiPiPy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findIfExistsCuPciS_iiPiPy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cmpe297_hw2_rabin_karp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__findIfExistsCuPciS_iiPiPy # -- Begin function _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.p2align 4, 0x90
.type _Z29__device_stub__findIfExistsCuPciS_iiPiPy,@function
_Z29__device_stub__findIfExistsCuPciS_iiPiPy: # @_Z29__device_stub__findIfExistsCuPciS_iiPiPy
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14findIfExistsCuPciS_iiPiPy, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__findIfExistsCuPciS_iiPiPy, .Lfunc_end0-_Z29__device_stub__findIfExistsCuPciS_iiPiPy
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $200, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1111573832, 13(%rsp) # imm = 0x42414548
movw $19521, 17(%rsp) # imm = 0x4C41
movb $0, 19(%rsp)
movw $16961, 10(%rsp) # imm = 0x4241
movb $0, 12(%rsp)
movl $20, %edi
callq malloc
movq %rax, %rbx
movl $5, %edi
callq malloc
movq %rax, %r14
movl $0, (%rax)
movb $0, 4(%rax)
leaq 32(%rsp), %rdi
movl $5, %esi
callq hipMalloc
xorl %eax, %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
shll $8, %r12d
movsbl 10(%rsp,%rax), %ecx
addl %r12d, %ecx
movslq %ecx, %r12
imulq $-2089327119, %r12, %rcx # imm = 0x837765F1
shrq $32, %rcx
addl %r12d, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $9, %ecx
addl %edx, %ecx
imull $997, %ecx, %ecx # imm = 0x3E5
subl %ecx, %r12d
incq %rax
cmpq $1, %rax
je .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
movl $6, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5:
leaq 48(%rsp), %rdi
movl $2, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.6:
leaq 40(%rsp), %rdi
movl $20, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_7
.LBB1_8:
movq 48(%rsp), %rdi
leaq 10(%rsp), %rsi
movl $2, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
.LBB1_10:
movq 56(%rsp), %rdi
leaq 13(%rsp), %rsi
movl $6, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
.LBB1_12:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 136(%rsp)
movl $6, 28(%rsp)
movq %rcx, 128(%rsp)
movl $2, 24(%rsp)
movl %r12d, 20(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z14findIfExistsCuPciS_iiPiPy, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_15
# %bb.16:
movq 40(%rsp), %rsi
movl $20, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_17
# %bb.18:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
movl $5, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %eax, %eax
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_19: # =>This Inner Loop Header: Depth=1
movq %rsi, %rcx
movslq (%r14,%rax,4), %rsi
cmpq %rsi, %rcx
cmovaq %rcx, %rsi
incq %rax
cmpq $5, %rax
jne .LBB1_19
# %bb.20:
movl $.L.str.6, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 13(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 10(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_21: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.11, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB1_21
# %bb.22:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 240
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.LBB1_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB1_4
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_4
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
.LBB1_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findIfExistsCuPciS_iiPiPy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findIfExistsCuPciS_iiPiPy,@object # @_Z14findIfExistsCuPciS_iiPiPy
.section .rodata,"a",@progbits
.globl _Z14findIfExistsCuPciS_iiPiPy
.p2align 3, 0x0
_Z14findIfExistsCuPciS_iiPiPy:
.quad _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.size _Z14findIfExistsCuPciS_iiPiPy, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocated input (error code %s)!\n"
.size .L.str, 44
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failer to allocate result (error code %s)!\n"
.size .L.str.1, 44
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to copy pattern (error code %s)!\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to copy input (error code %s)!\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy result (error code %s)!\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total cycles: %d \n"
.size .L.str.6, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Input string = %s\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "pattern=%s\n"
.size .L.str.10, 12
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Pos:%d Result: %d\n"
.size .L.str.11, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findIfExistsCuPciS_iiPiPy"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Searching for a single pattern in a single string"
.size .Lstr, 50
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Print at which position the pattern was found"
.size .Lstr.1, 46
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findIfExistsCuPciS_iiPiPy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findIfExistsCuPciS_iiPiPy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
cudaMallocHost((void**)&pinnedMemory, BYTES);
cudaMallocHost((void**)&pinnedOutput, BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pinnedMemory, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pinnedOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
cudaFreeHost(pinnedOutput);
cudaFreeHost(pinnedMemory);
free(hostPageable);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pageableInput, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(deviceOut, pageableOutput, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pageableOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z15manipulateInputPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fe20000011604 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0005 */
/*00a0*/ LEA R7, R2, -R7, 0x1 ; /* 0x8000000702077211 */
/* 0x004fca00078e08ff */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
cudaMallocHost((void**)&pinnedMemory, BYTES);
cudaMallocHost((void**)&pinnedOutput, BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pinnedMemory, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pinnedOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
cudaFreeHost(pinnedOutput);
cudaFreeHost(pinnedMemory);
free(hostPageable);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pageableInput, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(deviceOut, pageableOutput, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pageableOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} | .file "tmpxft_0012202c_00000000-6_module_4_jrenga2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15manipulateInputPjS_PjS_
.type _Z37__device_stub__Z15manipulateInputPjS_PjS_, @function
_Z37__device_stub__Z15manipulateInputPjS_PjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15manipulateInputPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z15manipulateInputPjS_PjS_, .-_Z37__device_stub__Z15manipulateInputPjS_PjS_
.globl _Z15manipulateInputPjS_
.type _Z15manipulateInputPjS_, @function
_Z15manipulateInputPjS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15manipulateInputPjS_, .-_Z15manipulateInputPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Final Output Value:\n"
.LC1:
.string "pageableOutput[%d] = %u\n"
.text
.globl _Z19test_pageableMemoryv
.type _Z19test_pageableMemoryv, @function
_Z19test_pageableMemoryv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
movl $0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $2049, %rax
jne .L12
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $8192, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8188(%rbx), %ecx
movl $2047, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movss 44(%rsp), %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19test_pageableMemoryv, .-_Z19test_pageableMemoryv
.section .rodata.str1.1
.LC2:
.string "pinnedOutput[%d] = %u\n"
.text
.globl _Z17test_pinnedMemoryv
.type _Z17test_pinnedMemoryv, @function
_Z17test_pinnedMemoryv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $8192, %esi
call cudaMallocHost@PLT
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %eax
.L20:
movl %eax, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $2049, %rax
jne .L20
movq (%rsp), %rax
movq (%rbx), %rdx
movq %rdx, (%rax)
movq 8184(%rbx), %rdx
movq %rdx, 8184(%rax)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
movq %rbx, %rsi
subq %rax, %rsi
addl $8192, %eax
shrl $3, %eax
movl %eax, %eax
movq %rax, %rcx
rep movsq
movq %rcx, %rax
movq 8(%rsp), %rdx
movq $0, (%rdx)
movq $0, 8184(%rdx)
leaq 8(%rdx), %rdi
andq $-8, %rdi
subq %rdi, %rdx
leal 8192(%rdx), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep stosq
movl $1, %ecx
movl $8192, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl 8188(%rax), %ecx
movl $2047, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq (%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 60(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z17test_pinnedMemoryv, .-_Z17test_pinnedMemoryv
.section .rodata.str1.1
.LC3:
.string "Results:\n"
.LC4:
.string "--------\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Pinned Memory Test Duration: %3f seconds\n"
.align 8
.LC6:
.string "Pageable Memory Test Duration: %3f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
call _Z17test_pinnedMemoryv
movss %xmm0, 8(%rsp)
call _Z17test_pinnedMemoryv
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15manipulateInputPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15manipulateInputPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
cudaMallocHost((void**)&pinnedMemory, BYTES);
cudaMallocHost((void**)&pinnedOutput, BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pinnedMemory, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pinnedOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
cudaFreeHost(pinnedOutput);
cudaFreeHost(pinnedMemory);
free(hostPageable);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
// Define the time container
float time;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
// Start the event timer:
cudaEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
cudaMalloc((void**)&deviceIn, BYTES);
cudaMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
cudaMemcpy(deviceIn, pageableInput, BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(deviceOut, pageableOutput, BYTES, cudaMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
cudaMemcpy(pageableOutput, deviceOut, BYTES, cudaMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
cudaFree(deviceIn);
cudaFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&time, startEvent, stopEvent);
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
hipHostMalloc((void**)&pinnedMemory, BYTES, hipHostMallocDefault);
hipHostMalloc((void**)&pinnedOutput, BYTES, hipHostMallocDefault);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pinnedMemory, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pinnedOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
hipHostFree(pinnedOutput);
hipHostFree(pinnedMemory);
free(hostPageable);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pageableInput, BYTES, hipMemcpyHostToDevice);
hipMemcpy(deviceOut, pageableOutput, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pageableOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
hipHostMalloc((void**)&pinnedMemory, BYTES, hipHostMallocDefault);
hipHostMalloc((void**)&pinnedOutput, BYTES, hipHostMallocDefault);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pinnedMemory, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pinnedOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
hipHostFree(pinnedOutput);
hipHostFree(pinnedMemory);
free(hostPageable);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pageableInput, BYTES, hipMemcpyHostToDevice);
hipMemcpy(deviceOut, pageableOutput, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pageableOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15manipulateInputPjS_
.globl _Z15manipulateInputPjS_
.p2align 8
.type _Z15manipulateInputPjS_,@function
_Z15manipulateInputPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshrrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15manipulateInputPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15manipulateInputPjS_, .Lfunc_end0-_Z15manipulateInputPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15manipulateInputPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15manipulateInputPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Assignment For Module 04:
//
//
// Author: Justin Renga
// NOTE: This implementation was inspired from the sample code from
// https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
// and, as such, there may be similarities between them.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCKSIZE 8
#define THREADCOUNT 256
// Define the array size as a constant value
#define ARRAY_SIZE 2048
#define BYTES ARRAY_SIZE * sizeof(unsigned int)
/// @brief The kernel function that will be used to test the functionality
/// of pinned and pageable memory.
__global__ void manipulateInput(unsigned int* input, unsigned int* output)
{
const unsigned int thread_index = (blockIdx.x * blockDim.x) + threadIdx.x;
output[thread_index] = (2 * input[thread_index]) - (thread_index/2);
}
/// @brief A function to test the usage of Pinned Memory.
float test_pinnedMemory()
{
// Define data containers
unsigned int* pinnedMemory;
unsigned int* pinnedOutput;
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* hostPageable;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Allocate Pageable Memory (on host)
hostPageable = (unsigned int*) malloc(BYTES);
// Allocate Pinned Memory (on host)
// Need to use cudaMallocHost() to establish pinned memory
hipHostMalloc((void**)&pinnedMemory, BYTES, hipHostMallocDefault);
hipHostMalloc((void**)&pinnedOutput, BYTES, hipHostMallocDefault);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
hostPageable[i] = (i + 1);
}
// Copy the pageable memory to the pinned memory
memcpy(pinnedMemory, hostPageable, BYTES);
memset(pinnedOutput, 0, BYTES);
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pinnedMemory, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pinnedOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pinnedOutput[%d] = %u\n", ARRAY_SIZE-1, pinnedOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
hipHostFree(pinnedOutput);
hipHostFree(pinnedMemory);
free(hostPageable);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @ brief A function to test the usage of Pageable Memory
float test_pageableMemory()
{
// Define data containers
unsigned int* deviceIn;
unsigned int* deviceOut;
unsigned int* pageableInput;
unsigned int* pageableOutput;
// Establish CUDA start/stop events
hipEvent_t startEvent;
hipEvent_t stopEvent;
// Define the time container
float time;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
// Start the event timer:
hipEventRecord(startEvent, 0);
// Begin the memory allocations
// Allocate Pageable Memory (on host)
pageableInput = (unsigned int*) malloc(BYTES);
pageableOutput = (unsigned int*) malloc(BYTES);
hipMalloc((void**)&deviceIn, BYTES);
hipMalloc((void**)&deviceOut, BYTES);
// Initialize the pageable memory
for (unsigned int i = 0; i < ARRAY_SIZE; ++i)
{
pageableInput[i] = (i + 1);
pageableOutput[i] = 0;
}
// Copy the pinned memory to the device
hipMemcpy(deviceIn, pageableInput, BYTES, hipMemcpyHostToDevice);
hipMemcpy(deviceOut, pageableOutput, BYTES, hipMemcpyHostToDevice);
// Execute the KERNEL
manipulateInput<<<BLOCKSIZE, THREADCOUNT>>>(deviceIn, deviceOut);
// Obtain the output
hipMemcpy(pageableOutput, deviceOut, BYTES, hipMemcpyDeviceToHost);
printf("Final Output Value:\n");
printf("pageableOutput[%d] = %u\n", ARRAY_SIZE-1, pageableOutput[ARRAY_SIZE-1]);
// Free Memory
hipFree(deviceIn);
hipFree(deviceOut);
free(pageableInput);
free(pageableOutput);
// Stop the event timer
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&time, startEvent, stopEvent);
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return time;
}
/// @brief The main function
///
/// @param [in] argc The number of arguments passed into the program
/// @param [in] argv The actual arguments passed into the program
///
/// @return EXIT_SUCCESS upon success
int main(int argc, const char* argv[])
{
// Create an array that will hold the durations of the tests
float duration[2];
// Execute and store the results of the two tests
duration[0] = test_pinnedMemory();
duration[1] = test_pinnedMemory();
// Output the results of the tests
printf("Results:\n");
printf("--------\n");
printf("Pinned Memory Test Duration: %3f seconds\n", duration[0]);
printf("Pageable Memory Test Duration: %3f seconds\n", duration[1]);
return EXIT_SUCCESS;
} | .text
.file "module_4_jrenga2.hip"
.globl _Z30__device_stub__manipulateInputPjS_ # -- Begin function _Z30__device_stub__manipulateInputPjS_
.p2align 4, 0x90
.type _Z30__device_stub__manipulateInputPjS_,@function
_Z30__device_stub__manipulateInputPjS_: # @_Z30__device_stub__manipulateInputPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__manipulateInputPjS_, .Lfunc_end0-_Z30__device_stub__manipulateInputPjS_
.cfi_endproc
# -- End function
.globl _Z17test_pinnedMemoryv # -- Begin function _Z17test_pinnedMemoryv
.p2align 4, 0x90
.type _Z17test_pinnedMemoryv,@function
_Z17test_pinnedMemoryv: # @_Z17test_pinnedMemoryv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %rax
movl %eax, (%rbx,%r14,4)
movq %rax, %r14
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
movq 40(%rsp), %r14
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movq %rbx, %rsi
callq memcpy@PLT
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
xorl %esi, %esi
callq memset@PLT
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rax
movl 8188(%rax), %edx
movl $.L.str.1, %edi
movl $2047, %esi # imm = 0x7FF
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17test_pinnedMemoryv, .Lfunc_end1-_Z17test_pinnedMemoryv
.cfi_endproc
# -- End function
.globl _Z19test_pageableMemoryv # -- Begin function _Z19test_pageableMemoryv
.p2align 4, 0x90
.type _Z19test_pageableMemoryv,@function
_Z19test_pageableMemoryv: # @_Z19test_pageableMemoryv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r15), %rax
movl %eax, (%rbx,%r15,4)
movq %rax, %r15
cmpq $2048, %rax # imm = 0x800
jne .LBB2_1
# %bb.2:
movq 24(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl 8188(%r14), %edx
movl $.L.str.2, %edi
movl $2047, %esi # imm = 0x7FF
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19test_pageableMemoryv, .Lfunc_end2-_Z19test_pageableMemoryv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z17test_pinnedMemoryv
movss %xmm0, (%rsp) # 4-byte Spill
callq _Z17test_pinnedMemoryv
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15manipulateInputPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15manipulateInputPjS_,@object # @_Z15manipulateInputPjS_
.section .rodata,"a",@progbits
.globl _Z15manipulateInputPjS_
.p2align 3, 0x0
_Z15manipulateInputPjS_:
.quad _Z30__device_stub__manipulateInputPjS_
.size _Z15manipulateInputPjS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "pinnedOutput[%d] = %u\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pageableOutput[%d] = %u\n"
.size .L.str.2, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pinned Memory Test Duration: %3f seconds\n"
.size .L.str.5, 44
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pageable Memory Test Duration: %3f seconds\n"
.size .L.str.6, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15manipulateInputPjS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Final Output Value:"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Results:"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "--------"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__manipulateInputPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15manipulateInputPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15manipulateInputPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fe20000011604 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0005 */
/*00a0*/ LEA R7, R2, -R7, 0x1 ; /* 0x8000000702077211 */
/* 0x004fca00078e08ff */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15manipulateInputPjS_
.globl _Z15manipulateInputPjS_
.p2align 8
.type _Z15manipulateInputPjS_,@function
_Z15manipulateInputPjS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshrrev_b32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v1
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15manipulateInputPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15manipulateInputPjS_, .Lfunc_end0-_Z15manipulateInputPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15manipulateInputPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15manipulateInputPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012202c_00000000-6_module_4_jrenga2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z15manipulateInputPjS_PjS_
.type _Z37__device_stub__Z15manipulateInputPjS_PjS_, @function
_Z37__device_stub__Z15manipulateInputPjS_PjS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15manipulateInputPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z15manipulateInputPjS_PjS_, .-_Z37__device_stub__Z15manipulateInputPjS_PjS_
.globl _Z15manipulateInputPjS_
.type _Z15manipulateInputPjS_, @function
_Z15manipulateInputPjS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15manipulateInputPjS_, .-_Z15manipulateInputPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Final Output Value:\n"
.LC1:
.string "pageableOutput[%d] = %u\n"
.text
.globl _Z19test_pageableMemoryv
.type _Z19test_pageableMemoryv, @function
_Z19test_pageableMemoryv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
movl $0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $2049, %rax
jne .L12
movl $1, %ecx
movl $8192, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $8192, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8188(%rbx), %ecx
movl $2047, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movss 44(%rsp), %xmm0
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19test_pageableMemoryv, .-_Z19test_pageableMemoryv
.section .rodata.str1.1
.LC2:
.string "pinnedOutput[%d] = %u\n"
.text
.globl _Z17test_pinnedMemoryv
.type _Z17test_pinnedMemoryv, @function
_Z17test_pinnedMemoryv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $8192, %esi
call cudaMallocHost@PLT
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMallocHost@PLT
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $1, %eax
.L20:
movl %eax, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $2049, %rax
jne .L20
movq (%rsp), %rax
movq (%rbx), %rdx
movq %rdx, (%rax)
movq 8184(%rbx), %rdx
movq %rdx, 8184(%rax)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
movq %rbx, %rsi
subq %rax, %rsi
addl $8192, %eax
shrl $3, %eax
movl %eax, %eax
movq %rax, %rcx
rep movsq
movq %rcx, %rax
movq 8(%rsp), %rdx
movq $0, (%rdx)
movq $0, 8184(%rdx)
leaq 8(%rdx), %rdi
andq $-8, %rdi
subq %rdi, %rdx
leal 8192(%rdx), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep stosq
movl $1, %ecx
movl $8192, %edx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
movl 8188(%rax), %ecx
movl $2047, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
movq (%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movss 60(%rsp), %xmm0
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z15manipulateInputPjS_PjS_
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z17test_pinnedMemoryv, .-_Z17test_pinnedMemoryv
.section .rodata.str1.1
.LC3:
.string "Results:\n"
.LC4:
.string "--------\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Pinned Memory Test Duration: %3f seconds\n"
.align 8
.LC6:
.string "Pageable Memory Test Duration: %3f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
call _Z17test_pinnedMemoryv
movss %xmm0, 8(%rsp)
call _Z17test_pinnedMemoryv
movss %xmm0, 12(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15manipulateInputPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15manipulateInputPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "module_4_jrenga2.hip"
.globl _Z30__device_stub__manipulateInputPjS_ # -- Begin function _Z30__device_stub__manipulateInputPjS_
.p2align 4, 0x90
.type _Z30__device_stub__manipulateInputPjS_,@function
_Z30__device_stub__manipulateInputPjS_: # @_Z30__device_stub__manipulateInputPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__manipulateInputPjS_, .Lfunc_end0-_Z30__device_stub__manipulateInputPjS_
.cfi_endproc
# -- End function
.globl _Z17test_pinnedMemoryv # -- Begin function _Z17test_pinnedMemoryv
.p2align 4, 0x90
.type _Z17test_pinnedMemoryv,@function
_Z17test_pinnedMemoryv: # @_Z17test_pinnedMemoryv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
leaq 40(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %rax
movl %eax, (%rbx,%r14,4)
movq %rax, %r14
cmpq $2048, %rax # imm = 0x800
jne .LBB1_1
# %bb.2:
movq 40(%rsp), %r14
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movq %rbx, %rsi
callq memcpy@PLT
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
xorl %esi, %esi
callq memset@PLT
movq 32(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movq 8(%rsp), %rax
movl 8188(%rax), %edx
movl $.L.str.1, %edi
movl $2047, %esi # imm = 0x7FF
xorl %eax, %eax
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17test_pinnedMemoryv, .Lfunc_end1-_Z17test_pinnedMemoryv
.cfi_endproc
# -- End function
.globl _Z19test_pageableMemoryv # -- Begin function _Z19test_pageableMemoryv
.p2align 4, 0x90
.type _Z19test_pageableMemoryv,@function
_Z19test_pageableMemoryv: # @_Z19test_pageableMemoryv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r15), %rax
movl %eax, (%rbx,%r15,4)
movq %rax, %r15
cmpq $2048, %rax # imm = 0x800
jne .LBB2_1
# %bb.2:
movq 24(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 248(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15manipulateInputPjS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movl 8188(%r14), %edx
movl $.L.str.2, %edi
movl $2047, %esi # imm = 0x7FF
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19test_pageableMemoryv, .Lfunc_end2-_Z19test_pageableMemoryv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z17test_pinnedMemoryv
movss %xmm0, (%rsp) # 4-byte Spill
callq _Z17test_pinnedMemoryv
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15manipulateInputPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15manipulateInputPjS_,@object # @_Z15manipulateInputPjS_
.section .rodata,"a",@progbits
.globl _Z15manipulateInputPjS_
.p2align 3, 0x0
_Z15manipulateInputPjS_:
.quad _Z30__device_stub__manipulateInputPjS_
.size _Z15manipulateInputPjS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "pinnedOutput[%d] = %u\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pageableOutput[%d] = %u\n"
.size .L.str.2, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pinned Memory Test Duration: %3f seconds\n"
.size .L.str.5, 44
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pageable Memory Test Duration: %3f seconds\n"
.size .L.str.6, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15manipulateInputPjS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Final Output Value:"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Results:"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "--------"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__manipulateInputPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15manipulateInputPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
cudaMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
cudaStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
cudaStreamCreate(&streams[i]);
cudaMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
cudaMemcpy(d_data,h_data,sizeof(float),cudaMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
cudaDeviceSynchronize();
// stop timer and report execution time
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z6kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ I2F.F64 R2, R8 ; /* 0x0000000800027312 */
/* 0x0000620000201c00 */
/*0080*/ BSSY B0, 0xc0 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*0090*/ MOV R0, 0xb0 ; /* 0x000000b000007802 */
/* 0x000fcc0000000f00 */
/*00a0*/ CALL.REL.NOINC 0x6c0 ; /* 0x0000061000007944 */
/* 0x003fea0003c00000 */
/*00b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00c0*/ DADD R4, R2, c[0x2][0x0] ; /* 0x0080000002047629 */
/* 0x000e620000000000 */
/*00d0*/ BSSY B0, 0x1f0 ; /* 0x0000011000007945 */
/* 0x000ff20003800000 */
/*00e0*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x002fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000f */
/*0100*/ ISETP.NE.AND P0, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fd800078e000e */
/*0120*/ @P0 BRA 0x1e0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0130*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e5c0003f0c200 */
/*0140*/ @P0 BRA 0x1d0 ; /* 0x0000008000000947 */
/* 0x002fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0160*/ LOP3.LUT R0, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03007812 */
/* 0x000fc800078ec0ff */
/*0170*/ ISETP.NE.OR P0, PT, R0, 0x7ff00000, P0 ; /* 0x7ff000000000780c */
/* 0x000fda0000705670 */
/*0180*/ @P0 BRA 0x1e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*01b0*/ SEL R5, RZ, 0x7ff00000, !P0 ; /* 0x7ff00000ff057807 */
/* 0x000fe20004000000 */
/*01c0*/ BRA 0x1e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*01d0*/ DADD R4, R2, c[0x2][0x0] ; /* 0x0080000002047629 */
/* 0x00028c0000000000 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0210*/ BSSY B0, 0x360 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0220*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0230*/ FSEL R5, R5, 1.875, P0 ; /* 0x3ff0000005057808 */
/* 0x004fe40000000000 */
/*0240*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x000fe40000000000 */
/*0250*/ MUFU.RSQ64H R3, R5 ; /* 0x0000000500037308 */
/* 0x002e620000001c00 */
/*0260*/ IADD3 R2, R5, -0x3500000, RZ ; /* 0xfcb0000005027810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R2, 0x7ca00000, PT ; /* 0x7ca000000200780c */
/* 0x000fe40003f06070 */
/*0280*/ DMUL R6, R2, R2 ; /* 0x0000000202067228 */
/* 0x002e4c0000000000 */
/*0290*/ DFMA R6, -R6, R4, 1 ; /* 0x3ff000000606742b */
/* 0x002e4c0000000104 */
/*02a0*/ DFMA R10, R6, R10, 0.5 ; /* 0x3fe00000060a742b */
/* 0x002fc8000000000a */
/*02b0*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x000e4c0000000000 */
/*02c0*/ DFMA R12, R10, R6, R2 ; /* 0x000000060a0c722b */
/* 0x003e0c0000000002 */
/*02d0*/ DMUL R14, R12, R4 ; /* 0x000000040c0e7228 */
/* 0x001e080000000000 */
/*02e0*/ IADD3 R11, R13, -0x100000, RZ ; /* 0xfff000000d0b7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0300*/ DFMA R16, R14, -R14, R4 ; /* 0x8000000e0e10722b */
/* 0x001e0c0000000004 */
/*0310*/ DFMA R6, R16, R10, R14 ; /* 0x0000000a1006722b */
/* 0x001062000000000e */
/*0320*/ @!P0 BRA 0x350 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0330*/ MOV R0, 0x350 ; /* 0x0000035000007802 */
/* 0x000fca0000000f00 */
/*0340*/ CALL.REL.NOINC 0x3f0 ; /* 0x000000a000007944 */
/* 0x003fea0003c00000 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x002e620000301000 */
/*0370*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fc800078e00ff */
/*0390*/ IMAD.WIDE R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fc800078e0203 */
/*03a0*/ IMAD R8, R5, c[0x0][0xc], R8 ; /* 0x0000030005087a24 */
/* 0x000fca00078e0208 */
/*03b0*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fe20003f06270 */
/*03c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0021d8000c101904 */
/*03d0*/ @!P0 BRA 0x70 ; /* 0xfffffc9000008947 */
/* 0x001fea000383ffff */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R2, -0x3400000, PT ; /* 0xfcc000000200780c */
/* 0x000fe20003f06070 */
/*0400*/ BSSY B1, 0x670 ; /* 0x0000026000017945 */
/* 0x000fe20003800000 */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000c */
/*0420*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0010 */
/*0430*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fce00078e0011 */
/*0440*/ @!P0 BRA 0x4d0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0450*/ DFMA.RM R2, R2, R10, R14 ; /* 0x0000000a0202722b */
/* 0x000e14000000400e */
/*0460*/ IADD3 R6, P0, R2, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x001fca0007f1e0ff */
/*0470*/ IMAD.X R7, RZ, RZ, R3, P0 ; /* 0x000000ffff077224 */
/* 0x000fcc00000e0603 */
/*0480*/ DFMA.RP R4, -R2, R6, R4 ; /* 0x000000060204722b */
/* 0x000e0c0000008104 */
/*0490*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*04a0*/ FSEL R2, R6, R2, P0 ; /* 0x0000000206027208 */
/* 0x001fe40000000000 */
/*04b0*/ FSEL R3, R7, R3, P0 ; /* 0x0000000307037208 */
/* 0x000fe20000000000 */
/*04c0*/ BRA 0x660 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*04d0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*04e0*/ @!P0 BRA 0x650 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*04f0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0500*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff028424 */
/* 0x000fe200078e00ff */
/*0510*/ @!P0 MOV R3, 0xfff80000 ; /* 0xfff8000000038802 */
/* 0x000fe20000000f00 */
/*0520*/ @!P0 BRA 0x660 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0540*/ @P0 BRA 0x650 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0550*/ DMUL R2, R4, 8.11296384146066816958e+31 ; /* 0x4690000004027828 */
/* 0x0000620000000000 */
/*0560*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0590*/ MUFU.RSQ64H R5, R3 ; /* 0x0000000300057308 */
/* 0x002e260000001c00 */
/*05a0*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x001e0c0000000000 */
/*05b0*/ DFMA R6, R2, -R6, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000806 */
/*05c0*/ DFMA R10, R6, R10, 0.5 ; /* 0x3fe00000060a742b */
/* 0x001fc8000000000a */
/*05d0*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x000e0c0000000000 */
/*05e0*/ DFMA R6, R10, R6, R4 ; /* 0x000000060a06722b */
/* 0x001e0c0000000004 */
/*05f0*/ DMUL R4, R2, R6 ; /* 0x0000000602047228 */
/* 0x0010480000000000 */
/*0600*/ IADD3 R7, R7, -0x100000, RZ ; /* 0xfff0000007077810 */
/* 0x001fe40007ffe0ff */
/*0610*/ DFMA R10, R4, -R4, R2 ; /* 0x80000004040a722b */
/* 0x002e0c0000000002 */
/*0620*/ DFMA R2, R6, R10, R4 ; /* 0x0000000a0602722b */
/* 0x001e140000000004 */
/*0630*/ IADD3 R3, R3, -0x3500000, RZ ; /* 0xfcb0000003037810 */
/* 0x001fe20007ffe0ff */
/*0640*/ BRA 0x660 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0650*/ DADD R2, R4, R4 ; /* 0x0000000004027229 */
/* 0x00004c0000000004 */
/*0660*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0670*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x002fe400078e0002 */
/*0680*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0690*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*06a0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0000 */
/*06b0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff94002007950 */
/* 0x000fea0003c3ffff */
/*06c0*/ MUFU.RCP64H R11, 1.785396575927734375 ; /* 0x3ffc90fc000b7908 */
/* 0x000e220000001800 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, -0x7f23cc9 ; /* 0xf80dc337ff047424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ffc90fc ; /* 0x3ffc90fcff057424 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff067424 */
/* 0x000fe400078e00ff */
/*0710*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff077424 */
/* 0x000fe400078e00ff */
/*0720*/ IMAD.SHL.U32 R9, R3, 0x2, RZ ; /* 0x0000000203097824 */
/* 0x000fe200078e00ff */
/*0730*/ DFMA R4, R10, -R4, 1 ; /* 0x3ff000000a04742b */
/* 0x001e080000000804 */
/*0740*/ ISETP.GT.U32.AND P0, PT, R9, -0x2000001, PT ; /* 0xfdffffff0900780c */
/* 0x000fe40003f04070 */
/*0750*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0760*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*0770*/ DMUL R4, R10, c[0x2][0x8] ; /* 0x008002000a047a28 */
/* 0x001e0c0000000000 */
/*0780*/ DFMA R4, R10, c[0x2][0x8], R4 ; /* 0x008002000a047a2b */
/* 0x001e0c0000000004 */
/*0790*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x001e080000000000 */
/*07a0*/ DADD R14, -R4, c[0x2][0x8] ; /* 0x00800200040e7629 */
/* 0x000e480000000100 */
/*07b0*/ DFMA R6, R12, R6, c[0x2][0x10] ; /* 0x008004000c06762b */
/* 0x001e080000000006 */
/*07c0*/ DADD R16, R14, R14 ; /* 0x000000000e107229 */
/* 0x002fc8000000000e */
/*07d0*/ DFMA R6, R12, R6, c[0x2][0x18] ; /* 0x008006000c06762b */
/* 0x001e080000000006 */
/*07e0*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x000fc80000000000 */
/*07f0*/ DFMA R6, R12, R6, c[0x2][0x20] ; /* 0x008008000c06762b */
/* 0x001e080000000006 */
/*0800*/ DFMA R20, -R4, c[0x2][0x8], R16 ; /* 0x0080020004147a2b */
/* 0x000e480000000110 */
/*0810*/ DFMA R6, R12, R6, c[0x2][0x28] ; /* 0x00800a000c06762b */
/* 0x001e080000000006 */
/*0820*/ DMUL R10, R10, R20 ; /* 0x000000140a0a7228 */
/* 0x002fc80000000000 */
/*0830*/ DFMA R6, R12, R6, c[0x2][0x30] ; /* 0x00800c000c06762b */
/* 0x001e080000000006 */
/*0840*/ DFMA R16, R4, R4, -R14 ; /* 0x000000040410722b */
/* 0x000fc8000000080e */
/*0850*/ DFMA R18, R12, R6, c[0x2][0x38] ; /* 0x00800e000c12762b */
/* 0x001e0c0000000006 */
/*0860*/ DFMA R6, R12, R18, c[0x2][0x40] ; /* 0x008010000c06762b */
/* 0x001e0c0000000012 */
/*0870*/ DADD R22, -R6, c[0x2][0x40] ; /* 0x0080100006167629 */
/* 0x001e0c0000000100 */
/*0880*/ DFMA R22, R12, R18, R22 ; /* 0x000000120c16722b */
/* 0x001e080000000016 */
/*0890*/ DMUL R12, R4, R14 ; /* 0x0000000e040c7228 */
/* 0x000e480000000000 */
/*08a0*/ DADD R18, RZ, R22 ; /* 0x00000000ff127229 */
/* 0x001e080000000016 */
/*08b0*/ DFMA R20, R4, R14, -R12 ; /* 0x0000000e0414722b */
/* 0x002e48000000080c */
/*08c0*/ DADD R18, R18, c[0x2][0x48] ; /* 0x0080120012127629 */
/* 0x001e080000000000 */
/*08d0*/ DFMA R22, R10, R14, R20 ; /* 0x0000000e0a16722b */
/* 0x0023e40000000014 */
/*08e0*/ IADD3 R21, R11, 0x100000, RZ ; /* 0x001000000b157810 */
/* 0x002fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000a */
/*0900*/ DADD R14, R6, R18 ; /* 0x00000000060e7229 */
/* 0x001e0a0000000012 */
/*0910*/ DFMA R20, R4, R20, R16 ; /* 0x000000140414722b */
/* 0x000e480000000010 */
/*0920*/ DMUL R16, R14, R12 ; /* 0x0000000c0e107228 */
/* 0x001e080000000000 */
/*0930*/ DFMA R20, R4, R20, R22 ; /* 0x000000140414722b */
/* 0x002fc80000000016 */
/*0940*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x000e48000000080e */
/*0950*/ DFMA R22, R14, R12, -R16 ; /* 0x0000000c0e16722b */
/* 0x001e080000000810 */
/*0960*/ DADD R6, R18, R6 ; /* 0x0000000012067229 */
/* 0x0023e40000000006 */
/*0970*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x002fe400078e00ff */
/*0980*/ DFMA R20, R14, R20, R22 ; /* 0x000000140e14722b */
/* 0x0010620000000016 */
/*0990*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe200078e00ff */
/*09a0*/ MOV R14, 0xfefa39ef ; /* 0xfefa39ef000e7802 */
/* 0x001fe20000000f00 */
/*09b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fe62e42 ; /* 0x3fe62e42ff0f7424 */
/* 0x000fc600078e00ff */
/*09c0*/ DFMA R20, R6, R12, R20 ; /* 0x0000000c0614722b */
/* 0x002e0c0000000014 */
/*09d0*/ DADD R12, R16, R20 ; /* 0x00000000100c7229 */
/* 0x001e0c0000000014 */
/*09e0*/ DADD R6, R4, R12 ; /* 0x0000000004067229 */
/* 0x001e08000000000c */
/*09f0*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0a00*/ DADD R4, R4, -R6 ; /* 0x0000000004047229 */
/* 0x001e080000000806 */
/*0a10*/ DADD R16, R20, R16 ; /* 0x0000000014107229 */
/* 0x002fc80000000010 */
/*0a20*/ DADD R4, R12, R4 ; /* 0x000000000c047229 */
/* 0x001e0c0000000004 */
/*0a30*/ DADD R4, R16, R4 ; /* 0x0000000010047229 */
/* 0x001e0c0000000004 */
/*0a40*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x001e0c0000000004 */
/*0a50*/ DADD R12, R6, R10 ; /* 0x00000000060c7229 */
/* 0x001e0c000000000a */
/*0a60*/ DFMA R4, R14, 2, R12 ; /* 0x400000000e04782b */
/* 0x001e08000000000c */
/*0a70*/ DADD R6, R6, -R12 ; /* 0x0000000006067229 */
/* 0x000e48000000080c */
/*0a80*/ DFMA R14, R14, -2, R4 ; /* 0xc00000000e0e782b */
/* 0x001e080000000004 */
/*0a90*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x0023e40000000006 */
/*0aa0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3b39803f ; /* 0x3b39803fff0a7424 */
/* 0x002fe400078e00ff */
/*0ab0*/ DADD R14, -R12, R14 ; /* 0x000000000c0e7229 */
/* 0x001e22000000010e */
/*0ac0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3c7abc9e ; /* 0x3c7abc9eff0b7424 */
/* 0x000fca00078e00ff */
/*0ad0*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x001064000000080e */
/*0ae0*/ LOP3.LUT R15, R3, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff030f7812 */
/* 0x001fe200078ec0ff */
/*0af0*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0002 */
/*0b00*/ DFMA R6, R10, 2, R6 ; /* 0x400000000a06782b */
/* 0x002e220000000006 */
/*0b10*/ SEL R15, R15, R3, P0 ; /* 0x000000030f0f7207 */
/* 0x000fca0000000000 */
/*0b20*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*0b30*/ DADD R12, R4, -R10 ; /* 0x00000000040c7229 */
/* 0x001e08000000080a */
/*0b40*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x000e480000000000 */
/*0b50*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x0011e4000000000c */
/*0b60*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe200078e00ff */
/*0b70*/ MOV R13, 0x3ff71547 ; /* 0x3ff71547000d7802 */
/* 0x000fe20000000f00 */
/*0b80*/ DFMA R10, R10, R14, -R4 ; /* 0x0000000e0a0a722b */
/* 0x002e0c0000000804 */
/*0b90*/ DFMA R6, R6, R14, R10 ; /* 0x0000000e0606722b */
/* 0x001e0c000000000a */
/*0ba0*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*0bb0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*0bc0*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*0bd0*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*0be0*/ DFMA R16, R14, c[0x2][0x50], R10 ; /* 0x008014000e107a2b */
/* 0x001e0c000000000a */
/*0bf0*/ DFMA R14, R14, c[0x2][0x58], R16 ; /* 0x008016000e0e7a2b */
/* 0x001e0c0000000010 */
/*0c00*/ DFMA R16, R14, R18, c[0x2][0x60] ; /* 0x008018000e10762b */
/* 0x001e0c0000000012 */
/*0c10*/ DFMA R16, R14, R16, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000010 */
/*0c20*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0c30*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0c40*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0c50*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0c60*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0c70*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0c80*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0c90*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0ca0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*0cb0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*0cc0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0cd0*/ @!P0 BRA 0xdb0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ce0*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*0cf0*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*0d00*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*0d10*/ FSEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000000000 */
/*0d20*/ @!P1 LEA.HI R9, R12, R12, RZ, 0x1 ; /* 0x0000000c0c099211 */
/* 0x000fe400078f08ff */
/*0d30*/ FSEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000000000 */
/*0d40*/ @!P1 SHF.R.S32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff099819 */
/* 0x000fc80000011409 */
/*0d50*/ @!P1 LEA R13, R9, R17, 0x14 ; /* 0x00000011090d9211 */
/* 0x000fe200078ea0ff */
/*0d60*/ @!P1 IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0c9824 */
/* 0x000fca00078e0a09 */
/*0d70*/ @!P1 LEA R17, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c119811 */
/* 0x000fe200078ea0ff */
/*0d80*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c9224 */
/* 0x000fe400078e0010 */
/*0d90*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fcc00078e00ff */
/*0da0*/ @!P1 DMUL R14, R12, R16 ; /* 0x000000100c0e9228 */
/* 0x0000540000000000 */
/*0db0*/ LOP3.LUT R9, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f097812 */
/* 0x002fe200078ec0ff */
/*0dc0*/ DADD R4, R4, -R10 ; /* 0x0000000004047229 */
/* 0x000e46000000080a */
/*0dd0*/ ISETP.NE.AND P0, PT, R9, 0x7ff00000, PT ; /* 0x7ff000000900780c */
/* 0x000fc60003f05270 */
/*0de0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e620000000004 */
/*0df0*/ ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; /* 0x000000ff0e00720c */
/* 0x000fda0004702270 */
/*0e00*/ @!P0 DFMA R14, R4, R14, R14 ; /* 0x0000000e040e822b */
/* 0x0022a4000000000e */
/*0e10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0000 */
/*0e20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0e30*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff1c004007950 */
/* 0x004fea0003c3ffff */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
cudaMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
cudaStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
cudaStreamCreate(&streams[i]);
cudaMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
cudaMemcpy(d_data,h_data,sizeof(float),cudaMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
cudaDeviceSynchronize();
// stop timer and report execution time
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000e2d2a_00000000-6_stream_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPfiPfi
.type _Z26__device_stub__Z6kernelPfiPfi, @function
_Z26__device_stub__Z6kernelPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPfiPfi, .-_Z26__device_stub__Z6kernelPfiPfi
.globl _Z6kernelPfi
.type _Z6kernelPfi, @function
_Z6kernelPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfi, .-_Z6kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "execution time (ms): %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0x3f800000, (%r12)
leaq 48(%rsp), %rbx
leaq 112(%rsp), %rbp
movq %rbp, %r13
jmp .L14
.L12:
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
addq $8, %rbx
addq $8, %rbp
cmpq %r13, %rbx
je .L19
.L14:
movq %rbx, %rdi
call cudaStreamCreate@PLT
movl $4194304, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq (%rbx), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 0(%rbp), %rdi
movl $1048576, %esi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L12
.L18:
movl $0, %esi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L13
.L19:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <cuda.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
cudaMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
cudaStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
cudaStreamCreate(&streams[i]);
cudaMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
cudaMemcpy(d_data,h_data,sizeof(float),cudaMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
cudaDeviceSynchronize();
// stop timer and report execution time
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
cudaDeviceReset();
return 0;
} | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
hipMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
hipStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
hipStreamCreate(&streams[i]);
hipMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
hipMemcpy(d_data,h_data,sizeof(float),hipMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
hipDeviceSynchronize();
// stop timer and report execution time
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
hipMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
hipStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
hipStreamCreate(&streams[i]);
hipMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
hipMemcpy(d_data,h_data,sizeof(float),hipMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
hipDeviceSynchronize();
// stop timer and report execution time
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfi
.globl _Z6kernelPfi
.p2align 8
.type _Z6kernelPfi,@function
_Z6kernelPfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s33, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s20, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s33, v1
s_cbranch_execz .LBB0_3
s_load_b32 s61, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0x3ff00000
s_mov_b32 s60, 0
s_mov_b32 s5, 0x3fe55555
s_mov_b32 s4, 0x55555555
s_mov_b32 s7, 0x3fba6564
s_mov_b32 s6, 0x968915a9
s_mov_b32 s9, 0x3fbdee67
s_mov_b32 s8, 0x4222de17
s_mov_b32 s11, 0x3fbe25e4
s_mov_b32 s10, 0x3abe935a
s_mov_b32 s13, 0x3fc110ef
s_mov_b32 s12, 0x47e6c9c2
s_mov_b32 s15, 0x3fc3b13b
s_mov_b32 s14, 0xcfa74449
s_mov_b32 s17, 0x3fc745d1
s_mov_b32 s16, 0x71bf3c30
s_mov_b32 s19, 0x3fcc71c7
s_mov_b32 s18, 0x1c7792ce
s_waitcnt lgkmcnt(0)
s_mul_i32 s61, s61, s20
s_mov_b32 s21, 0x3fd24924
s_mov_b32 s20, 0x924920da
s_mov_b32 s23, 0x3fd99999
s_mov_b32 s22, 0x9999999c
s_mov_b32 s25, 0x3fe62e42
s_mov_b32 s24, 0xfefa39ef
s_mov_b32 s27, 0x3c7abc9e
s_mov_b32 s26, 0x3b39803f
s_mov_b32 s29, 0xbfe55555
s_mov_b32 s31, 0x3c8543b0
s_mov_b32 s30, 0xd5df274d
s_mov_b32 s35, 0x3ff71547
s_mov_b32 s34, 0x652b82fe
s_mov_b32 s37, 0xbfe62e42
s_mov_b32 s39, 0xbc7abc9e
s_mov_b32 s41, 0x3e928af3
s_mov_b32 s40, 0xfca7ab0c
s_mov_b32 s43, 0x3e5ade15
s_mov_b32 s42, 0x6a5dcb37
s_mov_b32 s45, 0x3ec71dee
s_mov_b32 s44, 0x623fde64
s_mov_b32 s47, 0x3efa0199
s_mov_b32 s46, 0x7c89e6b0
s_mov_b32 s49, 0x3f2a01a0
s_mov_b32 s48, 0x14761f6e
s_mov_b32 s51, 0x3f56c16c
s_mov_b32 s50, 0x1852b7b0
s_mov_b32 s53, 0x3f811111
s_mov_b32 s52, 0x11122322
s_mov_b32 s55, 0x3fa55555
s_mov_b32 s54, 0x555502a1
s_mov_b32 s57, 0x3fc55555
s_mov_b32 s56, 0x55555511
s_mov_b32 s59, 0x3fe00000
s_mov_b32 s58, 11
.LBB0_2:
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_mov_b32 s28, s4
s_mov_b32 s36, s24
s_mov_b32 s38, s26
v_cndmask_b32_e32 v3, 0x400921f9, v0, vcc_lo
v_cndmask_b32_e64 v2, 0xf01b866e, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[4:5]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[10:11]
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
v_add_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[12:13], s[8:9], s[6:7]
v_add_f64 v[10:11], v[12:13], -v[10:11]
v_mul_f64 v[18:19], v[6:7], v[12:13]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[22:23], v[12:13], v[6:7], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[12:13], v[14:15]
v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
v_fma_f64 v[12:13], v[12:13], v[4:5], v[22:23]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[16:17], v[10:11]
v_add_f64 v[12:13], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[14:15], s[4:5]
v_add_f64 v[16:17], v[14:15], -v[16:17]
v_add_f64 v[18:19], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[20:21], s[28:29]
v_add_f64 v[10:11], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[18:19]
v_add_f64 v[14:15], v[14:15], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[10:11], s[30:31]
v_add_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[20:21], v[10:11]
v_add_f64 v[16:17], v[20:21], -v[14:15]
v_mul_f64 v[20:21], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[16:17]
v_fma_f64 v[16:17], v[12:13], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[16:17]
v_fma_f64 v[8:9], v[8:9], v[14:15], v[10:11]
v_frexp_exp_i32_f64_e32 v10, v[2:3]
v_ldexp_f64 v[2:3], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[20:21], v[8:9]
v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[10:11], v10
v_add_f64 v[12:13], v[2:3], v[6:7]
v_add_f64 v[14:15], v[6:7], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[16:17], v[10:11], s[24:25]
v_add_f64 v[2:3], v[12:13], -v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_fma_f64 v[14:15], v[10:11], s[24:25], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[6:7], -v[2:3]
v_add_f64 v[4:5], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[10:11], s[26:27], v[14:15]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], v[6:7]
v_add_f64 v[8:9], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[4:5], -v[16:17]
v_add_f64 v[10:11], v[4:5], v[8:9]
v_add_f64 v[12:13], v[8:9], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[6:7], -v[16:17]
v_add_f64 v[14:15], v[10:11], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[12:13]
v_add_f64 v[18:19], v[10:11], -v[14:15]
v_add_f64 v[8:9], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[6:7], v[2:3]
v_add_f64 v[4:5], v[4:5], -v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[8:9], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[12:13], v[4:5]
v_add_f64 v[12:13], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[10:11], v[4:5]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[14:15], -v[10:11]
v_add_f64 v[2:3], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
v_cvt_f64_i32_e32 v[4:5], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[14:15], v[2:3]
v_add_f64 v[8:9], v[6:7], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[10:11], v[6:7], v[4:5]
v_add_f64 v[2:3], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], v[6:7], -v[10:11]
v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
v_fma_f64 v[2:3], v[4:5], v[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], v[2:3]
v_dual_cndmask_b32 v7, v5, v11 :: v_dual_cndmask_b32 v6, v4, v10
v_add_f64 v[4:5], v[4:5], -v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[8:9], v[6:7], s[34:35]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[6:7]|
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[6:7]
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_rndne_f64_e32 v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[8:9], s[36:37], v[6:7]
v_cvt_i32_f64_e32 v16, v[8:9]
v_fma_f64 v[12:13], v[8:9], s[38:39], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], s[42:43], s[40:41]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[44:45]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[46:47]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[48:49]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[50:51]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[52:53]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[54:55]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[56:57]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[58:59]
v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[12:13], v[14:15], 1.0
v_ldexp_f64 v[8:9], v[8:9], v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0x7ff00000, v9, s0
v_cndmask_b32_e64 v5, 0, v4, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0, v8, vcc_lo
v_fma_f64 v[2:3], v[4:5], v[2:3], v[4:5]
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
v_cmp_gt_f64_e64 s0, 0x10000000, |v[2:3]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, 1, s0
v_lshlrev_b32_e32 v4, 8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[2:3], |v[2:3]|, v4
v_rsq_f64_e32 v[4:5], v[2:3]
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[6:7], v[2:3], v[4:5]
v_mul_f64 v[4:5], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 0.5
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[6:7], v[8:9], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[6:7], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffff80, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s61, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s33, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s60, vcc_lo, s60
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s60
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 62
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfi, .Lfunc_end0-_Z6kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 64
.sgpr_spill_count: 0
.symbol: _Z6kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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