system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001730a2_00000000-6_mat_vec_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6matvecPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matvecPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
.globl _Z6matvecPfS_S_i
.type _Z6matvecPfS_S_i, @function
_Z6matvecPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matvecPfS_S_i, .-_Z6matvecPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "y[0]=%8.4e and y[1]=%8.4e\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Number of elements in array %8.0f\n"
.section .rodata.str1.1
.LC8:
.string "Elapsed time: %8.8f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $400000000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 24(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L12
movl $-1, %ecx
movl $0, %edx
movl $0, %eax
movss .LC1(%rip), %xmm0
movss .LC2(%rip), %xmm3
movaps %xmm3, %xmm2
movss .LC3(%rip), %xmm1
jmp .L15
.L13:
movq 24(%rsp), %rsi
movss %xmm2, 4(%rsi,%rdx)
movq 8(%rsp), %rsi
movss %xmm1, (%rsi,%rax,4)
movq 16(%rsp), %rsi
movl $0x00000000, (%rsi,%rax,4)
addq $1, %rax
addq $40004, %rdx
addl $10001, %ecx
.L15:
movq 24(%rsp), %rsi
movss %xmm0, (%rsi,%rdx)
testl %eax, %eax
je .L13
movl %ecx, %esi
movq 24(%rsp), %rdi
movss %xmm3, (%rdi,%rsi,4)
cmpl $9998, %eax
jbe .L13
movl %eax, %eax
movq 8(%rsp), %rdx
movl $0x3f800000, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax,4)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6matvecPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matvecPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1082130432
.align 4
.LC2:
.long -1082130432
.align 4
.LC3:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1086556160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_vec_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matvecPfS_S_i # -- Begin function _Z21__device_stub__matvecPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matvecPfS_S_i,@function
_Z21__device_stub__matvecPfS_S_i: # @_Z21__device_stub__matvecPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matvecPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matvecPfS_S_i, .Lfunc_end0-_Z21__device_stub__matvecPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x40c3880000000000 # double 1.0E+4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4294967295, %r14d # imm = 0xFFFFFFFF
callq clock
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %r15
xorl %r12d, %r12d
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rax
movq (%rsp), %rcx
leaq 4(%r15), %rdx
movl $4294967295, %esi # imm = 0xFFFFFFFF
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $-1082130432, (%rdx) # imm = 0xBF800000
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $1065353216, (%rax,%r12) # imm = 0x3F800000
movl $0, (%rcx,%r12)
addq $4, %r12
addq $10001, %rsi # imm = 0x2711
addq $40004, %rdx # imm = 0x9C44
cmpq $40000, %r12 # imm = 0x9C40
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1082130432, -4(%rdx) # imm = 0x40800000
testq %r12, %r12
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %esi, %edi
movl $-1082130432, (%r15,%rdi,4) # imm = 0xBF800000
cmpq $39996, %r12 # imm = 0x9C3C
jne .LBB1_3
jmp .LBB1_4
.LBB1_5:
leaq 11(%r14), %rdi
addq $1025, %r14 # imm = 0x401
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 28(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matvecPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq (%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matvecPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matvecPfS_S_i,@object # @_Z6matvecPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6matvecPfS_S_i
.p2align 3, 0x0
_Z6matvecPfS_S_i:
.quad _Z21__device_stub__matvecPfS_S_i
.size _Z6matvecPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "y[0]=%8.4e and y[1]=%8.4e\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of elements in array %8.0f\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time: %8.8f seconds\n"
.size .L.str.2, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matvecPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matvecPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matvecPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
cudaProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
cudaMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
cudaDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
cudaFree(sin_arr);
cudaFree(cos_arr);
cudaFree(tan_arr);
cudaProfilerStop();
return 0;
} | code for sm_80
Function : _Z17calculator_kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F.F64 R2, R11 ; /* 0x0000000b00027312 */
/* 0x000e220000201c00 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ BSSY B0, 0x540 ; /* 0x000004a000007945 */
/* 0x000fe20003800000 */
/*00a0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e0c0000000000 */
/*00b0*/ F2F.F32.F64 R8, R2 ; /* 0x0000000200087310 */
/* 0x001e240000301000 */
/*00c0*/ FMUL R0, R8.reuse, 0.63661974668502807617 ; /* 0x3f22f98308007820 */
/* 0x041fe20000400000 */
/*00d0*/ FSETP.GE.AND P0, PT, |R8|, 105615, PT ; /* 0x47ce47800800780b */
/* 0x000fca0003f06200 */
/*00e0*/ F2I.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e300000203100 */
/*00f0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201400 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0000 */
/*0110*/ FFMA R4, R5, -1.5707962512969970703, R8 ; /* 0xbfc90fda05047823 */
/* 0x001fc80000000008 */
/*0120*/ FFMA R4, R5, -7.5497894158615963534e-08, R4 ; /* 0xb3a2216805047823 */
/* 0x000fc80000000004 */
/*0130*/ FFMA R10, R5, -5.3903029534742383927e-15, R4 ; /* 0xa7c234c5050a7823 */
/* 0x000fc80000000004 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000a */
/*0150*/ @!P0 BRA 0x530 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0160*/ FSETP.NEU.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fda0003f2d200 */
/*0170*/ @!P1 BRA 0x510 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.SHL.U32 R2, R8, 0x100, RZ ; /* 0x0000010008027824 */
/* 0x000fe200078e00ff */
/*0190*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01d0*/ LOP3.LUT R7, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000002077812 */
/* 0x000fe200078efcff */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0001 */
/*01f0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0240*/ ISETP.NE.AND P1, PT, R12, 0x6, PT ; /* 0x000000060c00780c */
/* 0x000fe20003f25270 */
/*0250*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0260*/ IMAD.WIDE.U32 R2, R2, R7, RZ ; /* 0x0000000702027225 */
/* 0x004fca00078e00ff */
/*0270*/ IADD3 R13, P2, R2, R6, RZ ; /* 0x00000006020d7210 */
/* 0x000fc80007f5e0ff */
/*0280*/ IADD3.X R6, R3, UR4, RZ, P2, !PT ; /* 0x0000000403067c10 */
/* 0x000fe200097fe4ff */
/*0290*/ STL [R0], R13 ; /* 0x0000000d00007387 */
/* 0x0001e40000100800 */
/*02a0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*02b0*/ @P1 BRA 0x1f0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*02c0*/ SHF.R.U32.HI R0, RZ, 0x17, R8 ; /* 0x00000017ff007819 */
/* 0x000fe20000011608 */
/*02d0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e60000100800 */
/*02e0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*02f0*/ IADD3 R0, R0, -0x80, RZ ; /* 0xffffff8000007810 */
/* 0x000fc80007ffe0ff */
/*0300*/ LOP3.LUT P1, R7, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00077812 */
/* 0x000fe4000782c0ff */
/*0310*/ SHF.R.U32.HI R0, RZ, 0x5, R0 ; /* 0x00000005ff007819 */
/* 0x000fc80000011600 */
/*0320*/ IADD3 R2, -R0.reuse, 0x4, RZ ; /* 0x0000000400027810 */
/* 0x040fe40007ffe1ff */
/*0330*/ IADD3 R0, -R0, 0x6, RZ ; /* 0x0000000600007810 */
/* 0x000fca0007ffe1ff */
/*0340*/ @P1 IMAD R13, R2, 0x4, R1.reuse ; /* 0x00000004020d1824 */
/* 0x100fe400078e0201 */
/*0350*/ IMAD R12, R0, 0x4, R1 ; /* 0x00000004000c7824 */
/* 0x000fc600078e0201 */
/*0360*/ @P1 LDL R5, [R13] ; /* 0x000000000d051983 */
/* 0x000ea80000100800 */
/*0370*/ LDL R0, [R12] ; /* 0x000000000c007983 */
/* 0x000ee80000100800 */
/*0380*/ LDL R3, [R12+-0x4] ; /* 0xfffffc000c037983 */
/* 0x000f220000100800 */
/*0390*/ @P1 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007021810 */
/* 0x000fc80007ffe1ff */
/*03a0*/ @P1 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff041219 */
/* 0x084fe40000011605 */
/*03b0*/ @P1 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700051219 */
/* 0x088fe400000006ff */
/*03c0*/ @P1 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff021219 */
/* 0x010fe40000011603 */
/*03d0*/ @P1 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703071219 */
/* 0x000fc600000006ff */
/*03e0*/ @P1 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102001824 */
/* 0x000fe400078e0205 */
/*03f0*/ @P1 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104031824 */
/* 0x000fe200078e0207 */
/*0400*/ LOP3.LUT P1, R6, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008067812 */
/* 0x001fc6000782c0ff */
/*0410*/ IMAD.SHL.U32 R4, R3.reuse, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x040fe200078e00ff */
/*0420*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0430*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*0440*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f45270 */
/*0450*/ LEA.HI R0, R0, R7, RZ, 0x2 ; /* 0x0000000700007211 */
/* 0x000fd600078f10ff */
/*0460*/ @P2 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff052212 */
/* 0x000fe400078e33ff */
/*0470*/ @P2 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff042212 */
/* 0x000fe400078e33ff */
/*0480*/ @P2 LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006062812 */
/* 0x000fe400078e3cff */
/*0490*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e240000301c00 */
/*04a0*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f45270 */
/*04b0*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a00 */
/*04c0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0006 */
/*04d0*/ DMUL R2, R2, c[0x2][0x8] ; /* 0x0080020002027a28 */
/* 0x001e140000000000 */
/*04e0*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*04f0*/ FSEL R6, R2, -R2, !P2 ; /* 0x8000000202067208 */
/* 0x001fe20005000000 */
/*0500*/ BRA 0x530 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0510*/ FMUL R6, RZ, R8 ; /* 0x00000008ff067220 */
/* 0x000fe40000400000 */
/*0520*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P2, RZ, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x040fe2000784c0ff */
/*0550*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff0c7424 */
/* 0x000fe200078e00ff */
/*0560*/ LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fe2000782c0ff */
/*0570*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x000fe20000400000 */
/*0580*/ BSSY B0, 0xa90 ; /* 0x0000050000007945 */
/* 0x000fe20003800000 */
/*0590*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0d7424 */
/* 0x000fe200078e00ff */
/*05a0*/ FSEL R3, R12, 0.041666727513074874878, !P2 ; /* 0x3d2aaabb0c037808 */
/* 0x000fe20005000000 */
/*05b0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fe200078e00ff */
/*05c0*/ SHF.R.S32.HI R14, RZ, 0x1f, R11 ; /* 0x0000001fff0e7819 */
/* 0x000fe2000001140b */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*05e0*/ FSEL R5, -R13, -0.4999999701976776123, !P2 ; /* 0xbeffffff0d057808 */
/* 0x000fc60005000100 */
/*05f0*/ @P2 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff042424 */
/* 0x000fc800078e00ff */
/*0600*/ @P2 FFMA R2, R7.reuse, R4, -0.0013887860113754868507 ; /* 0xbab607ed07022423 */
/* 0x040fe20000000004 */
/*0610*/ FSEL R4, R6, 1, !P2 ; /* 0x3f80000006047808 */
/* 0x000fe20005000000 */
/*0620*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0630*/ FFMA R2, R7.reuse, R2, R3 ; /* 0x0000000207027223 */
/* 0x040fe40000000003 */
/*0640*/ FFMA R3, R4, R7, RZ ; /* 0x0000000704037223 */
/* 0x000fe400000000ff */
/*0650*/ FFMA R2, R7, R2, R5 ; /* 0x0000000207027223 */
/* 0x000fc80000000005 */
/*0660*/ FFMA R5, R2, R3, R4 ; /* 0x0000000302057223 */
/* 0x000fe40000000004 */
/*0670*/ IMAD.WIDE R2, R11, R0, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fc800078e0200 */
/*0680*/ @P1 FFMA R5, R5, -1, RZ ; /* 0xbf80000005051823 */
/* 0x000fe400000000ff */
/*0690*/ IMAD.MOV.U32 R0, RZ, RZ, R9 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0009 */
/*06a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*06b0*/ @!P0 BRA 0xa80 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.NEU.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fda0003f2d200 */
/*06d0*/ @!P1 BRA 0xa60 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*06e0*/ SHF.R.U32.HI R0, RZ, 0x17, R8 ; /* 0x00000017ff007819 */
/* 0x000fe20000011608 */
/*06f0*/ IMAD.SHL.U32 R2, R8, 0x100, RZ ; /* 0x0000010008027824 */
/* 0x001fe200078e00ff */
/*0700*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0710*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0720*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*0730*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*0740*/ LOP3.LUT R17, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000002117812 */
/* 0x000fe400078efcff */
/*0750*/ IADD3 R16, R0, -0x80, RZ ; /* 0xffffff8000107810 */
/* 0x000fe20007ffe0ff */
/*0760*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*0770*/ SHF.R.U32.HI R18, RZ, 0x5, R16 ; /* 0x00000005ff127819 */
/* 0x000fe40000011610 */
/*0780*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0790*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*07a0*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*07b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*07d0*/ ISETP.NE.AND P1, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f25270 */
/*07e0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*07f0*/ IMAD.WIDE.U32 R2, R2, R17, RZ ; /* 0x0000001102027225 */
/* 0x004fca00078e00ff */
/*0800*/ IADD3 R15, P2, R2, R6, RZ ; /* 0x00000006020f7210 */
/* 0x000fc80007f5e0ff */
/*0810*/ IADD3.X R6, R3, UR4, RZ, P2, !PT ; /* 0x0000000403067c10 */
/* 0x000fe200097fe4ff */
/*0820*/ STL [R0], R15 ; /* 0x0000000f00007387 */
/* 0x0001e40000100800 */
/*0830*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0840*/ @P1 BRA 0x780 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0850*/ LOP3.LUT P1, R16, R16, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f10107812 */
/* 0x000fe2000782c0ff */
/*0860*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*0870*/ IADD3 R0, -R18.reuse, 0x4, RZ ; /* 0x0000000412007810 */
/* 0x040fe40007ffe1ff */
/*0880*/ IADD3 R18, -R18, 0x6, RZ ; /* 0x0000000612127810 */
/* 0x000fca0007ffe1ff */
/*0890*/ IMAD R18, R18, 0x4, R1 ; /* 0x0000000412127824 */
/* 0x000fc800078e0201 */
/*08a0*/ @P1 IMAD R15, R0, 0x4, R1 ; /* 0x00000004000f1824 */
/* 0x000fe200078e0201 */
/*08b0*/ LDL R3, [R18+-0x4] ; /* 0xfffffc0012037983 */
/* 0x000ea80000100800 */
/*08c0*/ @P1 LDL R2, [R15] ; /* 0x000000000f021983 */
/* 0x000ee80000100800 */
/*08d0*/ LDL R0, [R18] ; /* 0x0000000012007983 */
/* 0x000f220000100800 */
/*08e0*/ @P1 IADD3 R7, -R16, 0x20, RZ ; /* 0x0000002010071810 */
/* 0x000fc80007ffe1ff */
/*08f0*/ @P1 SHF.R.U32.HI R4, RZ, R7.reuse, R2 ; /* 0x00000007ff041219 */
/* 0x088fe40000011602 */
/*0900*/ @P1 SHF.R.U32.HI R2, RZ, R7, R3 ; /* 0x00000007ff021219 */
/* 0x004fe40000011603 */
/*0910*/ @P1 SHF.L.U32 R5, R0, R16.reuse, RZ ; /* 0x0000001000051219 */
/* 0x090fe400000006ff */
/*0920*/ @P1 SHF.L.U32 R7, R3, R16, RZ ; /* 0x0000001003071219 */
/* 0x000fc600000006ff */
/*0930*/ @P1 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102001824 */
/* 0x000fe400078e0205 */
/*0940*/ @P1 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104031824 */
/* 0x000fca00078e0207 */
/*0950*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0960*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*0970*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f45270 */
/*0980*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fd800078e00ff */
/*0990*/ @P2 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff052212 */
/* 0x000fe400078e33ff */
/*09a0*/ @P2 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff042212 */
/* 0x000fc800078e33ff */
/*09b0*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e620000301c00 */
/*09c0*/ LOP3.LUT P1, R6, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008067812 */
/* 0x001fe2000782c0ff */
/*09d0*/ DMUL R2, R2, c[0x2][0x8] ; /* 0x0080020002027a28 */
/* 0x002e060000000000 */
/*09e0*/ @P2 LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006062812 */
/* 0x000fe400078e3cff */
/*09f0*/ LEA.HI R0, R0, R7, RZ, 0x2 ; /* 0x0000000700007211 */
/* 0x000fca00078f10ff */
/*0a00*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e220000301000 */
/*0a10*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f45270 */
/*0a20*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a00 */
/*0a30*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0006 */
/*0a40*/ FSEL R6, R2, -R2, !P2 ; /* 0x8000000202067208 */
/* 0x001fe20005000000 */
/*0a50*/ BRA 0xa80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a60*/ FMUL R6, RZ, R8 ; /* 0x00000008ff067220 */
/* 0x000fe40000400000 */
/*0a70*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a90*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ FMUL R2, R6, R6 ; /* 0x0000000606027220 */
/* 0x001fe20000400000 */
/*0ab0*/ BSSY B0, 0xfc0 ; /* 0x0000050000007945 */
/* 0x000fe20003800000 */
/*0ac0*/ IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff007424 */
/* 0x000fe200078e00ff */
/*0ad0*/ LOP3.LUT P2, RZ, R4.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104ff7812 */
/* 0x040fe4000784c0ff */
/*0ae0*/ LOP3.LUT P1, RZ, R4, 0x2, RZ, 0xc0, !PT ; /* 0x0000000204ff7812 */
/* 0x000fc4000782c0ff */
/*0af0*/ FSEL R3, R12, 0.041666727513074874878, !P2 ; /* 0x3d2aaabb0c037808 */
/* 0x000fe20005000000 */
/*0b00*/ IMAD.SHL.U32 R12, R11, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x000fe200078e00ff */
/*0b10*/ FSEL R13, -R13, -0.4999999701976776123, !P2 ; /* 0xbeffffff0d0d7808 */
/* 0x000fe40005000100 */
/*0b20*/ SHF.L.U64.HI R11, R11, 0x2, R14 ; /* 0x000000020b0b7819 */
/* 0x000fca000001020e */
/*0b30*/ @P2 IMAD.MOV.U32 R5, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff052424 */
/* 0x000fc800078e00ff */
/*0b40*/ @P2 FFMA R0, R2, R5, -0.0013887860113754868507 ; /* 0xbab607ed02002423 */
/* 0x000fe20000000005 */
/*0b50*/ FSEL R5, R6, 1, !P2 ; /* 0x3f80000006057808 */
/* 0x000fc60005000000 */
/*0b60*/ FFMA R0, R2.reuse, R0, R3 ; /* 0x0000000002007223 */
/* 0x040fe40000000003 */
/*0b70*/ FFMA R3, R5, R2, RZ ; /* 0x0000000205037223 */
/* 0x000fe400000000ff */
/*0b80*/ FFMA R0, R2, R0, R13 ; /* 0x0000000002007223 */
/* 0x000fe2000000000d */
/*0b90*/ IADD3 R2, P2, R12, c[0x0][0x168], RZ ; /* 0x00005a000c027a10 */
/* 0x000fc60007f5e0ff */
/*0ba0*/ FFMA R5, R0, R3, R5 ; /* 0x0000000300057223 */
/* 0x000fe20000000005 */
/*0bb0*/ IADD3.X R3, R11, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000b037a10 */
/* 0x000fc600017fe4ff */
/*0bc0*/ @P1 FFMA R5, R5, -1, RZ ; /* 0xbf80000005051823 */
/* 0x000fca00000000ff */
/*0bd0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101906 */
/*0be0*/ @!P0 BRA 0xfb0 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ FSETP.NEU.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fda0003f0d200 */
/*0c00*/ @!P0 BRA 0xf90 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0c10*/ SHF.R.U32.HI R0, RZ, 0x17, R8 ; /* 0x00000017ff007819 */
/* 0x000fe20000011608 */
/*0c20*/ IMAD.SHL.U32 R2, R8, 0x100, RZ ; /* 0x0000010008027824 */
/* 0x001fe200078e00ff */
/*0c30*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0c40*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0c50*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*0c60*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*0c70*/ LOP3.LUT R13, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020d7812 */
/* 0x000fe400078efcff */
/*0c80*/ IADD3 R10, R0, -0x80, RZ ; /* 0xffffff80000a7810 */
/* 0x000fe20007ffe0ff */
/*0c90*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*0ca0*/ SHF.R.U32.HI R14, RZ, 0x5, R10 ; /* 0x00000005ff0e7819 */
/* 0x000fe4000001160a */
/*0cb0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0cc0*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0cd0*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0ce0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0d00*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0d10*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0d20*/ IMAD.WIDE.U32 R2, R2, R13, RZ ; /* 0x0000000d02027225 */
/* 0x004fca00078e00ff */
/*0d30*/ IADD3 R9, P1, R2, R6, RZ ; /* 0x0000000602097210 */
/* 0x000fc80007f3e0ff */
/*0d40*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0d50*/ STL [R0], R9 ; /* 0x0000000900007387 */
/* 0x0001e40000100800 */
/*0d60*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0d70*/ @P0 BRA 0xcb0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0d80*/ LOP3.LUT P0, R10, R10, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0a0a7812 */
/* 0x000fe2000780c0ff */
/*0d90*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*0da0*/ IADD3 R0, -R14.reuse, 0x4, RZ ; /* 0x000000040e007810 */
/* 0x040fe40007ffe1ff */
/*0db0*/ IADD3 R14, -R14, 0x6, RZ ; /* 0x000000060e0e7810 */
/* 0x000fca0007ffe1ff */
/*0dc0*/ IMAD R14, R14, 0x4, R1 ; /* 0x000000040e0e7824 */
/* 0x000fc800078e0201 */
/*0dd0*/ @P0 IMAD R9, R0, 0x4, R1 ; /* 0x0000000400090824 */
/* 0x000fe200078e0201 */
/*0de0*/ LDL R3, [R14+-0x4] ; /* 0xfffffc000e037983 */
/* 0x000ea80000100800 */
/*0df0*/ @P0 LDL R2, [R9] ; /* 0x0000000009020983 */
/* 0x000ee80000100800 */
/*0e00*/ LDL R0, [R14] ; /* 0x000000000e007983 */
/* 0x000f220000100800 */
/*0e10*/ @P0 IADD3 R7, -R10, 0x20, RZ ; /* 0x000000200a070810 */
/* 0x000fc40007ffe1ff */
/*0e20*/ LOP3.LUT P1, R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fe4000782c0ff */
/*0e30*/ @P0 SHF.R.U32.HI R4, RZ, R7.reuse, R2 ; /* 0x00000007ff040219 */
/* 0x088fe40000011602 */
/*0e40*/ @P0 SHF.R.U32.HI R2, RZ, R7, R3 ; /* 0x00000007ff020219 */
/* 0x004fe40000011603 */
/*0e50*/ @P0 SHF.L.U32 R5, R0, R10.reuse, RZ ; /* 0x0000000a00050219 */
/* 0x090fe400000006ff */
/*0e60*/ @P0 SHF.L.U32 R7, R3, R10, RZ ; /* 0x0000000a03070219 */
/* 0x000fc600000006ff */
/*0e70*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*0e80*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*0e90*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0ea0*/ SHF.R.U32.HI R9, RZ, 0x1f, R5 ; /* 0x0000001fff097819 */
/* 0x000fc80000011605 */
/*0eb0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0ec0*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fd800078e00ff */
/*0ed0*/ @P0 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff050212 */
/* 0x000fe400078e33ff */
/*0ee0*/ @P0 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff040212 */
/* 0x000fc800078e33ff */
/*0ef0*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e640000301c00 */
/*0f00*/ DMUL R2, R2, c[0x2][0x8] ; /* 0x0080020002027a28 */
/* 0x002e620000000000 */
/*0f10*/ LEA.HI R9, R0, R9, RZ, 0x2 ; /* 0x0000000900097211 */
/* 0x000fd200078f10ff */
/*0f20*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e620000301000 */
/*0f30*/ @P0 LOP3.LUT R8, R8, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000008080812 */
/* 0x000fe200078e3cff */
/*0f40*/ IMAD.MOV R0, RZ, RZ, -R9 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0a09 */
/*0f50*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0f60*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff091224 */
/* 0x000fc600078e0000 */
/*0f70*/ FSEL R10, R2, -R2, !P0 ; /* 0x80000002020a7208 */
/* 0x002fe20004000000 */
/*0f80*/ BRA 0xfb0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0f90*/ FMUL R10, RZ, R8 ; /* 0x00000008ff0a7220 */
/* 0x000fe40000400000 */
/*0fa0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0fb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0fc0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3c190000 ; /* 0x3c190000ff037424 */
/* 0x000fe200078e00ff */
/*0fd0*/ FSETP.NEU.AND P0, PT, |R10|.reuse, 0.00049096695147454738617, PT ; /* 0x3a00b43c0a00780b */
/* 0x040fe20003f0d200 */
/*0fe0*/ FMUL R0, R10, R10 ; /* 0x0000000a0a007220 */
/* 0x000fe20000400000 */
/*0ff0*/ LOP3.LUT R9, R9, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109097812 */
/* 0x000fc600078ec0ff */
/*1000*/ FFMA R3, R0, R3, 0.003265380859375 ; /* 0x3b56000000037423 */
/* 0x000fe20000000003 */
/*1010*/ ISETP.NE.U32.AND P1, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fc60003f25070 */
/*1020*/ FFMA R3, R0, R3, 0.0242919921875 ; /* 0x3cc7000000037423 */
/* 0x000fc80000000003 */
/*1030*/ FFMA R3, R0, R3, 0.053466796875 ; /* 0x3d5b000000037423 */
/* 0x000fc80000000003 */
/*1040*/ FFMA R3, R0, R3, 0.13337790966033935547 ; /* 0x3e08943800037423 */
/* 0x000fc80000000003 */
/*1050*/ FFMA R3, R0.reuse, R3, 0.33333230018615722656 ; /* 0x3eaaaa8800037423 */
/* 0x040fe40000000003 */
/*1060*/ FMUL R0, R0, R10 ; /* 0x0000000a00007220 */
/* 0x000fc80000400000 */
/*1070*/ @P0 FFMA R10, R3, R0, R10 ; /* 0x00000000030a0223 */
/* 0x000fe2000000000a */
/*1080*/ IADD3 R12, P0, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*1090*/ IADD3.X R13, R11, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000b0d7a10 */
/* 0x000fe200007fe4ff */
/*10a0*/ @!P1 MUFU.RCP R10, -R10 ; /* 0x8000000a000a9308 */
/* 0x000e280000001000 */
/*10b0*/ STG.E [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x001fe2000c101906 */
/*10c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
cudaProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
cudaMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
cudaDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
cudaFree(sin_arr);
cudaFree(cos_arr);
cudaFree(tan_arr);
cudaProfilerStop();
return 0;
} | .file "tmpxft_000a081d_00000000-6_trigonometric_ratio.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17calculator_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
.globl _Z17calculator_kernelPfS_S_i
.type _Z17calculator_kernelPfS_S_i, @function
_Z17calculator_kernelPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17calculator_kernelPfS_S_i, .-_Z17calculator_kernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "sin (%d) = %f cos (%d) = %f tan (%d) = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaProfilerStart@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl %ebx, %edx
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq 24(%rsp), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rbx,4), %xmm2
movl %ebx, %r8d
movq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movl %ebx, %ecx
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17calculator_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calculator_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
cudaProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
cudaMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
cudaMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
cudaDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
cudaFree(sin_arr);
cudaFree(cos_arr);
cudaFree(tan_arr);
cudaProfilerStop();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
hipProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
hipMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
hipDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
hipFree(sin_arr);
hipFree(cos_arr);
hipFree(tan_arr);
hipProfilerStop();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
hipProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
hipMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
hipDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
hipFree(sin_arr);
hipFree(cos_arr);
hipFree(tan_arr);
hipProfilerStop();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17calculator_kernelPfS_S_i
.globl _Z17calculator_kernelPfS_S_i
.p2align 8
.type _Z17calculator_kernelPfS_S_i,@function
_Z17calculator_kernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_14
v_cvt_f64_i32_e32 v[2:3], v1
s_mov_b32 s3, 0x3f91df46
s_mov_b32 s2, 0xa2506b91
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v3, v[2:3]
v_and_b32_e32 v0, 0x7fffffff, v3
v_cmp_ngt_f32_e64 s5, 0x48000000, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s5
s_xor_b32 s4, exec_lo, s2
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v2, v0, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v2, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v2, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v2, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v13
v_mad_u64_u32 v[9:10], null, v2, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v14
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v2, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v11
v_mad_u64_u32 v[11:12], null, v2, 0x4e441529, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v5, v12
v_mad_u64_u32 v[12:13], null, v2, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v2, 0, 0xffffffe0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, v11, v9 :: v_dual_add_nc_u32 v2, v2, v14
v_dual_cndmask_b32 v6, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v9, v6, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v11, v6, s2
v_cndmask_b32_e64 v5, v5, v10, s2
v_sub_nc_u32_e32 v11, 32, v2
v_cndmask_b32_e64 v10, v10, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v9, s3
v_cndmask_b32_e64 v9, v9, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v5, v10, s3
v_alignbit_b32 v12, v6, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v9, v5, v11
v_cndmask_b32_e32 v2, v12, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v8, v9, vcc_lo
v_cndmask_b32_e64 v4, v7, v4, s2
v_bfe_u32 v7, v2, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v2, v6, 30
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, 0, v7
v_alignbit_b32 v10, v5, v4, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v9
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_clz_i32_u32_e32 v10, v8
v_alignbit_b32 v6, v6, v5, 30
v_alignbit_b32 v4, v5, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_u32_e32 v10, 32, v10
v_xor_b32_e32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v9
v_sub_nc_u32_e32 v6, 31, v10
v_lshlrev_b32_e32 v12, 23, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_alignbit_b32 v8, v8, v5, v6
v_alignbit_b32 v4, v5, v4, v6
v_lshrrev_b32_e32 v6, 29, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v5, v8, v4, 9
v_lshlrev_b32_e32 v6, 31, v6
v_lshrrev_b32_e32 v8, 9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v9, v5
v_or_b32_e32 v11, 0.5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v9, 32, v9
v_sub_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v13, 31, v9
v_alignbit_b32 v4, v5, v4, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, v8, v11
v_add_lshl_u32 v8, v9, v10, 23
v_lshrrev_b32_e32 v4, 9, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, 0x3fc90fda, v5
v_sub_nc_u32_e32 v4, v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v5, 0x3fc90fda, -v9
v_add_nc_u32_e32 v4, 0x33000000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v5, v5, 0x33a22168, v8
v_or_b32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, 0x3fc90fda, v4
v_lshrrev_b32_e32 v4, 30, v2
v_add_f32_e32 v2, v9, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, v7, v4
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v2, 0x3f22f983, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v4, v2
v_fma_f32 v2, v4, 0xbfc90fda, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v4, 0xb3a22168, v2
v_fmamk_f32 v2, v4, 0xa7c234c4, v2
v_cvt_i32_f32_e32 v4, v4
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v2, v2 :: v_dual_and_b32 v8, 1, v4
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
v_dual_fmaak_f32 v6, s2, v5, 0x3c0881c4 :: v_dual_lshlrev_b32 v9, 30, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v8
v_xor_b32_e32 v4, v0, v3
v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
v_fmaak_f32 v7, s3, v5, 0xbab64f3b
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v6
v_dual_fmaak_f32 v7, v5, v7, 0x3d2aabf7 :: v_dual_fmac_f32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, v5, v7, 0xbf000004
v_fma_f32 v5, v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, v5, v2 :: v_dual_and_b32 v6, 0x80000000, v9
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_class_f32_e64 vcc_lo, v3, 0x1f8
v_xor3_b32 v7, v6, v5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, s2, v5
v_add_co_ci_u32_e64 v6, s2, s3, v6, s2
global_store_b32 v[5:6], v7, off
s_and_saveexec_b32 s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v7, 0
v_and_or_b32 v15, v0, s2, 0x800000
v_lshrrev_b32_e32 v12, 23, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
v_add_nc_u32_e32 v13, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e64 s2, 63, v13
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v14, 0, 0xffffffc0, s2
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v13
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s3, 31, v14
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v6, v10
v_cndmask_b32_e64 v5, v9, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v16, v16, v14
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s4, 31, v16
v_mov_b32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, v10, v8, s2
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v8, v5, s3
v_mov_b32_e32 v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
v_mov_b32_e32 v6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s4
v_cndmask_b32_e64 v7, v12, v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v6, v16
v_cndmask_b32_e64 v13, v13, v11, s2
v_cndmask_b32_e64 v12, v14, v12, s2
v_cndmask_b32_e64 v11, v11, v9, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s2, 0, v6
v_cndmask_b32_e64 v10, v13, v7, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s3
v_cndmask_b32_e64 v7, v7, v11, s3
v_sub_nc_u32_e32 v13, 32, v6
v_cndmask_b32_e64 v11, v11, v8, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s4
v_cndmask_b32_e64 v10, v10, v7, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v11, s4
v_cndmask_b32_e64 v5, v11, v5, s4
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v7, v13
v_cndmask_b32_e64 v6, v14, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v7, v5, v13
v_cndmask_b32_e64 v8, v9, v10, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v6, 29, 1
v_cndmask_b32_e64 v7, v12, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v6, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v5, v7, v5, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v8, v11
v_xor_b32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v7, v8
v_alignbit_b32 v5, v7, v5, v8
v_lshrrev_b32_e32 v8, 29, v6
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v10, v5, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v9, v6
v_clz_i32_u32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v13, 0.5, v8
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v14
v_sub_nc_u32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v7, v5, v15
v_or_b32_e32 v7, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v5, 9, v5
v_mul_f32_e32 v11, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v10
v_fma_f32 v10, v7, 0x3fc90fda, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fmamk_f32 v7, v7, 0x33a22168, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v5, v8
v_fmac_f32_e32 v7, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v11, v7
.LBB0_7:
s_and_not1_saveexec_b32 s2, s6
v_mul_f32_e64 v5, 0x3f22f983, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v6, 0xb3a22168, v5
v_fmamk_f32 v5, v6, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v6, v6
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v5, v5 :: v_dual_and_b32 v10, 1, v6
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[6:7], s[0:1], 0x8
v_fmaak_f32 v8, s2, v7, 0x3c0881c4
v_cmp_eq_u32_e64 s2, 0, v10
v_lshlrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
v_fmaak_f32 v9, s3, v7, 0xbab64f3b
v_and_b32_e32 v6, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v8, v7, v8
v_fmaak_f32 v9, v7, v9, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, v5, v8
v_fmaak_f32 v9, v7, v9, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v7, v9, 1.0
v_cndmask_b32_e64 v5, -v5, v7, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v7, v6, v5
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, s6, v5
v_add_co_ci_u32_e64 v6, s2, s7, v6, s2
global_store_b32 v[5:6], v7, off
s_and_saveexec_b32 s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s2
s_cbranch_execz .LBB0_11
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v7, 0
v_and_or_b32 v3, v0, s2, 0x800000
v_lshrrev_b32_e32 v0, 23, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v3, 0xfe5163ab, 0
v_add_nc_u32_e32 v0, 0xffffff88, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e64 s2, 63, v0
v_mad_u64_u32 v[8:9], null, v3, 0x3c439041, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, 0, 0xffffffc0, s2
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v13, v0
v_mad_u64_u32 v[9:10], null, v3, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s3, 31, v0
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v6, v10
v_cndmask_b32_e64 v5, v9, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v0, v14, v0
v_mad_u64_u32 v[10:11], null, v3, 0xf534ddc0, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s4, 31, v0
v_mov_b32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v3, 0xfc2757d1, v[6:7]
v_mov_b32_e32 v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v3, 0x4e441529, v[6:7]
v_mov_b32_e32 v6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[13:14], null, v3, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v3, 0, 0xffffffe0, s4
v_cndmask_b32_e64 v6, v12, v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v0, v3, v0
v_cndmask_b32_e64 v7, v13, v11, s2
v_cndmask_b32_e64 v12, v14, v12, s2
v_cndmask_b32_e64 v11, v11, v9, s2
v_cndmask_b32_e64 v3, v10, v8, s2
v_sub_nc_u32_e32 v10, 32, v0
v_cndmask_b32_e64 v8, v7, v6, s3
v_cndmask_b32_e64 v7, v12, v7, s3
v_cndmask_b32_e64 v6, v6, v11, s3
v_cndmask_b32_e64 v11, v11, v3, s3
v_cmp_eq_u32_e64 s2, 0, v0
v_cndmask_b32_e64 v3, v3, v5, s3
v_cndmask_b32_e64 v7, v7, v8, s4
v_cndmask_b32_e64 v8, v8, v6, s4
v_cndmask_b32_e64 v6, v6, v11, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v11, v3, s4
v_alignbit_b32 v12, v7, v8, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v9, v8, v6, v10
v_alignbit_b32 v10, v6, v3, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v12, v7, s2
v_cndmask_b32_e64 v5, v9, v8, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v6, v10, v6, s2
v_bfe_u32 v7, v0, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v0, v5, 30
v_alignbit_b32 v5, v5, v6, 30
v_alignbit_b32 v3, v6, v3, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, 0, v7
v_xor_b32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, v5, v9
v_xor_b32_e32 v3, v3, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v10, v8
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, 31, v10
v_lshlrev_b32_e32 v12, 23, v10
v_alignbit_b32 v8, v8, v5, v6
v_alignbit_b32 v3, v5, v3, v6
v_lshrrev_b32_e32 v6, 29, v0
v_lshrrev_b32_e32 v0, 30, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v8, v3, 9
v_lshlrev_b32_e32 v6, 31, v6
v_lshrrev_b32_e32 v8, 9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v9, v5
v_or_b32_e32 v11, 0.5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v9, 32, v9
v_sub_nc_u32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v13, 31, v9
v_alignbit_b32 v3, v5, v3, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, v8, v11
v_add_lshl_u32 v8, v9, v10, 23
v_lshrrev_b32_e32 v3, 9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, 0x3fc90fda, v5
v_sub_nc_u32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v5, 0x3fc90fda, -v9
v_add_nc_u32_e32 v3, 0x33000000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v5, v5, 0x33a22168, v8
v_or_b32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_dual_add_f32 v6, v9, v5 :: v_dual_add_nc_u32 v5, v7, v0
.LBB0_11:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v0, 0x3f22f983, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v0, v0
v_fma_f32 v3, v0, 0xbfc90fda, |v3|
v_cvt_i32_f32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v0, 0xb3a22168, v3
v_fmamk_f32 v6, v0, 0xa7c234c4, v3
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, v6, v6
s_mov_b32 s2, 0x3c971480
v_and_b32_e32 v5, 1, v5
v_fmaak_f32 v3, s2, v0, 0xbf039337
s_mov_b32 s2, 0xbc8cedd3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v7, s2, v0, 0x3ec54587
s_load_b64 s[2:3], s[0:1], 0x10
v_fmaak_f32 v3, v0, v3, 0x3f93f425
v_cmp_eq_u32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, v7, v3
v_mul_f32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v0, v6, v6
v_rcp_f32_e32 v7, v3
v_sub_f32_e32 v8, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v0, v0, v6, -v8
s_waitcnt_depctr 0xfff
v_fma_f32 v6, v3, -v7, 1.0
v_fma_f32 v0, v0, -v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, v0, -v7, -v7
v_cndmask_b32_e64 v0, v0, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v4, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17calculator_kernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17calculator_kernelPfS_S_i, .Lfunc_end0-_Z17calculator_kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17calculator_kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17calculator_kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define ITER 100000
#define THREAD_PER_BLOCK 10
#define PI 3.1415926535
#define RAD(X) X *(PI / 180.0)
__global__ void calculator_kernel(float *sin_arr, float *cos_arr, float *tan_arr, int N)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
{
float rad = RAD(idx);
sin_arr[idx] = sinf(rad);
cos_arr[idx] = cosf(rad);
tan_arr[idx] = tanf(rad);
}
}
int main()
{
hipProfilerStart();
float *sin_arr, *cos_arr, *tan_arr;
hipMallocManaged((void **)&sin_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&cos_arr, sizeof(float) * ITER);
hipMallocManaged((void **)&tan_arr, sizeof(float) * ITER);
calculator_kernel<<<ITER / THREAD_PER_BLOCK, THREAD_PER_BLOCK>>>(sin_arr, cos_arr, tan_arr, ITER);
hipDeviceSynchronize();
for (int i = 0; i < ITER; i++)
{
printf("sin (%d) = %f cos (%d) = %f tan (%d) = %f\n", i, sin_arr[i], i, cos_arr[i], i, tan_arr[i]);
}
hipFree(sin_arr);
hipFree(cos_arr);
hipFree(tan_arr);
hipProfilerStop();
return 0;
} | .text
.file "trigonometric_ratio.hip"
.globl _Z32__device_stub__calculator_kernelPfS_S_i # -- Begin function _Z32__device_stub__calculator_kernelPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__calculator_kernelPfS_S_i,@function
_Z32__device_stub__calculator_kernelPfS_S_i: # @_Z32__device_stub__calculator_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17calculator_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__calculator_kernelPfS_S_i, .Lfunc_end0-_Z32__device_stub__calculator_kernelPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
callq hipProfilerStart
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 9990(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100000, 36(%rsp) # imm = 0x186A0
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17calculator_kernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
movl %ebx, %ecx
movb $3, %al
callq printf
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_3
# %bb.4:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipProfilerStop
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17calculator_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17calculator_kernelPfS_S_i,@object # @_Z17calculator_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17calculator_kernelPfS_S_i
.p2align 3, 0x0
_Z17calculator_kernelPfS_S_i:
.quad _Z32__device_stub__calculator_kernelPfS_S_i
.size _Z17calculator_kernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sin (%d) = %f cos (%d) = %f tan (%d) = %f\n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17calculator_kernelPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__calculator_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17calculator_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a081d_00000000-6_trigonometric_ratio.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17calculator_kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
.globl _Z17calculator_kernelPfS_S_i
.type _Z17calculator_kernelPfS_S_i, @function
_Z17calculator_kernelPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17calculator_kernelPfS_S_i, .-_Z17calculator_kernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "sin (%d) = %f cos (%d) = %f tan (%d) = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaProfilerStart@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $400000, %esi
call cudaMallocManaged@PLT
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10000, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movl %ebx, %edx
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq 24(%rsp), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rbx,4), %xmm2
movl %ebx, %r8d
movq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movl %ebx, %ecx
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $100000, %rbx
jne .L13
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $100000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17calculator_kernelPfS_S_iPfS_S_i
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z17calculator_kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calculator_kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "trigonometric_ratio.hip"
.globl _Z32__device_stub__calculator_kernelPfS_S_i # -- Begin function _Z32__device_stub__calculator_kernelPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__calculator_kernelPfS_S_i,@function
_Z32__device_stub__calculator_kernelPfS_S_i: # @_Z32__device_stub__calculator_kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17calculator_kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__calculator_kernelPfS_S_i, .Lfunc_end0-_Z32__device_stub__calculator_kernelPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
callq hipProfilerStart
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
movl $1, %edx
callq hipMallocManaged
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 9990(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100000, 36(%rsp) # imm = 0x186A0
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17calculator_kernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq 8(%rsp), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %ebx, %esi
movl %ebx, %edx
movl %ebx, %ecx
movb $3, %al
callq printf
incq %rbx
cmpq $100000, %rbx # imm = 0x186A0
jne .LBB1_3
# %bb.4:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipProfilerStop
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17calculator_kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17calculator_kernelPfS_S_i,@object # @_Z17calculator_kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z17calculator_kernelPfS_S_i
.p2align 3, 0x0
_Z17calculator_kernelPfS_S_i:
.quad _Z32__device_stub__calculator_kernelPfS_S_i
.size _Z17calculator_kernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sin (%d) = %f cos (%d) = %f tan (%d) = %f\n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17calculator_kernelPfS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__calculator_kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17calculator_kernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
__global__ void AvePoolForward(const int nthreads,
const float* const bottom_data, const int num, const int channels,
const int height, const int width, const int pooled_height,
const int pooled_width, const int kernel_h, const int kernel_w,
const int stride_h, const int stride_w, const int pad_h, const int pad_w,
float* const top_data) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
const int pw = index % pooled_width;
const int ph = (index / pooled_width) % pooled_height;
const int c = (index / pooled_width / pooled_height) % channels;
const int n = index / pooled_width / pooled_height / channels;
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
const int pool_size = (hend - hstart) * (wend - wstart);
hstart = max(hstart, 0);
wstart = max(wstart, 0);
hend = min(hend, height);
wend = min(wend, width);
float aveval = 0;
const float* const bottom_slice =
bottom_data + (n * channels + c) * height * width;
for (int h = hstart; h < hend; ++h) {
for (int w = wstart; w < wend; ++w) {
aveval += bottom_slice[h * width + w];
}
}
top_data[index] = aveval / pool_size;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_fwd(
const float* bottom_data,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float* top_data,
cudaStream_t stream)
{
int count = pooled_width_ * pooled_height_ * channels_ * num;
AvePoolForward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, bottom_data, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, top_data);
}
__global__ void AvePoolBackward(const int nthreads, const float* const top_diff,
const int num, const int channels, const int height,
const int width, const int pooled_height, const int pooled_width,
const int kernel_h, const int kernel_w, const int stride_h,
const int stride_w, const int pad_h, const int pad_w,
float* const bottom_diff) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
// find out the local index
// find out the local offset
const int w = index % width + pad_w;
const int h = (index / width) % height + pad_h;
const int c = (index / width / height) % channels;
const int n = index / width / height / channels;
const int phstart = (h < kernel_h) ? 0 : (h - kernel_h) / stride_h + 1;
const int phend = min(h / stride_h + 1, pooled_height);
const int pwstart = (w < kernel_w) ? 0 : (w - kernel_w) / stride_w + 1;
const int pwend = min(w / stride_w + 1, pooled_width);
float gradient = 0;
const float* const top_diff_slice =
top_diff + (n * channels + c) * pooled_height * pooled_width;
for (int ph = phstart; ph < phend; ++ph) {
for (int pw = pwstart; pw < pwend; ++pw) {
// figure out the pooling size
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
int pool_size = (hend - hstart) * (wend - wstart);
gradient += top_diff_slice[ph * pooled_width + pw] / pool_size;
}
}
bottom_diff[index] = gradient;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_bwd(
const float* top_diff,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float *bottom_diff,
cudaStream_t stream)
{
int count = width_ * height_ * channels_ * num;
AvePoolBackward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, top_diff, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, bottom_diff);
} | .file "tmpxft_001704c5_00000000-6_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.type _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, @function
_Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf:
.LFB2053:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 40(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, .-_Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.globl _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.type _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, @function
_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, .-_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.globl neuralops_cuda_caffe_avgpool2d_fwd
.type neuralops_cuda_caffe_avgpool2d_fwd, @function
neuralops_cuda_caffe_avgpool2d_fwd:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movl %r8d, %r15d
movl %r9d, %r13d
movl %r9d, %ebx
imull 112(%rsp), %ebx
imull %edx, %ebx
imull %esi, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movq 176(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 176(%rsp)
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 184
pushq %r13
.cfi_def_cfa_offset 192
movl %r15d, %r9d
movl %r14d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 88(%rsp), %rsi
movl %ebx, %edi
call _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $80, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size neuralops_cuda_caffe_avgpool2d_fwd, .-neuralops_cuda_caffe_avgpool2d_fwd
.globl _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.type _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, @function
_Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf:
.LFB2055:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 40(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, .-_Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.globl _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.type _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, @function
_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, .-_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.globl neuralops_cuda_caffe_avgpool2d_bwd
.type neuralops_cuda_caffe_avgpool2d_bwd, @function
neuralops_cuda_caffe_avgpool2d_bwd:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %r8d, %ebx
imull %ecx, %ebx
imull %edx, %ebx
imull %esi, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movq 176(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 176(%rsp)
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
movl %r14d, %r9d
movl %r13d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 88(%rsp), %rsi
movl %ebx, %edi
call _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $80, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.cfi_endproc
.LFE2028:
.size neuralops_cuda_caffe_avgpool2d_bwd, .-neuralops_cuda_caffe_avgpool2d_bwd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf"
.align 8
.LC1:
.string "_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
__global__ void AvePoolForward(const int nthreads,
const float* const bottom_data, const int num, const int channels,
const int height, const int width, const int pooled_height,
const int pooled_width, const int kernel_h, const int kernel_w,
const int stride_h, const int stride_w, const int pad_h, const int pad_w,
float* const top_data) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
const int pw = index % pooled_width;
const int ph = (index / pooled_width) % pooled_height;
const int c = (index / pooled_width / pooled_height) % channels;
const int n = index / pooled_width / pooled_height / channels;
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
const int pool_size = (hend - hstart) * (wend - wstart);
hstart = max(hstart, 0);
wstart = max(wstart, 0);
hend = min(hend, height);
wend = min(wend, width);
float aveval = 0;
const float* const bottom_slice =
bottom_data + (n * channels + c) * height * width;
for (int h = hstart; h < hend; ++h) {
for (int w = wstart; w < wend; ++w) {
aveval += bottom_slice[h * width + w];
}
}
top_data[index] = aveval / pool_size;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_fwd(
const float* bottom_data,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float* top_data,
cudaStream_t stream)
{
int count = pooled_width_ * pooled_height_ * channels_ * num;
AvePoolForward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, bottom_data, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, top_data);
}
__global__ void AvePoolBackward(const int nthreads, const float* const top_diff,
const int num, const int channels, const int height,
const int width, const int pooled_height, const int pooled_width,
const int kernel_h, const int kernel_w, const int stride_h,
const int stride_w, const int pad_h, const int pad_w,
float* const bottom_diff) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
// find out the local index
// find out the local offset
const int w = index % width + pad_w;
const int h = (index / width) % height + pad_h;
const int c = (index / width / height) % channels;
const int n = index / width / height / channels;
const int phstart = (h < kernel_h) ? 0 : (h - kernel_h) / stride_h + 1;
const int phend = min(h / stride_h + 1, pooled_height);
const int pwstart = (w < kernel_w) ? 0 : (w - kernel_w) / stride_w + 1;
const int pwend = min(w / stride_w + 1, pooled_width);
float gradient = 0;
const float* const top_diff_slice =
top_diff + (n * channels + c) * pooled_height * pooled_width;
for (int ph = phstart; ph < phend; ++ph) {
for (int pw = pwstart; pw < pwend; ++pw) {
// figure out the pooling size
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
int pool_size = (hend - hstart) * (wend - wstart);
gradient += top_diff_slice[ph * pooled_width + pw] / pool_size;
}
}
bottom_diff[index] = gradient;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_bwd(
const float* top_diff,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float *bottom_diff,
cudaStream_t stream)
{
int count = width_ * height_ * channels_ * num;
AvePoolBackward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, top_diff, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, bottom_diff);
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void AvePoolForward(const int nthreads,
const float* const bottom_data, const int num, const int channels,
const int height, const int width, const int pooled_height,
const int pooled_width, const int kernel_h, const int kernel_w,
const int stride_h, const int stride_w, const int pad_h, const int pad_w,
float* const top_data) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
const int pw = index % pooled_width;
const int ph = (index / pooled_width) % pooled_height;
const int c = (index / pooled_width / pooled_height) % channels;
const int n = index / pooled_width / pooled_height / channels;
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
const int pool_size = (hend - hstart) * (wend - wstart);
hstart = max(hstart, 0);
wstart = max(wstart, 0);
hend = min(hend, height);
wend = min(wend, width);
float aveval = 0;
const float* const bottom_slice =
bottom_data + (n * channels + c) * height * width;
for (int h = hstart; h < hend; ++h) {
for (int w = wstart; w < wend; ++w) {
aveval += bottom_slice[h * width + w];
}
}
top_data[index] = aveval / pool_size;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_fwd(
const float* bottom_data,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float* top_data,
hipStream_t stream)
{
int count = pooled_width_ * pooled_height_ * channels_ * num;
AvePoolForward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, bottom_data, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, top_data);
}
__global__ void AvePoolBackward(const int nthreads, const float* const top_diff,
const int num, const int channels, const int height,
const int width, const int pooled_height, const int pooled_width,
const int kernel_h, const int kernel_w, const int stride_h,
const int stride_w, const int pad_h, const int pad_w,
float* const bottom_diff) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
// find out the local index
// find out the local offset
const int w = index % width + pad_w;
const int h = (index / width) % height + pad_h;
const int c = (index / width / height) % channels;
const int n = index / width / height / channels;
const int phstart = (h < kernel_h) ? 0 : (h - kernel_h) / stride_h + 1;
const int phend = min(h / stride_h + 1, pooled_height);
const int pwstart = (w < kernel_w) ? 0 : (w - kernel_w) / stride_w + 1;
const int pwend = min(w / stride_w + 1, pooled_width);
float gradient = 0;
const float* const top_diff_slice =
top_diff + (n * channels + c) * pooled_height * pooled_width;
for (int ph = phstart; ph < phend; ++ph) {
for (int pw = pwstart; pw < pwend; ++pw) {
// figure out the pooling size
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
int pool_size = (hend - hstart) * (wend - wstart);
gradient += top_diff_slice[ph * pooled_width + pw] / pool_size;
}
}
bottom_diff[index] = gradient;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_bwd(
const float* top_diff,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float *bottom_diff,
hipStream_t stream)
{
int count = width_ * height_ * channels_ * num;
AvePoolBackward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, top_diff, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, bottom_diff);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void AvePoolForward(const int nthreads,
const float* const bottom_data, const int num, const int channels,
const int height, const int width, const int pooled_height,
const int pooled_width, const int kernel_h, const int kernel_w,
const int stride_h, const int stride_w, const int pad_h, const int pad_w,
float* const top_data) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
const int pw = index % pooled_width;
const int ph = (index / pooled_width) % pooled_height;
const int c = (index / pooled_width / pooled_height) % channels;
const int n = index / pooled_width / pooled_height / channels;
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
const int pool_size = (hend - hstart) * (wend - wstart);
hstart = max(hstart, 0);
wstart = max(wstart, 0);
hend = min(hend, height);
wend = min(wend, width);
float aveval = 0;
const float* const bottom_slice =
bottom_data + (n * channels + c) * height * width;
for (int h = hstart; h < hend; ++h) {
for (int w = wstart; w < wend; ++w) {
aveval += bottom_slice[h * width + w];
}
}
top_data[index] = aveval / pool_size;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_fwd(
const float* bottom_data,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float* top_data,
hipStream_t stream)
{
int count = pooled_width_ * pooled_height_ * channels_ * num;
AvePoolForward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, bottom_data, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, top_data);
}
__global__ void AvePoolBackward(const int nthreads, const float* const top_diff,
const int num, const int channels, const int height,
const int width, const int pooled_height, const int pooled_width,
const int kernel_h, const int kernel_w, const int stride_h,
const int stride_w, const int pad_h, const int pad_w,
float* const bottom_diff) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
// find out the local index
// find out the local offset
const int w = index % width + pad_w;
const int h = (index / width) % height + pad_h;
const int c = (index / width / height) % channels;
const int n = index / width / height / channels;
const int phstart = (h < kernel_h) ? 0 : (h - kernel_h) / stride_h + 1;
const int phend = min(h / stride_h + 1, pooled_height);
const int pwstart = (w < kernel_w) ? 0 : (w - kernel_w) / stride_w + 1;
const int pwend = min(w / stride_w + 1, pooled_width);
float gradient = 0;
const float* const top_diff_slice =
top_diff + (n * channels + c) * pooled_height * pooled_width;
for (int ph = phstart; ph < phend; ++ph) {
for (int pw = pwstart; pw < pwend; ++pw) {
// figure out the pooling size
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
int pool_size = (hend - hstart) * (wend - wstart);
gradient += top_diff_slice[ph * pooled_width + pw] / pool_size;
}
}
bottom_diff[index] = gradient;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_bwd(
const float* top_diff,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float *bottom_diff,
hipStream_t stream)
{
int count = width_ * height_ * channels_ * num;
AvePoolBackward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, top_diff, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, bottom_diff);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.globl _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.p2align 8
.type _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf,@function
_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b256 s[4:11], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v1
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s7, s2
v_xor_b32_e32 v3, s2, v3
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s12, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s12, v0
s_ashr_i32 s12, s6, 31
s_add_i32 s13, s6, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s13, s13, s12
v_cvt_f32_u32_e32 v5, s13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
s_sub_i32 s2, 0, s13
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cvt_u32_f32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_lo_u32 v4, s2, v2
s_load_b64 s[2:3], s[0:1], 0x38
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_ashrrev_i32_e32 v0, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v5, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v5, v0
v_xor_b32_e32 v0, s12, v0
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s13
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s13, v4
v_cmp_le_u32_e32 vcc_lo, s13, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s13, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v0
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s6
s_mov_b32 s6, exec_lo
v_sub_nc_u32_e32 v2, v3, v2
v_mul_lo_u32 v3, v3, s7
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, s10
v_sub_nc_u32_e32 v3, v1, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v2
v_mul_lo_u32 v2, v3, s11
s_add_i32 s2, s2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, s8, v5
v_max_i32_e32 v10, 0, v5
v_subrev_nc_u32_e32 v6, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_i32_e32 v7, s2, v3
s_add_i32 s2, s3, s5
v_add_nc_u32_e32 v2, s9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_i32_e32 v11, s4, v7
v_min_i32_e32 v9, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e64 v10, v11
s_cbranch_execz .LBB0_9
s_mul_i32 s4, s5, s4
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_lo_u32 v2, s4, v0
v_max_i32_e32 v0, 0, v6
v_min_i32_e32 v12, s5, v9
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v0, v12
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[13:14], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s5, v10, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s2, s2, v13
v_add_co_ci_u32_e64 v14, s2, s3, v14, s2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v10, 1, v10
v_add_nc_u32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v10, v11
s_or_b32 s7, s2, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_8
.LBB0_4:
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v15, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, s2, v13, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, v14, v4, s2
.LBB0_6:
global_load_b32 v16, v[3:4], off
v_add_nc_u32_e32 v15, 1, v15
v_add_co_u32 v3, s2, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v16
v_cmp_ge_i32_e64 s3, v15, v12
s_or_b32 s8, s3, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s8
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s6
v_sub_nc_u32_e32 v0, v7, v5
v_sub_nc_u32_e32 v2, v9, v6
s_load_b64 s[0:1], s[0:1], 0x40
v_mul_lo_u32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v0
v_div_scale_f32 v0, null, v3, v3, v8
v_div_scale_f32 v5, vcc_lo, v8, v3, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v4, 1.0
v_fmac_f32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v2, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v2, v4
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v0, -v0, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v0, v4, v6
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, v3, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, .Lfunc_end0-_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.globl _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.p2align 8
.type _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf,@function
_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_14
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x30
s_load_b32 s7, s[0:1], 0x38
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s5, s2
v_xor_b32_e32 v3, s2, v3
s_xor_b32 s8, s8, s2
v_cvt_f32_u32_e32 v0, s8
s_sub_i32 s9, 0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s9, v0
s_ashr_i32 s9, s4, 31
s_add_i32 s10, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s10, s9
v_cvt_f32_u32_e32 v5, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
s_sub_i32 s2, 0, s10
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_mul_lo_u32 v2, v0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v6, s8, v2
v_cmp_le_u32_e32 vcc_lo, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s8, v2
v_cvt_u32_f32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_lo_u32 v4, s2, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v5, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s9, v3
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s10
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s10, v4
v_cmp_le_u32_e32 vcc_lo, s10, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v4
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_mov_b32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, s4
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s7, v2
v_cmpx_le_i32_e64 s3, v2
s_cbranch_execz .LBB1_3
s_ashr_i32 s8, s6, 31
v_subrev_nc_u32_e32 v6, s3, v2
s_add_i32 s9, s6, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s9, s9, s8
v_ashrrev_i32_e32 v7, 31, v6
v_cvt_f32_u32_e32 v3, s9
s_sub_i32 s10, 0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_rcp_iflag_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v6, v7
v_xor_b32_e32 v7, s8, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s10, v3
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v5
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, s9
v_sub_nc_u32_e32 v5, v6, v5
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s9, v5
v_cmp_le_u32_e32 vcc_lo, s9, v5
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v3
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v7
v_sub_nc_u32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, 1, v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_ashr_i32 s9, s6, 31
v_ashrrev_i32_e32 v6, 31, v2
s_add_i32 s2, s6, s9
s_clause 0x1
s_load_b32 s10, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x34
s_xor_b32 s11, s2, s9
v_add_nc_u32_e32 v2, v2, v6
v_cvt_f32_u32_e32 v3, s11
s_sub_i32 s2, 0, s11
v_mul_lo_u32 v0, v0, s5
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
v_sub_nc_u32_e32 v0, v1, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v7, s2, v3
s_load_b32 s2, s[0:1], 0x2c
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v3, v7
v_xor_b32_e32 v7, v2, v6
v_add_nc_u32_e32 v9, v3, v8
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v8, s10, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[2:3], null, v7, v9, 0
v_cmpx_le_i32_e64 s2, v8
s_cbranch_execz .LBB1_5
s_ashr_i32 s13, s8, 31
v_subrev_nc_u32_e32 v9, s2, v8
s_add_i32 s14, s8, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s14, s14, s13
v_ashrrev_i32_e32 v10, 31, v9
v_cvt_f32_u32_e32 v0, s14
s_sub_i32 s15, 0, s14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v9, v10
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v10, s13, v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s15, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s14
v_sub_nc_u32_e32 v2, v9, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
v_dual_cndmask_b32 v2, v2, v11 :: v_dual_add_nc_u32 v9, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, 1, v0
v_cndmask_b32_e32 v0, v0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v10
v_sub_nc_u32_e32 v0, v0, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, 1, v0
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v3, s11
s_load_b32 s12, s[0:1], 0x20
v_xor_b32_e32 v6, s9, v6
s_mov_b32 s9, exec_lo
v_sub_nc_u32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s11, v2
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_dual_cndmask_b32 v2, v2, v9 :: v_dual_add_nc_u32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, 1, v3
v_dual_cndmask_b32 v2, v3, v7 :: v_dual_mov_b32 v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v6
v_sub_nc_u32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v6, s12, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB1_13
s_ashr_i32 s13, s8, 31
v_ashrrev_i32_e32 v7, 31, v8
s_add_i32 s11, s8, s13
s_add_i32 s4, s7, s4
s_xor_b32 s14, s11, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v7
v_cvt_f32_u32_e32 v2, s14
s_sub_i32 s11, 0, s14
v_xor_b32_e32 v8, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
v_xor_b32_e32 v7, s13, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s11, v2
s_load_b32 s11, s[0:1], 0x24
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v2, v3
v_mad_u64_u32 v[2:3], null, v8, v9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v3, s14
v_sub_nc_u32_e32 v2, v8, v2
v_add_nc_u32_e32 v8, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s14, v2
v_subrev_nc_u32_e32 v9, s14, v2
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v8, 1, v3
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s11, s12
s_load_b64 s[12:13], s[0:1], 0x8
v_mul_lo_u32 v2, s14, v4
v_mul_lo_u32 v4, v0, s8
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v7
v_add_nc_u32_e32 v9, s2, v4
v_sub_nc_u32_e32 v8, s10, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v7, v3, v7
v_ashrrev_i32_e32 v3, 31, v2
v_subrev_nc_u32_e32 v9, s10, v9
s_add_i32 s10, s10, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, 1, v7
v_lshlrev_b64 v[11:12], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, v5, s11, v[0:1]
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_min_i32_e32 v10, s11, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_lt_i32_e64 s2, v0, v10
s_mov_b32 s12, 0
s_branch .LBB1_8
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v5, 1, v5
v_add_nc_u32_e32 v2, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v5, v6
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB1_12
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_7
v_mul_lo_u32 v3, v5, s6
v_mov_b32_e32 v14, v9
s_mov_b32 s13, 0
v_mov_b32_e32 v13, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v15, s7, v3
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v16, s3, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_min_i32_e32 v16, s4, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, v11, v3
v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_nc_u32_e32 v15, v16, v15
v_mov_b32_e32 v16, v0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_10:
global_load_b32 v17, v[3:4], off
v_min_i32_e32 v18, s10, v14
v_add_nc_u32_e32 v16, 1, v16
v_add_nc_u32_e32 v14, s8, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v18, v13
v_subrev_nc_u32_e32 v13, s8, v13
v_mul_lo_u32 v18, v18, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v18, v18
s_waitcnt vmcnt(0)
v_div_scale_f32 v19, null, v18, v18, v17
v_div_scale_f32 v22, vcc_lo, v17, v18, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v20, v19
s_waitcnt_depctr 0xfff
v_fma_f32 v21, -v19, v20, 1.0
v_fmac_f32_e32 v20, v21, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v22, v20
v_fma_f32 v23, -v19, v21, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v23, v20
v_fma_f32 v19, -v19, v21, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v19, v19, v20, v21
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_div_fixup_f32 v17, v19, v18, v17
v_cmp_ge_i32_e32 vcc_lo, v16, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_f32_e32 v7, v7, v17
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB1_10
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB1_7
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s12
.LBB1_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s9
s_load_b64 s[0:1], s[0:1], 0x40
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, .Lfunc_end1-_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
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.size: 4
.value_kind: by_value
- .address_space: global
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.value_kind: global_buffer
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.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
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.size: 2
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.size: 2
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.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
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- .args:
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.language: OpenCL C
.language_version:
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- 0
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.name: _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
__global__ void AvePoolForward(const int nthreads,
const float* const bottom_data, const int num, const int channels,
const int height, const int width, const int pooled_height,
const int pooled_width, const int kernel_h, const int kernel_w,
const int stride_h, const int stride_w, const int pad_h, const int pad_w,
float* const top_data) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
const int pw = index % pooled_width;
const int ph = (index / pooled_width) % pooled_height;
const int c = (index / pooled_width / pooled_height) % channels;
const int n = index / pooled_width / pooled_height / channels;
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
const int pool_size = (hend - hstart) * (wend - wstart);
hstart = max(hstart, 0);
wstart = max(wstart, 0);
hend = min(hend, height);
wend = min(wend, width);
float aveval = 0;
const float* const bottom_slice =
bottom_data + (n * channels + c) * height * width;
for (int h = hstart; h < hend; ++h) {
for (int w = wstart; w < wend; ++w) {
aveval += bottom_slice[h * width + w];
}
}
top_data[index] = aveval / pool_size;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_fwd(
const float* bottom_data,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float* top_data,
hipStream_t stream)
{
int count = pooled_width_ * pooled_height_ * channels_ * num;
AvePoolForward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, bottom_data, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, top_data);
}
__global__ void AvePoolBackward(const int nthreads, const float* const top_diff,
const int num, const int channels, const int height,
const int width, const int pooled_height, const int pooled_width,
const int kernel_h, const int kernel_w, const int stride_h,
const int stride_w, const int pad_h, const int pad_w,
float* const bottom_diff) {
//CUDA_KERNEL_LOOP(index, nthreads) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < nthreads) {
// find out the local index
// find out the local offset
const int w = index % width + pad_w;
const int h = (index / width) % height + pad_h;
const int c = (index / width / height) % channels;
const int n = index / width / height / channels;
const int phstart = (h < kernel_h) ? 0 : (h - kernel_h) / stride_h + 1;
const int phend = min(h / stride_h + 1, pooled_height);
const int pwstart = (w < kernel_w) ? 0 : (w - kernel_w) / stride_w + 1;
const int pwend = min(w / stride_w + 1, pooled_width);
float gradient = 0;
const float* const top_diff_slice =
top_diff + (n * channels + c) * pooled_height * pooled_width;
for (int ph = phstart; ph < phend; ++ph) {
for (int pw = pwstart; pw < pwend; ++pw) {
// figure out the pooling size
int hstart = ph * stride_h - pad_h;
int wstart = pw * stride_w - pad_w;
int hend = min(hstart + kernel_h, height + pad_h);
int wend = min(wstart + kernel_w, width + pad_w);
int pool_size = (hend - hstart) * (wend - wstart);
gradient += top_diff_slice[ph * pooled_width + pw] / pool_size;
}
}
bottom_diff[index] = gradient;
}
}
extern "C" void neuralops_cuda_caffe_avgpool2d_bwd(
const float* top_diff,
int num, int channels_, int height_, int width_,
int pooled_height_, int pooled_width_,
int kernel_h_, int kernel_w_,
int pad_h_, int pad_w_,
int stride_h_, int stride_w_,
float *bottom_diff,
hipStream_t stream)
{
int count = width_ * height_ * channels_ * num;
AvePoolBackward<<<(count+1024-1)/1024, 1024, 0, stream>>>(
count, top_diff, num, channels_,
height_, width_, pooled_height_, pooled_width_, kernel_h_,
kernel_w_, stride_h_, stride_w_, pad_h_, pad_w_, bottom_diff);
} | .text
.file "pool.hip"
.globl _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf # -- Begin function _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.p2align 4, 0x90
.type _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf,@function
_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf: # @_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf, .Lfunc_end0-_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.cfi_endproc
# -- End function
.globl neuralops_cuda_caffe_avgpool2d_fwd # -- Begin function neuralops_cuda_caffe_avgpool2d_fwd
.p2align 4, 0x90
.type neuralops_cuda_caffe_avgpool2d_fwd,@function
neuralops_cuda_caffe_avgpool2d_fwd: # @neuralops_cuda_caffe_avgpool2d_fwd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, 8(%rsp) # 4-byte Spill
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %r13
movq 368(%rsp), %r9
movl %edx, %ebp
imull %esi, %ebp
imull %ebx, %ebp
imull 304(%rsp), %ebp
leal 1023(%rbp), %eax
leal 2046(%rbp), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 360(%rsp), %rax
movl 352(%rsp), %ecx
movl 344(%rsp), %edx
movl 336(%rsp), %esi
movl 328(%rsp), %edi
movl 320(%rsp), %r8d
movl 312(%rsp), %r9d
movl %ebp, 60(%rsp)
movq %r13, 120(%rsp)
movl %r12d, 56(%rsp)
movl %r15d, 52(%rsp)
movl %r14d, 48(%rsp)
movl 8(%rsp), %r10d # 4-byte Reload
movl %r10d, 44(%rsp)
movl %ebx, 40(%rsp)
movl 304(%rsp), %r10d
movl %r10d, 36(%rsp)
movl %r9d, 32(%rsp)
movl %r8d, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size neuralops_cuda_caffe_avgpool2d_fwd, .Lfunc_end1-neuralops_cuda_caffe_avgpool2d_fwd
.cfi_endproc
# -- End function
.globl _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf # -- Begin function _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.p2align 4, 0x90
.type _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf,@function
_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf: # @_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf, .Lfunc_end2-_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.cfi_endproc
# -- End function
.globl neuralops_cuda_caffe_avgpool2d_bwd # -- Begin function neuralops_cuda_caffe_avgpool2d_bwd
.p2align 4, 0x90
.type neuralops_cuda_caffe_avgpool2d_bwd,@function
neuralops_cuda_caffe_avgpool2d_bwd: # @neuralops_cuda_caffe_avgpool2d_bwd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 8(%rsp) # 4-byte Spill
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %r13
movq 368(%rsp), %r9
movl %edx, %eax
imull %esi, %eax
movl %ecx, %ebx
imull %r8d, %ebx
imull %eax, %ebx
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 360(%rsp), %rax
movl 352(%rsp), %ecx
movl 344(%rsp), %edx
movl 336(%rsp), %esi
movl 328(%rsp), %edi
movl 320(%rsp), %r8d
movl 312(%rsp), %r9d
movl 304(%rsp), %r10d
movl %ebx, 60(%rsp)
movq %r13, 120(%rsp)
movl %r12d, 56(%rsp)
movl %r15d, 52(%rsp)
movl %r14d, 48(%rsp)
movl %ebp, 44(%rsp)
movl 8(%rsp), %r11d # 4-byte Reload
movl %r11d, 40(%rsp)
movl %r10d, 36(%rsp)
movl %r9d, 32(%rsp)
movl %r8d, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size neuralops_cuda_caffe_avgpool2d_bwd, .Lfunc_end3-neuralops_cuda_caffe_avgpool2d_bwd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf,@object # @_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.section .rodata,"a",@progbits
.globl _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.p2align 3, 0x0
_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf:
.quad _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.size _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, 8
.type _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf,@object # @_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.globl _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.p2align 3, 0x0
_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf:
.quad _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.size _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.addrsig_sym _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.addrsig_sym _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001704c5_00000000-6_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.type _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, @function
_Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf:
.LFB2053:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 40(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, .-_Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.globl _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.type _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, @function
_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, .-_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.globl neuralops_cuda_caffe_avgpool2d_fwd
.type neuralops_cuda_caffe_avgpool2d_fwd, @function
neuralops_cuda_caffe_avgpool2d_fwd:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r14d
movl %r8d, %r15d
movl %r9d, %r13d
movl %r9d, %ebx
imull 112(%rsp), %ebx
imull %edx, %ebx
imull %esi, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movq 176(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 176(%rsp)
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 184
pushq %r13
.cfi_def_cfa_offset 192
movl %r15d, %r9d
movl %r14d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 88(%rsp), %rsi
movl %ebx, %edi
call _Z50__device_stub__Z14AvePoolForwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $80, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.cfi_endproc
.LFE2027:
.size neuralops_cuda_caffe_avgpool2d_fwd, .-neuralops_cuda_caffe_avgpool2d_fwd
.globl _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.type _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, @function
_Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf:
.LFB2055:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 40(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movq 320(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 256(%rsp), %rax
movq %rax, 160(%rsp)
leaq 264(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 288(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 264
pushq 56(%rsp)
.cfi_def_cfa_offset 272
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf, .-_Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
.globl _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.type _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, @function
_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf:
.LFB2056:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 88(%rsp)
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
call _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, .-_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.globl neuralops_cuda_caffe_avgpool2d_bwd
.type neuralops_cuda_caffe_avgpool2d_bwd, @function
neuralops_cuda_caffe_avgpool2d_bwd:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movl %r8d, %ebx
imull %ecx, %ebx
imull %edx, %ebx
imull %esi, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movq 176(%rsp), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 120
pushq 176(%rsp)
.cfi_def_cfa_offset 128
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
movl 160(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 144
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 192(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 176(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
movl %r14d, %r9d
movl %r13d, %r8d
movl %r12d, %ecx
movl %ebp, %edx
movq 88(%rsp), %rsi
movl %ebx, %edi
call _Z51__device_stub__Z15AvePoolBackwardiPKfiiiiiiiiiiiiPfiPKfiiiiiiiiiiiiPf
addq $80, %rsp
.cfi_def_cfa_offset 112
jmp .L23
.cfi_endproc
.LFE2028:
.size neuralops_cuda_caffe_avgpool2d_bwd, .-neuralops_cuda_caffe_avgpool2d_bwd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf"
.align 8
.LC1:
.string "_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pool.hip"
.globl _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf # -- Begin function _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.p2align 4, 0x90
.type _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf,@function
_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf: # @_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf, .Lfunc_end0-_Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.cfi_endproc
# -- End function
.globl neuralops_cuda_caffe_avgpool2d_fwd # -- Begin function neuralops_cuda_caffe_avgpool2d_fwd
.p2align 4, 0x90
.type neuralops_cuda_caffe_avgpool2d_fwd,@function
neuralops_cuda_caffe_avgpool2d_fwd: # @neuralops_cuda_caffe_avgpool2d_fwd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, 8(%rsp) # 4-byte Spill
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %r13
movq 368(%rsp), %r9
movl %edx, %ebp
imull %esi, %ebp
imull %ebx, %ebp
imull 304(%rsp), %ebp
leal 1023(%rbp), %eax
leal 2046(%rbp), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 360(%rsp), %rax
movl 352(%rsp), %ecx
movl 344(%rsp), %edx
movl 336(%rsp), %esi
movl 328(%rsp), %edi
movl 320(%rsp), %r8d
movl 312(%rsp), %r9d
movl %ebp, 60(%rsp)
movq %r13, 120(%rsp)
movl %r12d, 56(%rsp)
movl %r15d, 52(%rsp)
movl %r14d, 48(%rsp)
movl 8(%rsp), %r10d # 4-byte Reload
movl %r10d, 44(%rsp)
movl %ebx, 40(%rsp)
movl 304(%rsp), %r10d
movl %r10d, 36(%rsp)
movl %r9d, 32(%rsp)
movl %r8d, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size neuralops_cuda_caffe_avgpool2d_fwd, .Lfunc_end1-neuralops_cuda_caffe_avgpool2d_fwd
.cfi_endproc
# -- End function
.globl _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf # -- Begin function _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.p2align 4, 0x90
.type _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf,@function
_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf: # @_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 208(%rsp), %rax
movq %rax, 128(%rsp)
leaq 216(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf, .Lfunc_end2-_Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.cfi_endproc
# -- End function
.globl neuralops_cuda_caffe_avgpool2d_bwd # -- Begin function neuralops_cuda_caffe_avgpool2d_bwd
.p2align 4, 0x90
.type neuralops_cuda_caffe_avgpool2d_bwd,@function
neuralops_cuda_caffe_avgpool2d_bwd: # @neuralops_cuda_caffe_avgpool2d_bwd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 8(%rsp) # 4-byte Spill
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %r13
movq 368(%rsp), %r9
movl %edx, %eax
imull %esi, %eax
movl %ecx, %ebx
imull %r8d, %ebx
imull %eax, %ebx
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 360(%rsp), %rax
movl 352(%rsp), %ecx
movl 344(%rsp), %edx
movl 336(%rsp), %esi
movl 328(%rsp), %edi
movl 320(%rsp), %r8d
movl 312(%rsp), %r9d
movl 304(%rsp), %r10d
movl %ebx, 60(%rsp)
movq %r13, 120(%rsp)
movl %r12d, 56(%rsp)
movl %r15d, 52(%rsp)
movl %r14d, 48(%rsp)
movl %ebp, 44(%rsp)
movl 8(%rsp), %r11d # 4-byte Reload
movl %r11d, 40(%rsp)
movl %r10d, 36(%rsp)
movl %r9d, 32(%rsp)
movl %r8d, 28(%rsp)
movl %edx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %edi, 16(%rsp)
movl %esi, 12(%rsp)
movq %rax, 112(%rsp)
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 28(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rax
movq %rax, 224(%rsp)
leaq 12(%rsp), %rax
movq %rax, 232(%rsp)
leaq 112(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size neuralops_cuda_caffe_avgpool2d_bwd, .Lfunc_end3-neuralops_cuda_caffe_avgpool2d_bwd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf,@object # @_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.section .rodata,"a",@progbits
.globl _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.p2align 3, 0x0
_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf:
.quad _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.size _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf, 8
.type _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf,@object # @_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.globl _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.p2align 3, 0x0
_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf:
.quad _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.size _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14AvePoolForwardiPKfiiiiiiiiiiiiPf"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__AvePoolForwardiPKfiiiiiiiiiiiiPf
.addrsig_sym _Z30__device_stub__AvePoolBackwardiPKfiiiiiiiiiiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14AvePoolForwardiPKfiiiiiiiiiiiiPf
.addrsig_sym _Z15AvePoolBackwardiPKfiiiiiiiiiiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma once
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, cudaGetErrorString(x));}} while(0) | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, cudaGetErrorString(x));}} while(0) | .file "tmpxft_0016b0a2_00000000-6_macros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
#define CUDA_CALL(x) do { if((x) != cudaSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, cudaGetErrorString(x));}} while(0) | #pragma once
#include <hip/hip_runtime.h>
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, hipGetErrorString(x));}} while(0) |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, hipGetErrorString(x));}} while(0) | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#define CUDA_CALL(x) do { if((x) != hipSuccess) { \
printf("Error at %s:%d -- %s\n",__FILE__,__LINE__, hipGetErrorString(x));}} while(0) | .text
.file "macros.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b0a2_00000000-6_macros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "macros.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
cudaMalloc(&g_indata_device, N * sizeof(float));
cudaMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
cudaMemcpy(g_indata_device, g_indata_host, N * sizeof(float), cudaMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
cudaFree(g_indata_device);
cudaFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} | code for sm_80
Function : _Z7reduce4PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R2, UR5, R7 ; /* 0x0000000502027c24 */
/* 0x001fca000f8e0207 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0005 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*00b0*/ LDG.E.CONSTANT R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e9900 */
/*00c0*/ LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e9900 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00f0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fca0000000000 */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0140*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*0160*/ @!P0 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403028824 */
/* 0x000fe200078e0200 */
/*0170*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x000fe20000004800 */
/*0180*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0190*/ @!P0 LDS R5, [R2] ; /* 0x0000000002058984 */
/* 0x000e240000000800 */
/*01a0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*01b0*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x0001e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 BRA 0x150 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
cudaMalloc(&g_indata_device, N * sizeof(float));
cudaMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
cudaMemcpy(g_indata_device, g_indata_host, N * sizeof(float), cudaMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
cudaFree(g_indata_device);
cudaFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} | .file "tmpxft_00172fee_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce4PfS_PfS_
.type _Z28__device_stub__Z7reduce4PfS_PfS_, @function
_Z28__device_stub__Z7reduce4PfS_PfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce4PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z28__device_stub__Z7reduce4PfS_PfS_, .-_Z28__device_stub__Z7reduce4PfS_PfS_
.globl _Z7reduce4PfS_
.type _Z7reduce4PfS_, @function
_Z7reduce4PfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce4PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z7reduce4PfS_, .-_Z7reduce4PfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time taken by function: "
.LC2:
.string " microseconds"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 400000000(%r12), %rbp
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $400000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390625, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce4PfS_PfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7reduce4PfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce4PfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
cudaMalloc(&g_indata_device, N * sizeof(float));
cudaMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
cudaMemcpy(g_indata_device, g_indata_host, N * sizeof(float), cudaMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
cudaFree(g_indata_device);
cudaFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
hipMalloc(&g_indata_device, N * sizeof(float));
hipMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
hipMemcpy(g_indata_device, g_indata_host, N * sizeof(float), hipMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
hipFree(g_indata_device);
hipFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
hipMalloc(&g_indata_device, N * sizeof(float));
hipMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
hipMemcpy(g_indata_device, g_indata_host, N * sizeof(float), hipMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
hipFree(g_indata_device);
hipFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce4PfS_
.globl _Z7reduce4PfS_
.p2align 8
.type _Z7reduce4PfS_,@function
_Z7reduce4PfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s0
s_cmp_lt_u32 s0, 2
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s0, 4
s_mov_b32 s0, s1
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s1, s0, 1
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s1, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce4PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce4PfS_, .Lfunc_end0-_Z7reduce4PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce4PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce4PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <chrono>
using namespace std::chrono;
__global__ void reduce4(float *g_idata, float *g_odata) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * (blockDim.x * 2) + threadIdx.x;
sdata[tid] = g_idata[i] + g_idata[i + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) { sdata[tid] += sdata[tid + s]; }
__syncthreads();
}
}
int main(void) {
int N = 100000000;
float *g_indata_host, *g_indata_device, *g_outdata_host, *g_outdata_device;
g_indata_host = (float *) malloc(N * sizeof(float));
g_outdata_host = (float *) malloc(sizeof(float));
hipMalloc(&g_indata_device, N * sizeof(float));
hipMalloc(&g_outdata_device, sizeof(float));
for (auto i = 0; i < N; i++) {
g_indata_host[i] = static_cast <float> (rand()) / static_cast <float> (RAND_MAX);;
}
hipMemcpy(g_indata_device, g_indata_host, N * sizeof(float), hipMemcpyHostToDevice);
// This is where the code is run
auto start = high_resolution_clock::now();
reduce4<<<(N + 255) / 256, 256>>>(g_indata_device, g_outdata_device);
auto stop = high_resolution_clock::now();
auto duration = duration_cast<microseconds>(stop - start);
std::cout << "Time taken by function: "
<< duration.count() << " microseconds" << std::endl;
hipFree(g_indata_device);
hipFree(g_outdata_device);
free(g_indata_host);
free(g_outdata_host);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce4PfS_ # -- Begin function _Z22__device_stub__reduce4PfS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce4PfS_,@function
_Z22__device_stub__reduce4PfS_: # @_Z22__device_stub__reduce4PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce4PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce4PfS_, .Lfunc_end0-_Z22__device_stub__reduce4PfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2:
movq (%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390369(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce4PfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $7, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce4PfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce4PfS_,@object # @_Z7reduce4PfS_
.section .rodata,"a",@progbits
.globl _Z7reduce4PfS_
.p2align 3, 0x0
_Z7reduce4PfS_:
.quad _Z22__device_stub__reduce4PfS_
.size _Z7reduce4PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken by function: "
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " microseconds"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce4PfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce4PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce4PfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7reduce4PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0040*/ USHF.L.U32 UR5, UR4, 0x1, URZ ; /* 0x0000000104057899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ IMAD R2, R2, UR5, R7 ; /* 0x0000000502027c24 */
/* 0x001fca000f8e0207 */
/*0080*/ IADD3 R4, R2.reuse, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x040fe20007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0005 */
/*00a0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*00b0*/ LDG.E.CONSTANT R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e9900 */
/*00c0*/ LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e9900 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00f0*/ FADD R0, R4, R3 ; /* 0x0000000304007221 */
/* 0x004fca0000000000 */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0140*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f06070 */
/*0160*/ @!P0 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403028824 */
/* 0x000fe200078e0200 */
/*0170*/ @!P0 LDS R4, [R7.X4] ; /* 0x0000000007048984 */
/* 0x000fe20000004800 */
/*0180*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0190*/ @!P0 LDS R5, [R2] ; /* 0x0000000002058984 */
/* 0x000e240000000800 */
/*01a0*/ @!P0 FADD R4, R4, R5 ; /* 0x0000000504048221 */
/* 0x001fca0000000000 */
/*01b0*/ @!P0 STS [R7.X4], R4 ; /* 0x0000000407008388 */
/* 0x0001e80000004800 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 BRA 0x150 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7reduce4PfS_
.globl _Z7reduce4PfS_
.p2align 8
.type _Z7reduce4PfS_,@function
_Z7reduce4PfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s0
s_cmp_lt_u32 s0, 2
v_lshl_add_u32 v1, s15, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s0, 4
s_mov_b32 s0, s1
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s1, s0, 1
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s1, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7reduce4PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7reduce4PfS_, .Lfunc_end0-_Z7reduce4PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7reduce4PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7reduce4PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00172fee_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7reduce4PfS_PfS_
.type _Z28__device_stub__Z7reduce4PfS_PfS_, @function
_Z28__device_stub__Z7reduce4PfS_PfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7reduce4PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z28__device_stub__Z7reduce4PfS_PfS_, .-_Z28__device_stub__Z7reduce4PfS_PfS_
.globl _Z7reduce4PfS_
.type _Z7reduce4PfS_, @function
_Z7reduce4PfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7reduce4PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z7reduce4PfS_, .-_Z7reduce4PfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time taken by function: "
.LC2:
.string " microseconds"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 400000000(%r12), %rbp
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $400000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390625, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
movq %rdx, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7reduce4PfS_PfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7reduce4PfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7reduce4PfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__reduce4PfS_ # -- Begin function _Z22__device_stub__reduce4PfS_
.p2align 4, 0x90
.type _Z22__device_stub__reduce4PfS_,@function
_Z22__device_stub__reduce4PfS_: # @_Z22__device_stub__reduce4PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7reduce4PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__reduce4PfS_, .Lfunc_end0-_Z22__device_stub__reduce4PfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2:
movq (%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390369(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7reduce4PfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %r14
shrq $63, %r14
sarq $7, %rdx
addq %rdx, %r14
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r14, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6:
movzbl 67(%r15), %eax
jmp .LBB1_8
.LBB1_7:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 128
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7reduce4PfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7reduce4PfS_,@object # @_Z7reduce4PfS_
.section .rodata,"a",@progbits
.globl _Z7reduce4PfS_
.p2align 3, 0x0
_Z7reduce4PfS_:
.quad _Z22__device_stub__reduce4PfS_
.size _Z7reduce4PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken by function: "
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " microseconds"
.size .L.str.1, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7reduce4PfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__reduce4PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7reduce4PfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
cudaMallocManaged(&ptr,size);
printf("do_gpu_cudaMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
cudaHostAlloc(&ptr,size,cudaHostAllocPortable);
printf("do_gpu_cudaHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
cudaGetDeviceCount(&num_gpus);
return num_gpus;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
cudaMallocManaged(&ptr,size);
printf("do_gpu_cudaMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
cudaHostAlloc(&ptr,size,cudaHostAllocPortable);
printf("do_gpu_cudaHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
cudaGetDeviceCount(&num_gpus);
return num_gpus;
} | .file "tmpxft_000128ff_00000000-6_cuda_helpers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "do_gpu_cudaMallocManaged ptr = %lu\n"
.text
.globl do_gpu_cudaMallocManaged
.type do_gpu_cudaMallocManaged, @function
do_gpu_cudaMallocManaged:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size do_gpu_cudaMallocManaged, .-do_gpu_cudaMallocManaged
.globl do_cpu_malloc
.type do_cpu_malloc, @function
do_cpu_malloc:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size do_cpu_malloc, .-do_cpu_malloc
.section .rodata.str1.8
.align 8
.LC2:
.string "do_gpu_cudaHostAlloc ptr = %lu %g [GB]\n"
.text
.globl do_gpu_cudaHostAlloc
.type do_gpu_cudaHostAlloc, @function
do_gpu_cudaHostAlloc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
testq %rbx, %rbx
js .L10
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L11:
mulsd .LC1(%rip), %xmm0
movq (%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L11
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size do_gpu_cudaHostAlloc, .-do_gpu_cudaHostAlloc
.globl get_cuda_num_devices
.type get_cuda_num_devices, @function
get_cuda_num_devices:
.LFB2060:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size get_cuda_num_devices, .-get_cuda_num_devices
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
cudaMallocManaged(&ptr,size);
printf("do_gpu_cudaMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
cudaHostAlloc(&ptr,size,cudaHostAllocPortable);
printf("do_gpu_cudaHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
cudaGetDeviceCount(&num_gpus);
return num_gpus;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
hipMallocManaged(&ptr,size);
printf("do_gpu_hipMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
hipHostAlloc(&ptr,size,hipHostMallocPortable);
printf("do_gpu_hipHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
hipGetDeviceCount(&num_gpus);
return num_gpus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
hipMallocManaged(&ptr,size);
printf("do_gpu_hipMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
hipHostAlloc(&ptr,size,hipHostMallocPortable);
printf("do_gpu_hipHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
hipGetDeviceCount(&num_gpus);
return num_gpus;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" void * do_gpu_cudaMallocManaged(unsigned long int size){
char *ptr;
hipMallocManaged(&ptr,size);
printf("do_gpu_hipMallocManaged ptr = %lu\n",(unsigned long int) ptr);
return (void*) ptr;
}
extern "C" void * do_cpu_malloc(unsigned long int size){
return malloc(size);
}
extern "C" void * do_gpu_cudaHostAlloc(unsigned long int size){
char *ptr;
hipHostAlloc(&ptr,size,hipHostMallocPortable);
printf("do_gpu_hipHostAlloc ptr = %lu %g [GB]\n",(unsigned long int) ptr, (double) size/(1024.0*1024.0*1024.0) );
return (void*) ptr;
}
extern "C" int get_cuda_num_devices(){
int num_gpus;
hipGetDeviceCount(&num_gpus);
return num_gpus;
} | .text
.file "cuda_helpers.hip"
.globl do_gpu_cudaMallocManaged # -- Begin function do_gpu_cudaMallocManaged
.p2align 4, 0x90
.type do_gpu_cudaMallocManaged,@function
do_gpu_cudaMallocManaged: # @do_gpu_cudaMallocManaged
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size do_gpu_cudaMallocManaged, .Lfunc_end0-do_gpu_cudaMallocManaged
.cfi_endproc
# -- End function
.globl do_cpu_malloc # -- Begin function do_cpu_malloc
.p2align 4, 0x90
.type do_cpu_malloc,@function
do_cpu_malloc: # @do_cpu_malloc
.cfi_startproc
# %bb.0:
jmp malloc # TAILCALL
.Lfunc_end1:
.size do_cpu_malloc, .Lfunc_end1-do_cpu_malloc
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function do_gpu_cudaHostAlloc
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl do_gpu_cudaHostAlloc
.p2align 4, 0x90
.type do_gpu_cudaHostAlloc,@function
do_gpu_cudaHostAlloc: # @do_gpu_cudaHostAlloc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipHostAlloc
movq %rbx, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
movq 8(%rsp), %rsi
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size do_gpu_cudaHostAlloc, .Lfunc_end2-do_gpu_cudaHostAlloc
.cfi_endproc
# -- End function
.globl get_cuda_num_devices # -- Begin function get_cuda_num_devices
.p2align 4, 0x90
.type get_cuda_num_devices,@function
get_cuda_num_devices: # @get_cuda_num_devices
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size get_cuda_num_devices, .Lfunc_end3-get_cuda_num_devices
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "do_gpu_hipMallocManaged ptr = %lu\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "do_gpu_hipHostAlloc ptr = %lu %g [GB]\n"
.size .L.str.1, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000128ff_00000000-6_cuda_helpers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "do_gpu_cudaMallocManaged ptr = %lu\n"
.text
.globl do_gpu_cudaMallocManaged
.type do_gpu_cudaMallocManaged, @function
do_gpu_cudaMallocManaged:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size do_gpu_cudaMallocManaged, .-do_gpu_cudaMallocManaged
.globl do_cpu_malloc
.type do_cpu_malloc, @function
do_cpu_malloc:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size do_cpu_malloc, .-do_cpu_malloc
.section .rodata.str1.8
.align 8
.LC2:
.string "do_gpu_cudaHostAlloc ptr = %lu %g [GB]\n"
.text
.globl do_gpu_cudaHostAlloc
.type do_gpu_cudaHostAlloc, @function
do_gpu_cudaHostAlloc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
testq %rbx, %rbx
js .L10
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L11:
mulsd .LC1(%rip), %xmm0
movq (%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L11
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size do_gpu_cudaHostAlloc, .-do_gpu_cudaHostAlloc
.globl get_cuda_num_devices
.type get_cuda_num_devices, @function
get_cuda_num_devices:
.LFB2060:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L18
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size get_cuda_num_devices, .-get_cuda_num_devices
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_helpers.hip"
.globl do_gpu_cudaMallocManaged # -- Begin function do_gpu_cudaMallocManaged
.p2align 4, 0x90
.type do_gpu_cudaMallocManaged,@function
do_gpu_cudaMallocManaged: # @do_gpu_cudaMallocManaged
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size do_gpu_cudaMallocManaged, .Lfunc_end0-do_gpu_cudaMallocManaged
.cfi_endproc
# -- End function
.globl do_cpu_malloc # -- Begin function do_cpu_malloc
.p2align 4, 0x90
.type do_cpu_malloc,@function
do_cpu_malloc: # @do_cpu_malloc
.cfi_startproc
# %bb.0:
jmp malloc # TAILCALL
.Lfunc_end1:
.size do_cpu_malloc, .Lfunc_end1-do_cpu_malloc
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function do_gpu_cudaHostAlloc
.LCPI2_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl do_gpu_cudaHostAlloc
.p2align 4, 0x90
.type do_gpu_cudaHostAlloc,@function
do_gpu_cudaHostAlloc: # @do_gpu_cudaHostAlloc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq %rdi, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %edx
callq hipHostAlloc
movq %rbx, %xmm1
punpckldq .LCPI2_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
movq 8(%rsp), %rsi
subpd .LCPI2_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size do_gpu_cudaHostAlloc, .Lfunc_end2-do_gpu_cudaHostAlloc
.cfi_endproc
# -- End function
.globl get_cuda_num_devices # -- Begin function get_cuda_num_devices
.p2align 4, 0x90
.type get_cuda_num_devices,@function
get_cuda_num_devices: # @get_cuda_num_devices
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size get_cuda_num_devices, .Lfunc_end3-get_cuda_num_devices
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "do_gpu_hipMallocManaged ptr = %lu\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "do_gpu_hipHostAlloc ptr = %lu %g [GB]\n"
.size .L.str.1, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} | code for sm_80
Function : _Z3addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} | .file "tmpxft_00088feb_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_i
.globl _Z3addPfS_S_i
.p2align 8
.type _Z3addPfS_S_i,@function
_Z3addPfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_i, .Lfunc_end0-_Z3addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(float *array_a, float *array_b, float *array_c, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
for (int i = tid; i < size; i += step) {
array_c[i] = array_a[i] + array_b[i];
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_i
.globl _Z3addPfS_S_i
.p2align 8
.type _Z3addPfS_S_i,@function
_Z3addPfS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_i, .Lfunc_end0-_Z3addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00088feb_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} | .file "tmpxft_001aec66_00000000-6_spmv_csr_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} | #include <hip/hip_runtime.h>
/*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*#include <stdio.h>
#include <math.h>
#include <time.h>
#include <iostream>
#include <fstream>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include "book.h"
#include "cusparse.h"
*/
#define BlockDim 1024
template <typename T>
__global__ void spmv_csr_vector_kernel(T * d_val, T * d_vector, int * d_cols, int * d_ptr, int N, T * d_out)
{
// Thread ID in block
int t = threadIdx.x;
// Thread ID in warp
int lane = t & (warpSize - 1);
// Number of warps per block
int warpsPerBlock = blockDim.x / warpSize;
// One row per warp
int row = (blockIdx.x * warpsPerBlock) + (t / warpSize);
__shared__ volatile T vals[BlockDim];
if (row < N)
{
int rowStart = d_ptr[row];
int rowEnd = d_ptr[row + 1];
T sum = 0;
// Use all threads in a warp accumulate multiplied elements
for (int j = rowStart + lane; j < rowEnd; j += warpSize)
{
int col = d_cols[j];
sum += d_val[j] * d_vector[col];
}
vals[t] = sum;
__syncthreads();
// Reduce partial sums
if (lane < 16) vals[t] += vals[t + 16];
if (lane < 8) vals[t] += vals[t + 8];
if (lane < 4) vals[t] += vals[t + 4];
if (lane < 2) vals[t] += vals[t + 2];
if (lane < 1) vals[t] += vals[t + 1];
__syncthreads();
// Write result
if (lane == 0)
{
d_out[row] = vals[t];
}
}
} | .text
.file "spmv_csr_vector.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aec66_00000000-6_spmv_csr_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spmv_csr_vector.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .file "tmpxft_0008e7b4_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L12
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1048576, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 1073741824(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %r13, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $268435456, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPfS_"
.LC7:
.string "device_n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8device_n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8device_n
.comm _ZL8device_n,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected device_n
.type device_n,@object
.section .bss,"aw",@nobits
.globl device_n
.p2align 2, 0x0
device_n:
.long 0
.size device_n, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
__constant__ int device_n;
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// if (threadIdx.x == 0) {
// printf("%d %d %d\n", blockIdx.x, gridDim.x, blockDim.x);
// }
for (int i = index; i < n; i += stride) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $device_n, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type device_n,@object # @device_n
.local device_n
.comm device_n,4,4
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "device_n"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym device_n
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected device_n
.type device_n,@object
.section .bss,"aw",@nobits
.globl device_n
.p2align 2, 0x0
device_n:
.long 0
.size device_n, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008e7b4_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L12
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1048576, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 1073741824(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %r13, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $268435456, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPfS_"
.LC7:
.string "device_n"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8device_n(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8device_n
.comm _ZL8device_n,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_9
# %bb.8:
movzbl 67(%r15), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $device_n, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type device_n,@object # @device_n
.local device_n
.comm device_n,4,4
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "device_n"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym device_n
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
cudaMemcpy(d_a, a, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sizeof(int), cudaMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z7DotProdPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R16, [RZ] ; /* 0x00000000ff107984 */
/* 0x001e220000000c00 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0120*/ LDS.128 R20, [0x10] ; /* 0x00001000ff147984 */
/* 0x000e680000000c00 */
/*0130*/ LDS.128 R4, [0x20] ; /* 0x00002000ff047984 */
/* 0x000ea80000000c00 */
/*0140*/ LDS.128 R24, [0x30] ; /* 0x00003000ff187984 */
/* 0x000ee80000000c00 */
/*0150*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000f280000000c00 */
/*0160*/ LDS.128 R12, [0x50] ; /* 0x00005000ff0c7984 */
/* 0x000f620000000c00 */
/*0170*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x001fc80007ffe010 */
/*0180*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x002fe40007ffe010 */
/*0190*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000e240000000c00 */
/*01a0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*01b0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x004fe40007ffe014 */
/*01c0*/ LDS.128 R20, [0x70] ; /* 0x00007000ff147984 */
/* 0x000e640000000c00 */
/*01d0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*01e0*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x008fe40007ffe004 */
/*01f0*/ LDS.128 R4, [0x80] ; /* 0x00008000ff047984 */
/* 0x000ea40000000c00 */
/*0200*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0210*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x010fe40007ffe018 */
/*0220*/ LDS.128 R24, [0x90] ; /* 0x00009000ff187984 */
/* 0x000ee40000000c00 */
/*0230*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0240*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x020fe40007ffe008 */
/*0250*/ LDS.128 R8, [0xa0] ; /* 0x0000a000ff087984 */
/* 0x000f240000000c00 */
/*0260*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*0270*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x001fe40007ffe00c */
/*0280*/ LDS.128 R12, [0xb0] ; /* 0x0000b000ff0c7984 */
/* 0x000e240000000c00 */
/*0290*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*02a0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x002fe40007ffe010 */
/*02b0*/ LDS.128 R16, [0xc0] ; /* 0x0000c000ff107984 */
/* 0x000e640000000c00 */
/*02c0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*02d0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x004fe40007ffe014 */
/*02e0*/ LDS.128 R20, [0xd0] ; /* 0x0000d000ff147984 */
/* 0x000ea40000000c00 */
/*02f0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0300*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x008fe40007ffe004 */
/*0310*/ LDS.128 R4, [0xe0] ; /* 0x0000e000ff047984 */
/* 0x000ee40000000c00 */
/*0320*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0330*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x010fe40007ffe018 */
/*0340*/ LDS.128 R24, [0xf0] ; /* 0x0000f000ff187984 */
/* 0x000f240000000c00 */
/*0350*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0360*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x001fe40007ffe008 */
/*0370*/ LDS.128 R8, [0x100] ; /* 0x00010000ff087984 */
/* 0x000e240000000c00 */
/*0380*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*0390*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x002fe40007ffe00c */
/*03a0*/ LDS.128 R12, [0x110] ; /* 0x00011000ff0c7984 */
/* 0x000e640000000c00 */
/*03b0*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*03c0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x004fe40007ffe010 */
/*03d0*/ LDS.128 R16, [0x120] ; /* 0x00012000ff107984 */
/* 0x000ea40000000c00 */
/*03e0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*03f0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x008fe40007ffe014 */
/*0400*/ LDS.128 R20, [0x130] ; /* 0x00013000ff147984 */
/* 0x000ee40000000c00 */
/*0410*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0420*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x010fe40007ffe004 */
/*0430*/ LDS.128 R4, [0x140] ; /* 0x00014000ff047984 */
/* 0x000f240000000c00 */
/*0440*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0450*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x001fe40007ffe018 */
/*0460*/ LDS.128 R24, [0x150] ; /* 0x00015000ff187984 */
/* 0x000e240000000c00 */
/*0470*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0480*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x002fe40007ffe008 */
/*0490*/ LDS.128 R8, [0x160] ; /* 0x00016000ff087984 */
/* 0x000e640000000c00 */
/*04a0*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*04b0*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x004fe40007ffe00c */
/*04c0*/ LDS.128 R12, [0x170] ; /* 0x00017000ff0c7984 */
/* 0x000ea40000000c00 */
/*04d0*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*04e0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x008fe40007ffe010 */
/*04f0*/ LDS.128 R16, [0x180] ; /* 0x00018000ff107984 */
/* 0x000ee40000000c00 */
/*0500*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*0510*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x010fc80007ffe014 */
/*0520*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0530*/ IADD3 R4, R24, R7, R4 ; /* 0x0000000718047210 */
/* 0x001fc80007ffe004 */
/*0540*/ IADD3 R4, R26, R25, R4 ; /* 0x000000191a047210 */
/* 0x000fc80007ffe004 */
/*0550*/ IADD3 R4, R8, R27, R4 ; /* 0x0000001b08047210 */
/* 0x002fc80007ffe004 */
/*0560*/ IADD3 R4, R10, R9, R4 ; /* 0x000000090a047210 */
/* 0x000fc80007ffe004 */
/*0570*/ IADD3 R4, R12, R11, R4 ; /* 0x0000000b0c047210 */
/* 0x004fc80007ffe004 */
/*0580*/ IADD3 R4, R14, R13, R4 ; /* 0x0000000d0e047210 */
/* 0x000fc80007ffe004 */
/*0590*/ IADD3 R4, R16, R15, R4 ; /* 0x0000000f10047210 */
/* 0x008fc80007ffe004 */
/*05a0*/ IADD3 R4, R18, R17, R4 ; /* 0x0000001112047210 */
/* 0x000fca0007ffe004 */
/*05b0*/ IMAD.IADD R19, R4, 0x1, R19 ; /* 0x0000000104137824 */
/* 0x000fca00078e0213 */
/*05c0*/ RED.E.ADD.STRONG.GPU [R2.64], R19 ; /* 0x000000130200798e */
/* 0x000fe2000c10e184 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
cudaMemcpy(d_a, a, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sizeof(int), cudaMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00014016_00000000-6_dotprod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
.type _Z30__device_stub__Z7DotProdPiS_S_PiS_S_, @function
_Z30__device_stub__Z7DotProdPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7DotProdPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7DotProdPiS_S_PiS_S_, .-_Z30__device_stub__Z7DotProdPiS_S_PiS_S_
.globl _Z7DotProdPiS_S_
.type _Z7DotProdPiS_S_, @function
_Z7DotProdPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7DotProdPiS_S_, .-_Z7DotProdPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nArray A:\n"
.LC1:
.string "%d "
.LC2:
.string "\nArray B:\n"
.LC3:
.string "\n"
.LC4:
.string "\nLaunching Kernel\n"
.LC5:
.string "\nDot Product is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, 0(%r13)
movl $1, %eax
.L12:
movl %eax, -4(%r12,%rax,4)
leal (%rax,%rax), %edx
movl %edx, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $1001, %rax
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 4000(%r12), %r15
leaq .LC1(%rip), %r14
.L13:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 4000(%rbp), %r15
leaq .LC1(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 0(%r13), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7DotProdPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7DotProdPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
cudaMalloc(&d_a, n);
cudaMalloc(&d_b, n);
cudaMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
cudaMemcpy(d_a, a, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, n, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, sizeof(int), cudaMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
cudaMemcpy(c, d_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
hipMemcpy(d_a, a, n, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, n, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sizeof(int), hipMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
hipMemcpy(d_a, a, n, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, n, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sizeof(int), hipMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7DotProdPiS_S_
.globl _Z7DotProdPiS_S_
.p2align 8
.type _Z7DotProdPiS_S_,@function
_Z7DotProdPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s2, 0x190
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc1 .LBB0_2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7DotProdPiS_S_
.amdhsa_group_segment_fixed_size 400
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7DotProdPiS_S_, .Lfunc_end0-_Z7DotProdPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 400
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7DotProdPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7DotProdPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define SIZE 1000
#define NUM_BLOCKS 10
#define THREADS_PER_BLOCK 100
__global__ void DotProd(int *a, int *b, int *c) {
__shared__ int temp[THREADS_PER_BLOCK];
int x = threadIdx.x + blockDim.x * blockIdx.x;
/*printf("Block ID :%d:\n", blockIdx.x);
printf("Block Dim :%d:\n", blockDim.x);
printf("Theard ID :%d:\n", threadIdx.x);*/
temp[threadIdx.x] = a[x] * b[x];
// printf("Temp:%d\n", temp[threadIdx.x]);
__syncthreads();
if (threadIdx.x == 0)
{
int i,sum = 0;
for (i = 0; i < THREADS_PER_BLOCK; i++)
{
sum += temp[i];
}
// printf("\nSUM[%d]:%d", blockIdx.x, sum);
atomicAdd(c, sum);
}
}
int main() {
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int n = SIZE * sizeof(int);
int i;
// STEP 1 : Allocate memory for Host and Device variables
a = (int*)malloc(n);
b = (int*)malloc(n);
c = (int*)malloc(sizeof(int));
hipMalloc(&d_a, n);
hipMalloc(&d_b, n);
hipMalloc(&d_c, sizeof(int));
// STEP 2: Initialize Host variables
*c = 0;
for (i = 0; i < SIZE; i++) {
a[i] = i + 1;
b[i] = 2 * (i + 1);
}
// Display the values of the arrays
printf("\nArray A:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", a[i]);
}
printf("\nArray B:\n");
for (i = 0; i < SIZE; i++) {
printf("%d ", b[i]);
}
printf("\n");
// STEP 3: Copy data to device variables.
hipMemcpy(d_a, a, n, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, n, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, sizeof(int), hipMemcpyHostToDevice);
// STEP 4: Launch the Kernel
printf("\nLaunching Kernel\n");
DotProd <<<NUM_BLOCKS, THREADS_PER_BLOCK>>> (d_a, d_b, d_c);
//STEP 5: Copy results from device to Host.
hipMemcpy(c, d_c, sizeof(int), hipMemcpyDeviceToHost);
printf("\nDot Product is: %d\n", *c);
//STEP 6: Free Memory
free(a); free(b); free(c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "dotprod.hip"
.globl _Z22__device_stub__DotProdPiS_S_ # -- Begin function _Z22__device_stub__DotProdPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__DotProdPiS_S_,@function
_Z22__device_stub__DotProdPiS_S_: # @_Z22__device_stub__DotProdPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7DotProdPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__DotProdPiS_S_, .Lfunc_end0-_Z22__device_stub__DotProdPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $0, (%r15)
movl $2, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
addl $2, %eax
movq %rdx, %rcx
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 90(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7DotProdPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7DotProdPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7DotProdPiS_S_,@object # @_Z7DotProdPiS_S_
.section .rodata,"a",@progbits
.globl _Z7DotProdPiS_S_
.p2align 3, 0x0
_Z7DotProdPiS_S_:
.quad _Z22__device_stub__DotProdPiS_S_
.size _Z7DotProdPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nDot Product is: %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7DotProdPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nArray A:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nArray B:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nLaunching Kernel"
.size .Lstr.2, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__DotProdPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7DotProdPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7DotProdPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R7 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0203 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R16, [RZ] ; /* 0x00000000ff107984 */
/* 0x001e220000000c00 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fc400078e00ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0120*/ LDS.128 R20, [0x10] ; /* 0x00001000ff147984 */
/* 0x000e680000000c00 */
/*0130*/ LDS.128 R4, [0x20] ; /* 0x00002000ff047984 */
/* 0x000ea80000000c00 */
/*0140*/ LDS.128 R24, [0x30] ; /* 0x00003000ff187984 */
/* 0x000ee80000000c00 */
/*0150*/ LDS.128 R8, [0x40] ; /* 0x00004000ff087984 */
/* 0x000f280000000c00 */
/*0160*/ LDS.128 R12, [0x50] ; /* 0x00005000ff0c7984 */
/* 0x000f620000000c00 */
/*0170*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x001fc80007ffe010 */
/*0180*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x002fe40007ffe010 */
/*0190*/ LDS.128 R16, [0x60] ; /* 0x00006000ff107984 */
/* 0x000e240000000c00 */
/*01a0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*01b0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x004fe40007ffe014 */
/*01c0*/ LDS.128 R20, [0x70] ; /* 0x00007000ff147984 */
/* 0x000e640000000c00 */
/*01d0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*01e0*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x008fe40007ffe004 */
/*01f0*/ LDS.128 R4, [0x80] ; /* 0x00008000ff047984 */
/* 0x000ea40000000c00 */
/*0200*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0210*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x010fe40007ffe018 */
/*0220*/ LDS.128 R24, [0x90] ; /* 0x00009000ff187984 */
/* 0x000ee40000000c00 */
/*0230*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0240*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x020fe40007ffe008 */
/*0250*/ LDS.128 R8, [0xa0] ; /* 0x0000a000ff087984 */
/* 0x000f240000000c00 */
/*0260*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*0270*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x001fe40007ffe00c */
/*0280*/ LDS.128 R12, [0xb0] ; /* 0x0000b000ff0c7984 */
/* 0x000e240000000c00 */
/*0290*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*02a0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x002fe40007ffe010 */
/*02b0*/ LDS.128 R16, [0xc0] ; /* 0x0000c000ff107984 */
/* 0x000e640000000c00 */
/*02c0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*02d0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x004fe40007ffe014 */
/*02e0*/ LDS.128 R20, [0xd0] ; /* 0x0000d000ff147984 */
/* 0x000ea40000000c00 */
/*02f0*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0300*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x008fe40007ffe004 */
/*0310*/ LDS.128 R4, [0xe0] ; /* 0x0000e000ff047984 */
/* 0x000ee40000000c00 */
/*0320*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0330*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x010fe40007ffe018 */
/*0340*/ LDS.128 R24, [0xf0] ; /* 0x0000f000ff187984 */
/* 0x000f240000000c00 */
/*0350*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0360*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x001fe40007ffe008 */
/*0370*/ LDS.128 R8, [0x100] ; /* 0x00010000ff087984 */
/* 0x000e240000000c00 */
/*0380*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*0390*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x002fe40007ffe00c */
/*03a0*/ LDS.128 R12, [0x110] ; /* 0x00011000ff0c7984 */
/* 0x000e640000000c00 */
/*03b0*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*03c0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x004fe40007ffe010 */
/*03d0*/ LDS.128 R16, [0x120] ; /* 0x00012000ff107984 */
/* 0x000ea40000000c00 */
/*03e0*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*03f0*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x008fe40007ffe014 */
/*0400*/ LDS.128 R20, [0x130] ; /* 0x00013000ff147984 */
/* 0x000ee40000000c00 */
/*0410*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0420*/ IADD3 R24, R24, R7, R4 ; /* 0x0000000718187210 */
/* 0x010fe40007ffe004 */
/*0430*/ LDS.128 R4, [0x140] ; /* 0x00014000ff047984 */
/* 0x000f240000000c00 */
/*0440*/ IADD3 R24, R26, R25, R24 ; /* 0x000000191a187210 */
/* 0x000fc80007ffe018 */
/*0450*/ IADD3 R8, R8, R27, R24 ; /* 0x0000001b08087210 */
/* 0x001fe40007ffe018 */
/*0460*/ LDS.128 R24, [0x150] ; /* 0x00015000ff187984 */
/* 0x000e240000000c00 */
/*0470*/ IADD3 R8, R10, R9, R8 ; /* 0x000000090a087210 */
/* 0x000fc80007ffe008 */
/*0480*/ IADD3 R12, R12, R11, R8 ; /* 0x0000000b0c0c7210 */
/* 0x002fe40007ffe008 */
/*0490*/ LDS.128 R8, [0x160] ; /* 0x00016000ff087984 */
/* 0x000e640000000c00 */
/*04a0*/ IADD3 R12, R14, R13, R12 ; /* 0x0000000d0e0c7210 */
/* 0x000fc80007ffe00c */
/*04b0*/ IADD3 R16, R16, R15, R12 ; /* 0x0000000f10107210 */
/* 0x004fe40007ffe00c */
/*04c0*/ LDS.128 R12, [0x170] ; /* 0x00017000ff0c7984 */
/* 0x000ea40000000c00 */
/*04d0*/ IADD3 R16, R18, R17, R16 ; /* 0x0000001112107210 */
/* 0x000fc80007ffe010 */
/*04e0*/ IADD3 R20, R20, R19, R16 ; /* 0x0000001314147210 */
/* 0x008fe40007ffe010 */
/*04f0*/ LDS.128 R16, [0x180] ; /* 0x00018000ff107984 */
/* 0x000ee40000000c00 */
/*0500*/ IADD3 R20, R22, R21, R20 ; /* 0x0000001516147210 */
/* 0x000fc80007ffe014 */
/*0510*/ IADD3 R4, R4, R23, R20 ; /* 0x0000001704047210 */
/* 0x010fc80007ffe014 */
/*0520*/ IADD3 R4, R6, R5, R4 ; /* 0x0000000506047210 */
/* 0x000fc80007ffe004 */
/*0530*/ IADD3 R4, R24, R7, R4 ; /* 0x0000000718047210 */
/* 0x001fc80007ffe004 */
/*0540*/ IADD3 R4, R26, R25, R4 ; /* 0x000000191a047210 */
/* 0x000fc80007ffe004 */
/*0550*/ IADD3 R4, R8, R27, R4 ; /* 0x0000001b08047210 */
/* 0x002fc80007ffe004 */
/*0560*/ IADD3 R4, R10, R9, R4 ; /* 0x000000090a047210 */
/* 0x000fc80007ffe004 */
/*0570*/ IADD3 R4, R12, R11, R4 ; /* 0x0000000b0c047210 */
/* 0x004fc80007ffe004 */
/*0580*/ IADD3 R4, R14, R13, R4 ; /* 0x0000000d0e047210 */
/* 0x000fc80007ffe004 */
/*0590*/ IADD3 R4, R16, R15, R4 ; /* 0x0000000f10047210 */
/* 0x008fc80007ffe004 */
/*05a0*/ IADD3 R4, R18, R17, R4 ; /* 0x0000001112047210 */
/* 0x000fca0007ffe004 */
/*05b0*/ IMAD.IADD R19, R4, 0x1, R19 ; /* 0x0000000104137824 */
/* 0x000fca00078e0213 */
/*05c0*/ RED.E.ADD.STRONG.GPU [R2.64], R19 ; /* 0x000000130200798e */
/* 0x000fe2000c10e184 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7DotProdPiS_S_
.globl _Z7DotProdPiS_S_
.p2align 8
.type _Z7DotProdPiS_S_,@function
_Z7DotProdPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v3
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s2, 0x190
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc1 .LBB0_2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7DotProdPiS_S_
.amdhsa_group_segment_fixed_size 400
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7DotProdPiS_S_, .Lfunc_end0-_Z7DotProdPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 400
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7DotProdPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7DotProdPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014016_00000000-6_dotprod.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
.type _Z30__device_stub__Z7DotProdPiS_S_PiS_S_, @function
_Z30__device_stub__Z7DotProdPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7DotProdPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7DotProdPiS_S_PiS_S_, .-_Z30__device_stub__Z7DotProdPiS_S_PiS_S_
.globl _Z7DotProdPiS_S_
.type _Z7DotProdPiS_S_, @function
_Z7DotProdPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7DotProdPiS_S_, .-_Z7DotProdPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nArray A:\n"
.LC1:
.string "%d "
.LC2:
.string "\nArray B:\n"
.LC3:
.string "\n"
.LC4:
.string "\nLaunching Kernel\n"
.LC5:
.string "\nDot Product is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, 0(%r13)
movl $1, %eax
.L12:
movl %eax, -4(%r12,%rax,4)
leal (%rax,%rax), %edx
movl %edx, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $1001, %rax
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 4000(%r12), %r15
leaq .LC1(%rip), %r14
.L13:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 4000(%rbp), %r15
leaq .LC1(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 0(%r13), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7DotProdPiS_S_PiS_S_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7DotProdPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7DotProdPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dotprod.hip"
.globl _Z22__device_stub__DotProdPiS_S_ # -- Begin function _Z22__device_stub__DotProdPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__DotProdPiS_S_,@function
_Z22__device_stub__DotProdPiS_S_: # @_Z22__device_stub__DotProdPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7DotProdPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__DotProdPiS_S_, .Lfunc_end0-_Z22__device_stub__DotProdPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $0, (%r15)
movl $2, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movl %eax, (%r14,%rcx,4)
addl $2, %eax
movq %rdx, %rcx
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 90(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7DotProdPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7DotProdPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7DotProdPiS_S_,@object # @_Z7DotProdPiS_S_
.section .rodata,"a",@progbits
.globl _Z7DotProdPiS_S_
.p2align 3, 0x0
_Z7DotProdPiS_S_:
.quad _Z22__device_stub__DotProdPiS_S_
.size _Z7DotProdPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nDot Product is: %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7DotProdPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nArray A:"
.size .Lstr, 10
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nArray B:"
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nLaunching Kernel"
.size .Lstr.2, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__DotProdPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7DotProdPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | .file "tmpxft_000e1f9b_00000000-6_prac6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " n, x = %d %f \n"
.text
.globl _Z5prac6ii
.type _Z5prac6ii, @function
_Z5prac6ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %r15d
imull %esi, %r15d
movslq %r15d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L13
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L14
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L12
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5prac6ii, .-_Z5prac6ii
.section .rodata.str1.1
.LC1:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
cudaMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
cudaMemcpy(h_x,d_x,nsize*sizeof(float),cudaMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
cudaFree(d_x);
free(h_x);
return 0;
} | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15my_first_kernelPf
.globl _Z15my_first_kernelPf
.p2align 8
.type _Z15my_first_kernelPf,@function
_Z15my_first_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// include files
//
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
//
// kernel routine
//
__global__ void my_first_kernel(float *x)
{
int tid = threadIdx.x + blockDim.x*blockIdx.x;
x[tid] = threadIdx.x;
}
//
// CUDA routine to be called by main code
//
extern
int prac6(int nblocks, int nthreads)
{
float *h_x, *d_x;
int nsize, n;
// allocate memory for arrays
nsize = nblocks*nthreads ;
h_x = (float *)malloc(nsize*sizeof(float));
hipMalloc((void **)&d_x, nsize*sizeof(float));
// execute kernel
my_first_kernel<<<nblocks,nthreads>>>(d_x);
// copy back results and print them out
hipMemcpy(h_x,d_x,nsize*sizeof(float),hipMemcpyDeviceToHost);
for (n=0; n<nsize; n++) printf(" n, x = %d %f \n",n,h_x[n]);
// free memory
hipFree(d_x);
free(h_x);
return 0;
} | .text
.file "prac6.hip"
.globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelPf,@function
_Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf
.cfi_endproc
# -- End function
.globl _Z5prac6ii # -- Begin function _Z5prac6ii
.p2align 4, 0x90
.type _Z5prac6ii,@function
_Z5prac6ii: # @_Z5prac6ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %r12d
imull %edi, %r12d
movslq %r12d, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebp, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %r12d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5prac6ii, .Lfunc_end1-_Z5prac6ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf
.section .rodata,"a",@progbits
.globl _Z15my_first_kernelPf
.p2align 3, 0x0
_Z15my_first_kernelPf:
.quad _Z30__device_stub__my_first_kernelPf
.size _Z15my_first_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " n, x = %d %f \n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelPf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15my_first_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ I2F.U32 R5, R0 ; /* 0x0000000000057306 */
/* 0x001e220000201000 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0207 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15my_first_kernelPf
.globl _Z15my_first_kernelPf
.p2align 8
.type _Z15my_first_kernelPf,@function
_Z15my_first_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_cvt_f32_u32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15my_first_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15my_first_kernelPf, .Lfunc_end0-_Z15my_first_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15my_first_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15my_first_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e1f9b_00000000-6_prac6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15my_first_kernelPfPf
.type _Z35__device_stub__Z15my_first_kernelPfPf, @function
_Z35__device_stub__Z15my_first_kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15my_first_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z15my_first_kernelPfPf, .-_Z35__device_stub__Z15my_first_kernelPfPf
.globl _Z15my_first_kernelPf
.type _Z15my_first_kernelPf, @function
_Z15my_first_kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15my_first_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15my_first_kernelPf, .-_Z15my_first_kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " n, x = %d %f \n"
.text
.globl _Z5prac6ii
.type _Z5prac6ii, @function
_Z5prac6ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebx
movl %esi, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %r15d
imull %esi, %r15d
movslq %r15d, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %r13d, 28(%rsp)
movl $1, 32(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L13
movl $0, %ebx
leaq .LC0(%rip), %r13
.L14:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L14
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z35__device_stub__Z15my_first_kernelPfPf
jmp .L12
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z5prac6ii, .-_Z5prac6ii
.section .rodata.str1.1
.LC1:
.string "_Z15my_first_kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15my_first_kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prac6.hip"
.globl _Z30__device_stub__my_first_kernelPf # -- Begin function _Z30__device_stub__my_first_kernelPf
.p2align 4, 0x90
.type _Z30__device_stub__my_first_kernelPf,@function
_Z30__device_stub__my_first_kernelPf: # @_Z30__device_stub__my_first_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15my_first_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__my_first_kernelPf, .Lfunc_end0-_Z30__device_stub__my_first_kernelPf
.cfi_endproc
# -- End function
.globl _Z5prac6ii # -- Begin function _Z5prac6ii
.p2align 4, 0x90
.type _Z5prac6ii,@function
_Z5prac6ii: # @_Z5prac6ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %r12d
imull %edi, %r12d
movslq %r12d, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %ebp, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15my_first_kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %r12d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_4
.LBB1_5: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5prac6ii, .Lfunc_end1-_Z5prac6ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15my_first_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15my_first_kernelPf,@object # @_Z15my_first_kernelPf
.section .rodata,"a",@progbits
.globl _Z15my_first_kernelPf
.p2align 3, 0x0
_Z15my_first_kernelPf:
.quad _Z30__device_stub__my_first_kernelPf
.size _Z15my_first_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " n, x = %d %f \n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15my_first_kernelPf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__my_first_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15my_first_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
cudaEvent_t start, stop; //time start and stop
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( cudaMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( cudaMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( cudaMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
cudaEventRecord( stop, 0 );
cudaEventSynchronize(stop);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( cudaMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), cudaMemcpyDeviceToHost) );
// Free out memory
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z10stencil_1dPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fc800078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80402058981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+0x200] ; /* 0x0002000402068981 */
/* 0x000f22000c1e1900 */
/*00b0*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fc60000011400 */
/*00c0*/ STS [R13.X4+0x8], R4 ; /* 0x000008040d007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4], R5 ; /* 0x000000050d008388 */
/* 0x008fe80000004800 */
/*00e0*/ @!P0 STS [R13.X4+0x208], R6 ; /* 0x000208060d008388 */
/* 0x010fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R0, c[0x0][0x16c], R15, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f140f */
/*0120*/ LDS R7, [R13.X4+0x4] ; /* 0x000004000d077984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R8, [R13.X4] ; /* 0x000000000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+0x8] ; /* 0x000008000d097984 */
/* 0x000e280000004800 */
/*0150*/ LDS R10, [R13.X4+0xc] ; /* 0x00000c000d0a7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R13.X4+0x10] ; /* 0x000010000d0b7984 */
/* 0x000e620000004800 */
/*0170*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*0180*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fca0007ffe007 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
cudaEvent_t start, stop; //time start and stop
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( cudaMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( cudaMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( cudaMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
cudaEventRecord( stop, 0 );
cudaEventSynchronize(stop);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( cudaMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), cudaMemcpyDeviceToHost) );
// Free out memory
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | .file "tmpxft_001407f7_00000000-6_1D_Stencil_SharedMem.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10stencil_1dPiS_PiS_
.type _Z32__device_stub__Z10stencil_1dPiS_PiS_, @function
_Z32__device_stub__Z10stencil_1dPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_1dPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10stencil_1dPiS_PiS_, .-_Z32__device_stub__Z10stencil_1dPiS_PiS_
.globl _Z10stencil_1dPiS_
.type _Z10stencil_1dPiS_, @function
_Z10stencil_1dPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_1dPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10stencil_1dPiS_, .-_Z10stencil_1dPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anerisheth19/1D-Stencil-on-GPU--CUDA/master/1D_Stencil_SharedMem.cu"
.section .rodata.str1.1
.LC2:
.string "GPU Execution Time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4000, %rsp
.cfi_def_cfa_offset 8112
movq %fs:40, %rax
movq %rax, 8088(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 4064(%rsp), %rax
leaq 8080(%rsp), %rdx
.L18:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
leaq 8(%rsp), %rdi
movl $4016, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $71, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $72, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 4064(%rsp), %rsi
movl $1, %ecx
movl $4016, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $75, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $89, %edx
leaq .LC1(%rip), %rsi
call _ZL11handleError9cudaErrorPKci
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8088(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $8096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10stencil_1dPiS_PiS_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10stencil_1dPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
cudaEvent_t start, stop; //time start and stop
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( cudaMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( cudaMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( cudaMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), cudaMemcpyHostToDevice) );
cudaEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
cudaEventRecord( stop, 0 );
cudaEventSynchronize(stop);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start );
cudaEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( cudaMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), cudaMemcpyDeviceToHost) );
// Free out memory
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( hipMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( hipMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( hipMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( hipMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), hipMemcpyDeviceToHost) );
// Free out memory
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( hipMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( hipMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( hipMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( hipMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), hipMemcpyDeviceToHost) );
// Free out memory
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_
.globl _Z10stencil_1dPiS_
.p2align 8
.type _Z10stencil_1dPiS_,@function
_Z10stencil_1dPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:8
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-8
global_load_b32 v3, v[3:4], off offset:512
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:130
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 20
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_
.amdhsa_group_segment_fixed_size 528
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_, .Lfunc_end0-_Z10stencil_1dPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 528
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //ECGR 6090 Heterogeneous Computing Homework 0
// Problem 2 c - 1D Stencil on GPU with shared memory
//Written by Aneri Sheth - 801085402
// Reference taken from Lecture Slides by Dr. Tabkhi
//Other reference taken from https://github.com/szymonm/pwir-cuda-labs/tree/master/lab1 and https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#using-cuda-gpu-timers
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define RADIUS 2 //radius = 2,4,8,16
#define BLOCK_SIZE 128 //fixed number of threads per block
#define NUM_ELEMENTS 1000 //job size = 1K, 10K, 100K, 1M and 10M
// CUDA API error checking macro
static void handleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ),
file, line );
exit( EXIT_FAILURE );
}
}
#define cudaCheck( err ) (handleError( err, __FILE__, __LINE__ ))
__global__ void stencil_1d(int *in, int *out)
{
__shared__ int temp[BLOCK_SIZE + 2 * RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + RADIUS;
temp[lindex] = in[gindex]; //storing in shared memory
if (threadIdx.x < RADIUS)
{
temp[lindex - RADIUS] = in[gindex - RADIUS];
temp[lindex + BLOCK_SIZE] = in[gindex + BLOCK_SIZE];
}
__syncthreads();
int result = 0;
for (int offset = -RADIUS ; offset <= RADIUS ; offset++)
{
result += temp[lindex + offset];
}
// Store the result
out[gindex] = result;
}
int main()
{
unsigned int i;
//CPU array copies
int h_in[NUM_ELEMENTS + 2 * RADIUS], h_out[NUM_ELEMENTS];
//GPU array copies
int *d_in, *d_out;
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
for( i = 0; i < (NUM_ELEMENTS + 2*RADIUS); ++i )
h_in[i] = 1;
// Allocate device memory
cudaCheck( hipMalloc( &d_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int)) );
cudaCheck( hipMalloc( &d_out, NUM_ELEMENTS * sizeof(int)) );
//copy fro CPU to GPU memory
cudaCheck( hipMemcpy( d_in, h_in, (NUM_ELEMENTS + 2*RADIUS) * sizeof(int), hipMemcpyHostToDevice) );
hipEventRecord( start, 0 );
//Call stencil kernel
stencil_1d<<< (NUM_ELEMENTS + BLOCK_SIZE - 1)/BLOCK_SIZE, BLOCK_SIZE >>> (d_in, d_out);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start );
hipEventDestroy( stop );
printf("GPU Execution Time = %f\n",time);
//copy from device to host
cudaCheck( hipMemcpy( h_out, d_out, NUM_ELEMENTS * sizeof(int), hipMemcpyDeviceToHost) );
// Free out memory
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "1D_Stencil_SharedMem.hip"
.globl _Z25__device_stub__stencil_1dPiS_ # -- Begin function _Z25__device_stub__stencil_1dPiS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_,@function
_Z25__device_stub__stencil_1dPiS_: # @_Z25__device_stub__stencil_1dPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_1dPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $8120, %rsp # imm = 0x1FB8
.cfi_def_cfa_offset 8128
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 4096(%rsp,%rax,4)
incq %rax
cmpq $1004, %rax # imm = 0x3EC
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4016, %esi # imm = 0xFB0
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_ZL11handleError10hipError_tPKci.exit
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL11handleError10hipError_tPKci.exit6
movq 24(%rsp), %rdi
leaq 4096(%rsp), %rsi
movl $4016, %edx # imm = 0xFB0
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL11handleError10hipError_tPKci.exit8
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 120(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencil_1dPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11handleError10hipError_tPKci.exit10
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8120, %rsp # imm = 0x1FB8
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 8128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $73, %ecx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_4
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $91, %ecx
.LBB1_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_,@object # @_Z10stencil_1dPiS_
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_
.p2align 3, 0x0
_Z10stencil_1dPiS_:
.quad _Z25__device_stub__stencil_1dPiS_
.size _Z10stencil_1dPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anerisheth19/1D-Stencil-on-GPU--CUDA/master/1D_Stencil_SharedMem.hip"
.size .L.str, 126
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time = %f\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10stencil_1dPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R13, 0x2, PT ; /* 0x000000020d00780c */
/* 0x001fe20003f06070 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fc800078e020d */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80402058981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R6, [R2.64+0x200] ; /* 0x0002000402068981 */
/* 0x000f22000c1e1900 */
/*00b0*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fc60000011400 */
/*00c0*/ STS [R13.X4+0x8], R4 ; /* 0x000008040d007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [R13.X4], R5 ; /* 0x000000050d008388 */
/* 0x008fe80000004800 */
/*00e0*/ @!P0 STS [R13.X4+0x208], R6 ; /* 0x000208060d008388 */
/* 0x010fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R3, R0, c[0x0][0x16c], R15, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe200000f140f */
/*0120*/ LDS R7, [R13.X4+0x4] ; /* 0x000004000d077984 */
/* 0x000fe80000004800 */
/*0130*/ LDS R8, [R13.X4] ; /* 0x000000000d087984 */
/* 0x000fe80000004800 */
/*0140*/ LDS R9, [R13.X4+0x8] ; /* 0x000008000d097984 */
/* 0x000e280000004800 */
/*0150*/ LDS R10, [R13.X4+0xc] ; /* 0x00000c000d0a7984 */
/* 0x000fe80000004800 */
/*0160*/ LDS R11, [R13.X4+0x10] ; /* 0x000010000d0b7984 */
/* 0x000e620000004800 */
/*0170*/ IADD3 R7, R9, R7, R8 ; /* 0x0000000709077210 */
/* 0x001fc80007ffe008 */
/*0180*/ IADD3 R7, R11, R10, R7 ; /* 0x0000000a0b077210 */
/* 0x002fca0007ffe007 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10stencil_1dPiS_
.globl _Z10stencil_1dPiS_
.p2align 8
.type _Z10stencil_1dPiS_,@function
_Z10stencil_1dPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v6 offset:8
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v0, v[3:4], off offset:-8
global_load_b32 v3, v[3:4], off offset:512
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v5, v0, v3 offset1:130
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v3, s2, v5
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 20
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v3, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10stencil_1dPiS_
.amdhsa_group_segment_fixed_size 528
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10stencil_1dPiS_, .Lfunc_end0-_Z10stencil_1dPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 528
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10stencil_1dPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10stencil_1dPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001407f7_00000000-6_1D_Stencil_SharedMem.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10stencil_1dPiS_PiS_
.type _Z32__device_stub__Z10stencil_1dPiS_PiS_, @function
_Z32__device_stub__Z10stencil_1dPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10stencil_1dPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z10stencil_1dPiS_PiS_, .-_Z32__device_stub__Z10stencil_1dPiS_PiS_
.globl _Z10stencil_1dPiS_
.type _Z10stencil_1dPiS_, @function
_Z10stencil_1dPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10stencil_1dPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10stencil_1dPiS_, .-_Z10stencil_1dPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anerisheth19/1D-Stencil-on-GPU--CUDA/master/1D_Stencil_SharedMem.cu"
.section .rodata.str1.1
.LC2:
.string "GPU Execution Time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4000, %rsp
.cfi_def_cfa_offset 8112
movq %fs:40, %rax
movq %rax, 8088(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 4064(%rsp), %rax
leaq 8080(%rsp), %rdx
.L18:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
leaq 8(%rsp), %rdi
movl $4016, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $71, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $72, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 4064(%rsp), %rsi
movl $1, %ecx
movl $4016, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $75, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $89, %edx
leaq .LC1(%rip), %rsi
call _ZL11handleError9cudaErrorPKci
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8088(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $8096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z10stencil_1dPiS_PiS_
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10stencil_1dPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10stencil_1dPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1D_Stencil_SharedMem.hip"
.globl _Z25__device_stub__stencil_1dPiS_ # -- Begin function _Z25__device_stub__stencil_1dPiS_
.p2align 4, 0x90
.type _Z25__device_stub__stencil_1dPiS_,@function
_Z25__device_stub__stencil_1dPiS_: # @_Z25__device_stub__stencil_1dPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10stencil_1dPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__stencil_1dPiS_, .Lfunc_end0-_Z25__device_stub__stencil_1dPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $8120, %rsp # imm = 0x1FB8
.cfi_def_cfa_offset 8128
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, 4096(%rsp,%rax,4)
incq %rax
cmpq $1004, %rax # imm = 0x3EC
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4016, %esi # imm = 0xFB0
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_ZL11handleError10hipError_tPKci.exit
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZL11handleError10hipError_tPKci.exit6
movq 24(%rsp), %rdi
leaq 4096(%rsp), %rsi
movl $4016, %edx # imm = 0xFB0
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_ZL11handleError10hipError_tPKci.exit8
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 120(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10stencil_1dPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_ZL11handleError10hipError_tPKci.exit10
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8120, %rsp # imm = 0x1FB8
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 8128
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $73, %ecx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $74, %ecx
jmp .LBB1_4
.LBB1_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $77, %ecx
jmp .LBB1_4
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $91, %ecx
.LBB1_4:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10stencil_1dPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10stencil_1dPiS_,@object # @_Z10stencil_1dPiS_
.section .rodata,"a",@progbits
.globl _Z10stencil_1dPiS_
.p2align 3, 0x0
_Z10stencil_1dPiS_:
.quad _Z25__device_stub__stencil_1dPiS_
.size _Z10stencil_1dPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anerisheth19/1D-Stencil-on-GPU--CUDA/master/1D_Stencil_SharedMem.hip"
.size .L.str, 126
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time = %f\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s in %s at line %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10stencil_1dPiS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__stencil_1dPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10stencil_1dPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ double2 pow(double2 a, int b){
double r = sqrt(a.x*a.x + a.y*a.y);
double theta = atan(a.y / a.x);
return{pow(r,b)*cos(b*theta),pow(r,b)*sin(b*theta)};
}
__global__ void pow_test(double2 *a, int b, double2 *c){
c[0] = pow(a[0],b);
} | .file "tmpxft_0000d26e_00000000-6_pow_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3pow7double2i
.type _Z3pow7double2i, @function
_Z3pow7double2i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3pow7double2i, .-_Z3pow7double2i
.globl _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
.type _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_, @function
_Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8pow_testP7double2iS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_, .-_Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
.globl _Z8pow_testP7double2iS0_
.type _Z8pow_testP7double2iS0_, @function
_Z8pow_testP7double2iS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8pow_testP7double2iS0_, .-_Z8pow_testP7double2iS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8pow_testP7double2iS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8pow_testP7double2iS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ double2 pow(double2 a, int b){
double r = sqrt(a.x*a.x + a.y*a.y);
double theta = atan(a.y / a.x);
return{pow(r,b)*cos(b*theta),pow(r,b)*sin(b*theta)};
}
__global__ void pow_test(double2 *a, int b, double2 *c){
c[0] = pow(a[0],b);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double2 pow(double2 a, int b){
double r = sqrt(a.x*a.x + a.y*a.y);
double theta = atan(a.y / a.x);
return{pow(r,b)*cos(b*theta),pow(r,b)*sin(b*theta)};
}
__global__ void pow_test(double2 *a, int b, double2 *c){
c[0] = pow(a[0],b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double2 pow(double2 a, int b){
double r = sqrt(a.x*a.x + a.y*a.y);
double theta = atan(a.y / a.x);
return{pow(r,b)*cos(b*theta),pow(r,b)*sin(b*theta)};
}
__global__ void pow_test(double2 *a, int b, double2 *c){
c[0] = pow(a[0],b);
} | .text
.file "pow_test.hip"
.globl _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_ # -- Begin function _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.p2align 4, 0x90
.type _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_,@function
_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_: # @_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_, .Lfunc_end0-_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_,@object # @_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.section .rodata,"a",@progbits
.globl _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.p2align 3, 0x0
_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_:
.quad _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.size _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d26e_00000000-6_pow_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3pow7double2i
.type _Z3pow7double2i, @function
_Z3pow7double2i:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3pow7double2i, .-_Z3pow7double2i
.globl _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
.type _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_, @function
_Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8pow_testP7double2iS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_, .-_Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
.globl _Z8pow_testP7double2iS0_
.type _Z8pow_testP7double2iS0_, @function
_Z8pow_testP7double2iS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z8pow_testP7double2iS0_P7double2iS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8pow_testP7double2iS0_, .-_Z8pow_testP7double2iS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8pow_testP7double2iS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8pow_testP7double2iS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pow_test.hip"
.globl _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_ # -- Begin function _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.p2align 4, 0x90
.type _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_,@function
_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_: # @_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_, .Lfunc_end0-_Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_,@object # @_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.section .rodata,"a",@progbits
.globl _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.p2align 3, 0x0
_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_:
.quad _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.size _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8pow_testP15HIP_vector_typeIdLj2EEiS1_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__pow_testP15HIP_vector_typeIdLj2EEiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8pow_testP15HIP_vector_typeIdLj2EEiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void aKernel()
{
int idx = threadIdx.x;
int r1, r2, res_diff;
__shared__ int arr[512];
arr[idx] = idx;
printf("A: Thread %5d, value %5d\n", idx, arr[idx]);
__syncthreads();
r1 = arr[idx];
if (idx < 511) {
int temp = arr[idx + 1];
__syncthreads();
arr[idx] = temp;
}
r2 = arr[idx];
res_diff = r2 - r1;
printf("B: Thread %5d, value %5d, diff=%5d\n", idx, arr[idx], res_diff);
}
int main()
{
aKernel<<<1, 512>>> ();
return 0;
} | code for sm_80
Function : _Z7aKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0060*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0070*/ IADD3 R16, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001107a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R17, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff117624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0011 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff037224 */
/* 0x001fe200078e0002 */
/*00c0*/ STS [R2.X4], R2 ; /* 0x0000000202007388 */
/* 0x0001e80000004800 */
/*00d0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100a00 */
/*00e0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fe40000000000 */
/*00f0*/ MOV R3, 0x160 ; /* 0x0000016000037802 */
/* 0x001fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0140*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0150*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GT.AND P0, PT, R2, 0x1fe, PT ; /* 0x000001fe0200780c */
/* 0x000fe20003f04270 */
/*0190*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*01a0*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*01d0*/ LDC.64 R8, c[0x4][R3] ; /* 0x0100000003087b82 */
/* 0x0000620000000a00 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fc800078e00ff */
/*0200*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0210*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000ea40000004800 */
/*0220*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x004fcc00078e0000 */
/*0230*/ @!P0 LDS R11, [R2.X4+0x4] ; /* 0x00000400020b8984 */
/* 0x000ea80000004800 */
/*0240*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fe20000010000 */
/*0250*/ IMAD.IADD R0, R11, 0x1, -R0 ; /* 0x000000010b007824 */
/* 0x004fca00078e0a00 */
/*0260*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e80000100a00 */
/*0270*/ @!P0 STS [R2.X4], R11 ; /* 0x0000000b02008388 */
/* 0x0001e80000004800 */
/*0280*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0001e40000100800 */
/*0290*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*02a0*/ MOV R11, 0x310 ; /* 0x00000310000b7802 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R20, 0x290 ; /* 0x0000029000147802 */
/* 0x000fc40000000f00 */
/*02c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02e0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02f0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0300*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void aKernel()
{
int idx = threadIdx.x;
int r1, r2, res_diff;
__shared__ int arr[512];
arr[idx] = idx;
printf("A: Thread %5d, value %5d\n", idx, arr[idx]);
__syncthreads();
r1 = arr[idx];
if (idx < 511) {
int temp = arr[idx + 1];
__syncthreads();
arr[idx] = temp;
}
r2 = arr[idx];
res_diff = r2 - r1;
printf("B: Thread %5d, value %5d, diff=%5d\n", idx, arr[idx], res_diff);
}
int main()
{
aKernel<<<1, 512>>> ();
return 0;
} | .file "tmpxft_000c8659_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7aKernelvv
.type _Z25__device_stub__Z7aKernelvv, @function
_Z25__device_stub__Z7aKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7aKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7aKernelvv, .-_Z25__device_stub__Z7aKernelvv
.globl _Z7aKernelv
.type _Z7aKernelv, @function
_Z7aKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7aKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7aKernelv, .-_Z7aKernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7aKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7aKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7aKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. |
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void aKernel()
{
int idx = threadIdx.x;
int r1, r2, res_diff;
__shared__ int arr[512];
arr[idx] = idx;
printf("A: Thread %5d, value %5d\n", idx, arr[idx]);
__syncthreads();
r1 = arr[idx];
if (idx < 511) {
int temp = arr[idx + 1];
__syncthreads();
arr[idx] = temp;
}
r2 = arr[idx];
res_diff = r2 - r1;
printf("B: Thread %5d, value %5d, diff=%5d\n", idx, arr[idx], res_diff);
}
int main()
{
aKernel<<<1, 512>>> ();
return 0;
} |
#include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void aKernel()
{
int idx = threadIdx.x;
int r1, r2, res_diff;
__shared__ int arr[512];
arr[idx] = idx;
printf("A: Thread %5d, value %5d\n", idx, arr[idx]);
__syncthreads();
r1 = arr[idx];
if (idx < 511) {
int temp = arr[idx + 1];
__syncthreads();
arr[idx] = temp;
}
r2 = arr[idx];
res_diff = r2 - r1;
printf("B: Thread %5d, value %5d, diff=%5d\n", idx, arr[idx], res_diff);
}
int main()
{
aKernel<<<1, 512>>> ();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. |
#include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void aKernel()
{
int idx = threadIdx.x;
int r1, r2, res_diff;
__shared__ int arr[512];
arr[idx] = idx;
printf("A: Thread %5d, value %5d\n", idx, arr[idx]);
__syncthreads();
r1 = arr[idx];
if (idx < 511) {
int temp = arr[idx + 1];
__syncthreads();
arr[idx] = temp;
}
r2 = arr[idx];
res_diff = r2 - r1;
printf("B: Thread %5d, value %5d, diff=%5d\n", idx, arr[idx], res_diff);
}
int main()
{
aKernel<<<1, 512>>> ();
return 0;
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__aKernelv # -- Begin function _Z22__device_stub__aKernelv
.p2align 4, 0x90
.type _Z22__device_stub__aKernelv,@function
_Z22__device_stub__aKernelv: # @_Z22__device_stub__aKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7aKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__aKernelv, .Lfunc_end0-_Z22__device_stub__aKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7aKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7aKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7aKernelv,@object # @_Z7aKernelv
.section .rodata,"a",@progbits
.globl _Z7aKernelv
.p2align 3, 0x0
_Z7aKernelv:
.quad _Z22__device_stub__aKernelv
.size _Z7aKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7aKernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__aKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7aKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8659_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7aKernelvv
.type _Z25__device_stub__Z7aKernelvv, @function
_Z25__device_stub__Z7aKernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7aKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7aKernelvv, .-_Z25__device_stub__Z7aKernelvv
.globl _Z7aKernelv
.type _Z7aKernelv, @function
_Z7aKernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7aKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7aKernelv, .-_Z7aKernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7aKernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7aKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7aKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__aKernelv # -- Begin function _Z22__device_stub__aKernelv
.p2align 4, 0x90
.type _Z22__device_stub__aKernelv,@function
_Z22__device_stub__aKernelv: # @_Z22__device_stub__aKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7aKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__aKernelv, .Lfunc_end0-_Z22__device_stub__aKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7aKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7aKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7aKernelv,@object # @_Z7aKernelv
.section .rodata,"a",@progbits
.globl _Z7aKernelv
.p2align 3, 0x0
_Z7aKernelv:
.quad _Z22__device_stub__aKernelv
.size _Z7aKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7aKernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__aKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7aKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} | .file "tmpxft_000c28bf_00000000-6_matMul_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6matMulPfS_S_j
.type _Z6matMulPfS_S_j, @function
_Z6matMulPfS_S_j:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r11
movq %rsi, %r9
movq %rdx, %r8
movl %ecx, %esi
movl %ecx, %edi
movl $0, %ebx
movl $0, %ebp
movl $0, %r12d
testl %ecx, %ecx
jne .L4
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %r10d
.L7:
leal (%rbx,%r10), %eax
leaq (%r11,%rax,4), %rcx
movl $0x00000000, (%rcx)
movl %r10d, %edx
movl %ebx, %eax
.L6:
movl %eax, %r14d
movl %edx, %r13d
movss (%r9,%r14,4), %xmm0
mulss (%r8,%r13,4), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addl %esi, %edx
cmpl %edi, %eax
jne .L6
leal 1(%r10), %eax
cmpl %eax, %esi
jne .L9
leal 1(%rbp), %edx
addl %eax, %ebx
addl %eax, %edi
cmpl %r10d, %ebp
je .L3
movl %edx, %ebp
.L4:
movl %r12d, %r10d
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z6matMulPfS_S_j, .-_Z6matMulPfS_S_j
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L18
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L15:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Syntax: %s <matrix Width>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Allocate memory for matrices M and N...\n"
.section .rodata.str1.1
.LC3:
.string "Initialize matrices...\n"
.LC4:
.string "Multiply matrices...\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\nExecution Time (microseconds): %9.2f\n"
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "matMul_cpu.out"
.LC9:
.string "%6.2f "
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L22
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L21:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ebp
imull %ebx, %ebp
movslq %ebp, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 40(%rsp)
movl $42, %edi
call srand48@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z10randomInitPfi
movl %ebp, %esi
movq %r14, %rdi
call _Z10randomInitPfi
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %r14
movq %r12, %rdi
call _Z6matMulPfS_S_j
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L28
testl %ebx, %ebx
jle .L24
movslq %ebx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
leal -1(%rbx), %eax
leaq 4(%r14,%rax,4), %rbp
movl $0, %r14d
movl %ebx, %ebx
negq %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 16(%rsp)
leaq .LC9(%rip), %r13
jmp .L25
.L33:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r14d
movq 8(%rsp), %rax
addq %rax, %rbp
cmpl %r15d, %r14d
je .L24
.L25:
movq 16(%rsp), %rax
leaq (%rax,%rbp), %rbx
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
jmp .L33
.L24:
movq %r12, %rdi
call fclose@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movl $0, %eax
jmp .L21
.L28:
movl $1, %eax
jmp .L21
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
// Computes the matrix product using line matrices:
void matMul(float* P, float* M, float* N, unsigned int Width) {
for (unsigned int i = 0; i < Width; ++i) {
for (unsigned int j = 0; j < Width; ++j) {
P[i * Width + j] = 0.0;
for (unsigned int k = 0; k < Width; ++k) {
P[i * Width + j] += M[i * Width + k] * N[k * Width + j];
}
}
}
}
// Allocates a matrix with random float entries.
void randomInit(float* data, int size) {
for (int i = 0; i < size; ++i) {
data[i] = (float)drand48();
}
}
int main(int argc, char* argv[])
{
if (argc != 2) {
fprintf(stderr, "Syntax: %s <matrix Width>\n", argv[0]);
return EXIT_FAILURE;
}
int Width = atoi(argv[1]);
// allocate host memory for matrices M and N
printf("Allocate memory for matrices M and N...\n");
float* M = (float*) malloc(Width * Width * sizeof(float));
float* N = (float*) malloc(Width * Width * sizeof(float));
float* P = (float*) malloc(Width * Width * sizeof(float));
// set seed for drand48()
srand48(42);
// initialize matrices
printf("Initialize matrices...\n");
randomInit(M, Width*Width);
randomInit(N, Width*Width);
printf("Multiply matrices...\n");
struct timeval begin, end;
gettimeofday(&begin, NULL);
matMul( P, M, N, Width );
gettimeofday(&end, NULL);
double cpuTime = 1000000*(double)(end.tv_sec - begin.tv_sec);
cpuTime += (double)(end.tv_usec - begin.tv_usec);
// print times
printf("\nExecution Time (microseconds): %9.2f\n", cpuTime);
// print result
FILE *ptr_file;
ptr_file =fopen("matMul_cpu.out", "w");
if (!ptr_file) return 1;
for (int i=0; i < Width; i++){
for (int j=0; j < Width; j++) fprintf(ptr_file,"%6.2f ", P[i * Width + j]);
fprintf(ptr_file,"\n");
}
fclose(ptr_file);
// clean up memory
free(M);
free(N);
free(P);
return 0;
} | .text
.file "matMul_cpu.hip"
.globl _Z6matMulPfS_S_j # -- Begin function _Z6matMulPfS_S_j
.p2align 4, 0x90
.type _Z6matMulPfS_S_j,@function
_Z6matMulPfS_S_j: # @_Z6matMulPfS_S_j
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB0_8
# %bb.1: # %.preheader.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %r9d, %r10d
imull %ecx, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
leal (%r10,%r11), %ebx
movl $0, (%rdi,%rbx,4)
xorps %xmm0, %xmm0
movl %r11d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r8,%r14), %r15d
movss (%rsi,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %ebp, %r15d
mulss (%rdx,%r15,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdi,%rbx,4)
incq %r14
addl %ecx, %ebp
cmpq %r14, %rax
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=2
incq %r11
cmpq %rax, %r11
jne .LBB0_3
# %bb.6: # in Loop: Header=BB0_2 Depth=1
incl %r9d
addq %rax, %r8
cmpl %eax, %r9d
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge
retq
.Lfunc_end0:
.size _Z6matMulPfS_S_j, .Lfunc_end0-_Z6matMulPfS_S_j
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_23
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movl $42, %edi
callq srand48
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
je .LBB2_7
# %bb.2: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit
testl %ebx, %ebx
je .LBB2_7
# %bb.5: # %.lr.ph.i47.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB2_6
.LBB2_7: # %_Z10randomInitPfi.exit51
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r13d, %r13d
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
je .LBB2_14
# %bb.8: # %.preheader.i.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
# Child Loop BB2_11 Depth 3
movl %ecx, %edx
imull %ebx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
leal (%rdx,%rsi), %edi
movl $0, (%rbp,%rdi,4)
xorps %xmm0, %xmm0
movl %r13d, %r8d
movq %rax, %r9
movq %rsi, %r10
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
movl %r8d, %r11d
movss (%r14,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r10d, %r11d
mulss (%r15,%r11,4), %xmm1
addss %xmm1, %xmm0
addq %rbx, %r10
incl %r8d
decq %r9
jne .LBB2_11
# %bb.12: # in Loop: Header=BB2_10 Depth=2
movss %xmm0, (%rbp,%rdi,4)
incq %rsi
cmpq %rax, %rsi
jne .LBB2_10
# %bb.13: # in Loop: Header=BB2_9 Depth=1
incl %ecx
addl %ebx, %r13d
cmpl %ebx, %ecx
jne .LBB2_9
.LBB2_14: # %_Z6matMulPfS_S_j.exit
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
subq 56(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_0(%rip), %xmm1
subq 64(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
testq %rax, %rax
je .LBB2_21
# %bb.15: # %.preheader57
movq %rax, %rdi
movq %rbp, 8(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_20
# %bb.16: # %.preheader.lr.ph
movl %ebx, %eax
xorl %ecx, %ecx
xorl %edx, %edx
movq %rax, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
movq %rdx, 24(%rsp) # 8-byte Spill
movq %rcx, 32(%rsp) # 8-byte Spill
movl %ecx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
movq %rdi, %rbp
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %rbp, %rdi
movb $1, %al
callq fprintf
incq %r13
cmpq %r13, 16(%rsp) # 8-byte Folded Reload
jne .LBB2_18
# %bb.19: # %._crit_edge
# in Loop: Header=BB2_17 Depth=1
movl $10, %edi
movq %rbp, %rsi
callq fputc@PLT
movq 24(%rsp), %rdx # 8-byte Reload
incq %rdx
movq 32(%rsp), %rcx # 8-byte Reload
addl %ebx, %ecx
movq 16(%rsp), %rax # 8-byte Reload
cmpq %rax, %rdx
movq %rbp, %rdi
jne .LBB2_17
.LBB2_20: # %._crit_edge60
callq fclose
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
jmp .LBB2_22
.LBB2_23:
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
.LBB2_21:
movl $1, %eax
.LBB2_22:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Syntax: %s <matrix Width>\n"
.size .L.str, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nExecution Time (microseconds): %9.2f\n"
.size .L.str.4, 39
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "matMul_cpu.out"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%6.2f "
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocate memory for matrices M and N..."
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize matrices..."
.size .Lstr.1, 23
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Multiply matrices..."
.size .Lstr.2, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c28bf_00000000-6_matMul_cpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6matMulPfS_S_j
.type _Z6matMulPfS_S_j, @function
_Z6matMulPfS_S_j:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r11
movq %rsi, %r9
movq %rdx, %r8
movl %ecx, %esi
movl %ecx, %edi
movl $0, %ebx
movl $0, %ebp
movl $0, %r12d
testl %ecx, %ecx
jne .L4
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl %eax, %r10d
.L7:
leal (%rbx,%r10), %eax
leaq (%r11,%rax,4), %rcx
movl $0x00000000, (%rcx)
movl %r10d, %edx
movl %ebx, %eax
.L6:
movl %eax, %r14d
movl %edx, %r13d
movss (%r9,%r14,4), %xmm0
mulss (%r8,%r13,4), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addl $1, %eax
addl %esi, %edx
cmpl %edi, %eax
jne .L6
leal 1(%r10), %eax
cmpl %eax, %esi
jne .L9
leal 1(%rbp), %edx
addl %eax, %ebx
addl %eax, %edi
cmpl %r10d, %ebp
je .L3
movl %edx, %ebp
.L4:
movl %r12d, %r10d
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z6matMulPfS_S_j, .-_Z6matMulPfS_S_j
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L18
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L15:
call drand48@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Syntax: %s <matrix Width>\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Allocate memory for matrices M and N...\n"
.section .rodata.str1.1
.LC3:
.string "Initialize matrices...\n"
.LC4:
.string "Multiply matrices...\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "\nExecution Time (microseconds): %9.2f\n"
.section .rodata.str1.1
.LC7:
.string "w"
.LC8:
.string "matMul_cpu.out"
.LC9:
.string "%6.2f "
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L22
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L21:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L32
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r15d
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ebp
imull %ebx, %ebp
movslq %ebp, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 40(%rsp)
movl $42, %edi
call srand48@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %esi
movq %r13, %rdi
call _Z10randomInitPfi
movl %ebp, %esi
movq %r14, %rdi
call _Z10randomInitPfi
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %r14
movq %r12, %rdi
call _Z6matMulPfS_S_j
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC5(%rip), %xmm1
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L28
testl %ebx, %ebx
jle .L24
movslq %ebx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
leal -1(%rbx), %eax
leaq 4(%r14,%rax,4), %rbp
movl $0, %r14d
movl %ebx, %ebx
negq %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 16(%rsp)
leaq .LC9(%rip), %r13
jmp .L25
.L33:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %r14d
movq 8(%rsp), %rax
addq %rax, %rbp
cmpl %r15d, %r14d
je .L24
.L25:
movq 16(%rsp), %rax
leaq (%rax,%rbp), %rbx
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
jmp .L33
.L24:
movq %r12, %rdi
call fclose@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movl $0, %eax
jmp .L21
.L28:
movl $1, %eax
jmp .L21
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMul_cpu.hip"
.globl _Z6matMulPfS_S_j # -- Begin function _Z6matMulPfS_S_j
.p2align 4, 0x90
.type _Z6matMulPfS_S_j,@function
_Z6matMulPfS_S_j: # @_Z6matMulPfS_S_j
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
je .LBB0_8
# %bb.1: # %.preheader.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movl %r9d, %r10d
imull %ecx, %r10d
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
leal (%r10,%r11), %ebx
movl $0, (%rdi,%rbx,4)
xorps %xmm0, %xmm0
movl %r11d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r8,%r14), %r15d
movss (%rsi,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %ebp, %r15d
mulss (%rdx,%r15,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rdi,%rbx,4)
incq %r14
addl %ecx, %ebp
cmpq %r14, %rax
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=2
incq %r11
cmpq %rax, %r11
jne .LBB0_3
# %bb.6: # in Loop: Header=BB0_2 Depth=1
incl %r9d
addq %rax, %r8
cmpl %eax, %r9d
jne .LBB0_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_8: # %._crit_edge
retq
.Lfunc_end0:
.size _Z6matMulPfS_S_j, .Lfunc_end0-_Z6matMulPfS_S_j
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_23
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl %ebx, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %rbp
movl $42, %edi
callq srand48
movl $.Lstr.1, %edi
callq puts@PLT
testl %ebx, %ebx
je .LBB2_7
# %bb.2: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit
testl %ebx, %ebx
je .LBB2_7
# %bb.5: # %.lr.ph.i47.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
callq drand48
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB2_6
.LBB2_7: # %_Z10randomInitPfi.exit51
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r13d, %r13d
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebx, %ebx
je .LBB2_14
# %bb.8: # %.preheader.i.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_9: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
# Child Loop BB2_11 Depth 3
movl %ecx, %edx
imull %ebx, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
leal (%rdx,%rsi), %edi
movl $0, (%rbp,%rdi,4)
xorps %xmm0, %xmm0
movl %r13d, %r8d
movq %rax, %r9
movq %rsi, %r10
.p2align 4, 0x90
.LBB2_11: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
movl %r8d, %r11d
movss (%r14,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r10d, %r11d
mulss (%r15,%r11,4), %xmm1
addss %xmm1, %xmm0
addq %rbx, %r10
incl %r8d
decq %r9
jne .LBB2_11
# %bb.12: # in Loop: Header=BB2_10 Depth=2
movss %xmm0, (%rbp,%rdi,4)
incq %rsi
cmpq %rax, %rsi
jne .LBB2_10
# %bb.13: # in Loop: Header=BB2_9 Depth=1
incl %ecx
addl %ebx, %r13d
cmpl %ebx, %ecx
jne .LBB2_9
.LBB2_14: # %_Z6matMulPfS_S_j.exit
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
subq 56(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_0(%rip), %xmm1
subq 64(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
testq %rax, %rax
je .LBB2_21
# %bb.15: # %.preheader57
movq %rax, %rdi
movq %rbp, 8(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_20
# %bb.16: # %.preheader.lr.ph
movl %ebx, %eax
xorl %ecx, %ecx
xorl %edx, %edx
movq %rax, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
movq %rdx, 24(%rsp) # 8-byte Spill
movq %rcx, 32(%rsp) # 8-byte Spill
movl %ecx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
movq %rdi, %rbp
leaq (%rcx,%rax,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %esi
movq %rbp, %rdi
movb $1, %al
callq fprintf
incq %r13
cmpq %r13, 16(%rsp) # 8-byte Folded Reload
jne .LBB2_18
# %bb.19: # %._crit_edge
# in Loop: Header=BB2_17 Depth=1
movl $10, %edi
movq %rbp, %rsi
callq fputc@PLT
movq 24(%rsp), %rdx # 8-byte Reload
incq %rdx
movq 32(%rsp), %rcx # 8-byte Reload
addl %ebx, %ecx
movq 16(%rsp), %rax # 8-byte Reload
cmpq %rax, %rdx
movq %rbp, %rdi
jne .LBB2_17
.LBB2_20: # %._crit_edge60
callq fclose
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
jmp .LBB2_22
.LBB2_23:
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
.LBB2_21:
movl $1, %eax
.LBB2_22:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Syntax: %s <matrix Width>\n"
.size .L.str, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nExecution Time (microseconds): %9.2f\n"
.size .L.str.4, 39
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "matMul_cpu.out"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%6.2f "
.size .L.str.7, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocate memory for matrices M and N..."
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize matrices..."
.size .Lstr.1, 23
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Multiply matrices..."
.size .Lstr.2, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif | code for sm_80
Function : _Z17CheckPrime_Kernelii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif | .file "tmpxft_00101ee6_00000000-6_CheckPrime_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z17CheckPrime_Kerneliiii
.type _Z37__device_stub__Z17CheckPrime_Kerneliiii, @function
_Z37__device_stub__Z17CheckPrime_Kerneliiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17CheckPrime_Kernelii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z17CheckPrime_Kerneliiii, .-_Z37__device_stub__Z17CheckPrime_Kerneliiii
.globl _Z17CheckPrime_Kernelii
.type _Z17CheckPrime_Kernelii, @function
_Z17CheckPrime_Kernelii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z17CheckPrime_Kerneliiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17CheckPrime_Kernelii, .-_Z17CheckPrime_Kernelii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17CheckPrime_Kernelii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17CheckPrime_Kernelii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "hip/hip_runtime.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "hip/hip_runtime.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17CheckPrime_Kernelii
.globl _Z17CheckPrime_Kernelii
.p2align 8
.type _Z17CheckPrime_Kernelii,@function
_Z17CheckPrime_Kernelii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17CheckPrime_Kernelii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17CheckPrime_Kernelii, .Lfunc_end0-_Z17CheckPrime_Kernelii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17CheckPrime_Kernelii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17CheckPrime_Kernelii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __CHECK_PRIME_KERNEL
#define __CHECK_PRIME_KERNEL
#include "hip/hip_runtime.h"
__global__ void CheckPrime_Kernel(int A, int B)
{
// Because of the simplicity of this tutorial, we are going to assume that
// every block has 256 threads. Each thread simply multiplies two numbers,
// and then stores the result.
// The grid of blocks is 128 blocks long.
int tid = (blockIdx.y * 128 * 256) + blockIdx.x * 256 + threadIdx.x; // This gives every thread a unique ID.
// By no coincidence, we'll be using this thread ID to determine which data elements to multiply.
//pResult[tid] = pDataA[tid] * pDataB[tid]; // Each thread only multiplies one data element.
//pResult[tid] = pDataA[tid] * pDataB[tid] / 12.34567;
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567);
//pResult[tid] = sqrt(pDataA[tid] * pDataB[tid] / 12.34567) * sin(pDataA[tid]);
}
#endif | .text
.file "CheckPrime_Kernel.hip"
.globl _Z32__device_stub__CheckPrime_Kernelii # -- Begin function _Z32__device_stub__CheckPrime_Kernelii
.p2align 4, 0x90
.type _Z32__device_stub__CheckPrime_Kernelii,@function
_Z32__device_stub__CheckPrime_Kernelii: # @_Z32__device_stub__CheckPrime_Kernelii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17CheckPrime_Kernelii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__CheckPrime_Kernelii, .Lfunc_end0-_Z32__device_stub__CheckPrime_Kernelii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17CheckPrime_Kernelii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17CheckPrime_Kernelii,@object # @_Z17CheckPrime_Kernelii
.section .rodata,"a",@progbits
.globl _Z17CheckPrime_Kernelii
.p2align 3, 0x0
_Z17CheckPrime_Kernelii:
.quad _Z32__device_stub__CheckPrime_Kernelii
.size _Z17CheckPrime_Kernelii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17CheckPrime_Kernelii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__CheckPrime_Kernelii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17CheckPrime_Kernelii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17CheckPrime_Kernelii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17CheckPrime_Kernelii
.globl _Z17CheckPrime_Kernelii
.p2align 8
.type _Z17CheckPrime_Kernelii,@function
_Z17CheckPrime_Kernelii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17CheckPrime_Kernelii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17CheckPrime_Kernelii, .Lfunc_end0-_Z17CheckPrime_Kernelii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17CheckPrime_Kernelii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z17CheckPrime_Kernelii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101ee6_00000000-6_CheckPrime_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z17CheckPrime_Kerneliiii
.type _Z37__device_stub__Z17CheckPrime_Kerneliiii, @function
_Z37__device_stub__Z17CheckPrime_Kerneliiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17CheckPrime_Kernelii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z17CheckPrime_Kerneliiii, .-_Z37__device_stub__Z17CheckPrime_Kerneliiii
.globl _Z17CheckPrime_Kernelii
.type _Z17CheckPrime_Kernelii, @function
_Z17CheckPrime_Kernelii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z17CheckPrime_Kerneliiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17CheckPrime_Kernelii, .-_Z17CheckPrime_Kernelii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17CheckPrime_Kernelii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17CheckPrime_Kernelii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CheckPrime_Kernel.hip"
.globl _Z32__device_stub__CheckPrime_Kernelii # -- Begin function _Z32__device_stub__CheckPrime_Kernelii
.p2align 4, 0x90
.type _Z32__device_stub__CheckPrime_Kernelii,@function
_Z32__device_stub__CheckPrime_Kernelii: # @_Z32__device_stub__CheckPrime_Kernelii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17CheckPrime_Kernelii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__CheckPrime_Kernelii, .Lfunc_end0-_Z32__device_stub__CheckPrime_Kernelii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17CheckPrime_Kernelii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17CheckPrime_Kernelii,@object # @_Z17CheckPrime_Kernelii
.section .rodata,"a",@progbits
.globl _Z17CheckPrime_Kernelii
.p2align 3, 0x0
_Z17CheckPrime_Kernelii:
.quad _Z32__device_stub__CheckPrime_Kernelii
.size _Z17CheckPrime_Kernelii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17CheckPrime_Kernelii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__CheckPrime_Kernelii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17CheckPrime_Kernelii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <string>
#include <cstdlib>
// 2 GB of data
#define BYTES 2147483648
#define MAX_STRIDE 4194304
#define MAX_INDEX (BYTES/MAX_STRIDE)
static void __global__
Set(const int Seed, const int Stride, char *data) {
// Everyone set some data
for(int i = threadIdx.x; i < BYTES ; i+= blockDim.x ) {
data[i] = (char)(i * threadIdx.x + Seed);
}
}
static void __global__
CacheTest(const int Seed , const int Stride , char *data, int *result ) {
if(threadIdx.x == 0 ) {
int local_result = 0;
for(int i = 0 ; i < MAX_INDEX; ++i) {
local_result += data[i *(Stride+1)];
}
*result = local_result; // Here to make sure we don't optimize the loop away
}
}
static void Validate(bool cond, std::string msg) {
if(!cond) {
std::cout << msg << std::endl;
cudaDeviceReset();
std::exit(EXIT_FAILURE);
}
}
static void CudaCheck(std::string msg, cudaError err) {
Validate(err==cudaSuccess, cudaGetErrorString(err) + std::string("\n") + msg);
}
void sort(float *durations, int size) {
for(int i = 1 ; i < size; ++i) {
float cand = durations[i];
int j = i;
while( j > 0 && cand < durations[j-1]) {
if(durations[j] < durations[j-1]) {
durations[j] = durations[j-1];
}
--j;
}
durations[j] = cand;
}
}
float Run(const int Seed, const int Stride) {
const int Blocks = 1;
const int Threads = 1024;
float time;
cudaEvent_t start,end;
char *d_data;
int *d_result;
CudaCheck("Malloc Result", cudaMalloc(&d_result, sizeof(int) ) );
CudaCheck("Malloc Data", cudaMalloc(&d_data, BYTES ) );
CudaCheck("Memset Result", cudaMemset(d_result, 0, sizeof(int) ) );
CudaCheck("Memset Data", cudaMemset(d_data, 0, BYTES ) );
Set<<<Blocks,Threads>>>(Seed, Stride, d_data);
CudaCheck("Set",cudaDeviceSynchronize());
CudaCheck("Create start",cudaEventCreate(&start));
CudaCheck("Create end",cudaEventCreate(&end));
CudaCheck("Record start",cudaEventRecord(start,0));
CacheTest<<<Blocks,Threads>>>(Seed, Stride, d_data, d_result);
CudaCheck("Record end",cudaEventRecord(end,0));
CudaCheck("Device Sync",cudaDeviceSynchronize());
CudaCheck("Event sync", cudaEventSynchronize(end) );
CudaCheck("Get elapsed time",cudaEventElapsedTime(&time,start,end));
CudaCheck("Destroy start",cudaEventDestroy(start));
CudaCheck("Destroy end",cudaEventDestroy(end));
CudaCheck("Free result", cudaFree(d_result));
CudaCheck("Free data", cudaFree(d_data));
CudaCheck("Reset",cudaDeviceReset());
return time;
}
int main(int argc, char* argv[]) {
const int Runs = 50;
float durations[Runs];
Validate(argc==2,"Usage: " + std::string(argv[0]) + " stride");
const int Stride = atoi(argv[1]);
Validate(Stride <= MAX_STRIDE,"Decrease Stride");
std::cout << "Stride: " << Stride << std::endl;
for(int i = 0 ; i < Runs ; ++i ) {
durations[i] = Run(i+1, Stride);
}
sort(durations,Runs);
float time = 0;
int count = 0;
for(int i = 0; i < Runs; ++i) {
time += durations[i];
++count;
}
time /= count;
std::cout << "Elapsed Time: " << time << "ms" << std::endl;
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z9CacheTestiiPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R36, -RZ, RZ, 0, 0 ; /* 0x00000000ff247435 */
/* 0x000fe200000001ff */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ ULEA UR10, UR5, 0x20, 0x5 ; /* 0x00000020050a7891 */
/* 0x000fe4000f8e283f */
/*0080*/ USHF.L.U32 UR11, UR5, 0x1, URZ ; /* 0x00000001050b7899 */
/* 0x000fe4000800063f */
/*0090*/ UIMAD UR12, UR5, 0x3, URZ ; /* 0x00000003050c78a4 */
/* 0x000fe4000f8e023f */
/*00a0*/ USHF.L.U32 UR13, UR5, 0x2, URZ ; /* 0x00000002050d7899 */
/* 0x000fc4000800063f */
/*00b0*/ UIMAD UR14, UR5, 0x5, URZ ; /* 0x00000005050e78a4 */
/* 0x000fe4000f8e023f */
/*00c0*/ UIMAD UR15, UR5, 0x6, URZ ; /* 0x00000006050f78a4 */
/* 0x000fe4000f8e023f */
/*00d0*/ UIMAD UR16, UR5, 0x7, URZ ; /* 0x00000007051078a4 */
/* 0x000fe4000f8e023f */
/*00e0*/ USHF.L.U32 UR17, UR5, 0x3, URZ ; /* 0x0000000305117899 */
/* 0x000fe4000800063f */
/*00f0*/ UIMAD UR18, UR5, 0x9, URZ ; /* 0x00000009051278a4 */
/* 0x000fe4000f8e023f */
/*0100*/ UIMAD UR19, UR5, 0xa, URZ ; /* 0x0000000a051378a4 */
/* 0x000fc4000f8e023f */
/*0110*/ UIMAD UR20, UR5, 0xb, URZ ; /* 0x0000000b051478a4 */
/* 0x000fe4000f8e023f */
/*0120*/ UIMAD UR21, UR5, 0xc, URZ ; /* 0x0000000c051578a4 */
/* 0x000fe4000f8e023f */
/*0130*/ UIMAD UR22, UR5, 0xd, URZ ; /* 0x0000000d051678a4 */
/* 0x000fe4000f8e023f */
/*0140*/ UIMAD UR23, UR5, 0xe, URZ ; /* 0x0000000e051778a4 */
/* 0x000fe4000f8e023f */
/*0150*/ UIMAD UR24, UR5, 0xf, URZ ; /* 0x0000000f051878a4 */
/* 0x000fe4000f8e023f */
/*0160*/ USHF.L.U32 UR25, UR5, 0x4, URZ ; /* 0x0000000405197899 */
/* 0x000fc4000800063f */
/*0170*/ UIMAD UR26, UR5, 0x11, URZ ; /* 0x00000011051a78a4 */
/* 0x000fe4000f8e023f */
/*0180*/ UIMAD UR27, UR5, 0x12, URZ ; /* 0x00000012051b78a4 */
/* 0x000fe4000f8e023f */
/*0190*/ UIMAD UR28, UR5, 0x13, URZ ; /* 0x00000013051c78a4 */
/* 0x000fe4000f8e023f */
/*01a0*/ UIMAD UR29, UR5, 0x14, URZ ; /* 0x00000014051d78a4 */
/* 0x000fe4000f8e023f */
/*01b0*/ UIMAD UR30, UR5, 0x15, URZ ; /* 0x00000015051e78a4 */
/* 0x000fe4000f8e023f */
/*01c0*/ UIMAD UR31, UR5, 0x16, URZ ; /* 0x00000016051f78a4 */
/* 0x000fc4000f8e023f */
/*01d0*/ UIMAD UR32, UR5, 0x17, URZ ; /* 0x00000017052078a4 */
/* 0x000fe4000f8e023f */
/*01e0*/ UIMAD UR33, UR5, 0x18, URZ ; /* 0x00000018052178a4 */
/* 0x000fe4000f8e023f */
/*01f0*/ UIMAD UR34, UR5, 0x19, URZ ; /* 0x00000019052278a4 */
/* 0x000fe4000f8e023f */
/*0200*/ UIMAD UR35, UR5, 0x1a, URZ ; /* 0x0000001a052378a4 */
/* 0x000fe4000f8e023f */
/*0210*/ UIMAD UR36, UR5, 0x1b, URZ ; /* 0x0000001b052478a4 */
/* 0x000fe4000f8e023f */
/*0220*/ UIMAD UR37, UR5, 0x1c, URZ ; /* 0x0000001c052578a4 */
/* 0x000fc4000f8e023f */
/*0230*/ UIMAD UR38, UR5, 0x1d, URZ ; /* 0x0000001d052678a4 */
/* 0x000fe4000f8e023f */
/*0240*/ UIMAD UR39, UR5, 0x1e, URZ ; /* 0x0000001e052778a4 */
/* 0x000fe4000f8e023f */
/*0250*/ UIMAD UR40, UR5, 0x1f, URZ ; /* 0x0000001f052878a4 */
/* 0x000fe4000f8e023f */
/*0260*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0270*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0280*/ UIADD3 UR50, UP0, UR12, UR8, URZ ; /* 0x000000080c327290 */
/* 0x000fe4000ff1e03f */
/*0290*/ UIADD3 UR49, UP1, UR11, UR8, URZ ; /* 0x000000080b317290 */
/* 0x000fc4000ff3e03f */
/*02a0*/ ULEA.HI.X.SX32 UR51, UR12, UR9, 0x1, UP0 ; /* 0x000000090c337291 */
/* 0x000fe400080f0e3f */
/*02b0*/ UIADD3 UR54, UP6, UR14, UR8, URZ ; /* 0x000000080e367290 */
/* 0x000fe2000ffde03f */
/*02c0*/ MOV R6, UR50 ; /* 0x0000003200067c02 */
/* 0x000fe20008000f00 */
/*02d0*/ ULEA.HI.X.SX32 UR52, UR11, UR9, 0x1, UP1 ; /* 0x000000090b347291 */
/* 0x000fe200088f0e3f */
/*02e0*/ IMAD.U32 R2, RZ, RZ, UR49 ; /* 0x00000031ff027e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ UIADD3 UR58, UP3, UR16, UR8, URZ ; /* 0x00000008103a7290 */
/* 0x000fe2000ff7e03f */
/*0300*/ IMAD.U32 R7, RZ, RZ, UR51 ; /* 0x00000033ff077e24 */
/* 0x000fe2000f8e00ff */
/*0310*/ UIADD3 UR53, UP4, UR13, UR8, URZ ; /* 0x000000080d357290 */
/* 0x000fe4000ff9e03f */
/*0320*/ UIADD3 UR57, UP5, UR15, UR8, URZ ; /* 0x000000080f397290 */
/* 0x000fe2000ffbe03f */
/*0330*/ IMAD.U32 R3, RZ, RZ, UR52 ; /* 0x00000034ff037e24 */
/* 0x000fe2000f8e00ff */
/*0340*/ ULEA.HI.X.SX32 UR55, UR14, UR9, 0x1, UP6 ; /* 0x000000090e377291 */
/* 0x000fe2000b0f0e3f */
/*0350*/ LDG.E.S8 R34, [R6.64+0x3] ; /* 0x0000030606227981 */
/* 0x0000a2000c1e1300 */
/*0360*/ ULEA.HI.X.SX32 UR59, UR16, UR9, 0x1, UP3 ; /* 0x00000009103b7291 */
/* 0x000fc400098f0e3f */
/*0370*/ UIADD3 UR4, UP1, UR18, UR8, URZ ; /* 0x0000000812047290 */
/* 0x000fe4000ff3e03f */
/*0380*/ UIADD3 UR61, UP2, UR17, UR8, URZ ; /* 0x00000008113d7290 */
/* 0x000fe4000ff5e03f */
/*0390*/ ULEA.HI.X.SX32 UR56, UR13, UR9, 0x1, UP4 ; /* 0x000000090d387291 */
/* 0x000fe4000a0f0e3f */
/*03a0*/ UIADD3 UR41, UP0, UR19, UR8, URZ ; /* 0x0000000813297290 */
/* 0x000fe2000ff1e03f */
/*03b0*/ IMAD.U32 R10, RZ, RZ, UR54 ; /* 0x00000036ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*03c0*/ ULEA.HI.X.SX32 UR60, UR15, UR9, 0x1, UP5 ; /* 0x000000090f3c7291 */
/* 0x000fe2000a8f0e3f */
/*03d0*/ LDG.E.S8 R35, [R2.64+0x2] ; /* 0x0000020602237981 */
/* 0x0002a2000c1e1300 */
/*03e0*/ UIADD3 UR42, UP4, UR20, UR8, URZ ; /* 0x00000008142a7290 */
/* 0x000fe2000ff9e03f */
/*03f0*/ IMAD.U32 R11, RZ, RZ, UR55 ; /* 0x00000037ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0400*/ UIADD3 UR43, UP6, UR21, UR8, URZ ; /* 0x00000008152b7290 */
/* 0x000fe2000ffde03f */
/*0410*/ IMAD.U32 R6, RZ, RZ, UR58 ; /* 0x0000003aff067e24 */
/* 0x001fe2000f8e00ff */
/*0420*/ ULEA.HI.X.SX32 UR48, UR18, UR9, 0x1, UP1 ; /* 0x0000000912307291 */
/* 0x000fe200088f0e3f */
/*0430*/ MOV R7, UR59 ; /* 0x0000003b00077c02 */
/* 0x000fe20008000f00 */
/*0440*/ ULEA.HI.X.SX32 UR52, UR20, UR9, 0x1, UP4 ; /* 0x0000000914347291 */
/* 0x000fc4000a0f0e3f */
/*0450*/ ULEA.HI.X.SX32 UR46, UR17, UR9, 0x1, UP2 ; /* 0x00000009112e7291 */
/* 0x000fe200090f0e3f */
/*0460*/ MOV R2, UR57 ; /* 0x0000003900027c02 */
/* 0x002fe20008000f00 */
/*0470*/ ULEA.HI.X.SX32 UR50, UR19, UR9, 0x1, UP0 ; /* 0x0000000913327291 */
/* 0x000fe200080f0e3f */
/*0480*/ IMAD.U32 R3, RZ, RZ, UR60 ; /* 0x0000003cff037e24 */
/* 0x000fe2000f8e00ff */
/*0490*/ UIADD3 UR47, UP2, UR24, UR8, URZ ; /* 0x00000008182f7290 */
/* 0x000fe2000ff5e03f */
/*04a0*/ IMAD.U32 R8, RZ, RZ, UR53 ; /* 0x00000035ff087e24 */
/* 0x000fe2000f8e00ff */
/*04b0*/ UIADD3 UR51, UP0, UR26, UR8, URZ ; /* 0x000000081a337290 */
/* 0x000fe2000ff1e03f */
/*04c0*/ MOV R9, UR56 ; /* 0x0000003800097c02 */
/* 0x000fe20008000f00 */
/*04d0*/ UIADD3 UR45, UP3, UR23, UR8, URZ ; /* 0x00000008172d7290 */
/* 0x000fe2000ff7e03f */
/*04e0*/ LDG.E.S8 R32, [R10.64+0x5] ; /* 0x000005060a207981 */
/* 0x0000e2000c1e1300 */
/*04f0*/ ULEA.HI.X.SX32 UR54, UR21, UR9, 0x1, UP6 ; /* 0x0000000915367291 */
/* 0x000fc4000b0f0e3f */
/*0500*/ UIADD3 UR44, UP5, UR22, UR8, URZ ; /* 0x00000008162c7290 */
/* 0x000fe2000ffbe03f */
/*0510*/ LDG.E.S8 R30, [R6.64+0x7] ; /* 0x00000706061e7981 */
/* 0x000322000c1e1300 */
/*0520*/ UIADD3 UR55, UP6, UR28, UR8, URZ ; /* 0x000000081c377290 */
/* 0x000fe4000ffde03f */
/*0530*/ ULEA.HI.X.SX32 UR60, UR24, UR9, 0x1, UP2 ; /* 0x00000009183c7291 */
/* 0x000fe200090f0e3f */
/*0540*/ LDG.E.S8 R31, [R2.64+0x6] ; /* 0x00000606021f7981 */
/* 0x000b22000c1e1300 */
/*0550*/ UIADD3 UR49, UP1, UR25, UR8, URZ ; /* 0x0000000819317290 */
/* 0x000fe2000ff3e03f */
/*0560*/ IMAD.U32 R11, RZ, RZ, UR48 ; /* 0x00000030ff0b7e24 */
/* 0x001fe2000f8e00ff */
/*0570*/ ULEA.HI.X.SX32 UR48, UR26, UR9, 0x1, UP0 ; /* 0x000000091a307291 */
/* 0x000fe200080f0e3f */
/*0580*/ LDG.E.S8 R33, [R8.64+0x4] ; /* 0x0000040608217981 */
/* 0x0000e2000c1e1300 */
/*0590*/ ULEA.HI.X.SX32 UR58, UR23, UR9, 0x1, UP3 ; /* 0x00000009173a7291 */
/* 0x000fe200098f0e3f */
/*05a0*/ IMAD.U32 R6, RZ, RZ, UR42 ; /* 0x0000002aff067e24 */
/* 0x002fc4000f8e00ff */
/*05b0*/ IMAD.U32 R7, RZ, RZ, UR52 ; /* 0x00000034ff077e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ ULEA.HI.X.SX32 UR56, UR22, UR9, 0x1, UP5 ; /* 0x0000000916387291 */
/* 0x000fe2000a8f0e3f */
/*05d0*/ MOV R3, UR50 ; /* 0x0000003200037c02 */
/* 0x020fe20008000f00 */
/*05e0*/ IMAD.U32 R2, RZ, RZ, UR41 ; /* 0x00000029ff027e24 */
/* 0x000fe2000f8e00ff */
/*05f0*/ ULEA.HI.X.SX32 UR50, UR28, UR9, 0x1, UP6 ; /* 0x000000091c327291 */
/* 0x000fe2000b0f0e3f */
/*0600*/ MOV R10, UR4 ; /* 0x00000004000a7c02 */
/* 0x000fe20008000f00 */
/*0610*/ UIADD3 UR57, UP5, UR29, UR8, URZ ; /* 0x000000081d397290 */
/* 0x000fe2000ffbe03f */
/*0620*/ IMAD.U32 R8, RZ, RZ, UR61 ; /* 0x0000003dff087e24 */
/* 0x001fe2000f8e00ff */
/*0630*/ UIADD3 UR59, UP3, UR30, UR8, URZ ; /* 0x000000081e3b7290 */
/* 0x000fe2000ff7e03f */
/*0640*/ IMAD.U32 R9, RZ, RZ, UR46 ; /* 0x0000002eff097e24 */
/* 0x000fe2000f8e00ff */
/*0650*/ UIADD3 UR53, UP4, UR27, UR8, URZ ; /* 0x000000081b357290 */
/* 0x000fe2000ff9e03f */
/*0660*/ LDG.E.S8 R26, [R6.64+0xb] ; /* 0x00000b06061a7981 */
/* 0x000162000c1e1300 */
/*0670*/ UIADD3 UR61, UP2, UR31, UR8, URZ ; /* 0x000000081f3d7290 */
/* 0x000fe2000ff5e03f */
/*0680*/ MOV R20, UR47 ; /* 0x0000002f00147c02 */
/* 0x000fe20008000f00 */
/*0690*/ ULEA.HI.X.SX32 UR46, UR25, UR9, 0x1, UP1 ; /* 0x00000009192e7291 */
/* 0x000fe200088f0e3f */
/*06a0*/ IMAD.U32 R21, RZ, RZ, UR60 ; /* 0x0000003cff157e24 */
/* 0x000fe2000f8e00ff */
/*06b0*/ UIADD3 UR4, UP1, UR32, UR8, URZ ; /* 0x0000000820047290 */
/* 0x000fe2000ff3e03f */
/*06c0*/ LDG.E.S8 R27, [R2.64+0xa] ; /* 0x00000a06021b7981 */
/* 0x000362000c1e1300 */
/*06d0*/ MOV R12, UR43 ; /* 0x0000002b000c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ IMAD.U32 R13, RZ, RZ, UR54 ; /* 0x00000036ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*06f0*/ ULEA.HI.X.SX32 UR52, UR29, UR9, 0x1, UP5 ; /* 0x000000091d347291 */
/* 0x000fe2000a8f0e3f */
/*0700*/ IMAD.U32 R7, RZ, RZ, UR48 ; /* 0x00000030ff077e24 */
/* 0x001fe2000f8e00ff */
/*0710*/ ULEA.HI.X.SX32 UR48, UR30, UR9, 0x1, UP3 ; /* 0x000000091e307291 */
/* 0x000fe200098f0e3f */
/*0720*/ IMAD.U32 R18, RZ, RZ, UR45 ; /* 0x0000002dff127e24 */
/* 0x000fe2000f8e00ff */
/*0730*/ UIADD3 UR41, UP0, UR33, UR8, URZ ; /* 0x0000000821297290 */
/* 0x000fe2000ff1e03f */
/*0740*/ IMAD.U32 R19, RZ, RZ, UR58 ; /* 0x0000003aff137e24 */
/* 0x000fe2000f8e00ff */
/*0750*/ ULEA.HI.X.SX32 UR42, UR27, UR9, 0x1, UP4 ; /* 0x000000091b2a7291 */
/* 0x000fe2000a0f0e3f */
/*0760*/ IMAD.U32 R2, RZ, RZ, UR55 ; /* 0x00000037ff027e24 */
/* 0x002fe2000f8e00ff */
/*0770*/ MOV R3, UR50 ; /* 0x0000003200037c02 */
/* 0x000fe20008000f00 */
/*0780*/ LDG.E.S8 R29, [R8.64+0x8] ; /* 0x00000806081d7981 */
/* 0x0000a2000c1e1300 */
/*0790*/ UIADD3 UR43, UP4, UR34, UR8, URZ ; /* 0x00000008222b7290 */
/* 0x000fe2000ff9e03f */
/*07a0*/ IMAD.U32 R6, RZ, RZ, UR51 ; /* 0x00000033ff067e24 */
/* 0x000fe2000f8e00ff */
/*07b0*/ ULEA.HI.X.SX32 UR47, UR31, UR9, 0x1, UP2 ; /* 0x000000091f2f7291 */
/* 0x000fe200090f0e3f */
/*07c0*/ LDG.E.S8 R28, [R10.64+0x9] ; /* 0x000009060a1c7981 */
/* 0x0002a2000c1e1300 */
/*07d0*/ IMAD.U32 R22, RZ, RZ, UR57 ; /* 0x00000039ff167e24 */
/* 0x000fc6000f8e00ff */
/*07e0*/ LDG.E.S8 R16, [R20.64+0xf] ; /* 0x00000f0614107981 */
/* 0x0002a2000c1e1300 */
/*07f0*/ IMAD.U32 R8, RZ, RZ, UR44 ; /* 0x0000002cff087e24 */
/* 0x001fe2000f8e00ff */
/*0800*/ UIADD3 UR44, UP6, UR35, UR8, URZ ; /* 0x00000008232c7290 */
/* 0x000fe4000ffde03f */
/*0810*/ LDG.E.S8 R25, [R12.64+0xc] ; /* 0x00000c060c197981 */
/* 0x0000a2000c1e1300 */
/*0820*/ MOV R9, UR56 ; /* 0x0000003800097c02 */
/* 0x000fe20008000f00 */
/*0830*/ IMAD.U32 R10, RZ, RZ, UR49 ; /* 0x00000031ff0a7e24 */
/* 0x002fe2000f8e00ff */
/*0840*/ MOV R11, UR46 ; /* 0x0000002e000b7c02 */
/* 0x000fe20008000f00 */
/*0850*/ LDG.E.S8 R17, [R18.64+0xe] ; /* 0x00000e0612117981 */
/* 0x0002a2000c1e1300 */
/*0860*/ IMAD.U32 R23, RZ, RZ, UR52 ; /* 0x00000034ff177e24 */
/* 0x000fe4000f8e00ff */
/*0870*/ IMAD.U32 R20, RZ, RZ, UR4 ; /* 0x00000004ff147e24 */
/* 0x000fe2000f8e00ff */
/*0880*/ ULEA.HI.X.SX32 UR4, UR34, UR9, 0x1, UP4 ; /* 0x0000000922047291 */
/* 0x000fe2000a0f0e3f */
/*0890*/ LDG.E.S8 R14, [R6.64+0x11] ; /* 0x00001106060e7981 */
/* 0x0002a2000c1e1300 */
/*08a0*/ UIADD3 UR45, UP5, UR36, UR8, URZ ; /* 0x00000008242d7290 */
/* 0x000fc6000ffbe03f */
/*08b0*/ LDG.E.S8 R12, [R2.64+0x13] ; /* 0x00001306020c7981 */
/* 0x0010a2000c1e1300 */
/*08c0*/ IMAD.U32 R19, RZ, RZ, UR48 ; /* 0x00000030ff137e24 */
/* 0x002fe2000f8e00ff */
/*08d0*/ ULEA.HI.X.SX32 UR48, UR32, UR9, 0x1, UP1 ; /* 0x0000000920307291 */
/* 0x000fe200088f0e3f */
/*08e0*/ MOV R18, UR59 ; /* 0x0000003b00127c02 */
/* 0x000fe20008000f00 */
/*08f0*/ LDG.E.S8 R15, [R10.64+0x10] ; /* 0x000010060a0f7981 */
/* 0x0002a2000c1e1300 */
/*0900*/ MOV R7, UR47 ; /* 0x0000002f00077c02 */
/* 0x000fe20008000f00 */
/*0910*/ ULEA.HI.X.SX32 UR47, UR33, UR9, 0x1, UP0 ; /* 0x00000009212f7291 */
/* 0x000fe400080f0e3f */
/*0920*/ LDG.E.S8 R24, [R8.64+0xd] ; /* 0x00000d0608187981 */
/* 0x0002a2000c1e1300 */
/*0930*/ MOV R2, UR41 ; /* 0x0000002900027c02 */
/* 0x001fe20008000f00 */
/*0940*/ ULEA.HI.X.SX32 UR41, UR35, UR9, 0x1, UP6 ; /* 0x0000000923297291 */
/* 0x000fc4000b0f0e3f */
/*0950*/ UIADD3 UR46, UP3, UR37, UR8, URZ ; /* 0x00000008252e7290 */
/* 0x000fe2000ff7e03f */
/*0960*/ LDG.E.S8 R11, [R22.64+0x14] ; /* 0x00001406160b7981 */
/* 0x0020a2000c1e1300 */
/*0970*/ IMAD.U32 R21, RZ, RZ, UR48 ; /* 0x00000030ff157e24 */
/* 0x000fe2000f8e00ff */
/*0980*/ MOV R8, UR53 ; /* 0x0000003500087c02 */
/* 0x000fe20008000f00 */
/*0990*/ IMAD.U32 R9, RZ, RZ, UR42 ; /* 0x0000002aff097e24 */
/* 0x000fe2000f8e00ff */
/*09a0*/ LDG.E.S8 R10, [R18.64+0x15] ; /* 0x00001506120a7981 */
/* 0x0002a2000c1e1300 */
/*09b0*/ IMAD.U32 R6, RZ, RZ, UR61 ; /* 0x0000003dff067e24 */
/* 0x000fe2000f8e00ff */
/*09c0*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x001fe20008000f00 */
/*09d0*/ ULEA.HI.X.SX32 UR4, UR36, UR9, 0x1, UP5 ; /* 0x0000000924047291 */
/* 0x000fe2000a8f0e3f */
/*09e0*/ IMAD.U32 R3, RZ, RZ, UR47 ; /* 0x0000002fff037e24 */
/* 0x000fe2000f8e00ff */
/*09f0*/ UIADD3 UR42, UP2, UR38, UR8, URZ ; /* 0x00000008262a7290 */
/* 0x000fe2000ff5e03f */
/*0a00*/ LDG.E.S8 R13, [R8.64+0x12] ; /* 0x00001206080d7981 */
/* 0x0000a2000c1e1300 */
/*0a10*/ MOV R19, UR41 ; /* 0x0000002900137c02 */
/* 0x002fe20008000f00 */
/*0a20*/ ULEA.HI.X.SX32 UR41, UR37, UR9, 0x1, UP3 ; /* 0x0000000925297291 */
/* 0x000fe200098f0e3f */
/*0a30*/ IMAD.U32 R22, RZ, RZ, UR43 ; /* 0x0000002bff167e24 */
/* 0x000fe2000f8e00ff */
/*0a40*/ LDG.E.S8 R8, [R20.64+0x17] ; /* 0x0000170614087981 */
/* 0x0010a8000c1e1300 */
/*0a50*/ LDG.E.S8 R9, [R6.64+0x16] ; /* 0x0000160606097981 */
/* 0x0002a2000c1e1300 */
/*0a60*/ MOV R21, UR4 ; /* 0x0000000400157c02 */
/* 0x001fe20008000f00 */
/*0a70*/ ULEA.HI.X.SX32 UR4, UR38, UR9, 0x1, UP2 ; /* 0x0000000926047291 */
/* 0x000fc400090f0e3f */
/*0a80*/ LDG.E.S8 R7, [R2.64+0x18] ; /* 0x0000180602077981 */
/* 0x0020a2000c1e1300 */
/*0a90*/ IMAD.U32 R18, RZ, RZ, UR44 ; /* 0x0000002cff127e24 */
/* 0x000fc6000f8e00ff */
/*0aa0*/ LDG.E.S8 R6, [R22.64+0x19] ; /* 0x0000190616067981 */
/* 0x0002a2000c1e1300 */
/*0ab0*/ IMAD.U32 R20, RZ, RZ, UR45 ; /* 0x0000002dff147e24 */
/* 0x000fc6000f8e00ff */
/*0ac0*/ LDG.E.S8 R0, [R18.64+0x1a] ; /* 0x00001a0612007981 */
/* 0x0002a2000c1e1300 */
/*0ad0*/ MOV R3, UR41 ; /* 0x0000002900037c02 */
/* 0x001fe20008000f00 */
/*0ae0*/ UIADD3 UR41, UP0, UR39, UR8, URZ ; /* 0x0000000827297290 */
/* 0x000fe4000ff1e03f */
/*0af0*/ LDG.E.S8 R5, [R20.64+0x1b] ; /* 0x00001b0614057981 */
/* 0x0000a2000c1e1300 */
/*0b00*/ IMAD.U32 R22, RZ, RZ, UR42 ; /* 0x0000002aff167e24 */
/* 0x002fe2000f8e00ff */
/*0b10*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x000fe20008000f00 */
/*0b20*/ ULEA.HI.X.SX32 UR42, UR39, UR9, 0x1, UP0 ; /* 0x00000009272a7291 */
/* 0x000fe400080f0e3f */
/*0b30*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe40000000800 */
/*0b40*/ UIADD3 UR4, UP0, UR8, UR4, URZ ; /* 0x0000000408047290 */
/* 0x000fe2000ff1e03f */
/*0b50*/ IMAD.U32 R18, RZ, RZ, UR41 ; /* 0x00000029ff127e24 */
/* 0x000fe2000f8e00ff */
/*0b60*/ MOV R19, UR42 ; /* 0x0000002a00137c02 */
/* 0x000fc40008000f00 */
/*0b70*/ ULEA.HI.X.SX32 UR42, UR5, UR9, 0x1, UP0 ; /* 0x00000009052a7291 */
/* 0x000fc600080f0e3f */
/*0b80*/ LDG.E.S8 R37, [R18.64+0x1e] ; /* 0x00001e0612257981 */
/* 0x0002a2000c1e1300 */
/*0b90*/ IMAD.U32 R20, RZ, RZ, UR4 ; /* 0x00000004ff147e24 */
/* 0x001fe4000f8e00ff */
/*0ba0*/ MOV R21, UR42 ; /* 0x0000002a00157c02 */
/* 0x000fcc0008000f00 */
/*0bb0*/ LDG.E.S8 R21, [R20.64+0x1] ; /* 0x0000010614157981 */
/* 0x000ea2000c1e1300 */
/*0bc0*/ MOV R18, UR8 ; /* 0x0000000800127c02 */
/* 0x002fe20008000f00 */
/*0bd0*/ IMAD.U32 R19, RZ, RZ, UR9 ; /* 0x00000009ff137e24 */
/* 0x000fca000f8e00ff */
/*0be0*/ LDG.E.S8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1300 */
/*0bf0*/ UIADD3 UR41, UP0, UR40, UR8, URZ ; /* 0x0000000828297290 */
/* 0x000fe2000ff1e03f */
/*0c00*/ IMAD.U32 R2, RZ, RZ, UR46 ; /* 0x0000002eff027e24 */
/* 0x000fc6000f8e00ff */
/*0c10*/ ULEA.HI.X.SX32 UR4, UR40, UR9, 0x1, UP0 ; /* 0x0000000928047291 */
/* 0x000fe400080f0e3f */
/*0c20*/ LDG.E.S8 R3, [R2.64+0x1c] ; /* 0x00001c0602037981 */
/* 0x0000e8000c1e1300 */
/*0c30*/ LDG.E.S8 R2, [R22.64+0x1d] ; /* 0x00001d0616027981 */
/* 0x001164000c1e1300 */
/*0c40*/ IMAD.U32 R22, RZ, RZ, UR41 ; /* 0x00000029ff167e24 */
/* 0x001fe2000f8e00ff */
/*0c50*/ MOV R23, UR4 ; /* 0x0000000400177c02 */
/* 0x000fca0008000f00 */
/*0c60*/ LDG.E.S8 R22, [R22.64+0x1f] ; /* 0x00001f0616167981 */
/* 0x000f62000c1e1300 */
/*0c70*/ IADD3 R4, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R4, 0x200, PT ; /* 0x000002000400780c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP0, UR10, UR8, URZ ; /* 0x000000080a087290 */
/* 0x000fc8000ff1e03f */
/*0ca0*/ ULEA.HI.X.SX32 UR9, UR10, UR9, 0x1, UP0 ; /* 0x000000090a097291 */
/* 0x000fe200080f0e3f */
/*0cb0*/ IADD3 R36, R21, R36, R18 ; /* 0x0000002415247210 */
/* 0x004fc80007ffe012 */
/*0cc0*/ IADD3 R34, R34, R36, R35 ; /* 0x0000002422227210 */
/* 0x000fc80007ffe023 */
/*0cd0*/ IADD3 R32, R32, R34, R33 ; /* 0x0000002220207210 */
/* 0x008fc80007ffe021 */
/*0ce0*/ IADD3 R30, R30, R32, R31 ; /* 0x000000201e1e7210 */
/* 0x010fc80007ffe01f */
/*0cf0*/ IADD3 R28, R28, R30, R29 ; /* 0x0000001e1c1c7210 */
/* 0x000fc80007ffe01d */
/*0d00*/ IADD3 R26, R26, R28, R27 ; /* 0x0000001c1a1a7210 */
/* 0x020fc80007ffe01b */
/*0d10*/ IADD3 R24, R24, R26, R25 ; /* 0x0000001a18187210 */
/* 0x000fc80007ffe019 */
/*0d20*/ IADD3 R16, R16, R24, R17 ; /* 0x0000001810107210 */
/* 0x000fc80007ffe011 */
/*0d30*/ IADD3 R14, R14, R16, R15 ; /* 0x000000100e0e7210 */
/* 0x000fc80007ffe00f */
/*0d40*/ IADD3 R12, R12, R14, R13 ; /* 0x0000000e0c0c7210 */
/* 0x000fc80007ffe00d */
/*0d50*/ IADD3 R10, R10, R12, R11 ; /* 0x0000000c0a0a7210 */
/* 0x000fc80007ffe00b */
/*0d60*/ IADD3 R8, R8, R10, R9 ; /* 0x0000000a08087210 */
/* 0x000fc80007ffe009 */
/*0d70*/ IADD3 R6, R6, R8, R7 ; /* 0x0000000806067210 */
/* 0x000fc80007ffe007 */
/*0d80*/ IADD3 R0, R5, R6, R0 ; /* 0x0000000605007210 */
/* 0x000fc80007ffe000 */
/*0d90*/ IADD3 R0, R2, R0, R3 ; /* 0x0000000002007210 */
/* 0x000fc80007ffe003 */
/*0da0*/ IADD3 R36, R22, R0, R37 ; /* 0x0000000016247210 */
/* 0x000fe20007ffe025 */
/*0db0*/ @P0 BRA 0x280 ; /* 0xfffff4c000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0dd0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0de0*/ STG.E [R2.64], R36 ; /* 0x0000002402007986 */
/* 0x000fe2000c101906 */
/*0df0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3SetiiPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD R5, R4, R4.reuse, c[0x0][0x160] ; /* 0x0000580004057624 */
/* 0x081fe200078e0204 */
/*0040*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fc80000000f00 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0.reuse, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x040fe400000f0eff */
/*0070*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc60007ffe0ff */
/*0080*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101104 */
/*0090*/ IMAD R5, R4, c[0x0][0x0], R5 ; /* 0x0000000004057a24 */
/* 0x001fe200078e0205 */
/*00a0*/ BRA 0x50 ; /* 0xffffffa000007947 */
/* 0x000fea000383ffff */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <string>
#include <cstdlib>
// 2 GB of data
#define BYTES 2147483648
#define MAX_STRIDE 4194304
#define MAX_INDEX (BYTES/MAX_STRIDE)
static void __global__
Set(const int Seed, const int Stride, char *data) {
// Everyone set some data
for(int i = threadIdx.x; i < BYTES ; i+= blockDim.x ) {
data[i] = (char)(i * threadIdx.x + Seed);
}
}
static void __global__
CacheTest(const int Seed , const int Stride , char *data, int *result ) {
if(threadIdx.x == 0 ) {
int local_result = 0;
for(int i = 0 ; i < MAX_INDEX; ++i) {
local_result += data[i *(Stride+1)];
}
*result = local_result; // Here to make sure we don't optimize the loop away
}
}
static void Validate(bool cond, std::string msg) {
if(!cond) {
std::cout << msg << std::endl;
cudaDeviceReset();
std::exit(EXIT_FAILURE);
}
}
static void CudaCheck(std::string msg, cudaError err) {
Validate(err==cudaSuccess, cudaGetErrorString(err) + std::string("\n") + msg);
}
void sort(float *durations, int size) {
for(int i = 1 ; i < size; ++i) {
float cand = durations[i];
int j = i;
while( j > 0 && cand < durations[j-1]) {
if(durations[j] < durations[j-1]) {
durations[j] = durations[j-1];
}
--j;
}
durations[j] = cand;
}
}
float Run(const int Seed, const int Stride) {
const int Blocks = 1;
const int Threads = 1024;
float time;
cudaEvent_t start,end;
char *d_data;
int *d_result;
CudaCheck("Malloc Result", cudaMalloc(&d_result, sizeof(int) ) );
CudaCheck("Malloc Data", cudaMalloc(&d_data, BYTES ) );
CudaCheck("Memset Result", cudaMemset(d_result, 0, sizeof(int) ) );
CudaCheck("Memset Data", cudaMemset(d_data, 0, BYTES ) );
Set<<<Blocks,Threads>>>(Seed, Stride, d_data);
CudaCheck("Set",cudaDeviceSynchronize());
CudaCheck("Create start",cudaEventCreate(&start));
CudaCheck("Create end",cudaEventCreate(&end));
CudaCheck("Record start",cudaEventRecord(start,0));
CacheTest<<<Blocks,Threads>>>(Seed, Stride, d_data, d_result);
CudaCheck("Record end",cudaEventRecord(end,0));
CudaCheck("Device Sync",cudaDeviceSynchronize());
CudaCheck("Event sync", cudaEventSynchronize(end) );
CudaCheck("Get elapsed time",cudaEventElapsedTime(&time,start,end));
CudaCheck("Destroy start",cudaEventDestroy(start));
CudaCheck("Destroy end",cudaEventDestroy(end));
CudaCheck("Free result", cudaFree(d_result));
CudaCheck("Free data", cudaFree(d_data));
CudaCheck("Reset",cudaDeviceReset());
return time;
}
int main(int argc, char* argv[]) {
const int Runs = 50;
float durations[Runs];
Validate(argc==2,"Usage: " + std::string(argv[0]) + " stride");
const int Stride = atoi(argv[1]);
Validate(Stride <= MAX_STRIDE,"Decrease Stride");
std::cout << "Stride: " << Stride << std::endl;
for(int i = 0 ; i < Runs ; ++i ) {
durations[i] = Run(i+1, Stride);
}
sort(durations,Runs);
float time = 0;
int count = 0;
for(int i = 0; i < Runs; ++i) {
time += durations[i];
++count;
}
time /= count;
std::cout << "Elapsed Time: " << time << "ms" << std::endl;
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <cstdlib>
// 2 GB of data
#define BYTES 2147483648
#define MAX_STRIDE 4194304
#define MAX_INDEX (BYTES/MAX_STRIDE)
static void __global__
Set(const int Seed, const int Stride, char *data) {
// Everyone set some data
for(int i = threadIdx.x; i < BYTES ; i+= blockDim.x ) {
data[i] = (char)(i * threadIdx.x + Seed);
}
}
static void __global__
CacheTest(const int Seed , const int Stride , char *data, int *result ) {
if(threadIdx.x == 0 ) {
int local_result = 0;
for(int i = 0 ; i < MAX_INDEX; ++i) {
local_result += data[i *(Stride+1)];
}
*result = local_result; // Here to make sure we don't optimize the loop away
}
}
static void Validate(bool cond, std::string msg) {
if(!cond) {
std::cout << msg << std::endl;
hipDeviceReset();
std::exit(EXIT_FAILURE);
}
}
static void CudaCheck(std::string msg, hipError_t err) {
Validate(err==hipSuccess, hipGetErrorString(err) + std::string("\n") + msg);
}
void sort(float *durations, int size) {
for(int i = 1 ; i < size; ++i) {
float cand = durations[i];
int j = i;
while( j > 0 && cand < durations[j-1]) {
if(durations[j] < durations[j-1]) {
durations[j] = durations[j-1];
}
--j;
}
durations[j] = cand;
}
}
float Run(const int Seed, const int Stride) {
const int Blocks = 1;
const int Threads = 1024;
float time;
hipEvent_t start,end;
char *d_data;
int *d_result;
CudaCheck("Malloc Result", hipMalloc(&d_result, sizeof(int) ) );
CudaCheck("Malloc Data", hipMalloc(&d_data, BYTES ) );
CudaCheck("Memset Result", hipMemset(d_result, 0, sizeof(int) ) );
CudaCheck("Memset Data", hipMemset(d_data, 0, BYTES ) );
Set<<<Blocks,Threads>>>(Seed, Stride, d_data);
CudaCheck("Set",hipDeviceSynchronize());
CudaCheck("Create start",hipEventCreate(&start));
CudaCheck("Create end",hipEventCreate(&end));
CudaCheck("Record start",hipEventRecord(start,0));
CacheTest<<<Blocks,Threads>>>(Seed, Stride, d_data, d_result);
CudaCheck("Record end",hipEventRecord(end,0));
CudaCheck("Device Sync",hipDeviceSynchronize());
CudaCheck("Event sync", hipEventSynchronize(end) );
CudaCheck("Get elapsed time",hipEventElapsedTime(&time,start,end));
CudaCheck("Destroy start",hipEventDestroy(start));
CudaCheck("Destroy end",hipEventDestroy(end));
CudaCheck("Free result", hipFree(d_result));
CudaCheck("Free data", hipFree(d_data));
CudaCheck("Reset",hipDeviceReset());
return time;
}
int main(int argc, char* argv[]) {
const int Runs = 50;
float durations[Runs];
Validate(argc==2,"Usage: " + std::string(argv[0]) + " stride");
const int Stride = atoi(argv[1]);
Validate(Stride <= MAX_STRIDE,"Decrease Stride");
std::cout << "Stride: " << Stride << std::endl;
for(int i = 0 ; i < Runs ; ++i ) {
durations[i] = Run(i+1, Stride);
}
sort(durations,Runs);
float time = 0;
int count = 0;
for(int i = 0; i < Runs; ++i) {
time += durations[i];
++count;
}
time /= count;
std::cout << "Elapsed Time: " << time << "ms" << std::endl;
return EXIT_SUCCESS;
} |
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