system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This is based on an example developed by Mark Harris for his NVIDIA blog:
http://devblogs.nvidia.com/parallelforall/gpu-pro-tip-cuda-7-streams-simplify-concurrency/
-- I have added some timing to it
*/
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
const int N = 1 << 20;
__global__ void kernel(float *x, int n)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (int i = tid; i < n; i += blockDim.x * gridDim.x) {
x[i] = sqrt(pow(3.14159,i));
}
}
int main()
{
// initialise CUDA timing, and start timer
float milli;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
float *h_data, *d_data;
h_data = (float *) malloc(sizeof(float));
hipMalloc(&d_data, sizeof(float));
h_data[0] = 1.0f;
// set up 8 streams
const int num_streams = 8;
hipStream_t streams[num_streams];
float *data[num_streams];
// loop over 8 streams
for (int i = 0; i < num_streams; i++) {
hipStreamCreate(&streams[i]);
hipMalloc(&data[i], N * sizeof(float));
// launch one worker kernel per stream
kernel<<<1, 64, 0, streams[i]>>>(data[i], N);
// do a Memcpy and launch a dummy kernel on the default stream
hipMemcpy(d_data,h_data,sizeof(float),hipMemcpyHostToDevice);
kernel<<<1, 1>>>(d_data, 0);
}
// wait for completion of all kernels
hipDeviceSynchronize();
// stop timer and report execution time
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
printf("execution time (ms): %f \n",milli);
hipDeviceReset();
return 0;
} | .text
.file "stream_test.hip"
.globl _Z21__device_stub__kernelPfi # -- Begin function _Z21__device_stub__kernelPfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfi,@function
_Z21__device_stub__kernelPfi: # @_Z21__device_stub__kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfi, .Lfunc_end0-_Z21__device_stub__kernelPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 96(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1065353216, (%r14) # imm = 0x3F800000
leaq 63(%rbx), %r15
leaq 80(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
addq $8, %r12
cmpq $64, %r12
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $112, %rdi
callq hipStreamCreate
leaq (%rsp,%r12), %rbp
addq $176, %rbp
movl $4194304, %esi # imm = 0x400000
movq %rbp, %rdi
callq hipMalloc
movq 112(%rsp,%r12), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq (%rbp), %rax
movq %rax, 72(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPfi, %edi
movq %r13, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 96(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq 96(%rsp), %rax
movq %rax, 72(%rsp)
movl $0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPfi, %edi
movq %r13, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 104(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfi,@object # @_Z6kernelPfi
.section .rodata,"a",@progbits
.globl _Z6kernelPfi
.p2align 3, 0x0
_Z6kernelPfi:
.quad _Z21__device_stub__kernelPfi
.size _Z6kernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "execution time (ms): %f \n"
.size .L.str, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e2d2a_00000000-6_stream_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPfiPfi
.type _Z26__device_stub__Z6kernelPfiPfi, @function
_Z26__device_stub__Z6kernelPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6kernelPfiPfi, .-_Z26__device_stub__Z6kernelPfiPfi
.globl _Z6kernelPfi
.type _Z6kernelPfi, @function
_Z6kernelPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfi, .-_Z6kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "execution time (ms): %f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0x3f800000, (%r12)
leaq 48(%rsp), %rbx
leaq 112(%rsp), %rbp
movq %rbp, %r13
jmp .L14
.L12:
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
addq $8, %rbx
addq $8, %rbp
cmpq %r13, %rbx
je .L19
.L14:
movq %rbx, %rdi
call cudaStreamCreate@PLT
movl $4194304, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movq (%rbx), %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 0(%rbp), %rdi
movl $1048576, %esi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L12
.L18:
movl $0, %esi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z6kernelPfiPfi
jmp .L13
.L19:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream_test.hip"
.globl _Z21__device_stub__kernelPfi # -- Begin function _Z21__device_stub__kernelPfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfi,@function
_Z21__device_stub__kernelPfi: # @_Z21__device_stub__kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfi, .Lfunc_end0-_Z21__device_stub__kernelPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 96(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1065353216, (%r14) # imm = 0x3F800000
leaq 63(%rbx), %r15
leaq 80(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
addq $8, %r12
cmpq $64, %r12
je .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r12), %rdi
addq $112, %rdi
callq hipStreamCreate
leaq (%rsp,%r12), %rbp
addq $176, %rbp
movl $4194304, %esi # imm = 0x400000
movq %rbp, %rdi
callq hipMalloc
movq 112(%rsp,%r12), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq (%rbp), %rax
movq %rax, 72(%rsp)
movl $1048576, 12(%rsp) # imm = 0x100000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPfi, %edi
movq %r13, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq 96(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq 96(%rsp), %rax
movq %rax, 72(%rsp)
movl $0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPfi, %edi
movq %r13, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 104(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceReset
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfi,@object # @_Z6kernelPfi
.section .rodata,"a",@progbits
.globl _Z6kernelPfi
.p2align 3, 0x0
_Z6kernelPfi:
.quad _Z21__device_stub__kernelPfi
.size _Z6kernelPfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "execution time (ms): %f \n"
.size .L.str, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z19STREAM_Scale_doublePdS_dm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x3, R9 ; /* 0x0000000300077819 */
/* 0x000fc80000010209 */
/*00c0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fc600078e02ff */
/*0110*/ IADD3.X R7, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007077a10 */
/* 0x000fe400007fe4ff */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fca0007f1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x17c], PT, P0 ; /* 0x00005f0009007a0c */
/* 0x000fe20003f06100 */
/*0160*/ DMUL R2, R2, c[0x0][0x170] ; /* 0x00005c0002027a28 */
/* 0x004e0e0000000000 */
/*0170*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0011ea000c101b04 */
/*0180*/ @!P0 BRA 0xa0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .file "tmpxft_0015a85a_00000000-6_STREAM_Scale_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
.type _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm, @function
_Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19STREAM_Scale_doublePdS_dm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm, .-_Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
.globl _Z19STREAM_Scale_doublePdS_dm
.type _Z19STREAM_Scale_doublePdS_dm, @function
_Z19STREAM_Scale_doublePdS_dm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19STREAM_Scale_doublePdS_dm, .-_Z19STREAM_Scale_doublePdS_dm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19STREAM_Scale_doublePdS_dm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19STREAM_Scale_doublePdS_dm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19STREAM_Scale_doublePdS_dm
.globl _Z19STREAM_Scale_doublePdS_dm
.p2align 8
.type _Z19STREAM_Scale_doublePdS_dm,@function
_Z19STREAM_Scale_doublePdS_dm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 3
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[5:6], v[5:6], off
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_mul_f64 v[5:6], v[5:6], s[8:9]
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19STREAM_Scale_doublePdS_dm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19STREAM_Scale_doublePdS_dm, .Lfunc_end0-_Z19STREAM_Scale_doublePdS_dm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19STREAM_Scale_doublePdS_dm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19STREAM_Scale_doublePdS_dm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void STREAM_Scale_double(double *a, double *b, double scale, size_t len)
{
size_t idx = threadIdx.x + blockIdx.x * blockDim.x;
while (idx < len) {
b[idx] = scale* a[idx];
idx += blockDim.x * gridDim.x;
}
} | .text
.file "STREAM_Scale_double.hip"
.globl _Z34__device_stub__STREAM_Scale_doublePdS_dm # -- Begin function _Z34__device_stub__STREAM_Scale_doublePdS_dm
.p2align 4, 0x90
.type _Z34__device_stub__STREAM_Scale_doublePdS_dm,@function
_Z34__device_stub__STREAM_Scale_doublePdS_dm: # @_Z34__device_stub__STREAM_Scale_doublePdS_dm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19STREAM_Scale_doublePdS_dm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__STREAM_Scale_doublePdS_dm, .Lfunc_end0-_Z34__device_stub__STREAM_Scale_doublePdS_dm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19STREAM_Scale_doublePdS_dm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19STREAM_Scale_doublePdS_dm,@object # @_Z19STREAM_Scale_doublePdS_dm
.section .rodata,"a",@progbits
.globl _Z19STREAM_Scale_doublePdS_dm
.p2align 3, 0x0
_Z19STREAM_Scale_doublePdS_dm:
.quad _Z34__device_stub__STREAM_Scale_doublePdS_dm
.size _Z19STREAM_Scale_doublePdS_dm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19STREAM_Scale_doublePdS_dm"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__STREAM_Scale_doublePdS_dm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19STREAM_Scale_doublePdS_dm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19STREAM_Scale_doublePdS_dm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.SHL.U32 R6, R0.reuse, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x041fe200078e00ff */
/*00b0*/ SHF.L.U64.HI R7, R0, 0x3, R9 ; /* 0x0000000300077819 */
/* 0x000fc80000010209 */
/*00c0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ IADD3.X R5, R7, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590007057a10 */
/* 0x000fca00007fe4ff */
/*00e0*/ LDG.E.64 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IADD3 R6, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fc600078e02ff */
/*0110*/ IADD3.X R7, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007077a10 */
/* 0x000fe400007fe4ff */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fca0007f1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x17c], PT, P0 ; /* 0x00005f0009007a0c */
/* 0x000fe20003f06100 */
/*0160*/ DMUL R2, R2, c[0x0][0x170] ; /* 0x00005c0002027a28 */
/* 0x004e0e0000000000 */
/*0170*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0011ea000c101b04 */
/*0180*/ @!P0 BRA 0xa0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19STREAM_Scale_doublePdS_dm
.globl _Z19STREAM_Scale_doublePdS_dm
.p2align 8
.type _Z19STREAM_Scale_doublePdS_dm,@function
_Z19STREAM_Scale_doublePdS_dm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s12, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_mov_b32 s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s11
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s12, s10
s_lshl_b64 s[12:13], s[10:11], 3
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s10
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b64 v[5:6], v[5:6], off
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_mul_f64 v[5:6], v[5:6], s[8:9]
global_store_b64 v[7:8], v[5:6], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19STREAM_Scale_doublePdS_dm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19STREAM_Scale_doublePdS_dm, .Lfunc_end0-_Z19STREAM_Scale_doublePdS_dm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19STREAM_Scale_doublePdS_dm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19STREAM_Scale_doublePdS_dm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015a85a_00000000-6_STREAM_Scale_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
.type _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm, @function
_Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19STREAM_Scale_doublePdS_dm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm, .-_Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
.globl _Z19STREAM_Scale_doublePdS_dm
.type _Z19STREAM_Scale_doublePdS_dm, @function
_Z19STREAM_Scale_doublePdS_dm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19STREAM_Scale_doublePdS_dmPdS_dm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19STREAM_Scale_doublePdS_dm, .-_Z19STREAM_Scale_doublePdS_dm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19STREAM_Scale_doublePdS_dm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19STREAM_Scale_doublePdS_dm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "STREAM_Scale_double.hip"
.globl _Z34__device_stub__STREAM_Scale_doublePdS_dm # -- Begin function _Z34__device_stub__STREAM_Scale_doublePdS_dm
.p2align 4, 0x90
.type _Z34__device_stub__STREAM_Scale_doublePdS_dm,@function
_Z34__device_stub__STREAM_Scale_doublePdS_dm: # @_Z34__device_stub__STREAM_Scale_doublePdS_dm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19STREAM_Scale_doublePdS_dm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__STREAM_Scale_doublePdS_dm, .Lfunc_end0-_Z34__device_stub__STREAM_Scale_doublePdS_dm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19STREAM_Scale_doublePdS_dm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19STREAM_Scale_doublePdS_dm,@object # @_Z19STREAM_Scale_doublePdS_dm
.section .rodata,"a",@progbits
.globl _Z19STREAM_Scale_doublePdS_dm
.p2align 3, 0x0
_Z19STREAM_Scale_doublePdS_dm:
.quad _Z34__device_stub__STREAM_Scale_doublePdS_dm
.size _Z19STREAM_Scale_doublePdS_dm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19STREAM_Scale_doublePdS_dm"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__STREAM_Scale_doublePdS_dm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19STREAM_Scale_doublePdS_dm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
#define PI 3.141592653589793
#define left ((ix-1) + Nx*iz) //Izquierda
#define top (ix + Nx*(iz-1)) //Arriba
#define center (ix + Nx*iz) //Centro
#define bottom (ix + Nx*(iz+1)) //Abajo
#define right ((ix+1) + Nx*iz) //Derecha
// A = Presente
// B = Pasado
// C = Futuro
//DEVICE CODE - Kernel1
__global__ void kernel_lap(float *lap, float *A, int nx, int ny, float dh){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< ny-4){
lap[tid] =((-1./560)*(A[ tid - 4 ] + A[tid + 4] + A[tid + 4*nx ] + A[tid -4*nx]) +
(8./315)*(A[ tid - 3 ] + A[tid + 3] + A[tid + 3*nx ] + A[tid -3*nx]) +
(-1./5)*(A[ tid - 2 ] + A[tid + 2] + A[tid + 2*nx ] + A[tid -2*nx]) +
(8./5)*(A[ tid - 1 ] + A[tid + 1] + A[tid + 1*nx ] + A[tid -1*nx]) +
(-205./36)*(A[tid]))/(dh*dh);
__syncthreads();
}
}
__global__
void get_CPML_x(float *a_x, float *b_x, int CPMLimit, float R, float VelMax, int Nx, float dt, float dh, float frec){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lx = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lx);
a_x[ix] = 0;
b_x[ix] = 0;
if (ix<CPMLimit+1) //Left CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx))*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx));
__syncthreads();
__syncthreads();
}
if (ix>(Nx-CPMLimit-1) && ix<Nx) //Right CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) )*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) );
__syncthreads();
__syncthreads();
}
}
__global__
void get_CPML_z(float *a_z, float *b_z, int CPMLimit, float R, float VelMax, int Nz, float dt, float dh, float frec){
//dh = dx; Notacion
int iz = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lz = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lz);
//Inicializando valores de CPML
a_z[iz] = 0;
b_z[iz] = 0;
if (iz>(Nz-CPMLimit-1) && iz<Nz) //bottom CPML
{
b_z[iz] = exp(-( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) )*dt);
__syncthreads();
a_z[iz] = (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) * ( b_z[iz] - 1 ) / ( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) );
__syncthreads();
}
}
__global__
void PSI(float *A, float *a_x, float *b_x, float *a_z, float *b_z, float *Psi_x, float *Psi_z, int CPMLimit, int Nx, int Nz, float dh){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Row of the A matrix
int iz = threadIdx.y + blockDim.y * blockIdx.y; // Column of the A matrix
int tid = ix + iz*Nx;
if(ix > 3 && ix < Nx-4 && iz > 3 && iz< Nz-4)
{
// Primera derivada de segundo orden centrada
/*
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (-1./2)*A[tid-1] + (1./2)*A[tid+1])/(2*dh);
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (-1./2)*A[tid-Nx] + (1./2)*A[tid+Nx])/(2*dh);
*/
// Primera derivada de octavo orden centrada
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (1./280.)*A[tid-4] - (4./105.)*A[tid-3] + (1./5.)*A[tid-2] - (4./5.)*A[tid-1] + (4./5.)*A[tid+1] + (-1./5.)*A[tid+2] + (4./105.)*A[tid+3] + (-1./280.)*A[tid+4] )/(dh);
__syncthreads();
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (1./280.)*A[tid-4*Nx] + (-4./105.)*A[tid-3*Nx] + (1./5.)*A[tid-2*Nx] + (-4./5.)*A[tid-1*Nx] + (4./5.)*A[tid+1*Nx] + (-1./5.)*A[tid+2*Nx] + (4./105.)*A[tid+3*Nx] + (-1./280.)*A[tid+4*Nx] )/(dh);
__syncthreads();
}
}
__global__
void kernel_propaga(float *lap, float *A, float *B, int nx, int nz, float *source, float *c, float *traza, float *P, float *dP, int it, int sx, int sz, int borde, float dt, float *a_z, float *a_x, float *b_z, float *b_x, float *Psi_x, float *Psi_z, float *Z_x, float *Z_z, float *temp, float dh, int modo){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
float G = c[tid]*c[tid]*dt*dt;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4){
// Calculo de las derivadas de psi
// Primera derivada de segundo orden central
//temp[tid]=((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/(2*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/(2*dh);
// Primera derivada octavo orden central
temp[tid]=( (1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1]
+ (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh)
+ ( (1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx]
+ (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh);
__syncthreads();
// Calculo de los zetas
// Derivadas de segundo orden
// Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( (A[tid+1] -2*A[tid] + A[tid-1])/(dh*dh) + ((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/dh);
// Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( (A[tid-nx] -2*A[tid] + A[tid+nx])/(dh*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/dh);
// Derivadas de octavo orden
Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( ( (-1./560)*A[tid-4] + (8./315)*A[tid-3] + (-1./5)*A[tid-2] + (8./5)*A[tid-1] + (-205./72)*A[tid] + (8./5)*A[tid+1] + (-1./5)*A[tid+2] + (8./315)*A[tid+3] + (-1./560)*A[tid+4] )/(dh*dh) + ((1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1] + (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh*dh));
__syncthreads();
Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( ( (-1./560)*A[tid-4*nx] + (8./315)*A[tid-3*nx] + (-1./5)*A[tid-2*nx] + (8./5)*A[tid-1*nx] + (-205./72)*A[tid] + (8./5)*A[tid+1*nx] + (-1./5)*A[tid+2*nx] + (8./315)*A[tid+3*nx] + (-1./560)*A[tid+4*nx] )/(dh*dh) + ((1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx] + (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh*dh));
__syncthreads();
}
//if(ix<nx-1 && iy<nz-1){
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4 ){
B[tid]=2*A[tid] - B[tid] + G*( lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix < nx && iy< nz){
// if(it<Nt){
if(ix==(sx-1+4) && iy==(sz-1+4)){
A[tid] = A[tid] + source[it];
__syncthreads();
}
// }
if(modo==1 || modo==3 ){
P[tid+nx*nz*it]=B[tid];
__syncthreads();
}
if(modo==2 || modo==3 ){
dP[tid+nx*nz*it]=c[tid]*c[tid]*(lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix>=borde && ix< nx-borde && iy==sz-1+4){
traza[(ix-borde)+it*(nx-2*borde)]=B[tid];
__syncthreads();
}
}
__syncthreads();
}
// A = Presente
// B = Pasado
// C = Futuro
//HOST CODE
int main(){
cudaDeviceReset();
//variables host
int borde=20;
int nx=210;
int ny=71;
int modo=1;
int it;
int nt;
int sx = ceil(nx/2);
int sz = 6;
float VelMax=4700;
float R=100e-6;
float frec=3;
float tend=1.0;
float dt=0.001;
float dh=25;
float *A_d, *B_d, *Pt_d, *Pt_h, *P_d, *P_h, *dP_d, *dP_h, *s_h, *s_d, *v_d, *v_h, *A_x, *A_z, *B_x, *B_z, *lap, *temp, *temp1, *Psi_x, *Psi_z, *Z_x, *Z_z;
FILE *source, *model_ori;
nt= ceil(tend/dt);
Pt_h = (float *)calloc((nx-2*borde)*nt,sizeof(float));
v_h = (float *)calloc(nx*ny,sizeof(float));
s_h = (float *)calloc(nt,sizeof(float));
P_h = (float *)calloc(nx*ny*nt,sizeof(float));
dP_h = (float *)calloc(nx*ny*nt,sizeof(float));
//variables y memory allocation en device
cudaMalloc(&Pt_d,(nx-2*borde)*nt*sizeof(float));
cudaMalloc(&A_d, nx*ny*sizeof(float));
cudaMalloc(&B_d, nx*ny*sizeof(float));
cudaMalloc(&P_d, nx*ny*nt*sizeof(float));
cudaMalloc(&dP_d, nx*ny*nt*sizeof(float));
cudaMalloc(&s_d, nt*sizeof(float));
cudaMalloc(&v_d, nx*ny*sizeof(float));
cudaMalloc(&lap, nx*ny*sizeof(float));
cudaMalloc(&Psi_x, nx*ny*sizeof(float));
cudaMalloc(&Psi_z, nx*ny*sizeof(float));
cudaMalloc(&Z_x, nx*ny*sizeof(float));
cudaMalloc(&Z_z, nx*ny*sizeof(float));
cudaMalloc(&temp1, nx*ny*sizeof(float));
cudaMalloc(&A_x, nx*sizeof(float));
cudaMalloc(&A_z, ny*sizeof(float));
cudaMalloc(&B_x, nx*sizeof(float));
cudaMalloc(&B_z, ny*sizeof(float));
cudaMemset(A_d,0,nx*ny*sizeof(float));
cudaMemset(B_d,0,nx*ny*sizeof(float));
cudaMemset(lap,0,nx*ny*sizeof(float));
cudaMemset(Psi_x,0,nx*ny*sizeof(float));
cudaMemset(Psi_z,0,nx*ny*sizeof(float));
cudaMemset(Z_x,0,nx*ny*sizeof(float));
cudaMemset(Z_z,0,nx*ny*sizeof(float));
cudaMemset(temp1,0,nx*ny*sizeof(float));
cudaMemset(A_x,0,nx*sizeof(float));
cudaMemset(A_z,0,ny*sizeof(float));
cudaMemset(B_x,0,nx*sizeof(float));
cudaMemset(B_z,0,ny*sizeof(float));
//Leer y condicionar archivos fuente
source = fopen ("Fuente.bin","rb");
fread(s_h,nt*sizeof(float),1,source);
printf("\nDatos de fuente cargados...\n");
fclose(source);
//Leer y condicionar archivos modelo original
model_ori = fopen ("Modelo_ori.bin","rb");
fread(v_h,nx*ny*sizeof(float),1,model_ori);
printf("\nDatos de modelo original cargados...\n");
fclose(model_ori);
//Enviando informacion necesaria a la GPU
cudaMemcpy(v_d, v_h, nx*ny*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(s_d, s_h, nt*sizeof(float), cudaMemcpyHostToDevice);
//ejecución Kernel
dim3 dimGrid_M(ceil((nx) / (float)TILE_WIDTH_X) , ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_M(TILE_WIDTH_X , TILE_WIDTH_Y);
dim3 dimGrid_Vx(ceil((nx) / (float)TILE_WIDTH_X));
dim3 dimBlock_Vx(TILE_WIDTH_X);
dim3 dimGrid_Vz(ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_Vz(TILE_WIDTH_Y);
get_CPML_x<<<dimGrid_Vx, dimBlock_Vx>>>(A_x, B_x, borde, R, VelMax, nx, dt, dh, frec);
get_CPML_z<<<dimGrid_Vz, dimBlock_Vz>>>(A_z, B_z, borde, R, VelMax, ny, dt, dh, frec);
for (it=0;it<nt;it++){
printf("Voy en el paso temporal %d \n",it+1);
PSI<<<dimGrid_M, dimBlock_M>>>(A_d, A_x, B_x, A_z, B_z, Psi_x, Psi_z, borde, nx, ny, dh);
kernel_lap<<<dimGrid_M, dimBlock_M>>>(lap,A_d,nx,ny,dh); //#blocks=dimGrid, #threads=dimBlock
kernel_propaga<<<dimGrid_M, dimBlock_M>>>(lap,A_d,B_d,nx,ny,s_d,v_d,Pt_d,P_d,dP_d,it,sx,sz,borde,dt,A_z,A_x,B_z,B_x,Psi_x,Psi_z,Z_x,Z_z,temp1,dh,modo); //#blocks=dimGrid,
temp = A_d;
A_d = B_d;
B_d = temp;
}
if(modo==1 || modo==3){
cudaMemcpy(P_h, P_d, nx*ny*nt*sizeof(float), cudaMemcpyDeviceToHost);
}
if(modo==2 || modo==3){
cudaMemcpy(dP_h, dP_d, nx*ny*nt*sizeof(float), cudaMemcpyDeviceToHost);
}
cudaMemcpy(Pt_h, Pt_d, (nx-2*borde)*nt*sizeof(float), cudaMemcpyDeviceToHost);
//---------------------------------------
// Guarda informacion -----------------------
// Trazas
source=fopen("Trazas.bin","wb");
fwrite(Pt_h,sizeof(float),(nx-2*borde)*nt,source);
fclose(source);
free(Pt_h);
cudaFree(Pt_d);
// Frente de Onda
source=fopen("Frentedeonda.bin","wb");
fwrite(P_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(P_h);
cudaFree(P_d);
// Derivad Frente de Onda
source=fopen("DerivadaFrentedeOnda.bin","wb");
fwrite(dP_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(dP_h);
cudaFree(dP_d);
// Liberamos resto de punteros
// Host
free(s_h);
free(v_h);
// Device
cudaFree(A_d);
cudaFree(B_d);
cudaFree(lap);
cudaFree(s_d);
cudaFree(v_d);
cudaFree(A_x);
cudaFree(A_z);
cudaFree(B_x);
cudaFree(B_z);
cudaFree(Psi_x);
cudaFree(Psi_z);
cudaFree(Z_x);
cudaFree(Z_z);
printf("\n Creo que Termine ....\n");
cudaDeviceReset();
return 0;
} | .file "tmpxft_00008543_00000000-6_propagator_8_cpml.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif
.type _Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif, @function
_Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_lapPfS_iif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif, .-_Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif
.globl _Z10kernel_lapPfS_iif
.type _Z10kernel_lapPfS_iif, @function
_Z10kernel_lapPfS_iif:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10kernel_lapPfS_iif, .-_Z10kernel_lapPfS_iif
.globl _Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff
.type _Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff, @function
_Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10get_CPML_xPfS_iffifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff, .-_Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff
.globl _Z10get_CPML_xPfS_iffifff
.type _Z10get_CPML_xPfS_iffifff, @function
_Z10get_CPML_xPfS_iffifff:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10get_CPML_xPfS_iffifff, .-_Z10get_CPML_xPfS_iffifff
.globl _Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff
.type _Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff, @function
_Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff:
.LFB2086:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10get_CPML_zPfS_iffifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff, .-_Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff
.globl _Z10get_CPML_zPfS_iffifff
.type _Z10get_CPML_zPfS_iffifff, @function
_Z10get_CPML_zPfS_iffifff:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10get_CPML_zPfS_iffifff, .-_Z10get_CPML_zPfS_iffifff
.globl _Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif
.type _Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif, @function
_Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif:
.LFB2088:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 4(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3PSIPfS_S_S_S_S_S_iiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif, .-_Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif
.globl _Z3PSIPfS_S_S_S_S_S_iiif
.type _Z3PSIPfS_S_S_S_S_S_iiif, @function
_Z3PSIPfS_S_S_S_S_S_iiif:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z3PSIPfS_S_S_S_S_S_iiif, .-_Z3PSIPfS_S_S_S_S_S_iiif
.globl _Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.type _Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, @function
_Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi:
.LFB2090:
.cfi_startproc
endbr64
subq $456, %rsp
.cfi_def_cfa_offset 464
movq %rdi, 152(%rsp)
movq %rsi, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ecx, 132(%rsp)
movl %r8d, 128(%rsp)
movq %r9, 120(%rsp)
movss %xmm0, 84(%rsp)
movss %xmm1, 80(%rsp)
movq 464(%rsp), %rax
movq %rax, 112(%rsp)
movq 472(%rsp), %rax
movq %rax, 104(%rsp)
movq 480(%rsp), %rax
movq %rax, 96(%rsp)
movq 488(%rsp), %rax
movq %rax, 88(%rsp)
movq 528(%rsp), %rax
movq %rax, 72(%rsp)
movq 536(%rsp), %rax
movq %rax, 64(%rsp)
movq 544(%rsp), %rax
movq %rax, 56(%rsp)
movq 552(%rsp), %rax
movq %rax, 48(%rsp)
movq 560(%rsp), %rax
movq %rax, 40(%rsp)
movq 568(%rsp), %rax
movq %rax, 32(%rsp)
movq 576(%rsp), %rax
movq %rax, 24(%rsp)
movq 584(%rsp), %rax
movq %rax, 16(%rsp)
movq 592(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
leaq 152(%rsp), %rax
movq %rax, 224(%rsp)
leaq 144(%rsp), %rax
movq %rax, 232(%rsp)
leaq 136(%rsp), %rax
movq %rax, 240(%rsp)
leaq 132(%rsp), %rax
movq %rax, 248(%rsp)
leaq 128(%rsp), %rax
movq %rax, 256(%rsp)
leaq 120(%rsp), %rax
movq %rax, 264(%rsp)
leaq 112(%rsp), %rax
movq %rax, 272(%rsp)
leaq 104(%rsp), %rax
movq %rax, 280(%rsp)
leaq 96(%rsp), %rax
movq %rax, 288(%rsp)
leaq 88(%rsp), %rax
movq %rax, 296(%rsp)
leaq 496(%rsp), %rax
movq %rax, 304(%rsp)
leaq 504(%rsp), %rax
movq %rax, 312(%rsp)
leaq 512(%rsp), %rax
movq %rax, 320(%rsp)
leaq 520(%rsp), %rax
movq %rax, 328(%rsp)
leaq 84(%rsp), %rax
movq %rax, 336(%rsp)
leaq 72(%rsp), %rax
movq %rax, 344(%rsp)
leaq 64(%rsp), %rax
movq %rax, 352(%rsp)
leaq 56(%rsp), %rax
movq %rax, 360(%rsp)
leaq 48(%rsp), %rax
movq %rax, 368(%rsp)
leaq 40(%rsp), %rax
movq %rax, 376(%rsp)
leaq 32(%rsp), %rax
movq %rax, 384(%rsp)
leaq 24(%rsp), %rax
movq %rax, 392(%rsp)
leaq 16(%rsp), %rax
movq %rax, 400(%rsp)
leaq 8(%rsp), %rax
movq %rax, 408(%rsp)
leaq 80(%rsp), %rax
movq %rax, 416(%rsp)
leaq 600(%rsp), %rax
movq %rax, 424(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $1, 192(%rsp)
movl $1, 196(%rsp)
leaq 168(%rsp), %rcx
leaq 160(%rsp), %rdx
leaq 188(%rsp), %rsi
leaq 176(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $456, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 168(%rsp)
.cfi_def_cfa_offset 472
pushq 168(%rsp)
.cfi_def_cfa_offset 480
leaq 240(%rsp), %r9
movq 204(%rsp), %rcx
movl 212(%rsp), %r8d
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
leaq _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 464
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, .-_Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.globl _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.type _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, @function
_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 152(%rsp)
.cfi_def_cfa_offset 32
pushq 152(%rsp)
.cfi_def_cfa_offset 40
pushq 152(%rsp)
.cfi_def_cfa_offset 48
pushq 152(%rsp)
.cfi_def_cfa_offset 56
pushq 152(%rsp)
.cfi_def_cfa_offset 64
pushq 152(%rsp)
.cfi_def_cfa_offset 72
pushq 152(%rsp)
.cfi_def_cfa_offset 80
pushq 152(%rsp)
.cfi_def_cfa_offset 88
pushq 152(%rsp)
.cfi_def_cfa_offset 96
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
pushq 152(%rsp)
.cfi_def_cfa_offset 136
pushq 152(%rsp)
.cfi_def_cfa_offset 144
pushq 152(%rsp)
.cfi_def_cfa_offset 152
pushq 152(%rsp)
.cfi_def_cfa_offset 160
call _Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
addq $152, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, .-_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Fuente.bin"
.LC2:
.string "\nDatos de fuente cargados...\n"
.LC3:
.string "Modelo_ori.bin"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\nDatos de modelo original cargados...\n"
.section .rodata.str1.1
.LC10:
.string "Voy en el paso temporal %d \n"
.LC11:
.string "wb"
.LC12:
.string "Trazas.bin"
.LC13:
.string "Frentedeonda.bin"
.LC14:
.string "DerivadaFrentedeOnda.bin"
.LC15:
.string "\n Creo que Termine ....\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
call cudaDeviceReset@PLT
movl $4, %esi
movl $170000, %edi
call calloc@PLT
movq %rax, %r15
movl $4, %esi
movl $14910, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $1000, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $14910000, %edi
call calloc@PLT
movq %rax, %r14
movl $4, %esi
movl $14910000, %edi
call calloc@PLT
movq %rax, 8(%rsp)
leaq 40(%rsp), %rdi
movl $680000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $59640000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $59640000, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 144(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 152(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $59640, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $840, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $284, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $840, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $284, %esi
call cudaMalloc@PLT
movl $59640, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 112(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 128(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 136(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 144(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 152(%rsp), %rdi
call cudaMemset@PLT
movl $59640, %edx
movl $0, %esi
movq 120(%rsp), %rdi
call cudaMemset@PLT
movl $840, %edx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movl $284, %edx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movl $840, %edx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movl $284, %edx
movl $0, %esi
movq 104(%rsp), %rdi
call cudaMemset@PLT
leaq .LC0(%rip), %rbp
movq %rbp, %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %r8
movl $1, %ecx
movl $4000, %edx
movl $4000, %esi
movq %r13, %rdi
call __fread_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq %rbp, %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %r8
movl $1, %ecx
movl $59640, %edx
movl $59640, %esi
movq %r12, %rdi
call __fread_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movl $1, %ecx
movl $59640, %edx
movq %r12, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %r13, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $7, 160(%rsp)
movl $3, 164(%rsp)
movl $1, 168(%rsp)
movl $32, 172(%rsp)
movl $32, 176(%rsp)
movl $1, 180(%rsp)
movl $7, 184(%rsp)
movl $1, 188(%rsp)
movl $32, 196(%rsp)
movl $1, 200(%rsp)
movl $3, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $32, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L44:
movl 228(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 220(%rsp), %rdx
movq 208(%rsp), %rdi
movl 216(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L45:
movl $0, %ebx
jmp .L49
.L53:
movss .LC5(%rip), %xmm4
movss .LC6(%rip), %xmm3
movss .LC7(%rip), %xmm2
movl $210, %ecx
movss .LC8(%rip), %xmm1
movss .LC9(%rip), %xmm0
movl $20, %edx
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z39__device_stub__Z10get_CPML_xPfS_iffifffPfS_iffifff
jmp .L44
.L54:
movss .LC5(%rip), %xmm4
movss .LC6(%rip), %xmm3
movss .LC7(%rip), %xmm2
movl $71, %ecx
movss .LC8(%rip), %xmm1
movss .LC9(%rip), %xmm0
movl $20, %edx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z39__device_stub__Z10get_CPML_zPfS_iffifffPfS_iffifff
jmp .L45
.L56:
pushq $71
.cfi_def_cfa_offset 312
pushq $210
.cfi_def_cfa_offset 320
pushq $20
.cfi_def_cfa_offset 328
pushq 160(%rsp)
.cfi_def_cfa_offset 336
movss .LC6(%rip), %xmm0
movq 160(%rsp), %r9
movq 136(%rsp), %r8
movq 120(%rsp), %rcx
movq 128(%rsp), %rdx
movq 112(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z38__device_stub__Z3PSIPfS_S_S_S_S_S_iiifPfS_S_S_S_S_S_iiif
addq $32, %rsp
.cfi_def_cfa_offset 304
jmp .L46
.L57:
movss .LC6(%rip), %xmm0
movl $71, %ecx
movl $210, %edx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z35__device_stub__Z10kernel_lapPfS_iifPfS_iif
jmp .L47
.L48:
movq 24(%rsp), %rax
movq 32(%rsp), %rdx
movq %rdx, 24(%rsp)
movq %rax, 32(%rsp)
cmpl $1000, %ebx
je .L55
.L49:
movl %ebx, %ebp
addl $1, %ebx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 180(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movq 160(%rsp), %rdi
movl 168(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L46:
movl 180(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movq 160(%rsp), %rdi
movl 168(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L47:
movl 180(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 172(%rsp), %rdx
movq 160(%rsp), %rdi
movl 168(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
pushq $1
.cfi_def_cfa_offset 312
pushq 128(%rsp)
.cfi_def_cfa_offset 320
pushq 168(%rsp)
.cfi_def_cfa_offset 328
pushq 168(%rsp)
.cfi_def_cfa_offset 336
pushq 168(%rsp)
.cfi_def_cfa_offset 344
pushq 168(%rsp)
.cfi_def_cfa_offset 352
pushq 144(%rsp)
.cfi_def_cfa_offset 360
pushq 160(%rsp)
.cfi_def_cfa_offset 368
pushq 144(%rsp)
.cfi_def_cfa_offset 376
pushq 160(%rsp)
.cfi_def_cfa_offset 384
pushq $20
.cfi_def_cfa_offset 392
pushq $6
.cfi_def_cfa_offset 400
pushq $105
.cfi_def_cfa_offset 408
pushq %rbp
.cfi_def_cfa_offset 416
pushq 168(%rsp)
.cfi_def_cfa_offset 424
pushq 168(%rsp)
.cfi_def_cfa_offset 432
pushq 168(%rsp)
.cfi_def_cfa_offset 440
pushq 208(%rsp)
.cfi_def_cfa_offset 448
movss .LC6(%rip), %xmm1
movss .LC7(%rip), %xmm0
movq 208(%rsp), %r9
movl $71, %r8d
movl $210, %ecx
movq 176(%rsp), %rdx
movq 168(%rsp), %rsi
movq 256(%rsp), %rdi
call _Z75__device_stub__Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fiPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
addq $144, %rsp
.cfi_def_cfa_offset 304
jmp .L48
.L55:
movl $2, %ecx
movl $59640000, %edx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $680000, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC11(%rip), %rbp
movq %rbp, %rsi
leaq .LC12(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rcx
movl $170000, %edx
movl $4, %esi
movq %r15, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r15, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq .LC13(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rcx
movl $14910000, %edx
movl $4, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rsi
leaq .LC14(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rcx
movl $14910000, %edx
movl $4, %esi
movq 8(%rsp), %r14
movq %r14, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rdi
call cudaFree@PLT
movq 144(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rdi
call cudaFree@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi"
.section .rodata.str1.1
.LC17:
.string "_Z3PSIPfS_S_S_S_S_S_iiif"
.LC18:
.string "_Z10get_CPML_zPfS_iffifff"
.LC19:
.string "_Z10get_CPML_xPfS_iffifff"
.LC20:
.string "_Z10kernel_lapPfS_iif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z3PSIPfS_S_S_S_S_S_iiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10get_CPML_zPfS_iffifff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10get_CPML_xPfS_iffifff(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_lapPfS_iif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1077936128
.align 4
.LC6:
.long 1103626240
.align 4
.LC7:
.long 981668463
.align 4
.LC8:
.long 1167253504
.align 4
.LC9:
.long 953267991
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
#define PI 3.141592653589793
#define left ((ix-1) + Nx*iz) //Izquierda
#define top (ix + Nx*(iz-1)) //Arriba
#define center (ix + Nx*iz) //Centro
#define bottom (ix + Nx*(iz+1)) //Abajo
#define right ((ix+1) + Nx*iz) //Derecha
// A = Presente
// B = Pasado
// C = Futuro
//DEVICE CODE - Kernel1
__global__ void kernel_lap(float *lap, float *A, int nx, int ny, float dh){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< ny-4){
lap[tid] =((-1./560)*(A[ tid - 4 ] + A[tid + 4] + A[tid + 4*nx ] + A[tid -4*nx]) +
(8./315)*(A[ tid - 3 ] + A[tid + 3] + A[tid + 3*nx ] + A[tid -3*nx]) +
(-1./5)*(A[ tid - 2 ] + A[tid + 2] + A[tid + 2*nx ] + A[tid -2*nx]) +
(8./5)*(A[ tid - 1 ] + A[tid + 1] + A[tid + 1*nx ] + A[tid -1*nx]) +
(-205./36)*(A[tid]))/(dh*dh);
__syncthreads();
}
}
__global__
void get_CPML_x(float *a_x, float *b_x, int CPMLimit, float R, float VelMax, int Nx, float dt, float dh, float frec){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lx = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lx);
a_x[ix] = 0;
b_x[ix] = 0;
if (ix<CPMLimit+1) //Left CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx))*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx));
__syncthreads();
__syncthreads();
}
if (ix>(Nx-CPMLimit-1) && ix<Nx) //Right CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) )*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) );
__syncthreads();
__syncthreads();
}
}
__global__
void get_CPML_z(float *a_z, float *b_z, int CPMLimit, float R, float VelMax, int Nz, float dt, float dh, float frec){
//dh = dx; Notacion
int iz = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lz = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lz);
//Inicializando valores de CPML
a_z[iz] = 0;
b_z[iz] = 0;
if (iz>(Nz-CPMLimit-1) && iz<Nz) //bottom CPML
{
b_z[iz] = exp(-( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) )*dt);
__syncthreads();
a_z[iz] = (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) * ( b_z[iz] - 1 ) / ( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) );
__syncthreads();
}
}
__global__
void PSI(float *A, float *a_x, float *b_x, float *a_z, float *b_z, float *Psi_x, float *Psi_z, int CPMLimit, int Nx, int Nz, float dh){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Row of the A matrix
int iz = threadIdx.y + blockDim.y * blockIdx.y; // Column of the A matrix
int tid = ix + iz*Nx;
if(ix > 3 && ix < Nx-4 && iz > 3 && iz< Nz-4)
{
// Primera derivada de segundo orden centrada
/*
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (-1./2)*A[tid-1] + (1./2)*A[tid+1])/(2*dh);
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (-1./2)*A[tid-Nx] + (1./2)*A[tid+Nx])/(2*dh);
*/
// Primera derivada de octavo orden centrada
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (1./280.)*A[tid-4] - (4./105.)*A[tid-3] + (1./5.)*A[tid-2] - (4./5.)*A[tid-1] + (4./5.)*A[tid+1] + (-1./5.)*A[tid+2] + (4./105.)*A[tid+3] + (-1./280.)*A[tid+4] )/(dh);
__syncthreads();
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (1./280.)*A[tid-4*Nx] + (-4./105.)*A[tid-3*Nx] + (1./5.)*A[tid-2*Nx] + (-4./5.)*A[tid-1*Nx] + (4./5.)*A[tid+1*Nx] + (-1./5.)*A[tid+2*Nx] + (4./105.)*A[tid+3*Nx] + (-1./280.)*A[tid+4*Nx] )/(dh);
__syncthreads();
}
}
__global__
void kernel_propaga(float *lap, float *A, float *B, int nx, int nz, float *source, float *c, float *traza, float *P, float *dP, int it, int sx, int sz, int borde, float dt, float *a_z, float *a_x, float *b_z, float *b_x, float *Psi_x, float *Psi_z, float *Z_x, float *Z_z, float *temp, float dh, int modo){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
float G = c[tid]*c[tid]*dt*dt;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4){
// Calculo de las derivadas de psi
// Primera derivada de segundo orden central
//temp[tid]=((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/(2*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/(2*dh);
// Primera derivada octavo orden central
temp[tid]=( (1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1]
+ (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh)
+ ( (1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx]
+ (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh);
__syncthreads();
// Calculo de los zetas
// Derivadas de segundo orden
// Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( (A[tid+1] -2*A[tid] + A[tid-1])/(dh*dh) + ((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/dh);
// Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( (A[tid-nx] -2*A[tid] + A[tid+nx])/(dh*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/dh);
// Derivadas de octavo orden
Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( ( (-1./560)*A[tid-4] + (8./315)*A[tid-3] + (-1./5)*A[tid-2] + (8./5)*A[tid-1] + (-205./72)*A[tid] + (8./5)*A[tid+1] + (-1./5)*A[tid+2] + (8./315)*A[tid+3] + (-1./560)*A[tid+4] )/(dh*dh) + ((1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1] + (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh*dh));
__syncthreads();
Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( ( (-1./560)*A[tid-4*nx] + (8./315)*A[tid-3*nx] + (-1./5)*A[tid-2*nx] + (8./5)*A[tid-1*nx] + (-205./72)*A[tid] + (8./5)*A[tid+1*nx] + (-1./5)*A[tid+2*nx] + (8./315)*A[tid+3*nx] + (-1./560)*A[tid+4*nx] )/(dh*dh) + ((1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx] + (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh*dh));
__syncthreads();
}
//if(ix<nx-1 && iy<nz-1){
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4 ){
B[tid]=2*A[tid] - B[tid] + G*( lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix < nx && iy< nz){
// if(it<Nt){
if(ix==(sx-1+4) && iy==(sz-1+4)){
A[tid] = A[tid] + source[it];
__syncthreads();
}
// }
if(modo==1 || modo==3 ){
P[tid+nx*nz*it]=B[tid];
__syncthreads();
}
if(modo==2 || modo==3 ){
dP[tid+nx*nz*it]=c[tid]*c[tid]*(lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix>=borde && ix< nx-borde && iy==sz-1+4){
traza[(ix-borde)+it*(nx-2*borde)]=B[tid];
__syncthreads();
}
}
__syncthreads();
}
// A = Presente
// B = Pasado
// C = Futuro
//HOST CODE
int main(){
cudaDeviceReset();
//variables host
int borde=20;
int nx=210;
int ny=71;
int modo=1;
int it;
int nt;
int sx = ceil(nx/2);
int sz = 6;
float VelMax=4700;
float R=100e-6;
float frec=3;
float tend=1.0;
float dt=0.001;
float dh=25;
float *A_d, *B_d, *Pt_d, *Pt_h, *P_d, *P_h, *dP_d, *dP_h, *s_h, *s_d, *v_d, *v_h, *A_x, *A_z, *B_x, *B_z, *lap, *temp, *temp1, *Psi_x, *Psi_z, *Z_x, *Z_z;
FILE *source, *model_ori;
nt= ceil(tend/dt);
Pt_h = (float *)calloc((nx-2*borde)*nt,sizeof(float));
v_h = (float *)calloc(nx*ny,sizeof(float));
s_h = (float *)calloc(nt,sizeof(float));
P_h = (float *)calloc(nx*ny*nt,sizeof(float));
dP_h = (float *)calloc(nx*ny*nt,sizeof(float));
//variables y memory allocation en device
cudaMalloc(&Pt_d,(nx-2*borde)*nt*sizeof(float));
cudaMalloc(&A_d, nx*ny*sizeof(float));
cudaMalloc(&B_d, nx*ny*sizeof(float));
cudaMalloc(&P_d, nx*ny*nt*sizeof(float));
cudaMalloc(&dP_d, nx*ny*nt*sizeof(float));
cudaMalloc(&s_d, nt*sizeof(float));
cudaMalloc(&v_d, nx*ny*sizeof(float));
cudaMalloc(&lap, nx*ny*sizeof(float));
cudaMalloc(&Psi_x, nx*ny*sizeof(float));
cudaMalloc(&Psi_z, nx*ny*sizeof(float));
cudaMalloc(&Z_x, nx*ny*sizeof(float));
cudaMalloc(&Z_z, nx*ny*sizeof(float));
cudaMalloc(&temp1, nx*ny*sizeof(float));
cudaMalloc(&A_x, nx*sizeof(float));
cudaMalloc(&A_z, ny*sizeof(float));
cudaMalloc(&B_x, nx*sizeof(float));
cudaMalloc(&B_z, ny*sizeof(float));
cudaMemset(A_d,0,nx*ny*sizeof(float));
cudaMemset(B_d,0,nx*ny*sizeof(float));
cudaMemset(lap,0,nx*ny*sizeof(float));
cudaMemset(Psi_x,0,nx*ny*sizeof(float));
cudaMemset(Psi_z,0,nx*ny*sizeof(float));
cudaMemset(Z_x,0,nx*ny*sizeof(float));
cudaMemset(Z_z,0,nx*ny*sizeof(float));
cudaMemset(temp1,0,nx*ny*sizeof(float));
cudaMemset(A_x,0,nx*sizeof(float));
cudaMemset(A_z,0,ny*sizeof(float));
cudaMemset(B_x,0,nx*sizeof(float));
cudaMemset(B_z,0,ny*sizeof(float));
//Leer y condicionar archivos fuente
source = fopen ("Fuente.bin","rb");
fread(s_h,nt*sizeof(float),1,source);
printf("\nDatos de fuente cargados...\n");
fclose(source);
//Leer y condicionar archivos modelo original
model_ori = fopen ("Modelo_ori.bin","rb");
fread(v_h,nx*ny*sizeof(float),1,model_ori);
printf("\nDatos de modelo original cargados...\n");
fclose(model_ori);
//Enviando informacion necesaria a la GPU
cudaMemcpy(v_d, v_h, nx*ny*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(s_d, s_h, nt*sizeof(float), cudaMemcpyHostToDevice);
//ejecución Kernel
dim3 dimGrid_M(ceil((nx) / (float)TILE_WIDTH_X) , ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_M(TILE_WIDTH_X , TILE_WIDTH_Y);
dim3 dimGrid_Vx(ceil((nx) / (float)TILE_WIDTH_X));
dim3 dimBlock_Vx(TILE_WIDTH_X);
dim3 dimGrid_Vz(ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_Vz(TILE_WIDTH_Y);
get_CPML_x<<<dimGrid_Vx, dimBlock_Vx>>>(A_x, B_x, borde, R, VelMax, nx, dt, dh, frec);
get_CPML_z<<<dimGrid_Vz, dimBlock_Vz>>>(A_z, B_z, borde, R, VelMax, ny, dt, dh, frec);
for (it=0;it<nt;it++){
printf("Voy en el paso temporal %d \n",it+1);
PSI<<<dimGrid_M, dimBlock_M>>>(A_d, A_x, B_x, A_z, B_z, Psi_x, Psi_z, borde, nx, ny, dh);
kernel_lap<<<dimGrid_M, dimBlock_M>>>(lap,A_d,nx,ny,dh); //#blocks=dimGrid, #threads=dimBlock
kernel_propaga<<<dimGrid_M, dimBlock_M>>>(lap,A_d,B_d,nx,ny,s_d,v_d,Pt_d,P_d,dP_d,it,sx,sz,borde,dt,A_z,A_x,B_z,B_x,Psi_x,Psi_z,Z_x,Z_z,temp1,dh,modo); //#blocks=dimGrid,
temp = A_d;
A_d = B_d;
B_d = temp;
}
if(modo==1 || modo==3){
cudaMemcpy(P_h, P_d, nx*ny*nt*sizeof(float), cudaMemcpyDeviceToHost);
}
if(modo==2 || modo==3){
cudaMemcpy(dP_h, dP_d, nx*ny*nt*sizeof(float), cudaMemcpyDeviceToHost);
}
cudaMemcpy(Pt_h, Pt_d, (nx-2*borde)*nt*sizeof(float), cudaMemcpyDeviceToHost);
//---------------------------------------
// Guarda informacion -----------------------
// Trazas
source=fopen("Trazas.bin","wb");
fwrite(Pt_h,sizeof(float),(nx-2*borde)*nt,source);
fclose(source);
free(Pt_h);
cudaFree(Pt_d);
// Frente de Onda
source=fopen("Frentedeonda.bin","wb");
fwrite(P_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(P_h);
cudaFree(P_d);
// Derivad Frente de Onda
source=fopen("DerivadaFrentedeOnda.bin","wb");
fwrite(dP_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(dP_h);
cudaFree(dP_d);
// Liberamos resto de punteros
// Host
free(s_h);
free(v_h);
// Device
cudaFree(A_d);
cudaFree(B_d);
cudaFree(lap);
cudaFree(s_d);
cudaFree(v_d);
cudaFree(A_x);
cudaFree(A_z);
cudaFree(B_x);
cudaFree(B_z);
cudaFree(Psi_x);
cudaFree(Psi_z);
cudaFree(Z_x);
cudaFree(Z_z);
printf("\n Creo que Termine ....\n");
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
#define PI 3.141592653589793
#define left ((ix-1) + Nx*iz) //Izquierda
#define top (ix + Nx*(iz-1)) //Arriba
#define center (ix + Nx*iz) //Centro
#define bottom (ix + Nx*(iz+1)) //Abajo
#define right ((ix+1) + Nx*iz) //Derecha
// A = Presente
// B = Pasado
// C = Futuro
//DEVICE CODE - Kernel1
__global__ void kernel_lap(float *lap, float *A, int nx, int ny, float dh){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< ny-4){
lap[tid] =((-1./560)*(A[ tid - 4 ] + A[tid + 4] + A[tid + 4*nx ] + A[tid -4*nx]) +
(8./315)*(A[ tid - 3 ] + A[tid + 3] + A[tid + 3*nx ] + A[tid -3*nx]) +
(-1./5)*(A[ tid - 2 ] + A[tid + 2] + A[tid + 2*nx ] + A[tid -2*nx]) +
(8./5)*(A[ tid - 1 ] + A[tid + 1] + A[tid + 1*nx ] + A[tid -1*nx]) +
(-205./36)*(A[tid]))/(dh*dh);
__syncthreads();
}
}
__global__
void get_CPML_x(float *a_x, float *b_x, int CPMLimit, float R, float VelMax, int Nx, float dt, float dh, float frec){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lx = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lx);
a_x[ix] = 0;
b_x[ix] = 0;
if (ix<CPMLimit+1) //Left CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx))*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx));
__syncthreads();
__syncthreads();
}
if (ix>(Nx-CPMLimit-1) && ix<Nx) //Right CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) )*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) );
__syncthreads();
__syncthreads();
}
}
__global__
void get_CPML_z(float *a_z, float *b_z, int CPMLimit, float R, float VelMax, int Nz, float dt, float dh, float frec){
//dh = dx; Notacion
int iz = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lz = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lz);
//Inicializando valores de CPML
a_z[iz] = 0;
b_z[iz] = 0;
if (iz>(Nz-CPMLimit-1) && iz<Nz) //bottom CPML
{
b_z[iz] = exp(-( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) )*dt);
__syncthreads();
a_z[iz] = (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) * ( b_z[iz] - 1 ) / ( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) );
__syncthreads();
}
}
__global__
void PSI(float *A, float *a_x, float *b_x, float *a_z, float *b_z, float *Psi_x, float *Psi_z, int CPMLimit, int Nx, int Nz, float dh){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Row of the A matrix
int iz = threadIdx.y + blockDim.y * blockIdx.y; // Column of the A matrix
int tid = ix + iz*Nx;
if(ix > 3 && ix < Nx-4 && iz > 3 && iz< Nz-4)
{
// Primera derivada de segundo orden centrada
/*
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (-1./2)*A[tid-1] + (1./2)*A[tid+1])/(2*dh);
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (-1./2)*A[tid-Nx] + (1./2)*A[tid+Nx])/(2*dh);
*/
// Primera derivada de octavo orden centrada
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (1./280.)*A[tid-4] - (4./105.)*A[tid-3] + (1./5.)*A[tid-2] - (4./5.)*A[tid-1] + (4./5.)*A[tid+1] + (-1./5.)*A[tid+2] + (4./105.)*A[tid+3] + (-1./280.)*A[tid+4] )/(dh);
__syncthreads();
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (1./280.)*A[tid-4*Nx] + (-4./105.)*A[tid-3*Nx] + (1./5.)*A[tid-2*Nx] + (-4./5.)*A[tid-1*Nx] + (4./5.)*A[tid+1*Nx] + (-1./5.)*A[tid+2*Nx] + (4./105.)*A[tid+3*Nx] + (-1./280.)*A[tid+4*Nx] )/(dh);
__syncthreads();
}
}
__global__
void kernel_propaga(float *lap, float *A, float *B, int nx, int nz, float *source, float *c, float *traza, float *P, float *dP, int it, int sx, int sz, int borde, float dt, float *a_z, float *a_x, float *b_z, float *b_x, float *Psi_x, float *Psi_z, float *Z_x, float *Z_z, float *temp, float dh, int modo){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
float G = c[tid]*c[tid]*dt*dt;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4){
// Calculo de las derivadas de psi
// Primera derivada de segundo orden central
//temp[tid]=((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/(2*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/(2*dh);
// Primera derivada octavo orden central
temp[tid]=( (1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1]
+ (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh)
+ ( (1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx]
+ (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh);
__syncthreads();
// Calculo de los zetas
// Derivadas de segundo orden
// Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( (A[tid+1] -2*A[tid] + A[tid-1])/(dh*dh) + ((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/dh);
// Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( (A[tid-nx] -2*A[tid] + A[tid+nx])/(dh*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/dh);
// Derivadas de octavo orden
Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( ( (-1./560)*A[tid-4] + (8./315)*A[tid-3] + (-1./5)*A[tid-2] + (8./5)*A[tid-1] + (-205./72)*A[tid] + (8./5)*A[tid+1] + (-1./5)*A[tid+2] + (8./315)*A[tid+3] + (-1./560)*A[tid+4] )/(dh*dh) + ((1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1] + (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh*dh));
__syncthreads();
Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( ( (-1./560)*A[tid-4*nx] + (8./315)*A[tid-3*nx] + (-1./5)*A[tid-2*nx] + (8./5)*A[tid-1*nx] + (-205./72)*A[tid] + (8./5)*A[tid+1*nx] + (-1./5)*A[tid+2*nx] + (8./315)*A[tid+3*nx] + (-1./560)*A[tid+4*nx] )/(dh*dh) + ((1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx] + (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh*dh));
__syncthreads();
}
//if(ix<nx-1 && iy<nz-1){
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4 ){
B[tid]=2*A[tid] - B[tid] + G*( lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix < nx && iy< nz){
// if(it<Nt){
if(ix==(sx-1+4) && iy==(sz-1+4)){
A[tid] = A[tid] + source[it];
__syncthreads();
}
// }
if(modo==1 || modo==3 ){
P[tid+nx*nz*it]=B[tid];
__syncthreads();
}
if(modo==2 || modo==3 ){
dP[tid+nx*nz*it]=c[tid]*c[tid]*(lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix>=borde && ix< nx-borde && iy==sz-1+4){
traza[(ix-borde)+it*(nx-2*borde)]=B[tid];
__syncthreads();
}
}
__syncthreads();
}
// A = Presente
// B = Pasado
// C = Futuro
//HOST CODE
int main(){
hipDeviceReset();
//variables host
int borde=20;
int nx=210;
int ny=71;
int modo=1;
int it;
int nt;
int sx = ceil(nx/2);
int sz = 6;
float VelMax=4700;
float R=100e-6;
float frec=3;
float tend=1.0;
float dt=0.001;
float dh=25;
float *A_d, *B_d, *Pt_d, *Pt_h, *P_d, *P_h, *dP_d, *dP_h, *s_h, *s_d, *v_d, *v_h, *A_x, *A_z, *B_x, *B_z, *lap, *temp, *temp1, *Psi_x, *Psi_z, *Z_x, *Z_z;
FILE *source, *model_ori;
nt= ceil(tend/dt);
Pt_h = (float *)calloc((nx-2*borde)*nt,sizeof(float));
v_h = (float *)calloc(nx*ny,sizeof(float));
s_h = (float *)calloc(nt,sizeof(float));
P_h = (float *)calloc(nx*ny*nt,sizeof(float));
dP_h = (float *)calloc(nx*ny*nt,sizeof(float));
//variables y memory allocation en device
hipMalloc(&Pt_d,(nx-2*borde)*nt*sizeof(float));
hipMalloc(&A_d, nx*ny*sizeof(float));
hipMalloc(&B_d, nx*ny*sizeof(float));
hipMalloc(&P_d, nx*ny*nt*sizeof(float));
hipMalloc(&dP_d, nx*ny*nt*sizeof(float));
hipMalloc(&s_d, nt*sizeof(float));
hipMalloc(&v_d, nx*ny*sizeof(float));
hipMalloc(&lap, nx*ny*sizeof(float));
hipMalloc(&Psi_x, nx*ny*sizeof(float));
hipMalloc(&Psi_z, nx*ny*sizeof(float));
hipMalloc(&Z_x, nx*ny*sizeof(float));
hipMalloc(&Z_z, nx*ny*sizeof(float));
hipMalloc(&temp1, nx*ny*sizeof(float));
hipMalloc(&A_x, nx*sizeof(float));
hipMalloc(&A_z, ny*sizeof(float));
hipMalloc(&B_x, nx*sizeof(float));
hipMalloc(&B_z, ny*sizeof(float));
hipMemset(A_d,0,nx*ny*sizeof(float));
hipMemset(B_d,0,nx*ny*sizeof(float));
hipMemset(lap,0,nx*ny*sizeof(float));
hipMemset(Psi_x,0,nx*ny*sizeof(float));
hipMemset(Psi_z,0,nx*ny*sizeof(float));
hipMemset(Z_x,0,nx*ny*sizeof(float));
hipMemset(Z_z,0,nx*ny*sizeof(float));
hipMemset(temp1,0,nx*ny*sizeof(float));
hipMemset(A_x,0,nx*sizeof(float));
hipMemset(A_z,0,ny*sizeof(float));
hipMemset(B_x,0,nx*sizeof(float));
hipMemset(B_z,0,ny*sizeof(float));
//Leer y condicionar archivos fuente
source = fopen ("Fuente.bin","rb");
fread(s_h,nt*sizeof(float),1,source);
printf("\nDatos de fuente cargados...\n");
fclose(source);
//Leer y condicionar archivos modelo original
model_ori = fopen ("Modelo_ori.bin","rb");
fread(v_h,nx*ny*sizeof(float),1,model_ori);
printf("\nDatos de modelo original cargados...\n");
fclose(model_ori);
//Enviando informacion necesaria a la GPU
hipMemcpy(v_d, v_h, nx*ny*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(s_d, s_h, nt*sizeof(float), hipMemcpyHostToDevice);
//ejecución Kernel
dim3 dimGrid_M(ceil((nx) / (float)TILE_WIDTH_X) , ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_M(TILE_WIDTH_X , TILE_WIDTH_Y);
dim3 dimGrid_Vx(ceil((nx) / (float)TILE_WIDTH_X));
dim3 dimBlock_Vx(TILE_WIDTH_X);
dim3 dimGrid_Vz(ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_Vz(TILE_WIDTH_Y);
get_CPML_x<<<dimGrid_Vx, dimBlock_Vx>>>(A_x, B_x, borde, R, VelMax, nx, dt, dh, frec);
get_CPML_z<<<dimGrid_Vz, dimBlock_Vz>>>(A_z, B_z, borde, R, VelMax, ny, dt, dh, frec);
for (it=0;it<nt;it++){
printf("Voy en el paso temporal %d \n",it+1);
PSI<<<dimGrid_M, dimBlock_M>>>(A_d, A_x, B_x, A_z, B_z, Psi_x, Psi_z, borde, nx, ny, dh);
kernel_lap<<<dimGrid_M, dimBlock_M>>>(lap,A_d,nx,ny,dh); //#blocks=dimGrid, #threads=dimBlock
kernel_propaga<<<dimGrid_M, dimBlock_M>>>(lap,A_d,B_d,nx,ny,s_d,v_d,Pt_d,P_d,dP_d,it,sx,sz,borde,dt,A_z,A_x,B_z,B_x,Psi_x,Psi_z,Z_x,Z_z,temp1,dh,modo); //#blocks=dimGrid,
temp = A_d;
A_d = B_d;
B_d = temp;
}
if(modo==1 || modo==3){
hipMemcpy(P_h, P_d, nx*ny*nt*sizeof(float), hipMemcpyDeviceToHost);
}
if(modo==2 || modo==3){
hipMemcpy(dP_h, dP_d, nx*ny*nt*sizeof(float), hipMemcpyDeviceToHost);
}
hipMemcpy(Pt_h, Pt_d, (nx-2*borde)*nt*sizeof(float), hipMemcpyDeviceToHost);
//---------------------------------------
// Guarda informacion -----------------------
// Trazas
source=fopen("Trazas.bin","wb");
fwrite(Pt_h,sizeof(float),(nx-2*borde)*nt,source);
fclose(source);
free(Pt_h);
hipFree(Pt_d);
// Frente de Onda
source=fopen("Frentedeonda.bin","wb");
fwrite(P_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(P_h);
hipFree(P_d);
// Derivad Frente de Onda
source=fopen("DerivadaFrentedeOnda.bin","wb");
fwrite(dP_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(dP_h);
hipFree(dP_d);
// Liberamos resto de punteros
// Host
free(s_h);
free(v_h);
// Device
hipFree(A_d);
hipFree(B_d);
hipFree(lap);
hipFree(s_d);
hipFree(v_d);
hipFree(A_x);
hipFree(A_z);
hipFree(B_x);
hipFree(B_z);
hipFree(Psi_x);
hipFree(Psi_z);
hipFree(Z_x);
hipFree(Z_z);
printf("\n Creo que Termine ....\n");
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h> //manipulacion de ficheros, lectura-escritura ficheros, scandf-printf
#include <stdlib.h> //Conversion de tipos de datos, memoria dinamica, abs
#include <string.h> //Uso de memcpy principalmente
#include <math.h> //funciones matemáticas
#define TILE_WIDTH_X 32
#define TILE_WIDTH_Y 32
#define PI 3.141592653589793
#define left ((ix-1) + Nx*iz) //Izquierda
#define top (ix + Nx*(iz-1)) //Arriba
#define center (ix + Nx*iz) //Centro
#define bottom (ix + Nx*(iz+1)) //Abajo
#define right ((ix+1) + Nx*iz) //Derecha
// A = Presente
// B = Pasado
// C = Futuro
//DEVICE CODE - Kernel1
__global__ void kernel_lap(float *lap, float *A, int nx, int ny, float dh){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< ny-4){
lap[tid] =((-1./560)*(A[ tid - 4 ] + A[tid + 4] + A[tid + 4*nx ] + A[tid -4*nx]) +
(8./315)*(A[ tid - 3 ] + A[tid + 3] + A[tid + 3*nx ] + A[tid -3*nx]) +
(-1./5)*(A[ tid - 2 ] + A[tid + 2] + A[tid + 2*nx ] + A[tid -2*nx]) +
(8./5)*(A[ tid - 1 ] + A[tid + 1] + A[tid + 1*nx ] + A[tid -1*nx]) +
(-205./36)*(A[tid]))/(dh*dh);
__syncthreads();
}
}
__global__
void get_CPML_x(float *a_x, float *b_x, int CPMLimit, float R, float VelMax, int Nx, float dt, float dh, float frec){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lx = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lx);
a_x[ix] = 0;
b_x[ix] = 0;
if (ix<CPMLimit+1) //Left CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx))*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((CPMLimit-ix)*dh)/Lx) * (((CPMLimit-ix)*dh)/Lx)) + (PI * frec * (Lx - ((CPMLimit-ix)*dh))/Lx));
__syncthreads();
__syncthreads();
}
if (ix>(Nx-CPMLimit-1) && ix<Nx) //Right CPML
{
b_x[ix] = exp(-( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) )*dt);
__syncthreads();
a_x[ix] = (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) * ( b_x[ix] - 1 ) / ( (d0 * VelMax * (((ix-Nx+CPMLimit+1)*dh)/Lx) * (((ix-Nx+CPMLimit+1)*dh)/Lx)) + (PI * frec * (Lx - ((ix-Nx+CPMLimit+1)*dh))/Lx) );
__syncthreads();
__syncthreads();
}
}
__global__
void get_CPML_z(float *a_z, float *b_z, int CPMLimit, float R, float VelMax, int Nz, float dt, float dh, float frec){
//dh = dx; Notacion
int iz = threadIdx.x + blockDim.x * blockIdx.x; // Indice vector
float Lz = CPMLimit*dh;
float d0 = -3*log(R)/(2*Lz);
//Inicializando valores de CPML
a_z[iz] = 0;
b_z[iz] = 0;
if (iz>(Nz-CPMLimit-1) && iz<Nz) //bottom CPML
{
b_z[iz] = exp(-( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) )*dt);
__syncthreads();
a_z[iz] = (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) * ( b_z[iz] - 1 ) / ( (d0 * VelMax * (((iz-Nz+CPMLimit+1)*dh)/Lz) * (((iz-Nz+CPMLimit+1)*dh)/Lz)) + (PI * frec * (Lz - ((iz-Nz+CPMLimit+1)*dh))/Lz) );
__syncthreads();
}
}
__global__
void PSI(float *A, float *a_x, float *b_x, float *a_z, float *b_z, float *Psi_x, float *Psi_z, int CPMLimit, int Nx, int Nz, float dh){
int ix = threadIdx.x + blockDim.x * blockIdx.x; // Row of the A matrix
int iz = threadIdx.y + blockDim.y * blockIdx.y; // Column of the A matrix
int tid = ix + iz*Nx;
if(ix > 3 && ix < Nx-4 && iz > 3 && iz< Nz-4)
{
// Primera derivada de segundo orden centrada
/*
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (-1./2)*A[tid-1] + (1./2)*A[tid+1])/(2*dh);
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (-1./2)*A[tid-Nx] + (1./2)*A[tid+Nx])/(2*dh);
*/
// Primera derivada de octavo orden centrada
Psi_x[tid] = Psi_x[tid]*b_x[ix] + a_x[ix]*( (1./280.)*A[tid-4] - (4./105.)*A[tid-3] + (1./5.)*A[tid-2] - (4./5.)*A[tid-1] + (4./5.)*A[tid+1] + (-1./5.)*A[tid+2] + (4./105.)*A[tid+3] + (-1./280.)*A[tid+4] )/(dh);
__syncthreads();
Psi_z[tid] = Psi_z[tid]*b_z[iz] + a_z[iz]*( (1./280.)*A[tid-4*Nx] + (-4./105.)*A[tid-3*Nx] + (1./5.)*A[tid-2*Nx] + (-4./5.)*A[tid-1*Nx] + (4./5.)*A[tid+1*Nx] + (-1./5.)*A[tid+2*Nx] + (4./105.)*A[tid+3*Nx] + (-1./280.)*A[tid+4*Nx] )/(dh);
__syncthreads();
}
}
__global__
void kernel_propaga(float *lap, float *A, float *B, int nx, int nz, float *source, float *c, float *traza, float *P, float *dP, int it, int sx, int sz, int borde, float dt, float *a_z, float *a_x, float *b_z, float *b_x, float *Psi_x, float *Psi_z, float *Z_x, float *Z_z, float *temp, float dh, int modo){
int ix=threadIdx.x + blockIdx.x*blockDim.x;
int iy=threadIdx.y + blockIdx.y*blockDim.y;
int tid = ix + iy*nx;
float G = c[tid]*c[tid]*dt*dt;
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4){
// Calculo de las derivadas de psi
// Primera derivada de segundo orden central
//temp[tid]=((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/(2*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/(2*dh);
// Primera derivada octavo orden central
temp[tid]=( (1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1]
+ (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh)
+ ( (1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx]
+ (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh);
__syncthreads();
// Calculo de los zetas
// Derivadas de segundo orden
// Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( (A[tid+1] -2*A[tid] + A[tid-1])/(dh*dh) + ((-1./2)*Psi_x[tid-1] + (1./2)*Psi_x[tid+1])/dh);
// Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( (A[tid-nx] -2*A[tid] + A[tid+nx])/(dh*dh) + ((-1./2)*Psi_z[tid-nx] + (1./2)*Psi_z[tid+nx])/dh);
// Derivadas de octavo orden
Z_x[tid]=b_x[ix]*Z_x[tid] + a_x[ix]*( ( (-1./560)*A[tid-4] + (8./315)*A[tid-3] + (-1./5)*A[tid-2] + (8./5)*A[tid-1] + (-205./72)*A[tid] + (8./5)*A[tid+1] + (-1./5)*A[tid+2] + (8./315)*A[tid+3] + (-1./560)*A[tid+4] )/(dh*dh) + ((1./280)*Psi_x[tid-4] + (-4./105)*Psi_x[tid-3] + (1./5)*Psi_x[tid-2] + (-4./5)*Psi_x[tid-1] + (4./5)*Psi_x[tid+1] + (-1./5)*Psi_x[tid+2] + (4./105)*Psi_x[tid+3] + (-1./280)*Psi_x[tid+4] )/(dh*dh));
__syncthreads();
Z_z[tid]=b_z[iy]*Z_z[tid] + a_z[iy]*( ( (-1./560)*A[tid-4*nx] + (8./315)*A[tid-3*nx] + (-1./5)*A[tid-2*nx] + (8./5)*A[tid-1*nx] + (-205./72)*A[tid] + (8./5)*A[tid+1*nx] + (-1./5)*A[tid+2*nx] + (8./315)*A[tid+3*nx] + (-1./560)*A[tid+4*nx] )/(dh*dh) + ((1./280)*Psi_z[tid-4*nx] + (-4./105)*Psi_z[tid-3*nx] + (1./5)*Psi_z[tid-2*nx] + (-4./5)*Psi_z[tid-1*nx] + (4./5)*Psi_z[tid+1*nx] + (-1./5)*Psi_z[tid+2*nx] + (4./105)*Psi_z[tid+3*nx] + (-1./280)*Psi_z[tid+4*nx] )/(dh*dh));
__syncthreads();
}
//if(ix<nx-1 && iy<nz-1){
if(ix > 3 && ix < nx-4 && iy > 3 && iy< nz-4 ){
B[tid]=2*A[tid] - B[tid] + G*( lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix < nx && iy< nz){
// if(it<Nt){
if(ix==(sx-1+4) && iy==(sz-1+4)){
A[tid] = A[tid] + source[it];
__syncthreads();
}
// }
if(modo==1 || modo==3 ){
P[tid+nx*nz*it]=B[tid];
__syncthreads();
}
if(modo==2 || modo==3 ){
dP[tid+nx*nz*it]=c[tid]*c[tid]*(lap[tid] + Z_x[tid] + Z_z[tid] + temp[tid]);
__syncthreads();
}
if(ix>=borde && ix< nx-borde && iy==sz-1+4){
traza[(ix-borde)+it*(nx-2*borde)]=B[tid];
__syncthreads();
}
}
__syncthreads();
}
// A = Presente
// B = Pasado
// C = Futuro
//HOST CODE
int main(){
hipDeviceReset();
//variables host
int borde=20;
int nx=210;
int ny=71;
int modo=1;
int it;
int nt;
int sx = ceil(nx/2);
int sz = 6;
float VelMax=4700;
float R=100e-6;
float frec=3;
float tend=1.0;
float dt=0.001;
float dh=25;
float *A_d, *B_d, *Pt_d, *Pt_h, *P_d, *P_h, *dP_d, *dP_h, *s_h, *s_d, *v_d, *v_h, *A_x, *A_z, *B_x, *B_z, *lap, *temp, *temp1, *Psi_x, *Psi_z, *Z_x, *Z_z;
FILE *source, *model_ori;
nt= ceil(tend/dt);
Pt_h = (float *)calloc((nx-2*borde)*nt,sizeof(float));
v_h = (float *)calloc(nx*ny,sizeof(float));
s_h = (float *)calloc(nt,sizeof(float));
P_h = (float *)calloc(nx*ny*nt,sizeof(float));
dP_h = (float *)calloc(nx*ny*nt,sizeof(float));
//variables y memory allocation en device
hipMalloc(&Pt_d,(nx-2*borde)*nt*sizeof(float));
hipMalloc(&A_d, nx*ny*sizeof(float));
hipMalloc(&B_d, nx*ny*sizeof(float));
hipMalloc(&P_d, nx*ny*nt*sizeof(float));
hipMalloc(&dP_d, nx*ny*nt*sizeof(float));
hipMalloc(&s_d, nt*sizeof(float));
hipMalloc(&v_d, nx*ny*sizeof(float));
hipMalloc(&lap, nx*ny*sizeof(float));
hipMalloc(&Psi_x, nx*ny*sizeof(float));
hipMalloc(&Psi_z, nx*ny*sizeof(float));
hipMalloc(&Z_x, nx*ny*sizeof(float));
hipMalloc(&Z_z, nx*ny*sizeof(float));
hipMalloc(&temp1, nx*ny*sizeof(float));
hipMalloc(&A_x, nx*sizeof(float));
hipMalloc(&A_z, ny*sizeof(float));
hipMalloc(&B_x, nx*sizeof(float));
hipMalloc(&B_z, ny*sizeof(float));
hipMemset(A_d,0,nx*ny*sizeof(float));
hipMemset(B_d,0,nx*ny*sizeof(float));
hipMemset(lap,0,nx*ny*sizeof(float));
hipMemset(Psi_x,0,nx*ny*sizeof(float));
hipMemset(Psi_z,0,nx*ny*sizeof(float));
hipMemset(Z_x,0,nx*ny*sizeof(float));
hipMemset(Z_z,0,nx*ny*sizeof(float));
hipMemset(temp1,0,nx*ny*sizeof(float));
hipMemset(A_x,0,nx*sizeof(float));
hipMemset(A_z,0,ny*sizeof(float));
hipMemset(B_x,0,nx*sizeof(float));
hipMemset(B_z,0,ny*sizeof(float));
//Leer y condicionar archivos fuente
source = fopen ("Fuente.bin","rb");
fread(s_h,nt*sizeof(float),1,source);
printf("\nDatos de fuente cargados...\n");
fclose(source);
//Leer y condicionar archivos modelo original
model_ori = fopen ("Modelo_ori.bin","rb");
fread(v_h,nx*ny*sizeof(float),1,model_ori);
printf("\nDatos de modelo original cargados...\n");
fclose(model_ori);
//Enviando informacion necesaria a la GPU
hipMemcpy(v_d, v_h, nx*ny*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(s_d, s_h, nt*sizeof(float), hipMemcpyHostToDevice);
//ejecución Kernel
dim3 dimGrid_M(ceil((nx) / (float)TILE_WIDTH_X) , ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_M(TILE_WIDTH_X , TILE_WIDTH_Y);
dim3 dimGrid_Vx(ceil((nx) / (float)TILE_WIDTH_X));
dim3 dimBlock_Vx(TILE_WIDTH_X);
dim3 dimGrid_Vz(ceil((ny) / (float)TILE_WIDTH_Y));
dim3 dimBlock_Vz(TILE_WIDTH_Y);
get_CPML_x<<<dimGrid_Vx, dimBlock_Vx>>>(A_x, B_x, borde, R, VelMax, nx, dt, dh, frec);
get_CPML_z<<<dimGrid_Vz, dimBlock_Vz>>>(A_z, B_z, borde, R, VelMax, ny, dt, dh, frec);
for (it=0;it<nt;it++){
printf("Voy en el paso temporal %d \n",it+1);
PSI<<<dimGrid_M, dimBlock_M>>>(A_d, A_x, B_x, A_z, B_z, Psi_x, Psi_z, borde, nx, ny, dh);
kernel_lap<<<dimGrid_M, dimBlock_M>>>(lap,A_d,nx,ny,dh); //#blocks=dimGrid, #threads=dimBlock
kernel_propaga<<<dimGrid_M, dimBlock_M>>>(lap,A_d,B_d,nx,ny,s_d,v_d,Pt_d,P_d,dP_d,it,sx,sz,borde,dt,A_z,A_x,B_z,B_x,Psi_x,Psi_z,Z_x,Z_z,temp1,dh,modo); //#blocks=dimGrid,
temp = A_d;
A_d = B_d;
B_d = temp;
}
if(modo==1 || modo==3){
hipMemcpy(P_h, P_d, nx*ny*nt*sizeof(float), hipMemcpyDeviceToHost);
}
if(modo==2 || modo==3){
hipMemcpy(dP_h, dP_d, nx*ny*nt*sizeof(float), hipMemcpyDeviceToHost);
}
hipMemcpy(Pt_h, Pt_d, (nx-2*borde)*nt*sizeof(float), hipMemcpyDeviceToHost);
//---------------------------------------
// Guarda informacion -----------------------
// Trazas
source=fopen("Trazas.bin","wb");
fwrite(Pt_h,sizeof(float),(nx-2*borde)*nt,source);
fclose(source);
free(Pt_h);
hipFree(Pt_d);
// Frente de Onda
source=fopen("Frentedeonda.bin","wb");
fwrite(P_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(P_h);
hipFree(P_d);
// Derivad Frente de Onda
source=fopen("DerivadaFrentedeOnda.bin","wb");
fwrite(dP_h,sizeof(float),nx*ny*nt,source);
fclose(source);
free(dP_h);
hipFree(dP_d);
// Liberamos resto de punteros
// Host
free(s_h);
free(v_h);
// Device
hipFree(A_d);
hipFree(B_d);
hipFree(lap);
hipFree(s_d);
hipFree(v_d);
hipFree(A_x);
hipFree(A_z);
hipFree(B_x);
hipFree(B_z);
hipFree(Psi_x);
hipFree(Psi_z);
hipFree(Z_x);
hipFree(Z_z);
printf("\n Creo que Termine ....\n");
hipDeviceReset();
return 0;
} | .text
.file "propagator_8_cpml.hip"
.globl _Z25__device_stub__kernel_lapPfS_iif # -- Begin function _Z25__device_stub__kernel_lapPfS_iif
.p2align 4, 0x90
.type _Z25__device_stub__kernel_lapPfS_iif,@function
_Z25__device_stub__kernel_lapPfS_iif: # @_Z25__device_stub__kernel_lapPfS_iif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_lapPfS_iif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_lapPfS_iif, .Lfunc_end0-_Z25__device_stub__kernel_lapPfS_iif
.cfi_endproc
# -- End function
.globl _Z25__device_stub__get_CPML_xPfS_iffifff # -- Begin function _Z25__device_stub__get_CPML_xPfS_iffifff
.p2align 4, 0x90
.type _Z25__device_stub__get_CPML_xPfS_iffifff,@function
_Z25__device_stub__get_CPML_xPfS_iffifff: # @_Z25__device_stub__get_CPML_xPfS_iffifff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10get_CPML_xPfS_iffifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z25__device_stub__get_CPML_xPfS_iffifff, .Lfunc_end1-_Z25__device_stub__get_CPML_xPfS_iffifff
.cfi_endproc
# -- End function
.globl _Z25__device_stub__get_CPML_zPfS_iffifff # -- Begin function _Z25__device_stub__get_CPML_zPfS_iffifff
.p2align 4, 0x90
.type _Z25__device_stub__get_CPML_zPfS_iffifff,@function
_Z25__device_stub__get_CPML_zPfS_iffifff: # @_Z25__device_stub__get_CPML_zPfS_iffifff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10get_CPML_zPfS_iffifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z25__device_stub__get_CPML_zPfS_iffifff, .Lfunc_end2-_Z25__device_stub__get_CPML_zPfS_iffifff
.cfi_endproc
# -- End function
.globl _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif # -- Begin function _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif
.p2align 4, 0x90
.type _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif,@function
_Z18__device_stub__PSIPfS_S_S_S_S_S_iiif: # @_Z18__device_stub__PSIPfS_S_S_S_S_S_iiif
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3PSIPfS_S_S_S_S_S_iiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif, .Lfunc_end3-_Z18__device_stub__PSIPfS_S_S_S_S_S_iiif
.cfi_endproc
# -- End function
.globl _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi # -- Begin function _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.p2align 4, 0x90
.type _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi,@function
_Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi: # @_Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.cfi_startproc
# %bb.0:
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 320
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 320(%rsp), %rax
movq %rax, 144(%rsp)
leaq 328(%rsp), %rax
movq %rax, 152(%rsp)
leaq 336(%rsp), %rax
movq %rax, 160(%rsp)
leaq 344(%rsp), %rax
movq %rax, 168(%rsp)
leaq 352(%rsp), %rax
movq %rax, 176(%rsp)
leaq 360(%rsp), %rax
movq %rax, 184(%rsp)
leaq 368(%rsp), %rax
movq %rax, 192(%rsp)
leaq 376(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 448(%rsp), %rax
movq %rax, 280(%rsp)
movq %rsp, %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $328, %rsp # imm = 0x148
.cfi_adjust_cfa_offset -328
retq
.Lfunc_end4:
.size _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, .Lfunc_end4-_Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x3a83126f # float 0.00100000005
.LCPI5_1:
.long 0x41c80000 # float 25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %rbp # imm = 0x100000020
callq hipDeviceReset
movl $170000, %edi # imm = 0x29810
movl $4, %esi
callq calloc
movq %rax, 352(%rsp) # 8-byte Spill
movl $14910, %edi # imm = 0x3A3E
movl $4, %esi
callq calloc
movq %rax, %r14
movl $1000, %edi # imm = 0x3E8
movl $4, %esi
callq calloc
movq %rax, %r15
movl $14910000, %edi # imm = 0xE38230
movl $4, %esi
callq calloc
movq %rax, 360(%rsp) # 8-byte Spill
movl $14910000, %edi # imm = 0xE38230
movl $4, %esi
callq calloc
movq %rax, 368(%rsp) # 8-byte Spill
leaq 224(%rsp), %rdi
movl $680000, %esi # imm = 0xA6040
callq hipMalloc
leaq 8(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 136(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 216(%rsp), %rdi
movl $59640000, %esi # imm = 0x38E08C0
callq hipMalloc
leaq 344(%rsp), %rdi
movl $59640000, %esi # imm = 0x38E08C0
callq hipMalloc
leaq 208(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 200(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 176(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 168(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 160(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 192(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 184(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 336(%rsp), %rdi
movl $59640, %esi # imm = 0xE8F8
callq hipMalloc
leaq 128(%rsp), %rdi
movl $840, %esi # imm = 0x348
callq hipMalloc
leaq 120(%rsp), %rdi
movl $284, %esi # imm = 0x11C
callq hipMalloc
leaq 112(%rsp), %rdi
movl $840, %esi # imm = 0x348
callq hipMalloc
leaq 104(%rsp), %rdi
movl $284, %esi # imm = 0x11C
callq hipMalloc
movq 8(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 136(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 176(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 168(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 160(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 192(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 184(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 336(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
xorl %esi, %esi
callq hipMemset
movq 128(%rsp), %rdi
movl $840, %edx # imm = 0x348
xorl %esi, %esi
callq hipMemset
movq 120(%rsp), %rdi
movl $284, %edx # imm = 0x11C
xorl %esi, %esi
callq hipMemset
movq 112(%rsp), %rdi
movl $840, %edx # imm = 0x348
xorl %esi, %esi
callq hipMemset
movq 104(%rsp), %rdi
movl $284, %edx # imm = 0x11C
xorl %esi, %esi
callq hipMemset
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $4000, %esi # imm = 0xFA0
movl $1, %edx
movq %r15, %rdi
movq %rax, %rcx
callq fread
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq fclose
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $59640, %esi # imm = 0xE8F8
movl $1, %edx
movq %r14, %rdi
movq %rax, %rcx
callq fread
movl $.Lstr.1, %edi
callq puts@PLT
movq %rbx, %rdi
callq fclose
movq 200(%rsp), %rdi
movl $59640, %edx # imm = 0xE8F8
movq %r14, 384(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 208(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r15, 376(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -25(%rbp), %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 128(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $20, 32(%rsp)
movl $953267991, 24(%rsp) # imm = 0x38D1B717
movl $1167253504, 16(%rsp) # imm = 0x4592E000
movl $210, 152(%rsp)
movl $981668463, 144(%rsp) # imm = 0x3A83126F
movl $1103626240, 4(%rsp) # imm = 0x41C80000
movl $1077936128, (%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 152(%rsp), %rax
movq %rax, 280(%rsp)
leaq 144(%rsp), %rax
movq %rax, 288(%rsp)
leaq 4(%rsp), %rax
movq %rax, 296(%rsp)
movq %rsp, %rax
movq %rax, 304(%rsp)
leaq 56(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z10get_CPML_xPfS_iffifff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
leaq -29(%rbp), %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 120(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $20, 32(%rsp)
movl $953267991, 24(%rsp) # imm = 0x38D1B717
movl $1167253504, 16(%rsp) # imm = 0x4592E000
movl $71, 152(%rsp)
movl $981668463, 144(%rsp) # imm = 0x3A83126F
movl $1103626240, 4(%rsp) # imm = 0x41C80000
movl $1077936128, (%rsp) # imm = 0x40400000
leaq 80(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 152(%rsp), %rax
movq %rax, 280(%rsp)
leaq 144(%rsp), %rax
movq %rax, 288(%rsp)
leaq 4(%rsp), %rax
movq %rax, 296(%rsp)
movq %rsp, %rax
movq %rax, 304(%rsp)
leaq 56(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z10get_CPML_zPfS_iffifff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movabsq $137438953504, %rbp # imm = 0x2000000020
movabsq $12884901895, %r15 # imm = 0x300000007
leaq 88(%rsp), %r13
leaq 240(%rsp), %rbx
xorl %r12d, %r12d
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_11: # in Loop: Header=BB5_5 Depth=1
movq 8(%rsp), %rax
movq 136(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 136(%rsp)
movl %r14d, %r12d
cmpl $1000, %r14d # imm = 0x3E8
je .LBB5_12
.LBB5_5: # =>This Inner Loop Header: Depth=1
leal 1(%r12), %r14d
movl $.L.str.5, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_5 Depth=1
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq 128(%rsp), %rax
movq %rax, 72(%rsp)
movq 112(%rsp), %rax
movq %rax, 48(%rsp)
movq 120(%rsp), %rax
movq %rax, 40(%rsp)
movq 104(%rsp), %rax
movq %rax, 32(%rsp)
movq 168(%rsp), %rax
movq %rax, 24(%rsp)
movq 160(%rsp), %rax
movq %rax, 16(%rsp)
movl $20, 4(%rsp)
movl $210, (%rsp)
movl $71, 236(%rsp)
movl $1103626240, 232(%rsp) # imm = 0x41C80000
leaq 80(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rax
movq %rax, 248(%rsp)
leaq 48(%rsp), %rax
movq %rax, 256(%rsp)
leaq 40(%rsp), %rax
movq %rax, 264(%rsp)
leaq 32(%rsp), %rax
movq %rax, 272(%rsp)
leaq 24(%rsp), %rax
movq %rax, 280(%rsp)
leaq 16(%rsp), %rax
movq %rax, 288(%rsp)
leaq 4(%rsp), %rax
movq %rax, 296(%rsp)
movq %rsp, %rax
movq %rax, 304(%rsp)
leaq 236(%rsp), %rax
movq %rax, 312(%rsp)
leaq 232(%rsp), %rax
movq %rax, 320(%rsp)
leaq 56(%rsp), %rdi
movq %r13, %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z3PSIPfS_S_S_S_S_S_iiif, %edi
movq %rbx, %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7: # in Loop: Header=BB5_5 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_9
# %bb.8: # in Loop: Header=BB5_5 Depth=1
movq 176(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl $210, 32(%rsp)
movl $71, 24(%rsp)
movl $1103626240, 16(%rsp) # imm = 0x41C80000
leaq 80(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 56(%rsp), %rdi
movq %r13, %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z10kernel_lapPfS_iif, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_9: # in Loop: Header=BB5_5 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_11
# %bb.10: # in Loop: Header=BB5_5 Depth=1
movq 176(%rsp), %rdi
movq 8(%rsp), %rsi
movq 136(%rsp), %rdx
movq 208(%rsp), %r9
movl $210, %ecx
movl $71, %r8d
movss .LCPI5_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
pushq $1
.cfi_adjust_cfa_offset 8
pushq 344(%rsp)
.cfi_adjust_cfa_offset 8
pushq 200(%rsp)
.cfi_adjust_cfa_offset 8
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq $20
.cfi_adjust_cfa_offset 8
pushq $6
.cfi_adjust_cfa_offset 8
pushq $105
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
pushq 456(%rsp)
.cfi_adjust_cfa_offset 8
pushq 336(%rsp)
.cfi_adjust_cfa_offset 8
pushq 352(%rsp)
.cfi_adjust_cfa_offset 8
pushq 336(%rsp)
.cfi_adjust_cfa_offset 8
callq _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
addq $144, %rsp
.cfi_adjust_cfa_offset -144
jmp .LBB5_11
.LBB5_12:
movq 216(%rsp), %rsi
movl $59640000, %edx # imm = 0x38E08C0
movq 360(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 224(%rsp), %rsi
movl $680000, %edx # imm = 0xA6040
movq 352(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %edi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
movl $4, %esi
movl $170000, %edx # imm = 0x29810
movq %r15, %rdi
movq %rax, %rcx
callq fwrite
movq %rbx, %rdi
callq fclose
movq %r15, %rdi
callq free
movq 224(%rsp), %rdi
callq hipFree
movl $.L.str.8, %edi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
movl $4, %esi
movl $14910000, %edx # imm = 0xE38230
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %rbx, %rdi
callq fclose
movq %r14, %rdi
callq free
movq 216(%rsp), %rdi
callq hipFree
movl $.L.str.9, %edi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
movl $4, %esi
movl $14910000, %edx # imm = 0xE38230
movq 368(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %rbx, %rdi
callq fclose
movq %r14, %rdi
callq free
movq 344(%rsp), %rdi
callq hipFree
movq 376(%rsp), %rdi # 8-byte Reload
callq free
movq 384(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movl $.Lstr.2, %edi
callq puts@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_lapPfS_iif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10get_CPML_xPfS_iffifff, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10get_CPML_zPfS_iffifff, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3PSIPfS_S_S_S_S_S_iiif, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_lapPfS_iif,@object # @_Z10kernel_lapPfS_iif
.section .rodata,"a",@progbits
.globl _Z10kernel_lapPfS_iif
.p2align 3, 0x0
_Z10kernel_lapPfS_iif:
.quad _Z25__device_stub__kernel_lapPfS_iif
.size _Z10kernel_lapPfS_iif, 8
.type _Z10get_CPML_xPfS_iffifff,@object # @_Z10get_CPML_xPfS_iffifff
.globl _Z10get_CPML_xPfS_iffifff
.p2align 3, 0x0
_Z10get_CPML_xPfS_iffifff:
.quad _Z25__device_stub__get_CPML_xPfS_iffifff
.size _Z10get_CPML_xPfS_iffifff, 8
.type _Z10get_CPML_zPfS_iffifff,@object # @_Z10get_CPML_zPfS_iffifff
.globl _Z10get_CPML_zPfS_iffifff
.p2align 3, 0x0
_Z10get_CPML_zPfS_iffifff:
.quad _Z25__device_stub__get_CPML_zPfS_iffifff
.size _Z10get_CPML_zPfS_iffifff, 8
.type _Z3PSIPfS_S_S_S_S_S_iiif,@object # @_Z3PSIPfS_S_S_S_S_S_iiif
.globl _Z3PSIPfS_S_S_S_S_S_iiif
.p2align 3, 0x0
_Z3PSIPfS_S_S_S_S_S_iiif:
.quad _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif
.size _Z3PSIPfS_S_S_S_S_S_iiif, 8
.type _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi,@object # @_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.globl _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.p2align 3, 0x0
_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi:
.quad _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.size _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Fuente.bin"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "rb"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Modelo_ori.bin"
.size .L.str.3, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Voy en el paso temporal %d \n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Trazas.bin"
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "wb"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Frentedeonda.bin"
.size .L.str.8, 17
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "DerivadaFrentedeOnda.bin"
.size .L.str.9, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10kernel_lapPfS_iif"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10get_CPML_xPfS_iffifff"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10get_CPML_zPfS_iffifff"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3PSIPfS_S_S_S_S_S_iiif"
.size .L__unnamed_4, 25
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi"
.size .L__unnamed_5, 62
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nDatos de fuente cargados..."
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nDatos de modelo original cargados..."
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n Creo que Termine ...."
.size .Lstr.2, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_lapPfS_iif
.addrsig_sym _Z25__device_stub__get_CPML_xPfS_iffifff
.addrsig_sym _Z25__device_stub__get_CPML_zPfS_iffifff
.addrsig_sym _Z18__device_stub__PSIPfS_S_S_S_S_S_iiif
.addrsig_sym _Z29__device_stub__kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_lapPfS_iif
.addrsig_sym _Z10get_CPML_xPfS_iffifff
.addrsig_sym _Z10get_CPML_zPfS_iffifff
.addrsig_sym _Z3PSIPfS_S_S_S_S_S_iiif
.addrsig_sym _Z14kernel_propagaPfS_S_iiS_S_S_S_S_iiiifS_S_S_S_S_S_S_S_S_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
cudaMalloc ( (void**) &a_gpu, size );
cudaMalloc ( (void**) &b_gpu, size );
cudaMalloc ( (void**) &c_gpu, size );
cudaMemcpy ( a_gpu, a, size, cudaMemcpyHostToDevice );
cudaMemcpy ( b_gpu, b, size, cudaMemcpyHostToDevice );
cudaMemcpy ( c_gpu, c, size, cudaMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} | code for sm_80
Function : _Z4kernPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, 3 ; /* 0x4040000000057421 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
cudaMalloc ( (void**) &a_gpu, size );
cudaMalloc ( (void**) &b_gpu, size );
cudaMalloc ( (void**) &c_gpu, size );
cudaMemcpy ( a_gpu, a, size, cudaMemcpyHostToDevice );
cudaMemcpy ( b_gpu, b, size, cudaMemcpyHostToDevice );
cudaMemcpy ( c_gpu, c, size, cudaMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} | .file "tmpxft_000c8902_00000000-6_transaction_count.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4kernPfPf
.type _Z23__device_stub__Z4kernPfPf, @function
_Z23__device_stub__Z4kernPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4kernPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4kernPfPf, .-_Z23__device_stub__Z4kernPfPf
.globl _Z4kernPf
.type _Z4kernPf, @function
_Z4kernPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4kernPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4kernPf, .-_Z4kernPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, %ebx
jmp .L13
.L12:
subl $1, %ebx
je .L17
.L13:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4kernPfPf
jmp .L12
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4kernPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4kernPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
cudaMalloc ( (void**) &a_gpu, size );
cudaMalloc ( (void**) &b_gpu, size );
cudaMalloc ( (void**) &c_gpu, size );
cudaMemcpy ( a_gpu, a, size, cudaMemcpyHostToDevice );
cudaMemcpy ( b_gpu, b, size, cudaMemcpyHostToDevice );
cudaMemcpy ( c_gpu, c, size, cudaMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
hipMalloc ( (void**) &a_gpu, size );
hipMalloc ( (void**) &b_gpu, size );
hipMalloc ( (void**) &c_gpu, size );
hipMemcpy ( a_gpu, a, size, hipMemcpyHostToDevice );
hipMemcpy ( b_gpu, b, size, hipMemcpyHostToDevice );
hipMemcpy ( c_gpu, c, size, hipMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
hipMalloc ( (void**) &a_gpu, size );
hipMalloc ( (void**) &b_gpu, size );
hipMalloc ( (void**) &c_gpu, size );
hipMemcpy ( a_gpu, a, size, hipMemcpyHostToDevice );
hipMemcpy ( b_gpu, b, size, hipMemcpyHostToDevice );
hipMemcpy ( c_gpu, c, size, hipMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4kernPf
.globl _Z4kernPf
.p2align 8
.type _Z4kernPf,@function
_Z4kernPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x40400000, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4kernPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4kernPf, .Lfunc_end0-_Z4kernPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4kernPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4kernPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void kern(float *a) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
a[idx] = a[idx] + 3.0;
}
int main() {
int tn, nx=32*16*2;
float *a, *b, *c;
a = (float *) malloc (nx*sizeof(float));
b = (float *) malloc (nx*sizeof(float));
c = (float *) malloc (nx*sizeof(float));
float *a_gpu, *b_gpu, *c_gpu;
int size = nx*sizeof(float);
hipMalloc ( (void**) &a_gpu, size );
hipMalloc ( (void**) &b_gpu, size );
hipMalloc ( (void**) &c_gpu, size );
hipMemcpy ( a_gpu, a, size, hipMemcpyHostToDevice );
hipMemcpy ( b_gpu, b, size, hipMemcpyHostToDevice );
hipMemcpy ( c_gpu, c, size, hipMemcpyHostToDevice );
int tpb = 512;
int bpg = nx/tpb;
for(tn=1; tn<=10; tn++) {
kern <<<dim3(bpg),dim3(tpb)>>> (a_gpu);
}
} | .text
.file "transaction_count.hip"
.globl _Z19__device_stub__kernPf # -- Begin function _Z19__device_stub__kernPf
.p2align 4, 0x90
.type _Z19__device_stub__kernPf,@function
_Z19__device_stub__kernPf: # @_Z19__device_stub__kernPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4kernPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__kernPf, .Lfunc_end0-_Z19__device_stub__kernPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r12
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $10, %r12d
leaq 510(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 16(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z4kernPf, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4kernPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4kernPf,@object # @_Z4kernPf
.section .rodata,"a",@progbits
.globl _Z4kernPf
.p2align 3, 0x0
_Z4kernPf:
.quad _Z19__device_stub__kernPf
.size _Z4kernPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4kernPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__kernPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4kernPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4kernPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, 3 ; /* 0x4040000000057421 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4kernPf
.globl _Z4kernPf
.p2align 8
.type _Z4kernPf,@function
_Z4kernPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x40400000, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4kernPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4kernPf, .Lfunc_end0-_Z4kernPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4kernPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4kernPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8902_00000000-6_transaction_count.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4kernPfPf
.type _Z23__device_stub__Z4kernPfPf, @function
_Z23__device_stub__Z4kernPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4kernPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4kernPfPf, .-_Z23__device_stub__Z4kernPfPf
.globl _Z4kernPf
.type _Z4kernPf, @function
_Z4kernPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4kernPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4kernPf, .-_Z4kernPf
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, %ebx
jmp .L13
.L12:
subl $1, %ebx
je .L17
.L13:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4kernPfPf
jmp .L12
.L17:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4kernPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4kernPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transaction_count.hip"
.globl _Z19__device_stub__kernPf # -- Begin function _Z19__device_stub__kernPf
.p2align 4, 0x90
.type _Z19__device_stub__kernPf,@function
_Z19__device_stub__kernPf: # @_Z19__device_stub__kernPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4kernPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__kernPf, .Lfunc_end0-_Z19__device_stub__kernPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rbx # imm = 0x100000002
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r12
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $10, %r12d
leaq 510(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 16(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z4kernPf, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4kernPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4kernPf,@object # @_Z4kernPf
.section .rodata,"a",@progbits
.globl _Z4kernPf
.p2align 3, 0x0
_Z4kernPf:
.quad _Z19__device_stub__kernPf
.size _Z4kernPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4kernPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__kernPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4kernPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} | code for sm_80
Function : vsquare
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*00a0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} | .file "tmpxft_000b28b1_00000000-6_vsquareold.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7vsquarePKdPdPKdPd
.type _Z29__device_stub__Z7vsquarePKdPdPKdPd, @function
_Z29__device_stub__Z7vsquarePKdPdPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq vsquare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7vsquarePKdPdPKdPd, .-_Z29__device_stub__Z7vsquarePKdPdPKdPd
.globl vsquare
.type vsquare, @function
vsquare:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7vsquarePKdPdPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vsquare, .-vsquare
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vsquare"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vsquare(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} | #include <hip/hip_runtime.h>
// filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vsquare
.globl vsquare
.p2align 8
.type vsquare,@function
vsquare:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vsquare
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vsquare, .Lfunc_end0-vsquare
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vsquare
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vsquare.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// filename: vsquare.cu
// a simple CUDA kernel to element multiply vector with itself
extern "C" // ensure function name to be exactly "vsquare"
{
__global__ void vsquare(const double *a, double *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] * a[i];
}
} | .text
.file "vsquareold.hip"
.globl __device_stub__vsquare # -- Begin function __device_stub__vsquare
.p2align 4, 0x90
.type __device_stub__vsquare,@function
__device_stub__vsquare: # @__device_stub__vsquare
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $vsquare, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__vsquare, .Lfunc_end0-__device_stub__vsquare
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vsquare, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vsquare,@object # @vsquare
.section .rodata,"a",@progbits
.globl vsquare
.p2align 3, 0x0
vsquare:
.quad __device_stub__vsquare
.size vsquare, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vsquare"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vsquare
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vsquare
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : vsquare
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0e0000000000 */
/*00a0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vsquare
.globl vsquare
.p2align 8
.type vsquare,@function
vsquare:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vsquare
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vsquare, .Lfunc_end0-vsquare
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vsquare
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vsquare.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b28b1_00000000-6_vsquareold.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7vsquarePKdPdPKdPd
.type _Z29__device_stub__Z7vsquarePKdPdPKdPd, @function
_Z29__device_stub__Z7vsquarePKdPdPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq vsquare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z7vsquarePKdPdPKdPd, .-_Z29__device_stub__Z7vsquarePKdPdPKdPd
.globl vsquare
.type vsquare, @function
vsquare:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7vsquarePKdPdPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vsquare, .-vsquare
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vsquare"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vsquare(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vsquareold.hip"
.globl __device_stub__vsquare # -- Begin function __device_stub__vsquare
.p2align 4, 0x90
.type __device_stub__vsquare,@function
__device_stub__vsquare: # @__device_stub__vsquare
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $vsquare, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__vsquare, .Lfunc_end0-__device_stub__vsquare
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vsquare, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vsquare,@object # @vsquare
.section .rodata,"a",@progbits
.globl vsquare
.p2align 3, 0x0
vsquare:
.quad __device_stub__vsquare
.size vsquare, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vsquare"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vsquare
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vsquare
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //ECGR 6090 Heterogeneous Computing Homework 1
// Problem 1 - Naive Matrix Multiplication on GPU
//Written by Aneri Sheth - 801085402
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define N 100
#define M 100
#define k 100
__global__ void matrix_mul(float *a, float *b, float *c){
int row = (blockIdx.y * blockDim.y) + threadIdx.y; //where am I in matrix
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
float temp = 0.0; //calculate sum
for(int i = 0;i < k;i++)
{
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp; //final c matrix
}
//Function to initialize matrices with random values
void randomInit(float* data, int size)
{
for (int i = 0; i < size; i++)
for (int j = 0; j < size; j++)
*(data + i*size + j) = rand() % 10;
}
//Function to display matrices
void display_matrix(int size, float *matrix)
{
for(int i = 0; i < size; i++){
for (int j = 0; j < size; j++){
printf("Matrix = %f ",*(matrix + i*size + j));
}
}
}
int main(void)
{
float *a, *b, *c; //CPU copies
float *g_a, *g_b, *g_c; //GPU copies
int matrix_size = N * M * sizeof(float);
cudaEvent_t start, stop; //time start and stop
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Allocate device memory
cudaMalloc((void **)&g_a, matrix_size);
cudaMalloc((void **)&g_b, matrix_size);
cudaMalloc((void **)&g_c, matrix_size);
//Allocate CPU memory
a = (float *)malloc(matrix_size); randomInit(a, N);
b = (float *)malloc(matrix_size); randomInit(b, M);
c = (float *)malloc(matrix_size);
//Copy CPU memory to GPU memory
cudaMemcpy(g_a, a, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(g_b, b, matrix_size, cudaMemcpyHostToDevice);
//display_matrix(N,k,a);
//display_matrix(k,M,b);
//Set thread and grid dimensions
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
//dim3 threadBlocks = dim3()
dim3 threadsPerBlock = dim3(16,16,1);
cudaEventRecord( start, 0 );
//Call the kernel
matrix_mul<<<threadBlocks,threadsPerBlock>>>(g_a,g_b,g_c);
//display_matrix(N,M,g_c);
cudaEventRecord( stop, 0 );
cudaEventSynchronize(stop);
cudaEventElapsedTime( &time, start, stop);
cudaEventDestroy( start );
cudaEventDestroy( stop );
//display_matrix(N,M,g_c);
printf("GPU Execution Time = %f\n",time);
//Copy from device to host
cudaMemcpy(c, g_c, matrix_size, cudaMemcpyDeviceToHost);
//display_matrix(N,M,c);
//free cpu and gpu memory
free(a); free(b); free(c);
cudaFree(g_a); cudaFree(g_b); cudaFree(g_c);
return 0;
} | .file "tmpxft_00179efd_00000000-6_Naive_matrix_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r15
leaq 0(,%r15,4), %r14
leaq (%rdi,%r14), %rbp
movl $0, %r13d
movl $0, %r12d
.L5:
movq (%rsp), %rax
leaq (%rax,%r13,4), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r12d
addq %r15, %r13
addq %r14, %rbp
cmpl %r12d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix = %f "
.text
.globl _Z14display_matrixiPf
.type _Z14display_matrixiPf, @function
_Z14display_matrixiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movq %rsi, 16(%rsp)
testl %edi, %edi
jle .L9
movslq %edi, %r15
leaq 0(,%r15,4), %rax
movq %rax, 24(%rsp)
leaq (%rsi,%rax), %rbp
movl $0, %r14d
movl $0, %r13d
leaq .LC0(%rip), %r12
.L11:
movq 16(%rsp), %rax
leaq (%rax,%r14,4), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addl $1, %r13d
addq %r15, %r14
movq 24(%rsp), %rax
addq %rax, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L9:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14display_matrixiPf, .-_Z14display_matrixiPf
.globl _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
.type _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_, @function
_Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_mulPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_, .-_Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
.globl _Z10matrix_mulPfS_S_
.type _Z10matrix_mulPfS_S_, @function
_Z10matrix_mulPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrix_mulPfS_S_, .-_Z10matrix_mulPfS_S_
.section .rodata.str1.1
.LC1:
.string "GPU Execution Time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100, %esi
movq %rax, %rdi
call _Z10randomInitPfi
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %esi
movq %rax, %rdi
call _Z10randomInitPfi
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $7, 48(%rsp)
movl $7, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10matrix_mulPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //ECGR 6090 Heterogeneous Computing Homework 1
// Problem 1 - Naive Matrix Multiplication on GPU
//Written by Aneri Sheth - 801085402
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define N 100
#define M 100
#define k 100
__global__ void matrix_mul(float *a, float *b, float *c){
int row = (blockIdx.y * blockDim.y) + threadIdx.y; //where am I in matrix
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
float temp = 0.0; //calculate sum
for(int i = 0;i < k;i++)
{
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp; //final c matrix
}
//Function to initialize matrices with random values
void randomInit(float* data, int size)
{
for (int i = 0; i < size; i++)
for (int j = 0; j < size; j++)
*(data + i*size + j) = rand() % 10;
}
//Function to display matrices
void display_matrix(int size, float *matrix)
{
for(int i = 0; i < size; i++){
for (int j = 0; j < size; j++){
printf("Matrix = %f ",*(matrix + i*size + j));
}
}
}
int main(void)
{
float *a, *b, *c; //CPU copies
float *g_a, *g_b, *g_c; //GPU copies
int matrix_size = N * M * sizeof(float);
cudaEvent_t start, stop; //time start and stop
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//Allocate device memory
cudaMalloc((void **)&g_a, matrix_size);
cudaMalloc((void **)&g_b, matrix_size);
cudaMalloc((void **)&g_c, matrix_size);
//Allocate CPU memory
a = (float *)malloc(matrix_size); randomInit(a, N);
b = (float *)malloc(matrix_size); randomInit(b, M);
c = (float *)malloc(matrix_size);
//Copy CPU memory to GPU memory
cudaMemcpy(g_a, a, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(g_b, b, matrix_size, cudaMemcpyHostToDevice);
//display_matrix(N,k,a);
//display_matrix(k,M,b);
//Set thread and grid dimensions
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
//dim3 threadBlocks = dim3()
dim3 threadsPerBlock = dim3(16,16,1);
cudaEventRecord( start, 0 );
//Call the kernel
matrix_mul<<<threadBlocks,threadsPerBlock>>>(g_a,g_b,g_c);
//display_matrix(N,M,g_c);
cudaEventRecord( stop, 0 );
cudaEventSynchronize(stop);
cudaEventElapsedTime( &time, start, stop);
cudaEventDestroy( start );
cudaEventDestroy( stop );
//display_matrix(N,M,g_c);
printf("GPU Execution Time = %f\n",time);
//Copy from device to host
cudaMemcpy(c, g_c, matrix_size, cudaMemcpyDeviceToHost);
//display_matrix(N,M,c);
//free cpu and gpu memory
free(a); free(b); free(c);
cudaFree(g_a); cudaFree(g_b); cudaFree(g_c);
return 0;
} | //ECGR 6090 Heterogeneous Computing Homework 1
// Problem 1 - Naive Matrix Multiplication on GPU
//Written by Aneri Sheth - 801085402
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define N 100
#define M 100
#define k 100
__global__ void matrix_mul(float *a, float *b, float *c){
int row = (blockIdx.y * blockDim.y) + threadIdx.y; //where am I in matrix
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
float temp = 0.0; //calculate sum
for(int i = 0;i < k;i++)
{
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp; //final c matrix
}
//Function to initialize matrices with random values
void randomInit(float* data, int size)
{
for (int i = 0; i < size; i++)
for (int j = 0; j < size; j++)
*(data + i*size + j) = rand() % 10;
}
//Function to display matrices
void display_matrix(int size, float *matrix)
{
for(int i = 0; i < size; i++){
for (int j = 0; j < size; j++){
printf("Matrix = %f ",*(matrix + i*size + j));
}
}
}
int main(void)
{
float *a, *b, *c; //CPU copies
float *g_a, *g_b, *g_c; //GPU copies
int matrix_size = N * M * sizeof(float);
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
//Allocate device memory
hipMalloc((void **)&g_a, matrix_size);
hipMalloc((void **)&g_b, matrix_size);
hipMalloc((void **)&g_c, matrix_size);
//Allocate CPU memory
a = (float *)malloc(matrix_size); randomInit(a, N);
b = (float *)malloc(matrix_size); randomInit(b, M);
c = (float *)malloc(matrix_size);
//Copy CPU memory to GPU memory
hipMemcpy(g_a, a, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(g_b, b, matrix_size, hipMemcpyHostToDevice);
//display_matrix(N,k,a);
//display_matrix(k,M,b);
//Set thread and grid dimensions
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
//dim3 threadBlocks = dim3()
dim3 threadsPerBlock = dim3(16,16,1);
hipEventRecord( start, 0 );
//Call the kernel
matrix_mul<<<threadBlocks,threadsPerBlock>>>(g_a,g_b,g_c);
//display_matrix(N,M,g_c);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop);
hipEventDestroy( start );
hipEventDestroy( stop );
//display_matrix(N,M,g_c);
printf("GPU Execution Time = %f\n",time);
//Copy from device to host
hipMemcpy(c, g_c, matrix_size, hipMemcpyDeviceToHost);
//display_matrix(N,M,c);
//free cpu and gpu memory
free(a); free(b); free(c);
hipFree(g_a); hipFree(g_b); hipFree(g_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //ECGR 6090 Heterogeneous Computing Homework 1
// Problem 1 - Naive Matrix Multiplication on GPU
//Written by Aneri Sheth - 801085402
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define N 100
#define M 100
#define k 100
__global__ void matrix_mul(float *a, float *b, float *c){
int row = (blockIdx.y * blockDim.y) + threadIdx.y; //where am I in matrix
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
float temp = 0.0; //calculate sum
for(int i = 0;i < k;i++)
{
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp; //final c matrix
}
//Function to initialize matrices with random values
void randomInit(float* data, int size)
{
for (int i = 0; i < size; i++)
for (int j = 0; j < size; j++)
*(data + i*size + j) = rand() % 10;
}
//Function to display matrices
void display_matrix(int size, float *matrix)
{
for(int i = 0; i < size; i++){
for (int j = 0; j < size; j++){
printf("Matrix = %f ",*(matrix + i*size + j));
}
}
}
int main(void)
{
float *a, *b, *c; //CPU copies
float *g_a, *g_b, *g_c; //GPU copies
int matrix_size = N * M * sizeof(float);
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
//Allocate device memory
hipMalloc((void **)&g_a, matrix_size);
hipMalloc((void **)&g_b, matrix_size);
hipMalloc((void **)&g_c, matrix_size);
//Allocate CPU memory
a = (float *)malloc(matrix_size); randomInit(a, N);
b = (float *)malloc(matrix_size); randomInit(b, M);
c = (float *)malloc(matrix_size);
//Copy CPU memory to GPU memory
hipMemcpy(g_a, a, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(g_b, b, matrix_size, hipMemcpyHostToDevice);
//display_matrix(N,k,a);
//display_matrix(k,M,b);
//Set thread and grid dimensions
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
//dim3 threadBlocks = dim3()
dim3 threadsPerBlock = dim3(16,16,1);
hipEventRecord( start, 0 );
//Call the kernel
matrix_mul<<<threadBlocks,threadsPerBlock>>>(g_a,g_b,g_c);
//display_matrix(N,M,g_c);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop);
hipEventDestroy( start );
hipEventDestroy( stop );
//display_matrix(N,M,g_c);
printf("GPU Execution Time = %f\n",time);
//Copy from device to host
hipMemcpy(c, g_c, matrix_size, hipMemcpyDeviceToHost);
//display_matrix(N,M,c);
//free cpu and gpu memory
free(a); free(b); free(c);
hipFree(g_a); hipFree(g_b); hipFree(g_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPfS_S_
.globl _Z10matrix_mulPfS_S_
.p2align 8
.type _Z10matrix_mulPfS_S_,@function
_Z10matrix_mulPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, 0x64
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_nc_u32_e32 v3, 0x64, v3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x190
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v4, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v4, v7
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, 0x64, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPfS_S_, .Lfunc_end0-_Z10matrix_mulPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //ECGR 6090 Heterogeneous Computing Homework 1
// Problem 1 - Naive Matrix Multiplication on GPU
//Written by Aneri Sheth - 801085402
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<time.h>
#define N 100
#define M 100
#define k 100
__global__ void matrix_mul(float *a, float *b, float *c){
int row = (blockIdx.y * blockDim.y) + threadIdx.y; //where am I in matrix
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
float temp = 0.0; //calculate sum
for(int i = 0;i < k;i++)
{
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp; //final c matrix
}
//Function to initialize matrices with random values
void randomInit(float* data, int size)
{
for (int i = 0; i < size; i++)
for (int j = 0; j < size; j++)
*(data + i*size + j) = rand() % 10;
}
//Function to display matrices
void display_matrix(int size, float *matrix)
{
for(int i = 0; i < size; i++){
for (int j = 0; j < size; j++){
printf("Matrix = %f ",*(matrix + i*size + j));
}
}
}
int main(void)
{
float *a, *b, *c; //CPU copies
float *g_a, *g_b, *g_c; //GPU copies
int matrix_size = N * M * sizeof(float);
hipEvent_t start, stop; //time start and stop
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
//Allocate device memory
hipMalloc((void **)&g_a, matrix_size);
hipMalloc((void **)&g_b, matrix_size);
hipMalloc((void **)&g_c, matrix_size);
//Allocate CPU memory
a = (float *)malloc(matrix_size); randomInit(a, N);
b = (float *)malloc(matrix_size); randomInit(b, M);
c = (float *)malloc(matrix_size);
//Copy CPU memory to GPU memory
hipMemcpy(g_a, a, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(g_b, b, matrix_size, hipMemcpyHostToDevice);
//display_matrix(N,k,a);
//display_matrix(k,M,b);
//Set thread and grid dimensions
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
//dim3 threadBlocks = dim3()
dim3 threadsPerBlock = dim3(16,16,1);
hipEventRecord( start, 0 );
//Call the kernel
matrix_mul<<<threadBlocks,threadsPerBlock>>>(g_a,g_b,g_c);
//display_matrix(N,M,g_c);
hipEventRecord( stop, 0 );
hipEventSynchronize(stop);
hipEventElapsedTime( &time, start, stop);
hipEventDestroy( start );
hipEventDestroy( stop );
//display_matrix(N,M,g_c);
printf("GPU Execution Time = %f\n",time);
//Copy from device to host
hipMemcpy(c, g_c, matrix_size, hipMemcpyDeviceToHost);
//display_matrix(N,M,c);
//free cpu and gpu memory
free(a); free(b); free(c);
hipFree(g_a); hipFree(g_b); hipFree(g_c);
return 0;
} | .text
.file "Naive_matrix_mul.hip"
.globl _Z25__device_stub__matrix_mulPfS_S_ # -- Begin function _Z25__device_stub__matrix_mulPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPfS_S_,@function
_Z25__device_stub__matrix_mulPfS_S_: # @_Z25__device_stub__matrix_mulPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_mulPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPfS_S_, .Lfunc_end0-_Z25__device_stub__matrix_mulPfS_S_
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
leaq (,%r14,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addq %r15, %rbx
cmpq %r14, %r12
jne .LBB1_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge13
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z14display_matrixiPf # -- Begin function _Z14display_matrixiPf
.p2align 4, 0x90
.type _Z14display_matrixiPf,@function
_Z14display_matrixiPf: # @_Z14display_matrixiPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
leaq (,%r14,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r12
addq %r15, %rbx
cmpq %r14, %r12
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_6: # %._crit_edge13
retq
.Lfunc_end2:
.size _Z14display_matrixiPf, .Lfunc_end2-_Z14display_matrixiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movq %rax, %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r14
addq $400, %r15 # imm = 0x190
cmpq $100, %r14
jne .LBB3_1
# %bb.4: # %_Z10randomInitPfi.exit
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movq %rax, %r12
.p2align 4, 0x90
.LBB3_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i27
# in Loop: Header=BB3_5 Depth=1
incq %r15
addq $400, %r12 # imm = 0x190
cmpq $100, %r15
jne .LBB3_5
# %bb.8: # %_Z10randomInitPfi.exit30
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movq 40(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $30064771079, %rdi # imm = 0x700000007
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10matrix_mulPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_mulPfS_S_,@object # @_Z10matrix_mulPfS_S_
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPfS_S_
.p2align 3, 0x0
_Z10matrix_mulPfS_S_:
.quad _Z25__device_stub__matrix_mulPfS_S_
.size _Z10matrix_mulPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix = %f "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time = %f\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_mulPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179efd_00000000-6_Naive_matrix_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L3
movslq %esi, %r15
leaq 0(,%r15,4), %r14
leaq (%rdi,%r14), %rbp
movl $0, %r13d
movl $0, %r12d
.L5:
movq (%rsp), %rax
leaq (%rax,%r13,4), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r12d
addq %r15, %r13
addq %r14, %rbp
cmpl %r12d, 12(%rsp)
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix = %f "
.text
.globl _Z14display_matrixiPf
.type _Z14display_matrixiPf, @function
_Z14display_matrixiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 12(%rsp)
movq %rsi, 16(%rsp)
testl %edi, %edi
jle .L9
movslq %edi, %r15
leaq 0(,%r15,4), %rax
movq %rax, 24(%rsp)
leaq (%rsi,%rax), %rbp
movl $0, %r14d
movl $0, %r13d
leaq .LC0(%rip), %r12
.L11:
movq 16(%rsp), %rax
leaq (%rax,%r14,4), %rbx
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
addl $1, %r13d
addq %r15, %r14
movq 24(%rsp), %rax
addq %rax, %rbp
cmpl %r13d, 12(%rsp)
jne .L11
.L9:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z14display_matrixiPf, .-_Z14display_matrixiPf
.globl _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
.type _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_, @function
_Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_mulPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_, .-_Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
.globl _Z10matrix_mulPfS_S_
.type _Z10matrix_mulPfS_S_, @function
_Z10matrix_mulPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrix_mulPfS_S_, .-_Z10matrix_mulPfS_S_
.section .rodata.str1.1
.LC1:
.string "GPU Execution Time = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $100, %esi
movq %rax, %rdi
call _Z10randomInitPfi
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %esi
movq %rax, %rdi
call _Z10randomInitPfi
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %ecx
movl $40000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $7, 48(%rsp)
movl $7, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10matrix_mulPfS_S_PfS_S_
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10matrix_mulPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Naive_matrix_mul.hip"
.globl _Z25__device_stub__matrix_mulPfS_S_ # -- Begin function _Z25__device_stub__matrix_mulPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPfS_S_,@function
_Z25__device_stub__matrix_mulPfS_S_: # @_Z25__device_stub__matrix_mulPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_mulPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPfS_S_, .Lfunc_end0-_Z25__device_stub__matrix_mulPfS_S_
.cfi_endproc
# -- End function
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
leaq (,%r14,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r12
addq %r15, %rbx
cmpq %r14, %r12
jne .LBB1_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge13
retq
.Lfunc_end1:
.size _Z10randomInitPfi, .Lfunc_end1-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z14display_matrixiPf # -- Begin function _Z14display_matrixiPf
.p2align 4, 0x90
.type _Z14display_matrixiPf,@function
_Z14display_matrixiPf: # @_Z14display_matrixiPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
leaq (,%r14,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r12
addq %r15, %rbx
cmpq %r14, %r12
jne .LBB2_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB2_6: # %._crit_edge13
retq
.Lfunc_end2:
.size _Z14display_matrixiPf, .Lfunc_end2-_Z14display_matrixiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
movq %rax, %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r14
addq $400, %r15 # imm = 0x190
cmpq $100, %r14
jne .LBB3_1
# %bb.4: # %_Z10randomInitPfi.exit
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
movq %rax, %r12
.p2align 4, 0x90
.LBB3_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $100, %r13
jne .LBB3_6
# %bb.7: # %._crit_edge.i27
# in Loop: Header=BB3_5 Depth=1
incq %r15
addq $400, %r12 # imm = 0x190
cmpq $100, %r15
jne .LBB3_5
# %bb.8: # %_Z10randomInitPfi.exit30
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movq 40(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $30064771079, %rdi # imm = 0x700000007
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10matrix_mulPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrix_mulPfS_S_,@object # @_Z10matrix_mulPfS_S_
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPfS_S_
.p2align 3, 0x0
_Z10matrix_mulPfS_S_:
.quad _Z25__device_stub__matrix_mulPfS_S_
.size _Z10matrix_mulPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Matrix = %f "
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time = %f\n"
.size .L.str.1, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPfS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrix_mulPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(cufftComplex *c, cufftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(cufftComplex *c, cufftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(cufftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
cufftHandle plan;
cufftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
cudaMalloc(&gpu_c, sizeof(cufftComplex)*sizex*sizey);//note that gpu_c is 1D variable
cudaMalloc(&gpu_g, sizeof(cufftComplex)*sizex*sizey);
cudaMalloc(&gpu_dkx, sizeof(double));
cudaMalloc(&gpu_dky, sizeof(double));
cudaMemcpy(gpu_c, c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dkx, dkx, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dky, dky, sizeof(double), cudaMemcpyHostToDevice);
cufftPlan2d(&plan, sizex, sizey, CUFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_FORWARD);
cufftExecC2C(plan, gpu_g, gpu_g, CUFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_INVERSE);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
cudaMemcpy(c, gpu_c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
cufftDestroy(plan);
cudaFree(gpu_c);
cudaFree(gpu_g);
cudaFree(gpu_dkx);
cudaFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} | code for sm_80
Function : _Z8iterate3P6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fc800000001ff */
/*0090*/ LEA R3, R3, R0, 0x9 ; /* 0x0000000003037211 */
/* 0x000fcc00078e48ff */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ FMUL R4, R0, 3.814697265625e-06 ; /* 0x3680000000047820 */
/* 0x004fcc0000400000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8iterate2P6float2S0_PdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0060*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0080*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fc600078e00ff */
/*0090*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*00b0*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e680000002600 */
/*00c0*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00d0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fc400078e0200 */
/*00e0*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x002fc800078e0203 */
/*00f0*/ IMAD R14, R10, 0x200, R5 ; /* 0x000002000a0e7824 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fc800078e020f */
/*0110*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e020f */
/*0120*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R14.64+0x4], RZ ; /* 0x000004ff0e007986 */
/* 0x0001e8000c101904 */
/*0140*/ LDG.E R4, [R14.64] ; /* 0x000000040e047981 */
/* 0x000128000c1e1900 */
/*0150*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000f62000c1e1900 */
/*0160*/ ISETP.GE.AND P0, PT, R10.reuse, 0x100, PT ; /* 0x000001000a00780c */
/* 0x040fe20003f06270 */
/*0170*/ BSSY B0, 0x3f0 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*0180*/ IADD3 R11, R10, -0x200, RZ ; /* 0xfffffe000a0b7810 */
/* 0x000fc80007ffe0ff */
/*0190*/ SEL R12, R10, R11, !P0 ; /* 0x0000000b0a0c7207 */
/* 0x000fe40004000000 */
/*01a0*/ ISETP.GE.AND P0, PT, R5.reuse, 0x100, PT ; /* 0x000001000500780c */
/* 0x040fe40003f06270 */
/*01b0*/ IADD3 R10, R5.reuse, -0x200, RZ ; /* 0xfffffe00050a7810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ I2F.F64 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000ea40000201c00 */
/*01d0*/ SEL R16, R5, R10, !P0 ; /* 0x0000000a05107207 */
/* 0x000fcc0004000000 */
/*01e0*/ I2F.F64 R10, R16 ; /* 0x00000010000a7312 */
/* 0x000ee20000201c00 */
/*01f0*/ DMUL R8, R12, R8 ; /* 0x000000080c087228 */
/* 0x0042a40000000000 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x002fe400078e00ff */
/*0210*/ DMUL R6, R10, R6 ; /* 0x000000060a067228 */
/* 0x008fc80000000000 */
/*0220*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x004e4c0000000000 */
/*0230*/ DFMA R10, R6, R6, R8 ; /* 0x00000006060a722b */
/* 0x0022a40000000008 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x002fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff097424 */
/* 0x000fe400078e00ff */
/*0260*/ DADD R6, R10, R10 ; /* 0x000000000a067229 */
/* 0x004e4c000000000a */
/*0270*/ DMUL R6, R10, R6 ; /* 0x000000060a067228 */
/* 0x002e480000000000 */
/*0280*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x000fc80000000000 */
/*0290*/ DFMA R8, R6, c[0x2][0x0], R8 ; /* 0x0080000006087a2b */
/* 0x002e4c0000000008 */
/*02a0*/ MUFU.RCP64H R13, R9 ; /* 0x00000009000d7308 */
/* 0x002e640000001800 */
/*02b0*/ DFMA R6, -R8, R12, 1 ; /* 0x3ff000000806742b */
/* 0x002e0c000000010c */
/*02c0*/ DFMA R14, R6, R6, R6 ; /* 0x00000006060e722b */
/* 0x001e220000000006 */
/*02d0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x010fea0000201800 */
/*02e0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e06000000000c */
/*02f0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x020e660000201800 */
/*0300*/ DFMA R12, -R8, R14, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010e */
/*0310*/ DFMA R12, R14, R12, R14 ; /* 0x0000000c0e0c722b */
/* 0x001fc8000000000e */
/*0320*/ DFMA R6, -R10, R4, R6 ; /* 0x000000040a06722b */
/* 0x002e0c0000000106 */
/*0330*/ DMUL R10, R6, R12 ; /* 0x0000000c060a7228 */
/* 0x001e080000000000 */
/*0340*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0350*/ DFMA R4, -R8, R10, R6 ; /* 0x0000000a0804722b */
/* 0x001e0c0000000106 */
/*0360*/ DFMA R4, R12, R4, R10 ; /* 0x000000040c04722b */
/* 0x001e14000000000a */
/*0370*/ FFMA R10, RZ, R9, R5 ; /* 0x00000009ff0a7223 */
/* 0x001fca0000000005 */
/*0380*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0390*/ @P0 BRA P1, 0x3e0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03a0*/ MOV R0, 0x3c0 ; /* 0x000003c000007802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x420 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x000e240000301000 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0430*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0440*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0460*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0480*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*04a0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*04b0*/ BSSY B1, 0x9c0 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*04c0*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*04d0*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*04f0*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0500*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0510*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*0520*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*0530*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0540*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*0550*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*0560*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*0570*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0580*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0590*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*05a0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*05b0*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*05c0*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*05d0*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*05e0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*05f0*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0600*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*0610*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*0620*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0630*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0640*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0650*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0660*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0670*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0680*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0690*/ @P0 BRA 0x860 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*06c0*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*06d0*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*06e0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*06f0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0700*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0720*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0730*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0740*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0750*/ @P0 BRA 0x9b0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0760*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0770*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0780*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0790*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*07a0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*07b0*/ @!P0 BRA 0x9b0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*07d0*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*07f0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0800*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0810*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0820*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0830*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0840*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0850*/ BRA 0x9b0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0860*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0870*/ @P0 BRA 0x990 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0880*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0890*/ @P0 BRA 0x960 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*08a0*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*08b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*08d0*/ @!P0 BRA 0x9b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*08f0*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*0900*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0910*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0920*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0930*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0940*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0950*/ BRA 0x9b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0980*/ BRA 0x9b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*09a0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*09d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff61004007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8iterate1P6float2S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0090*/ LEA R0, R3, R0, 0x9 ; /* 0x0000000003007211 */
/* 0x000fca00078e48ff */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R4, R2.reuse, R2 ; /* 0x0000000202047221 */
/* 0x044fe40000000000 */
/*00d0*/ FADD R5, -R2, 1 ; /* 0x3f80000002057421 */
/* 0x000fe40000000100 */
/*00e0*/ FADD R7, -R4.reuse, 1 ; /* 0x3f80000004077421 */
/* 0x040fe40000000100 */
/*00f0*/ FMUL R6, R4, R5 ; /* 0x0000000504067220 */
/* 0x000fe40000400000 */
/*0100*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0110*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(cufftComplex *c, cufftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(cufftComplex *c, cufftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(cufftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
cufftHandle plan;
cufftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
cudaMalloc(&gpu_c, sizeof(cufftComplex)*sizex*sizey);//note that gpu_c is 1D variable
cudaMalloc(&gpu_g, sizeof(cufftComplex)*sizex*sizey);
cudaMalloc(&gpu_dkx, sizeof(double));
cudaMalloc(&gpu_dky, sizeof(double));
cudaMemcpy(gpu_c, c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dkx, dkx, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dky, dky, sizeof(double), cudaMemcpyHostToDevice);
cufftPlan2d(&plan, sizex, sizey, CUFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_FORWARD);
cufftExecC2C(plan, gpu_g, gpu_g, CUFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_INVERSE);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
cudaMemcpy(c, gpu_c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
cufftDestroy(plan);
cudaFree(gpu_c);
cudaFree(gpu_g);
cudaFree(gpu_dkx);
cudaFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} | .file "tmpxft_00176c43_00000000-6_2d_cahn_hillard_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB2080:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L4
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L4:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE2080:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
.type _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_, @function
_Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_:
.LFB2106:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8iterate1P6float2S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_, .-_Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
.globl _Z8iterate1P6float2S0_
.type _Z8iterate1P6float2S0_, @function
_Z8iterate1P6float2S0_:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z8iterate1P6float2S0_, .-_Z8iterate1P6float2S0_
.globl _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
.type _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_, @function
_Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_:
.LFB2108:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8iterate2P6float2S0_PdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_, .-_Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
.globl _Z8iterate2P6float2S0_PdS1_
.type _Z8iterate2P6float2S0_PdS1_, @function
_Z8iterate2P6float2S0_PdS1_:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z8iterate2P6float2S0_PdS1_, .-_Z8iterate2P6float2S0_PdS1_
.globl _Z33__device_stub__Z8iterate3P6float2P6float2
.type _Z33__device_stub__Z8iterate3P6float2P6float2, @function
_Z33__device_stub__Z8iterate3P6float2P6float2:
.LFB2110:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8iterate3P6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _Z33__device_stub__Z8iterate3P6float2P6float2, .-_Z33__device_stub__Z8iterate3P6float2P6float2
.globl _Z8iterate3P6float2
.type _Z8iterate3P6float2, @function
_Z8iterate3P6float2:
.LFB2111:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8iterate3P6float2P6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _Z8iterate3P6float2, .-_Z8iterate3P6float2
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "w"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string ".//output//order_parameter_000.vtk"
.align 8
.LC3:
.string "Can't open order_parameter_000.vtk file for writting\n"
.section .rodata.str1.1
.LC4:
.string "# vtk DataFile Version 3.0\n"
.LC5:
.string "Order Parameter data\n"
.LC6:
.string "ASCII\n"
.LC7:
.string "DATASET STRUCTURED_POINTS\n"
.LC8:
.string "DIMENSIONS %d %d 1\n"
.LC9:
.string "ORIGIN 0 0 0\n"
.LC10:
.string "SPACING 1 1 1\n"
.LC11:
.string "POINT_DATA %d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "SCALARS order_parameter double\n"
.section .rodata.str1.1
.LC13:
.string "LOOKUP_TABLE default\n"
.LC18:
.string "%f\n"
.LC19:
.string "%03d.vtk"
.section .rodata.str1.8
.align 8
.LC20:
.string "Can't open order_parameter_%03d.vtk file for writting\n"
.section .rodata.str1.1
.LC21:
.string "%lf\n"
.LC24:
.string "%f%%\n"
.LC26:
.string "time taken =%f\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -2097152(%rsp), %r11
.cfi_def_cfa 11, 2097208
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $264, %rsp
.cfi_def_cfa_offset 2097472
movq %fs:40, %rax
movq %rax, 2097400(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, (%rsp)
movabsq $8462391747554520878, %rax
movabsq $8243105135625973620, %rdx
movq %rax, 2097264(%rsp)
movq %rdx, 2097272(%rsp)
movabsq $8241992348308169842, %rax
movabsq $26865902857579873, %rdx
movq %rax, 2097276(%rsp)
movq %rdx, 2097284(%rsp)
movsd .LC0(%rip), %xmm0
movsd %xmm0, 56(%rsp)
movsd %xmm0, 64(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L51
.L31:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $512, %r8d
movl $512, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $262144, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 4192(%rsp), %rax
movq %rax, 8(%rsp)
leaq 2101344(%rsp), %r14
movq %rax, %r12
leaq .LC18(%rip), %r13
jmp .L32
.L51:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L52:
addq $4096, %r12
cmpq %r14, %r12
je .L34
.L32:
leaq -4096(%r12), %rbx
.L33:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC14(%rip), %xmm0
mulsd .LC15(%rip), %xmm0
addsd .LC16(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
movl $0x00000000, 4(%rbx)
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L33
jmp .L52
.L34:
movq %rbp, %rdi
call fclose@PLT
leaq 24(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $2097152, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 20(%rsp), %rdi
movl $41, %ecx
movl $512, %edx
movl $512, %esi
call cufftPlan2d@PLT
movl $32, 72(%rsp)
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $16, 84(%rsp)
movl $16, 88(%rsp)
movl $1, 92(%rsp)
movl $1, %r15d
jmp .L45
.L55:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
jmp .L35
.L56:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
jmp .L36
.L37:
movslq %r15d, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %r15d, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %r15d
je .L53
.L38:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC22(%rip), %xmm0
divsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r15d
cmpl $100001, %r15d
je .L54
.L45:
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L35:
movq 24(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movq 32(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L36:
movq 24(%rsp), %rsi
movl $1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movq 24(%rsp), %rdi
call _Z33__device_stub__Z8iterate3P6float2P6float2
jmp .L37
.L53:
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $2097152, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2097254(%rsp), %rbp
movl %r15d, %r8d
leaq .LC19(%rip), %rcx
movl $10, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 2097264(%rsp), %rsi
leaq 2097296(%rsp), %rbx
movl $100, %edx
movq %rbx, %rdi
call __strcat_chk@PLT
movl $100, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L57
.L39:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $512, %r8d
movl $512, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $262144, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rbp
leaq .LC21(%rip), %r13
.L40:
leaq -4096(%rbp), %rbx
.L41:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L41
addq $4096, %rbp
cmpq %r14, %rbp
jne .L40
movq %r12, %rdi
call fclose@PLT
movl $0, %ebx
leaq 2097296(%rsp), %rbp
jmp .L43
.L57:
movl %r15d, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L44:
movb $0, (%rbx,%rbp)
addq $1, %rbx
.L43:
movq %rbp, %rdi
call strlen@PLT
cmpq %rax, %rbx
jb .L44
jmp .L38
.L54:
movl 20(%rsp), %edi
call cufftDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
movq (%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC25(%rip), %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 2097400(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $2097416, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.section .rodata.str1.1
.LC27:
.string "_Z8iterate3P6float2"
.LC28:
.string "_Z8iterate2P6float2S0_PdS1_"
.LC29:
.string "_Z8iterate1P6float2S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2113:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate3P6float2(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate2P6float2S0_PdS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate1P6float2S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2113:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1065951739
.align 8
.LC14:
.long -4194304
.long 1105199103
.align 8
.LC15:
.long 0
.long 1071644672
.align 8
.LC16:
.long 0
.long 1070596096
.align 8
.LC22:
.long 0
.long 1079574528
.align 8
.LC23:
.long 0
.long 1090021888
.align 8
.LC25:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cufft.h>
#include "device_launch_parameters.h"
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(cufftComplex *c, cufftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(cufftComplex *c, cufftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(cufftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
cufftHandle plan;
cufftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
cudaMalloc(&gpu_c, sizeof(cufftComplex)*sizex*sizey);//note that gpu_c is 1D variable
cudaMalloc(&gpu_g, sizeof(cufftComplex)*sizex*sizey);
cudaMalloc(&gpu_dkx, sizeof(double));
cudaMalloc(&gpu_dky, sizeof(double));
cudaMemcpy(gpu_c, c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dkx, dkx, sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(gpu_dky, dky, sizeof(double), cudaMemcpyHostToDevice);
cufftPlan2d(&plan, sizex, sizey, CUFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_FORWARD);
cufftExecC2C(plan, gpu_g, gpu_g, CUFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
cufftExecC2C(plan, gpu_c, gpu_c, CUFFT_INVERSE);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
cudaMemcpy(c, gpu_c, sizeof(cufftComplex)*sizex*sizey, cudaMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
cufftDestroy(plan);
cudaFree(gpu_c);
cudaFree(gpu_g);
cudaFree(gpu_dkx);
cudaFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(hipfftComplex *c, hipfftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(hipfftComplex *c, hipfftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(hipfftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
hipfftHandle plan;
hipfftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
hipMalloc(&gpu_c, sizeof(hipfftComplex)*sizex*sizey);//note that gpu_c is 1D variable
hipMalloc(&gpu_g, sizeof(hipfftComplex)*sizex*sizey);
hipMalloc(&gpu_dkx, sizeof(double));
hipMalloc(&gpu_dky, sizeof(double));
hipMemcpy(gpu_c, c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyHostToDevice);
hipMemcpy(gpu_dkx, dkx, sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(gpu_dky, dky, sizeof(double), hipMemcpyHostToDevice);
hipfftPlan2d(&plan, sizex, sizey, HIPFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_FORWARD);
hipfftExecC2C(plan, gpu_g, gpu_g, HIPFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_BACKWARD);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
hipMemcpy(c, gpu_c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
hipfftDestroy(plan);
hipFree(gpu_c);
hipFree(gpu_g);
hipFree(gpu_dkx);
hipFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(hipfftComplex *c, hipfftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(hipfftComplex *c, hipfftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(hipfftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
hipfftHandle plan;
hipfftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
hipMalloc(&gpu_c, sizeof(hipfftComplex)*sizex*sizey);//note that gpu_c is 1D variable
hipMalloc(&gpu_g, sizeof(hipfftComplex)*sizex*sizey);
hipMalloc(&gpu_dkx, sizeof(double));
hipMalloc(&gpu_dky, sizeof(double));
hipMemcpy(gpu_c, c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyHostToDevice);
hipMemcpy(gpu_dkx, dkx, sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(gpu_dky, dky, sizeof(double), hipMemcpyHostToDevice);
hipfftPlan2d(&plan, sizex, sizey, HIPFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_FORWARD);
hipfftExecC2C(plan, gpu_g, gpu_g, HIPFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_BACKWARD);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
hipMemcpy(c, gpu_c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
hipfftDestroy(plan);
hipFree(gpu_c);
hipFree(gpu_g);
hipFree(gpu_dkx);
hipFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.globl _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 8
.type _Z8iterate1P15HIP_vector_typeIfLj2EES1_,@function
_Z8iterate1P15HIP_vector_typeIfLj2EES1_:
s_load_b32 s4, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_mul_i32 s15, s15, s5
s_mul_i32 s14, s14, s4
v_add_lshl_u32 v1, s15, v1, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v2, v2
v_sub_f32_e32 v4, 1.0, v2
v_fma_f32 v2, v2, -2.0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v4
v_mul_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8iterate1P15HIP_vector_typeIfLj2EES1_, .Lfunc_end0-_Z8iterate1P15HIP_vector_typeIfLj2EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.globl _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 8
.type _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@function
_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_:
s_load_b32 s2, s[0:1], 0x2c
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v3, 9, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[4:5], 0x0
s_load_b64 s[2:3], s[6:7], 0x0
global_store_b32 v[4:5], v6, off offset:4
global_store_b32 v[0:1], v6, off offset:4
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[0:1], off
v_add_nc_u32_e32 v0, 0xfffffe00, v3
v_cmp_gt_i32_e32 vcc_lo, 0x100, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v3 :: v_dual_add_nc_u32 v3, 0xfffffe00, v2
v_cmp_gt_i32_e32 vcc_lo, 0x100, v2
v_cvt_f64_i32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_cvt_f64_i32_e32 v[2:3], v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[0:1], s[2:3], v[0:1]
v_mul_f64 v[2:3], s[0:1], v[2:3]
s_mov_b32 s1, 0x3f50624d
s_mov_b32 s0, 0xd2f1a9fc
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[0:1]
v_fma_f64 v[0:1], v[2:3], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[0:1], v[0:1]
v_mul_f64 v[6:7], v[0:1], s[0:1]
v_mul_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], s[0:1], 1.0
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v8
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v9
v_fma_f64 v[2:3], -v[6:7], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[0:1], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[6:7], v[0:1], v[2:3]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[4:5], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, .Lfunc_end1-_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8iterate3P15HIP_vector_typeIfLj2EE
.globl _Z8iterate3P15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z8iterate3P15HIP_vector_typeIfLj2EE,@function
_Z8iterate3P15HIP_vector_typeIfLj2EE:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x36800000, v2
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate3P15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8iterate3P15HIP_vector_typeIfLj2EE, .Lfunc_end2-_Z8iterate3P15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate1P15HIP_vector_typeIfLj2EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate3P15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate3P15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //2d cahn hillard with initial condition as random noise using spectral with periodic boundary conditions
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#define sizex 512
#define sizey 512
#define dt 1.0e-3
#define PI 3.14159265358979323846
#define BLOCK_SIZE_X 32
#define BLOCK_SIZE_Y 32
#define NT 100000 //number of time steps
int iDivUp(int a, int b)
{
return (a % b != 0) ? (a / b + 1) : (a / b);
}
__global__ void iterate1(hipfftComplex *c, hipfftComplex *g)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
g[p].x = 2 * c[p].x*(1 - c[p].x)*(1 - 2 * c[p].x);
}
__global__ void iterate2(hipfftComplex *c, hipfftComplex *g, double *dkx, double *dky)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
double kx, ky;
if (i < sizex / 2)
kx = i * *dkx;
else
kx = (i - sizex) * *dkx;
if (j < sizey / 2)
ky = j * *dky;
else
ky = (j - sizey) * *dky;
int p = i + j * sizex;
c[p].y = 0;
g[p].y = 0;
c[p].x = (c[p].x - dt * (kx*kx + ky * ky)*g[p].x) / (1 + 2 * (kx*kx + ky*ky) * (kx*kx + ky*ky) * dt);
}
__global__ void iterate3(hipfftComplex *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int p = i + j * sizex;
c[p].x = c[p].x/(sizex*sizey);
c[p].y = 0;
}
int main()
{
clock_t t;
t = clock();
hipfftHandle plan;
hipfftComplex c[sizex][sizey], *gpu_c, *gpu_g;
char output_filename[100];
char str1[]=".//output//order_parameter_";
char str2[10];
double *dkx, *dky;
double *gpu_dkx, *gpu_dky;
double dkx0 = 2 * PI / sizex;
double dky0 = 2 * PI / sizey;
dkx = &dkx0;
dky = &dky0;
srand(time(0));
double random;
FILE *file0;
file0 = fopen(".//output//order_parameter_000.vtk", "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_000.vtk file for writting\n");
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int i = 0; i < sizex; i++)
{
for (int j = 0; j < sizey; j++)
{
random = rand();
random /= RAND_MAX;
random = 0.25 + 0.5* random;
c[i][j].x = random;
c[i][j].y = 0.0f;
fprintf(file0, "%f\n", c[i][j].x);
}
}
fclose(file0);
hipMalloc(&gpu_c, sizeof(hipfftComplex)*sizex*sizey);//note that gpu_c is 1D variable
hipMalloc(&gpu_g, sizeof(hipfftComplex)*sizex*sizey);
hipMalloc(&gpu_dkx, sizeof(double));
hipMalloc(&gpu_dky, sizeof(double));
hipMemcpy(gpu_c, c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyHostToDevice);
hipMemcpy(gpu_dkx, dkx, sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(gpu_dky, dky, sizeof(double), hipMemcpyHostToDevice);
hipfftPlan2d(&plan, sizex, sizey, HIPFFT_C2C);
dim3 dimBlock(BLOCK_SIZE_X, BLOCK_SIZE_Y);
dim3 dimGrid(iDivUp(sizex, BLOCK_SIZE_X), iDivUp(sizey, BLOCK_SIZE_Y));
for (int t = 1; t <= NT; t++)
{
iterate1<<< dimGrid, dimBlock >>>(gpu_c, gpu_g);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_FORWARD);
hipfftExecC2C(plan, gpu_g, gpu_g, HIPFFT_FORWARD);
iterate2<<< dimGrid, dimBlock >>>(gpu_c, gpu_g, gpu_dkx, gpu_dky);
hipfftExecC2C(plan, gpu_c, gpu_c, HIPFFT_BACKWARD);
iterate3<<< dimGrid, dimBlock >>>(gpu_c);
if(t%100 == 0)
{ //print order parameter in vtk file
hipMemcpy(c, gpu_c, sizeof(hipfftComplex)*sizex*sizey, hipMemcpyDeviceToHost);
sprintf(str2, "%03d.vtk", t);
strcat(output_filename, str1);
strcat(output_filename, str2);
FILE *file0;
file0 = fopen(output_filename, "w");
if (file0 == NULL)
{
printf("Can't open order_parameter_%03d.vtk file for writting\n", t);
}
fprintf(file0, "# vtk DataFile Version 3.0\n");
fprintf(file0, "Order Parameter data\n");
fprintf(file0, "ASCII\n");
fprintf(file0, "DATASET STRUCTURED_POINTS\n");
fprintf(file0, "DIMENSIONS %d %d 1\n", sizex, sizey);
fprintf(file0, "ORIGIN 0 0 0\n");
fprintf(file0, "SPACING 1 1 1\n");
fprintf(file0, "POINT_DATA %d\n", sizex*sizey);
fprintf(file0, "SCALARS order_parameter double\n");
fprintf(file0, "LOOKUP_TABLE default\n");
for (int x = 0; x < sizex; x++)
{
for (int y = 0; y < sizey; y++)
{
fprintf(file0, "%lf\n", c[x][y].x);
}
}
fclose(file0);
//printf("closed order_parameter_%03d.vtk file\n", t);
for(int k=0;k<strlen(output_filename);k++)
{
output_filename[k] = 0;
}
}
printf("%f%%\n", (double)t*100/NT);
}
hipfftDestroy(plan);
hipFree(gpu_c);
hipFree(gpu_g);
hipFree(gpu_dkx);
hipFree(gpu_dky);
t = clock() - t;
double timetaken = ((double)t) / CLOCKS_PER_SEC;
printf("time taken =%f\n", timetaken);
return 0;
} | .text
.file "2d_cahn_hillard_code.hip"
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end0:
.size _Z6iDivUpii, .Lfunc_end0-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_ # -- Begin function _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 4, 0x90
.type _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_,@function
_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_: # @_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_, .Lfunc_end1-_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_ # -- Begin function _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 4, 0x90
.type _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@function
_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_: # @_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, .Lfunc_end2-_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE # -- Begin function _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE,@function
_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE: # @_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE, .Lfunc_end3-_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.byte 46 # 0x2e
.byte 47 # 0x2f
.byte 47 # 0x2f
.byte 111 # 0x6f
.byte 117 # 0x75
.byte 116 # 0x74
.byte 112 # 0x70
.byte 117 # 0x75
.byte 116 # 0x74
.byte 47 # 0x2f
.byte 47 # 0x2f
.byte 111 # 0x6f
.byte 114 # 0x72
.byte 100 # 0x64
.byte 101 # 0x65
.byte 114 # 0x72
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_2:
.quad 0x3fe0000000000000 # double 0.5
.LCPI4_3:
.quad 0x3fd0000000000000 # double 0.25
.LCPI4_4:
.quad 0x3ff0000000000000 # double 1
.LCPI4_5:
.quad 0x4059000000000000 # double 100
.LCPI4_6:
.quad 0x40f86a0000000000 # double 1.0E+5
.LCPI4_7:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2097528, %rsp # imm = 0x200178
.cfi_def_cfa_offset 2097584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 168(%rsp) # 8-byte Spill
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [46,47,47,111,117,116,112,117,116,47,47,111,114,100,101,114]
movaps %xmm0, 208(%rsp)
movabsq $8387230146345660511, %rax # imm = 0x74656D617261705F
movq %rax, 224(%rsp)
movl $6255205, 232(%rsp) # imm = 0x5F7265
movabsq $4578227859533081880, %rax # imm = 0x3F8921FB54442D18
movq %rax, 184(%rsp)
movq %rax, 176(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_2:
movl $.L.str.3, %edi
movl $27, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.4, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.6, %edi
movl $26, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
xorl %r14d, %r14d
movl $.L.str.7, %esi
movq %rbx, %rdi
movl $512, %edx # imm = 0x200
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq fprintf
movl $.L.str.8, %edi
movl $13, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %edi
movl $14, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $262144, %edx # imm = 0x40000
xorl %eax, %eax
callq fprintf
movl $.L.str.11, %edi
movl $31, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.12, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
leaq 372(%rsp), %r15
.p2align 4, 0x90
.LBB4_3: # %.preheader111
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_1(%rip), %xmm0
mulsd .LCPI4_2(%rip), %xmm0
addsd .LCPI4_3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%r15,%r12,8)
movl $0, (%r15,%r12,8)
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
incq %r14
addq $4096, %r15 # imm = 0x1000
cmpq $512, %r14 # imm = 0x200
jne .LBB4_3
# %bb.6:
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $68719476752, %r15 # imm = 0x1000000010
movq %rbx, %rdi
callq fclose
leaq 8(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 104(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 368(%rsp), %rsi
movl $1, %ebp
movl $2097152, %edx # imm = 0x200000
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp), %rdi
leaq 184(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
movl $41, %ecx
callq hipfftPlan2d
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
leaq 88(%rsp), %r13
movsd %xmm0, 96(%rsp) # 8-byte Spill
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_23: # %.loopexit
# in Loop: Header=BB4_7 Depth=1
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI4_5(%rip), %xmm0
divsd .LCPI4_6(%rip), %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_4(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
incl %ebp
cmpl $100001, %ebp # imm = 0x186A1
je .LBB4_24
.LBB4_7: # =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
# Child Loop BB4_18 Depth 3
# Child Loop BB4_22 Depth 2
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 32(%rsp)
movq %r13, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %edi
leaq 128(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
movq 80(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq 80(%rsp), %rdi
movq 72(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 32(%rsp)
movq %rdx, 16(%rsp)
movq %rsi, 120(%rsp)
movq %r13, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %edi
leaq 128(%rsp), %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_11: # in Loop: Header=BB4_7 Depth=1
movq 80(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $1, %ecx
callq hipfftExecC2C
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_7 Depth=1
imull $-1030792151, %ebp, %eax # imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
leaq 256(%rsp), %r12
ja .LBB4_23
# %bb.14: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
leaq 368(%rsp), %r14
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.14, %esi
leaq 246(%rsp), %rbx
movq %rbx, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq sprintf
movq %r12, %rdi
leaq 208(%rsp), %rsi
callq strcat
movq %r12, %rdi
movq %rbx, %rsi
callq strcat
movl $.L.str.1, %esi
movq %r12, %rdi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB4_16
# %bb.15: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.15, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
.LBB4_16: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.3, %edi
movl $27, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.4, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.6, %edi
movl $26, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.7, %esi
movq %rbx, %rdi
movl $512, %edx # imm = 0x200
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq fprintf
movl $.L.str.8, %edi
movl $13, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %edi
movl $14, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $262144, %edx # imm = 0x40000
xorl %eax, %eax
callq fprintf
movl $.L.str.11, %edi
movl $31, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.12, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movq %r14, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_17: # %.preheader
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_18 Depth 3
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB4_18
# %bb.19: # in Loop: Header=BB4_17 Depth=2
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $512, %r14 # imm = 0x200
jne .LBB4_17
# %bb.20: # in Loop: Header=BB4_7 Depth=1
movq %rbx, %rdi
callq fclose
cmpb $0, 256(%rsp)
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $68719476752, %r15 # imm = 0x1000000010
leaq 88(%rsp), %r13
leaq 256(%rsp), %r12
je .LBB4_23
# %bb.21: # %.lr.ph.preheader
# in Loop: Header=BB4_7 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_22: # %.lr.ph
# Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
movb $0, 256(%rsp,%rbx)
incq %rbx
movq %r12, %rdi
callq strlen
cmpq %rbx, %rax
ja .LBB4_22
jmp .LBB4_23
.LBB4_24:
movq 80(%rsp), %rdi
callq hipfftDestroy
movq 8(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
callq clock
subq 168(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_7(%rip), %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $2097528, %rsp # imm = 0x200178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8iterate1P15HIP_vector_typeIfLj2EES1_,@object # @_Z8iterate1P15HIP_vector_typeIfLj2EES1_
.section .rodata,"a",@progbits
.globl _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 3, 0x0
_Z8iterate1P15HIP_vector_typeIfLj2EES1_:
.quad _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.size _Z8iterate1P15HIP_vector_typeIfLj2EES1_, 8
.type _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@object # @_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.globl _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 3, 0x0
_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_:
.quad _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.size _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, 8
.type _Z8iterate3P15HIP_vector_typeIfLj2EE,@object # @_Z8iterate3P15HIP_vector_typeIfLj2EE
.globl _Z8iterate3P15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z8iterate3P15HIP_vector_typeIfLj2EE:
.quad _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.size _Z8iterate3P15HIP_vector_typeIfLj2EE, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ".//output//order_parameter_000.vtk"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "# vtk DataFile Version 3.0\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Order Parameter data\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ASCII\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "DATASET STRUCTURED_POINTS\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "DIMENSIONS %d %d 1\n"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ORIGIN 0 0 0\n"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SPACING 1 1 1\n"
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "POINT_DATA %d\n"
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "SCALARS order_parameter double\n"
.size .L.str.11, 32
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "LOOKUP_TABLE default\n"
.size .L.str.12, 22
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f\n"
.size .L.str.13, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%03d.vtk"
.size .L.str.14, 9
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Can't open order_parameter_%03d.vtk file for writting\n"
.size .L.str.15, 55
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%lf\n"
.size .L.str.16, 5
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f%%\n"
.size .L.str.17, 6
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "time taken =%f\n"
.size .L.str.18, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8iterate1P15HIP_vector_typeIfLj2EES1_"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_"
.size .L__unnamed_2, 45
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8iterate3P15HIP_vector_typeIfLj2EE"
.size .L__unnamed_3, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Can't open order_parameter_000.vtk file for writting"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.addrsig_sym _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.addrsig_sym _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.addrsig_sym _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.addrsig_sym _Z8iterate3P15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8iterate3P6float2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fc800000001ff */
/*0090*/ LEA R3, R3, R0, 0x9 ; /* 0x0000000003037211 */
/* 0x000fcc00078e48ff */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ FMUL R4, R0, 3.814697265625e-06 ; /* 0x3680000000047820 */
/* 0x004fcc0000400000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8iterate2P6float2S0_PdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0060*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0080*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fc600078e00ff */
/*0090*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*00b0*/ S2R R10, SR_CTAID.Y ; /* 0x00000000000a7919 */
/* 0x000e680000002600 */
/*00c0*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00d0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fc400078e0200 */
/*00e0*/ IMAD R10, R10, c[0x0][0x4], R3 ; /* 0x000001000a0a7a24 */
/* 0x002fc800078e0203 */
/*00f0*/ IMAD R14, R10, 0x200, R5 ; /* 0x000002000a0e7824 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R2, R14, R15, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fc800078e020f */
/*0110*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e020f */
/*0120*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R14.64+0x4], RZ ; /* 0x000004ff0e007986 */
/* 0x0001e8000c101904 */
/*0140*/ LDG.E R4, [R14.64] ; /* 0x000000040e047981 */
/* 0x000128000c1e1900 */
/*0150*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000f62000c1e1900 */
/*0160*/ ISETP.GE.AND P0, PT, R10.reuse, 0x100, PT ; /* 0x000001000a00780c */
/* 0x040fe20003f06270 */
/*0170*/ BSSY B0, 0x3f0 ; /* 0x0000027000007945 */
/* 0x000fe20003800000 */
/*0180*/ IADD3 R11, R10, -0x200, RZ ; /* 0xfffffe000a0b7810 */
/* 0x000fc80007ffe0ff */
/*0190*/ SEL R12, R10, R11, !P0 ; /* 0x0000000b0a0c7207 */
/* 0x000fe40004000000 */
/*01a0*/ ISETP.GE.AND P0, PT, R5.reuse, 0x100, PT ; /* 0x000001000500780c */
/* 0x040fe40003f06270 */
/*01b0*/ IADD3 R10, R5.reuse, -0x200, RZ ; /* 0xfffffe00050a7810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ I2F.F64 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000ea40000201c00 */
/*01d0*/ SEL R16, R5, R10, !P0 ; /* 0x0000000a05107207 */
/* 0x000fcc0004000000 */
/*01e0*/ I2F.F64 R10, R16 ; /* 0x00000010000a7312 */
/* 0x000ee20000201c00 */
/*01f0*/ DMUL R8, R12, R8 ; /* 0x000000080c087228 */
/* 0x0042a40000000000 */
/*0200*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x002fe400078e00ff */
/*0210*/ DMUL R6, R10, R6 ; /* 0x000000060a067228 */
/* 0x008fc80000000000 */
/*0220*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x004e4c0000000000 */
/*0230*/ DFMA R10, R6, R6, R8 ; /* 0x00000006060a722b */
/* 0x0022a40000000008 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x002fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff097424 */
/* 0x000fe400078e00ff */
/*0260*/ DADD R6, R10, R10 ; /* 0x000000000a067229 */
/* 0x004e4c000000000a */
/*0270*/ DMUL R6, R10, R6 ; /* 0x000000060a067228 */
/* 0x002e480000000000 */
/*0280*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x000fc80000000000 */
/*0290*/ DFMA R8, R6, c[0x2][0x0], R8 ; /* 0x0080000006087a2b */
/* 0x002e4c0000000008 */
/*02a0*/ MUFU.RCP64H R13, R9 ; /* 0x00000009000d7308 */
/* 0x002e640000001800 */
/*02b0*/ DFMA R6, -R8, R12, 1 ; /* 0x3ff000000806742b */
/* 0x002e0c000000010c */
/*02c0*/ DFMA R14, R6, R6, R6 ; /* 0x00000006060e722b */
/* 0x001e220000000006 */
/*02d0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x010fea0000201800 */
/*02e0*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e06000000000c */
/*02f0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x020e660000201800 */
/*0300*/ DFMA R12, -R8, R14, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000010e */
/*0310*/ DFMA R12, R14, R12, R14 ; /* 0x0000000c0e0c722b */
/* 0x001fc8000000000e */
/*0320*/ DFMA R6, -R10, R4, R6 ; /* 0x000000040a06722b */
/* 0x002e0c0000000106 */
/*0330*/ DMUL R10, R6, R12 ; /* 0x0000000c060a7228 */
/* 0x001e080000000000 */
/*0340*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe40003f2e200 */
/*0350*/ DFMA R4, -R8, R10, R6 ; /* 0x0000000a0804722b */
/* 0x001e0c0000000106 */
/*0360*/ DFMA R4, R12, R4, R10 ; /* 0x000000040c04722b */
/* 0x001e14000000000a */
/*0370*/ FFMA R10, RZ, R9, R5 ; /* 0x00000009ff0a7223 */
/* 0x001fca0000000005 */
/*0380*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0390*/ @P0 BRA P1, 0x3e0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*03a0*/ MOV R0, 0x3c0 ; /* 0x000003c000007802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x420 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*03d0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x000e240000301000 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0430*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0440*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0460*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0470*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0480*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*04a0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*04b0*/ BSSY B1, 0x9c0 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*04c0*/ LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f7812 */
/* 0x000fc600078ec0ff */
/*04d0*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*04f0*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0500*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0510*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*0520*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*0530*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0540*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*0550*/ LOP3.LUT R11, R11, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef807 */
/*0560*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef807 */
/*0570*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0580*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0590*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*05a0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*05b0*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*05c0*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*05d0*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*05e0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*05f0*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0600*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*0610*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*0620*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0630*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0640*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0650*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0660*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0670*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0680*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0690*/ @P0 BRA 0x860 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R7, PT ; /* 0x000000070c00720c */
/* 0x040fe20003f06070 */
/*06c0*/ IMAD.IADD R6, R12, 0x1, -R7 ; /* 0x000000010c067824 */
/* 0x000fc600078e0a07 */
/*06d0*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*06e0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*06f0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0700*/ IMAD.IADD R16, R6, 0x1, -R13 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0d */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0720*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0730*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0740*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0750*/ @P0 BRA 0x9b0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0760*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0770*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0780*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0790*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*07a0*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*07b0*/ @!P0 BRA 0x9b0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*07d0*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*07e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*07f0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0800*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0810*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0820*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0830*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0840*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0850*/ BRA 0x9b0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0860*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0870*/ @P0 BRA 0x990 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0880*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0890*/ @P0 BRA 0x960 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*08a0*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*08b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*08d0*/ @!P0 BRA 0x9b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*08f0*/ LOP3.LUT R13, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070d7812 */
/* 0x000fe400078e4809 */
/*0900*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0910*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0920*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0930*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0940*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0950*/ BRA 0x9b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0980*/ BRA 0x9b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*09a0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*09d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff61004007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8iterate1P6float2S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0090*/ LEA R0, R3, R0, 0x9 ; /* 0x0000000003007211 */
/* 0x000fca00078e48ff */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R4, R2.reuse, R2 ; /* 0x0000000202047221 */
/* 0x044fe40000000000 */
/*00d0*/ FADD R5, -R2, 1 ; /* 0x3f80000002057421 */
/* 0x000fe40000000100 */
/*00e0*/ FADD R7, -R4.reuse, 1 ; /* 0x3f80000004077421 */
/* 0x040fe40000000100 */
/*00f0*/ FMUL R6, R4, R5 ; /* 0x0000000504067220 */
/* 0x000fe40000400000 */
/*0100*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0110*/ FMUL R7, R6, R7 ; /* 0x0000000706077220 */
/* 0x000fca0000400000 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.globl _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 8
.type _Z8iterate1P15HIP_vector_typeIfLj2EES1_,@function
_Z8iterate1P15HIP_vector_typeIfLj2EES1_:
s_load_b32 s4, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_mul_i32 s15, s15, s5
s_mul_i32 s14, s14, s4
v_add_lshl_u32 v1, s15, v1, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v2, v2
v_sub_f32_e32 v4, 1.0, v2
v_fma_f32 v2, v2, -2.0, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v4
v_mul_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8iterate1P15HIP_vector_typeIfLj2EES1_, .Lfunc_end0-_Z8iterate1P15HIP_vector_typeIfLj2EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.globl _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 8
.type _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@function
_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_:
s_load_b32 s2, s[0:1], 0x2c
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v3, 9, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[4:5], 0x0
s_load_b64 s[2:3], s[6:7], 0x0
global_store_b32 v[4:5], v6, off offset:4
global_store_b32 v[0:1], v6, off offset:4
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[0:1], off
v_add_nc_u32_e32 v0, 0xfffffe00, v3
v_cmp_gt_i32_e32 vcc_lo, 0x100, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v3 :: v_dual_add_nc_u32 v3, 0xfffffe00, v2
v_cmp_gt_i32_e32 vcc_lo, 0x100, v2
v_cvt_f64_i32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_cvt_f64_i32_e32 v[2:3], v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[0:1], s[2:3], v[0:1]
v_mul_f64 v[2:3], s[0:1], v[2:3]
s_mov_b32 s1, 0x3f50624d
s_mov_b32 s0, 0xd2f1a9fc
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], v[0:1]
v_fma_f64 v[0:1], v[2:3], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[0:1], v[0:1]
v_mul_f64 v[6:7], v[0:1], s[0:1]
v_mul_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], s[0:1], 1.0
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v8
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v9
v_fma_f64 v[2:3], -v[6:7], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], v[2:3]
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[0:1], v[2:3]
v_mul_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[6:7], v[0:1], v[2:3]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[4:5], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, .Lfunc_end1-_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8iterate3P15HIP_vector_typeIfLj2EE
.globl _Z8iterate3P15HIP_vector_typeIfLj2EE
.p2align 8
.type _Z8iterate3P15HIP_vector_typeIfLj2EE,@function
_Z8iterate3P15HIP_vector_typeIfLj2EE:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s15, s15, s3
s_mul_i32 s14, s14, s2
v_add_lshl_u32 v1, s15, v1, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x36800000, v2
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8iterate3P15HIP_vector_typeIfLj2EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8iterate3P15HIP_vector_typeIfLj2EE, .Lfunc_end2-_Z8iterate3P15HIP_vector_typeIfLj2EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate1P15HIP_vector_typeIfLj2EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8iterate3P15HIP_vector_typeIfLj2EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8iterate3P15HIP_vector_typeIfLj2EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00176c43_00000000-6_2d_cahn_hillard_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB2080:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L4
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L4:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE2080:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
.type _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_, @function
_Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_:
.LFB2106:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8iterate1P6float2S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_, .-_Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
.globl _Z8iterate1P6float2S0_
.type _Z8iterate1P6float2S0_, @function
_Z8iterate1P6float2S0_:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z8iterate1P6float2S0_, .-_Z8iterate1P6float2S0_
.globl _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
.type _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_, @function
_Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_:
.LFB2108:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8iterate2P6float2S0_PdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_, .-_Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
.globl _Z8iterate2P6float2S0_PdS1_
.type _Z8iterate2P6float2S0_PdS1_, @function
_Z8iterate2P6float2S0_PdS1_:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z8iterate2P6float2S0_PdS1_, .-_Z8iterate2P6float2S0_PdS1_
.globl _Z33__device_stub__Z8iterate3P6float2P6float2
.type _Z33__device_stub__Z8iterate3P6float2P6float2, @function
_Z33__device_stub__Z8iterate3P6float2P6float2:
.LFB2110:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8iterate3P6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _Z33__device_stub__Z8iterate3P6float2P6float2, .-_Z33__device_stub__Z8iterate3P6float2P6float2
.globl _Z8iterate3P6float2
.type _Z8iterate3P6float2, @function
_Z8iterate3P6float2:
.LFB2111:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8iterate3P6float2P6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _Z8iterate3P6float2, .-_Z8iterate3P6float2
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "w"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string ".//output//order_parameter_000.vtk"
.align 8
.LC3:
.string "Can't open order_parameter_000.vtk file for writting\n"
.section .rodata.str1.1
.LC4:
.string "# vtk DataFile Version 3.0\n"
.LC5:
.string "Order Parameter data\n"
.LC6:
.string "ASCII\n"
.LC7:
.string "DATASET STRUCTURED_POINTS\n"
.LC8:
.string "DIMENSIONS %d %d 1\n"
.LC9:
.string "ORIGIN 0 0 0\n"
.LC10:
.string "SPACING 1 1 1\n"
.LC11:
.string "POINT_DATA %d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "SCALARS order_parameter double\n"
.section .rodata.str1.1
.LC13:
.string "LOOKUP_TABLE default\n"
.LC18:
.string "%f\n"
.LC19:
.string "%03d.vtk"
.section .rodata.str1.8
.align 8
.LC20:
.string "Can't open order_parameter_%03d.vtk file for writting\n"
.section .rodata.str1.1
.LC21:
.string "%lf\n"
.LC24:
.string "%f%%\n"
.LC26:
.string "time taken =%f\n"
.text
.globl main
.type main, @function
main:
.LFB2081:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -2097152(%rsp), %r11
.cfi_def_cfa 11, 2097208
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $264, %rsp
.cfi_def_cfa_offset 2097472
movq %fs:40, %rax
movq %rax, 2097400(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, (%rsp)
movabsq $8462391747554520878, %rax
movabsq $8243105135625973620, %rdx
movq %rax, 2097264(%rsp)
movq %rdx, 2097272(%rsp)
movabsq $8241992348308169842, %rax
movabsq $26865902857579873, %rdx
movq %rax, 2097276(%rsp)
movq %rdx, 2097284(%rsp)
movsd .LC0(%rip), %xmm0
movsd %xmm0, 56(%rsp)
movsd %xmm0, 64(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L51
.L31:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $512, %r8d
movl $512, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $262144, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 4192(%rsp), %rax
movq %rax, 8(%rsp)
leaq 2101344(%rsp), %r14
movq %rax, %r12
leaq .LC18(%rip), %r13
jmp .L32
.L51:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L31
.L52:
addq $4096, %r12
cmpq %r14, %r12
je .L34
.L32:
leaq -4096(%r12), %rbx
.L33:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC14(%rip), %xmm0
mulsd .LC15(%rip), %xmm0
addsd .LC16(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
movl $0x00000000, 4(%rbx)
cvtss2sd %xmm0, %xmm0
movq %r13, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L33
jmp .L52
.L34:
movq %rbp, %rdi
call fclose@PLT
leaq 24(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $2097152, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 20(%rsp), %rdi
movl $41, %ecx
movl $512, %edx
movl $512, %esi
call cufftPlan2d@PLT
movl $32, 72(%rsp)
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $16, 84(%rsp)
movl $16, 88(%rsp)
movl $1, 92(%rsp)
movl $1, %r15d
jmp .L45
.L55:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z8iterate1P6float2S0_P6float2S0_
jmp .L35
.L56:
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z8iterate2P6float2S0_PdS1_P6float2S0_PdS1_
jmp .L36
.L37:
movslq %r15d, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %r15d, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %r15d
je .L53
.L38:
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC22(%rip), %xmm0
divsd .LC23(%rip), %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %r15d
cmpl $100001, %r15d
je .L54
.L45:
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L35:
movq 24(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movq 32(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L36:
movq 24(%rsp), %rsi
movl $1, %ecx
movq %rsi, %rdx
movl 20(%rsp), %edi
call cufftExecC2C@PLT
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movq 24(%rsp), %rdi
call _Z33__device_stub__Z8iterate3P6float2P6float2
jmp .L37
.L53:
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $2097152, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2097254(%rsp), %rbp
movl %r15d, %r8d
leaq .LC19(%rip), %rcx
movl $10, %edx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 2097264(%rsp), %rsi
leaq 2097296(%rsp), %rbx
movl $100, %edx
movq %rbx, %rdi
call __strcat_chk@PLT
movl $100, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call __strcat_chk@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
je .L57
.L39:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $512, %r8d
movl $512, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $262144, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 8(%rsp), %rbp
leaq .LC21(%rip), %r13
.L40:
leaq -4096(%rbp), %rbx
.L41:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L41
addq $4096, %rbp
cmpq %r14, %rbp
jne .L40
movq %r12, %rdi
call fclose@PLT
movl $0, %ebx
leaq 2097296(%rsp), %rbp
jmp .L43
.L57:
movl %r15d, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L44:
movb $0, (%rbx,%rbp)
addq $1, %rbx
.L43:
movq %rbp, %rdi
call strlen@PLT
cmpq %rax, %rbx
jb .L44
jmp .L38
.L54:
movl 20(%rsp), %edi
call cufftDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
movq (%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC25(%rip), %xmm0
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 2097400(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $2097416, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size main, .-main
.section .rodata.str1.1
.LC27:
.string "_Z8iterate3P6float2"
.LC28:
.string "_Z8iterate2P6float2S0_PdS1_"
.LC29:
.string "_Z8iterate1P6float2S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2113:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate3P6float2(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate2P6float2S0_PdS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z8iterate1P6float2S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2113:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1065951739
.align 8
.LC14:
.long -4194304
.long 1105199103
.align 8
.LC15:
.long 0
.long 1071644672
.align 8
.LC16:
.long 0
.long 1070596096
.align 8
.LC22:
.long 0
.long 1079574528
.align 8
.LC23:
.long 0
.long 1090021888
.align 8
.LC25:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2d_cahn_hillard_code.hip"
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end0:
.size _Z6iDivUpii, .Lfunc_end0-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_ # -- Begin function _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 4, 0x90
.type _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_,@function
_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_: # @_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_, .Lfunc_end1-_Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_ # -- Begin function _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 4, 0x90
.type _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@function
_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_: # @_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, .Lfunc_end2-_Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE # -- Begin function _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE,@function
_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE: # @_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE, .Lfunc_end3-_Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.byte 46 # 0x2e
.byte 47 # 0x2f
.byte 47 # 0x2f
.byte 111 # 0x6f
.byte 117 # 0x75
.byte 116 # 0x74
.byte 112 # 0x70
.byte 117 # 0x75
.byte 116 # 0x74
.byte 47 # 0x2f
.byte 47 # 0x2f
.byte 111 # 0x6f
.byte 114 # 0x72
.byte 100 # 0x64
.byte 101 # 0x65
.byte 114 # 0x72
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_2:
.quad 0x3fe0000000000000 # double 0.5
.LCPI4_3:
.quad 0x3fd0000000000000 # double 0.25
.LCPI4_4:
.quad 0x3ff0000000000000 # double 1
.LCPI4_5:
.quad 0x4059000000000000 # double 100
.LCPI4_6:
.quad 0x40f86a0000000000 # double 1.0E+5
.LCPI4_7:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2097528, %rsp # imm = 0x200178
.cfi_def_cfa_offset 2097584
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 168(%rsp) # 8-byte Spill
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [46,47,47,111,117,116,112,117,116,47,47,111,114,100,101,114]
movaps %xmm0, 208(%rsp)
movabsq $8387230146345660511, %rax # imm = 0x74656D617261705F
movq %rax, 224(%rsp)
movl $6255205, 232(%rsp) # imm = 0x5F7265
movabsq $4578227859533081880, %rax # imm = 0x3F8921FB54442D18
movq %rax, 184(%rsp)
movq %rax, 176(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB4_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_2:
movl $.L.str.3, %edi
movl $27, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.4, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.6, %edi
movl $26, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
xorl %r14d, %r14d
movl $.L.str.7, %esi
movq %rbx, %rdi
movl $512, %edx # imm = 0x200
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq fprintf
movl $.L.str.8, %edi
movl $13, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %edi
movl $14, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $262144, %edx # imm = 0x40000
xorl %eax, %eax
callq fprintf
movl $.L.str.11, %edi
movl $31, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.12, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
leaq 372(%rsp), %r15
.p2align 4, 0x90
.LBB4_3: # %.preheader111
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_1(%rip), %xmm0
mulsd .LCPI4_2(%rip), %xmm0
addsd .LCPI4_3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%r15,%r12,8)
movl $0, (%r15,%r12,8)
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
incq %r14
addq $4096, %r15 # imm = 0x1000
cmpq $512, %r14 # imm = 0x200
jne .LBB4_3
# %bb.6:
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $68719476752, %r15 # imm = 0x1000000010
movq %rbx, %rdi
callq fclose
leaq 8(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 72(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 104(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 368(%rsp), %rsi
movl $1, %ebp
movl $2097152, %edx # imm = 0x200000
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp), %rdi
leaq 184(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
movl $41, %ecx
callq hipfftPlan2d
movsd .LCPI4_4(%rip), %xmm0 # xmm0 = mem[0],zero
leaq 88(%rsp), %r13
movsd %xmm0, 96(%rsp) # 8-byte Spill
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_23: # %.loopexit
# in Loop: Header=BB4_7 Depth=1
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI4_5(%rip), %xmm0
divsd .LCPI4_6(%rip), %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd .LCPI4_4(%rip), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
incl %ebp
cmpl $100001, %ebp # imm = 0x186A1
je .LBB4_24
.LBB4_7: # =>This Loop Header: Depth=1
# Child Loop BB4_17 Depth 2
# Child Loop BB4_18 Depth 3
# Child Loop BB4_22 Depth 2
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq 72(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 32(%rsp)
movq %r13, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %edi
leaq 128(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
movq 80(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq 80(%rsp), %rdi
movq 72(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_11
# %bb.10: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq 72(%rsp), %rcx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 32(%rsp)
movq %rdx, 16(%rsp)
movq %rsi, 120(%rsp)
movq %r13, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %edi
leaq 128(%rsp), %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_11: # in Loop: Header=BB4_7 Depth=1
movq 80(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $1, %ecx
callq hipfftExecC2C
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 128(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %r13, %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13: # in Loop: Header=BB4_7 Depth=1
imull $-1030792151, %ebp, %eax # imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
leaq 256(%rsp), %r12
ja .LBB4_23
# %bb.14: # in Loop: Header=BB4_7 Depth=1
movq 8(%rsp), %rsi
movl $2097152, %edx # imm = 0x200000
leaq 368(%rsp), %r14
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.14, %esi
leaq 246(%rsp), %rbx
movq %rbx, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq sprintf
movq %r12, %rdi
leaq 208(%rsp), %rsi
callq strcat
movq %r12, %rdi
movq %rbx, %rsi
callq strcat
movl $.L.str.1, %esi
movq %r12, %rdi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB4_16
# %bb.15: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.15, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
.LBB4_16: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.3, %edi
movl $27, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.4, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.5, %edi
movl $6, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.6, %edi
movl $26, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.7, %esi
movq %rbx, %rdi
movl $512, %edx # imm = 0x200
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq fprintf
movl $.L.str.8, %edi
movl $13, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.9, %edi
movl $14, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.10, %esi
movq %rbx, %rdi
movl $262144, %edx # imm = 0x40000
xorl %eax, %eax
callq fprintf
movl $.L.str.11, %edi
movl $31, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movl $.L.str.12, %edi
movl $21, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
movq %r14, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_17: # %.preheader
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_18 Depth 3
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_17 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB4_18
# %bb.19: # in Loop: Header=BB4_17 Depth=2
incq %r14
addq $4096, %r12 # imm = 0x1000
cmpq $512, %r14 # imm = 0x200
jne .LBB4_17
# %bb.20: # in Loop: Header=BB4_7 Depth=1
movq %rbx, %rdi
callq fclose
cmpb $0, 256(%rsp)
movabsq $137438953504, %r14 # imm = 0x2000000020
movabsq $68719476752, %r15 # imm = 0x1000000010
leaq 88(%rsp), %r13
leaq 256(%rsp), %r12
je .LBB4_23
# %bb.21: # %.lr.ph.preheader
# in Loop: Header=BB4_7 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_22: # %.lr.ph
# Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
movb $0, 256(%rsp,%rbx)
incq %rbx
movq %r12, %rdi
callq strlen
cmpq %rbx, %rax
ja .LBB4_22
jmp .LBB4_23
.LBB4_24:
movq 80(%rsp), %rdi
callq hipfftDestroy
movq 8(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
callq clock
subq 168(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI4_7(%rip), %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $2097528, %rsp # imm = 0x200178
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate1P15HIP_vector_typeIfLj2EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8iterate3P15HIP_vector_typeIfLj2EE, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8iterate1P15HIP_vector_typeIfLj2EES1_,@object # @_Z8iterate1P15HIP_vector_typeIfLj2EES1_
.section .rodata,"a",@progbits
.globl _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.p2align 3, 0x0
_Z8iterate1P15HIP_vector_typeIfLj2EES1_:
.quad _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.size _Z8iterate1P15HIP_vector_typeIfLj2EES1_, 8
.type _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_,@object # @_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.globl _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.p2align 3, 0x0
_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_:
.quad _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.size _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_, 8
.type _Z8iterate3P15HIP_vector_typeIfLj2EE,@object # @_Z8iterate3P15HIP_vector_typeIfLj2EE
.globl _Z8iterate3P15HIP_vector_typeIfLj2EE
.p2align 3, 0x0
_Z8iterate3P15HIP_vector_typeIfLj2EE:
.quad _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.size _Z8iterate3P15HIP_vector_typeIfLj2EE, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ".//output//order_parameter_000.vtk"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "# vtk DataFile Version 3.0\n"
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Order Parameter data\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ASCII\n"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "DATASET STRUCTURED_POINTS\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "DIMENSIONS %d %d 1\n"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ORIGIN 0 0 0\n"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "SPACING 1 1 1\n"
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "POINT_DATA %d\n"
.size .L.str.10, 15
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "SCALARS order_parameter double\n"
.size .L.str.11, 32
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "LOOKUP_TABLE default\n"
.size .L.str.12, 22
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f\n"
.size .L.str.13, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%03d.vtk"
.size .L.str.14, 9
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Can't open order_parameter_%03d.vtk file for writting\n"
.size .L.str.15, 55
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%lf\n"
.size .L.str.16, 5
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "%f%%\n"
.size .L.str.17, 6
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "time taken =%f\n"
.size .L.str.18, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8iterate1P15HIP_vector_typeIfLj2EES1_"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_"
.size .L__unnamed_2, 45
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z8iterate3P15HIP_vector_typeIfLj2EE"
.size .L__unnamed_3, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Can't open order_parameter_000.vtk file for writting"
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__iterate1P15HIP_vector_typeIfLj2EES1_
.addrsig_sym _Z23__device_stub__iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.addrsig_sym _Z23__device_stub__iterate3P15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8iterate1P15HIP_vector_typeIfLj2EES1_
.addrsig_sym _Z8iterate2P15HIP_vector_typeIfLj2EES1_PdS2_
.addrsig_sym _Z8iterate3P15HIP_vector_typeIfLj2EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} | code for sm_80
Function : _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R23, SR_TID.X ; /* 0x0000000000177919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x164], PT ; /* 0x0000590017007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f01270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0070*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*0080*/ IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff167624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ LOP3.LUT R35, R22.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316237812 */
/* 0x040fe400078ec0ff */
/*00b0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R0, -R35, c[0x0][0x168], RZ ; /* 0x00005a0023007a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc6000f8e023f */
/*00e0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00f0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0100*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0110*/ USHF.L.U32 UR8, UR4, 0x2, URZ ; /* 0x0000000204087899 */
/* 0x000fe4000800063f */
/*0120*/ USHF.L.U64.HI UR9, UR4, 0x2, UR5 ; /* 0x0000000204097899 */
/* 0x000fe40008010205 */
/*0130*/ IMAD R33, R23.reuse, c[0x0][0x168], RZ ; /* 0x00005a0017217a24 */
/* 0x040fe200078e02ff */
/*0140*/ ISETP.GE.U32.AND P2, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003f46070 */
/*0150*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R23, R23, c[0x0][0x0], RZ ; /* 0x0000000017177a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R21, P0, R33, UR4, RZ ; /* 0x0000000421157c10 */
/* 0x002fe4000ff1e0ff */
/*0180*/ SHF.R.S32.HI R32, RZ, 0x1f, R33 ; /* 0x0000001fff207819 */
/* 0x000fc40000011421 */
/*0190*/ ISETP.GE.AND P1, PT, R23, c[0x0][0x164], PT ; /* 0x0000590017007a0c */
/* 0x000fe20003f26270 */
/*01a0*/ IMAD.SHL.U32 R20, R21, 0x4, RZ ; /* 0x0000000415147824 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3.X R2, R32, UR5, RZ, P0, !PT ; /* 0x0000000520027c10 */
/* 0x000fe400087fe4ff */
/*01c0*/ ISETP.NE.AND P0, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fe40003f05270 */
/*01d0*/ SHF.L.U64.HI R21, R21, 0x2, R2 ; /* 0x0000000215157819 */
/* 0x000fe40000010202 */
/*01e0*/ IADD3 R2, P3, R20.reuse, c[0x0][0x170], RZ ; /* 0x00005c0014027a10 */
/* 0x040fe40007f7e0ff */
/*01f0*/ IADD3 R20, P4, R20, c[0x0][0x178], RZ ; /* 0x00005e0014147a10 */
/* 0x000fc40007f9e0ff */
/*0200*/ IADD3.X R3, R21.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0015037a10 */
/* 0x040fe40001ffe4ff */
/*0210*/ IADD3.X R21, R21, c[0x0][0x17c], RZ, P4, !PT ; /* 0x00005f0015157a10 */
/* 0x000fe200027fe4ff */
/*0220*/ @!P2 BRA 0x7c0 ; /* 0x000005900000a947 */
/* 0x001fea0003800000 */
/*0230*/ IMAD.SHL.U32 R24, R33.reuse, 0x4, RZ ; /* 0x0000000421187824 */
/* 0x040fe200078e00ff */
/*0240*/ IADD3 R4, R33.reuse, 0x3, RZ ; /* 0x0000000321047810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0260*/ IADD3 R6, R33.reuse, 0x2, RZ ; /* 0x0000000221067810 */
/* 0x040fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0280*/ SHF.L.U64.HI R32, R33.reuse, 0x2, R32 ; /* 0x0000000221207819 */
/* 0x040fe20000010220 */
/*0290*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0209 */
/*02a0*/ IADD3 R8, R33, 0x1, RZ ; /* 0x0000000121087810 */
/* 0x000fc40007ffe0ff */
/*02b0*/ IADD3 R27, P2, R24, c[0x0][0x188], RZ ; /* 0x00006200181b7a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x080fe200078e0209 */
/*02d0*/ IADD3 R26, P3, R24.reuse, c[0x0][0x180], RZ ; /* 0x00006000181a7a10 */
/* 0x040fe40007f7e0ff */
/*02e0*/ IADD3 R25, P4, R24.reuse, c[0x0][0x170], RZ ; /* 0x00005c0018197a10 */
/* 0x040fe20007f9e0ff */
/*02f0*/ IMAD.U32 R31, RZ, RZ, UR8 ; /* 0x00000008ff1f7e24 */
/* 0x000fe2000f8e00ff */
/*0300*/ IADD3 R24, P5, R24, c[0x0][0x178], RZ ; /* 0x00005e0018187a10 */
/* 0x000fe20007fbe0ff */
/*0310*/ IMAD.U32 R29, RZ, RZ, UR9 ; /* 0x00000009ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0320*/ IADD3.X R34, R32.reuse, c[0x0][0x18c], RZ, P2, !PT ; /* 0x0000630020227a10 */
/* 0x040fe200017fe4ff */
/*0330*/ IMAD.MOV.U32 R28, RZ, RZ, R0 ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e0000 */
/*0340*/ IADD3.X R36, R32, c[0x0][0x184], RZ, P3, !PT ; /* 0x0000610020247a10 */
/* 0x000fe20001ffe4ff */
/*0350*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*0360*/ IADD3.X R38, R32, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0020267a10 */
/* 0x000fc400027fe4ff */
/*0370*/ IADD3.X R32, R32, c[0x0][0x17c], RZ, P5, !PT ; /* 0x00005f0020207a10 */
/* 0x000fe40002ffe4ff */
/*0380*/ IADD3 R18, P2, R31, R24, RZ ; /* 0x000000181f127210 */
/* 0x000fca0007f5e0ff */
/*0390*/ IMAD.X R15, R29, 0x1, R32, P2 ; /* 0x000000011d0f7824 */
/* 0x001fe400010e0620 */
/*03a0*/ IMAD.MOV.U32 R14, RZ, RZ, R18 ; /* 0x000000ffff0e7224 */
/* 0x000fca00078e0012 */
/*03b0*/ LDG.E R10, [R14.64] ; /* 0x000000060e0a7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FSETP.GEU.AND P2, PT, R10, c[0x0][0x16c], PT ; /* 0x00005b000a007a0b */
/* 0x004fda0003f4e000 */
/*03d0*/ @P2 LDG.E R19, [R2.64] ; /* 0x0000000602132981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R10, P3, R31.reuse, R26, RZ ; /* 0x0000001a1f0a7210 */
/* 0x040fe40007f7e0ff */
/*03f0*/ IADD3 R12, P4, R31, R25, RZ ; /* 0x000000191f0c7210 */
/* 0x000fc60007f9e0ff */
/*0400*/ IMAD.X R11, R29.reuse, 0x1, R36, P3 ; /* 0x000000011d0b7824 */
/* 0x040fe400018e0624 */
/*0410*/ IMAD.X R13, R29, 0x1, R38, P4 ; /* 0x000000011d0d7824 */
/* 0x000fc600020e0626 */
/*0420*/ @P2 STG.E [R10.64], R19 ; /* 0x000000130a002986 */
/* 0x0041e8000c101906 */
/*0430*/ @!P2 LDG.E R37, [R12.64] ; /* 0x000000060c25a981 */
/* 0x000ea2000c1e1900 */
/*0440*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R21 ; /* 0x000000ffff0f2224 */
/* 0x000fe400078e0015 */
/*0450*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff122224 */
/* 0x000fe400078e0014 */
/*0460*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x001fe200078e000f */
/*0470*/ @!P2 STG.E [R10.64], R37 ; /* 0x000000250a00a986 */
/* 0x0041e8000c101906 */
/*0480*/ LDG.E R39, [R18.64] ; /* 0x0000000612277981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R14, P2, R31, R27, RZ ; /* 0x0000001b1f0e7210 */
/* 0x000fc40007f5e0ff */
/*04a0*/ IADD3 R16, P3, R8, R31, RZ ; /* 0x0000001f08107210 */
/* 0x000fc60007f7e0ff */
/*04b0*/ IMAD.X R15, R29, 0x1, R34, P2 ; /* 0x000000011d0f7824 */
/* 0x000fe400010e0622 */
/*04c0*/ IMAD.X R17, R9, 0x1, R29, P3 ; /* 0x0000000109117824 */
/* 0x000fc600018e061d */
/*04d0*/ STG.E [R14.64], R39 ; /* 0x000000270e007986 */
/* 0x0043e8000c101906 */
/*04e0*/ LDG.E R40, [R16.64] ; /* 0x0000000610287981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ FSETP.GEU.AND P2, PT, R40, c[0x0][0x16c], PT ; /* 0x00005b0028007a0b */
/* 0x004fda0003f4e000 */
/*0500*/ @P2 LDG.E R41, [R2.64] ; /* 0x0000000602292981 */
/* 0x000ea2000c1e1900 */
/*0510*/ @P2 IMAD.MOV.U32 R19, RZ, RZ, R21 ; /* 0x000000ffff132224 */
/* 0x000fe400078e0015 */
/*0520*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff122224 */
/* 0x000fe200078e0014 */
/*0530*/ @P2 STG.E [R10.64+0x4], R41 ; /* 0x000004290a002986 */
/* 0x0045e8000c101906 */
/*0540*/ @!P2 LDG.E R37, [R12.64+0x4] ; /* 0x000004060c25a981 */
/* 0x001ee2000c1e1900 */
/*0550*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff13a224 */
/* 0x000fe400078e0011 */
/*0560*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e0010 */
/*0570*/ @!P2 STG.E [R10.64+0x4], R37 ; /* 0x000004250a00a986 */
/* 0x008fe8000c101906 */
/*0580*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ee8000c1e1900 */
/*0590*/ STG.E [R14.64+0x4], R19 ; /* 0x000004130e007986 */
/* 0x0081e8000c101906 */
/*05a0*/ LDG.E R39, [R16.64+0x4] ; /* 0x0000040610277981 */
/* 0x002ee4000c1e1900 */
/*05b0*/ FSETP.GEU.AND P2, PT, R39, c[0x0][0x16c], PT ; /* 0x00005b0027007a0b */
/* 0x008fda0003f4e000 */
/*05c0*/ @P2 LDG.E R41, [R2.64] ; /* 0x0000000602292981 */
/* 0x004ea2000c1e1900 */
/*05d0*/ @P2 IMAD.MOV.U32 R40, RZ, RZ, R20 ; /* 0x000000ffff282224 */
/* 0x000fe200078e0014 */
/*05e0*/ @!P2 IADD3 R40, P3, R6, R31, RZ ; /* 0x0000001f0628a210 */
/* 0x000fe20007f7e0ff */
/*05f0*/ @P2 IMAD.MOV.U32 R43, RZ, RZ, R21 ; /* 0x000000ffff2b2224 */
/* 0x000fc800078e0015 */
/*0600*/ @!P2 IMAD.X R43, R7, 0x1, R29, P3 ; /* 0x00000001072ba824 */
/* 0x000fe200018e061d */
/*0610*/ @P2 STG.E [R10.64+0x8], R41 ; /* 0x000008290a002986 */
/* 0x0043e8000c101906 */
/*0620*/ @!P2 LDG.E R39, [R12.64+0x8] ; /* 0x000008060c27a981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.MOV.U32 R19, RZ, RZ, R43 ; /* 0x000000ffff137224 */
/* 0x001fe400078e002b */
/*0640*/ IMAD.MOV.U32 R18, RZ, RZ, R40 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0028 */
/*0650*/ @!P2 STG.E [R10.64+0x8], R39 ; /* 0x000008270a00a986 */
/* 0x004fe8000c101906 */
/*0660*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R14.64+0x8], R19 ; /* 0x000008130e007986 */
/* 0x004fe8000c101906 */
/*0680*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080610107981 */
/* 0x000ea4000c1e1900 */
/*0690*/ FSETP.GEU.AND P2, PT, R16, c[0x0][0x16c], PT ; /* 0x00005b0010007a0b */
/* 0x004fda0003f4e000 */
/*06a0*/ @P2 LDG.E R37, [R2.64] ; /* 0x0000000602252981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ @P2 IMAD.MOV.U32 R40, RZ, RZ, R20 ; /* 0x000000ffff282224 */
/* 0x000fe200078e0014 */
/*06c0*/ @!P2 IADD3 R40, P3, R4, R31, RZ ; /* 0x0000001f0428a210 */
/* 0x000fe20007f7e0ff */
/*06d0*/ @P2 IMAD.MOV.U32 R41, RZ, RZ, R21 ; /* 0x000000ffff292224 */
/* 0x002fe200078e0015 */
/*06e0*/ @P2 STG.E [R10.64+0xc], R37 ; /* 0x00000c250a002986 */
/* 0x004fe8000c101906 */
/*06f0*/ @!P2 LDG.E R13, [R12.64+0xc] ; /* 0x00000c060c0da981 */
/* 0x000ea2000c1e1900 */
/*0700*/ @!P2 IMAD.X R41, R5, 0x1, R29, P3 ; /* 0x000000010529a824 */
/* 0x000fc600018e061d */
/*0710*/ @!P2 STG.E [R10.64+0xc], R13 ; /* 0x00000c0d0a00a986 */
/* 0x0041e4000c101906 */
/*0720*/ IMAD.MOV.U32 R10, RZ, RZ, R40 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0028 */
/*0730*/ IMAD.MOV.U32 R11, RZ, RZ, R41 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0029 */
/*0740*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R28, R28, -0x4, RZ ; /* 0xfffffffc1c1c7810 */
/* 0x000fe40007ffe0ff */
/*0760*/ IADD3 R31, P3, R31, 0x10, RZ ; /* 0x000000101f1f7810 */
/* 0x000fe40007f7e0ff */
/*0770*/ ISETP.NE.AND P2, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe40003f45270 */
/*0780*/ IADD3 R30, R30, 0x4, RZ ; /* 0x000000041e1e7810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.X R29, RZ, RZ, R29, P3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200018e061d */
/*07a0*/ STG.E [R14.64+0xc], R17 ; /* 0x00000c110e007986 */
/* 0x0041f2000c101906 */
/*07b0*/ @P2 BRA 0x380 ; /* 0xfffffbc000002947 */
/* 0x000fea000383ffff */
/*07c0*/ @!P0 BRA 0xb90 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD.IADD R30, R33, 0x1, R30 ; /* 0x00000001211e7824 */
/* 0x000fca00078e021e */
/*07e0*/ IADD3 R4, P0, R30, UR4, RZ ; /* 0x000000041e047c10 */
/* 0x000fc8000ff1e0ff */
/*07f0*/ LEA.HI.X.SX32 R5, R30, UR5, 0x1, P0 ; /* 0x000000051e057c11 */
/* 0x000fe200080f0eff */
/*0800*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fc600078e00ff */
/*0810*/ SHF.L.U64.HI R14, R4, 0x2, R5 ; /* 0x00000002040e7819 */
/* 0x001fe40000010205 */
/*0820*/ IADD3 R10, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fc80007f1e0ff */
/*0830*/ IADD3.X R11, R14, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000e0b7a10 */
/* 0x000fca00007fe4ff */
/*0840*/ LDG.E R4, [R10.64] ; /* 0x000000060a047981 */
/* 0x000ea4000c1e1900 */
/*0850*/ FSETP.GEU.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0b */
/* 0x004fda0003f0e000 */
/*0860*/ @P0 LDG.E R13, [R2.64] ; /* 0x00000006020d0981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IADD3 R4, P2, R6.reuse, c[0x0][0x180], RZ ; /* 0x0000600006047a10 */
/* 0x040fe40007f5e0ff */
/*0880*/ IADD3 R8, P3, R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a10 */
/* 0x000fe40007f7e0ff */
/*0890*/ IADD3.X R5, R14.reuse, c[0x0][0x184], RZ, P2, !PT ; /* 0x000061000e057a10 */
/* 0x040fe400017fe4ff */
/*08a0*/ IADD3.X R9, R14, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d000e097a10 */
/* 0x000fe20001ffe4ff */
/*08b0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R21 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0015 */
/*08c0*/ @P0 STG.E [R4.64], R13 ; /* 0x0000000d04000986 */
/* 0x0041e8000c101906 */
/*08d0*/ @!P0 LDG.E R15, [R8.64] ; /* 0x00000006080f8981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff078224 */
/* 0x000fc400078e000b */
/*08f0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R20 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e0014 */
/*0900*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e000a */
/*0910*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x001fe200078e0007 */
/*0920*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0041e8000c101906 */
/*0930*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000ea2000c1e1900 */
/*0940*/ IADD3 R6, P0, R6, c[0x0][0x188], RZ ; /* 0x0000620006067a10 */
/* 0x000fc80007f1e0ff */
/*0950*/ IADD3.X R7, R14, c[0x0][0x18c], RZ, P0, !PT ; /* 0x000063000e077a10 */
/* 0x000fe400007fe4ff */
/*0960*/ ISETP.NE.AND P0, PT, R35, 0x1, PT ; /* 0x000000012300780c */
/* 0x000fc60003f05270 */
/*0970*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041f4000c101906 */
/*0980*/ @!P0 BRA 0xb90 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004060a0c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FSETP.GEU.AND P0, PT, R12, c[0x0][0x16c], PT ; /* 0x00005b000c007a0b */
/* 0x004fda0003f0e000 */
/*09b0*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000006020f0981 */
/* 0x001ea2000c1e1900 */
/*09c0*/ @!P0 IADD3 R12, R30, 0x1, RZ ; /* 0x000000011e0c8810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ @!P0 IADD3 R16, P2, R12.reuse, UR4, RZ ; /* 0x000000040c108c10 */
/* 0x040fe2000ff5e0ff */
/*09e0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e0224 */
/* 0x000fe200078e0014 */
/*09f0*/ @P0 STG.E [R4.64+0x4], R15 ; /* 0x0000040f04000986 */
/* 0x004fe8000c101906 */
/*0a00*/ @!P0 LDG.E R13, [R8.64+0x4] ; /* 0x00000406080d8981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ @!P0 LEA.HI.X.SX32 R19, R12, UR5, 0x1, P2 ; /* 0x000000050c138c11 */
/* 0x000fe200090f0eff */
/*0a20*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0015 */
/*0a30*/ @!P0 LEA R14, P2, R16, c[0x0][0x178], 0x2 ; /* 0x00005e00100e8a11 */
/* 0x000fc800078410ff */
/*0a40*/ @!P0 LEA.HI.X R17, R16, c[0x0][0x17c], R19, 0x2, P2 ; /* 0x00005f0010118a11 */
/* 0x000fe200010f1413 */
/*0a50*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000e */
/*0a60*/ @!P0 STG.E [R4.64+0x4], R13 ; /* 0x0000040d04008986 */
/* 0x0041e6000c101906 */
/*0a70*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x001fca00078e0011 */
/*0a80*/ LDG.E R15, [R12.64] ; /* 0x000000060c0f7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ ISETP.NE.AND P0, PT, R35, 0x2, PT ; /* 0x000000022300780c */
/* 0x000fc60003f05270 */
/*0aa0*/ STG.E [R6.64+0x4], R15 ; /* 0x0000040f06007986 */
/* 0x0041f4000c101906 */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R10, [R10.64+0x8] ; /* 0x000008060a0a7981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ FSETP.GEU.AND P0, PT, R10, c[0x0][0x16c], PT ; /* 0x00005b000a007a0b */
/* 0x004fda0003f0e000 */
/*0ae0*/ @P0 LDG.E R3, [R2.64] ; /* 0x0000000602030981 */
/* 0x000ea2000c1e1900 */
/*0af0*/ @!P0 IADD3 R12, R30, 0x2, RZ ; /* 0x000000021e0c8810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ @!P0 IADD3 R13, P2, R12, UR4, RZ ; /* 0x000000040c0d8c10 */
/* 0x000fc8000ff5e0ff */
/*0b10*/ @!P0 LEA.HI.X.SX32 R12, R12, UR5, 0x1, P2 ; /* 0x000000050c0c8c11 */
/* 0x000fe200090f0eff */
/*0b20*/ @P0 STG.E [R4.64+0x8], R3 ; /* 0x0000080304000986 */
/* 0x0043e8000c101906 */
/*0b30*/ @!P0 LDG.E R9, [R8.64+0x8] ; /* 0x0000080608098981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ @!P0 LEA R20, P2, R13, c[0x0][0x178], 0x2 ; /* 0x00005e000d148a11 */
/* 0x000fc800078410ff */
/*0b50*/ @!P0 LEA.HI.X R21, R13, c[0x0][0x17c], R12, 0x2, P2 ; /* 0x00005f000d158a11 */
/* 0x000fe200010f140c */
/*0b60*/ @!P0 STG.E [R4.64+0x8], R9 ; /* 0x0000080904008986 */
/* 0x0043ea000c101906 */
/*0b70*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ STG.E [R6.64+0x8], R21 ; /* 0x0000081506007986 */
/* 0x0043e4000c101906 */
/*0b90*/ @!P1 BRA 0x130 ; /* 0xfffff59000009947 */
/* 0x000fea000383ffff */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} | .file "tmpxft_000883f9_00000000-6_selection_k_radius_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
.type _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf, @function
_Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22selection_k_radius_gpuiiifPKiPKfPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf, .-_Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf, @function
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, .-_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22selection_k_radius_gpuiiifPKiPKfPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22selection_k_radius_gpuiiifPKiPKfPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 8
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf,@function
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
s_load_b32 s2, s[0:1], 0x4
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[16:17], s[0:1], 0x28
s_mul_i32 s0, s15, s2
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s4
v_mul_lo_u32 v1, v0, s4
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[0:1], 2
s_mov_b32 s0, 0
s_add_u32 s1, s6, s14
s_addc_u32 s3, s7, s15
s_add_u32 s6, s8, s14
s_addc_u32 s7, s9, s15
s_cmp_gt_i32 s4, 0
s_cselect_b32 s8, -1, 0
s_and_b32 s9, s12, 0xffff
s_add_u32 s10, s10, s14
s_addc_u32 s11, s11, s15
s_add_u32 s13, s16, s14
s_mul_i32 s12, s4, s9
s_addc_u32 s14, s17, s15
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v0, s9, v0
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v8, v0, s4
s_mov_b32 s15, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s1, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v10
v_lshlrev_b64 v[12:13], 2, v[8:9]
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s13, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s14, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s1, v12
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s16
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v14, off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
global_load_b32 v14, v[2:3], off
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 s5, v14
s_xor_b32 s16, exec_lo, s16
s_cbranch_execz .LBB0_8
global_load_b32 v15, v[10:11], off
global_load_b32 v14, v[12:13], off
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v15, off
.LBB0_8:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_5
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v15, off
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, .Lfunc_end0-_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z22selection_k_radius_gpuiiifPKiPKfPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void selection_k_radius_gpu(int b, int m, int k, float radius, const int* idx, const float* val, int* idx_out, float* val_out){
int batch_index = blockIdx.x;
int stride = batch_index * m * k;
idx += stride;
val += stride;
idx_out += stride;
val_out += stride;
for(int i = threadIdx.x; i < m;i += blockDim.x) {
for(int j = 0;j < k;j ++) {
if(val[i * k + j] < radius) {
idx_out[i * k + j] = idx[i * k + j];
val_out[i * k + j] = val[i * k + j];
} else {
idx_out[i * k + j] = idx[i * k ];
val_out[i * k + j] = val[i * k ];
}
}
}
} | .text
.file "selection_k_radius_gpu.hip"
.globl _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf # -- Begin function _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 4, 0x90
.type _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf,@function
_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf: # @_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22selection_k_radius_gpuiiifPKiPKfPiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf, .Lfunc_end0-_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22selection_k_radius_gpuiiifPKiPKfPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf,@object # @_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .rodata,"a",@progbits
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 3, 0x0
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
.quad _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22selection_k_radius_gpuiiifPKiPKfPiPf"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R23, SR_TID.X ; /* 0x0000000000177919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R23, c[0x0][0x164], PT ; /* 0x0000590017007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f01270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0070*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*0080*/ IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff167624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ LOP3.LUT R35, R22.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316237812 */
/* 0x040fe400078ec0ff */
/*00b0*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R0, -R35, c[0x0][0x168], RZ ; /* 0x00005a0023007a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc6000f8e023f */
/*00e0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe40000000800 */
/*00f0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0100*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0110*/ USHF.L.U32 UR8, UR4, 0x2, URZ ; /* 0x0000000204087899 */
/* 0x000fe4000800063f */
/*0120*/ USHF.L.U64.HI UR9, UR4, 0x2, UR5 ; /* 0x0000000204097899 */
/* 0x000fe40008010205 */
/*0130*/ IMAD R33, R23.reuse, c[0x0][0x168], RZ ; /* 0x00005a0017217a24 */
/* 0x040fe200078e02ff */
/*0140*/ ISETP.GE.U32.AND P2, PT, R22, 0x3, PT ; /* 0x000000031600780c */
/* 0x000fe20003f46070 */
/*0150*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R23, R23, c[0x0][0x0], RZ ; /* 0x0000000017177a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R21, P0, R33, UR4, RZ ; /* 0x0000000421157c10 */
/* 0x002fe4000ff1e0ff */
/*0180*/ SHF.R.S32.HI R32, RZ, 0x1f, R33 ; /* 0x0000001fff207819 */
/* 0x000fc40000011421 */
/*0190*/ ISETP.GE.AND P1, PT, R23, c[0x0][0x164], PT ; /* 0x0000590017007a0c */
/* 0x000fe20003f26270 */
/*01a0*/ IMAD.SHL.U32 R20, R21, 0x4, RZ ; /* 0x0000000415147824 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3.X R2, R32, UR5, RZ, P0, !PT ; /* 0x0000000520027c10 */
/* 0x000fe400087fe4ff */
/*01c0*/ ISETP.NE.AND P0, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fe40003f05270 */
/*01d0*/ SHF.L.U64.HI R21, R21, 0x2, R2 ; /* 0x0000000215157819 */
/* 0x000fe40000010202 */
/*01e0*/ IADD3 R2, P3, R20.reuse, c[0x0][0x170], RZ ; /* 0x00005c0014027a10 */
/* 0x040fe40007f7e0ff */
/*01f0*/ IADD3 R20, P4, R20, c[0x0][0x178], RZ ; /* 0x00005e0014147a10 */
/* 0x000fc40007f9e0ff */
/*0200*/ IADD3.X R3, R21.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0015037a10 */
/* 0x040fe40001ffe4ff */
/*0210*/ IADD3.X R21, R21, c[0x0][0x17c], RZ, P4, !PT ; /* 0x00005f0015157a10 */
/* 0x000fe200027fe4ff */
/*0220*/ @!P2 BRA 0x7c0 ; /* 0x000005900000a947 */
/* 0x001fea0003800000 */
/*0230*/ IMAD.SHL.U32 R24, R33.reuse, 0x4, RZ ; /* 0x0000000421187824 */
/* 0x040fe200078e00ff */
/*0240*/ IADD3 R4, R33.reuse, 0x3, RZ ; /* 0x0000000321047810 */
/* 0x040fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0260*/ IADD3 R6, R33.reuse, 0x2, RZ ; /* 0x0000000221067810 */
/* 0x040fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0280*/ SHF.L.U64.HI R32, R33.reuse, 0x2, R32 ; /* 0x0000000221207819 */
/* 0x040fe20000010220 */
/*0290*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0209 */
/*02a0*/ IADD3 R8, R33, 0x1, RZ ; /* 0x0000000121087810 */
/* 0x000fc40007ffe0ff */
/*02b0*/ IADD3 R27, P2, R24, c[0x0][0x188], RZ ; /* 0x00006200181b7a10 */
/* 0x000fe20007f5e0ff */
/*02c0*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x080fe200078e0209 */
/*02d0*/ IADD3 R26, P3, R24.reuse, c[0x0][0x180], RZ ; /* 0x00006000181a7a10 */
/* 0x040fe40007f7e0ff */
/*02e0*/ IADD3 R25, P4, R24.reuse, c[0x0][0x170], RZ ; /* 0x00005c0018197a10 */
/* 0x040fe20007f9e0ff */
/*02f0*/ IMAD.U32 R31, RZ, RZ, UR8 ; /* 0x00000008ff1f7e24 */
/* 0x000fe2000f8e00ff */
/*0300*/ IADD3 R24, P5, R24, c[0x0][0x178], RZ ; /* 0x00005e0018187a10 */
/* 0x000fe20007fbe0ff */
/*0310*/ IMAD.U32 R29, RZ, RZ, UR9 ; /* 0x00000009ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0320*/ IADD3.X R34, R32.reuse, c[0x0][0x18c], RZ, P2, !PT ; /* 0x0000630020227a10 */
/* 0x040fe200017fe4ff */
/*0330*/ IMAD.MOV.U32 R28, RZ, RZ, R0 ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e0000 */
/*0340*/ IADD3.X R36, R32, c[0x0][0x184], RZ, P3, !PT ; /* 0x0000610020247a10 */
/* 0x000fe20001ffe4ff */
/*0350*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*0360*/ IADD3.X R38, R32, c[0x0][0x174], RZ, P4, !PT ; /* 0x00005d0020267a10 */
/* 0x000fc400027fe4ff */
/*0370*/ IADD3.X R32, R32, c[0x0][0x17c], RZ, P5, !PT ; /* 0x00005f0020207a10 */
/* 0x000fe40002ffe4ff */
/*0380*/ IADD3 R18, P2, R31, R24, RZ ; /* 0x000000181f127210 */
/* 0x000fca0007f5e0ff */
/*0390*/ IMAD.X R15, R29, 0x1, R32, P2 ; /* 0x000000011d0f7824 */
/* 0x001fe400010e0620 */
/*03a0*/ IMAD.MOV.U32 R14, RZ, RZ, R18 ; /* 0x000000ffff0e7224 */
/* 0x000fca00078e0012 */
/*03b0*/ LDG.E R10, [R14.64] ; /* 0x000000060e0a7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FSETP.GEU.AND P2, PT, R10, c[0x0][0x16c], PT ; /* 0x00005b000a007a0b */
/* 0x004fda0003f4e000 */
/*03d0*/ @P2 LDG.E R19, [R2.64] ; /* 0x0000000602132981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IADD3 R10, P3, R31.reuse, R26, RZ ; /* 0x0000001a1f0a7210 */
/* 0x040fe40007f7e0ff */
/*03f0*/ IADD3 R12, P4, R31, R25, RZ ; /* 0x000000191f0c7210 */
/* 0x000fc60007f9e0ff */
/*0400*/ IMAD.X R11, R29.reuse, 0x1, R36, P3 ; /* 0x000000011d0b7824 */
/* 0x040fe400018e0624 */
/*0410*/ IMAD.X R13, R29, 0x1, R38, P4 ; /* 0x000000011d0d7824 */
/* 0x000fc600020e0626 */
/*0420*/ @P2 STG.E [R10.64], R19 ; /* 0x000000130a002986 */
/* 0x0041e8000c101906 */
/*0430*/ @!P2 LDG.E R37, [R12.64] ; /* 0x000000060c25a981 */
/* 0x000ea2000c1e1900 */
/*0440*/ @P2 IMAD.MOV.U32 R15, RZ, RZ, R21 ; /* 0x000000ffff0f2224 */
/* 0x000fe400078e0015 */
/*0450*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff122224 */
/* 0x000fe400078e0014 */
/*0460*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x001fe200078e000f */
/*0470*/ @!P2 STG.E [R10.64], R37 ; /* 0x000000250a00a986 */
/* 0x0041e8000c101906 */
/*0480*/ LDG.E R39, [R18.64] ; /* 0x0000000612277981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IADD3 R14, P2, R31, R27, RZ ; /* 0x0000001b1f0e7210 */
/* 0x000fc40007f5e0ff */
/*04a0*/ IADD3 R16, P3, R8, R31, RZ ; /* 0x0000001f08107210 */
/* 0x000fc60007f7e0ff */
/*04b0*/ IMAD.X R15, R29, 0x1, R34, P2 ; /* 0x000000011d0f7824 */
/* 0x000fe400010e0622 */
/*04c0*/ IMAD.X R17, R9, 0x1, R29, P3 ; /* 0x0000000109117824 */
/* 0x000fc600018e061d */
/*04d0*/ STG.E [R14.64], R39 ; /* 0x000000270e007986 */
/* 0x0043e8000c101906 */
/*04e0*/ LDG.E R40, [R16.64] ; /* 0x0000000610287981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ FSETP.GEU.AND P2, PT, R40, c[0x0][0x16c], PT ; /* 0x00005b0028007a0b */
/* 0x004fda0003f4e000 */
/*0500*/ @P2 LDG.E R41, [R2.64] ; /* 0x0000000602292981 */
/* 0x000ea2000c1e1900 */
/*0510*/ @P2 IMAD.MOV.U32 R19, RZ, RZ, R21 ; /* 0x000000ffff132224 */
/* 0x000fe400078e0015 */
/*0520*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R20 ; /* 0x000000ffff122224 */
/* 0x000fe200078e0014 */
/*0530*/ @P2 STG.E [R10.64+0x4], R41 ; /* 0x000004290a002986 */
/* 0x0045e8000c101906 */
/*0540*/ @!P2 LDG.E R37, [R12.64+0x4] ; /* 0x000004060c25a981 */
/* 0x001ee2000c1e1900 */
/*0550*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, R17 ; /* 0x000000ffff13a224 */
/* 0x000fe400078e0011 */
/*0560*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e0010 */
/*0570*/ @!P2 STG.E [R10.64+0x4], R37 ; /* 0x000004250a00a986 */
/* 0x008fe8000c101906 */
/*0580*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ee8000c1e1900 */
/*0590*/ STG.E [R14.64+0x4], R19 ; /* 0x000004130e007986 */
/* 0x0081e8000c101906 */
/*05a0*/ LDG.E R39, [R16.64+0x4] ; /* 0x0000040610277981 */
/* 0x002ee4000c1e1900 */
/*05b0*/ FSETP.GEU.AND P2, PT, R39, c[0x0][0x16c], PT ; /* 0x00005b0027007a0b */
/* 0x008fda0003f4e000 */
/*05c0*/ @P2 LDG.E R41, [R2.64] ; /* 0x0000000602292981 */
/* 0x004ea2000c1e1900 */
/*05d0*/ @P2 IMAD.MOV.U32 R40, RZ, RZ, R20 ; /* 0x000000ffff282224 */
/* 0x000fe200078e0014 */
/*05e0*/ @!P2 IADD3 R40, P3, R6, R31, RZ ; /* 0x0000001f0628a210 */
/* 0x000fe20007f7e0ff */
/*05f0*/ @P2 IMAD.MOV.U32 R43, RZ, RZ, R21 ; /* 0x000000ffff2b2224 */
/* 0x000fc800078e0015 */
/*0600*/ @!P2 IMAD.X R43, R7, 0x1, R29, P3 ; /* 0x00000001072ba824 */
/* 0x000fe200018e061d */
/*0610*/ @P2 STG.E [R10.64+0x8], R41 ; /* 0x000008290a002986 */
/* 0x0043e8000c101906 */
/*0620*/ @!P2 LDG.E R39, [R12.64+0x8] ; /* 0x000008060c27a981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IMAD.MOV.U32 R19, RZ, RZ, R43 ; /* 0x000000ffff137224 */
/* 0x001fe400078e002b */
/*0640*/ IMAD.MOV.U32 R18, RZ, RZ, R40 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0028 */
/*0650*/ @!P2 STG.E [R10.64+0x8], R39 ; /* 0x000008270a00a986 */
/* 0x004fe8000c101906 */
/*0660*/ LDG.E R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R14.64+0x8], R19 ; /* 0x000008130e007986 */
/* 0x004fe8000c101906 */
/*0680*/ LDG.E R16, [R16.64+0x8] ; /* 0x0000080610107981 */
/* 0x000ea4000c1e1900 */
/*0690*/ FSETP.GEU.AND P2, PT, R16, c[0x0][0x16c], PT ; /* 0x00005b0010007a0b */
/* 0x004fda0003f4e000 */
/*06a0*/ @P2 LDG.E R37, [R2.64] ; /* 0x0000000602252981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ @P2 IMAD.MOV.U32 R40, RZ, RZ, R20 ; /* 0x000000ffff282224 */
/* 0x000fe200078e0014 */
/*06c0*/ @!P2 IADD3 R40, P3, R4, R31, RZ ; /* 0x0000001f0428a210 */
/* 0x000fe20007f7e0ff */
/*06d0*/ @P2 IMAD.MOV.U32 R41, RZ, RZ, R21 ; /* 0x000000ffff292224 */
/* 0x002fe200078e0015 */
/*06e0*/ @P2 STG.E [R10.64+0xc], R37 ; /* 0x00000c250a002986 */
/* 0x004fe8000c101906 */
/*06f0*/ @!P2 LDG.E R13, [R12.64+0xc] ; /* 0x00000c060c0da981 */
/* 0x000ea2000c1e1900 */
/*0700*/ @!P2 IMAD.X R41, R5, 0x1, R29, P3 ; /* 0x000000010529a824 */
/* 0x000fc600018e061d */
/*0710*/ @!P2 STG.E [R10.64+0xc], R13 ; /* 0x00000c0d0a00a986 */
/* 0x0041e4000c101906 */
/*0720*/ IMAD.MOV.U32 R10, RZ, RZ, R40 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0028 */
/*0730*/ IMAD.MOV.U32 R11, RZ, RZ, R41 ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e0029 */
/*0740*/ LDG.E R17, [R10.64] ; /* 0x000000060a117981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R28, R28, -0x4, RZ ; /* 0xfffffffc1c1c7810 */
/* 0x000fe40007ffe0ff */
/*0760*/ IADD3 R31, P3, R31, 0x10, RZ ; /* 0x000000101f1f7810 */
/* 0x000fe40007f7e0ff */
/*0770*/ ISETP.NE.AND P2, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe40003f45270 */
/*0780*/ IADD3 R30, R30, 0x4, RZ ; /* 0x000000041e1e7810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.X R29, RZ, RZ, R29, P3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200018e061d */
/*07a0*/ STG.E [R14.64+0xc], R17 ; /* 0x00000c110e007986 */
/* 0x0041f2000c101906 */
/*07b0*/ @P2 BRA 0x380 ; /* 0xfffffbc000002947 */
/* 0x000fea000383ffff */
/*07c0*/ @!P0 BRA 0xb90 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*07d0*/ IMAD.IADD R30, R33, 0x1, R30 ; /* 0x00000001211e7824 */
/* 0x000fca00078e021e */
/*07e0*/ IADD3 R4, P0, R30, UR4, RZ ; /* 0x000000041e047c10 */
/* 0x000fc8000ff1e0ff */
/*07f0*/ LEA.HI.X.SX32 R5, R30, UR5, 0x1, P0 ; /* 0x000000051e057c11 */
/* 0x000fe200080f0eff */
/*0800*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fc600078e00ff */
/*0810*/ SHF.L.U64.HI R14, R4, 0x2, R5 ; /* 0x00000002040e7819 */
/* 0x001fe40000010205 */
/*0820*/ IADD3 R10, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fc80007f1e0ff */
/*0830*/ IADD3.X R11, R14, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000e0b7a10 */
/* 0x000fca00007fe4ff */
/*0840*/ LDG.E R4, [R10.64] ; /* 0x000000060a047981 */
/* 0x000ea4000c1e1900 */
/*0850*/ FSETP.GEU.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0b */
/* 0x004fda0003f0e000 */
/*0860*/ @P0 LDG.E R13, [R2.64] ; /* 0x00000006020d0981 */
/* 0x000ea2000c1e1900 */
/*0870*/ IADD3 R4, P2, R6.reuse, c[0x0][0x180], RZ ; /* 0x0000600006047a10 */
/* 0x040fe40007f5e0ff */
/*0880*/ IADD3 R8, P3, R6, c[0x0][0x170], RZ ; /* 0x00005c0006087a10 */
/* 0x000fe40007f7e0ff */
/*0890*/ IADD3.X R5, R14.reuse, c[0x0][0x184], RZ, P2, !PT ; /* 0x000061000e057a10 */
/* 0x040fe400017fe4ff */
/*08a0*/ IADD3.X R9, R14, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d000e097a10 */
/* 0x000fe20001ffe4ff */
/*08b0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R21 ; /* 0x000000ffff070224 */
/* 0x000fe400078e0015 */
/*08c0*/ @P0 STG.E [R4.64], R13 ; /* 0x0000000d04000986 */
/* 0x0041e8000c101906 */
/*08d0*/ @!P0 LDG.E R15, [R8.64] ; /* 0x00000006080f8981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff078224 */
/* 0x000fc400078e000b */
/*08f0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, R20 ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e0014 */
/*0900*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e000a */
/*0910*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x001fe200078e0007 */
/*0920*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0041e8000c101906 */
/*0930*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000ea2000c1e1900 */
/*0940*/ IADD3 R6, P0, R6, c[0x0][0x188], RZ ; /* 0x0000620006067a10 */
/* 0x000fc80007f1e0ff */
/*0950*/ IADD3.X R7, R14, c[0x0][0x18c], RZ, P0, !PT ; /* 0x000063000e077a10 */
/* 0x000fe400007fe4ff */
/*0960*/ ISETP.NE.AND P0, PT, R35, 0x1, PT ; /* 0x000000012300780c */
/* 0x000fc60003f05270 */
/*0970*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041f4000c101906 */
/*0980*/ @!P0 BRA 0xb90 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R12, [R10.64+0x4] ; /* 0x000004060a0c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FSETP.GEU.AND P0, PT, R12, c[0x0][0x16c], PT ; /* 0x00005b000c007a0b */
/* 0x004fda0003f0e000 */
/*09b0*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000006020f0981 */
/* 0x001ea2000c1e1900 */
/*09c0*/ @!P0 IADD3 R12, R30, 0x1, RZ ; /* 0x000000011e0c8810 */
/* 0x000fc80007ffe0ff */
/*09d0*/ @!P0 IADD3 R16, P2, R12.reuse, UR4, RZ ; /* 0x000000040c108c10 */
/* 0x040fe2000ff5e0ff */
/*09e0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, R20 ; /* 0x000000ffff0e0224 */
/* 0x000fe200078e0014 */
/*09f0*/ @P0 STG.E [R4.64+0x4], R15 ; /* 0x0000040f04000986 */
/* 0x004fe8000c101906 */
/*0a00*/ @!P0 LDG.E R13, [R8.64+0x4] ; /* 0x00000406080d8981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ @!P0 LEA.HI.X.SX32 R19, R12, UR5, 0x1, P2 ; /* 0x000000050c138c11 */
/* 0x000fe200090f0eff */
/*0a20*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R21 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0015 */
/*0a30*/ @!P0 LEA R14, P2, R16, c[0x0][0x178], 0x2 ; /* 0x00005e00100e8a11 */
/* 0x000fc800078410ff */
/*0a40*/ @!P0 LEA.HI.X R17, R16, c[0x0][0x17c], R19, 0x2, P2 ; /* 0x00005f0010118a11 */
/* 0x000fe200010f1413 */
/*0a50*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000e */
/*0a60*/ @!P0 STG.E [R4.64+0x4], R13 ; /* 0x0000040d04008986 */
/* 0x0041e6000c101906 */
/*0a70*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x001fca00078e0011 */
/*0a80*/ LDG.E R15, [R12.64] ; /* 0x000000060c0f7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ ISETP.NE.AND P0, PT, R35, 0x2, PT ; /* 0x000000022300780c */
/* 0x000fc60003f05270 */
/*0aa0*/ STG.E [R6.64+0x4], R15 ; /* 0x0000040f06007986 */
/* 0x0041f4000c101906 */
/*0ab0*/ @!P0 BRA 0xb90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R10, [R10.64+0x8] ; /* 0x000008060a0a7981 */
/* 0x000ea4000c1e1900 */
/*0ad0*/ FSETP.GEU.AND P0, PT, R10, c[0x0][0x16c], PT ; /* 0x00005b000a007a0b */
/* 0x004fda0003f0e000 */
/*0ae0*/ @P0 LDG.E R3, [R2.64] ; /* 0x0000000602030981 */
/* 0x000ea2000c1e1900 */
/*0af0*/ @!P0 IADD3 R12, R30, 0x2, RZ ; /* 0x000000021e0c8810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ @!P0 IADD3 R13, P2, R12, UR4, RZ ; /* 0x000000040c0d8c10 */
/* 0x000fc8000ff5e0ff */
/*0b10*/ @!P0 LEA.HI.X.SX32 R12, R12, UR5, 0x1, P2 ; /* 0x000000050c0c8c11 */
/* 0x000fe200090f0eff */
/*0b20*/ @P0 STG.E [R4.64+0x8], R3 ; /* 0x0000080304000986 */
/* 0x0043e8000c101906 */
/*0b30*/ @!P0 LDG.E R9, [R8.64+0x8] ; /* 0x0000080608098981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ @!P0 LEA R20, P2, R13, c[0x0][0x178], 0x2 ; /* 0x00005e000d148a11 */
/* 0x000fc800078410ff */
/*0b50*/ @!P0 LEA.HI.X R21, R13, c[0x0][0x17c], R12, 0x2, P2 ; /* 0x00005f000d158a11 */
/* 0x000fe200010f140c */
/*0b60*/ @!P0 STG.E [R4.64+0x8], R9 ; /* 0x0000080904008986 */
/* 0x0043ea000c101906 */
/*0b70*/ LDG.E R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ STG.E [R6.64+0x8], R21 ; /* 0x0000081506007986 */
/* 0x0043e4000c101906 */
/*0b90*/ @!P1 BRA 0x130 ; /* 0xfffff59000009947 */
/* 0x000fea000383ffff */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 8
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf,@function
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
s_load_b32 s2, s[0:1], 0x4
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[16:17], s[0:1], 0x28
s_mul_i32 s0, s15, s2
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s4
v_mul_lo_u32 v1, v0, s4
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[14:15], s[0:1], 2
s_mov_b32 s0, 0
s_add_u32 s1, s6, s14
s_addc_u32 s3, s7, s15
s_add_u32 s6, s8, s14
s_addc_u32 s7, s9, s15
s_cmp_gt_i32 s4, 0
s_cselect_b32 s8, -1, 0
s_and_b32 s9, s12, 0xffff
s_add_u32 s10, s10, s14
s_addc_u32 s11, s11, s15
s_add_u32 s13, s16, s14
s_mul_i32 s12, s4, s9
s_addc_u32 s14, s17, s15
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v0, s9, v0
v_add_nc_u32_e32 v1, s12, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v8, v0, s4
s_mov_b32 s15, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v4, vcc_lo, s1, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s10, v10
v_lshlrev_b64 v[12:13], 2, v[8:9]
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v11, vcc_lo
v_add_co_u32 v8, vcc_lo, s13, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s14, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s1, v12
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v13, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s16
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v14, off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
global_load_b32 v14, v[2:3], off
s_mov_b32 s16, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 s5, v14
s_xor_b32 s16, exec_lo, s16
s_cbranch_execz .LBB0_8
global_load_b32 v15, v[10:11], off
global_load_b32 v14, v[12:13], off
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v15, off
.LBB0_8:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_5
global_load_b32 v15, v[4:5], off
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v15, off
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, .Lfunc_end0-_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z22selection_k_radius_gpuiiifPKiPKfPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000883f9_00000000-6_selection_k_radius_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
.type _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf, @function
_Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22selection_k_radius_gpuiiifPKiPKfPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf, .-_Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf, @function
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z22selection_k_radius_gpuiiifPKiPKfPiPfiiifPKiPKfPiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, .-_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22selection_k_radius_gpuiiifPKiPKfPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22selection_k_radius_gpuiiifPKiPKfPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "selection_k_radius_gpu.hip"
.globl _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf # -- Begin function _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 4, 0x90
.type _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf,@function
_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf: # @_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22selection_k_radius_gpuiiifPKiPKfPiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf, .Lfunc_end0-_Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22selection_k_radius_gpuiiifPKiPKfPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22selection_k_radius_gpuiiifPKiPKfPiPf,@object # @_Z22selection_k_radius_gpuiiifPKiPKfPiPf
.section .rodata,"a",@progbits
.globl _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.p2align 3, 0x0
_Z22selection_k_radius_gpuiiifPKiPKfPiPf:
.quad _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.size _Z22selection_k_radius_gpuiiifPKiPKfPiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22selection_k_radius_gpuiiifPKiPKfPiPf"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__selection_k_radius_gpuiiifPKiPKfPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22selection_k_radius_gpuiiifPKiPKfPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} | code for sm_80
Function : _Z10volume_maxiPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FSETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f04000 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} | .file "tmpxft_00022dc7_00000000-6_volume_max_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
.type _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf, @function
_Z34__device_stub__Z10volume_maxiPfPKfiPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10volume_maxiPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf, .-_Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
.globl _Z10volume_maxiPfPKf
.type _Z10volume_maxiPfPKf, @function
_Z10volume_maxiPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10volume_maxiPfPKf, .-_Z10volume_maxiPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10volume_maxiPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10volume_maxiPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} | #include <hip/hip_runtime.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10volume_maxiPfPKf
.globl _Z10volume_maxiPfPKf
.p2align 8
.type _Z10volume_maxiPfPKf,@function
_Z10volume_maxiPfPKf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10volume_maxiPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10volume_maxiPfPKf, .Lfunc_end0-_Z10volume_maxiPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10volume_maxiPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10volume_maxiPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void volume_max(
const int num_elements,
float * v1,
const float * v2
){
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i >= num_elements) return;
if (v2[i] > v1[i])
v1[i] = v2[i];
} | .text
.file "volume_max_kernel.hip"
.globl _Z25__device_stub__volume_maxiPfPKf # -- Begin function _Z25__device_stub__volume_maxiPfPKf
.p2align 4, 0x90
.type _Z25__device_stub__volume_maxiPfPKf,@function
_Z25__device_stub__volume_maxiPfPKf: # @_Z25__device_stub__volume_maxiPfPKf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10volume_maxiPfPKf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__volume_maxiPfPKf, .Lfunc_end0-_Z25__device_stub__volume_maxiPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10volume_maxiPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10volume_maxiPfPKf,@object # @_Z10volume_maxiPfPKf
.section .rodata,"a",@progbits
.globl _Z10volume_maxiPfPKf
.p2align 3, 0x0
_Z10volume_maxiPfPKf:
.quad _Z25__device_stub__volume_maxiPfPKf
.size _Z10volume_maxiPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10volume_maxiPfPKf"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__volume_maxiPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10volume_maxiPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10volume_maxiPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FSETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f04000 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10volume_maxiPfPKf
.globl _Z10volume_maxiPfPKf
.p2align 8
.type _Z10volume_maxiPfPKf,@function
_Z10volume_maxiPfPKf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10volume_maxiPfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10volume_maxiPfPKf, .Lfunc_end0-_Z10volume_maxiPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10volume_maxiPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10volume_maxiPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00022dc7_00000000-6_volume_max_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
.type _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf, @function
_Z34__device_stub__Z10volume_maxiPfPKfiPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10volume_maxiPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf, .-_Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
.globl _Z10volume_maxiPfPKf
.type _Z10volume_maxiPfPKf, @function
_Z10volume_maxiPfPKf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10volume_maxiPfPKfiPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10volume_maxiPfPKf, .-_Z10volume_maxiPfPKf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10volume_maxiPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10volume_maxiPfPKf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "volume_max_kernel.hip"
.globl _Z25__device_stub__volume_maxiPfPKf # -- Begin function _Z25__device_stub__volume_maxiPfPKf
.p2align 4, 0x90
.type _Z25__device_stub__volume_maxiPfPKf,@function
_Z25__device_stub__volume_maxiPfPKf: # @_Z25__device_stub__volume_maxiPfPKf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10volume_maxiPfPKf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__volume_maxiPfPKf, .Lfunc_end0-_Z25__device_stub__volume_maxiPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10volume_maxiPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10volume_maxiPfPKf,@object # @_Z10volume_maxiPfPKf
.section .rodata,"a",@progbits
.globl _Z10volume_maxiPfPKf
.p2align 3, 0x0
_Z10volume_maxiPfPKf:
.quad _Z25__device_stub__volume_maxiPfPKf
.size _Z10volume_maxiPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10volume_maxiPfPKf"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__volume_maxiPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10volume_maxiPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
}
extern "C"
__global__ void deltasOne(float *inputs, float *outputs, float *weights, float *weightsDeltas, int offsetInputImages, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = inputSize*(gid+offsetInputImages);
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetInputImages+gid]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
} | .file "tmpxft_00094ef4_00000000-6_Perceptron.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.type _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, @function
_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasBatch(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, .-_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.globl deltasBatch
.type deltasBatch, @function
deltasBatch:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size deltasBatch, .-deltasBatch
.globl _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
.type _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii, @function
_Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasOne(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii, .-_Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
.globl deltasOne
.type deltasOne, @function
deltasOne:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size deltasOne, .-deltasOne
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "deltasOne"
.LC1:
.string "deltasBatch"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq deltasOne(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq deltasBatch(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
}
extern "C"
__global__ void deltasOne(float *inputs, float *outputs, float *weights, float *weightsDeltas, int offsetInputImages, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = inputSize*(gid+offsetInputImages);
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetInputImages+gid]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
}
extern "C"
__global__ void deltasOne(float *inputs, float *outputs, float *weights, float *weightsDeltas, int offsetInputImages, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = inputSize*(gid+offsetInputImages);
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetInputImages+gid]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
}
extern "C"
__global__ void deltasOne(float *inputs, float *outputs, float *weights, float *weightsDeltas, int offsetInputImages, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = inputSize*(gid+offsetInputImages);
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetInputImages+gid]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected deltasBatch
.globl deltasBatch
.p2align 8
.type deltasBatch,@function
deltasBatch:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[10:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s2, s4, 1
s_cmp_lt_i32 s4, 0
v_mul_lo_u32 v2, v1, s2
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s2, s2, -1
s_cmp_eq_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v4, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
global_store_b32 v[4:5], v0, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b32 s12, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_14
s_load_b64 s[6:7], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v4, s4, v2
v_ashrrev_i32_e32 v3, 31, v2
s_load_b128 s[0:3], s[0:1], 0x0
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v5, 31, v4
s_mul_i32 s13, s4, s12
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mul_lo_u32 v10, v1, s12
s_lshl_b64 s[8:9], s[4:5], 2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_mul_lo_u32 v0, s13, v1
s_mov_b32 s13, 0
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s10, v4
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s6, s8
s_addc_u32 s9, s7, s9
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_cmp_gt_i32 s4, 0
s_cselect_b32 s5, -1, 0
s_branch .LBB0_7
.LBB0_5:
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v12, v1
global_store_b32 v[4:5], v1, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, s4, v0
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s13, s12
s_cbranch_scc1 .LBB0_14
.LBB0_7:
v_mov_b32_e32 v1, 0
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_10
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b64 s[10:11], s[6:7]
s_mov_b32 s14, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_mov_b32_e32 v1, 0
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
.LBB0_9:
global_load_b32 v8, v[6:7], off
global_load_b32 v9, v11, s[10:11]
v_add_co_u32 v6, vcc_lo, v6, 4
s_add_i32 s14, s14, -1
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s14, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v8, v9
s_cbranch_scc0 .LBB0_9
.LBB0_10:
global_load_b32 v8, v11, s[8:9]
v_add_nc_u32_e32 v6, s13, v10
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v1
global_load_b32 v6, v[6:7], off
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v6, v1
v_cmpx_neq_f32_e32 0, v12
s_cbranch_execz .LBB0_6
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
v_ashrrev_i32_e32 v1, 31, v0
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
s_mov_b32 s11, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v6, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
.p2align 6
.LBB0_13:
global_load_b32 v1, v[6:7], off
global_load_b32 v13, v[8:9], off
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v12, v1
global_store_b32 v[8:9], v13, off
v_add_co_u32 v8, vcc_lo, v8, 4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_cbranch_scc0 .LBB0_13
s_branch .LBB0_5
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel deltasBatch
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size deltasBatch, .Lfunc_end0-deltasBatch
.section .AMDGPU.csdata,"",@progbits
.text
.protected deltasOne
.globl deltasOne
.p2align 8
.type deltasOne,@function
deltasOne:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_add_i32 s5, s4, 1
s_cmp_lt_i32 s4, 0
v_mul_lo_u32 v0, v1, s5
s_cbranch_scc1 .LBB1_3
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v2, v0
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[5:6], v4, off
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v2, v4, s4
s_cbranch_scc1 .LBB1_6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v1, 0
s_mov_b64 s[10:11], s[8:9]
s_mov_b32 s5, s4
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
.LBB1_5:
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v3, s[10:11]
v_add_co_u32 v5, vcc_lo, v5, 4
s_add_i32 s5, s5, -1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v7, v8
s_cbranch_scc0 .LBB1_5
s_branch .LBB1_7
.LBB1_6:
v_mov_b32_e32 v1, 0
.LBB1_7:
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[10:11], s[4:5], 2
v_mov_b32_e32 v6, 0
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
v_lshlrev_b64 v[3:4], 2, v[4:5]
global_load_b32 v5, v6, s[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_neq_f32_e32 0, v5
s_cbranch_execz .LBB1_12
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_11
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.LBB1_10:
global_load_b32 v6, v[3:4], off
global_load_b32 v7, v[1:2], off
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v7, v5, v6
global_store_b32 v[1:2], v7, off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cbranch_scc0 .LBB1_10
.LBB1_11:
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v5, v2
global_store_b32 v[0:1], v2, off
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel deltasOne
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size deltasOne, .Lfunc_end1-deltasOne
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: deltasBatch
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: deltasBatch.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: deltasOne
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: deltasOne.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void deltasBatch(float *inputs, float *outputs, float *weights, float *weightsDeltas, int noInputs, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = noInputs*inputSize*gid;
int offsetOutputs = noInputs*gid;
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for (int i=0;i<noInputs;i++){
sum=0;
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+i*inputSize+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetOutputs+i]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+i*inputSize+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
}
}
extern "C"
__global__ void deltasOne(float *inputs, float *outputs, float *weights, float *weightsDeltas, int offsetInputImages, int inputSize){
int gid = blockIdx.x * blockDim.x + threadIdx.x;
float sum=0;
int offsetDeltas = (inputSize+1)*gid;
int offsetInput = inputSize*(gid+offsetInputImages);
for(int imageIndex=0;imageIndex<=inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]=0;
}
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
sum+=inputs[offsetInput+imageIndex]*weights[imageIndex];
}
sum+=weights[inputSize];
if(sum>0) sum=1;
else sum=0;
sum=outputs[offsetInputImages+gid]-sum;
if(sum!=0){
for(int imageIndex=0;imageIndex<inputSize;imageIndex++){
weightsDeltas[offsetDeltas+imageIndex]+=sum*inputs[offsetInput+imageIndex];
}
weightsDeltas[offsetDeltas+inputSize]+=sum;
}
} | .text
.file "Perceptron.hip"
.globl __device_stub__deltasBatch # -- Begin function __device_stub__deltasBatch
.p2align 4, 0x90
.type __device_stub__deltasBatch,@function
__device_stub__deltasBatch: # @__device_stub__deltasBatch
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasBatch, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__deltasBatch, .Lfunc_end0-__device_stub__deltasBatch
.cfi_endproc
# -- End function
.globl __device_stub__deltasOne # -- Begin function __device_stub__deltasOne
.p2align 4, 0x90
.type __device_stub__deltasOne,@function
__device_stub__deltasOne: # @__device_stub__deltasOne
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasOne, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__deltasOne, .Lfunc_end1-__device_stub__deltasOne
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasBatch, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasOne, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type deltasBatch,@object # @deltasBatch
.section .rodata,"a",@progbits
.globl deltasBatch
.p2align 3, 0x0
deltasBatch:
.quad __device_stub__deltasBatch
.size deltasBatch, 8
.type deltasOne,@object # @deltasOne
.globl deltasOne
.p2align 3, 0x0
deltasOne:
.quad __device_stub__deltasOne
.size deltasOne, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "deltasBatch"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "deltasOne"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__deltasBatch
.addrsig_sym __device_stub__deltasOne
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deltasBatch
.addrsig_sym deltasOne
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094ef4_00000000-6_Perceptron.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.type _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, @function
_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasBatch(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii, .-_Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
.globl deltasBatch
.type deltasBatch, @function
deltasBatch:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11deltasBatchPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size deltasBatch, .-deltasBatch
.globl _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
.type _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii, @function
_Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq deltasOne(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii, .-_Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
.globl deltasOne
.type deltasOne, @function
deltasOne:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9deltasOnePfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size deltasOne, .-deltasOne
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "deltasOne"
.LC1:
.string "deltasBatch"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq deltasOne(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq deltasBatch(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Perceptron.hip"
.globl __device_stub__deltasBatch # -- Begin function __device_stub__deltasBatch
.p2align 4, 0x90
.type __device_stub__deltasBatch,@function
__device_stub__deltasBatch: # @__device_stub__deltasBatch
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasBatch, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__deltasBatch, .Lfunc_end0-__device_stub__deltasBatch
.cfi_endproc
# -- End function
.globl __device_stub__deltasOne # -- Begin function __device_stub__deltasOne
.p2align 4, 0x90
.type __device_stub__deltasOne,@function
__device_stub__deltasOne: # @__device_stub__deltasOne
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $deltasOne, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__deltasOne, .Lfunc_end1-__device_stub__deltasOne
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasBatch, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $deltasOne, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type deltasBatch,@object # @deltasBatch
.section .rodata,"a",@progbits
.globl deltasBatch
.p2align 3, 0x0
deltasBatch:
.quad __device_stub__deltasBatch
.size deltasBatch, 8
.type deltasOne,@object # @deltasOne
.globl deltasOne
.p2align 3, 0x0
deltasOne:
.quad __device_stub__deltasOne
.size deltasOne, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "deltasBatch"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "deltasOne"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__deltasBatch
.addrsig_sym __device_stub__deltasOne
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deltasBatch
.addrsig_sym deltasOne
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define NUM 512
__device__ inline void swap(int & a, int & b)
{
// Alternative swap doesn't use a temporary register:
// a ^= b;
// b ^= a;
// a ^= b;
int tmp = a;
a = b;
b = tmp;
}
__global__ static void bitonicSort(int * values, int *results)
{
extern __shared__ int shared[];
const unsigned int tid = threadIdx.x;
const unsigned int bid = blockIdx.x;
// Copy input to shared mem.
shared[tid] = values[(bid*NUM) + tid];
__syncthreads();
// Parallel bitonic sort.
for (unsigned int k = 2; k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2; j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
else
{
if (shared[tid] < shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
}
__syncthreads();
}
}
// Write result.
results[(bid*NUM) + tid] = shared[tid];
} | .file "tmpxft_0017f30f_00000000-6_bitonicKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL11bitonicSortPiS_, @function
_ZL11bitonicSortPiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL11bitonicSortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _ZL11bitonicSortPiS_, .-_ZL11bitonicSortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11bitonicSortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11bitonicSortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define NUM 512
__device__ inline void swap(int & a, int & b)
{
// Alternative swap doesn't use a temporary register:
// a ^= b;
// b ^= a;
// a ^= b;
int tmp = a;
a = b;
b = tmp;
}
__global__ static void bitonicSort(int * values, int *results)
{
extern __shared__ int shared[];
const unsigned int tid = threadIdx.x;
const unsigned int bid = blockIdx.x;
// Copy input to shared mem.
shared[tid] = values[(bid*NUM) + tid];
__syncthreads();
// Parallel bitonic sort.
for (unsigned int k = 2; k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2; j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
else
{
if (shared[tid] < shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
}
__syncthreads();
}
}
// Write result.
results[(bid*NUM) + tid] = shared[tid];
} | #include <hip/hip_runtime.h>
#define NUM 512
__device__ inline void swap(int & a, int & b)
{
// Alternative swap doesn't use a temporary register:
// a ^= b;
// b ^= a;
// a ^= b;
int tmp = a;
a = b;
b = tmp;
}
__global__ static void bitonicSort(int * values, int *results)
{
extern __shared__ int shared[];
const unsigned int tid = threadIdx.x;
const unsigned int bid = blockIdx.x;
// Copy input to shared mem.
shared[tid] = values[(bid*NUM) + tid];
__syncthreads();
// Parallel bitonic sort.
for (unsigned int k = 2; k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2; j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
else
{
if (shared[tid] < shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
}
__syncthreads();
}
}
// Write result.
results[(bid*NUM) + tid] = shared[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define NUM 512
__device__ inline void swap(int & a, int & b)
{
// Alternative swap doesn't use a temporary register:
// a ^= b;
// b ^= a;
// a ^= b;
int tmp = a;
a = b;
b = tmp;
}
__global__ static void bitonicSort(int * values, int *results)
{
extern __shared__ int shared[];
const unsigned int tid = threadIdx.x;
const unsigned int bid = blockIdx.x;
// Copy input to shared mem.
shared[tid] = values[(bid*NUM) + tid];
__syncthreads();
// Parallel bitonic sort.
for (unsigned int k = 2; k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2; j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
else
{
if (shared[tid] < shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
}
__syncthreads();
}
}
// Write result.
results[(bid*NUM) + tid] = shared[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL11bitonicSortPiS_,"axG",@progbits,_ZL11bitonicSortPiS_,comdat
.globl _ZL11bitonicSortPiS_
.p2align 8
.type _ZL11bitonicSortPiS_,@function
_ZL11bitonicSortPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_lshl_add_u32 v1, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, 2
global_load_b32 v4, v[3:4], off
v_lshl_add_u32 v3, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_lshl_b32 s2, s3, 1
s_cmpk_gt_u32 s3, 0x100
s_mov_b32 s3, s2
s_cbranch_scc1 .LBB0_11
.LBB0_2:
v_and_b32_e32 v4, s3, v0
s_mov_b32 s4, s3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s5, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
.LBB0_4:
s_mov_b32 s5, s4
s_lshr_b32 s4, s4, 1
s_mov_b32 s6, exec_lo
v_xor_b32_e32 v4, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v4, v0
s_cbranch_execz .LBB0_3
v_lshl_add_u32 v4, v4, 2, 0
s_mov_b32 s7, 0
ds_load_b32 v5, v3
ds_load_b32 v6, v4
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s2
s_cbranch_execz .LBB0_7
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s2, v5, v6
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s7, s2, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, v5, v6
s_and_not1_b32 s7, s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s7, s7, s2
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v6
ds_store_b32 v4, v5
s_branch .LBB0_3
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v3, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL11bitonicSortPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL11bitonicSortPiS_,"axG",@progbits,_ZL11bitonicSortPiS_,comdat
.Lfunc_end0:
.size _ZL11bitonicSortPiS_, .Lfunc_end0-_ZL11bitonicSortPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL11bitonicSortPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL11bitonicSortPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define NUM 512
__device__ inline void swap(int & a, int & b)
{
// Alternative swap doesn't use a temporary register:
// a ^= b;
// b ^= a;
// a ^= b;
int tmp = a;
a = b;
b = tmp;
}
__global__ static void bitonicSort(int * values, int *results)
{
extern __shared__ int shared[];
const unsigned int tid = threadIdx.x;
const unsigned int bid = blockIdx.x;
// Copy input to shared mem.
shared[tid] = values[(bid*NUM) + tid];
__syncthreads();
// Parallel bitonic sort.
for (unsigned int k = 2; k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2; j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
else
{
if (shared[tid] < shared[ixj])
{
swap(shared[tid], shared[ixj]);
}
}
}
__syncthreads();
}
}
// Write result.
results[(bid*NUM) + tid] = shared[tid];
} | .text
.file "bitonicKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017f30f_00000000-6_bitonicKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL11bitonicSortPiS_, @function
_ZL11bitonicSortPiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL11bitonicSortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _ZL11bitonicSortPiS_, .-_ZL11bitonicSortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11bitonicSortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11bitonicSortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonicKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
__global__ void fPixelGenerator(int width, unsigned char* pic) {
int frame = threadIdx.x; // ID da thread
for (int row = 0; row < width; row++) {
for (int col = 0; col < width; col++) {
float fx = col - 1024/2;
float fy = row - 1024/2;
float d = sqrtf( fx * fx + fy * fy );
unsigned char color = (unsigned char) (160.0f + 127.0f * cos(d/10.0f - frame/7.0f) / (d/50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char) color;
}
}
}
static void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
}
else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
unsigned char* pic = NULL;
cudaMallocManaged(&pic, frames * width * width * sizeof(unsigned char));
// start time
timeval start, end;
gettimeofday(&start, NULL);
// Pixel Generator
fPixelGenerator<<<1, frames>>>(width, pic);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// verify result by writing frames to BMP files
if ((width <= 256) && (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
// Free memory
cudaFree(pic);
return 0;
} | .file "tmpxft_00042cb8_00000000-6_wavecuda1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
#NO_APP
.text
.type _ZL8writeBMPiiPKhPKc, @function
_ZL8writeBMPiiPKhPKc:
.LFB3669:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movl %edi, %r15d
movl %esi, %r12d
movq %rdx, %rbx
movq %rcx, %rdi
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
movabsq $281474976664898, %rax
movabsq $11258999139074048, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movq $-65536, %rax
movabsq $34359869439, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $1064256886942924800, %rax
movl $247726080, %edx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movq $0, 46(%rsp)
leal 3(%r15), %ecx
andl $-4, %ecx
movl %ecx, %r13d
subl %r15d, %r13d
movl $0, %eax
.L2:
movzbl (%rsp,%rax), %edx
movb %dl, 64(%rsp,%rax)
addq $1, %rax
cmpq $54, %rax
jne .L2
movl %ecx, 82(%rsp)
movl %r12d, 86(%rsp)
imull %r12d, %ecx
movl %ecx, 98(%rsp)
addl $1078, %ecx
movl %ecx, 66(%rsp)
leaq 118(%rsp), %rax
movl $0, %edx
.L3:
movb %dl, (%rax)
movb $0, 1(%rax)
movb $0, 2(%rax)
movb $0, 3(%rax)
addl $1, %edx
addq $4, %rax
cmpl $256, %edx
jne .L3
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %rax, %rcx
movl $1078, %edx
movl $1, %esi
call fwrite@PLT
testl %r13d, %r13d
je .L12
movl $0, 64(%rsp)
testl %r12d, %r12d
jle .L5
movslq %r15d, %r15
movl $0, %ebp
movslq %r13d, %r13
.L6:
movq %r14, %rcx
movq %r15, %rdx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movq %r13, %rdx
movl $1, %esi
call fwrite@PLT
addl $1, %ebp
addq %r15, %rbx
cmpl %ebp, %r12d
jne .L6
.L5:
movq %r14, %rdi
call fclose@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
imull %r15d, %r12d
movslq %r12d, %rdx
movq %r14, %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
jmp .L5
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _ZL8writeBMPiiPKhPKc, .-_ZL8writeBMPiiPKhPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15fPixelGeneratoriPhiPh
.type _Z36__device_stub__Z15fPixelGeneratoriPhiPh, @function
_Z36__device_stub__Z15fPixelGeneratoriPhiPh:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15fPixelGeneratoriPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z15fPixelGeneratoriPhiPh, .-_Z36__device_stub__Z15fPixelGeneratoriPhiPh
.globl _Z15fPixelGeneratoriPh
.type _Z15fPixelGeneratoriPh, @function
_Z15fPixelGeneratoriPh:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15fPixelGeneratoriPhiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z15fPixelGeneratoriPh, .-_Z15fPixelGeneratoriPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s frame_width num_frames\n"
.align 8
.LC2:
.string "error: frame_width must be at least 100\n"
.align 8
.LC3:
.string "error: num_frames must be at least 1\n"
.align 8
.LC4:
.string "computing %d frames of %d by %d picture\n"
.section .rodata.str1.1
.LC6:
.string "compute time: %.4f s\n"
.LC7:
.string "wave%d.bmp"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L34
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
cmpl $99, %eax
jle .L35
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %edx
testl %eax, %eax
jle .L36
movl %ebp, %r8d
movl %ebp, %ecx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 8(%rsp)
movl %r12d, %esi
imull %ebp, %esi
imull %ebp, %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %r12d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
movsd .LC5(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
subsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $256, %ebp
jg .L29
cmpl $100, %r12d
jg .L29
imull %ebp, %ebp
movslq %ebp, %rbp
addl $1000, %r12d
movl $0, %r13d
movl $1000, %ebx
.L30:
leaq 64(%rsp), %r14
movl %ebx, %r8d
leaq .LC7(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq %r13, %rdx
addq 8(%rsp), %rdx
movq %r14, %rcx
movl %r15d, %esi
movl %r15d, %edi
call _ZL8writeBMPiiPKhPKc
addl $1, %ebx
addq %rbp, %r13
cmpl %r12d, %ebx
jne .L30
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z36__device_stub__Z15fPixelGeneratoriPhiPh
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z15fPixelGeneratoriPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15fPixelGeneratoriPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
__global__ void fPixelGenerator(int width, unsigned char* pic) {
int frame = threadIdx.x; // ID da thread
for (int row = 0; row < width; row++) {
for (int col = 0; col < width; col++) {
float fx = col - 1024/2;
float fy = row - 1024/2;
float d = sqrtf( fx * fx + fy * fy );
unsigned char color = (unsigned char) (160.0f + 127.0f * cos(d/10.0f - frame/7.0f) / (d/50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char) color;
}
}
}
static void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
}
else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
unsigned char* pic = NULL;
cudaMallocManaged(&pic, frames * width * width * sizeof(unsigned char));
// start time
timeval start, end;
gettimeofday(&start, NULL);
// Pixel Generator
fPixelGenerator<<<1, frames>>>(width, pic);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// verify result by writing frames to BMP files
if ((width <= 256) && (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
// Free memory
cudaFree(pic);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
__global__ void fPixelGenerator(int width, unsigned char* pic) {
int frame = threadIdx.x; // ID da thread
for (int row = 0; row < width; row++) {
for (int col = 0; col < width; col++) {
float fx = col - 1024/2;
float fy = row - 1024/2;
float d = sqrtf( fx * fx + fy * fy );
unsigned char color = (unsigned char) (160.0f + 127.0f * cos(d/10.0f - frame/7.0f) / (d/50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char) color;
}
}
}
static void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
}
else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
unsigned char* pic = NULL;
hipMallocManaged(&pic, frames * width * width * sizeof(unsigned char));
// start time
timeval start, end;
gettimeofday(&start, NULL);
// Pixel Generator
fPixelGenerator<<<1, frames>>>(width, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// verify result by writing frames to BMP files
if ((width <= 256) && (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
// Free memory
hipFree(pic);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
__global__ void fPixelGenerator(int width, unsigned char* pic) {
int frame = threadIdx.x; // ID da thread
for (int row = 0; row < width; row++) {
for (int col = 0; col < width; col++) {
float fx = col - 1024/2;
float fy = row - 1024/2;
float d = sqrtf( fx * fx + fy * fy );
unsigned char color = (unsigned char) (160.0f + 127.0f * cos(d/10.0f - frame/7.0f) / (d/50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char) color;
}
}
}
static void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
}
else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
unsigned char* pic = NULL;
hipMallocManaged(&pic, frames * width * width * sizeof(unsigned char));
// start time
timeval start, end;
gettimeofday(&start, NULL);
// Pixel Generator
fPixelGenerator<<<1, frames>>>(width, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// verify result by writing frames to BMP files
if ((width <= 256) && (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
// Free memory
hipFree(pic);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15fPixelGeneratoriPh
.globl _Z15fPixelGeneratoriPh
.p2align 8
.type _Z15fPixelGeneratoriPh,@function
_Z15fPixelGeneratoriPh:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_9
v_cvt_f32_i32_e32 v1, v0
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s0, s4, s4
s_mov_b32 s5, 0
v_mul_lo_u32 v0, v0, s0
v_div_scale_f32 v2, null, 0x40e00000, 0x40e00000, v1
v_div_scale_f32 v5, vcc_lo, v1, 0x40e00000, v1
s_mov_b32 s6, 0x7fffff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_mov_b32 s7, 0xb94c1982
s_mov_b32 s8, 0x37d75334
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v1, v2, 0x40e00000, v1
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v0, s4, v0
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, s4
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_add_i32 s0, s5, 0xfffffe00
s_mov_b32 s9, 0
v_cvt_f32_i32_e32 v2, s0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
v_div_scale_f32 v7, null, 0x42480000, 0x42480000, v3
v_div_scale_f32 v13, vcc_lo, v3, 0x42480000, v3
v_and_b32_e32 v14, 1, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v7
v_lshlrev_b32_e32 v6, 30, v6
v_cmp_eq_u32_e64 s0, 0, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_and_b32_e32 v6, 0x80000000, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v7, v8, 1.0
v_dual_mul_f32 v9, v5, v5 :: v_dual_fmac_f32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v11, s7, v9, 0x3c0881c4
v_fmaak_f32 v10, v9, v11, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v10
v_dual_fmaak_f32 v12, s8, v9, 0xbab64f3b :: v_dual_fmac_f32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v11, v9, v12, 0x3d2aabf7
v_mul_f32_e32 v12, v13, v8
v_fmaak_f32 v11, v9, v11, 0xbf000004
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v7, v12, v13
v_fma_f32 v9, v9, v11, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v15, v8
v_cndmask_b32_e64 v5, -v5, v9, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v7, v12, v13
v_xor_b32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v6, v7, v8, v12
v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
v_mul_f32_e32 v5, 0x42fe0000, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v6, 0x42480000, v3
v_dual_cndmask_b32 v4, 0x7fc00000, v5 :: v_dual_add_f32 v3, 1.0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v3, v3, v4
v_div_scale_f32 v8, vcc_lo, v4, v3, v4
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_div_fixup_f32 v3, v5, v3, v4
v_add_nc_u32_e32 v4, s9, v0
s_add_i32 s9, s9, 1
s_cmp_eq_u32 s4, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, 0x43200000, v3
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v5, vcc_lo
global_store_b8 v[3:4], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_5:
s_add_i32 s0, s9, 0xfffffe00
s_mov_b32 s1, exec_lo
v_cvt_f32_i32_e32 v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v3, v3, v2
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_div_scale_f32 v4, null, 0x41200000, 0x41200000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, 0x41200000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v4, v4, 0x41200000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v1
v_cmpx_ngt_f32_e64 0x48000000, |v4|
s_xor_b32 s10, exec_lo, s1
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v12, 0x7fffffff, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v15, v12, s6, 0x800000
v_lshrrev_b32_e32 v12, 23, v12
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v13, 0xffffff88, v12
v_cmp_lt_u32_e32 vcc_lo, 63, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v13
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 31, v14
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
v_add_nc_u32_e32 v16, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
v_cmp_lt_u32_e64 s1, 31, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v11
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
v_cndmask_b32_e64 v5, v8, v5, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v12
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v6, v13
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v7, v12, v10 :: v_dual_add_nc_u32 v6, v6, v16
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v14, v12
v_cndmask_b32_e32 v11, v11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e64 v10, v13, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s0
v_cndmask_b32_e64 v7, v7, v11, s0
v_sub_nc_u32_e32 v13, 32, v6
v_cndmask_b32_e64 v11, v11, v8, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s1
v_cndmask_b32_e64 v10, v10, v7, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v11, s1
v_cndmask_b32_e64 v5, v11, v5, s1
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v7, v13
v_cndmask_b32_e32 v6, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v7, v5, v13
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v6, 29, 1
v_cndmask_b32_e32 v7, v12, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v6, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v5, v7, v5, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v8, v11
v_xor_b32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v7, v8
v_alignbit_b32 v5, v7, v5, v8
v_lshrrev_b32_e32 v8, 29, v6
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v10, v5, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, v9, v6
v_clz_i32_u32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v13, 0.5, v8
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v14
v_sub_nc_u32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v7, v5, v15
v_or_b32_e32 v7, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v5, 9, v5
v_mul_f32_e32 v11, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v10
v_fma_f32 v10, v7, 0x3fc90fda, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fmac_f32_e32 v10, 0x33a22168, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v5, v8
v_fmac_f32_e32 v10, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v11, v10
.LBB0_7:
s_and_not1_saveexec_b32 s0, s10
s_cbranch_execz .LBB0_4
v_mul_f32_e64 v5, 0x3f22f983, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0xb3a22168, v6
v_fmac_f32_e32 v5, 0xa7c234c4, v6
v_cvt_i32_f32_e32 v6, v6
s_branch .LBB0_4
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15fPixelGeneratoriPh
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15fPixelGeneratoriPh, .Lfunc_end0-_Z15fPixelGeneratoriPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15fPixelGeneratoriPh
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z15fPixelGeneratoriPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <stdio.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
__global__ void fPixelGenerator(int width, unsigned char* pic) {
int frame = threadIdx.x; // ID da thread
for (int row = 0; row < width; row++) {
for (int col = 0; col < width; col++) {
float fx = col - 1024/2;
float fy = row - 1024/2;
float d = sqrtf( fx * fx + fy * fy );
unsigned char color = (unsigned char) (160.0f + 127.0f * cos(d/10.0f - frame/7.0f) / (d/50.0f + 1.0f));
pic[frame * width * width + row * width + col] = (unsigned char) color;
}
}
}
static void writeBMP(const int x, const int y, const unsigned char* const bmp, const char* const name) {
const unsigned char bmphdr[54] = {66, 77, 255, 255, 255, 255, 0, 0, 0, 0, 54, 4, 0, 0, 40, 0, 0, 0, 255, 255, 255, 255, 255, 255, 255, 255, 1, 0, 8, 0, 0, 0, 0, 0, 255, 255, 255, 255, 196, 14, 0, 0, 196, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
unsigned char hdr[1078];
int i, j, c, xcorr, diff;
FILE* f;
xcorr = (x + 3) >> 2 << 2; // BMPs have to be a multiple of 4 pixels wide
diff = xcorr - x;
for (i = 0; i < 54; i++) hdr[i] = bmphdr[i];
*((int*)(&hdr[18])) = xcorr;
*((int*)(&hdr[22])) = y;
*((int*)(&hdr[34])) = xcorr * y;
*((int*)(&hdr[2])) = xcorr * y + 1078;
for (i = 0; i < 256; i++) {
j = i * 4 + 54;
hdr[j+0] = i; // blue ColorTable
hdr[j+1] = 0; // green
hdr[j+2] = 0; // red
hdr[j+3] = 0; // dummy
}
f = fopen(name, "wb"); assert(f != NULL);
c = fwrite(hdr, 1, 1078, f); assert(c == 1078);
if (diff == 0) {
c = fwrite(bmp, 1, x * y, f); assert(c == x * y);
}
else {
*((int*)(&hdr[0])) = 0; // need up to three zero bytes
for (j = 0; j < y; j++) {
c = fwrite(&bmp[j * x], 1, x, f); assert(c == x);
c = fwrite(hdr, 1, diff, f); assert(c == diff);
}
}
fclose(f);
}
int main(int argc, char *argv[]) {
// check command line
if (argc != 3) {
fprintf(stderr, "usage: %s frame_width num_frames\n", argv[0]);
exit(-1);
}
int width = atoi(argv[1]);
if (width < 100) {
fprintf(stderr, "error: frame_width must be at least 100\n");
exit(-1);
}
int frames = atoi(argv[2]);
if (frames < 1) {
fprintf(stderr, "error: num_frames must be at least 1\n");
exit(-1);
}
printf("computing %d frames of %d by %d picture\n", frames, width, width);
// allocate picture array
unsigned char* pic = NULL;
hipMallocManaged(&pic, frames * width * width * sizeof(unsigned char));
// start time
timeval start, end;
gettimeofday(&start, NULL);
// Pixel Generator
fPixelGenerator<<<1, frames>>>(width, pic);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
double runtime = end.tv_sec + end.tv_usec / 1000000.0 - start.tv_sec - start.tv_usec / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// verify result by writing frames to BMP files
if ((width <= 256) && (frames <= 100)) {
for (int frame = 0; frame < frames; frame++) {
char name[32];
sprintf(name, "wave%d.bmp", frame + 1000);
writeBMP(width, width, &pic[frame * width * width], name);
}
}
// Free memory
hipFree(pic);
return 0;
} | .text
.file "wavecuda1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__fPixelGeneratoriPh # -- Begin function _Z30__device_stub__fPixelGeneratoriPh
.p2align 4, 0x90
.type _Z30__device_stub__fPixelGeneratoriPh,@function
_Z30__device_stub__fPixelGeneratoriPh: # @_Z30__device_stub__fPixelGeneratoriPh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15fPixelGeneratoriPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__fPixelGeneratoriPh, .Lfunc_end0-_Z30__device_stub__fPixelGeneratoriPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1256, %rsp # imm = 0x4E8
.cfi_def_cfa_offset 1312
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB1_19
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
cmpl $99, %r15d
jle .LBB1_2
# %bb.4:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB1_5
# %bb.6:
movl $.L.str.3, %edi
movl %r14d, %esi
movl %r15d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movq $0, 8(%rsp)
movl %r15d, %esi
imull %esi, %esi
imull %r14d, %esi
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r14d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movl %r15d, 20(%rsp)
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z15fPixelGeneratoriPh, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 24(%rsp), %xmm1
cvtsi2sdq 32(%rsp), %xmm0
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
subsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 136(%rsp), %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
cmpl $256, %r15d # imm = 0x100
jg .LBB1_18
# %bb.9:
cmpl $100, %r14d
jg .LBB1_18
# %bb.10: # %.lr.ph
movq %r15, %r13
imulq %r15, %r13
leal 3(%r15), %eax
andl $2147483644, %eax # imm = 0x7FFFFFFC
movl %eax, %ecx
imull %r15d, %ecx
movq %rcx, 56(%rsp) # 8-byte Spill
addl $1078, %ecx # imm = 0x436
movl %ecx, 16(%rsp) # 4-byte Spill
movl %eax, 4(%rsp) # 4-byte Spill
subl %r15d, %eax
movl %r15d, %ebx
movslq %eax, %r12
cmpl $2, %r14d
movl $1, %eax
cmovgel %r14d, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl %r13d, %eax
movq %rax, 40(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %eax, %eax
movq %r15, 72(%rsp) # 8-byte Spill
movq %r13, 64(%rsp) # 8-byte Spill
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_11 Depth=1
addq 80(%rsp), %r14 # 8-byte Folded Reload
movl $1, %esi
movq %r14, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movq %r13, %rcx
callq fwrite
.LBB1_17: # %_ZL8writeBMPiiPKhPKc.exit
# in Loop: Header=BB1_11 Depth=1
movq %r13, %rdi
callq fclose
movq 88(%rsp), %rax # 8-byte Reload
incq %rax
movq 64(%rsp), %r13 # 8-byte Reload
movq 96(%rsp), %rbp # 8-byte Reload
addl %r13d, %ebp
cmpq 48(%rsp), %rax # 8-byte Folded Reload
je .LBB1_18
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_16 Depth 2
movl %ebp, %ebp
leal 1000(%rax), %edx
movl $.L.str.5, %esi
leaq 144(%rsp), %rdi
movq %rax, %r15
xorl %eax, %eax
callq sprintf
movq 8(%rsp), %r14
# kill: def $r13d killed $r13d killed $r13 def $r13
movq %r15, 88(%rsp) # 8-byte Spill
imull %r15d, %r13d
movq %r13, 80(%rsp) # 8-byte Spill
movq 72(%rsp), %r15 # 8-byte Reload
movw $19778, 176(%rsp) # imm = 0x4D42
movl $4294967295, %eax # imm = 0xFFFFFFFF
movq %rax, 178(%rsp)
movabsq $171798692918, %rax # imm = 0x2800000436
movq %rax, 186(%rsp)
movq $-1, 194(%rsp)
movw $1, 202(%rsp)
movb $8, 204(%rsp)
leaq 205(%rsp), %rax
movb $0, 4(%rax)
movl $0, (%rax)
movabsq $16239271346175, %rcx # imm = 0xEC4FFFFFFFF
movq %rcx, 210(%rsp)
movw $3780, 218(%rsp) # imm = 0xEC4
movw $0, 23(%rax)
movq $0, 15(%rax)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 194(%rsp)
movl %r15d, 198(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 210(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 178(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movb %al, 230(%rsp,%rax,4)
movw $0, 231(%rsp,%rax,4)
movb $0, 233(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $.L.str.6, %esi
leaq 144(%rsp), %rdi
callq fopen
movq %rax, %r13
movl $1, %esi
movl $1078, %edx # imm = 0x436
leaq 176(%rsp), %rdi
movq %rax, %rcx
callq fwrite
cmpl %r15d, 4(%rsp) # 4-byte Folded Reload
movq %rbp, 96(%rsp) # 8-byte Spill
je .LBB1_14
# %bb.15: # %.lr.ph.i
# in Loop: Header=BB1_11 Depth=1
movl $0, 176(%rsp)
addq %rbp, %r14
movq %rbx, %r15
leaq 176(%rsp), %rbp
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %r13, %rcx
callq fwrite
movl $1, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
callq fwrite
addq %rbx, %r14
decq %r15
jne .LBB1_16
jmp .LBB1_17
.LBB1_18: # %.loopexit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1256, %rsp # imm = 0x4E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 1312
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_2:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $40, %esi
jmp .LBB1_3
.LBB1_5:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $37, %esi
.LBB1_3:
movl $1, %edx
callq fwrite
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15fPixelGeneratoriPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15fPixelGeneratoriPh,@object # @_Z15fPixelGeneratoriPh
.section .rodata,"a",@progbits
.globl _Z15fPixelGeneratoriPh
.p2align 3, 0x0
_Z15fPixelGeneratoriPh:
.quad _Z30__device_stub__fPixelGeneratoriPh
.size _Z15fPixelGeneratoriPh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s frame_width num_frames\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "error: frame_width must be at least 100\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error: num_frames must be at least 1\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "computing %d frames of %d by %d picture\n"
.size .L.str.3, 41
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "compute time: %.4f s\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wave%d.bmp"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "wb"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15fPixelGeneratoriPh"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__fPixelGeneratoriPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15fPixelGeneratoriPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00042cb8_00000000-6_wavecuda1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
#NO_APP
.text
.type _ZL8writeBMPiiPKhPKc, @function
_ZL8writeBMPiiPKhPKc:
.LFB3669:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1160, %rsp
.cfi_def_cfa_offset 1216
movl %edi, %r15d
movl %esi, %r12d
movq %rdx, %rbx
movq %rcx, %rdi
movq %fs:40, %rax
movq %rax, 1144(%rsp)
xorl %eax, %eax
movabsq $281474976664898, %rax
movabsq $11258999139074048, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
movq $-65536, %rax
movabsq $34359869439, %rdx
movq %rax, 16(%rsp)
movq %rdx, 24(%rsp)
movabsq $1064256886942924800, %rax
movl $247726080, %edx
movq %rax, 32(%rsp)
movq %rdx, 40(%rsp)
movq $0, 46(%rsp)
leal 3(%r15), %ecx
andl $-4, %ecx
movl %ecx, %r13d
subl %r15d, %r13d
movl $0, %eax
.L2:
movzbl (%rsp,%rax), %edx
movb %dl, 64(%rsp,%rax)
addq $1, %rax
cmpq $54, %rax
jne .L2
movl %ecx, 82(%rsp)
movl %r12d, 86(%rsp)
imull %r12d, %ecx
movl %ecx, 98(%rsp)
addl $1078, %ecx
movl %ecx, 66(%rsp)
leaq 118(%rsp), %rax
movl $0, %edx
.L3:
movb %dl, (%rax)
movb $0, 1(%rax)
movb $0, 2(%rax)
movb $0, 3(%rax)
addl $1, %edx
addq $4, %rax
cmpl $256, %edx
jne .L3
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r14
leaq 64(%rsp), %rdi
movq %rax, %rcx
movl $1078, %edx
movl $1, %esi
call fwrite@PLT
testl %r13d, %r13d
je .L12
movl $0, 64(%rsp)
testl %r12d, %r12d
jle .L5
movslq %r15d, %r15
movl $0, %ebp
movslq %r13d, %r13
.L6:
movq %r14, %rcx
movq %r15, %rdx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r14, %rcx
movq %r13, %rdx
movl $1, %esi
call fwrite@PLT
addl $1, %ebp
addq %r15, %rbx
cmpl %ebp, %r12d
jne .L6
.L5:
movq %r14, %rdi
call fclose@PLT
movq 1144(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $1160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
imull %r15d, %r12d
movslq %r12d, %rdx
movq %r14, %rcx
movl $1, %esi
movq %rbx, %rdi
call fwrite@PLT
jmp .L5
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _ZL8writeBMPiiPKhPKc, .-_ZL8writeBMPiiPKhPKc
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z15fPixelGeneratoriPhiPh
.type _Z36__device_stub__Z15fPixelGeneratoriPhiPh, @function
_Z36__device_stub__Z15fPixelGeneratoriPhiPh:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15fPixelGeneratoriPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z15fPixelGeneratoriPhiPh, .-_Z36__device_stub__Z15fPixelGeneratoriPhiPh
.globl _Z15fPixelGeneratoriPh
.type _Z15fPixelGeneratoriPh, @function
_Z15fPixelGeneratoriPh:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15fPixelGeneratoriPhiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z15fPixelGeneratoriPh, .-_Z15fPixelGeneratoriPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s frame_width num_frames\n"
.align 8
.LC2:
.string "error: frame_width must be at least 100\n"
.align 8
.LC3:
.string "error: num_frames must be at least 1\n"
.align 8
.LC4:
.string "computing %d frames of %d by %d picture\n"
.section .rodata.str1.1
.LC6:
.string "compute time: %.4f s\n"
.LC7:
.string "wave%d.bmp"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L34
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
cmpl $99, %eax
jle .L35
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %edx
testl %eax, %eax
jle .L36
movl %ebp, %r8d
movl %ebp, %ecx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 8(%rsp)
movl %r12d, %esi
imull %ebp, %esi
imull %ebp, %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %r12d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
movsd .LC5(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
subsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $256, %ebp
jg .L29
cmpl $100, %r12d
jg .L29
imull %ebp, %ebp
movslq %ebp, %rbp
addl $1000, %r12d
movl $0, %r13d
movl $1000, %ebx
.L30:
leaq 64(%rsp), %r14
movl %ebx, %r8d
leaq .LC7(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __sprintf_chk@PLT
movq %r13, %rdx
addq 8(%rsp), %rdx
movq %r14, %rcx
movl %r15d, %esi
movl %r15d, %edi
call _ZL8writeBMPiiPKhPKc
addl $1, %ebx
addq %rbp, %r13
cmpl %r12d, %ebx
jne .L30
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z36__device_stub__Z15fPixelGeneratoriPhiPh
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z15fPixelGeneratoriPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15fPixelGeneratoriPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wavecuda1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__fPixelGeneratoriPh # -- Begin function _Z30__device_stub__fPixelGeneratoriPh
.p2align 4, 0x90
.type _Z30__device_stub__fPixelGeneratoriPh,@function
_Z30__device_stub__fPixelGeneratoriPh: # @_Z30__device_stub__fPixelGeneratoriPh
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15fPixelGeneratoriPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z30__device_stub__fPixelGeneratoriPh, .Lfunc_end0-_Z30__device_stub__fPixelGeneratoriPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1256, %rsp # imm = 0x4E8
.cfi_def_cfa_offset 1312
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB1_19
# %bb.1:
movq 8(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
cmpl $99, %r15d
jle .LBB1_2
# %bb.4:
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
testl %r14d, %r14d
jle .LBB1_5
# %bb.6:
movl $.L.str.3, %edi
movl %r14d, %esi
movl %r15d, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq printf
movq $0, 8(%rsp)
movl %r15d, %esi
imull %esi, %esi
imull %r14d, %esi
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r14d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movl %r15d, 20(%rsp)
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 144(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z15fPixelGeneratoriPh, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 24(%rsp), %xmm1
cvtsi2sdq 32(%rsp), %xmm0
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 128(%rsp), %xmm1
subsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 136(%rsp), %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
cmpl $256, %r15d # imm = 0x100
jg .LBB1_18
# %bb.9:
cmpl $100, %r14d
jg .LBB1_18
# %bb.10: # %.lr.ph
movq %r15, %r13
imulq %r15, %r13
leal 3(%r15), %eax
andl $2147483644, %eax # imm = 0x7FFFFFFC
movl %eax, %ecx
imull %r15d, %ecx
movq %rcx, 56(%rsp) # 8-byte Spill
addl $1078, %ecx # imm = 0x436
movl %ecx, 16(%rsp) # 4-byte Spill
movl %eax, 4(%rsp) # 4-byte Spill
subl %r15d, %eax
movl %r15d, %ebx
movslq %eax, %r12
cmpl $2, %r14d
movl $1, %eax
cmovgel %r14d, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl %r13d, %eax
movq %rax, 40(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %eax, %eax
movq %r15, 72(%rsp) # 8-byte Spill
movq %r13, 64(%rsp) # 8-byte Spill
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_11 Depth=1
addq 80(%rsp), %r14 # 8-byte Folded Reload
movl $1, %esi
movq %r14, %rdi
movq 40(%rsp), %rdx # 8-byte Reload
movq %r13, %rcx
callq fwrite
.LBB1_17: # %_ZL8writeBMPiiPKhPKc.exit
# in Loop: Header=BB1_11 Depth=1
movq %r13, %rdi
callq fclose
movq 88(%rsp), %rax # 8-byte Reload
incq %rax
movq 64(%rsp), %r13 # 8-byte Reload
movq 96(%rsp), %rbp # 8-byte Reload
addl %r13d, %ebp
cmpq 48(%rsp), %rax # 8-byte Folded Reload
je .LBB1_18
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_16 Depth 2
movl %ebp, %ebp
leal 1000(%rax), %edx
movl $.L.str.5, %esi
leaq 144(%rsp), %rdi
movq %rax, %r15
xorl %eax, %eax
callq sprintf
movq 8(%rsp), %r14
# kill: def $r13d killed $r13d killed $r13 def $r13
movq %r15, 88(%rsp) # 8-byte Spill
imull %r15d, %r13d
movq %r13, 80(%rsp) # 8-byte Spill
movq 72(%rsp), %r15 # 8-byte Reload
movw $19778, 176(%rsp) # imm = 0x4D42
movl $4294967295, %eax # imm = 0xFFFFFFFF
movq %rax, 178(%rsp)
movabsq $171798692918, %rax # imm = 0x2800000436
movq %rax, 186(%rsp)
movq $-1, 194(%rsp)
movw $1, 202(%rsp)
movb $8, 204(%rsp)
leaq 205(%rsp), %rax
movb $0, 4(%rax)
movl $0, (%rax)
movabsq $16239271346175, %rcx # imm = 0xEC4FFFFFFFF
movq %rcx, 210(%rsp)
movw $3780, 218(%rsp) # imm = 0xEC4
movw $0, 23(%rax)
movq $0, 15(%rax)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 194(%rsp)
movl %r15d, 198(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 210(%rsp)
movl 16(%rsp), %eax # 4-byte Reload
movl %eax, 178(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movb %al, 230(%rsp,%rax,4)
movw $0, 231(%rsp,%rax,4)
movb $0, 233(%rsp,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $.L.str.6, %esi
leaq 144(%rsp), %rdi
callq fopen
movq %rax, %r13
movl $1, %esi
movl $1078, %edx # imm = 0x436
leaq 176(%rsp), %rdi
movq %rax, %rcx
callq fwrite
cmpl %r15d, 4(%rsp) # 4-byte Folded Reload
movq %rbp, 96(%rsp) # 8-byte Spill
je .LBB1_14
# %bb.15: # %.lr.ph.i
# in Loop: Header=BB1_11 Depth=1
movl $0, 176(%rsp)
addq %rbp, %r14
movq %rbx, %r15
leaq 176(%rsp), %rbp
.p2align 4, 0x90
.LBB1_16: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %r13, %rcx
callq fwrite
movl $1, %esi
movq %rbp, %rdi
movq %r12, %rdx
movq %r13, %rcx
callq fwrite
addq %rbx, %r14
decq %r15
jne .LBB1_16
jmp .LBB1_17
.LBB1_18: # %.loopexit
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1256, %rsp # imm = 0x4E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 1312
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB1_2:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $40, %esi
jmp .LBB1_3
.LBB1_5:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $37, %esi
.LBB1_3:
movl $1, %edx
callq fwrite
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15fPixelGeneratoriPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15fPixelGeneratoriPh,@object # @_Z15fPixelGeneratoriPh
.section .rodata,"a",@progbits
.globl _Z15fPixelGeneratoriPh
.p2align 3, 0x0
_Z15fPixelGeneratoriPh:
.quad _Z30__device_stub__fPixelGeneratoriPh
.size _Z15fPixelGeneratoriPh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s frame_width num_frames\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "error: frame_width must be at least 100\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error: num_frames must be at least 1\n"
.size .L.str.2, 38
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "computing %d frames of %d by %d picture\n"
.size .L.str.3, 41
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "compute time: %.4f s\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wave%d.bmp"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "wb"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15fPixelGeneratoriPh"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__fPixelGeneratoriPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15fPixelGeneratoriPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <vector_types.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <iostream>
#include <vector>
#include <ctime>
#include <cmath>
//#include <QDebug>
#define PI 3.14159265359
using namespace std;
template<class T>
class CudaArray
{
public:
CudaArray (int n) : dev{nullptr},nBytes{0}
{
try{
nBytes = n * sizeof(T);
cudaMalloc((void**)&dev,nBytes);
} catch (...){}
}
~CudaArray ()
{
try{
cudaFree (dev);
}
catch(...) {}
}
int getnBytes() const
{
return nBytes;
}
operator T* () const
{
return dev;
}
CudaArray& operator = (T* rhs) const
{
cudaMemcpy (dev,rhs,nBytes,cudaMemcpyHostToDevice);
}
void copyToCpu(T *cpu) const
{
cudaMemcpy (cpu,dev,nBytes,cudaMemcpyDeviceToHost);
}
private:
T *dev;
int nBytes;
};
__device__ float sinteta;
__device__ float costeta;
__global__ void kernelSetsincos(double teta)
{
sinteta = sin (teta);
costeta = cos (teta);
}
// http://habrahabr.ru/post/55461/ (c)
#define BLOCK_DIM 16
__global__ void kernelRotate(unsigned int* inputMatrix, unsigned int* outputMatrix, int width, int height)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int yIndex = blockDim.y * blockIdx.y + threadIdx.y;
if ((xIndex < width) && (yIndex < height))
{
//Линейный индекс элемента строки исходной матрицы
int inputIdx = xIndex + width * yIndex;
//Линейный индекс элемента столбца матрицы-результата
xIndex -= width / 2.0;
yIndex -= height / 2.0;
int nx = xIndex * costeta + yIndex * sinteta,
ny = -xIndex * sinteta + yIndex * costeta;
nx += width / 2.0;
ny += height / 2.0;
if (nx >= 0 && nx < width && ny >= 0 && ny < height){
int outputIdx = nx + width * ny;
outputMatrix[outputIdx] = inputMatrix[inputIdx];
}
}
// __shared__ float temp[BLOCK_DIM][BLOCK_DIM];
// int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
// int yIndex = blockIdx.y * blockDim.y + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// temp[threadIdx.y][threadIdx.x] = inputMatrix[idx];
// }
// //Синхронизируем все нити в блоке
// __syncthreads();
// xIndex = blockIdx.y * blockDim.y + threadIdx.x;
// yIndex = blockIdx.x * blockDim.x + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // xIndex -= width / 2.0;
// // yIndex -= height / 2.0;
// // float nx = xIndex * costeta + yIndex * sinteta,
// // ny = -xIndex * sinteta + yIndex * costeta;
// // nx += width / 2.0;
// // ny += height / 2.0;
// // //x[i] = xi * costeta + yi * sinteta;
// // //y[i] = -xi * sinteta + yi * costeta;
// // if (nx >= 0 && nx < width && ny >= 0 && ny < height){
// // // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// outputMatrix[idx] = temp[threadIdx.x][threadIdx.y];
// // }
// }
}
extern "C" void algoCudaRotate(unsigned char *input_output,int step,int rows,int cols,double angle)
{ // todo: Избавиться от не нужных копирований.
cudaMemset(&sinteta,0,sizeof(float));
cudaMemset(&costeta,0,sizeof(float));
kernelSetsincos<<<1,1>>> (-angle / 180.0 * PI);
// std::cerr << "sincos set\n";
int channels = 3,
width = cols, //cols * channels,
height = rows,
n = width * height,
bytesn = n * sizeof(int);
// std::cerr << "step: " << step << " rows: " << rows << " cols: " << cols << '\n';
unsigned int *data = new unsigned int [n];
for(int i = 0;i < height; ++i){ // Упаковка bgr в int 4 байта тип
for(int j = 0;j < width * channels; j += channels){
unsigned char b = input_output[step * i + j],
g = input_output[step * i + j + 1],
r = input_output[step * i + j + 2];
data[i * width + j / channels] = (int(b) << 16) | (int(g) << 8) | int(r);
}
}
//std::cerr << "array read\n";
CudaArray<unsigned int> inputimg(n),rotatedimg(n);
inputimg = data;
//std::cerr << "array copy to device\n";
dim3 gridSize = dim3(width / BLOCK_DIM, height / BLOCK_DIM, 1);
dim3 blockSize = dim3(BLOCK_DIM, BLOCK_DIM, 1);
kernelRotate<<< gridSize, blockSize >>> (inputimg,rotatedimg,width,height);
//std::cerr << "call kernel\n";
rotatedimg.copyToCpu(data);
// std::fill (input_output,input_output + height * step,0);
// std::cerr << "returen result to cpu mem\n";
for(int i = 0;i < height; ++i){ // распаковка
for(int j = 0;j < width * channels; j += channels){
unsigned int bgr = data[i * width + j / channels];
input_output[step * i + j] = (bgr >> 16);
input_output[step * i + j + 1] = (bgr & (255 << 8)) >> 8;
input_output[step * i + j + 2] = (bgr & 255);
}
}
cudaFree (&sinteta);
cudaFree (&costeta);
delete [] data;
}
extern "C" cudaError_t algoCuda_main()
{
return cudaGetLastError();
}
/* OpenCV data format
int limit = 10,
channel = 3;
unsigned char *input = img.data;
for(int i = 0;i < img.rows && limit ;i++){
for(int j = 0;j < img.cols * channel && limit; j += channel){
uchar b = input[img.step * i + j] ;
uchar g = input[img.step * i + j + 1];
uchar r = input[img.step * i + j + 2];
qDebug () << b << g << r;
limit--;
}
}
qDebug () << "next";
for (int i = 0; i < 10; i++){
cv::Vec3b intensity = img.at<cv::Vec3b>(0, i);
uchar b = intensity.val[0];
uchar g = intensity.val[1];
uchar r = intensity.val[2];
qDebug () << b << g << r;
}
/*
__global__ void kernCuda(float *Source,float * Destination, int width)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int i = abs(x*cosf(theta)-y*sinf(theta));
int j = abs(x*sinf(theta)+y*cosf(theta));
if(x<width && y<width){
Destination[j*width+i]=Source[y*width+x];
}
}
*/ | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <hip/hip_vector_types.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <ctime>
#include <cmath>
//#include <QDebug>
#define PI 3.14159265359
using namespace std;
template<class T>
class CudaArray
{
public:
CudaArray (int n) : dev{nullptr},nBytes{0}
{
try{
nBytes = n * sizeof(T);
hipMalloc((void**)&dev,nBytes);
} catch (...){}
}
~CudaArray ()
{
try{
hipFree (dev);
}
catch(...) {}
}
int getnBytes() const
{
return nBytes;
}
operator T* () const
{
return dev;
}
CudaArray& operator = (T* rhs) const
{
hipMemcpy (dev,rhs,nBytes,hipMemcpyHostToDevice);
}
void copyToCpu(T *cpu) const
{
hipMemcpy (cpu,dev,nBytes,hipMemcpyDeviceToHost);
}
private:
T *dev;
int nBytes;
};
__device__ float sinteta;
__device__ float costeta;
__global__ void kernelSetsincos(double teta)
{
sinteta = sin (teta);
costeta = cos (teta);
}
// http://habrahabr.ru/post/55461/ (c)
#define BLOCK_DIM 16
__global__ void kernelRotate(unsigned int* inputMatrix, unsigned int* outputMatrix, int width, int height)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int yIndex = blockDim.y * blockIdx.y + threadIdx.y;
if ((xIndex < width) && (yIndex < height))
{
//Линейный индекс элемента строки исходной матрицы
int inputIdx = xIndex + width * yIndex;
//Линейный индекс элемента столбца матрицы-результата
xIndex -= width / 2.0;
yIndex -= height / 2.0;
int nx = xIndex * costeta + yIndex * sinteta,
ny = -xIndex * sinteta + yIndex * costeta;
nx += width / 2.0;
ny += height / 2.0;
if (nx >= 0 && nx < width && ny >= 0 && ny < height){
int outputIdx = nx + width * ny;
outputMatrix[outputIdx] = inputMatrix[inputIdx];
}
}
// __shared__ float temp[BLOCK_DIM][BLOCK_DIM];
// int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
// int yIndex = blockIdx.y * blockDim.y + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// temp[threadIdx.y][threadIdx.x] = inputMatrix[idx];
// }
// //Синхронизируем все нити в блоке
// __syncthreads();
// xIndex = blockIdx.y * blockDim.y + threadIdx.x;
// yIndex = blockIdx.x * blockDim.x + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // xIndex -= width / 2.0;
// // yIndex -= height / 2.0;
// // float nx = xIndex * costeta + yIndex * sinteta,
// // ny = -xIndex * sinteta + yIndex * costeta;
// // nx += width / 2.0;
// // ny += height / 2.0;
// // //x[i] = xi * costeta + yi * sinteta;
// // //y[i] = -xi * sinteta + yi * costeta;
// // if (nx >= 0 && nx < width && ny >= 0 && ny < height){
// // // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// outputMatrix[idx] = temp[threadIdx.x][threadIdx.y];
// // }
// }
}
extern "C" void algoCudaRotate(unsigned char *input_output,int step,int rows,int cols,double angle)
{ // todo: Избавиться от не нужных копирований.
hipMemset(&sinteta,0,sizeof(float));
hipMemset(&costeta,0,sizeof(float));
kernelSetsincos<<<1,1>>> (-angle / 180.0 * PI);
// std::cerr << "sincos set\n";
int channels = 3,
width = cols, //cols * channels,
height = rows,
n = width * height,
bytesn = n * sizeof(int);
// std::cerr << "step: " << step << " rows: " << rows << " cols: " << cols << '\n';
unsigned int *data = new unsigned int [n];
for(int i = 0;i < height; ++i){ // Упаковка bgr в int 4 байта тип
for(int j = 0;j < width * channels; j += channels){
unsigned char b = input_output[step * i + j],
g = input_output[step * i + j + 1],
r = input_output[step * i + j + 2];
data[i * width + j / channels] = (int(b) << 16) | (int(g) << 8) | int(r);
}
}
//std::cerr << "array read\n";
CudaArray<unsigned int> inputimg(n),rotatedimg(n);
inputimg = data;
//std::cerr << "array copy to device\n";
dim3 gridSize = dim3(width / BLOCK_DIM, height / BLOCK_DIM, 1);
dim3 blockSize = dim3(BLOCK_DIM, BLOCK_DIM, 1);
kernelRotate<<< gridSize, blockSize >>> (inputimg,rotatedimg,width,height);
//std::cerr << "call kernel\n";
rotatedimg.copyToCpu(data);
// std::fill (input_output,input_output + height * step,0);
// std::cerr << "returen result to cpu mem\n";
for(int i = 0;i < height; ++i){ // распаковка
for(int j = 0;j < width * channels; j += channels){
unsigned int bgr = data[i * width + j / channels];
input_output[step * i + j] = (bgr >> 16);
input_output[step * i + j + 1] = (bgr & (255 << 8)) >> 8;
input_output[step * i + j + 2] = (bgr & 255);
}
}
hipFree (&sinteta);
hipFree (&costeta);
delete [] data;
}
extern "C" hipError_t algoCuda_main()
{
return hipGetLastError();
}
/* OpenCV data format
int limit = 10,
channel = 3;
unsigned char *input = img.data;
for(int i = 0;i < img.rows && limit ;i++){
for(int j = 0;j < img.cols * channel && limit; j += channel){
uchar b = input[img.step * i + j] ;
uchar g = input[img.step * i + j + 1];
uchar r = input[img.step * i + j + 2];
qDebug () << b << g << r;
limit--;
}
}
qDebug () << "next";
for (int i = 0; i < 10; i++){
cv::Vec3b intensity = img.at<cv::Vec3b>(0, i);
uchar b = intensity.val[0];
uchar g = intensity.val[1];
uchar r = intensity.val[2];
qDebug () << b << g << r;
}
/*
__global__ void kernCuda(float *Source,float * Destination, int width)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int i = abs(x*cosf(theta)-y*sinf(theta));
int j = abs(x*sinf(theta)+y*cosf(theta));
if(x<width && y<width){
Destination[j*width+i]=Source[y*width+x];
}
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <hip/hip_vector_types.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <ctime>
#include <cmath>
//#include <QDebug>
#define PI 3.14159265359
using namespace std;
template<class T>
class CudaArray
{
public:
CudaArray (int n) : dev{nullptr},nBytes{0}
{
try{
nBytes = n * sizeof(T);
hipMalloc((void**)&dev,nBytes);
} catch (...){}
}
~CudaArray ()
{
try{
hipFree (dev);
}
catch(...) {}
}
int getnBytes() const
{
return nBytes;
}
operator T* () const
{
return dev;
}
CudaArray& operator = (T* rhs) const
{
hipMemcpy (dev,rhs,nBytes,hipMemcpyHostToDevice);
}
void copyToCpu(T *cpu) const
{
hipMemcpy (cpu,dev,nBytes,hipMemcpyDeviceToHost);
}
private:
T *dev;
int nBytes;
};
__device__ float sinteta;
__device__ float costeta;
__global__ void kernelSetsincos(double teta)
{
sinteta = sin (teta);
costeta = cos (teta);
}
// http://habrahabr.ru/post/55461/ (c)
#define BLOCK_DIM 16
__global__ void kernelRotate(unsigned int* inputMatrix, unsigned int* outputMatrix, int width, int height)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int yIndex = blockDim.y * blockIdx.y + threadIdx.y;
if ((xIndex < width) && (yIndex < height))
{
//Линейный индекс элемента строки исходной матрицы
int inputIdx = xIndex + width * yIndex;
//Линейный индекс элемента столбца матрицы-результата
xIndex -= width / 2.0;
yIndex -= height / 2.0;
int nx = xIndex * costeta + yIndex * sinteta,
ny = -xIndex * sinteta + yIndex * costeta;
nx += width / 2.0;
ny += height / 2.0;
if (nx >= 0 && nx < width && ny >= 0 && ny < height){
int outputIdx = nx + width * ny;
outputMatrix[outputIdx] = inputMatrix[inputIdx];
}
}
// __shared__ float temp[BLOCK_DIM][BLOCK_DIM];
// int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
// int yIndex = blockIdx.y * blockDim.y + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// temp[threadIdx.y][threadIdx.x] = inputMatrix[idx];
// }
// //Синхронизируем все нити в блоке
// __syncthreads();
// xIndex = blockIdx.y * blockDim.y + threadIdx.x;
// yIndex = blockIdx.x * blockDim.x + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // xIndex -= width / 2.0;
// // yIndex -= height / 2.0;
// // float nx = xIndex * costeta + yIndex * sinteta,
// // ny = -xIndex * sinteta + yIndex * costeta;
// // nx += width / 2.0;
// // ny += height / 2.0;
// // //x[i] = xi * costeta + yi * sinteta;
// // //y[i] = -xi * sinteta + yi * costeta;
// // if (nx >= 0 && nx < width && ny >= 0 && ny < height){
// // // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// outputMatrix[idx] = temp[threadIdx.x][threadIdx.y];
// // }
// }
}
extern "C" void algoCudaRotate(unsigned char *input_output,int step,int rows,int cols,double angle)
{ // todo: Избавиться от не нужных копирований.
hipMemset(&sinteta,0,sizeof(float));
hipMemset(&costeta,0,sizeof(float));
kernelSetsincos<<<1,1>>> (-angle / 180.0 * PI);
// std::cerr << "sincos set\n";
int channels = 3,
width = cols, //cols * channels,
height = rows,
n = width * height,
bytesn = n * sizeof(int);
// std::cerr << "step: " << step << " rows: " << rows << " cols: " << cols << '\n';
unsigned int *data = new unsigned int [n];
for(int i = 0;i < height; ++i){ // Упаковка bgr в int 4 байта тип
for(int j = 0;j < width * channels; j += channels){
unsigned char b = input_output[step * i + j],
g = input_output[step * i + j + 1],
r = input_output[step * i + j + 2];
data[i * width + j / channels] = (int(b) << 16) | (int(g) << 8) | int(r);
}
}
//std::cerr << "array read\n";
CudaArray<unsigned int> inputimg(n),rotatedimg(n);
inputimg = data;
//std::cerr << "array copy to device\n";
dim3 gridSize = dim3(width / BLOCK_DIM, height / BLOCK_DIM, 1);
dim3 blockSize = dim3(BLOCK_DIM, BLOCK_DIM, 1);
kernelRotate<<< gridSize, blockSize >>> (inputimg,rotatedimg,width,height);
//std::cerr << "call kernel\n";
rotatedimg.copyToCpu(data);
// std::fill (input_output,input_output + height * step,0);
// std::cerr << "returen result to cpu mem\n";
for(int i = 0;i < height; ++i){ // распаковка
for(int j = 0;j < width * channels; j += channels){
unsigned int bgr = data[i * width + j / channels];
input_output[step * i + j] = (bgr >> 16);
input_output[step * i + j + 1] = (bgr & (255 << 8)) >> 8;
input_output[step * i + j + 2] = (bgr & 255);
}
}
hipFree (&sinteta);
hipFree (&costeta);
delete [] data;
}
extern "C" hipError_t algoCuda_main()
{
return hipGetLastError();
}
/* OpenCV data format
int limit = 10,
channel = 3;
unsigned char *input = img.data;
for(int i = 0;i < img.rows && limit ;i++){
for(int j = 0;j < img.cols * channel && limit; j += channel){
uchar b = input[img.step * i + j] ;
uchar g = input[img.step * i + j + 1];
uchar r = input[img.step * i + j + 2];
qDebug () << b << g << r;
limit--;
}
}
qDebug () << "next";
for (int i = 0; i < 10; i++){
cv::Vec3b intensity = img.at<cv::Vec3b>(0, i);
uchar b = intensity.val[0];
uchar g = intensity.val[1];
uchar r = intensity.val[2];
qDebug () << b << g << r;
}
/*
__global__ void kernCuda(float *Source,float * Destination, int width)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int i = abs(x*cosf(theta)-y*sinf(theta));
int j = abs(x*sinf(theta)+y*cosf(theta));
if(x<width && y<width){
Destination[j*width+i]=Source[y*width+x];
}
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kernelSetsincosd
.globl _Z15kernelSetsincosd
.p2align 8
.type _Z15kernelSetsincosd,@function
_Z15kernelSetsincosd:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f64_e64 s0, 0x41d00000, |s[2:3]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_mov_b32 vcc_lo, s0
s_cbranch_vccz .LBB0_2
v_ldexp_f64 v[0:1], |s[2:3]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |s[2:3]|
v_trig_preop_f64 v[2:3], |s[2:3]|, 0
s_and_b32 s1, s3, 0x7fffffff
v_trig_preop_f64 v[4:5], |s[2:3]|, 1
v_trig_preop_f64 v[14:15], |s[2:3]|, 2
s_mov_b32 s4, 0
s_mov_b32 s9, 0x3ff921fb
s_mov_b32 s8, 0x54442d18
s_mov_b32 s11, 0x3c91a626
s_mov_b32 s10, 0x33145c07
v_cndmask_b32_e32 v1, s1, v1, vcc_lo
v_cndmask_b32_e32 v0, s2, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[2:3], v[0:1]
v_mul_f64 v[8:9], v[4:5], v[0:1]
v_mul_f64 v[20:21], v[14:15], v[0:1]
v_fma_f64 v[2:3], v[2:3], v[0:1], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[4:5], v[4:5], v[0:1], -v[8:9]
v_fma_f64 v[0:1], v[14:15], v[0:1], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[8:9], v[2:3]
v_add_f64 v[12:13], v[10:11], -v[8:9]
v_add_f64 v[18:19], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[10:11], -v[12:13]
v_add_f64 v[2:3], v[2:3], -v[12:13]
v_ldexp_f64 v[12:13], v[18:19], -2
v_add_f64 v[6:7], v[18:19], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[8:9], -v[16:17]
v_add_f64 v[16:17], v[20:21], v[4:5]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[12:13]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[10:11], -v[6:7]
v_add_f64 v[2:3], v[2:3], v[8:9]
v_fract_f64_e32 v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[16:17], v[2:3]
v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[8:9], v[8:9], 2
v_add_f64 v[12:13], v[6:7], v[10:11]
v_add_f64 v[22:23], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[12:13], v[8:9]
v_add_f64 v[28:29], v[10:11], -v[22:23]
v_add_f64 v[2:3], v[2:3], -v[22:23]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_f64_e32 vcc_lo, 0, v[18:19]
v_add_f64 v[18:19], v[16:17], -v[20:21]
v_add_f64 v[6:7], v[10:11], -v[6:7]
s_and_b32 s1, vcc_lo, exec_lo
s_cselect_b32 s5, 0x40100000, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_f64 v[26:27], v[16:17], -v[18:19]
v_add_f64 v[8:9], v[8:9], s[4:5]
v_add_f64 v[4:5], v[4:5], -v[18:19]
v_add_f64 v[16:17], v[16:17], -v[28:29]
v_add_f64 v[18:19], v[20:21], -v[26:27]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[12:13], v[8:9]
v_add_f64 v[2:3], v[2:3], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[18:19]
v_cvt_i32_f64_e32 v24, v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_cvt_f64_i32_e32 v[22:23], v24
v_readfirstlane_b32 s1, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_add_f64 v[8:9], v[8:9], -v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[6:7], v[0:1]
v_add_f64 v[4:5], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[4:5], -v[8:9]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[4:5]
v_add_f64 v[2:3], v[12:13], -v[2:3]
s_cmp_lg_u32 vcc_lo, 0
s_addc_u32 s6, s1, 0
s_and_b32 s1, vcc_lo, exec_lo
s_cselect_b32 s5, 0x3ff00000, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_add_f64 v[2:3], v[4:5], -s[4:5]
v_add_f64 v[4:5], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f64 v[6:7], v[4:5], s[8:9]
v_add_f64 v[2:3], v[4:5], -v[2:3]
v_fma_f64 v[8:9], v[4:5], s[8:9], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_fma_f64 v[2:3], v[4:5], s[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[0:1], s[8:9], v[2:3]
v_add_f64 v[0:1], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[0:1], -v[6:7]
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_cbranch_execz .LBB0_3
s_branch .LBB0_4
.LBB0_2:
.LBB0_3:
s_mov_b32 s5, 0x3fe45f30
s_mov_b32 s4, 0x6dc9c883
s_mov_b32 s7, 0xbc91a626
v_mul_f64 v[0:1], |s[2:3]|, s[4:5]
s_mov_b32 s5, 0xbff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s6, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[2:3], v[0:1]
v_fma_f64 v[0:1], v[2:3], s[4:5], |s[2:3]|
v_mul_f64 v[4:5], v[2:3], s[6:7]
s_mov_b32 s5, 0xb97b839a
s_mov_b32 s4, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[2:3], s[6:7], v[0:1]
v_add_f64 v[6:7], v[0:1], v[4:5]
s_mov_b32 s7, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[0:1], -v[6:7]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[8:9], v[4:5]
v_fma_f64 v[4:5], v[2:3], s[6:7], v[4:5]
v_cvt_i32_f64_e32 v8, v[2:3]
v_add_f64 v[0:1], v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v8
v_add_f64 v[0:1], v[0:1], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
v_add_f64 v[0:1], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[0:1], -v[10:11]
v_add_f64 v[2:3], v[4:5], -v[6:7]
.LBB0_4:
v_mul_f64 v[4:5], v[0:1], v[0:1]
s_mov_b32 s5, 0xbe5ae600
s_mov_b32 s4, 0xb42fdfa7
s_mov_b32 s9, 0x3de5e0b2
s_mov_b32 s8, 0xf9a43bb8
s_mov_b32 s11, 0x3ec71de3
s_mov_b32 s10, 0x796cde01
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mul_f64 v[14:15], v[2:3], 0.5
v_cmp_class_f64_e64 s1, s[2:3], 0x1f8
s_bitcmp0_b32 s6, 0
s_cselect_b32 vcc_lo, -1, 0
v_fma_f64 v[6:7], v[4:5], s[8:9], s[4:5]
s_mov_b32 s5, 0x3e21eeb6
s_mov_b32 s4, 0x9037ab78
s_mov_b32 s9, 0xbda907db
s_mov_b32 s8, 0x46cc5e42
v_mul_f64 v[10:11], v[4:5], 0.5
v_fma_f64 v[8:9], v[4:5], s[8:9], s[4:5]
s_mov_b32 s5, 0xbe927e4f
s_mov_b32 s4, 0xa17f65f6
s_mov_b32 s9, 0xbf2a01a0
s_mov_b32 s8, 0x19e83e5c
v_mul_f64 v[16:17], v[0:1], -v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[10:11]
v_add_f64 v[12:13], -v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[4:5], v[8:9], s[4:5]
s_mov_b32 s5, 0x3efa01a0
s_mov_b32 s4, 0x19f4ec90
v_fma_f64 v[6:7], v[4:5], v[6:7], s[8:9]
s_mov_b32 s9, 0x3f811111
s_mov_b32 s8, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], -v[12:13], 1.0
v_fma_f64 v[8:9], v[4:5], v[8:9], s[4:5]
s_mov_b32 s5, 0xbf56c16c
s_mov_b32 s4, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[4:5], v[6:7], s[8:9]
v_add_f64 v[10:11], v[18:19], -v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[4:5], v[8:9], s[4:5]
s_mov_b32 s5, 0x3fa55555
s_mov_b32 s4, 0x55555555
v_fma_f64 v[6:7], v[16:17], v[6:7], v[14:15]
v_mul_f64 v[14:15], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[10:11], v[0:1], -v[2:3], v[10:11]
v_fma_f64 v[8:9], v[4:5], v[8:9], s[4:5]
s_mov_b32 s5, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[4:5], v[6:7], -v[2:3]
v_fma_f64 v[4:5], v[14:15], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[2:3], v[16:17], s[4:5], v[2:3]
s_lshl_b32 s4, s6, 30
s_xor_b32 s4, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 s4, s4, 0x80000000
v_add_f64 v[4:5], v[12:13], v[4:5]
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, sinteta@rel32@lo+4
s_addc_u32 s7, s7, sinteta@rel32@hi+12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v0, 0, v0, s1
v_xor_b32_e32 v1, s4, v1
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s1
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[6:7]
s_cbranch_vccz .LBB0_6
v_ldexp_f64 v[0:1], |s[2:3]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |s[2:3]|
v_trig_preop_f64 v[2:3], |s[2:3]|, 0
s_and_b32 s0, s3, 0x7fffffff
v_trig_preop_f64 v[4:5], |s[2:3]|, 1
v_trig_preop_f64 v[14:15], |s[2:3]|, 2
s_mov_b32 s7, 0x3ff921fb
s_mov_b32 s6, 0x54442d18
s_mov_b32 s9, 0x3c91a626
s_mov_b32 s8, 0x33145c07
v_cndmask_b32_e32 v1, s0, v1, vcc_lo
v_cndmask_b32_e32 v0, s2, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[2:3], v[0:1]
v_mul_f64 v[8:9], v[4:5], v[0:1]
v_mul_f64 v[20:21], v[14:15], v[0:1]
v_fma_f64 v[2:3], v[2:3], v[0:1], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[4:5], v[4:5], v[0:1], -v[8:9]
v_fma_f64 v[0:1], v[14:15], v[0:1], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[8:9], v[2:3]
v_add_f64 v[12:13], v[10:11], -v[8:9]
v_add_f64 v[18:19], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[10:11], -v[12:13]
v_add_f64 v[2:3], v[2:3], -v[12:13]
v_ldexp_f64 v[12:13], v[18:19], -2
v_add_f64 v[6:7], v[18:19], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[8:9], -v[16:17]
v_add_f64 v[16:17], v[20:21], v[4:5]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[12:13]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[6:7], v[10:11], -v[6:7]
v_add_f64 v[2:3], v[2:3], v[8:9]
v_fract_f64_e32 v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[16:17], v[2:3]
v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[8:9], v[8:9], 2
v_add_f64 v[12:13], v[6:7], v[10:11]
v_add_f64 v[22:23], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[12:13], v[8:9]
v_add_f64 v[28:29], v[10:11], -v[22:23]
v_add_f64 v[2:3], v[2:3], -v[22:23]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[18:19]
v_add_f64 v[18:19], v[16:17], -v[20:21]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s5, 0x40100000, 0
v_add_f64 v[26:27], v[16:17], -v[18:19]
v_add_f64 v[8:9], v[8:9], s[4:5]
v_add_f64 v[4:5], v[4:5], -v[18:19]
v_add_f64 v[16:17], v[16:17], -v[28:29]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[18:19], v[20:21], -v[26:27]
v_add_f64 v[24:25], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], v[16:17]
v_add_f64 v[4:5], v[4:5], v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v24, v[24:25]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[22:23], v24
v_add_f64 v[4:5], v[10:11], -v[6:7]
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[22:23]
v_add_f64 v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], v[8:9]
v_add_f64 v[2:3], v[14:15], -v[8:9]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[12:13], -v[2:3]
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s5, 0x3ff00000, 0
v_add_co_ci_u32_e64 v4, s0, 0, v24, vcc_lo
v_add_f64 v[0:1], v[0:1], v[2:3]
v_add_f64 v[2:3], v[14:15], -s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[2:3], v[0:1]
v_mul_f64 v[7:8], v[5:6], s[6:7]
v_add_f64 v[2:3], v[5:6], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[5:6], s[6:7], -v[7:8]
v_add_f64 v[0:1], v[0:1], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[5:6], s[8:9], v[9:10]
v_fma_f64 v[2:3], v[0:1], s[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[7:8], v[2:3]
v_add_f64 v[5:6], v[0:1], -v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[5:6]
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_7
s_branch .LBB0_8
.LBB0_6:
.LBB0_7:
s_mov_b32 s5, 0x3fe45f30
s_mov_b32 s4, 0x6dc9c883
s_mov_b32 s7, 0xbc91a626
v_mul_f64 v[0:1], |s[2:3]|, s[4:5]
s_mov_b32 s5, 0xbff921fb
s_mov_b32 s4, 0x54442d18
s_mov_b32 s6, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[0:1]
v_fma_f64 v[0:1], v[4:5], s[4:5], |s[2:3]|
v_mul_f64 v[2:3], v[4:5], s[6:7]
s_mov_b32 s3, 0xb97b839a
s_mov_b32 s2, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[4:5], s[6:7], v[0:1]
v_add_f64 v[6:7], v[0:1], v[2:3]
s_mov_b32 s7, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[0:1], -v[6:7]
v_add_f64 v[6:7], v[6:7], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_fma_f64 v[2:3], v[4:5], s[6:7], v[2:3]
v_add_f64 v[0:1], v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_fma_f64 v[2:3], v[4:5], s[2:3], v[0:1]
v_cvt_i32_f64_e32 v4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[8:9], v[2:3]
v_add_f64 v[6:7], v[0:1], -v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[6:7]
.LBB0_8:
v_mul_f64 v[5:6], v[0:1], v[0:1]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s5, 0x3de5e0b2
s_mov_b32 s4, 0xf9a43bb8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[15:16], v[2:3], 0.5
v_fma_f64 v[7:8], v[5:6], s[4:5], s[2:3]
s_mov_b32 s5, 0x3ec71de3
s_mov_b32 s4, 0x796cde01
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
v_mul_f64 v[11:12], v[5:6], 0.5
v_mul_f64 v[17:18], v[0:1], -v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
s_mov_b32 s5, 0xbda907db
s_mov_b32 s4, 0x46cc5e42
v_fma_f64 v[9:10], v[5:6], s[4:5], s[2:3]
s_mov_b32 s3, 0xbf2a01a0
s_mov_b32 s2, 0x19e83e5c
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], -v[11:12], 1.0
v_fma_f64 v[7:8], v[5:6], v[7:8], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[5:6], v[9:10], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], -v[13:14], 1.0
v_fma_f64 v[7:8], v[5:6], v[7:8], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[5:6], v[9:10], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[19:20], -v[11:12]
v_fma_f64 v[7:8], v[17:18], v[7:8], v[15:16]
v_mul_f64 v[15:16], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[5:6], v[9:10], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[7:8], v[5:6], v[7:8], -v[2:3]
v_fma_f64 v[2:3], v[0:1], -v[2:3], v[11:12]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[5:6], v[5:6], v[9:10], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[7:8], v[17:18], s[2:3], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[15:16], v[5:6], v[2:3]
v_add_f64 v[0:1], v[0:1], -v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[13:14], v[2:3]
v_and_b32_e32 v5, 1, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, 0x80000000, v1
v_lshlrev_b32_e32 v4, 30, v4
v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, 0x80000000, v4
v_cndmask_b32_e64 v0, 0, v0, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s1
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, costeta@rel32@lo+4
s_addc_u32 s1, s1, costeta@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernelSetsincosd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kernelSetsincosd, .Lfunc_end0-_Z15kernelSetsincosd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12kernelRotatePjS_ii
.globl _Z12kernelRotatePjS_ii
.p2align 8
.type _Z12kernelRotatePjS_ii,@function
_Z12kernelRotatePjS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cvt_f64_i32_e32 v[2:3], s8
v_cvt_f64_i32_e32 v[6:7], s9
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, sinteta@rel32@lo+4
s_addc_u32 s3, s3, sinteta@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, costeta@rel32@lo+4
s_addc_u32 s5, s5, costeta@rel32@hi+12
v_cvt_f64_i32_e32 v[4:5], v0
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[4:5], 0x0
v_cvt_f64_i32_e32 v[8:9], v1
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[4:5], v[2:3], -0.5, v[4:5]
v_fma_f64 v[8:9], v[6:7], -0.5, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v4, v[4:5]
v_cvt_i32_f64_e32 v5, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v8, 0, v4
v_cvt_f32_i32_e32 v4, v4
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v8, v8
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v9, s2, v5 :: v_dual_mul_f32 v8, s2, v8
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v9, s3, v4 :: v_dual_fmac_f32 v8, s3, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v4, v9
v_cvt_i32_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[4:5], v4
v_cvt_f64_i32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[2:3], 0.5, v[4:5]
v_fma_f64 v[4:5], v[6:7], 0.5, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v2, v[2:3]
v_cvt_i32_f64_e32 v3, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e64 s3, s8, v2
v_cmp_lt_i32_e64 s5, -1, v2
v_cmp_gt_i32_e64 s4, s9, v3
v_cmp_lt_i32_e64 s6, -1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 s2, s2, s5
s_and_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v3, s8, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12kernelRotatePjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12kernelRotatePjS_ii, .Lfunc_end1-_Z12kernelRotatePjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected sinteta
.type sinteta,@object
.section .bss,"aw",@nobits
.globl sinteta
.p2align 2, 0x0
sinteta:
.long 0x00000000
.size sinteta, 4
.protected costeta
.type costeta,@object
.globl costeta
.p2align 2, 0x0
costeta:
.long 0x00000000
.size costeta, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sinteta
.addrsig_sym costeta
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernelSetsincosd
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z15kernelSetsincosd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12kernelRotatePjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12kernelRotatePjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <hip/hip_vector_types.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#include <ctime>
#include <cmath>
//#include <QDebug>
#define PI 3.14159265359
using namespace std;
template<class T>
class CudaArray
{
public:
CudaArray (int n) : dev{nullptr},nBytes{0}
{
try{
nBytes = n * sizeof(T);
hipMalloc((void**)&dev,nBytes);
} catch (...){}
}
~CudaArray ()
{
try{
hipFree (dev);
}
catch(...) {}
}
int getnBytes() const
{
return nBytes;
}
operator T* () const
{
return dev;
}
CudaArray& operator = (T* rhs) const
{
hipMemcpy (dev,rhs,nBytes,hipMemcpyHostToDevice);
}
void copyToCpu(T *cpu) const
{
hipMemcpy (cpu,dev,nBytes,hipMemcpyDeviceToHost);
}
private:
T *dev;
int nBytes;
};
__device__ float sinteta;
__device__ float costeta;
__global__ void kernelSetsincos(double teta)
{
sinteta = sin (teta);
costeta = cos (teta);
}
// http://habrahabr.ru/post/55461/ (c)
#define BLOCK_DIM 16
__global__ void kernelRotate(unsigned int* inputMatrix, unsigned int* outputMatrix, int width, int height)
{
int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
int yIndex = blockDim.y * blockIdx.y + threadIdx.y;
if ((xIndex < width) && (yIndex < height))
{
//Линейный индекс элемента строки исходной матрицы
int inputIdx = xIndex + width * yIndex;
//Линейный индекс элемента столбца матрицы-результата
xIndex -= width / 2.0;
yIndex -= height / 2.0;
int nx = xIndex * costeta + yIndex * sinteta,
ny = -xIndex * sinteta + yIndex * costeta;
nx += width / 2.0;
ny += height / 2.0;
if (nx >= 0 && nx < width && ny >= 0 && ny < height){
int outputIdx = nx + width * ny;
outputMatrix[outputIdx] = inputMatrix[inputIdx];
}
}
// __shared__ float temp[BLOCK_DIM][BLOCK_DIM];
// int xIndex = blockIdx.x * blockDim.x + threadIdx.x;
// int yIndex = blockIdx.y * blockDim.y + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// temp[threadIdx.y][threadIdx.x] = inputMatrix[idx];
// }
// //Синхронизируем все нити в блоке
// __syncthreads();
// xIndex = blockIdx.y * blockDim.y + threadIdx.x;
// yIndex = blockIdx.x * blockDim.x + threadIdx.y;
// if ((xIndex < width) && (yIndex < height))
// {
// // xIndex -= width / 2.0;
// // yIndex -= height / 2.0;
// // float nx = xIndex * costeta + yIndex * sinteta,
// // ny = -xIndex * sinteta + yIndex * costeta;
// // nx += width / 2.0;
// // ny += height / 2.0;
// // //x[i] = xi * costeta + yi * sinteta;
// // //y[i] = -xi * sinteta + yi * costeta;
// // if (nx >= 0 && nx < width && ny >= 0 && ny < height){
// // // Линейный индекс элемента строки исходной матрицы
// int idx = yIndex * width + xIndex;
// //Копируем элементы исходной матрицы
// outputMatrix[idx] = temp[threadIdx.x][threadIdx.y];
// // }
// }
}
extern "C" void algoCudaRotate(unsigned char *input_output,int step,int rows,int cols,double angle)
{ // todo: Избавиться от не нужных копирований.
hipMemset(&sinteta,0,sizeof(float));
hipMemset(&costeta,0,sizeof(float));
kernelSetsincos<<<1,1>>> (-angle / 180.0 * PI);
// std::cerr << "sincos set\n";
int channels = 3,
width = cols, //cols * channels,
height = rows,
n = width * height,
bytesn = n * sizeof(int);
// std::cerr << "step: " << step << " rows: " << rows << " cols: " << cols << '\n';
unsigned int *data = new unsigned int [n];
for(int i = 0;i < height; ++i){ // Упаковка bgr в int 4 байта тип
for(int j = 0;j < width * channels; j += channels){
unsigned char b = input_output[step * i + j],
g = input_output[step * i + j + 1],
r = input_output[step * i + j + 2];
data[i * width + j / channels] = (int(b) << 16) | (int(g) << 8) | int(r);
}
}
//std::cerr << "array read\n";
CudaArray<unsigned int> inputimg(n),rotatedimg(n);
inputimg = data;
//std::cerr << "array copy to device\n";
dim3 gridSize = dim3(width / BLOCK_DIM, height / BLOCK_DIM, 1);
dim3 blockSize = dim3(BLOCK_DIM, BLOCK_DIM, 1);
kernelRotate<<< gridSize, blockSize >>> (inputimg,rotatedimg,width,height);
//std::cerr << "call kernel\n";
rotatedimg.copyToCpu(data);
// std::fill (input_output,input_output + height * step,0);
// std::cerr << "returen result to cpu mem\n";
for(int i = 0;i < height; ++i){ // распаковка
for(int j = 0;j < width * channels; j += channels){
unsigned int bgr = data[i * width + j / channels];
input_output[step * i + j] = (bgr >> 16);
input_output[step * i + j + 1] = (bgr & (255 << 8)) >> 8;
input_output[step * i + j + 2] = (bgr & 255);
}
}
hipFree (&sinteta);
hipFree (&costeta);
delete [] data;
}
extern "C" hipError_t algoCuda_main()
{
return hipGetLastError();
}
/* OpenCV data format
int limit = 10,
channel = 3;
unsigned char *input = img.data;
for(int i = 0;i < img.rows && limit ;i++){
for(int j = 0;j < img.cols * channel && limit; j += channel){
uchar b = input[img.step * i + j] ;
uchar g = input[img.step * i + j + 1];
uchar r = input[img.step * i + j + 2];
qDebug () << b << g << r;
limit--;
}
}
qDebug () << "next";
for (int i = 0; i < 10; i++){
cv::Vec3b intensity = img.at<cv::Vec3b>(0, i);
uchar b = intensity.val[0];
uchar g = intensity.val[1];
uchar r = intensity.val[2];
qDebug () << b << g << r;
}
/*
__global__ void kernCuda(float *Source,float * Destination, int width)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int i = abs(x*cosf(theta)-y*sinf(theta));
int j = abs(x*sinf(theta)+y*cosf(theta));
if(x<width && y<width){
Destination[j*width+i]=Source[y*width+x];
}
}
*/ | .text
.file "cuda_algo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__kernelSetsincosd # -- Begin function _Z30__device_stub__kernelSetsincosd
.p2align 4, 0x90
.type _Z30__device_stub__kernelSetsincosd,@function
_Z30__device_stub__kernelSetsincosd: # @_Z30__device_stub__kernelSetsincosd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15kernelSetsincosd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__kernelSetsincosd, .Lfunc_end0-_Z30__device_stub__kernelSetsincosd
.cfi_endproc
# -- End function
.globl _Z27__device_stub__kernelRotatePjS_ii # -- Begin function _Z27__device_stub__kernelRotatePjS_ii
.p2align 4, 0x90
.type _Z27__device_stub__kernelRotatePjS_ii,@function
_Z27__device_stub__kernelRotatePjS_ii: # @_Z27__device_stub__kernelRotatePjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12kernelRotatePjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__kernelRotatePjS_ii, .Lfunc_end1-_Z27__device_stub__kernelRotatePjS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function algoCudaRotate
.LCPI2_0:
.quad 0xc066800000000000 # double -180
.LCPI2_1:
.quad 0x400921fb54442eea # double 3.1415926535900001
.text
.globl algoCudaRotate
.p2align 4, 0x90
.type algoCudaRotate,@function
algoCudaRotate: # @algoCudaRotate
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl %ecx, %ebx
movl %edx, %ebp
movl %esi, %r12d
movq %rdi, %r14
.cfi_escape 0x2e, 0x00
movl $sinteta, %edi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
.cfi_escape 0x2e, 0x00
movl $costeta, %edi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
mulsd .LCPI2_1(%rip), %xmm0
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 32(%rsp)
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z15kernelSetsincosd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl %ebx, %r13d
imull %ebp, %r13d
movslq %r13d, %rax
leaq (,%rax,4), %rcx
testl %eax, %eax
movq $-1, %rdi
cmovnsq %rcx, %rdi
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, %r15
testl %ebp, %ebp
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
leal (%rbx,%rbx,2), %eax
cltq
movslq %r12d, %rcx
movslq %ebx, %rdx
movl %ebp, %esi
addq $2, %r14
shlq $2, %rdx
xorl %edi, %edi
movq %r15, %r8
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
incq %rdi
addq %rcx, %r14
addq %rdx, %r8
cmpq %rsi, %rdi
je .LBB2_8
.LBB2_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
testl %ebx, %ebx
jle .LBB2_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=1
movq %r8, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_4 Depth=1
# => This Inner Loop Header: Depth=2
movzbl -2(%r14,%r10), %r11d
movzbl -1(%r14,%r10), %ebp
movzbl (%r14,%r10), %r12d
shll $16, %r11d
shll $8, %ebp
orl %r11d, %ebp
orl %r12d, %ebp
movl %ebp, (%r9)
addq $3, %r10
addq $4, %r9
cmpq %rax, %r10
jl .LBB2_6
jmp .LBB2_7
.LBB2_8: # %._crit_edge113
movq $0, (%rsp)
shll $2, %r13d
movl %r13d, 8(%rsp)
movslq %r13d, %rbx
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp1:
jmp .LBB2_10
.LBB2_9:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.LBB2_10: # %_ZN9CudaArrayIjEC2Ei.exit
movq $0, 16(%rsp)
movl %ebx, 24(%rsp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp4:
jmp .LBB2_12
.LBB2_11:
.Ltmp5:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __cxa_begin_catch
.Ltmp6:
.cfi_escape 0x2e, 0x00
callq __cxa_end_catch
.Ltmp7:
.LBB2_12: # %_ZN9CudaArrayIjEC2Ei.exit93
movq (%rsp), %rdi
movslq 8(%rsp), %rdx
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.13: # %.noexc94
.LBB2_14:
.Ltmp8:
movq %rax, %rbx
jmp .LBB2_16
.LBB2_15:
.Ltmp11:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq _ZN9CudaArrayIjED2Ev
.LBB2_16:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
callq _ZN9CudaArrayIjED2Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size algoCudaRotate, .Lfunc_end2-algoCudaRotate
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 1 # On action: 1
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZN9CudaArrayIjED2Ev,"axG",@progbits,_ZN9CudaArrayIjED2Ev,comdat
.weak _ZN9CudaArrayIjED2Ev # -- Begin function _ZN9CudaArrayIjED2Ev
.p2align 4, 0x90
.type _ZN9CudaArrayIjED2Ev,@function
_ZN9CudaArrayIjED2Ev: # @_ZN9CudaArrayIjED2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq (%rdi), %rdi
.Ltmp12:
callq hipFree
.Ltmp13:
.LBB3_2:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 16
.Ltmp14:
movq %rax, %rdi
callq __cxa_begin_catch
.Ltmp15:
callq __cxa_end_catch
.Ltmp16:
jmp .LBB3_2
.LBB3_3:
.Ltmp17:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZN9CudaArrayIjED2Ev, .Lfunc_end3-_ZN9CudaArrayIjED2Ev
.cfi_endproc
.section .gcc_except_table._ZN9CudaArrayIjED2Ev,"aG",@progbits,_ZN9CudaArrayIjED2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase1-.Lttbaseref1
.Lttbaseref1:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 1 # On action: 1
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase1:
.p2align 2, 0x0
# -- End function
.text
.globl algoCuda_main # -- Begin function algoCuda_main
.p2align 4, 0x90
.type algoCuda_main,@function
algoCuda_main: # @algoCuda_main
.cfi_startproc
# %bb.0:
jmp hipGetLastError # TAILCALL
.Lfunc_end4:
.size algoCuda_main, .Lfunc_end4-algoCuda_main
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernelSetsincosd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12kernelRotatePjS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sinteta, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $costeta, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type sinteta,@object # @sinteta
.local sinteta
.comm sinteta,4,4
.type costeta,@object # @costeta
.local costeta
.comm costeta,4,4
.type _Z15kernelSetsincosd,@object # @_Z15kernelSetsincosd
.section .rodata,"a",@progbits
.globl _Z15kernelSetsincosd
.p2align 3, 0x0
_Z15kernelSetsincosd:
.quad _Z30__device_stub__kernelSetsincosd
.size _Z15kernelSetsincosd, 8
.type _Z12kernelRotatePjS_ii,@object # @_Z12kernelRotatePjS_ii
.globl _Z12kernelRotatePjS_ii
.p2align 3, 0x0
_Z12kernelRotatePjS_ii:
.quad _Z27__device_stub__kernelRotatePjS_ii
.size _Z12kernelRotatePjS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kernelSetsincosd"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12kernelRotatePjS_ii"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "sinteta"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "costeta"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kernelSetsincosd
.addrsig_sym _Z27__device_stub__kernelRotatePjS_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym sinteta
.addrsig_sym costeta
.addrsig_sym _Z15kernelSetsincosd
.addrsig_sym _Z12kernelRotatePjS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <string>
#include <fstream>
#include <sstream>
#include <vector>
#include <iterator>
#include <unordered_map>
#include <bitset>
#include <thread>
#include <math.h>
#define BITS 64
#define MAX_LEN_WORD 20
using namespace std;
string readFile(string file) {
ifstream MyFile;
MyFile.open(file);
stringstream strStream;
strStream << MyFile.rdbuf();
return strStream.str();
}
vector<string> strToVector(string data, char stop_w = '\n') {
vector<string> out;
size_t last_init = 0;
for (size_t i = 0; i < data.length(); i++) {
if (data[i] == stop_w) {
string temp = data.substr(last_init, i - last_init);
out.push_back(temp);
last_init = i + 1;
}
}
return out;
}
void printVector(vector<string> data) {
for (size_t i = 0; i < data.size(); i++) {
printf("%s\n", data[i].c_str());
}
}
void printVectorInt(vector<int> data) {
for (size_t i = 0; i < data.size(); i++) {
printf("%i ", data[i]);
}
printf("\n");
}
void printMap(unordered_map <string, int> data) {
for (unordered_map<string, int >::const_iterator it = data.begin(); it != data.end(); ++it) {
cout << it->first << " " << it->second << "\n";
}
}
string* text_generator(vector<string> my_dict, int len_words) {
string* text = new string[len_words];
for (size_t i = 0; i < len_words; i++) {
text[i] = my_dict[rand() % my_dict.size()];
}
return text;
}
unordered_map <string, int> get_frec(string* words, int len_words) {
unordered_map <string, int> out;
for (size_t i = 0; i < len_words; i++) {
if (out.count(words[i]) > 0) { // cuantas veces parece la palabra en el texto
out[words[i]] += 1;
}
else {
out[words[i]] = 1;
}
}
return out;
}
string sum_matrix(vector<long*> in_matrix) {
string out;
for (size_t j = 0; j < BITS; j++) {
long int temp = 0;
for (size_t i = 0; i < in_matrix.size(); i++) {
temp += in_matrix[i][j];
}
if (temp > 0) {
out += '1';
}
else {
out += '0';
}
}
return out;
}
size_t count_words(unordered_map <string, int>* in_words, int n_text) {
size_t count_l = 0;
for (size_t i = 0; i < n_text; i++) {
count_l += in_words[i].size();
}
return count_l;
}
char* strToChar(string data) {
char* out = new char[MAX_LEN_WORD];
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (i < data.size()) {
out[i] = data[i];
}
else {
out[i] = 0;
}
}
return out;
}
void compress_sim_data_cuda(unordered_map <string, int>* in_words, char * & s_out, int * & f_out , int n_text) {
size_t numerate = 0;
for (size_t i = 0; i < n_text; i++) {
for (unordered_map<string, int >::const_iterator it = in_words[i].begin(); it != in_words[i].end(); ++it) {
char* t_str = strToChar(it->first);
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
s_out[numerate * MAX_LEN_WORD + i] = t_str[i];
}
f_out[numerate] = it->second;
numerate++;
}
}
}
string* extract_sim_data_cuda(long * v_words, unordered_map <string, int>* in_words, int n_text) {
string* out = new string[n_text];
size_t numerate = 0;
for (size_t i = 0; i < n_text; i++) {
vector<long*> temp;
for (unordered_map<string, int >::const_iterator it = in_words[i].begin(); it != in_words[i].end(); ++it) {
long * t_bits = new long[BITS];
for (size_t b = 0; b < BITS; b++) {
t_bits[b] = v_words[numerate + b];
}
temp.push_back(t_bits);
numerate+= BITS;
}
out[i] = sum_matrix(temp);
}
return out;
}
void sim_hash_lineal(char* s_in, int* f_in, long* & out, int len) {
for (size_t t = 0; t < len; t++) {
unsigned long long int hash = 5381;
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (s_in[t * MAX_LEN_WORD + i] != 0) {
hash = ((hash << 5) + hash) + (int)s_in[t * MAX_LEN_WORD + i];
}
}
bool* bits = new bool[BITS];
for (size_t i = 0; i < BITS; i++) {
bits[i] = hash % 2;
hash = hash / 2;
}
for (size_t i = 0; i < BITS; i++) {
size_t p = (t * BITS) + i;
out[p] = (int)bits[i];
if (out[p] == 1) {
out[p] += f_in[t];
}
else {
out[p] -= f_in[t];
}
}
}
}
__global__ void cuda_sim_hash(char * s_in, int * f_in, long * out, int len)
{
int t = (blockIdx.x * blockDim.x) + (threadIdx.x);
if (t >= 0 && t < len) {
unsigned long long int hash = 5381;
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (s_in[t * MAX_LEN_WORD + i] != 0) {
hash = ((hash << 5) + hash) + (int)s_in[t * MAX_LEN_WORD + i];
}
}
bool* bits = new bool[BITS];
for (size_t i = 0; i < BITS; i++) {
bits[i] = hash % 2;
hash = hash / 2;
}
for (size_t i = 0; i < BITS; i++) {
size_t p = (t * BITS) + i;
out[p] = (int)bits[i];
if (out[p] == 1) {
out[p] += f_in[t];
}
else {
out[p] -= f_in[t];
}
}
delete bits;
}
}
bool compare_str(string * a, string * b, int len) {
for (size_t i = 0; i < len; i++) {
if (a[i] != b[i]) {
return false;
}
}
return true;
}
int main() {
clock_t begin, end;
double elapsed_secs;
long long int w_s; //palabras por segundo
srand(time(NULL));
string words = readFile("words.txt"); //leer palabras
vector<string> l_words = strToVector(words); //libreria de palabras
int long_text = 4000; //longitud de palabras por texto
int n_text = 2560; //cantidad de textos (documentos)
printf("Num. textos: %i, Long Text: %i \n", n_text, long_text);
unordered_map <string, int>* words_frec = new unordered_map <string, int>[n_text];
// diccionario de frecuencias por palabra de cada documento
for (size_t i = 0; i < n_text; i++) {
words_frec[i] = get_frec(text_generator(l_words, long_text), long_text);
}
size_t amount_words = count_words(words_frec, n_text);
printf("Total Words: %i words \n", amount_words);
char * s_in = new char[amount_words * MAX_LEN_WORD];
int * f_in = new int[amount_words];
long * out = new long[amount_words * BITS];
compress_sim_data_cuda(words_frec, s_in, f_in , n_text);
char* cu_s_in = 0;
int* cu_f_in = 0;
long* cu_out = 0;
cudaMalloc((void**)&cu_s_in, amount_words * sizeof(char) * MAX_LEN_WORD);
cudaMalloc((void**)&cu_f_in, amount_words * sizeof(int));
cudaMalloc((void**)&cu_out, amount_words * sizeof(long) * BITS);
begin = clock();
cudaMemcpy(cu_s_in, s_in, amount_words * sizeof(char) * MAX_LEN_WORD, cudaMemcpyHostToDevice);
cudaMemcpy(cu_f_in, f_in, amount_words * sizeof(int), cudaMemcpyHostToDevice);
int thr = 1024;
int dim_grid = (amount_words/thr)+1;
cuda_sim_hash <<< dim_grid, thr >>> (cu_s_in, cu_f_in, cu_out, amount_words);
cudaMemcpy(out, cu_out, amount_words * sizeof(long) * BITS, cudaMemcpyDeviceToHost);
end = clock();
elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Grilla: %d, Bloque: %d \n", dim_grid, thr);
printf("Tiempo Cuda: %f ms \n", elapsed_secs);
w_s = amount_words / elapsed_secs;
printf("palabras por Seg: %d words \n", w_s);
string* r_out = extract_sim_data_cuda(out, words_frec, n_text);
long* out_l = new long[amount_words * BITS];
begin = clock();
sim_hash_lineal(s_in, f_in, out_l, amount_words);
end = clock();
elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Tiempo Lineal: %f ms \n", elapsed_secs);
w_s = amount_words / elapsed_secs;
printf("palabras por Seg: %d words \n", w_s);
string* r_out_l = extract_sim_data_cuda(out_l, words_frec, n_text);
/*
for (size_t i = 0; i < n_text; i++) {
cout << r_out_l[i] << endl;
}*/
if (compare_str(r_out, r_out_l, n_text)) {
cout << "Ok" << endl;
}
else {
cout << "Error" << endl;
}
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <string>
#include <fstream>
#include <sstream>
#include <vector>
#include <iterator>
#include <unordered_map>
#include <bitset>
#include <thread>
#include <math.h>
#define BITS 64
#define MAX_LEN_WORD 20
using namespace std;
string readFile(string file) {
ifstream MyFile;
MyFile.open(file);
stringstream strStream;
strStream << MyFile.rdbuf();
return strStream.str();
}
vector<string> strToVector(string data, char stop_w = '\n') {
vector<string> out;
size_t last_init = 0;
for (size_t i = 0; i < data.length(); i++) {
if (data[i] == stop_w) {
string temp = data.substr(last_init, i - last_init);
out.push_back(temp);
last_init = i + 1;
}
}
return out;
}
void printVector(vector<string> data) {
for (size_t i = 0; i < data.size(); i++) {
printf("%s\n", data[i].c_str());
}
}
void printVectorInt(vector<int> data) {
for (size_t i = 0; i < data.size(); i++) {
printf("%i ", data[i]);
}
printf("\n");
}
void printMap(unordered_map <string, int> data) {
for (unordered_map<string, int >::const_iterator it = data.begin(); it != data.end(); ++it) {
cout << it->first << " " << it->second << "\n";
}
}
string* text_generator(vector<string> my_dict, int len_words) {
string* text = new string[len_words];
for (size_t i = 0; i < len_words; i++) {
text[i] = my_dict[rand() % my_dict.size()];
}
return text;
}
unordered_map <string, int> get_frec(string* words, int len_words) {
unordered_map <string, int> out;
for (size_t i = 0; i < len_words; i++) {
if (out.count(words[i]) > 0) { // cuantas veces parece la palabra en el texto
out[words[i]] += 1;
}
else {
out[words[i]] = 1;
}
}
return out;
}
string sum_matrix(vector<long*> in_matrix) {
string out;
for (size_t j = 0; j < BITS; j++) {
long int temp = 0;
for (size_t i = 0; i < in_matrix.size(); i++) {
temp += in_matrix[i][j];
}
if (temp > 0) {
out += '1';
}
else {
out += '0';
}
}
return out;
}
size_t count_words(unordered_map <string, int>* in_words, int n_text) {
size_t count_l = 0;
for (size_t i = 0; i < n_text; i++) {
count_l += in_words[i].size();
}
return count_l;
}
char* strToChar(string data) {
char* out = new char[MAX_LEN_WORD];
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (i < data.size()) {
out[i] = data[i];
}
else {
out[i] = 0;
}
}
return out;
}
void compress_sim_data_cuda(unordered_map <string, int>* in_words, char * & s_out, int * & f_out , int n_text) {
size_t numerate = 0;
for (size_t i = 0; i < n_text; i++) {
for (unordered_map<string, int >::const_iterator it = in_words[i].begin(); it != in_words[i].end(); ++it) {
char* t_str = strToChar(it->first);
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
s_out[numerate * MAX_LEN_WORD + i] = t_str[i];
}
f_out[numerate] = it->second;
numerate++;
}
}
}
string* extract_sim_data_cuda(long * v_words, unordered_map <string, int>* in_words, int n_text) {
string* out = new string[n_text];
size_t numerate = 0;
for (size_t i = 0; i < n_text; i++) {
vector<long*> temp;
for (unordered_map<string, int >::const_iterator it = in_words[i].begin(); it != in_words[i].end(); ++it) {
long * t_bits = new long[BITS];
for (size_t b = 0; b < BITS; b++) {
t_bits[b] = v_words[numerate + b];
}
temp.push_back(t_bits);
numerate+= BITS;
}
out[i] = sum_matrix(temp);
}
return out;
}
void sim_hash_lineal(char* s_in, int* f_in, long* & out, int len) {
for (size_t t = 0; t < len; t++) {
unsigned long long int hash = 5381;
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (s_in[t * MAX_LEN_WORD + i] != 0) {
hash = ((hash << 5) + hash) + (int)s_in[t * MAX_LEN_WORD + i];
}
}
bool* bits = new bool[BITS];
for (size_t i = 0; i < BITS; i++) {
bits[i] = hash % 2;
hash = hash / 2;
}
for (size_t i = 0; i < BITS; i++) {
size_t p = (t * BITS) + i;
out[p] = (int)bits[i];
if (out[p] == 1) {
out[p] += f_in[t];
}
else {
out[p] -= f_in[t];
}
}
}
}
__global__ void cuda_sim_hash(char * s_in, int * f_in, long * out, int len)
{
int t = (blockIdx.x * blockDim.x) + (threadIdx.x);
if (t >= 0 && t < len) {
unsigned long long int hash = 5381;
for (size_t i = 0; i < MAX_LEN_WORD; i++) {
if (s_in[t * MAX_LEN_WORD + i] != 0) {
hash = ((hash << 5) + hash) + (int)s_in[t * MAX_LEN_WORD + i];
}
}
bool* bits = new bool[BITS];
for (size_t i = 0; i < BITS; i++) {
bits[i] = hash % 2;
hash = hash / 2;
}
for (size_t i = 0; i < BITS; i++) {
size_t p = (t * BITS) + i;
out[p] = (int)bits[i];
if (out[p] == 1) {
out[p] += f_in[t];
}
else {
out[p] -= f_in[t];
}
}
delete bits;
}
}
bool compare_str(string * a, string * b, int len) {
for (size_t i = 0; i < len; i++) {
if (a[i] != b[i]) {
return false;
}
}
return true;
}
int main() {
clock_t begin, end;
double elapsed_secs;
long long int w_s; //palabras por segundo
srand(time(NULL));
string words = readFile("words.txt"); //leer palabras
vector<string> l_words = strToVector(words); //libreria de palabras
int long_text = 4000; //longitud de palabras por texto
int n_text = 2560; //cantidad de textos (documentos)
printf("Num. textos: %i, Long Text: %i \n", n_text, long_text);
unordered_map <string, int>* words_frec = new unordered_map <string, int>[n_text];
// diccionario de frecuencias por palabra de cada documento
for (size_t i = 0; i < n_text; i++) {
words_frec[i] = get_frec(text_generator(l_words, long_text), long_text);
}
size_t amount_words = count_words(words_frec, n_text);
printf("Total Words: %i words \n", amount_words);
char * s_in = new char[amount_words * MAX_LEN_WORD];
int * f_in = new int[amount_words];
long * out = new long[amount_words * BITS];
compress_sim_data_cuda(words_frec, s_in, f_in , n_text);
char* cu_s_in = 0;
int* cu_f_in = 0;
long* cu_out = 0;
hipMalloc((void**)&cu_s_in, amount_words * sizeof(char) * MAX_LEN_WORD);
hipMalloc((void**)&cu_f_in, amount_words * sizeof(int));
hipMalloc((void**)&cu_out, amount_words * sizeof(long) * BITS);
begin = clock();
hipMemcpy(cu_s_in, s_in, amount_words * sizeof(char) * MAX_LEN_WORD, hipMemcpyHostToDevice);
hipMemcpy(cu_f_in, f_in, amount_words * sizeof(int), hipMemcpyHostToDevice);
int thr = 1024;
int dim_grid = (amount_words/thr)+1;
cuda_sim_hash <<< dim_grid, thr >>> (cu_s_in, cu_f_in, cu_out, amount_words);
hipMemcpy(out, cu_out, amount_words * sizeof(long) * BITS, hipMemcpyDeviceToHost);
end = clock();
elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Grilla: %d, Bloque: %d \n", dim_grid, thr);
printf("Tiempo Cuda: %f ms \n", elapsed_secs);
w_s = amount_words / elapsed_secs;
printf("palabras por Seg: %d words \n", w_s);
string* r_out = extract_sim_data_cuda(out, words_frec, n_text);
long* out_l = new long[amount_words * BITS];
begin = clock();
sim_hash_lineal(s_in, f_in, out_l, amount_words);
end = clock();
elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
printf("Tiempo Lineal: %f ms \n", elapsed_secs);
w_s = amount_words / elapsed_secs;
printf("palabras por Seg: %d words \n", w_s);
string* r_out_l = extract_sim_data_cuda(out_l, words_frec, n_text);
/*
for (size_t i = 0; i < n_text; i++) {
cout << r_out_l[i] << endl;
}*/
if (compare_str(r_out, r_out_l, n_text)) {
cout << "Ok" << endl;
}
else {
cout << "Error" << endl;
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //使用constant memory存放向量
//global memory
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
cudaMalloc((void **)&A_d,Max * Max * sizeof(double));
cudaMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
cudaMemcpy(A_d, A,Max*Max*sizeof(double),cudaMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
cudaMemcpy(C_d, C,Max * sizeof(double), cudaMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
cudaMemcpyToSymbol(con_b, &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
cudaMemcpy(C, C_d, Max * sizeof(double), cudaMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
cudaFree(A_d);
cudaFree(C_d);
free(A);
free(test_c);
free(C);
} | code for sm_80
Function : _Z5multiPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD R2, R19, c[0x0][0x174], RZ ; /* 0x00005d0013027a24 */
/* 0x000fca00078e02ff */
/*0090*/ IADD3 R3, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002037a10 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LEA.HI R21, R2, R2, RZ, 0x1 ; /* 0x0000000202157211 */
/* 0x000fe400078f08ff */
/*00b0*/ LEA.HI R18, R3, R3, RZ, 0x1 ; /* 0x0000000303127211 */
/* 0x000fe400078f08ff */
/*00c0*/ SHF.R.S32.HI R21, RZ, 0x1, R21 ; /* 0x00000001ff157819 */
/* 0x000fe20000011415 */
/*00d0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*00e0*/ SHF.R.S32.HI R18, RZ, 0x1, R18 ; /* 0x00000001ff127819 */
/* 0x000fc80000011412 */
/*00f0*/ ISETP.GT.AND P0, PT, R18, R21, PT ; /* 0x000000151200720c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 BRA 0x9c0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.IADD R2, R18, 0x1, -R21 ; /* 0x0000000112027824 */
/* 0x000fe200078e0a15 */
/*0120*/ LOP3.LUT R3, RZ, R21, RZ, 0x33, !PT ; /* 0x00000015ff037212 */
/* 0x000fe400078e33ff */
/*0130*/ LEA.HI R19, R19, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0013137a11 */
/* 0x000fe400078f08ff */
/*0140*/ LOP3.LUT P1, R10, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020a7812 */
/* 0x000fe2000782c0ff */
/*0150*/ IMAD.IADD R3, R18, 0x1, R3 ; /* 0x0000000112037824 */
/* 0x000fe200078e0203 */
/*0160*/ SHF.R.S32.HI R19, RZ, 0x1, R19 ; /* 0x00000001ff137819 */
/* 0x000fc80000011413 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0180*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fca000001ff00 */
/*0190*/ @!P1 BRA 0x400 ; /* 0x0000026000009947 */
/* 0x000fec0003800000 */
/*01a0*/ IABS R4, R19.reuse ; /* 0x0000001300047213 */
/* 0x080fe20000000000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.NE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f25270 */
/*01d0*/ IMAD R8, R0, c[0x0][0x170], R21 ; /* 0x00005c0000087a24 */
/* 0x000fe200078e0215 */
/*01e0*/ I2F.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000209400 */
/*01f0*/ LOP3.LUT R11, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff0b7212 */
/* 0x000fe400078e33ff */
/*0200*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0209 */
/*0210*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0260*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R5, R3, R7, R2 ; /* 0x0000000703057227 */
/* 0x000fe400078e0002 */
/*0280*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*0290*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0010a2000c1e1b00 */
/*02a0*/ IABS R12, R19 ; /* 0x00000013000c7213 */
/* 0x000fe40000000000 */
/*02b0*/ IABS R13, R21 ; /* 0x00000015000d7213 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.GE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe20003f66270 */
/*02d0*/ IMAD.MOV R14, RZ, RZ, -R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0c */
/*02e0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.HI.U32 R12, R5, R13, RZ ; /* 0x0000000d050c7227 */
/* 0x000fe200078e00ff */
/*0300*/ IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fc60007ffe0ff */
/*0310*/ IMAD R13, R12, R14, R13 ; /* 0x0000000e0c0d7224 */
/* 0x000fe200078e020d */
/*0320*/ IABS R12, R19 ; /* 0x00000013000c7213 */
/* 0x000fc80000000000 */
/*0330*/ ISETP.GT.U32.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fda0003f44070 */
/*0340*/ @!P2 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0da824 */
/* 0x000fca00078e0a0c */
/*0350*/ ISETP.GT.U32.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fda0003f44070 */
/*0360*/ @!P2 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0da824 */
/* 0x000fe200078e0a0c */
/*0370*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f45270 */
/*0380*/ @!P3 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0db224 */
/* 0x000fe200078e0a0d */
/*0390*/ IADD3 R8, P3, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fc80007f7e0ff */
/*03a0*/ SEL R13, R11, R13, !P1 ; /* 0x0000000d0b0d7207 */
/* 0x000fe20004800000 */
/*03b0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fc800018e0609 */
/*03c0*/ IMAD.SHL.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7824 */
/* 0x000fcc00078e00ff */
/*03d0*/ LDC.64 R12, c[0x3][R13] ; /* 0x00c000000d0c7b82 */
/* 0x000ea40000000a00 */
/*03e0*/ DFMA R2, R12, R6, R2 ; /* 0x000000060c02722b */
/* 0x0060620000000002 */
/*03f0*/ @P2 BRA 0x290 ; /* 0xfffffe9000002947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x9c0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0410*/ IABS R20, R19 ; /* 0x0000001300147213 */
/* 0x000fe20000000000 */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD R4, R0, c[0x0][0x170], R21 ; /* 0x00005c0000047a24 */
/* 0x000fe200078e0215 */
/*0440*/ I2F.RP R6, R20 ; /* 0x0000001400067306 */
/* 0x001e220000209400 */
/*0450*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0470*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0480*/ IADD3 R23, R6, 0xffffffe, RZ ; /* 0x0ffffffe06177810 */
/* 0x001fcc0007ffe0ff */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e24000021f000 */
/*04a0*/ IMAD.MOV R7, RZ, RZ, -R23 ; /* 0x000000ffff077224 */
/* 0x001fc800078e0a17 */
/*04b0*/ IMAD R7, R7, R20, RZ ; /* 0x0000001407077224 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD.HI.U32 R22, R23, R7, R22 ; /* 0x0000000717167227 */
/* 0x000fc800078e0016 */
/*04d0*/ IABS R16, R19 ; /* 0x0000001300107213 */
/* 0x000fe20000000000 */
/*04e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x0010a2000c1e1b00 */
/*04f0*/ IABS R27, R21 ; /* 0x00000015001b7213 */
/* 0x000fe40000000000 */
/*0500*/ I2F.RP R8, R16 ; /* 0x0000001000087306 */
/* 0x000ee20000209400 */
/*0510*/ IABS R9, R19 ; /* 0x0000001300097213 */
/* 0x000fce0000000000 */
/*0520*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x008ee40000001000 */
/*0530*/ IADD3 R23, R8, 0xffffffe, RZ ; /* 0x0ffffffe08177810 */
/* 0x008fcc0007ffe0ff */
/*0540*/ F2I.FTZ.U32.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000ee2000021f000 */
/*0550*/ IADD3 R14, R21, 0x1, RZ ; /* 0x00000001150e7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.MOV R25, RZ, RZ, -R9 ; /* 0x000000ffff197224 */
/* 0x000fe400078e0a09 */
/*0570*/ IMAD.HI.U32 R8, R22, R27, RZ ; /* 0x0000001b16087227 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x000fc60000000000 */
/*0590*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*05a0*/ IMAD.MOV R11, RZ, RZ, -R23 ; /* 0x000000ffff0b7224 */
/* 0x008fc800078e0a17 */
/*05b0*/ IMAD R9, R11, R16, RZ ; /* 0x000000100b097224 */
/* 0x000fe200078e02ff */
/*05c0*/ IADD3 R15, R21, 0x2, RZ ; /* 0x00000002150f7810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ IMAD.HI.U32 R22, R23, R9, R22 ; /* 0x0000000917167227 */
/* 0x000fe200078e0016 */
/*05e0*/ MOV R23, R10 ; /* 0x0000000a00177202 */
/* 0x000fe40000000f00 */
/*05f0*/ IADD3 R26, R21, 0x3, RZ ; /* 0x00000003151a7810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD R27, R8, R25, R27 ; /* 0x00000019081b7224 */
/* 0x000fe200078e021b */
/*0610*/ IABS R17, R15 ; /* 0x0000000f00117213 */
/* 0x000fe20000000000 */
/*0620*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x0000e2000c1e1b00 */
/*0630*/ IMAD.HI.U32 R10, R22, R23, RZ ; /* 0x00000017160a7227 */
/* 0x000fe200078e00ff */
/*0640*/ IABS R12, R26 ; /* 0x0000001a000c7213 */
/* 0x000fc60000000000 */
/*0650*/ IMAD R23, R10, R25, R23 ; /* 0x000000190a177224 */
/* 0x000fe400078e0217 */
/*0660*/ IMAD.HI.U32 R24, R22.reuse, R17, RZ ; /* 0x0000001116187227 */
/* 0x040fe200078e00ff */
/*0670*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000126000c1e1b00 */
/*0680*/ IMAD.HI.U32 R13, R22, R12, RZ ; /* 0x0000000c160d7227 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD R17, R24, R25.reuse, R17 ; /* 0x0000001918117224 */
/* 0x080fe400078e0211 */
/*06a0*/ IMAD R25, R13, R25, R12 ; /* 0x000000190d197224 */
/* 0x000fe400078e020c */
/*06b0*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000162000c1e1b00 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fda0003f04070 */
/*06d0*/ @!P0 IMAD.IADD R27, R27, 0x1, -R16 ; /* 0x000000011b1b8824 */
/* 0x000fca00078e0a10 */
/*06e0*/ ISETP.GT.U32.AND P4, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f84070 */
/*06f0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0010 */
/*0700*/ ISETP.GE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc80003f66270 */
/*0710*/ ISETP.GT.U32.AND P5, PT, R20.reuse, R23, PT ; /* 0x000000171400720c */
/* 0x040fe40003fa4070 */
/*0720*/ ISETP.GT.U32.AND P1, PT, R20.reuse, R17, PT ; /* 0x000000111400720c */
/* 0x040fe40003f24070 */
/*0730*/ ISETP.GT.U32.AND P2, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fc60003f44070 */
/*0740*/ @!P4 IMAD.IADD R27, R27, 0x1, -R16 ; /* 0x000000011b1bc824 */
/* 0x000fe200078e0a10 */
/*0750*/ LOP3.LUT R24, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff187212 */
/* 0x000fca00078e33ff */
/*0760*/ @!P5 IMAD.IADD R23, R23, 0x1, -R16 ; /* 0x000000011717d824 */
/* 0x000fe200078e0a10 */
/*0770*/ ISETP.NE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003fa5270 */
/*0780*/ @!P3 IMAD.MOV R27, RZ, RZ, -R27 ; /* 0x000000ffff1bb224 */
/* 0x000fc600078e0a1b */
/*0790*/ ISETP.GT.U32.AND P3, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f64070 */
/*07a0*/ @!P1 IMAD.IADD R17, R17, 0x1, -R16.reuse ; /* 0x0000000111119824 */
/* 0x100fe200078e0a10 */
/*07b0*/ SEL R27, R24, R27, !P5 ; /* 0x0000001b181b7207 */
/* 0x000fe40006800000 */
/*07c0*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f06270 */
/*07d0*/ @!P2 IMAD.IADD R25, R25, 0x1, -R16 ; /* 0x000000011919a824 */
/* 0x000fe200078e0a10 */
/*07e0*/ ISETP.GT.U32.AND P1, PT, R20.reuse, R17, PT ; /* 0x000000111400720c */
/* 0x040fe20003f24070 */
/*07f0*/ IMAD.SHL.U32 R14, R27, 0x8, RZ ; /* 0x000000081b0e7824 */
/* 0x000fe200078e00ff */
/*0800*/ ISETP.GE.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f86270 */
/*0810*/ ISETP.GT.U32.AND P2, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fc60003f44070 */
/*0820*/ @!P3 IMAD.IADD R23, R23, 0x1, -R16.reuse ; /* 0x000000011717b824 */
/* 0x100fe200078e0a10 */
/*0830*/ LDC.64 R14, c[0x3][R14] ; /* 0x00c000000e0e7b82 */
/* 0x000ea20000000a00 */
/*0840*/ ISETP.GE.AND P6, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003fc6270 */
/*0850*/ @!P0 IMAD.MOV R23, RZ, RZ, -R23 ; /* 0x000000ffff178224 */
/* 0x000fe400078e0a17 */
/*0860*/ @!P1 IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x0000000111119824 */
/* 0x000fc600078e0a10 */
/*0870*/ SEL R23, R24, R23, !P5 ; /* 0x0000001718177207 */
/* 0x000fe20006800000 */
/*0880*/ @!P4 IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff11c224 */
/* 0x000fe200078e0a11 */
/*0890*/ @!P2 IADD3 R25, R25, -R16, RZ ; /* 0x800000101919a210 */
/* 0x000fc60007ffe0ff */
/*08a0*/ IMAD.SHL.U32 R16, R23, 0x8, RZ ; /* 0x0000000817107824 */
/* 0x000fe200078e00ff */
/*08b0*/ SEL R23, R24, R17, !P5 ; /* 0x0000001118177207 */
/* 0x000fe20006800000 */
/*08c0*/ @!P6 IMAD.MOV R25, RZ, RZ, -R25 ; /* 0x000000ffff19e224 */
/* 0x000fc800078e0a19 */
/*08d0*/ LDC.64 R16, c[0x3][R16] ; /* 0x00c0000010107b82 */
/* 0x000ee20000000a00 */
/*08e0*/ IMAD.SHL.U32 R23, R23, 0x8, RZ ; /* 0x0000000817177824 */
/* 0x000fe200078e00ff */
/*08f0*/ SEL R24, R24, R25, !P5 ; /* 0x0000001918187207 */
/* 0x000fca0006800000 */
/*0900*/ IMAD.SHL.U32 R24, R24, 0x8, RZ ; /* 0x0000000818187824 */
/* 0x000fe200078e00ff */
/*0910*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fc80007ffe0ff */
/*0920*/ ISETP.GE.AND P0, PT, R21, R18, PT ; /* 0x000000121500720c */
/* 0x000fe40003f06270 */
/*0930*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f3e0ff */
/*0940*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0950*/ DFMA R14, R14, R6, R2 ; /* 0x000000060e0e722b */
/* 0x0060e40000000002 */
/*0960*/ LDC.64 R6, c[0x3][R23] ; /* 0x00c0000017067b82 */
/* 0x001f300000000a00 */
/*0970*/ LDC.64 R2, c[0x3][R24] ; /* 0x00c0000018027b82 */
/* 0x000f620000000a00 */
/*0980*/ DFMA R8, R16, R8, R14 ; /* 0x000000081008722b */
/* 0x008f0c000000000e */
/*0990*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x010f4c0000000008 */
/*09a0*/ DFMA R2, R2, R12, R6 ; /* 0x0000000c0202722b */
/* 0x0200620000000006 */
/*09b0*/ @!P0 BRA 0x4d0 ; /* 0xfffffb1000008947 */
/* 0x000fea000383ffff */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*09d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*09e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea4000c1e1b00 */
/*09f0*/ DADD R6, R6, R2 ; /* 0x0000000006067229 */
/* 0x006e0e0000000002 */
/*0a00*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //使用constant memory存放向量
//global memory
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
cudaMalloc((void **)&A_d,Max * Max * sizeof(double));
cudaMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
cudaMemcpy(A_d, A,Max*Max*sizeof(double),cudaMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
cudaMemcpy(C_d, C,Max * sizeof(double), cudaMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
cudaMemcpyToSymbol(con_b, &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
cudaMemcpy(C, C_d, Max * sizeof(double), cudaMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
cudaFree(A_d);
cudaFree(C_d);
free(A);
free(test_c);
free(C);
} | .file "tmpxft_000989cd_00000000-6_ex7_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5multiPdS_iiPdS_ii
.type _Z28__device_stub__Z5multiPdS_iiPdS_ii, @function
_Z28__device_stub__Z5multiPdS_iiPdS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5multiPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5multiPdS_iiPdS_ii, .-_Z28__device_stub__Z5multiPdS_iiPdS_ii
.globl _Z5multiPdS_ii
.type _Z5multiPdS_ii, @function
_Z5multiPdS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5multiPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5multiPdS_ii, .-_Z5multiPdS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\344\275\277\347\224\250constant memory\345\255\230\346\224\276\345\220\221\351\207\217:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU TIME:%lf ms\n"
.LC5:
.string "CPU TIME:%lf ms\n"
.LC7:
.string "cpu:%lf gpu:%lf\n"
.LC8:
.string "result correct\n"
.LC9:
.string "resul wrong\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl Max(%rip), %r15d
movl %r15d, %eax
imull %r15d, %eax
cltq
salq $3, %rax
movq %rax, -128(%rbp)
movq %rax, %rdi
call malloc@PLT
movq %rax, -104(%rbp)
movslq %r15d, %r13
leaq 0(,%r13,8), %rax
movq %rax, -120(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
movq -120(%rbp), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %r12, %rdi
call malloc@PLT
movq %rax, -112(%rbp)
testl %r15d, %r15d
jle .L15
movq -104(%rbp), %rdx
movl $0, %ecx
movsd .LC1(%rip), %xmm4
movsd .LC2(%rip), %xmm3
.L16:
movl $0, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %ecx, %xmm2
.L17:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm4, %xmm1
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
addsd %xmm3, %xmm0
movsd %xmm0, (%rdx,%rax,8)
movq %rax, %r12
addq $1, %rax
cmpq %rax, %r13
jne .L17
addl $1, %ecx
movq -120(%rbp), %rax
addq %rax, %rdx
cmpl %ecx, %r15d
jne .L16
movl $0, %r13d
movl $0x000000000, %r15d
jmp .L18
.L35:
movq %rax, %r13
.L18:
leal -1(%r13), %eax
imull %r13d, %eax
addl $2, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq %r15, %xmm5
ucomisd %xmm0, %xmm5
ja .L42
sqrtsd %xmm0, %xmm0
.L21:
call log@PLT
movsd %xmm0, (%rbx,%r13,8)
movq $0x000000000, (%r14,%r13,8)
leaq 1(%r13), %rax
cmpq %r12, %r13
jne .L35
.L15:
leaq -96(%rbp), %rdi
movq -128(%rbp), %rsi
call cudaMalloc@PLT
movslq Max(%rip), %rsi
salq $3, %rsi
leaq -88(%rbp), %rdi
call cudaMalloc@PLT
call clock@PLT
movq %rax, -120(%rbp)
movl Max(%rip), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $3, %rdx
movl $1, %ecx
movq -104(%rbp), %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movslq Max(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl width(%rip), %r13d
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl Max(%rip), %eax
movl $0, %edx
divl %r13d
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r12d
leaq _ZL5con_b(%rip), %r15
.L23:
movl Max(%rip), %ecx
movslq %ecx, %rdx
salq $3, %rdx
shrq %rdx
imull %r12d, %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
cltq
leaq (%rbx,%rax,8), %rsi
movl $1, %r8d
movl $0, %ecx
movq %r15, %rdi
call cudaMemcpyToSymbol@PLT
movl %r13d, -80(%rbp)
movl -72(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movq -68(%rbp), %rdi
movl -60(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L22:
addl $1, %r12d
cmpl $2, %r12d
jne .L23
movslq Max(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq -120(%rbp), %rdi
subq %rdi, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm6, %xmm6
cvtsi2sdq %rdx, %xmm6
movq %xmm6, %r13
call clock@PLT
movq %rax, %r12
movl Max(%rip), %r9d
testl %r9d, %r9d
jle .L24
movq -112(%rbp), %rax
movq %rax, %rsi
movslq %r9d, %rcx
salq $3, %rcx
leaq (%rax,%rcx), %r10
movl $0, %edi
.L25:
movq %rsi, %r8
movsd (%rsi), %xmm1
movslq %edi, %rax
movq -104(%rbp), %rdx
leaq (%rdx,%rax,8), %rdx
movl $0, %eax
.L26:
movsd (%rdx,%rax), %xmm0
mulsd (%rbx,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L26
movsd %xmm1, (%r8)
addq $8, %rsi
addl %r9d, %edi
cmpq %r10, %rsi
jne .L25
.L24:
call clock@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm7, %xmm7
cvtsi2sdq %rdx, %xmm7
movq %xmm7, %rbx
movq %r13, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, Max(%rip)
jle .L27
movl $0, %ebx
movl $1, %eax
leaq .LC7(%rip), %r12
movl $0, %r13d
jmp .L30
.L42:
call sqrt@PLT
jmp .L21
.L44:
movl %r12d, %ecx
movl Max(%rip), %edx
movq -88(%rbp), %rsi
movq -96(%rbp), %rdi
call _Z28__device_stub__Z5multiPdS_iiPdS_ii
jmp .L22
.L28:
addq $1, %rbx
cmpl %ebx, Max(%rip)
jle .L45
.L30:
movq -112(%rbp), %rdi
movsd (%rdi,%rbx,8), %xmm2
movsd (%r14,%rbx,8), %xmm1
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
andpd .LC6(%rip), %xmm0
comisd err(%rip), %xmm0
jbe .L28
movapd %xmm2, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r13d, %eax
jmp .L28
.L45:
testb %al, %al
jne .L27
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L27:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L32:
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call free@PLT
movq -112(%rbp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5multiPdS_ii"
.LC11:
.string "con_b"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5multiPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $65536, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5con_b(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5con_b
.comm _ZL5con_b,65536,32
.globl err
.data
.align 8
.type err, @object
.size err, 8
err:
.long -1717986918
.long 1069128089
.globl width
.align 4
.type width, @object
.size width, 4
width:
.long 32
.globl Max
.align 4
.type Max, @object
.size Max, 4
Max:
.long 16384
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.align 8
.LC2:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //使用constant memory存放向量
//global memory
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
cudaMalloc((void **)&A_d,Max * Max * sizeof(double));
cudaMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
cudaMemcpy(A_d, A,Max*Max*sizeof(double),cudaMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
cudaMemcpy(C_d, C,Max * sizeof(double), cudaMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
cudaMemcpyToSymbol(con_b, &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
cudaMemcpy(C, C_d, Max * sizeof(double), cudaMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
cudaFree(A_d);
cudaFree(C_d);
free(A);
free(test_c);
free(C);
} | //使用constant memory存放向量
//global memory
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
hipMalloc((void **)&A_d,Max * Max * sizeof(double));
hipMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
hipMemcpy(A_d, A,Max*Max*sizeof(double),hipMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
hipMemcpy(C_d, C,Max * sizeof(double), hipMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
hipMemcpyToSymbol(HIP_SYMBOL(con_b), &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
hipMemcpy(C, C_d, Max * sizeof(double), hipMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
hipFree(A_d);
hipFree(C_d);
free(A);
free(test_c);
free(C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //使用constant memory存放向量
//global memory
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
hipMalloc((void **)&A_d,Max * Max * sizeof(double));
hipMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
hipMemcpy(A_d, A,Max*Max*sizeof(double),hipMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
hipMemcpy(C_d, C,Max * sizeof(double), hipMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
hipMemcpyToSymbol(HIP_SYMBOL(con_b), &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
hipMemcpy(C, C_d, Max * sizeof(double), hipMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
hipFree(A_d);
hipFree(C_d);
free(A);
free(test_c);
free(C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5multiPdS_ii
.globl _Z5multiPdS_ii
.p2align 8
.type _Z5multiPdS_ii,@function
_Z5multiPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x14
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s2, s4
s_add_i32 s2, s2, 1
s_lshr_b32 s5, s3, 31
s_mul_i32 s6, s2, s4
s_add_i32 s3, s3, s5
s_lshr_b32 s5, s6, 31
s_ashr_i32 s2, s3, 1
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s6, 1
s_cmp_ge_i32 s2, s3
s_cbranch_scc1 .LBB0_4
s_lshr_b32 s5, s4, 31
s_load_b64 s[6:7], s[0:1], 0x0
s_add_i32 s5, s4, s5
v_mad_u64_u32 v[2:3], null, v1, s4, s[2:3]
s_ashr_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s8, s5, 31
s_add_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s5, s8
v_ashrrev_i32_e32 v3, 31, v2
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
v_readfirstlane_b32 s6, v0
s_ashr_i32 s7, s2, 31
v_add_co_u32 v5, vcc_lo, v5, 8
s_add_i32 s9, s2, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s5, s6
s_xor_b32 s9, s9, s7
s_mul_hi_u32 s8, s6, s8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s6, s6, s8
s_mul_hi_u32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
s_sub_i32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s7
s_sub_i32 s6, s6, s7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, con_b@rel32@lo+4
s_addc_u32 s9, s9, con_b@rel32@hi+12
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 3
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_add_i32 s2, s2, 1
s_load_b64 s[6:7], s[6:7], 0x0
s_cmp_lt_i32 s2, s3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[7:8], s[6:7], v[3:4]
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[5:6], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[5:6]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5multiPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5multiPdS_ii, .Lfunc_end0-_Z5multiPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected con_b
.type con_b,@object
.section .bss,"aw",@nobits
.globl con_b
.p2align 4, 0x0
con_b:
.zero 65536
.size con_b, 65536
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym con_b
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5multiPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5multiPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //使用constant memory存放向量
//global memory
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <stdlib.h>
int Max=16384;
int width=32;
double err = 0.1;
__constant__ double con_b[8192];
__global__ void multi(double *A,double *C,const int Max,int i){
int idx=threadIdx.x+blockDim.x*blockIdx.x;
//int idy=threadIdx.y+blockDim.y*blockIdx.y;
if(idx<Max){
int k=0;
double sum=0;
for(k=i*Max/2;k<(i+1)*Max/2;k++){
sum+=A[idx*Max+k]*con_b[k%(Max/2)];
}
C[idx]+=sum;
}
}
int main(){
printf("使用constant memory存放向量:\n");
double *A =(double *)malloc(Max * Max * sizeof(double)); //A
double b[Max]; //b
double *C =(double *)malloc(Max * sizeof(double)); //C
double *test_c=(double *)malloc(Max * sizeof(double)); //cpu_test
int i,j;
for(i=0;i<Max;i++){
for(j=0;j<Max;j++){
A[i*Max+j]=i-0.1*j+1;
}
}
for(i=0;i<Max;i++){
b[i]=log(sqrt(i*i-i+2));
C[i]=0.0;
}
double *A_d,*C_d;
hipMalloc((void **)&A_d,Max * Max * sizeof(double));
hipMalloc((void **)&C_d,Max *sizeof(double));
clock_t start,end;
start=clock();
hipMemcpy(A_d, A,Max*Max*sizeof(double),hipMemcpyHostToDevice);
//cudaMemcpyToSymbol(con_b, b, sizeof(double) * Max);
hipMemcpy(C_d, C,Max * sizeof(double), hipMemcpyHostToDevice);
dim3 block(width,1);
dim3 grid(Max/block.x, 1);
for(int i=0;i<2;i++){
hipMemcpyToSymbol(HIP_SYMBOL(con_b), &b[i*Max/2], sizeof(double) * Max/2);
multi<<<grid,block>>>(A_d,C_d,Max,i);
}
hipMemcpy(C, C_d, Max * sizeof(double), hipMemcpyDeviceToHost);
end=clock();
double time=(end-start)*1000/CLOCKS_PER_SEC;
//cpu:
clock_t start_c,end_c;
start_c=clock();
for (int i = 0; i < Max; ++i){
for (int j = 0; j < Max; ++j)
{
test_c[i]+=A[i*Max+j]*b[j];
}
}
end_c=clock();
double time_C=(end_c-start_c)*1000/CLOCKS_PER_SEC;
printf("GPU TIME:%lf ms\n",time);
printf("CPU TIME:%lf ms\n",time_C);
//check result:
bool flag = true;
for (int i = 0; i < Max; ++i){
double a=test_c[i];
double b=C[i];
if (abs(a-b)>err)
{
printf("cpu:%lf gpu:%lf\n",a,b);
flag = false;
}
}
if (flag == true)
printf("result correct\n");
else{
printf("resul wrong\n");
}
hipFree(A_d);
hipFree(C_d);
free(A);
free(test_c);
free(C);
} | .text
.file "ex7_3.hip"
.globl _Z20__device_stub__multiPdS_ii # -- Begin function _Z20__device_stub__multiPdS_ii
.p2align 4, 0x90
.type _Z20__device_stub__multiPdS_ii,@function
_Z20__device_stub__multiPdS_ii: # @_Z20__device_stub__multiPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5multiPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__multiPdS_ii, .Lfunc_end0-_Z20__device_stub__multiPdS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xbfb999999999999a # double -0.10000000000000001
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $.Lstr, %edi
callq puts@PLT
movslq Max(%rip), %r12
movl %r12d, %r14d
movl %r12d, %edi
imull %edi, %edi
shlq $3, %rdi
callq malloc
movq %rax, %r13
movq %rsp, %rbx
leaq 15(,%r14,8), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
leaq (,%r12,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, -48(%rbp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, -96(%rbp) # 8-byte Spill
testq %r12, %r12
jle .LBB1_5
# %bb.1: # %.preheader77.lr.ph
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %edx
leaq (,%rdx,8), %rdx
addq %r13, %rdx
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
addsd %xmm2, %xmm3
addsd %xmm1, %xmm3
movsd %xmm3, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r14d, %eax
cmpq %r14, %rcx
jne .LBB1_2
.LBB1_5: # %.preheader76
movl Max(%rip), %esi
testl %esi, %esi
movq -48(%rbp), %r15 # 8-byte Reload
jle .LBB1_11
# %bb.6: # %.lr.ph81.preheader
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # %call.sqrt
# in Loop: Header=BB1_7 Depth=1
callq sqrt
.LBB1_10: # %.lr.ph81.split
# in Loop: Header=BB1_7 Depth=1
callq log
movsd %xmm0, (%rbx,%r14,8)
movq $0, (%r15,%r14,8)
incq %r14
movslq Max(%rip), %rsi
cmpq %rsi, %r14
jge .LBB1_11
.LBB1_7: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
leal -1(%r14), %eax
imull %r14d, %eax
addl $2, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd .LCPI1_3(%rip), %xmm0
jb .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB1_10
.LBB1_11: # %._crit_edge82
imull %esi, %esi
shlq $3, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movslq Max(%rip), %rsi
shlq $3, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
callq clock
movq %rax, -64(%rbp) # 8-byte Spill
movq -72(%rbp), %rdi
movl Max(%rip), %edx
imull %edx, %edx
shlq $3, %rdx
movq %r13, -104(%rbp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movslq Max(%rip), %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl width(%rip), %r12d
movabsq $4294967296, %rcx # imm = 0x100000000
movl Max(%rip), %eax
xorl %edx, %edx
divl %r12d
movl %eax, %r13d
orq %rcx, %r12
xorl %r14d, %r14d
orq %rcx, %r13
movabsq $9223372036854775804, %r15 # imm = 0x7FFFFFFFFFFFFFFC
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=1
incl %r14d
cmpl $1, %r14d
jne .LBB1_15
.LBB1_12: # =>This Inner Loop Header: Depth=1
movslq Max(%rip), %rdx
movl %edx, %eax
imull %r14d, %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movslq %ecx, %rax
leaq (%rbx,%rax,8), %rsi
shlq $2, %rdx
andq %r15, %rdx
movl $con_b, %edi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=1
movq -72(%rbp), %rax
movq -56(%rbp), %rcx
movl Max(%rip), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -80(%rbp)
movl %r14d, -76(%rbp)
leaq -168(%rbp), %rax
movq %rax, -208(%rbp)
leaq -160(%rbp), %rax
movq %rax, -200(%rbp)
leaq -80(%rbp), %rax
movq %rax, -192(%rbp)
leaq -76(%rbp), %rax
movq %rax, -184(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -112(%rbp), %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z5multiPdS_ii, %edi
leaq -208(%rbp), %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_14
.LBB1_15:
movq -56(%rbp), %rsi
movslq Max(%rip), %rdx
shlq $3, %rdx
movq -48(%rbp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
subq -64(%rbp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %r14 # imm = 0x20C49BA5E353F7CF
imulq %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -64(%rbp) # 8-byte Spill
callq clock
movq %rax, %r12
movl Max(%rip), %eax
testl %eax, %eax
movq -104(%rbp), %r15 # 8-byte Reload
movq -96(%rbp), %r13 # 8-byte Reload
jle .LBB1_20
# %bb.16: # %.preheader.lr.ph
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movl %ecx, %esi
leaq (%r15,%rsi,8), %rsi
movsd (%r13,%rdx,8), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rdi,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rbx,%rdi,8), %xmm1
addsd %xmm1, %xmm0
incq %rdi
cmpq %rdi, %rax
jne .LBB1_18
# %bb.19: # %._crit_edge86
# in Loop: Header=BB1_17 Depth=1
movsd %xmm0, (%r13,%rdx,8)
incq %rdx
addl %eax, %ecx
cmpq %rax, %rdx
jne .LBB1_17
.LBB1_20: # %._crit_edge89
callq clock
subq %r12, %rax
imulq %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -88(%rbp) # 8-byte Spill
movb $1, %bl
movl $.L.str.1, %edi
movsd -64(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd -88(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
cmpl $0, Max(%rip)
jle .LBB1_21
# %bb.22: # %.lr.ph93.preheader
xorl %r14d, %r14d
movapd .LCPI1_2(%rip), %xmm3 # xmm3 = [NaN,NaN]
movq -48(%rbp), %r12 # 8-byte Reload
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_23 Depth=1
incq %r14
movslq Max(%rip), %rax
cmpq %rax, %r14
jge .LBB1_26
.LBB1_23: # %.lr.ph93
# =>This Inner Loop Header: Depth=1
movsd (%r13,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r12,%r14,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
andpd %xmm3, %xmm2
ucomisd err(%rip), %xmm2
jbe .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movapd .LCPI1_2(%rip), %xmm3 # xmm3 = [NaN,NaN]
xorl %ebx, %ebx
jmp .LBB1_25
.LBB1_26: # %._crit_edge94.loopexit
testb $1, %bl
movl $.Lstr.1, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
jmp .LBB1_27
.LBB1_21:
movl $.Lstr.2, %edi
movq -48(%rbp), %r12 # 8-byte Reload
.LBB1_27: # %.critedge
callq puts@PLT
movq -72(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r13, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5multiPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $con_b, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $65536, %r9d # imm = 0x10000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type Max,@object # @Max
.data
.globl Max
.p2align 2, 0x0
Max:
.long 16384 # 0x4000
.size Max, 4
.type width,@object # @width
.globl width
.p2align 2, 0x0
width:
.long 32 # 0x20
.size width, 4
.type err,@object # @err
.globl err
.p2align 3, 0x0
err:
.quad 0x3fb999999999999a # double 0.10000000000000001
.size err, 8
.type con_b,@object # @con_b
.local con_b
.comm con_b,65536,16
.type _Z5multiPdS_ii,@object # @_Z5multiPdS_ii
.section .rodata,"a",@progbits
.globl _Z5multiPdS_ii
.p2align 3, 0x0
_Z5multiPdS_ii:
.quad _Z20__device_stub__multiPdS_ii
.size _Z5multiPdS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "GPU TIME:%lf ms\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU TIME:%lf ms\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cpu:%lf gpu:%lf\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5multiPdS_ii"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "con_b"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\344\275\277\347\224\250constant memory\345\255\230\346\224\276\345\220\221\351\207\217:"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "resul wrong"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "result correct"
.size .Lstr.2, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__multiPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym con_b
.addrsig_sym _Z5multiPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5multiPdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD R2, R19, c[0x0][0x174], RZ ; /* 0x00005d0013027a24 */
/* 0x000fca00078e02ff */
/*0090*/ IADD3 R3, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002037a10 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LEA.HI R21, R2, R2, RZ, 0x1 ; /* 0x0000000202157211 */
/* 0x000fe400078f08ff */
/*00b0*/ LEA.HI R18, R3, R3, RZ, 0x1 ; /* 0x0000000303127211 */
/* 0x000fe400078f08ff */
/*00c0*/ SHF.R.S32.HI R21, RZ, 0x1, R21 ; /* 0x00000001ff157819 */
/* 0x000fe20000011415 */
/*00d0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*00e0*/ SHF.R.S32.HI R18, RZ, 0x1, R18 ; /* 0x00000001ff127819 */
/* 0x000fc80000011412 */
/*00f0*/ ISETP.GT.AND P0, PT, R18, R21, PT ; /* 0x000000151200720c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 BRA 0x9c0 ; /* 0x000008b000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.IADD R2, R18, 0x1, -R21 ; /* 0x0000000112027824 */
/* 0x000fe200078e0a15 */
/*0120*/ LOP3.LUT R3, RZ, R21, RZ, 0x33, !PT ; /* 0x00000015ff037212 */
/* 0x000fe400078e33ff */
/*0130*/ LEA.HI R19, R19, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0013137a11 */
/* 0x000fe400078f08ff */
/*0140*/ LOP3.LUT P1, R10, R2, 0x3, RZ, 0xc0, !PT ; /* 0x00000003020a7812 */
/* 0x000fe2000782c0ff */
/*0150*/ IMAD.IADD R3, R18, 0x1, R3 ; /* 0x0000000112037824 */
/* 0x000fe200078e0203 */
/*0160*/ SHF.R.S32.HI R19, RZ, 0x1, R19 ; /* 0x00000001ff137819 */
/* 0x000fc80000011413 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0180*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fca000001ff00 */
/*0190*/ @!P1 BRA 0x400 ; /* 0x0000026000009947 */
/* 0x000fec0003800000 */
/*01a0*/ IABS R4, R19.reuse ; /* 0x0000001300047213 */
/* 0x080fe20000000000 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.NE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f25270 */
/*01d0*/ IMAD R8, R0, c[0x0][0x170], R21 ; /* 0x00005c0000087a24 */
/* 0x000fe200078e0215 */
/*01e0*/ I2F.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000209400 */
/*01f0*/ LOP3.LUT R11, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff0b7212 */
/* 0x000fe400078e33ff */
/*0200*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0209 */
/*0210*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0260*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R5, R3, R7, R2 ; /* 0x0000000703057227 */
/* 0x000fe400078e0002 */
/*0280*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*0290*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x0010a2000c1e1b00 */
/*02a0*/ IABS R12, R19 ; /* 0x00000013000c7213 */
/* 0x000fe40000000000 */
/*02b0*/ IABS R13, R21 ; /* 0x00000015000d7213 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.GE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe20003f66270 */
/*02d0*/ IMAD.MOV R14, RZ, RZ, -R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0c */
/*02e0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.HI.U32 R12, R5, R13, RZ ; /* 0x0000000d050c7227 */
/* 0x000fe200078e00ff */
/*0300*/ IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fc60007ffe0ff */
/*0310*/ IMAD R13, R12, R14, R13 ; /* 0x0000000e0c0d7224 */
/* 0x000fe200078e020d */
/*0320*/ IABS R12, R19 ; /* 0x00000013000c7213 */
/* 0x000fc80000000000 */
/*0330*/ ISETP.GT.U32.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fda0003f44070 */
/*0340*/ @!P2 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0da824 */
/* 0x000fca00078e0a0c */
/*0350*/ ISETP.GT.U32.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fda0003f44070 */
/*0360*/ @!P2 IMAD.IADD R13, R13, 0x1, -R12 ; /* 0x000000010d0da824 */
/* 0x000fe200078e0a0c */
/*0370*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f45270 */
/*0380*/ @!P3 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0db224 */
/* 0x000fe200078e0a0d */
/*0390*/ IADD3 R8, P3, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x001fc80007f7e0ff */
/*03a0*/ SEL R13, R11, R13, !P1 ; /* 0x0000000d0b0d7207 */
/* 0x000fe20004800000 */
/*03b0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fc800018e0609 */
/*03c0*/ IMAD.SHL.U32 R13, R13, 0x8, RZ ; /* 0x000000080d0d7824 */
/* 0x000fcc00078e00ff */
/*03d0*/ LDC.64 R12, c[0x3][R13] ; /* 0x00c000000d0c7b82 */
/* 0x000ea40000000a00 */
/*03e0*/ DFMA R2, R12, R6, R2 ; /* 0x000000060c02722b */
/* 0x0060620000000002 */
/*03f0*/ @P2 BRA 0x290 ; /* 0xfffffe9000002947 */
/* 0x000fea000383ffff */
/*0400*/ @!P0 BRA 0x9c0 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*0410*/ IABS R20, R19 ; /* 0x0000001300147213 */
/* 0x000fe20000000000 */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0430*/ IMAD R4, R0, c[0x0][0x170], R21 ; /* 0x00005c0000047a24 */
/* 0x000fe200078e0215 */
/*0440*/ I2F.RP R6, R20 ; /* 0x0000001400067306 */
/* 0x001e220000209400 */
/*0450*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0470*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0480*/ IADD3 R23, R6, 0xffffffe, RZ ; /* 0x0ffffffe06177810 */
/* 0x001fcc0007ffe0ff */
/*0490*/ F2I.FTZ.U32.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000e24000021f000 */
/*04a0*/ IMAD.MOV R7, RZ, RZ, -R23 ; /* 0x000000ffff077224 */
/* 0x001fc800078e0a17 */
/*04b0*/ IMAD R7, R7, R20, RZ ; /* 0x0000001407077224 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD.HI.U32 R22, R23, R7, R22 ; /* 0x0000000717167227 */
/* 0x000fc800078e0016 */
/*04d0*/ IABS R16, R19 ; /* 0x0000001300107213 */
/* 0x000fe20000000000 */
/*04e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x0010a2000c1e1b00 */
/*04f0*/ IABS R27, R21 ; /* 0x00000015001b7213 */
/* 0x000fe40000000000 */
/*0500*/ I2F.RP R8, R16 ; /* 0x0000001000087306 */
/* 0x000ee20000209400 */
/*0510*/ IABS R9, R19 ; /* 0x0000001300097213 */
/* 0x000fce0000000000 */
/*0520*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x008ee40000001000 */
/*0530*/ IADD3 R23, R8, 0xffffffe, RZ ; /* 0x0ffffffe08177810 */
/* 0x008fcc0007ffe0ff */
/*0540*/ F2I.FTZ.U32.TRUNC.NTZ R23, R23 ; /* 0x0000001700177305 */
/* 0x000ee2000021f000 */
/*0550*/ IADD3 R14, R21, 0x1, RZ ; /* 0x00000001150e7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.MOV R25, RZ, RZ, -R9 ; /* 0x000000ffff197224 */
/* 0x000fe400078e0a09 */
/*0570*/ IMAD.HI.U32 R8, R22, R27, RZ ; /* 0x0000001b16087227 */
/* 0x000fe200078e00ff */
/*0580*/ IABS R10, R14 ; /* 0x0000000e000a7213 */
/* 0x000fc60000000000 */
/*0590*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*05a0*/ IMAD.MOV R11, RZ, RZ, -R23 ; /* 0x000000ffff0b7224 */
/* 0x008fc800078e0a17 */
/*05b0*/ IMAD R9, R11, R16, RZ ; /* 0x000000100b097224 */
/* 0x000fe200078e02ff */
/*05c0*/ IADD3 R15, R21, 0x2, RZ ; /* 0x00000002150f7810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ IMAD.HI.U32 R22, R23, R9, R22 ; /* 0x0000000917167227 */
/* 0x000fe200078e0016 */
/*05e0*/ MOV R23, R10 ; /* 0x0000000a00177202 */
/* 0x000fe40000000f00 */
/*05f0*/ IADD3 R26, R21, 0x3, RZ ; /* 0x00000003151a7810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD R27, R8, R25, R27 ; /* 0x00000019081b7224 */
/* 0x000fe200078e021b */
/*0610*/ IABS R17, R15 ; /* 0x0000000f00117213 */
/* 0x000fe20000000000 */
/*0620*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x0000e2000c1e1b00 */
/*0630*/ IMAD.HI.U32 R10, R22, R23, RZ ; /* 0x00000017160a7227 */
/* 0x000fe200078e00ff */
/*0640*/ IABS R12, R26 ; /* 0x0000001a000c7213 */
/* 0x000fc60000000000 */
/*0650*/ IMAD R23, R10, R25, R23 ; /* 0x000000190a177224 */
/* 0x000fe400078e0217 */
/*0660*/ IMAD.HI.U32 R24, R22.reuse, R17, RZ ; /* 0x0000001116187227 */
/* 0x040fe200078e00ff */
/*0670*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000126000c1e1b00 */
/*0680*/ IMAD.HI.U32 R13, R22, R12, RZ ; /* 0x0000000c160d7227 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD R17, R24, R25.reuse, R17 ; /* 0x0000001918117224 */
/* 0x080fe400078e0211 */
/*06a0*/ IMAD R25, R13, R25, R12 ; /* 0x000000190d197224 */
/* 0x000fe400078e020c */
/*06b0*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000162000c1e1b00 */
/*06c0*/ ISETP.GT.U32.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fda0003f04070 */
/*06d0*/ @!P0 IMAD.IADD R27, R27, 0x1, -R16 ; /* 0x000000011b1b8824 */
/* 0x000fca00078e0a10 */
/*06e0*/ ISETP.GT.U32.AND P4, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f84070 */
/*06f0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0010 */
/*0700*/ ISETP.GE.AND P3, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc80003f66270 */
/*0710*/ ISETP.GT.U32.AND P5, PT, R20.reuse, R23, PT ; /* 0x000000171400720c */
/* 0x040fe40003fa4070 */
/*0720*/ ISETP.GT.U32.AND P1, PT, R20.reuse, R17, PT ; /* 0x000000111400720c */
/* 0x040fe40003f24070 */
/*0730*/ ISETP.GT.U32.AND P2, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fc60003f44070 */
/*0740*/ @!P4 IMAD.IADD R27, R27, 0x1, -R16 ; /* 0x000000011b1bc824 */
/* 0x000fe200078e0a10 */
/*0750*/ LOP3.LUT R24, RZ, R19, RZ, 0x33, !PT ; /* 0x00000013ff187212 */
/* 0x000fca00078e33ff */
/*0760*/ @!P5 IMAD.IADD R23, R23, 0x1, -R16 ; /* 0x000000011717d824 */
/* 0x000fe200078e0a10 */
/*0770*/ ISETP.NE.AND P5, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003fa5270 */
/*0780*/ @!P3 IMAD.MOV R27, RZ, RZ, -R27 ; /* 0x000000ffff1bb224 */
/* 0x000fc600078e0a1b */
/*0790*/ ISETP.GT.U32.AND P3, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f64070 */
/*07a0*/ @!P1 IMAD.IADD R17, R17, 0x1, -R16.reuse ; /* 0x0000000111119824 */
/* 0x100fe200078e0a10 */
/*07b0*/ SEL R27, R24, R27, !P5 ; /* 0x0000001b181b7207 */
/* 0x000fe40006800000 */
/*07c0*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f06270 */
/*07d0*/ @!P2 IMAD.IADD R25, R25, 0x1, -R16 ; /* 0x000000011919a824 */
/* 0x000fe200078e0a10 */
/*07e0*/ ISETP.GT.U32.AND P1, PT, R20.reuse, R17, PT ; /* 0x000000111400720c */
/* 0x040fe20003f24070 */
/*07f0*/ IMAD.SHL.U32 R14, R27, 0x8, RZ ; /* 0x000000081b0e7824 */
/* 0x000fe200078e00ff */
/*0800*/ ISETP.GE.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f86270 */
/*0810*/ ISETP.GT.U32.AND P2, PT, R20, R25, PT ; /* 0x000000191400720c */
/* 0x000fc60003f44070 */
/*0820*/ @!P3 IMAD.IADD R23, R23, 0x1, -R16.reuse ; /* 0x000000011717b824 */
/* 0x100fe200078e0a10 */
/*0830*/ LDC.64 R14, c[0x3][R14] ; /* 0x00c000000e0e7b82 */
/* 0x000ea20000000a00 */
/*0840*/ ISETP.GE.AND P6, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003fc6270 */
/*0850*/ @!P0 IMAD.MOV R23, RZ, RZ, -R23 ; /* 0x000000ffff178224 */
/* 0x000fe400078e0a17 */
/*0860*/ @!P1 IMAD.IADD R17, R17, 0x1, -R16 ; /* 0x0000000111119824 */
/* 0x000fc600078e0a10 */
/*0870*/ SEL R23, R24, R23, !P5 ; /* 0x0000001718177207 */
/* 0x000fe20006800000 */
/*0880*/ @!P4 IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff11c224 */
/* 0x000fe200078e0a11 */
/*0890*/ @!P2 IADD3 R25, R25, -R16, RZ ; /* 0x800000101919a210 */
/* 0x000fc60007ffe0ff */
/*08a0*/ IMAD.SHL.U32 R16, R23, 0x8, RZ ; /* 0x0000000817107824 */
/* 0x000fe200078e00ff */
/*08b0*/ SEL R23, R24, R17, !P5 ; /* 0x0000001118177207 */
/* 0x000fe20006800000 */
/*08c0*/ @!P6 IMAD.MOV R25, RZ, RZ, -R25 ; /* 0x000000ffff19e224 */
/* 0x000fc800078e0a19 */
/*08d0*/ LDC.64 R16, c[0x3][R16] ; /* 0x00c0000010107b82 */
/* 0x000ee20000000a00 */
/*08e0*/ IMAD.SHL.U32 R23, R23, 0x8, RZ ; /* 0x0000000817177824 */
/* 0x000fe200078e00ff */
/*08f0*/ SEL R24, R24, R25, !P5 ; /* 0x0000001918187207 */
/* 0x000fca0006800000 */
/*0900*/ IMAD.SHL.U32 R24, R24, 0x8, RZ ; /* 0x0000000818187824 */
/* 0x000fe200078e00ff */
/*0910*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fc80007ffe0ff */
/*0920*/ ISETP.GE.AND P0, PT, R21, R18, PT ; /* 0x000000121500720c */
/* 0x000fe40003f06270 */
/*0930*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f3e0ff */
/*0940*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0950*/ DFMA R14, R14, R6, R2 ; /* 0x000000060e0e722b */
/* 0x0060e40000000002 */
/*0960*/ LDC.64 R6, c[0x3][R23] ; /* 0x00c0000017067b82 */
/* 0x001f300000000a00 */
/*0970*/ LDC.64 R2, c[0x3][R24] ; /* 0x00c0000018027b82 */
/* 0x000f620000000a00 */
/*0980*/ DFMA R8, R16, R8, R14 ; /* 0x000000081008722b */
/* 0x008f0c000000000e */
/*0990*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x010f4c0000000008 */
/*09a0*/ DFMA R2, R2, R12, R6 ; /* 0x0000000c0202722b */
/* 0x0200620000000006 */
/*09b0*/ @!P0 BRA 0x4d0 ; /* 0xfffffb1000008947 */
/* 0x000fea000383ffff */
/*09c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*09d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*09e0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x001ea4000c1e1b00 */
/*09f0*/ DADD R6, R6, R2 ; /* 0x0000000006067229 */
/* 0x006e0e0000000002 */
/*0a00*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5multiPdS_ii
.globl _Z5multiPdS_ii
.p2align 8
.type _Z5multiPdS_ii,@function
_Z5multiPdS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[0:1], 0x14
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s2, s4
s_add_i32 s2, s2, 1
s_lshr_b32 s5, s3, 31
s_mul_i32 s6, s2, s4
s_add_i32 s3, s3, s5
s_lshr_b32 s5, s6, 31
s_ashr_i32 s2, s3, 1
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s6, 1
s_cmp_ge_i32 s2, s3
s_cbranch_scc1 .LBB0_4
s_lshr_b32 s5, s4, 31
s_load_b64 s[6:7], s[0:1], 0x0
s_add_i32 s5, s4, s5
v_mad_u64_u32 v[2:3], null, v1, s4, s[2:3]
s_ashr_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s8, s5, 31
s_add_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s5, s8
v_ashrrev_i32_e32 v3, 31, v2
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
v_readfirstlane_b32 s6, v0
s_ashr_i32 s7, s2, 31
v_add_co_u32 v5, vcc_lo, v5, 8
s_add_i32 s9, s2, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s5, s6
s_xor_b32 s9, s9, s7
s_mul_hi_u32 s8, s6, s8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s6, s6, s8
s_mul_hi_u32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s4
s_sub_i32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_sub_i32 s8, s6, s4
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s7
s_sub_i32 s6, s6, s7
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, con_b@rel32@lo+4
s_addc_u32 s9, s9, con_b@rel32@hi+12
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 3
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
s_add_i32 s2, s2, 1
s_load_b64 s[6:7], s[6:7], 0x0
s_cmp_lt_i32 s2, s3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[7:8], s[6:7], v[3:4]
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[5:6], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[3:4], v[5:6]
global_store_b64 v[0:1], v[2:3], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5multiPdS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5multiPdS_ii, .Lfunc_end0-_Z5multiPdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected con_b
.type con_b,@object
.section .bss,"aw",@nobits
.globl con_b
.p2align 4, 0x0
con_b:
.zero 65536
.size con_b, 65536
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym con_b
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5multiPdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5multiPdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000989cd_00000000-6_ex7_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5multiPdS_iiPdS_ii
.type _Z28__device_stub__Z5multiPdS_iiPdS_ii, @function
_Z28__device_stub__Z5multiPdS_iiPdS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5multiPdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5multiPdS_iiPdS_ii, .-_Z28__device_stub__Z5multiPdS_iiPdS_ii
.globl _Z5multiPdS_ii
.type _Z5multiPdS_ii, @function
_Z5multiPdS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5multiPdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5multiPdS_ii, .-_Z5multiPdS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\344\275\277\347\224\250constant memory\345\255\230\346\224\276\345\220\221\351\207\217:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU TIME:%lf ms\n"
.LC5:
.string "CPU TIME:%lf ms\n"
.LC7:
.string "cpu:%lf gpu:%lf\n"
.LC8:
.string "result correct\n"
.LC9:
.string "resul wrong\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl Max(%rip), %r15d
movl %r15d, %eax
imull %r15d, %eax
cltq
salq $3, %rax
movq %rax, -128(%rbp)
movq %rax, %rdi
call malloc@PLT
movq %rax, -104(%rbp)
movslq %r15d, %r13
leaq 0(,%r13,8), %rax
movq %rax, -120(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
movq -120(%rbp), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %r12, %rdi
call malloc@PLT
movq %rax, -112(%rbp)
testl %r15d, %r15d
jle .L15
movq -104(%rbp), %rdx
movl $0, %ecx
movsd .LC1(%rip), %xmm4
movsd .LC2(%rip), %xmm3
.L16:
movl $0, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %ecx, %xmm2
.L17:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm4, %xmm1
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
addsd %xmm3, %xmm0
movsd %xmm0, (%rdx,%rax,8)
movq %rax, %r12
addq $1, %rax
cmpq %rax, %r13
jne .L17
addl $1, %ecx
movq -120(%rbp), %rax
addq %rax, %rdx
cmpl %ecx, %r15d
jne .L16
movl $0, %r13d
movl $0x000000000, %r15d
jmp .L18
.L35:
movq %rax, %r13
.L18:
leal -1(%r13), %eax
imull %r13d, %eax
addl $2, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq %r15, %xmm5
ucomisd %xmm0, %xmm5
ja .L42
sqrtsd %xmm0, %xmm0
.L21:
call log@PLT
movsd %xmm0, (%rbx,%r13,8)
movq $0x000000000, (%r14,%r13,8)
leaq 1(%r13), %rax
cmpq %r12, %r13
jne .L35
.L15:
leaq -96(%rbp), %rdi
movq -128(%rbp), %rsi
call cudaMalloc@PLT
movslq Max(%rip), %rsi
salq $3, %rsi
leaq -88(%rbp), %rdi
call cudaMalloc@PLT
call clock@PLT
movq %rax, -120(%rbp)
movl Max(%rip), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $3, %rdx
movl $1, %ecx
movq -104(%rbp), %rsi
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movslq Max(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq %r14, %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl width(%rip), %r13d
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl Max(%rip), %eax
movl $0, %edx
divl %r13d
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r12d
leaq _ZL5con_b(%rip), %r15
.L23:
movl Max(%rip), %ecx
movslq %ecx, %rdx
salq $3, %rdx
shrq %rdx
imull %r12d, %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
cltq
leaq (%rbx,%rax,8), %rsi
movl $1, %r8d
movl $0, %ecx
movq %r15, %rdi
call cudaMemcpyToSymbol@PLT
movl %r13d, -80(%rbp)
movl -72(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -80(%rbp), %rdx
movq -68(%rbp), %rdi
movl -60(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L22:
addl $1, %r12d
cmpl $2, %r12d
jne .L23
movslq Max(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq -88(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq -120(%rbp), %rdi
subq %rdi, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm6, %xmm6
cvtsi2sdq %rdx, %xmm6
movq %xmm6, %r13
call clock@PLT
movq %rax, %r12
movl Max(%rip), %r9d
testl %r9d, %r9d
jle .L24
movq -112(%rbp), %rax
movq %rax, %rsi
movslq %r9d, %rcx
salq $3, %rcx
leaq (%rax,%rcx), %r10
movl $0, %edi
.L25:
movq %rsi, %r8
movsd (%rsi), %xmm1
movslq %edi, %rax
movq -104(%rbp), %rdx
leaq (%rdx,%rax,8), %rdx
movl $0, %eax
.L26:
movsd (%rdx,%rax), %xmm0
mulsd (%rbx,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L26
movsd %xmm1, (%r8)
addq $8, %rsi
addl %r9d, %edi
cmpq %r10, %rsi
jne .L25
.L24:
call clock@PLT
subq %r12, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm7, %xmm7
cvtsi2sdq %rdx, %xmm7
movq %xmm7, %rbx
movq %r13, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, Max(%rip)
jle .L27
movl $0, %ebx
movl $1, %eax
leaq .LC7(%rip), %r12
movl $0, %r13d
jmp .L30
.L42:
call sqrt@PLT
jmp .L21
.L44:
movl %r12d, %ecx
movl Max(%rip), %edx
movq -88(%rbp), %rsi
movq -96(%rbp), %rdi
call _Z28__device_stub__Z5multiPdS_iiPdS_ii
jmp .L22
.L28:
addq $1, %rbx
cmpl %ebx, Max(%rip)
jle .L45
.L30:
movq -112(%rbp), %rdi
movsd (%rdi,%rbx,8), %xmm2
movsd (%r14,%rbx,8), %xmm1
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
andpd .LC6(%rip), %xmm0
comisd err(%rip), %xmm0
jbe .L28
movapd %xmm2, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl %r13d, %eax
jmp .L28
.L45:
testb %al, %al
jne .L27
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L27:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L32:
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call free@PLT
movq -112(%rbp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5multiPdS_ii"
.LC11:
.string "con_b"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5multiPdS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $65536, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5con_b(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5con_b
.comm _ZL5con_b,65536,32
.globl err
.data
.align 8
.type err, @object
.size err, 8
err:
.long -1717986918
.long 1069128089
.globl width
.align 4
.type width, @object
.size width, 4
width:
.long 32
.globl Max
.align 4
.type Max, @object
.size Max, 4
Max:
.long 16384
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.align 8
.LC2:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex7_3.hip"
.globl _Z20__device_stub__multiPdS_ii # -- Begin function _Z20__device_stub__multiPdS_ii
.p2align 4, 0x90
.type _Z20__device_stub__multiPdS_ii,@function
_Z20__device_stub__multiPdS_ii: # @_Z20__device_stub__multiPdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5multiPdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__multiPdS_ii, .Lfunc_end0-_Z20__device_stub__multiPdS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xbfb999999999999a # double -0.10000000000000001
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.LCPI1_3:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $.Lstr, %edi
callq puts@PLT
movslq Max(%rip), %r12
movl %r12d, %r14d
movl %r12d, %edi
imull %edi, %edi
shlq $3, %rdi
callq malloc
movq %rax, %r13
movq %rsp, %rbx
leaq 15(,%r14,8), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
leaq (,%r12,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, -48(%rbp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, -96(%rbp) # 8-byte Spill
testq %r12, %r12
jle .LBB1_5
# %bb.1: # %.preheader77.lr.ph
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %edx
leaq (,%rdx,8), %rdx
addq %r13, %rdx
xorps %xmm2, %xmm2
cvtsi2sd %ecx, %xmm2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
mulsd %xmm0, %xmm3
addsd %xmm2, %xmm3
addsd %xmm1, %xmm3
movsd %xmm3, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %r14d, %eax
cmpq %r14, %rcx
jne .LBB1_2
.LBB1_5: # %.preheader76
movl Max(%rip), %esi
testl %esi, %esi
movq -48(%rbp), %r15 # 8-byte Reload
jle .LBB1_11
# %bb.6: # %.lr.ph81.preheader
xorl %r14d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # %call.sqrt
# in Loop: Header=BB1_7 Depth=1
callq sqrt
.LBB1_10: # %.lr.ph81.split
# in Loop: Header=BB1_7 Depth=1
callq log
movsd %xmm0, (%rbx,%r14,8)
movq $0, (%r15,%r14,8)
incq %r14
movslq Max(%rip), %rsi
cmpq %rsi, %r14
jge .LBB1_11
.LBB1_7: # %.lr.ph81
# =>This Inner Loop Header: Depth=1
leal -1(%r14), %eax
imull %r14d, %eax
addl $2, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd .LCPI1_3(%rip), %xmm0
jb .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB1_10
.LBB1_11: # %._crit_edge82
imull %esi, %esi
shlq $3, %rsi
leaq -72(%rbp), %rdi
callq hipMalloc
movslq Max(%rip), %rsi
shlq $3, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
callq clock
movq %rax, -64(%rbp) # 8-byte Spill
movq -72(%rbp), %rdi
movl Max(%rip), %edx
imull %edx, %edx
shlq $3, %rdx
movq %r13, -104(%rbp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movslq Max(%rip), %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl width(%rip), %r12d
movabsq $4294967296, %rcx # imm = 0x100000000
movl Max(%rip), %eax
xorl %edx, %edx
divl %r12d
movl %eax, %r13d
orq %rcx, %r12
xorl %r14d, %r14d
orq %rcx, %r13
movabsq $9223372036854775804, %r15 # imm = 0x7FFFFFFFFFFFFFFC
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=1
incl %r14d
cmpl $1, %r14d
jne .LBB1_15
.LBB1_12: # =>This Inner Loop Header: Depth=1
movslq Max(%rip), %rdx
movl %edx, %eax
imull %r14d, %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movslq %ecx, %rax
leaq (%rbx,%rax,8), %rsi
shlq $2, %rdx
andq %r15, %rdx
movl $con_b, %edi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=1
movq -72(%rbp), %rax
movq -56(%rbp), %rcx
movl Max(%rip), %edx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movl %edx, -80(%rbp)
movl %r14d, -76(%rbp)
leaq -168(%rbp), %rax
movq %rax, -208(%rbp)
leaq -160(%rbp), %rax
movq %rax, -200(%rbp)
leaq -80(%rbp), %rax
movq %rax, -192(%rbp)
leaq -76(%rbp), %rax
movq %rax, -184(%rbp)
leaq -152(%rbp), %rdi
leaq -136(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -112(%rbp), %rcx
callq __hipPopCallConfiguration
movq -152(%rbp), %rsi
movl -144(%rbp), %edx
movq -136(%rbp), %rcx
movl -128(%rbp), %r8d
movl $_Z5multiPdS_ii, %edi
leaq -208(%rbp), %r9
pushq -112(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB1_14
.LBB1_15:
movq -56(%rbp), %rsi
movslq Max(%rip), %rdx
shlq $3, %rdx
movq -48(%rbp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
subq -64(%rbp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %r14 # imm = 0x20C49BA5E353F7CF
imulq %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -64(%rbp) # 8-byte Spill
callq clock
movq %rax, %r12
movl Max(%rip), %eax
testl %eax, %eax
movq -104(%rbp), %r15 # 8-byte Reload
movq -96(%rbp), %r13 # 8-byte Reload
jle .LBB1_20
# %bb.16: # %.preheader.lr.ph
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movl %ecx, %esi
leaq (%r15,%rsi,8), %rsi
movsd (%r13,%rdx,8), %xmm0 # xmm0 = mem[0],zero
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rdi,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rbx,%rdi,8), %xmm1
addsd %xmm1, %xmm0
incq %rdi
cmpq %rdi, %rax
jne .LBB1_18
# %bb.19: # %._crit_edge86
# in Loop: Header=BB1_17 Depth=1
movsd %xmm0, (%r13,%rdx,8)
incq %rdx
addl %eax, %ecx
cmpq %rax, %rdx
jne .LBB1_17
.LBB1_20: # %._crit_edge89
callq clock
subq %r12, %rax
imulq %r14
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -88(%rbp) # 8-byte Spill
movb $1, %bl
movl $.L.str.1, %edi
movsd -64(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd -88(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
cmpl $0, Max(%rip)
jle .LBB1_21
# %bb.22: # %.lr.ph93.preheader
xorl %r14d, %r14d
movapd .LCPI1_2(%rip), %xmm3 # xmm3 = [NaN,NaN]
movq -48(%rbp), %r12 # 8-byte Reload
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_23 Depth=1
incq %r14
movslq Max(%rip), %rax
cmpq %rax, %r14
jge .LBB1_26
.LBB1_23: # %.lr.ph93
# =>This Inner Loop Header: Depth=1
movsd (%r13,%r14,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r12,%r14,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
andpd %xmm3, %xmm2
ucomisd err(%rip), %xmm2
jbe .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=1
movl $.L.str.3, %edi
movb $2, %al
callq printf
movapd .LCPI1_2(%rip), %xmm3 # xmm3 = [NaN,NaN]
xorl %ebx, %ebx
jmp .LBB1_25
.LBB1_26: # %._crit_edge94.loopexit
testb $1, %bl
movl $.Lstr.1, %eax
movl $.Lstr.2, %edi
cmoveq %rax, %rdi
jmp .LBB1_27
.LBB1_21:
movl $.Lstr.2, %edi
movq -48(%rbp), %r12 # 8-byte Reload
.LBB1_27: # %.critedge
callq puts@PLT
movq -72(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r13, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5multiPdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $con_b, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $65536, %r9d # imm = 0x10000
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type Max,@object # @Max
.data
.globl Max
.p2align 2, 0x0
Max:
.long 16384 # 0x4000
.size Max, 4
.type width,@object # @width
.globl width
.p2align 2, 0x0
width:
.long 32 # 0x20
.size width, 4
.type err,@object # @err
.globl err
.p2align 3, 0x0
err:
.quad 0x3fb999999999999a # double 0.10000000000000001
.size err, 8
.type con_b,@object # @con_b
.local con_b
.comm con_b,65536,16
.type _Z5multiPdS_ii,@object # @_Z5multiPdS_ii
.section .rodata,"a",@progbits
.globl _Z5multiPdS_ii
.p2align 3, 0x0
_Z5multiPdS_ii:
.quad _Z20__device_stub__multiPdS_ii
.size _Z5multiPdS_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "GPU TIME:%lf ms\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU TIME:%lf ms\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cpu:%lf gpu:%lf\n"
.size .L.str.3, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5multiPdS_ii"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "con_b"
.size .L__unnamed_2, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\344\275\277\347\224\250constant memory\345\255\230\346\224\276\345\220\221\351\207\217:"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "resul wrong"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "result correct"
.size .Lstr.2, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__multiPdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym con_b
.addrsig_sym _Z5multiPdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} | .file "tmpxft_0007947e_00000000-6_5_basic_elements.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} | #include "hip/hip_runtime.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
//__global__ void hello_kernel()
//{
// printf("Hello cuda world \n");
//}
//int main()
//{
// printf("hello from main \n");
//
// dim3 block();
//
// hello_kernel <<< 1, 1 >>> ();
//
// cudaDeviceSynchronize();
// cudaDeviceReset();
// return 0;
//} | .text
.file "5_basic_elements.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007947e_00000000-6_5_basic_elements.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "5_basic_elements.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} | code for sm_80
Function : _Z35calcConvolutionBackwardResetGradGPUPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x16c] ; /* 0x00005b0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01a0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fd60003f45270 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R0, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005007a24 */
/* 0x000fc800078e0200 */
/*0220*/ IMAD R0, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003007a24 */
/* 0x000fe400078e0200 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0240*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*0250*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0260*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} | .file "tmpxft_0013024d_00000000-6_calcConvolutionBackwardResetGradGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
.type _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii, @function
_Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z35calcConvolutionBackwardResetGradGPUPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii, .-_Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii, @function
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, .-_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z35calcConvolutionBackwardResetGradGPUPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z35calcConvolutionBackwardResetGradGPUPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z35calcConvolutionBackwardResetGradGPUPfiiii
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.p2align 8
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii,@function
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s4
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0xc
v_ashrrev_i32_e32 v3, 31, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s2, s3
v_xor_b32_e32 v3, s3, v3
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_mul_lo_u32 v1, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_add_lshl_u32 v0, v1, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35calcConvolutionBackwardResetGradGPUPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, .Lfunc_end0-_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z35calcConvolutionBackwardResetGradGPUPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z35calcConvolutionBackwardResetGradGPUPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionBackwardResetGradGPU( float *filter_grads, int in_size_z, int kernel_size, int filter_size, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if ( id < elements ) {
int i = id % kernel_size;
id /= kernel_size;
int j = id % kernel_size;
id /= kernel_size;
int z = id % in_size_z;
id /= in_size_z;
int filter = id;
int filter_grad_index = (filter * (in_size_z * kernel_size * kernel_size) + z * (kernel_size * kernel_size) + j * kernel_size + i) * 2;
filter_grads[ filter_grad_index ] = 0;
}
/* original code
int k_end = filter_grads.size();
int kernel_size_2 = kernel_size * kernel_size;
int i_end = kernel_size_2 * in.size.z;
for ( int k = 0; k < k_end; ++k ){
for ( int i = 0; i < i_end ; ++i ){
filter_grads[k].data[i].grad = 0;
}
}
*/
} | .text
.file "calcConvolutionBackwardResetGradGPU.hip"
.globl _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii # -- Begin function _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.p2align 4, 0x90
.type _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii,@function
_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii: # @_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z35calcConvolutionBackwardResetGradGPUPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii, .Lfunc_end0-_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35calcConvolutionBackwardResetGradGPUPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii,@object # @_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .rodata,"a",@progbits
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.p2align 3, 0x0
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
.quad _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z35calcConvolutionBackwardResetGradGPUPfiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z35calcConvolutionBackwardResetGradGPUPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z35calcConvolutionBackwardResetGradGPUPfiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x16c] ; /* 0x00005b0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01a0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*01c0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fd60003f45270 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01f0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff03aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0210*/ IMAD R0, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005007a24 */
/* 0x000fc800078e0200 */
/*0220*/ IMAD R0, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003007a24 */
/* 0x000fe400078e0200 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0240*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*0250*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0260*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z35calcConvolutionBackwardResetGradGPUPfiiii
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.p2align 8
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii,@function
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s4
v_add_nc_u32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0xc
v_ashrrev_i32_e32 v3, 31, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v3
v_xor_b32_e32 v4, v4, v3
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s4, s2, s3
v_xor_b32_e32 v3, s3, v3
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_cndmask_b32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_mul_lo_u32 v1, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_add_lshl_u32 v0, v1, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35calcConvolutionBackwardResetGradGPUPfiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, .Lfunc_end0-_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z35calcConvolutionBackwardResetGradGPUPfiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z35calcConvolutionBackwardResetGradGPUPfiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013024d_00000000-6_calcConvolutionBackwardResetGradGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
.type _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii, @function
_Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z35calcConvolutionBackwardResetGradGPUPfiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii, .-_Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii, @function
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z35calcConvolutionBackwardResetGradGPUPfiiiiPfiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, .-_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z35calcConvolutionBackwardResetGradGPUPfiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z35calcConvolutionBackwardResetGradGPUPfiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcConvolutionBackwardResetGradGPU.hip"
.globl _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii # -- Begin function _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.p2align 4, 0x90
.type _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii,@function
_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii: # @_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z35calcConvolutionBackwardResetGradGPUPfiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii, .Lfunc_end0-_Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35calcConvolutionBackwardResetGradGPUPfiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z35calcConvolutionBackwardResetGradGPUPfiiii,@object # @_Z35calcConvolutionBackwardResetGradGPUPfiiii
.section .rodata,"a",@progbits
.globl _Z35calcConvolutionBackwardResetGradGPUPfiiii
.p2align 3, 0x0
_Z35calcConvolutionBackwardResetGradGPUPfiiii:
.quad _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.size _Z35calcConvolutionBackwardResetGradGPUPfiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z35calcConvolutionBackwardResetGradGPUPfiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z50__device_stub__calcConvolutionBackwardResetGradGPUPfiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z35calcConvolutionBackwardResetGradGPUPfiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
cudaMalloc((void **)&devA,sizeof(int)*6);
cudaMemcpy(devA,a,sizeof(int)*6,cudaMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
cudaMemcpy(c,devA,sizeof(int)*6,cudaMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
cudaFree(devA);
return 0;
} | code for sm_80
Function : _Z3oddPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0060*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*00b0*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4evenPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0060*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0090*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*00a0*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x000fe8000c101904 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
cudaMalloc((void **)&devA,sizeof(int)*6);
cudaMemcpy(devA,a,sizeof(int)*6,cudaMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
cudaMemcpy(c,devA,sizeof(int)*6,cudaMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
cudaFree(devA);
return 0;
} | .file "tmpxft_0010c52f_00000000-6_Odd_Even.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4evenPiPi
.type _Z23__device_stub__Z4evenPiPi, @function
_Z23__device_stub__Z4evenPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4evenPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4evenPiPi, .-_Z23__device_stub__Z4evenPiPi
.globl _Z4evenPi
.type _Z4evenPi, @function
_Z4evenPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4evenPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4evenPi, .-_Z4evenPi
.globl _Z22__device_stub__Z3oddPiPi
.type _Z22__device_stub__Z3oddPiPi, @function
_Z22__device_stub__Z3oddPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3oddPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z22__device_stub__Z3oddPiPi, .-_Z22__device_stub__Z3oddPiPi
.globl _Z3oddPi
.type _Z3oddPi, @function
_Z3oddPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3oddPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3oddPi, .-_Z3oddPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello"
.LC1:
.string "After sort--------\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $6, 32(%rsp)
movl $7, 36(%rsp)
movl $5, 40(%rsp)
movl $2, 44(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L24
.L20:
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L22:
addl $1, %ebx
cmpl $6, %ebx
je .L31
.L24:
testb $1, %bl
jne .L20
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq (%rsp), %rdi
call _Z23__device_stub__Z4evenPiPi
jmp .L22
.L30:
movq (%rsp), %rdi
call _Z22__device_stub__Z3oddPiPi
jmp .L22
.L31:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $24, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 88(%rsp), %r12
leaq .LC2(%rip), %rbp
.L25:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L25
movq (%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3oddPi"
.LC4:
.string "_Z4evenPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3oddPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4evenPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
cudaMalloc((void **)&devA,sizeof(int)*6);
cudaMemcpy(devA,a,sizeof(int)*6,cudaMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
cudaMemcpy(c,devA,sizeof(int)*6,cudaMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
cudaFree(devA);
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
hipMalloc((void **)&devA,sizeof(int)*6);
hipMemcpy(devA,a,sizeof(int)*6,hipMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
hipMemcpy(c,devA,sizeof(int)*6,hipMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
hipFree(devA);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
hipMalloc((void **)&devA,sizeof(int)*6);
hipMemcpy(devA,a,sizeof(int)*6,hipMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
hipMemcpy(c,devA,sizeof(int)*6,hipMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
hipFree(devA);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4evenPi
.globl _Z4evenPi
.p2align 8
.type _Z4evenPi,@function
_Z4evenPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v2, 4, v3
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v0, v3, s[0:1]
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
v_add_co_u32 v3, s3, s0, v3
v_add_co_u32 v5, s0, s0, v2
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
v_add_co_ci_u32_e64 v6, null, s1, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4evenPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4evenPi, .Lfunc_end0-_Z4evenPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3oddPi
.globl _Z3oddPi
.p2align 8
.type _Z3oddPi,@function
_Z3oddPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, 4, v2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v0, v3, s[0:1]
global_load_b32 v1, v2, s[0:1] offset:8
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
s_cbranch_execz .LBB1_2
v_add_co_u32 v3, s2, s0, v3
v_add_co_u32 v5, s0, s0, v2
v_add_co_ci_u32_e64 v4, null, s1, 0, s2
v_add_co_ci_u32_e64 v6, null, s1, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off offset:8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3oddPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3oddPi, .Lfunc_end1-_Z3oddPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4evenPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4evenPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3oddPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z3oddPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
/*__global__ void device_func(int *a)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
a[tid]+=1;
//int tmp;
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even(a)
/*tmp=a[threadIdx.x*2];
a[threadIdx.x]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;
}
else{
odd(a)
/*tmp=a[threadIdx.x*2+1];
a[threadIdx.x+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
}}*/
__global__ void even(int *a)
{
if(a[threadIdx.x*2]>a[threadIdx.x*2+1]){
int
tmp=a[threadIdx.x*2];
a[threadIdx.x*2]=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=tmp;}
__syncthreads();
}
__global__ void odd(int *a)
{
if(a[threadIdx.x*2+1]>a[threadIdx.x*2+2])
{int tmp;
tmp=a[threadIdx.x*2+1];
a[threadIdx.x*2+1]=a[threadIdx.x*2+2];
a[threadIdx.x*2+2]=tmp;
__syncthreads();
}}
int main()
{
int a[]={6,7,5,2,3,1};
int *devA;
int c[6];
printf("hello");
//c=(int *)malloc(sizeof(int)*6);
hipMalloc((void **)&devA,sizeof(int)*6);
hipMemcpy(devA,a,sizeof(int)*6,hipMemcpyHostToDevice);
for(int i=0;i<6;i++)
{
if(i%2==0)
{
even<<<1,3>>>(devA);
}
else{
odd<<<1,3>>>(devA);
}
}
//device_func<<<1,3>>>(devA);
hipMemcpy(c,devA,sizeof(int)*6,hipMemcpyDeviceToHost);
printf("After sort--------\n");
for(int j=0;j<6;j++)
{
printf("%d ",c[j]);
}
hipFree(devA);
return 0;
} | .text
.file "Odd_Even.hip"
.globl _Z19__device_stub__evenPi # -- Begin function _Z19__device_stub__evenPi
.p2align 4, 0x90
.type _Z19__device_stub__evenPi,@function
_Z19__device_stub__evenPi: # @_Z19__device_stub__evenPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4evenPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__evenPi, .Lfunc_end0-_Z19__device_stub__evenPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__oddPi # -- Begin function _Z18__device_stub__oddPi
.p2align 4, 0x90
.type _Z18__device_stub__oddPi,@function
_Z18__device_stub__oddPi: # @_Z18__device_stub__oddPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3oddPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__oddPi, .Lfunc_end1-_Z18__device_stub__oddPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 6 # 0x6
.long 7 # 0x7
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [6,7,5,2]
movaps %xmm0, 96(%rsp)
movabsq $4294967299, %rax # imm = 0x100000003
movq %rax, 112(%rsp)
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
leaq 2(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
incl %r12d
cmpl $6, %r12d
je .LBB2_8
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r12b
jne .LBB2_4
# %bb.2: # in Loop: Header=BB2_1 Depth=1
testl %eax, %eax
jne .LBB2_7
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z4evenPi, %edi
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
testl %eax, %eax
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z3oddPi, %edi
jmp .LBB2_6
.LBB2_8:
movq (%rsp), %rsi
leaq 64(%rsp), %rdi
movl $24, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB2_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4evenPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3oddPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4evenPi,@object # @_Z4evenPi
.section .rodata,"a",@progbits
.globl _Z4evenPi
.p2align 3, 0x0
_Z4evenPi:
.quad _Z19__device_stub__evenPi
.size _Z4evenPi, 8
.type _Z3oddPi,@object # @_Z3oddPi
.globl _Z3oddPi
.p2align 3, 0x0
_Z3oddPi:
.quad _Z18__device_stub__oddPi
.size _Z3oddPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello"
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4evenPi"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3oddPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "After sort--------"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__evenPi
.addrsig_sym _Z18__device_stub__oddPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4evenPi
.addrsig_sym _Z3oddPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3oddPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0060*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*00b0*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4evenPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R2, 0x1, RZ ; /* 0x0000000102027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0060*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*0090*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*00a0*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x000fe8000c101904 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4evenPi
.globl _Z4evenPi
.p2align 8
.type _Z4evenPi,@function
_Z4evenPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v2, 4, v3
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v0, v3, s[0:1]
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
v_add_co_u32 v3, s3, s0, v3
v_add_co_u32 v5, s0, s0, v2
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
v_add_co_ci_u32_e64 v6, null, s1, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4evenPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4evenPi, .Lfunc_end0-_Z4evenPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3oddPi
.globl _Z3oddPi
.p2align 8
.type _Z3oddPi,@function
_Z3oddPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, 4, v2
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v0, v3, s[0:1]
global_load_b32 v1, v2, s[0:1] offset:8
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v0, v1
s_cbranch_execz .LBB1_2
v_add_co_u32 v3, s2, s0, v3
v_add_co_u32 v5, s0, s0, v2
v_add_co_ci_u32_e64 v4, null, s1, 0, s2
v_add_co_ci_u32_e64 v6, null, s1, 0, s0
s_clause 0x1
global_store_b32 v[3:4], v1, off
global_store_b32 v[5:6], v0, off offset:8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3oddPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3oddPi, .Lfunc_end1-_Z3oddPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4evenPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z4evenPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3oddPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z3oddPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010c52f_00000000-6_Odd_Even.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4evenPiPi
.type _Z23__device_stub__Z4evenPiPi, @function
_Z23__device_stub__Z4evenPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4evenPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4evenPiPi, .-_Z23__device_stub__Z4evenPiPi
.globl _Z4evenPi
.type _Z4evenPi, @function
_Z4evenPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4evenPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4evenPi, .-_Z4evenPi
.globl _Z22__device_stub__Z3oddPiPi
.type _Z22__device_stub__Z3oddPiPi, @function
_Z22__device_stub__Z3oddPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3oddPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z22__device_stub__Z3oddPiPi, .-_Z22__device_stub__Z3oddPiPi
.globl _Z3oddPi
.type _Z3oddPi, @function
_Z3oddPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3oddPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3oddPi, .-_Z3oddPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hello"
.LC1:
.string "After sort--------\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $6, 32(%rsp)
movl $7, 36(%rsp)
movl $5, 40(%rsp)
movl $2, 44(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L24
.L20:
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L22:
addl $1, %ebx
cmpl $6, %ebx
je .L31
.L24:
testb $1, %bl
jne .L20
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq (%rsp), %rdi
call _Z23__device_stub__Z4evenPiPi
jmp .L22
.L30:
movq (%rsp), %rdi
call _Z22__device_stub__Z3oddPiPi
jmp .L22
.L31:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $24, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 88(%rsp), %r12
leaq .LC2(%rip), %rbp
.L25:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L25
movq (%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3oddPi"
.LC4:
.string "_Z4evenPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3oddPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4evenPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Odd_Even.hip"
.globl _Z19__device_stub__evenPi # -- Begin function _Z19__device_stub__evenPi
.p2align 4, 0x90
.type _Z19__device_stub__evenPi,@function
_Z19__device_stub__evenPi: # @_Z19__device_stub__evenPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4evenPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__evenPi, .Lfunc_end0-_Z19__device_stub__evenPi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__oddPi # -- Begin function _Z18__device_stub__oddPi
.p2align 4, 0x90
.type _Z18__device_stub__oddPi,@function
_Z18__device_stub__oddPi: # @_Z18__device_stub__oddPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3oddPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__oddPi, .Lfunc_end1-_Z18__device_stub__oddPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 6 # 0x6
.long 7 # 0x7
.long 5 # 0x5
.long 2 # 0x2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [6,7,5,2]
movaps %xmm0, 96(%rsp)
movabsq $4294967299, %rax # imm = 0x100000003
movq %rax, 112(%rsp)
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
leaq 2(%rbx), %r14
leaq 56(%rsp), %r13
leaq 48(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
incl %r12d
cmpl $6, %r12d
je .LBB2_8
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r12b
jne .LBB2_4
# %bb.2: # in Loop: Header=BB2_1 Depth=1
testl %eax, %eax
jne .LBB2_7
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z4evenPi, %edi
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
testl %eax, %eax
jne .LBB2_7
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 32(%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movl $_Z3oddPi, %edi
jmp .LBB2_6
.LBB2_8:
movq (%rsp), %rsi
leaq 64(%rsp), %rdi
movl $24, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB2_9
# %bb.10:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4evenPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3oddPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4evenPi,@object # @_Z4evenPi
.section .rodata,"a",@progbits
.globl _Z4evenPi
.p2align 3, 0x0
_Z4evenPi:
.quad _Z19__device_stub__evenPi
.size _Z4evenPi, 8
.type _Z3oddPi,@object # @_Z3oddPi
.globl _Z3oddPi
.p2align 3, 0x0
_Z3oddPi:
.quad _Z18__device_stub__oddPi
.size _Z3oddPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hello"
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4evenPi"
.size .L__unnamed_1, 10
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3oddPi"
.size .L__unnamed_2, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "After sort--------"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__evenPi
.addrsig_sym _Z18__device_stub__oddPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4evenPi
.addrsig_sym _Z3oddPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define DEV 0
#define DGS_Check_Call( Statement , MsgString ) \
\
{ \
printf ( "Checking CUDA Call... \n") ; \
const cudaError_t error = Statement; \
if (error != cudaSuccess) \
{ \
printf( "Error checking CUDA Call... \n") ; \
printf( "Error: %s:%d, ", __FILE__, __LINE__) ; \
printf( "code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
printf( "Call Checked with error, stopping...\n"); \
exit(1); \
} \
printf ( "Call Checked OK, region... \n"); \
}
// Kernel declaration
__global__ void sumMatrixRowsKernel(int N, double * M_d, double * sum_d);
__host__ void sumMatrixRows(int M, int N, double * M_h, double * sum_h);
// Auxiliary functions declarations
void random_vector(double *a, size_t n);
void array_zeros(double *r, size_t n);
int main(int argc, char * argv[]) {
if (argc < 2) {
printf("El programa recibe M la dimensión de la matriz cuadrada aleatoria a sumar por filas");
}
// Recieve matrix dimension as input and convert it to int
int M = atoi(argv[1]);
// Declare M_h the matrix to sum, and sum_h the array of sums.
double * M_h = (double *) aligned_alloc(64, M*M*sizeof(double));
double * sum_h = (double *) aligned_alloc(64, M*sizeof(double));
// Assign random values to M_h and zeros to sum_h
random_vector(M_h, M*M);
array_zeros(sum_h, M);
printf("sum_h before: ");
for (int i = 0; i < M; ++i) {
printf("%f",sum_h[i]);
}
printf("\n");
// Invoke the function to sum the rows of M_h matrix
sumMatrixRows(M, M, M_h, sum_h);
printf("sum_h after: ");
for (int i = 0; i < M; ++i) {
printf("%f ",sum_h[i]);
}
printf("\n");
}
void sumMatrixRows(int M, int N, double * M_h, double * sum_h) {
// Set up device
// cudaSetDevice(DEV);
DGS_Check_Call(cudaSetDevice(DEV), "cudaSetDevice"); // dev - device identifier
// Declare the size of the matrix and the size of the sum array
int size_matrix = M * N * sizeof(double), size_sum = M * sizeof(double);
// Declare the Matrix and the sum array of the device
double * M_d, * sum_d;
// Allocate memory on device
cudaMalloc((void**)&M_d, size_matrix); // allocate Matrix space on device global memory
cudaMalloc((void**)&sum_d, size_sum); // allocate sum array space on device global memory
// Initialize matrices on device
cudaMemcpy(M_d, M_h, size_matrix, cudaMemcpyHostToDevice); // Copy matrix from host to device.
cudaMemset(sum_d, 0, size_sum); // Initialize sum_d as an array of 0 and size: size_sum in device (dont need to copy just initialize it on device because it is a simpe array of zeros)
// Set the execution
dim3 gridSize(1, 1); // Grid dimension (Just 1 block in both dims for now)
dim3 blockSize(M, 1, 1); // Block dimension (Just M threads -as many as rows- in x dim for now)
// Invoke kernel
sumMatrixRowsKernel <<< gridSize, blockSize >>> (N, M_d, sum_d);
// Bring result to host
cudaMemcpy(sum_h, sum_d, size_sum, cudaMemcpyDeviceToHost); // Copy the sum_d array from device global memory to host DRAM.
// Free memory on device
cudaFree(M_d); // Free matrix space in memory on device
cudaFree(sum_d); // Free sum array space in memory on device
}
// Kernel definition
__global__ void sumMatrixRowsKernel(int N, double * M_d, double * sum_d) {
double partial_sum = 0;
int aux = threadIdx.x * N; // There are as many threads as rows in M_d matrix. aux represents the pointer pointing to the first column of this row. Each thread will represent each row.
// Sum all elements of this row (N is the number of columns)
for (int k = 0; k < N; ++k) {
partial_sum += M_d[aux+k];
}
// Assign the partial_sum to the sum_d array of sums
sum_d[threadIdx.x] = partial_sum;
}
void random_vector(double *a, size_t n) {
for (unsigned int i = 0; i < n; i++) {
a[i] = (double)rand() / (double)RAND_MAX;
}
}
void array_zeros(double *r, size_t n) {
for (unsigned int i = 0; i < n; i++) {
r[i] = 0;
}
} | code for sm_80
Function : _Z19sumMatrixRowsKerneliPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fc6000001ff00 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x790 ; /* 0x0000072000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0080*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0090*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*00a0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*00c0*/ IMAD R3, R0, c[0x0][0x160], RZ ; /* 0x0000580000037a24 */
/* 0x001fd800078e02ff */
/*00d0*/ @!P0 BRA 0x690 ; /* 0x000005b000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R26, -R2, c[0x0][0x160], RZ ; /* 0x00005800021a7a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0120*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f04270 */
/*0130*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fd800078e0204 */
/*0140*/ @!P0 BRA 0x590 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x3f0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ LDG.E.64 R12, [R4.64] ; /* 0x00000006040c7981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000806040e7981 */
/* 0x000ee8000c1e1b00 */
/*01b0*/ LDG.E.64 R16, [R4.64+0x10] ; /* 0x0000100604107981 */
/* 0x000f28000c1e1b00 */
/*01c0*/ LDG.E.64 R18, [R4.64+0x18] ; /* 0x0000180604127981 */
/* 0x000f68000c1e1b00 */
/*01d0*/ LDG.E.64 R20, [R4.64+0x20] ; /* 0x0000200604147981 */
/* 0x000f68000c1e1b00 */
/*01e0*/ LDG.E.64 R24, [R4.64+0x28] ; /* 0x0000280604187981 */
/* 0x001f68000c1e1b00 */
/*01f0*/ LDG.E.64 R22, [R4.64+0x30] ; /* 0x0000300604167981 */
/* 0x000f68000c1e1b00 */
/*0200*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380604067981 */
/* 0x000f68000c1e1b00 */
/*0210*/ LDG.E.64 R8, [R4.64+0x40] ; /* 0x0000400604087981 */
/* 0x000f62000c1e1b00 */
/*0220*/ DADD R12, R12, R10 ; /* 0x000000000c0c7229 */
/* 0x0060c6000000000a */
/*0230*/ LDG.E.64 R10, [R4.64+0x48] ; /* 0x00004806040a7981 */
/* 0x0010a6000c1e1b00 */
/*0240*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008308000000000e */
/*0250*/ LDG.E.64 R12, [R4.64+0x50] ; /* 0x00005006040c7981 */
/* 0x0020e4000c1e1b00 */
/*0260*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x0103480000000010 */
/*0270*/ LDG.E.64 R14, [R4.64+0x58] ; /* 0x00005806040e7981 */
/* 0x002124000c1e1b00 */
/*0280*/ DADD R18, R16, R18 ; /* 0x0000000010127229 */
/* 0x0203480000000012 */
/*0290*/ LDG.E.64 R16, [R4.64+0x60] ; /* 0x0000600604107981 */
/* 0x002124000c1e1b00 */
/*02a0*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x0203480000000014 */
/*02b0*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680604127981 */
/* 0x002124000c1e1b00 */
/*02c0*/ DADD R24, R20, R24 ; /* 0x0000000014187229 */
/* 0x0203480000000018 */
/*02d0*/ LDG.E.64 R20, [R4.64+0x70] ; /* 0x0000700604147981 */
/* 0x002124000c1e1b00 */
/*02e0*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x0203480000000016 */
/*02f0*/ LDG.E.64 R24, [R4.64+0x78] ; /* 0x0000780604187981 */
/* 0x002122000c1e1b00 */
/*0300*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ DADD R6, R22, R6 ; /* 0x0000000016067229 */
/* 0x020e620000000006 */
/*0320*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0330*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fc60003f24270 */
/*0340*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002ea20000000008 */
/*0350*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fca0007f5e0ff */
/*0360*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0370*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0380*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x008f0c000000000c */
/*0390*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x010e0c000000000e */
/*03a0*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x001e0c0000000010 */
/*03b0*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x001e0c0000000012 */
/*03c0*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x001e0c0000000014 */
/*03d0*/ DADD R10, R6, R24 ; /* 0x00000000060a7229 */
/* 0x0010620000000018 */
/*03e0*/ @P1 BRA 0x190 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*03f0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*0400*/ @!P1 BRA 0x570 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0410*/ LDG.E.64 R22, [R4.64] ; /* 0x0000000604167981 */
/* 0x000ea8000c1e1b00 */
/*0420*/ LDG.E.64 R20, [R4.64+0x8] ; /* 0x0000080604147981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R18, [R4.64+0x10] ; /* 0x0000100604127981 */
/* 0x000f28000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R4.64+0x18] ; /* 0x0000180604107981 */
/* 0x000f68000c1e1b00 */
/*0450*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002006040e7981 */
/* 0x000f68000c1e1b00 */
/*0460*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002806040c7981 */
/* 0x000f68000c1e1b00 */
/*0470*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300604087981 */
/* 0x000f68000c1e1b00 */
/*0480*/ LDG.E.64 R6, [R4.64+0x38] ; /* 0x0000380604067981 */
/* 0x001f62000c1e1b00 */
/*0490*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*04a0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*04b0*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ DADD R22, R10, R22 ; /* 0x000000000a167229 */
/* 0x006ecc0000000016 */
/*04d0*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x008f0c0000000014 */
/*04e0*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x010f4c0000000012 */
/*04f0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x020e0c0000000010 */
/*0500*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x001e0c000000000e */
/*0510*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e0c000000000c */
/*0520*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0010640000000008 */
/*0530*/ IADD3 R12, P1, R4, 0x40, RZ ; /* 0x00000040040c7810 */
/* 0x001fc80007f3e0ff */
/*0540*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x0020620000000006 */
/*0550*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0605 */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0570*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x003fda0000705670 */
/*0580*/ @!P0 BRA 0x690 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x000ea8000c1e1b00 */
/*05a0*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080604087981 */
/* 0x000ee8000c1e1b00 */
/*05b0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001006040c7981 */
/* 0x000f28000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R4.64+0x18] ; /* 0x00001806040e7981 */
/* 0x000162000c1e1b00 */
/*05d0*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*05f0*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0600*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x004ecc000000000a */
/*0610*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x0083240000000008 */
/*0620*/ IADD3 R8, P1, R4, 0x20, RZ ; /* 0x0000002004087810 */
/* 0x002fc80007f3e0ff */
/*0630*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x010f62000000000c */
/*0640*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fe400008e0605 */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0008 */
/*0660*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0670*/ DADD R10, R6, R14 ; /* 0x00000000060a7229 */
/* 0x020064000000000e */
/*0680*/ @P0 BRA 0x590 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*0690*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*06a0*/ @!P0 BRA 0x790 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*06b0*/ IADD3 R4, R3, UR4, RZ ; /* 0x0000000403047c10 */
/* 0x000fe2000fffe0ff */
/*06c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*06d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*06e0*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0004 */
/*06f0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0005 */
/*0700*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0006 */
/*0720*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*0730*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R3, P1, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007f3e0ff */
/*0750*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*0760*/ IMAD.X R6, RZ, RZ, R6, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0606 */
/*0770*/ DADD R10, R4, R10 ; /* 0x00000000040a7229 */
/* 0x006052000000000a */
/*0780*/ @P0 BRA 0x700 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0790*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*07a0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fca00078e0003 */
/*07b0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe2000c101b06 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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